LPV542 Dual Nanopower 1.8 V, 490nA, RRIO CMOS Operational Amplifier

LPV542 Dual Nanopower 1.8 V, 490nA, RRIO CMOS Operational Amplifier
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LPV542
SNOSCX9 – MARCH 2015
LPV542 Dual Nanopower 1.8 V, 490nA, RRIO CMOS Operational Amplifier
1 Features
3 Description
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The LPV542 is an ultra-low-power, dual operational
amplifier that provides 8kHz of bandwidth from 490nA
of quiescent current making it well suited for batterypowered applications such as health and fitness
wearables, building automation, and remote sensing
nodes.
1
Wide Supply Range: 1.6 V to 5.5 V
Low Supply Current: 490 nA (typical/channel)
Good Offset Voltage: 3 mV (maximum/room)
Good TcVos: 1µV/°C (typical)
Gain-Bandwidth: 8 kHz (typical)
Rail-to-Rail Input and Output
Unity-Gain Stable
Low Input Bias Current : 1 pA (maximum/room)
EMI Hardened
Temperature Range: -40°C to 125°C
Thin 3 mm x 3 mm x 0.45 mm X1SON package
2 Applications
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Wearables
Personal Health Monitors
Battery Packs
Mobile Phones and Tablets
Solar-Powered or Energy Harvested Systems
PIR, Smoke, Gas, and Fire Detection Systems
Battery Powered Internet of Things (IoT) Devices
Remote Sensors
Micropower Reference Buffer
Each amplifier has a CMOS input stage with picoamp bias currents which reduces errors commonly
introduced in megaohm feedback resistance
topologies such as photodiode and charge sense
applications. In addition, the input common-mode
range extends to the power supply rails and the
output swings to within 3 mV of the rails, maintaining
the widest dynamic range possible. Likewise, EMI
protection is designed into the LPV542 in order to
reduce system sensitivity to unwanted RF signals
from mobile phones, WiFi, radio transmitters, and tag
readers.
The LPV542 operates on a supply voltage as low as
1.6 V, ensuring continuous superior performance in
low battery situations. The device is available in an 8pad, low-profile, leadless 3 mm x 3 mm x 0.45 mm
X1SON package and a standard 8 pin VSSOP.
Device Information(1)
PART NUMBER
LPV542
PACKAGE
BODY SIZE (NOM)
X1SON (8)
3.00 mm x 3.00 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
Nanopower Oxygen Sensor Amplifier
Supply Current vs. Supply Voltage
100 M
+
V
1 M
+
RL
VOUT
Supply Current per Channel (nA/Ch)
1000
VCM = 0.3V
900
800
700
600
500
400
125°C
85°C
25°C
0°C
-40°C
300
200
100
0
1.5
OXYGEN SENSOR
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LPV542
SNOSCX9 – MARCH 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Ratings............................
Thermal Information ..................................................
Electrical Characteristics 1.8 V .................................
Electrical Characteristics 3.3 V .................................
Electrical Characteristics 5 V ....................................
Typical Characteristics ..............................................
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 14
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application: 60 Hz Twin "T" Notch Filter..... 16
8.3 Do's and Don'ts ...................................................... 17
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
Device Support ....................................................
Documentation Support .......................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
2
DATE
REVISION
NOTES
March 2015
*
Initial release.
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5 Pin Configuration and Functions
8-Pad X1SON
DNX Package
Top View
8-Pin VSSOP
DGK Package
Top View
8
V+
7
OUT B
3
6
-IN B
4
5
+IN B
OUT A
1
-IN A
2
+IN A
V-
A
B
(1)
OUT A
1
-IN A
2
+IN A
3
V-
4
Exposed
Thermal
Die Pad
on
(1)
Underside
8
V+
7
OUT B
6
-IN B
5
+IN B
Connect thermal die pad to V-.
Pin Functions
PIN
I/O
DESCRIPTION
NAME
DGK
DNX
OUT A
1
1
O
Channel A Output
-IN A
2
2
I
Channel A Inverting Input
+IN A
3
3
I
Channel A Non-Inverting Input
V-
4
4
P
Negative (lowest) power supply
+IN B
5
5
I
Channel B Non-Inverting Input
-IN B
6
6
I
Channel B Inverting Input
OUT B
7
7
O
Channel B Output
V+
8
8
P
Positive (highest) power supply
Die Pad
--
DAP
P
Die Attach Pad. Connect to V- (DNX package only)
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
MAX
UNIT
-0.3
6
V
(V-) - 0.3
(V+) + 0.3
V
-10
10
mA
Supply voltage, V+ to V–
Voltage
Signal input pins
(2)
Current (2)
Continuous (4)
Output short current
Junction temperature
-40
150
°C
Storage temperature, Tstg
-65
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be
current-limited to 10 mA or less.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Short-circuit to V-.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Ratings
MAX
UNIT
Supply Voltage ( V+– V− )
MIN
1.6
NOM
5.5
V
Specified Temperature
-40
125
°C
6.4 Thermal Information
THERMAL METRIC (1)
DGK (VSSOP)
DNX (X1SON)
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
46.3
RθJC(top)
Junction-to-case (top) thermal resistance
33.3
RθJB
Junction-to-board thermal resistance
21
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
21.2
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics 1.8 V
TA = 25°C, V+ = 1.8V, V− = 0V, VCM = VO = V+/2, and RL > 1 MΩ , unless otherwise noted.
TYP (1)
MAX
VCM = 0.3 V
±1
±2
VCM = 1.5 V
±1
±3
PARAMETER
TEST CONDITIONS
MIN
UNIT
OFFSET VOLTAGE
Input offset voltage (VOS)
Over temperature
VCM = 0.3 V and 1.5 V
Drift (dVOS/dT)
Power-Supply Rejection Ratio
(PSRR)
1
VS = 1.6 V to 5.5 V, VCM = 0.3 V
mV
±4
83
µV/°C
109
dB
INPUT VOLTAGE RANGE
Common-mode voltage range (VCM)
CMRR ≥ 60 dB
Common-Mode Rejection Ratio
(CMRR)
0 V < VCM < 1.8 V
63
92
0 V < VCM < 0.7 V
87
92
1.3 V < VCM < 1.8 V
63
98
0
1.8
V
dB
INPUT BIAS CURRENT
Input bias current (IB)
TA = 25°C
±0.1
TA = –40°C to 125°C
±1
±100
Input offset current (IOS)
±0.1
pA
±1
INPUT IMPEDANCE
Differential
1013 || 2.5
Common mode
1013 || 2.5
Ω || pF
NOISE
Input voltage noise density, f = 1 kHz (en)
Current noise density, f = 1 kHz (in)
250
nV/√Hz
80
fA√Hz
101
dB
OPEN-LOOP GAIN
Open-loop voltage gain (AOL)
RL = 100 kΩ to V+/2, 0.5 V < VO < 1.3 V
91
OUTPUT
Voltage output swing from positive rail
RL = 100 kΩ to V+/2
3
20
Voltage output swing from negative rail
RL = 100 kΩ to V+/2
2
20
Output current sourcing
Sourcing, VO to V–, VIN(diff) = 100 mV
1
3
Output current sinking
Sinking, VO to V+, VIN(diff) = –100 mV
1
5
mV
mA
FREQUENCY RESPONSE
Gain-bandwidth product (GBWP)
CL = 20 pF
7
Slew rate (SR)
G = +1, Rising edge, 1Vp-p, CL = 20 pF
3.4
G = +1, Falling edge, 1Vp-p, CL = 20 pF
3.7
kHz
V/ms
POWER SUPPLY
Specified voltage range (VS)
Quiescent current per channel (IQ)
1.6
VCM = 0.3 V, IO = 0
5.5
490
Over temperature
Quiescent current per channel (IQ)
1100
VCM = 1.5 V, IO = 0
Over temperature
(1)
680
V
800
1100
nA
1500
Refer to Typical Characteristics.
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6.6 Electrical Characteristics 3.3 V
TA = 25°C, V+ = 3.3V, V− = 0V, VCM = VO = V+/2, and RL > 1 MΩ , unless otherwise noted.
TYP (1)
MAX
VCM = 0.3
±1
±2
VCM = 3 V
±1
±3
PARAMETER
TEST CONDITIONS
MIN
UNIT
OFFSET VOLTAGE
Input offset voltage (VOS)
Over temperature
VCM = 0.3 V and 3 V
Drift (dVOS/dT)
Power-Supply Rejection Ratio
(PSRR)
1
VS = 1.6 V to 5.5 V, VCM = 0.3 V
mV
±4
83
µV/°C
109
dB
INPUT VOLTAGE RANGE
Common-mode voltage range (VCM)
CMRR ≥ 60 dB
Common-Mode Rejection Ratio
(CMRR)
0 V < VCM < 3.3 V
64
98
0 V < VCM < 2.2V
88
98
2.7 V < VCM < 3.3 V
64
105
0
3.3
V
dB
INPUT BIAS CURRENT
Input bias current (IB)
TA = 25°C
±0.1
TA = –40°C to 125°C
±1
±100
Input offset current (IOS)
±0.1
pA
±1
INPUT IMPEDANCE
Differential
1013 || 2.5
Common mode
1013 || 2.5
Ω || pF
NOISE
Input voltage noise density, f = 1 kHz (en)
Current noise density, f = 1 kHz (in)
250
nV/√Hz
60
fA√Hz
101
dB
OPEN-LOOP GAIN
Open-loop voltage gain (AOL)
RL = 100 kΩ to V+/2, 0.5 V < VO < 2.8 V
91
OUTPUT
Voltage output swing from positive Rail
RL = 100 kΩ to V+/2
3
20
Voltage output swing from negative Rail
RL = 100 kΩ to V+/2
2
20
Output current sourcing
Sourcing, VO to V–, VIN(diff) = 100 mV
5
14
Output current sinking
Sinking, VO to V+, VIN(diff) = –100 mV
5
19
mV
mA
FREQUENCY RESPONSE
Gain-bandwidth product (GBWP)
CL = 20 pF
8
Slew rate (SR)
G = +1, Rising edge, 1Vp-p, CL = 20 pF
3.6
G = +1, Falling edge, 1Vp-p, CL = 20 pF
3.7
kHz
V/ms
POWER SUPPLY
Specified voltage range (VS)
Quiescent current per channel (IQ)
1.6
VCM = 0.3 V, IO = 0
5.5
480
Over temperature
Quiescent current per channel (IQ)
1200
VCM = 3 V, IO = 0
Over temperature
(1)
6
650
V
800
1100
nA
1500
Refer to Typical Characteristics.
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6.7 Electrical Characteristics 5 V
TA = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ , unless otherwise noted.
TYP (1)
MAX
VCM = 0.3 V
±1
±2
VCM = 4.7V
±1
±3
PARAMETER
TEST CONDITIONS
MIN
UNIT
OFFSET VOLTAGE
Input offset voltage (VOS)
Over temperature
VCM = 0.3 V and 4.7V
Drift (dVOS/dT)
Power-Supply Rejection Ratio
(PSRR)
mV
±4
1
VS = 1.6 V to 5.5 V, VCM = 0.3 V
83
µV/°C
109
dB
INPUT VOLTAGE RANGE
Common-Mode voltage range (VCM)
CMRR ≥ 60 dB
0
Common-Mode Rejection Ratio
(CMRR)
0 V < VCM < 5 V
73
101
0 V < VCM < 3.9V
88
101
4.4 V < VCM < 5 V
73
109
5
V
dB
INPUT BIAS CURRENT
Input bias current (IB)
TA = 25°C
±0.1
TA = –40°C to 125°C
±1
±100
Input offset current (IOS)
±0.1
pA
±1
INPUT IMPEDANCE
Differential
1013 || 2.5
Common mode
1013 || 2.5
Ω || pF
NOISE
Input voltage noise density, f = 1 kHz (en)
Current noise density, f = 1 kHz (in)
250
nV/√Hz
65
fA√Hz
101
dB
OPEN-LOOP GAIN
Open-loop voltage gain (AOL)
RL = 100 kΩ to V+/2, 0.5 V < VO < 4.5 V
91
OUTPUT
Voltage output swing from positive rail
RL = 100 kΩ to V+/2
3
20
Voltage output swing from negative rail
RL = 100 kΩ to V+/2
2
20
Output current sourcing
Sourcing, VO to V–, VIN(diff) = 100 mV
10
30
Output current sinking
Sinking, VO to V+, VIN(diff) = –100 mV
10
36
mV
mA
FREQUENCY RESPONSE
Gain-bandwidth product (GBWP)
CL = 20 pF
8
Slew rate (SR)
G = +1, Rising edge, 1Vp-p, CL = 20 pF
3.6
G = +1, Falling edge, 1Vp-p, CL = 20 pF
3.7
kHz
V/ms
POWER SUPPLY
Specified voltage range (VS)
Quiescent current per channel (IQ)
1.6
VCM = 0.3 V, IO = 0
5.5
480
Over temperature
Quiescent current per channel (IQ)
1300
VCM = 4.7 V, IO = 0
Over temperature
(1)
680
V
850
1100
nA
1600
Refer to Typical Characteristics.
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6.8 Typical Characteristics
TA = 25 °C, VS = 5 V, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
800
700
600
500
400
125°C
85°C
25°C
0°C
-40°C
300
200
100
0
1.5
2
2.5
3
3.5
4
4.5
5
Supply Voltage (V)
No Output Load
Supply Current per Channel (nA/Ch)
Supply Current per Channel (nA/Ch)
1000
VCM = 0.3V
900
VCM = VS - 0.3V
900
800
700
600
500
400
125°C
85°C
25°C
0°C
-40°C
300
200
100
0
5.5
1.5
2
VCM = 0.3 V
3.5
4
4.5
5
5.5
C001
VCM = (V+) – 0.3 V
Figure 1. Supply Voltage vs Supply Current per Channel,
Low Vcm
Figure 2. Supply Voltage vs Supply Current per Channel,
High Vcm
1000
1000
900
800
700
600
500
400
125°C
85°C
25°C
0°C
-40°C
300
200
100
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Common Mode Voltage (V)
900
800
700
600
500
400
125°C
85°C
25°C
0°C
-40°C
300
200
100
0
1.8
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
Common Mode Voltage (V)
C001
No Output Load
2.7
C001
No Output Load
Figure 3. Supply Current vs
Common Mode at 1.8 V
Figure 4. Supply Current vs
Common Mode at 2.7 V
1000
Supply Current per Channel (nA/Ch)
1000
Supply Current per Channel (nA/Ch)
3
Supply Voltage (V)
No Output Load
0
900
800
700
600
500
400
125°C
85°C
25°C
0°C
-40°C
300
200
100
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
Common Mode Voltage (V)
No Output Load
2.7
3.0
900
800
700
600
500
400
125°C
85°C
25°C
0°C
-40°C
300
200
100
0
3.3
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Common Mode Voltage (V)
C001
4.0
4.5
5.0
C001
No Output Load
Figure 5. Supply Current vs
Common Mode at 3.3 V
8
2.5
C001
Supply Current per Channel (nA/Ch)
Supply Current per Channel (nA/Ch)
1000
Figure 6. Supply Current vs
Common Mode at 5 V
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Typical Characteristics (continued)
100
100
10
10
Output Current (mA)
Output Current (mA)
TA = 25 °C, VS = 5 V, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
1
0.1
-40°C
0.01
1
0.1
-40°C
0.01
25°C
25°C
125°C
125°C
0.001
0.001
1
10
100
1000
10000
Output Referred to V- (mV)
1
100
1000
SRC
VS = 1.8 V
Figure 7. Output Sinking Current vs
Output Swing at 1.8 V
Figure 8. Output Sourcing Current vs
Output Swing at 1.8 V
100
10
10
Output Current (mA)
100
1
0.1
-40°C
0.01
1
0.1
-40°C
0.01
25°C
25°C
125°C
125°C
0.001
0.001
1
10
100
1000
10000
Output Referred to V- (mV)
1
10
100
1000
10000
Output Referred to V+ (mV)
SNK
VS = 2.7 V
SRC
VS = 2.7 V
Figure 9. Output Sinking Current vs
Output Swing at 2.7 V
Figure 10. Output Sourcing Current vs
Output Swing at 2.7 V
100
100
10
10
Output Current (mA)
Output Current (mA)
10000
Output Referred to V+ (mV)
VS = 1.8 V
Output Current (mA)
10
SNK
1
0.1
-40°C
0.01
1
0.1
-40°C
0.01
25°C
25°C
125°C
125°C
0.001
0.001
1
10
100
1000
10000
Output Referred to V- (mV)
1
10
VS = 3.3 V
100
1000
Output Referred to V+ (mV)
SNK
10000
SRC
VS = 3.3 V
Figure 11. Output Sinking Current vs
Output Swing at 3.3 V
Figure 12. Output Sourcing Current vs
Output Swing at 3.3 V
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Typical Characteristics (continued)
TA = 25 °C, VS = 5 V, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
10
10
Output Current (mA)
100
Output Current (mA)
100
1
0.1
-40°C
0.01
1
0.1
-40°C
0.01
25°C
25°C
125°C
125°C
0.001
0.001
1
10
100
1000
1
10000
Output Referred to V- (mV)
10000
SRC
Figure 14. Output Sourcing Current vs
Output Swing at 5 V
50
50
45
45
Short Circuit Current to V+ (mA)
Short Circuit Current to V- (mA)
1000
VS = 5 V
Figure 13. Output Sinking Current vs
Output Swing at 5 V
40
35
30
25
20
15
-40°C
10
25°C
5
125°C
0
40
35
30
25
20
15
-40°C
10
25°C
5
125°C
0
1.5
2
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
1.5
0.08
0.06
0.06
Input Bias Current (pA)
0.10
0.04
0.02
0.00
-0.02
-0.04
0.00
-0.04
-0.08
1.5
Common Mode Voltage (V)
VS = 1.8 V
5
SHR
-0.02
-0.08
1.2
4.5
0.02
-0.06
0.9
4
0.04
-0.06
0.6
3.5
Figure 16. Output Short Circut Current to V+ vs
Supply Voltage
0.08
0.3
3
Ouput set low (sinking), shorted to V+
0.10
0.0
2.5
Supply Voltage (V)
Figure 15. Output Short Circut Current to V- vs
Supply Voltage
-0.10
-0.3
2
SHR
Output set high (sourcing), shorted to V–
Input Bias Current (pA)
100
Output Referred to V+ (mV)
VS = 5 V
TA = 25°C
1.8
2.1
-0.10
-0.3
0.3
0.9
1.5
2.1
2.7
Common Mode Voltage (V)
C001
VS = 3.3 V
3.3
C004
TA = 25°C
Figure 18. Input Bias Current vs
Common Mode Voltage at 3.3V
Figure 17. Input Bias Current vs
Common Mode Voltage at 1.8 V
10
10
SNK
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Typical Characteristics (continued)
TA = 25 °C, VS = 5 V, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
0.10
2.0
1.5
0.06
Input Bias Current (pA)
Input Bias Current (pA)
0.08
0.04
0.02
0.00
-0.02
-0.04
-0.06
1.0
0.5
0.0
-0.5
-1.0
-1.5
-0.08
-0.10
-0.3
-2.0
0.3
0.9
1.5
2.1
2.7
3.3
3.9
4.5
5.1
Common Mode Voltage (V)
VS = 5 V
-0.3
0
TA = 25°C
VS = 1.8 V
0.9
1.2
1.5
1.8
2.1
C002
TA = 85°C
Figure 20. Input Bias Current vs
Common Mode Voltage at 1.8V
2.0
2.0
1.5
1.5
Input Bias Current (pA)
Input Bias Current (pA)
0.6
Common Mode Voltage (V)
Figure 19. Input Bias Current vs
Common Mode Voltage at 5V
1.0
0.5
0.0
-0.5
-1.0
-1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.0
-0.3
0.3
0.9
1.5
2.1
2.7
3.3
Common Mode Voltage (V)
VS = 3.3 V
-0.3
0.3
0.9
1.5
2.1
2.7
3.3
3.9
4.5
5.1
Common Mode Voltage (V)
C005
TA = 85°C
VS = 5 V
Figure 21. Input Bias Current vs
Common Mode Voltage at 3.3 V
C008
TA = 85°C
Figure 22. Input Bias Current vs
Common Mode Voltage at 5 V
50
50
40
40
30
30
Input Bias Current (pA)
Input Bias Current (pA)
0.3
C007
20
10
0
-10
-20
-30
-40
20
10
0
-10
-20
-30
-40
-50
-50
-0.3
0.0
0.3
0.6
0.9
1.2
1.5
Common Mode Voltage (V)
VS = 1.8 V
TA = 125°C
1.8
2.1
-0.3
0.3
0.9
1.5
2.1
2.7
3.3
Common Mode Voltage (V)
C003
VS = 3.3 V
Figure 23. Input Bias Current vs
Common Mode Voltage at 1.8 V
C006
TA = 125°C
Figure 24. Input Bias Current vs
Common Mode Voltage at 3.3 V
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Typical Characteristics (continued)
TA = 25 °C, VS = 5 V, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
Input Bias Current (pA)
40
30
20
10
0
-10
-20
-30
-40
-50
-0.3
0.3
0.9
1.5
2.1
2.7
3.3
3.9
4.5
5.1
Common Mode Voltage (V)
VS = 5 V
TA = 125°C
Input Referred Voltage Noise (nV/SqRtHz)
50
10k
VS = 5V
RL=100k
1k
100
100m
1
CL = 20 pF
10
100
1k
10k
100k
Frequency (Hz)
C009
VS = 5 V
Figure 25. Input Bias Current vs
Common Mode Voltage at 5 V
RL = 100 kΩ
C001
CL = 20 pF
Figure 26. Input Referred Voltage Noise
IN
OUT
OUT
50 mV/div
200 mV/div
IN
Time (100us/div)
Time (200us/div)
C001
VS = ±0.9 V
G = +1
RL = 10 MΩ
VIN = ±100 mV
CL = 20 pF
C002
VS = ±0.9 V
G = +1
Figure 27. Pulse Response, 200mVpp at 1.8 V
RL = 10 MΩ
VIN = ±500mV
CL = 20 pF
Figure 28. Pulse Response, 1Vpp at 1.8V
IN
OUT
OUT
50 mV/div
500 mV/div
IN
Time (100us/div)
Time (200us/div)
C003
VS = ±2.5 V
G = +1
RL = 10 MΩ
VIN = ±100 mV
CL = 20 pF
C002
VS = ±2.5 V
G = +1
Figure 29. Pulse Response, 200mVpp at 5V
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RL = 10 MΩ
VIN = ±1V
CL = 20 pF
Figure 30. Pulse Response, 2Vpp at 5V
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Typical Characteristics (continued)
TA = 25 °C, VS = 5 V, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
135
30
90
20
Phase
10
45
0
0
100
1000
10000
±45
100000
Frequency (Hz)
VS = 1.8 V
RL = 100 kΩ
90
10
45
0
0
±10
100
1000
VS = 5 V
180
135
30
90
20
10
45
0
0
1000
10000
±45
100000
Frequency (Hz)
VS = 1.8 V
RL = 1 MΩ
10
45
0
0
±10
100
1000
VS = 5 V
135
30
90
20
45
0
0
1000
10000
Frequency (Hz)
VS = 1.8 V
RL = 10 MΩ
C009
CL = 20 pF
-40°C
25°C
125°C
Gain
10
100
RL = 1 MΩ
40
180
Phase
±10
±45
100000
Figure 34. Gain and Phase vs
Temperature at 5 V
Gain (dB)
20
10000
Frequency (Hz)
C012
Phase (ƒ)
Gain (dB)
30
135
90
CL = 20 pF
-40°C
25°C
125°C
Gain
180
Phase
Figure 33. Gain and Phase vs
Temperature at 1.8 V
40
C008
CL = 20 pF
-40°C
25°C
125°C
Gain
Phase
100
RL = 100 kΩ
40
Gain (dB)
20
±10
±45
100000
Figure 32. Gain and Phase vs
Temperature at 5 V
Phase (ƒ)
Gain (dB)
30
10000
Frequency (Hz)
C011
CL = 20 pF
-40°C
25°C
125°C
Gain
135
Phase
Figure 31. Gain and Phase vs
Temperature at 1.8 V
40
180
Phase (ƒ)
±10
-40°C
25°C
125°C
Gain
Phase (ƒ)
20
40
90
10
45
0
0
100
1000
10000
±45
100000
Frequency (Hz)
C013
CL = 20 pF
135
Phase
±10
±45
100000
180
VS = 5 V
RL = 10 MΩ
Phase (ƒ)
Gain (dB)
30
180
Gain (dB)
-40°C
25°C
125°C
Gain
Phase (ƒ)
40
C010
CL = 20 pF
Figure 36. Gain and Phase vs
Temperature at 5 V
Figure 35. Gain and Phase vs
Temperature at 1.8 V
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7 Detailed Description
7.1 Overview
The LPV542 dual op amplifier is unity-gain stable and can operate on a single supply, making it highly versatile
and easy to use.
The LPV542 is fully specified and tested from 1.6 V to 5.5 V. Parameters that vary significantly with operating
voltages or temperature are shown in the Typical Characteristics curves.
7.2 Functional Block Diagram
7.3 Feature Description
The amplifier's differential inputs consist of a non-inverting input (+IN) and an inverting input (–IN). The amplifer
amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The
output voltage of the op-amp VOUT is given by Equation 1:
VOUT = AOL (IN+ – IN–)
where
•
AOL is the open-loop gain of the amplifier, typically around 100 dB (100,000x, or 100,000 Volts per microvolt).
(1)
7.4 Device Functional Modes
7.4.1 Rail-To-Rail Input
The input common-mode voltage range of the LPV542 extends to the supply rails. This is achieved with a
complementary input stage — an N-channel input differential pair in parallel with a P-channel differential pair.
The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 800 mV to 200 mV above
the positive supply, while the P-channel pair is on for inputs from 300 mV below the negative supply to
approximately (V+) – 800 mV. There is a small transition region, typically (V+) – 1.2 V to (V+) – 0.8 V, in which
both pairs are on. This 400 mV transition region can vary 200 mV with process variation. Within the 400 mV
transition region PSRR, CMRR, offset voltage, offset drift, and THD may be degraded compared to operation
outside this region.
7.4.2 Supply Current Changes over Common Mode
Because of the ultra-low supply current, changes in common mode voltages will cause a noticeable change in
the supply current as the input stages transition through the transition region, as shown in Figure 37 below.
Supply Current per Channel (nA/Ch)
1000
900
800
700
600
500
400
125°C
85°C
25°C
0°C
-40°C
300
200
100
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Common Mode Voltage (V)
4.5
5.0
C001
Figure 37. Supply Current Change over Common Mode at 5 V
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Device Functional Modes (continued)
For the lowest supply current operation, keep the input common mode range between V- and 1 V below V+.
7.4.3 Design Optimization With Rail-To-Rail Input
In most applications, operation is within the range of only one differential pair. However, some applications can
subject the amplifier to a common-mode signal in the transition region. Under this condition, the inherent
mismatch between the two differential pairs may lead to degradation of the CMRR and THD. The unity-gain
buffer configuration is the most problematic as it will traverse through the transition region if a sufficiently wide
input swing is required.
7.4.4 Design Optimization for Nanopower Operation
When designing for ultralow power, choose system components carefully. To minimize current consumption,
select large-value resistors. Any resistors will react with stray capacitance in the circuit and the input capacitance
of the operational amplifier. These parasitic RC combinations can affect the stability of the overall system. A
feedback capacitor may be required to assure stability and limit overshoot or gain peaking.
When possible, use AC coupling and AC feedback to reduce static current draw through the feedback elements.
Use film or ceramic capacitors since large electolytics may have static leakage currents in the tens to hundreds
of nanoamps.
7.4.5 Common-Mode Rejection
The CMRR for the LPV542 is specified in two ways so the best match for a given application may be used. First,
the CMRR of the device in the common-mode range below the transition region (VCM < (V+) – 0.9 V) is given.
This specification is the best indicator of the capability of the device when the application requires use of one of
the differential input pairs. Second, the CMRR at VS = 5 V over the entire common-mode range is specified.
7.4.6 Output Stage
The LPV542 output voltage swings 3 mV from rails at 3.3 V supply, which provides the maximum possible
dynamic range at the output. This is particularly important when operating on low supply voltages.
The LPV542 Maximum Output Voltage Swing defines the maximum swing possible under a particular output
load.
7.4.7 Driving Capacitive Load
The LPV542 is internally compensated for stable unity gain operation, with a 8 kHz typical gain bandwidth.
However, the unity gain follower is the most sensitive configuration to capacitive load. The combination of a
capacitive load placed directly on the output of an amplifier along with the amplifier’s output impedance creates a
phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the
response will be under damped which causes peaking in the transfer and, when there is too much peaking, the
op amp might start oscillating.
In order to drive heavy (>50pF) capacitive loads, an isolation resistor, RISO, should be used, as shown in
Figure 38. By using this isolation resistor, the capacitive load is isolated from the amplifier’s output. The larger
the value of RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop
will be stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and
reduced output current drive.
-
RISO
VOUT
VIN
+
CL
Figure 38. Resistive Isolation Of Capacitive Load
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LPV542 is a ultra-low power operational amplifier that provides 8 kHz bandwidth with only 490nA quiescent
current, and near precision offset and drift specifications at a low cost. These rail-to-rail input and output
amplifiers are specifically designed for battery-powered applications. The input common-mode voltage range
extends to the power-supply rails and the output swings to within millivolts of the rails, maintaining a wide
dynamic range.
8.2 Typical Application: 60 Hz Twin "T" Notch Filter
VBATT = 3V o2V @ end of life
CR2032 Coin Cell
225 mAh = 5 circuits @ 9.5 yrs.
10 M:
10 M:
VBATT
-
Remote Sensor
10 M:
+
VIN
Signal
+
60 Hz
To ADC
VOUT
10 M:
270 pF
270 pF
10 M:
10 M:
Signal × 2
(No 60 Hz)
60 Hz Twin T Notch Filter
270 pF
AV = 2 V/V
270 pF
Figure 39. 60 Hz Notch Filter
8.2.1 Design Requirements
Small signals from transducers in remote and distributed sensing applications commonly suffer strong 60 Hz
interference from AC power lines. The circuit of Figure 39 notches out the 60 Hz and provides a gain AV = 2 for
the sensor signal represented by a 1 kHz sine wave. Similar stages may be cascaded to remove 2nd and 3rd
harmonics of 60 Hz. Thanks to the nA power consumption of the LPV542, even 5 such circuits can run for 9.5
years from a small CR2032 lithium cell. These batteries have a nominal voltage of 3 V and an end of life voltage
of 2 V. With an operating voltage from 1.6 V to 5.5 V the LPV542 can function over this voltage range.
8.2.2 Detailed Design Procedure
The notch frequency is set by:
F0 = 1 / 2πRC.
(2)
To achieve a 60 Hz notch use R = 10 MΩ and C = 270 pF. If eliminating 50 Hz noise, which is common in
European systems, use R = 11.8 MΩ and C = 270 pF.
The Twin T Notch Filter works by having two separate paths from VIN to the amplifier’s input. A low frequency
path through the series input resistors and another separate high frequency path through the series input
capacitors. However, at frequencies around the notch frequency, the two paths have opposing phase angles and
the two signals will tend to cancel at the amplifier’s input.
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Typical Application: 60 Hz Twin "T" Notch Filter (continued)
To ensure that the target center frequency is achieved and to maximize the notch depth (Q factor) the filter
needs to be as balanced as possible. To obtain circuit balance, while overcoming limitations of available
standard resistor and capacitor values, use passives in parallel to achieve the 2C and R/2 circuit requirements
for the filter components that connect to ground.
To make sure passive component values stay as expected clean board with alcohol, rinse with deionized water,
and air dry. Make sure board remains in a relatively low humidity environment to minimize moisture which may
increase the conductivity of board components. Also large resistors come with considerable parasitic stray
capacitance which effects can be reduced by cutting out the ground plane below components of concern.
Large resistors are used in the feedback network to minimize battery drain. When designing with large resistors,
resistor thermal noise, op amp current noise, as well as op amp voltage noise, must be considered in the noise
analysis of the circuit. The noise analysis for the circuit in Figure 39 can be done over a bandwidth of 2 kHz,
which takes the conservative approach of overestimating the bandwidth (LPV542 typical GBW/AV is lower). The
total noise at the output is approximately 800 µVpp, which is excellent considering the total consumption of the
circuit is only 900 nA. The dominant noise terms are op amp voltage noise , current noise through the feedback
network (430 µVpp), and current noise through the notch filter network (280 µVpp). Thus the total circuit's noise
is below 1/2 LSB of a 10-bit system with a 2 V reference, which is 1 mV.
8.2.3 Application Curve
Figure 40. 60 Hz Notch Filter Waveform
8.3 Do's and Don'ts
Do properly bypass the power supplies.
Do add series resistance to the output when driving capacitive loads, particularly cables, Muxes and ADC inputs.
Do add series current limiting resistors and external schottky clamp diodes if input voltage is expected to exceed
the supplies. Limit the current to 1 mA or less (1 KΩ per volt).
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9 Power Supply Recommendations
The LPV542 is specified for operation from 1.6 V to 5.5 V (±0.8 V to ±2.75 V) over a –40°C to 125°C
temperature range. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 6 V can permanently damage the device.
For proper operation, the power supplies bust be properly decoupled. For decoupling the supply lines it is
suggested that 10 nF capacitors be placed as close as possible to the operational amplifier power supply pins.
For single supply, place a capacitor between V+ and V– supply leads. For dual supplies, place one capacitor
between V+ and ground, and one capacitor between V– and ground.
Low bandwidth nanopower devices do not have good high frequency (> 1 kHz) AC PSRR rejection against highfrequency switching supplies and other 1 kHz and above noise sources, so extra supply filtering is recommended
if kilohertz or above noise is expected on the power supply lines.
10 Layout
10.1 Layout Guidelines
The V+ pin should be bypassed to ground with a low ESR capacitor.
The optimum placement is closest to the V+ and ground pins.
Care should be taken to minimize the loop area formed by the bypass capacitor connection between V+ and
ground.
The ground pin should be connected to the PCB ground plane at the pin of the device.
The feedback components should be placed as close to the device as possible to minimize strays.
There is an internal electrical connection between the exposed Die Attach Pad (DAP) and the V- pin. For best
performance the DAP should be connected to the exact same potential as the V- pin. Do not use the DAP as the
primary V- supply. Floating the DAP pad is not recommended. The DAP and V- pin should be joined directly as
shown in the Layout Example.
10.2 Layout Example
Figure 41. X1SON Layout Example (top view)
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
TI FilterPro Filter Design software, http://www.ti.com/tool/filterpro
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• AN-1798 Designing with Electro-Chemical Sensors, SNOA514
• AN-1803 Design Considerations for a Transimpedance Amplifier, SNOA515
• AN-1852 Designing With pH Electrodes, SNOA529
• Compensate Transimpedance Amplifiers Intuitively, SBOA055
• Transimpedance Considerations for High-Speed Operational Amplifiers, SBOA112
• Noise Analysis of FET Transimpedance Amplifiers, SBOA060
• Circuit Board Layout Techniques, SLOA089
• Handbook of Operational Amplifier Applications, SBOA092
11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LPV542DGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
LP
V542
LPV542DGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
LP
V542
LPV542DNXR
ACTIVE
X1SON
DNX
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
LPV542
LPV542DNXT
ACTIVE
X1SON
DNX
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
LPV542
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LPV542DGKR
VSSOP
DGK
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LPV542DGKT
VSSOP
DGK
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LPV542DNXR
X1SON
DNX
8
3000
330.0
12.4
3.3
3.3
0.7
8.0
12.0
Q1
LPV542DNXT
X1SON
DNX
8
250
180.0
12.5
3.3
3.3
0.7
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LPV542DGKR
VSSOP
DGK
8
2500
364.0
364.0
27.0
LPV542DGKT
VSSOP
DGK
8
250
364.0
364.0
27.0
LPV542DNXR
X1SON
DNX
8
3000
338.0
355.0
50.0
LPV542DNXT
X1SON
DNX
8
250
338.0
355.0
50.0
Pack Materials-Page 2
PACKAGE OUTLINE
DNX0008A
X1SON - 0.5 mm max height
SCALE 4.300
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
0.5 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
(0.127)
TYP
1.65±0.1
4
5
2X
1.5
2.38±0.1
1
8
6X 0.5
8X
PIN 1 ID
(OPTIONAL)
8X
0.45
0.35
0.3
0.2
0.1
0.05
C A
C
B
4221623/A 08/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DNX0008A
X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
SYMM
8X (0.6)
1
8
8X (0.25)
SYMM
(2.38)
(0.94)
6X (0.5)
5
4
(0.575)
( 0.2) VIA
TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221623/A 08/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
DNX0008A
X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.51)
SYMM
METAL
TYP
8X (0.6)
1
8
2X
(1.06)
8X (0.25)
SYMM
(0.63)
6X (0.5)
5
4
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:30X
4221623/A 08/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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