CXM3001R
Digital Satellite Broadcast Front End IC Supports both Japanese Digital Systems
(BS and CS) in a Single Package
CXM3001R
The Japanese BS (broadcast satellite) digital TV broadcasting system
started service last year, meaning that Japan has entered an era of fullfledged digital TV broadcasting.
In the near future, CS (communication satellite) digital TV broadcasting
will begin from the new 110 degree east longitude satellite, providing
further impetus towards the popularization of digital satellite broadcasting.
Thus we expect a wide range of new developments in the near future,
such as viewing on data storage type set-top boxes and PCs.
The CXM3001R integrates almost all the required functions of a digital
satellite broadcast receiver front end in a single package and can
contribute to miniaturization and increased functionality in end products.
Front End Functions
Integrated on a Single IC
No External Inductors or
Varactors Required
The CXM3001R integrates, on a single
chip, all the functions required for digital satellite broadcast receiver, including a direct conversion circuit,
a PLL for tuning, an 8PSK/QPSK
demodulator, and an FEC. As a result,
it can greatly reduce the number of
external components used and contribute to miniaturization in end products.
The CXM3001R supports not only
Japan’s BS digital broadcasts, but also
the DVB-S standard and the 110 degree
east longitude satellite that will soon
start service.
Since all the inductors and varactors
required by the high-frequency
oscillator circuit in the direct conversion
block are built in, no adjustment of the
high-frequency circuit is required. As a
result, the front end block, which is
currently realized as a tuner pack or
module, can now be implemented
onboard.
V
O
I
C
TV tuner ICs up to now have had
the problem that once the IC is
complete, an extremely long time
is required to adjust the external
circuits. (This involves what is
commonly know as “trial and
error.”) Since joining Sony, I had
been solely involved with this
type of high-frequency related
work prior to this project, and I
really enjoyed that type of work.
However, since completing this
IC, this role is to no longer
required. (The IC simply works as
soon as it is installed on the
PWB!) Although I’m proud of this
IC I created, I’m going to miss the
challenge of the adjustment
process.
E
No 30 V Tuning System
Power Supply Required
Until now, TV tuner ICs have required
a 30 V power supply for tuning. However, this means that a special-purpose
power supply is required when used in
applications such as set-top boxes or
PCs, resulting in higher parts counts and
costs. However the CXM3001R
includes a built-in oscillator circuit and
does not require the 30 V power
supply. Furthermore, since the direct
conversion block includes a dedicated
voltage regulator circuit, these circuits
are not influenced by ripple and noise
on the power supply lines, and the
CXM3001R can easily be included in
digital equipment such as PCs.
■
Conforms to the BS digital
standard (ISDB-S)
■
Conforms to the digital CS
standard (DVB-S) and
supports the 110 degree east
longitude satellite
■
No external inductors or
varactors required
■
No 30 V tuning system power
supply required
■
Built-in waveform equalizer
Built-in Waveform
Equalizer
As opposed to conventional analog BS
broadcast receivers, BS digital broadcast receivers are more easily influenced
by the delayed wave reflections that
occur in the antenna lines. As a result,
reception can be difficult in larger
apartment buildings that use a shared
antenna system. To resolve this
problem, the CXM3001R includes a
built-in waveform equalizer in the
demodulator block, and can provide
stable reception in any environment.
Furthermore, it has a ±5 MHz automatic
carrier recovery function and can automatically compensate for frequency
offset in the antenna block.
RF AGC
RF input
VREF
OFFSET_I
VLOOP
AGC control
OFFSET_Q
VDD
ADC
ADC
LPF
TMRN
BCS
TMCC
decoder
AGC
LPF
SYNC
TER
TS7 to TS0
TEN
PAC
IQ AGC
Phase shifter
<Direct conversion
block>
OSC REG.
8PSK/QPSK
demodulator
FEC
Counter
Charge
pump
Phase
det.
Reference
counter
Loop filter
PLL REG.
PLL
control
Reference OSC
<PLL>
Clock
generator
I2C bus
<Demodulator block>
4 MHz
X’tal
VDDH
I2C bus
■ Figure 1 CXM3001R Block Diagram
(RF = 1125 MHz, input level = –40.0 dBm, TC8PSK)
■ Table 1 Main Specifications
1.E+00
Supply voltage
2.5 V, 3.3 V, 5 V
1.E–02
Package
120-pin LQFP
1.E–03
Reception frequency range 950 MHz to 2.15 GHz
BER
1.E–01
1.E–04
1.E–05
1.E–06
1.E–07
1.E–08
1.E–09
1.E–10
6
6.5
7
7.5
8
8.5
9
C/N [dB]
■ Figure 2 C/N vs. BER Characteristics
(RF = 1125 MHz, C/N = 7.9 dB, TC8PSK)
1.0E+00
1.0E–01
BER
1.0E–02
1.0E–03
1.0E–04
1.0E–05
1.0E–06
1.0E–07
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
Input level [dBm]
■ Figure 3 Input Level vs. BER Characteristics
■ Photograph 1 Mounted in an Actual Circuit
MPEG
TS
output
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