MX7541A

MX7541Axxxx
Rev. A
RELIABILITY REPORT
FOR
MX7541Axxxx
PLASTIC ENCAPSULATED DEVICES
August 15, 2003
MAXIM INTEGRATED PRODUCTS
120 SAN GABRIEL DR.
SUNNYVALE, CA 94086
Written by
Reviewed by
Jim Pedicord
Quality Assurance
Reliability Lab Manager
Bryan J. Preeshl
Quality Assurance
Executive Director
Conclusion
The MX7541A successfully meets the quality and reliability standards required of all Maxim products. In addition,
Maxim’s continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim’s quality
and reliability standards.
Table of Contents
I. ........Device Description
II. ........Manufacturing Information
III. .......Packaging Information
IV. .......Die Information
V. ........Quality Assurance Information
VI. .......Reliability Evaluation
......Attachments
I. Device Description
A. General
The MX7541A is a high performance CMOS multiplying 12-bit digital-to-analog converter (DAC). Low Power
operation and 2 bit (0.012%) linearity make it suitable for a wide range of precision data acquisition and
control applications.
Wafer level laser trimmied thin-film resistors and temperature compensated NMOS switches assure true 12bot performance over the full operating termperature range. In addition, all digital inputs are compatible with
both CMOS and TTL logic levels.
Maxim’s MX7541A is electrically and pin compatible with the Analog Devices AD7541A and the AD7541.
Package types include 18-Lead standard width DIP and Small Outline packages.
B. Absolute Maximum Ratings
Item
VDD to GND
VRef to GND
RFB to GND
Digital Input Voltage to GND
Output Voltage (OUT1, OUT2)
Operating Temperature Range
MX7541AJ/AK
MX7541AA/AB
Storage Temp.
Lead Temp. (10 sec.)
Continuous Power Dissipation (TA = +70°C)
18-Pin WSO
18-Pin DIP
Derates above +70°C
18-Pin WSO
18-Pin DIP
Rating
-0.3V, +7V
+/-25V
+/-25V
-0.3V,VDD
-0.3V, VDD
0°C to +70°C
-25°C to +85°C
-65°C to +150°C
+300°C
762mW
889mW
9.5mW/°C
11.1mW/°C
II. Manufacturing Information
A. Description/Function:
CMOS 12-Bit Multiplying DAC
B. Process:
SG5 (Standard 5 micron silicon gate CMOS)
C. Number of Device Transistors:
109
D. Fabrication Location:
Oregon, USA
E. Assembly Location:
Philippines, Malaysia, or Thailand
F. Date of Initial Production:
January, 1988
III. Packaging Information
A. Package Type:
18-Lead WSO
18-Lead PDIP
B. Lead Frame:
Copper
Copper
C. Lead Finish:
Solder Plate
Solder Plate
D. Die Attach:
Silver-filled Epoxy
Silver-filled Epoxy
E. Bondwire:
Gold (1.3 mil dia.)
Gold (1.3 mil dia.)
F. Mold Material:
Epoxy with silica filler
Epoxy with silica filler
G. Assembly Diagram:
Buildsheet # 05-0401-0436
Buildsheet # 05-0401-0435
H. Flammability Rating:
Class UL94-V0
Class UL94-V0
I. Classification of Moisture Sensitivity
per JEDEC standard JESD22-A112: Level 1
Level 1
IV. Die Information
A. Dimensions:
86 x 101 mils
B. Passivation:
Si3N4/SiO2 (Silicon nitride/ Silicon dioxide)
C. Interconnect:
Aluminum/Si (Si = 1%)
D. Backside Metallization:
None
E. Minimum Metal Width:
5 microns (as drawn)
F. Minimum Metal Spacing:
5 microns (as drawn)
G. Bondpad Dimensions:
5 mil. Sq.
H. Isolation Dielectric:
SiO2
I. Die Separation Method:
Wafer Saw
V. Quality Assurance Information
A. Quality Assurance Contacts:
Jim Pedicord (Manager, Reliability Operations)
Bryan Preeshl (Executive Director of QA)
Kenneth Huening (Vice President)
B. Outgoing Inspection Level: 0.1% for all electrical parameters guaranteed by the Datasheet.
0.1% For all Visual Defects.
C. Observed Outgoing Defect Rate: < 50 ppm
D. Sampling Plan: Mil-Std-105D
VI. Reliability Evaluation
A. Accelerated Life Test
The results of the 135°C biased (static) life test are shown in Table 1. Using these results, the Failure
Rate (λ) is calculated as follows:
λ=
1
=
MTTF
1.83
(Chi square value for MTTF upper limit)
192 x 4389 x 80 x 2
Temperature Acceleration factor assuming an activation energy of 0.8eV
λ = 13.57 x 10-9
λ = 13.57 F.I.T. (60% confidence level @ 25°C)
This low failure rate represents data collected from Maxim’s reliability monitor program. In addition to
routine production Burn-In, Maxim pulls a sample from every fabrication process three times per week and subjects
it to an extended Burn-In prior to shipment to ensure its reliability. The reliability control level for each lot to be
shipped as standard product is 59 F.I.T. at a 60% confidence level, which equates to 3 failures in an 80 piece
sample. Maxim performs failure analysis on any lot that exceeds this reliability control level. Attached Burn-In
Schematic (Spec. # 06-0248) shows the static Burn-In circuit. Maxim also performs quarterly 1000 hour life test
monitors. This data is published in the Product Reliability Report (RR-1M).
B. Moisture Resistance Tests
Maxim pulls pressure pot samples from every assembly process three times per week. Each lot sample
must meet an LTPD = 20 or less before shipment as standard product. Additionally, the industry standard
85°C/85%RH testing is done per generic device/package family once a quarter.
C. E.S.D. and Latch-Up Testing
The DA57 die type has been found to have all pins able to withstand a transient pulse of ± 1000V, per MilStd-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device
withstands a current of ±250mA.
Table 1
Reliability Evaluation Test Results
MX7541Axxxx
TEST ITEM
TEST CONDITION
Static Life Test (Note 1)
Ta = 135°C
Biased
Time = 192 hrs.
FAILURE
IDENTIFICATION
PACKAGE
DC Parameters
& functionality
SAMPLE
SIZE
NUMBER OF
FAILURES
80
0
77
77
0
0
0
Moisture Testing (Note 2)
Pressure Pot
Ta = 121°C
P = 15 psi.
RH= 100%
Time = 168hrs.
DC Parameters
& functionality
WSO
PDIP
85/85
Ta = 85°C
RH = 85%
Biased
Time = 1000hrs.
DC Parameters
& functionality
77
DC Parameters
& functionality
77
Mechanical Stress (Note 2)
Temperature
Cycle
-65°C/150°C
1000 Cycles
Method 1010
Note 1: Life Test Data may represent plastic DIP qualification lots.
Note 2: Generic Package/Process data
0
Attachment #1
TABLE II. Pin combination to be tested. 1/ 2/
Terminal A
(Each pin individually
connected to terminal A
with the other floating)
Terminal B
(The common combination
of all like-named pins
connected to terminal B)
1.
All pins except VPS1 3/
All VPS1 pins
2.
All input and output pins
All other input-output pins
1/ Table II is restated in narrative form in 3.4 below.
2/ No connects are not to be tested.
3/ Repeat pin combination I for each named Power supply and for ground
(e.g., where VPS1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc).
3.4
Pin combinations to be tested.
a.
Each pin individually connected to terminal A with respect to the device ground pin(s) connected
to terminal B. All pins except the one being tested and the ground pin(s) shall be open.
b.
Each pin individually connected to terminal A with respect to each different set of a combination
of all named power supply pins (e.g., VSS1, or VSS2 or VSS3 or VCC1 , or VCC2 ) connected to
terminal B. All pins except the one being tested and the power supply pin or set of pins shall be
open.
c.
Each input and each output individually connected to terminal A with respect to a combination of
all the other input and output pins connected to terminal B. All pins except the input or output pin
being tested and the combination of all the other input and output pins shall be open.
TERMINAL C
R1
R2
S1
TERMINAL A
REGULATED
HIGH VOLTAGE
SUPPLY
S2
C1
DUT
SOCKET
SHORT
TERMINAL B
TERMINAL D
Mil Std 883D
Method 3015.7
Notice 8
R = 1.5kΩ
C = 100pf
CURRENT
PROBE
(NOTE 6)

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project