datasheet for ML22808 by LAPIS Semiconductor

datasheet for ML22808 by LAPIS Semiconductor
FEDL2280XDIGEST-04
Issue Date: Nov.16, 2009
ML22808/ML22804/ML22802-XXX
ML22P808/ML22P804/ML22P802
LAPIS Semiconductor ADPCM Algorithm-Based Speech Synthesis LSI
GENERAL DESCRIPTION
The ML22808/ML22804/ML22802-xxx are speech synthesis LSI devices that have P2ROM for storing voice
data. The voice output component has an ADPCM2 decoder to enable high speech quality, a D/A converter,
and a low-pass filter.
It is easy to configure a speech synthesizer by connecting a power amplifier and a CPU externally.
The ML22808/ML22804/ML22802-xxx allow selection of a playback method from among the 8-bit PCM,
non-linear 8-bit PCM, 16-bit PCM, and 4-bit ADPCM2 algorithms and enable volume control.
The ML22808/ML22804/ML22802-xxx, supported by the ROM codes, are the products in which written speech
data is included.
The ML22P808/ML22P804/ML22P802 are OTP products in which speech data can be easily written by the user
using a dedicated writer. These devices are suitable for applications in developing products, manufacturing of a
wide variety of products in small quantities, and requiring quick turn around.
 Capacity of the internal memory device and the maximum vocal reproduction time (when 4-bit OKI
ADPCM2 algorithm used)
Product name
ROM capacity
ML22808-XXX/ML22P808
ML22804-XXX/ML22P804
ML22802-XXX/ML22P802
8 Mbits
4 Mbits
2 Mbits
Maximum vocal reproduction time (sec)
FSAM = 4.0 kHz
FSAM = 8.0 kHz
FSAM = 16 kHz
524
262
131
262
131
65
131
65
32
 Speech synthesis method:













An algorithm can be specified for each phrase from among the following:
4-bit OKI ADPCM2
8-bit Nonlinear PCM
8-bit PCM/16-bit PCM
Sampling frequency:
A fsam value can be specified fro each phrase.
4.0/8.0/16.0 kHz, 5.3/10.7 kHz, 6.4/12.8 kHz
Built-in low-pass filter and 12-bit D/A converter
CPU command interface:
3-wired serial / clock synchronous
Maximum number of phrases: 256 phrases, from 00h to FFh (per bank)
Memory bank switching:
Enabled between bank 1 and bank 4 using the SEL0 and SEL1 pins
Memory bank selecting:
Selectable between bank 1 and bank 4 by setting the SEL0 and SEL1 pins
(Other than ML22802/ML22P802)
Selectable between bank1 and bank 2 (ML22802/ML22P802)
Volume control:
Can be adjusted in 16 levels or set to OFF
Repeat function:
LOOP command
Source oscillation frequency: 4.096 MHz
Power supply voltage:
2.7 to 3.6 V
Operating temperature range: -20 to +85C
Package:
30-pin plastic SSOP (SSOP30-P-56-0.65-K)
Product name:
ML22P808MB, ML22P804MB, ML22P802MB
ML22808-xxxMB, ML22804-xxxMB, ML22802-xxxMB
(xxx indicates a ROM code number)
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ML22808/ML22804/Ml22802-XXX
The table below summarizes the differences between the ML2216 and the ML2280X.
Item
CPU interface
Playback method
Maximum number of phrases
Sampling frequency (kHz)
Clock frequency
D/A converter
Low-pass filter
Speaker driving amplifier
Edit ROM
Volume control
Silence insertion
Repeat function
Interval at which a seam is
silent during continuous
playback (*1)
Memory bank switching
Package
ML2216
Serial
4-bit ADPCM2
8-bit straight PCM
8-bit non-linear PCM
16-bit straight PCM
256
4.0/5.3/6.4/
8.0/10.7/12.8
16.0
4.096 MHz (has a crystal
oscillator circuit built-in)
Current-type 12-bit
3D comb filter
Built-in type;
0.3W (at 8, VDD=5V)
Yes
16 levels
Yes
20 to 1024 ms (4 ms steps)
Yes
ML2280X
Serial
4-bit ADPCM2
8-bit straight PCM
8-bit non-linear PCM
16-bit straight PCM
256 up to 1024 (per bank)
4.0/5.3/6.4/
8.0/10.7/12.8
16.0
4.096 MHz (has a crystal
oscillator circuit built-in)
Current-type 12-bit
3D comb filter
Yes
16 levels
Yes
20 to 1024 ms (4 ms steps)
Yes
No
No
No
44-pin QFP
Yes
30-pin SSOP
No
*1: Continuous playback as shown below is possible.
1 phrase
1 phrase
No silence interval
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FEDL2280XDIGEST-04
ML22808/ML22804/Ml22802-XXX
BLOCK DIAGRAM
ML22808/ML22804/ML22P808/ML22P804:
Address Controller
19-/20-bit Multiplexer
4-/8-Mbit ROM
VPP
DVDD
PVDD
DGND
PGND
Phrase Address Latch
19-/20-bit
Address Counter
ADPCM Synthesizer
CS
SCK
PCM Synthesizer
DI
BUSY
NCR
DIPH
SEL0
I/O
Interface
LPF
Timing
Controller
SEL1
12-bit DAC
TEST0
TEST1
RESET
OSC
TESTO1
TESTO2
XT
XT
AOUT
AV DD
AGND
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FEDL2280XDIGEST-04
ML22808/ML22804/Ml22802-XXX
ML22802/ML22P802:
Address Controller
18-bit Multiplexer
2-Mbit ROM
VPP
DVDD
PVDD
DGND
PGND
Phrase Address Latch
18-bit
Address Counter
ADPCM Synthesizer
CS
SCK
PCM Synthesizer
DI
BUSY
NCR
DIPH
SEL
I/O
Interface
LPF
Timing
Controller
TEST0
12-bit DAC
TEST1
RESET
TESTO1
OSC
TESTO2
XT
XT
AOUT
AVDD
AGND
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ML22808/ML22804/Ml22802-XXX
PIN CONFIGURATION (TOP VIEW)
ML22808/ML22804/ML22P808/ML22P804:
XT
XT
TEST0
TEST1
DGND
DIPH
SEL0
SEL1
CS
SCK
DI
BUSY
NCR
RESET
NC
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DVDD
AVDD
AOUT
NC
AGND
VPP
PGND
TESTO1
PVDD
NC
NC
PGND
TESTO0
NC
NC
NC: No Connection
30-Pin Plastic SSOP
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FEDL2280XDIGEST-04
ML22808/ML22804/Ml22802-XXX
ML22802/ML22P802:
XT
XT
TEST0
TEST1
DGND
DIPH
SEL
TEST2
CS
SCK
DI
BUSY
NCR
RESET
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DVDD
AVDD
AOUT
NC
AGND
VPP
PGND
TESTO1
PVDD
NC
NC
PGND
TESTO0
NC
NC
NC: No Connection
30-Pin Plastic SSOP
6/19
FEDL2280XDIGEST-04
ML22808/ML22804/Ml22802-XXX
PIN DESCRIPTION
Pin
Symbol
Type
1
XT
I
2
XT
O
3
4
5
TEST0
TEST1
DGND
I
I
—
6
DIPH
I
7
(SEL)
SEL0
I
8
(TEST2)
SEL1
I
9
CS
I
10
11
SCK
DI
I
I
12
BUSY
O
13
NCR
O
14
RESET
I
18
19,24
TESTO0
PGND
O
—
22
PVDD
—
23
TESTO1
O
Description
Connects to a crystal or a ceramic resonator.
A feedback resistor of around 1 M is built in between this XT pin and
XT pin. When using an external clock, input the clock from this pin.
If a crystal or a ceramic resonator is used, connect it as close to the LSI
as possible.
Connects to a crystal or a ceramic resonator.
When using an external clock, leave this pin open.
If a crystal or a ceramic resonator is used, connect it as close to the LSI
as possible
Input pin for testing. Tie this pin at a “L” level (DGND level).
Input pin for testing. Tie this pin at a “L” level (DGND level).
Digital ground pin.
Pin for choosing between rising edges and falling edges as to the edges
of the SCK pulses used for shifting serial data input to the DI pin into the
inside of the LSI. When this pin is at a “L” level, DI input data is shifted
into the LSI on the rising edges of the SCK clock pulses; when this pin is
at a “H” level, DI input data is shifted into the LSI on the falling edges of
the SCK clock pulses.
Memory bank selecting pin. Enabled when memory bank selecting is
specified at the time the PUP1 or PUP2 command is input. Do not
change during speech playback (when the BUSY pin is at “L”)
ML22808/ML22804/ML22P808/ML22P804:
Memory bank selecting pin. Enabled when memory bank selecting is
specified at the time the PUP1 or PUP2 command is input. Do not
change during speech playback (when the BUSY pin is at “L”)
ML22802/ML22P802:
Input pin for testing. Tie this pin at “L” (DGND level).
Chip select input pin.
A “L” level on this pin enables the serial interface.
Serial clock input pin.
Serial data input pin.
Pin that outputs a signal that indicates the phrase playback status.
If the LSI is playing a phrase, this pin outputs a “L” level.
If the LSI is in a standby state, this pin outputs a “H” level.
Pin that outputs a signal that indicates whether command input is
enabled or disabled.
If command input is enabled, this pin outputs a “H” level.
If command input is disabled, this pin outputs a “L” level.
During a reset input, the entire circuit is stopped and enters a power
down state.
Upon power-on, input a “L” level to this pin. Put this pin into a “H” level
after the power supply voltage is stabilized.
Output pin for testing. Leave this pin open.
Ground pin for the internal P2ROM.
Power supply pin for the internal P2ROM.
Connect a capacitor of 0.1 F or more between this pin and PGND.
Output pin for testing. Leave this pin open.
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ML22808/ML22804/Ml22802-XXX
Pin
Symbol
Type
25
VPP
I
26
28
AGND
AOUT
—
O
29
AVDD
—
30
DVDD
—
Description
VPP power supply pin used for writing data to the internal P2ROM.
Tie this pin at the DGND level.
Analog ground pin.
Playback signal output pin.
Analog power supply pin.
Connect a capacitor of 0.1 F or more between this pin and PGND.
Digital power supply pin.
Connect a capacitor of 0.1 F or more between this pin and PGND.
Note:
The pin names in the parentheses are applied to ML22802/ML22P802.
8/19
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ML22808/ML22804/Ml22802-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Digital power supply
voltage
Analog power supply
voltage
Symbol
(DGND = PGND = AGND = 0 V)
Rating
Unit
Condition
DVDD, PVDD
–0.3 to +5.0
V
–0.3 to +5.0
V
–0.3 to DVDD+0.3
V
1.3
W
Ta = 25°C
AVDD
Input voltage
VIN
Power dissipation
PD
Ta = 25°C
When a JEDEC2-layer
board is mounted
ISC
—
10
mA
TSTG
—
–55 to +150
°C
Output short-circuit
current
Storage temperature
RECOMMENDED OPERATING CONDITIONS
Parameter
Digital power supply
voltage
Analog power supply
voltage
Operating temperature
Master clock frequency
External crystal
oscillator capacitance
(DGND = PGND = AGND = 0 V)
Range
Unit
Symbol
Condition
DVDD, PVDD
—
2.7 to 3.6
V
AVDD
—
2.7 to 3.6
V
TOP
—
-20 to +85
Typ.
Max.
°C
fOSC
—
Cd, Cg
—
Min.
3.5
4.096
4.5
15
30
45
MHz
pF
9/19
FEDL2280XDIGEST-04
ML22808/ML22804/Ml22802-XXX
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
“H” input voltage
“L” input voltage
“H” output current 1
“H” output current 2 (*1)
“L” output current 1
“L” output current 2 (*1)
“H” input current 1
“H” input current 2 (*2)
“L” input current 1
“L” input current 2 (*2)
“H” output leakage
current (*3)
“L” output leakage
current (*3)
Supply current during
playback
Power-down supply
current
DVDD = PVDD = AVDD = 2.7 to 3.6 V, DGND = PGND = AGND = 0 V, Ta = -20 to +85°C
Symbol
Condition
Min.
Typ.
Max.
Unit
0.86 
—
—
V
VIH
—
VDD
0.14 
V
VIL
—
—
—
VDD
VOH1
IOH = 1 mA
VDD – 0.4
—
—
V
VOH2
IOH = 100 µA
VDD – 0.4
—
—
V
VOL1
IOL = 2 mA
—
—
0.4
V
VOL2
IOL = 100 µA
—
—
0.4
V
IIH1
VIH = DVDD
—
—
10
µA
IIH2
VIH = DVDD
0.3
2.0
15
µA
IIL1
VIL = DGND
–10
—
—
µA
IIL2
VIL = DGND
–15
2.0
–0.3
µA
ILOH
VIH = DVDD
—
—
10
µA
ILOL
VIL = DGND
–10
—
—
µA
IDD
fOSC = 4.096 MHz
No output load
—
—
10
mA
IDDS
Ta = -20 to +85°C
—
1
20
µA
Note: The input voltages and input currents apply to all the input pins except the XT pin.
The output voltages apply to all the output pins except the AOUT pin.
*1: Applies to the XT pin.
*2: Applies to the XT pin.
*3: Applies to the TESTO0 and TESTO1 pins.
Analog Section Characteristics
DVDD = PVDD = AVDD = 2.7 to 3.6 V, DGND = PGND = AGND = 0 V, Ta = -20 to +85°C
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
During silence
5
—
—
k
AOUT output load resistance
RLAO
playback
AOUT output voltage range
VAOUT
No output load
0.07  AVDD
—
0.64  AVDD
V
10/19
FEDL2280XDIGEST-04
ML22808/ML22804/Ml22802-XXX
FUNCTIONAL DESCRIPTION
Serial CPU Interface
Command data can be input through the DI pin by signals input through the CS and SCK pins.
Setting the CS pin to a “L” level enables the serial CPU interface.
After the CS pin is set to a “L” level, the command data, which is synchronized with the SCK clock signal, is
input through the DI pin from the MSB. The command data input through the DI pin is shifted into the LSI on
the rising or falling edges of the SCK clock pulses and the command is executed by the rising or falling edge of
the eighth pulse of the SCK clock.
Choosing between rising edges and falling edges of the clock pulses input through the SCK pin is determined by
the signal input through the DIPH pin:
- When the DIPH pin is at a “L” level, the data input through the DI pin is shifted into the LSI on the rising
edges of the SCK clock pulses.
- When the DIPH pin is at a “H” level, the data input through the DI pin is shifted into the LSI on the falling
edges of the SCK clock pulses.
It is possible to input command data in the LSI even by holding the CS pin continuously at a “L” level.
However, if unexpected pulses caused by noise are induced through the SCK pin, SCK clock pulses are
incorrectly counted. As a result, command data cannot be input correctly. Setting the CS pin to a “H” level
returns the count of the SCK clock pulses to the initial state.
Command and Data Input Timings
 SCK rising edge operation (when DIPH pin = “L” level)
CS
SCK
D7
DI
D6
D5
D4
D3
D2
D1
(MSB)
D0
(LSB)
CS
SCK
DI
D7
D6
D5
D4
D3
D2
D1
(MSB)
D0
(LSB)
 SCK falling edge operation (when DIPH pin = “H” level)
CS
SCK
D7
DI
D6
D5
D4
D3
D2
D1
(MSB)
D0
(LSB)
CS
SCK
DI
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
(LSB)
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ML22808/ML22804/Ml22802-XXX
Command List
Each command is configured in 1-byte (8-bit) units.
command by two bytes each.
Each of the PLAY and MUON command forms one
Command
D7
D6
D5
D4
D3
D2
D1
D0
PUP1
0
0
0
0


S1
S0
PUP2
0
0
0
1


S1
S0
PDWN1
0
0
1
0




PDWN2
0
0
1
1




0
1
0
0




F7
F6
F5
F4
F3
F2
F1
F0
0
1
1
0




0
1
1
1




M7
M6
M5
M4
M3
M2
M1
M0
SLOOP
1
0
0
0




CLOOP
1
0
0
1




VOL
1
0
1
0
V3
V2
V1
V0
PLAY
STOP
MUON
S1, S0
F7–F0
M7–M0
V3–V0
Description
Instantly shifts the device currently powered
down to a command wait state.
Suppresses pop noise and shifts the device
currently powered down to a command wait
state.
Instantly shifts the device from a command wait
state to a power down state.
Suppresses pop noise and shifts the device
from a command wait state to a power down
state.
Phrase-specified playback start command.
Use the data of the 2nd byte to specify a
phrase number.
Playback stop command.
Inserts silence.
Use the data of the 2nd byte to specify the
length of silence.
Command for setting the repeat playback
mode.
Enabled during playback.
Command for releasing the repeat playback
mode.
If the STOP command is input, repeat playback
mode is released automatically.
Volume setting command.
: Number of memory banks (*)
: Phrase address
: Length of silence period
: Sound volume
* S0 is fixed to “0” for ML22802/ML22P802.
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ML22808/ML22804/Ml22802-XXX
Power Down Function
This LSI has the power down function. When in a power down state, all the circuits including the oscillator
circuit stop operating, thus minimizing the supply current. When supplying an external clock to the XT pin, tie
the pin at a “L” level during power down.
The figure below shows a equivalent circuit to an oscillator circuit.
Power down signal
Master clock inside the
LSI
(During power down = “L”)
approx. 1 M
XT
XT
The Initial Status at Reset Input and the Status at Power Down of Output Pins
The status of relative output pins at reset input and power down is shown below.
Digital
output pin
State
NCR
BUSY
“H” level
“H” level
Analog
output pin
State
AOUT
GND level
Voice Synthesis Algorithm
The ML22804/ML22808-xxx contain four algorithm types to match the characteristic of playback voice: 4-bit
ADPCM2 algorithm, 8-bit straight ADPCM2 algorithm, 8-bit non-linear PCM algorithm, and 16-bit straight
PCM algorithm.
Key feature of each algorithm is described in the table below.
Voice synthesis
algorithm
Applied waveform
OKI 4-bit ADPCM2
Normal voice waveform
OKI 8-bit Nonlinear
PCM
8-bit PCM
16-bit PCM
High-frequency
components inclusive
sound effect etc.
Feature
LAPIS Semiconductor’s specific speech synthesis algorithm
of improved waveform follow-up with improved 4-bit ADPCM.
Algorithm, which plays back mid-range of waveform as 10-bit
equivalent voice quality.
Normal 8-bit PCM algorithm
Normal 16-bit PCM algorithm
13/19
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Memory Allocation and Creating Voice Data
The ROM is partitioned into four data areas: voice (i.e., phrase) control area, test area, voice area, and edit ROM
area.
The voice control area manages the ROM’s voice data. It contains data for controlling the start/stop addresses
of voice data for 256 phrases, use/non-use of the edit ROM function and so on.
The test area contains data for testing.
The voice area contains actual waveform data.
The edit ROM area contains data for effective use of voice data. For the details, refer to the section of “Edit
ROM Function.”
No edit ROM area is available unless the edit ROM is used.
The ROM data is created using a dedicated tool.
ROM address (ML22808/ML22804/ML22802-XXX, ML22P808/ML22P804/ML22P802)
0x00000
Voice control area
(Fixed16 Kbits)
0x007FF
0x00800
0x00807
0x00808
Test area
Voice area
Max: 0xFFFFF
Max: 0xFFFFF
Edit ROM area
Depends on creation
of ROM data.
Playback Time and Memory Capacity
The playback time depends upon the memory capacity, sampling frequency, and playback method.
The equation showing the relationship is given below.
The equation below gives the playback time when the edit ROM function is not used.
(Bit length is 2 bits for 2-bit ADPCM2; 4 bits for 4-bit ADPCM2; 8 bits for PCM.)
Example
: Let the sampling frequency be 16 kHz and 4-bit ADPCM2 algorithm.
approx. 65 seconds, as shown below.
Playback time =
1.024  (4096 – 16) (Kbit)
16 (kHz)  4 (bit)
Then the playback time is
 65 (sec)
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Edit ROM Function
The edit ROM function makes it possible to play back multiple phrases in succession.
are set using the edit ROM function:
 Continuous playback:
The following functions
There is no limit to the number of times a continuous playback can be
specified. It depends on the memory capacity only.
20 to 1024 ms
 Silence insertion function:
Using the edit ROM function enables an effective use of the memory capacity of voice ROM.
Below is an example of the ROM configuration in the case of using the edit ROM function.
Example 1:
Phrases Using the Edit ROM Function
Phrase 1
A
B
D
Phrase 2
A
C
D
Phrase 3
E
B
D
Phrase 4
E
C
D
Phrase 5
A
Example 2:
B
D
Silence
E
C
Example of ROM Data Where Contents of Example 1 Are Stored in ROM
Address control area
A
B
C
D
E
F
Editing area
15/19
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FEDL2280XDIGEST-04
ML22808/ML22804/Ml22802-XXX
Memory Bank Selecting Function
Using the memory bank selecting function, the internal ROM area in the ML22808/ML22804/ML22P808/
ML22P804 can be divided into up to four areas. If four banks are used, up to 1024 phrases can be played
back since each bank is capable of up to 256 phrases. Using the memory bank selecting function, the internal
ROM area in the MLl22802/ML22P802 can be divided into up to two areas. If two banks are used, up to 512
phrases can be played back because each bank is capable of up to 256 phrases. Using this function, it is
possible to put together multiple ROM codes into one code.
In the case of the ML22808/ML22804/ML22P808/ML22P804, the memory is used by setting the SEL1 and
SEL0 pins and in the case of the ML22802/ML22P802, the memory is used by setting the SEL pin, as shown in
the tables below. In addition, when playing phrases, it is necessary to specify the number of memory banks by
PUP1 or PUP2.
““ in the tables below means Don’t Care, whether 0 or 1.
Note that, if the memory bank selecting fnction is used, it is necessary to divide data when ROM data is created
and store the divided data in the specified area in advance.
For one memory banks:
SEL1

SEL0

ML22P808/ML22808-XXX
00000h -FFFFFh
ML22P804/ML22804-XXX
00000h – 7FFFFh
SEL

ML22P802/ML22802-XXX
00000h – 3FFFFh
ML22P804/ML22804-XXX
00000h – 3FFFFh
40000h – 7FFFFh
SEL
0
1
ML22P802/ML22802-XXX
00000h – 1FFFFh
20000h – 3FFFFh
For two memory banks:
SEL1


SEL0
0
1
ML22P808/ML22808-XXX
00000h – 7FFFFh
80000h – FFFFFh
For four memory banks:
SEL1
0
0
1
1
SEL0
0
1
0
1
ML22P808/ML22808-XXX
00000h–3FFFFh
40000h–7FFFFh
80000h–BFFFFh
C0000h–FFFFFh
ML22P804/ML22804-XXX
00000h–1FFFFh
20000h–3FFFFh
40000h–5FFFFh
60000h–7FFFFh
Shown below is an example of memory division for the M22808 (8 Mbits).
0–3FFFFh
Bank 1
Capacity: 8 Mbits
Max. number of
phrases: 256
Bank 1
Capacity: 4 Mbits
Max. number of
phrases: 256
40000–7FFFFh
Bank 2
Capacity: 4 Mbits
Max. number of
phrases: 256
80000–BFFFFh
C0000–FFFFFh
Number of memory
divisions: 1
8-Mbit  1 area
Bank 1
Capacity: 2 Mbits
Max. number of
phrases: 256
Bank 2
Capacity: 2 Mbits
Max. number of
phrases: 256
Bank 3
Capacity: 2 Mbits
Max. number of
phrases: 256
Bank 4
Capacity: 2 Mbits
Max. number of
phrases: 256
Number of memory
divisions: 2
Number of memory
divisions: 4
4-Mbit  2 areas
2-Mbit  4 areas
16/19
FEDL2280XDIGEST-04
ML22808/ML22804/Ml22802-XXX
APPLICATION CIRCUITS
 ML22808/ML22804/ML22P808/ML22P804
MCU
RESET
CS
SCK
DI
NCR
BUSY
AOUT
Speaker amplifier
DIPH
SEL1
SEL0
TEST0,1
VPP
33pF
XT
DVDD
PVDD
AVDD
3.3V
4.096MHz
XT
33pF
DGND
PGND
AGND
 ML22802/ML22P802
MCU
RESET
CS
SCK
DI
NCR
BUSY
AOUT
Speaker amplifier
DIPH
SEL
33pF
TEST0,1, 2
VPP
DVDD
PVDD
AVDD
XT
4.096MHz
XT
33pF
3.3V
DGND
PGND
AGND
17/19
FEDL2280XDIGEST-04
ML22808/ML22804/Ml22802-XXX
PACKAGE DIMENSIONS
(Unit: mm)
SSOP30-P-56-0.65-K
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5μm)
0.19 TYP.
5/Dec. 5, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
18/19
FEDL2280XDIGEST-04
ML22808/ML22804/Ml22802-XXX
NOTICE
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS
Semiconductor Co., Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be
obtained from LAPIS Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor
shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any
license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties.
LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such
technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such
as derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility
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The Products are not designed or manufactured to be used with any equipment, device or system which
requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat
to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
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representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled
under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit
under the Law.
Copyright
2009 - 2011 LAPIS Semiconductor Co., Ltd.
19/19
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