"X-Band Two-Stage High-Efficiency Switched

"X-Band Two-Stage High-Efficiency Switched
X -Band Two-Stage High-Efficiency
Switched-Mode Power Amplifiers
Srdjan Pajić, Student Member, IEEE, Narisi Wang, Student Member, IEEE, Paul M. Watson, Member, IEEE,
Tony K. Quach, Member, IEEE, and Zoya Popović, Fellow, IEEE
Abstract—This paper presents efficiency optimization of
-band two-stage microwave power amplifiers (PAs) in which
the output stage is designed to operate in class-E mode. A hybrid
PA which uses the same MESFET devices in both stages achieves
16 dB of saturated gain with an output power of 20 dBm and total
power added efficiency (PAE) of 52% at 10 GHz. A broadband
monolithic two-stage double heterojunction bipolar transistor
PA, fabricated by Northrop Grumman Space Technology, with a
class-AB first stage and class-E second stage achieves 24.6 dBm of
output power with 24.6-dB gain and total PAE of 52% at 8 GHz.
The design is performed starting from class-E theory and using
load–pull measurements and/or nonlinear simulations.
Index Terms—Class E, load–pull, power amplifiers, two stage.
Fig. 1. Directly coupled two-stage switched-mode PA. Interstage and
output matching networks provide fundamental and harmonic frequency
terminations for the first and second stage, respectively. Biasing is provided
using high-impedance bias lines and series dc blocking capacitors C .
WITCHED-MODE power amplifiers (PAs) exhibit inherently low gain compared to other classes of operation, due
to deep compression required for active device switching [1],
[2]. In order to improve the power gain, high-efficiency stages
can be cascaded. The goal of this paper is to examine tradeoffs in
high-efficiency PA design when the efficiencies, gains, biases,
and output powers of both stages are design parameters. The
analysis, design, and characterization of two dual-stage class-E
PAs is presented as follows.
• Section II discusses effects of driver-stage efficiency on
overall two-stage PA performance. By defining the reduction of PAE due to the addition of the driver stage, it is
found that the overall PAE can be equal or even greater
than the second stage PA, provided that a high-efficiency
driver stage is used.
• A hybrid two-stage class-E PA based on identical GaAs
MESFET driver and power stage active devices is presented in Section III. Bias control is used to ensure class-E
operation for different output powers using the same active device.
• Section IV discusses a monolithic two-stage class-E
PA implemented in InP DHBT technology, fabricated
by Northrop Grumman Space Technology (NGST). In
Manuscript received November 2, 2004; revised March 21, 2005. This work
was supported by Wright-Patterson Air Force Base, by Wyle Laboratories under
Grant PO 19035.0D.31-369S, and by the Defense Advanced Research Projects
Agency Intelligent RF Front Ends Program under Grant N00014-02-1-0501.
S. Pajić, N. Wang, and Z. Popović are with the Department of Electrical and
Computer Engineering, University of Colorado at Boulder, Boulder, CO 803090425 USA (e-mail: zoya.popovic@colorado.edu).
P. M. Watson and T. K. Quach are with the Sensors Directorate, Air Force
Research Laboratory, Wright-Patterson Air Force Base, WPAFB, OH 45433
USA. (e-mail: paul.watson@wpafb.af.mil).
Digital Object Identifier 10.1109/TMTT.2005.854239
this amplifier a smaller periphery device is used for the
class-AB driver stage.
Section V summarizes the properties of the PAs from Sections III and IV. The hybrid amplifier using the same device in both stages demonstrates comparable efficiency to
the monolithic PA.
Adding multiple amplifier stages to increase gain results in
decreased efficiency. To quantify the tradeoff between gain and
(Fig. 1)
efficiency in a two-stage amplifier, drain efficiency
can be expressed in terms of the drain efficiencies and gains of
, and
the individual stages
The assumption used to derive (1) is that the two stages are
perfectly isolated, so that their individual characteristics are
maintained. Assuming that the second stage already operates in
a high-efficiency mode (class E, for example), it is interesting
to examine the overall drain efficiency as a function of the mode
of operation of the driver stage. Fig. 2 shows the two-stage
dependence on the input stage drain efficiency. The parameter
in the plots is the second-stage gain . For an -band class-E
PA in the second stage, e.g., [3], with a saturated power gain
%, an increase of driver-stage efficiency
of 8 dB and
from 20% (Class A) to 70% (class E) results in the following:
• increase in overall
from 45% to 61%;
• 25% decrease in dc power consumption;
• 35% increase in battery lifetime (assuming constant battery characteristics over time);
• 48% reduction in power dissipated to heat in the active
0018-9480/$20.00 © 2005 IEEE
Fig. 2. Two-stage drain efficiency versus input stage drain efficiency. The
second-stage drain efficiency is fixed to 70% (solid lines) and 60% (dashed
. The vertical lines indicate
lines). The parameter is the second-stage gain
approximate limits for PA efficiency in different classes of operation at
microwave frequency.
decrease in overall gain by the amount of gain compression of the first stage.
However, as the second-stage gain reaches higher values
(above 12 dB), changing the mode of operation of the first
stage from low efficiency (e.g., class A) to high efficiency (e.g.,
switched mode) results in a minor efficiency improvement
(less than 8%). Since this is always followed by considerable
decrease in the first-stage gain due to compression, one may
decide not to sacrify a few decibels of gain for a few-percent
efficiency improvement. Switched-mode PAs are highly nonlinear as compared to A/AB classes. A comprehensive study of
class-E linearity is given in [4].
Two-stage drain efficiency is independent of first-stage gain.
On the other hand, the two-stage PAE is a function of drain
efficiency and gain of both stages
Since the increase in the first-stage drain efficiency affects the
gain of the first stage, it is more convenient to analyze PAE by
as the reduction of PAE due to the addition of a driver stage.
Combining (2) and (3), a relationship between required driverstage PAE and the reduction of the output-stage PAE can be
expressed as [5]
, and
are the efficiency and
gain values of the driver and output stages, respectively. Fig. 3 is a graphical representation of (4) for
equal to 8, 11, 14, and 17 dB.
is 55%
Fig. 3. PAE versus PAE for
in both cases and
is either 7 dB (upper curve set) or 11 dB (lower curve set).
The horizontal lines indicate approximate limits for microwave PA efficiency of
different classes of operation.
two cases: a higher gain high-efficiency second stage
dB), and a lower gain high-ef(
dB). The
ficiency second stage (
parameter is the gain of the first stage (
, and
dB), with typical gain values for different classes of operation of microwave active devices, from deeply saturated
class E to linear class A, respectively. To maintain the PAE
of the two-stage amplifier very close to the second-stage PAE
%) the PAE of the first stage has to be above
36%. This can be easily achieved if the first stage operates in
AB class, resulting in minimal gain reduction. However, if the
second stage has smaller gain, but high efficiency, in order to
maintain PAE reduction at the same value (less than 2%) the
efficiency of the first stage has to be around 50%. This can be
achieved operating the first stage PA in deeper AB or B class
of operation.
The PAE plot in Fig. 3 reveals another property of two-stage
amplifiers: the overall PAE can actually be equal or even greater
than the second stage PAE. For example, for a low-gain highdB,
efficiency second stage (
%), if the PAE of the first stage is the same as the second
stage PAE, the overall PAE will remain the same.
are presented.
In this paper, two PAs that optimize
• The first is a hybrid PA with identical GaAs MESFET
active devices in both stages. A highly efficient second
stage is designed to operate in switched mode (class E).
The driver stage is designed using the same device in class
E but at a lower bias.
• The second is a monolithic PA with InP DHBT active
devices with different peripheries for driver and output
stages. The second stage operates in an alternative class
E, achieving large bandwidth [6], while the first stage is
designed to operate in AB class, maximizing the gain with
minimal decrease in overall PAE.
Common practice for cascading amplifier stages includes the
PAJIĆ et al.:
Fig. 4. Measured 10-GHz source (left) and load–pull (right) contours of constant P
(solid) and gain or (dashed). The active device is terminated with an
and the maximal are marked
“open” at 20 GHz. The experimentally determined optimal bias point is V = 1:55 V and V = 4:2 V. The maximal P
by “x” and “+,” respectively. Selected optimal source and load impedances (circles) are Z = (7:7 + j 12) and Z = (27:2 + j 25:8) . The calculated
optimal impedance for class-E mode Z at 10 GHz is shown.
cascading two balanced amplifiers, which provides isolation between separately designed stages due to the
matching provided by directional couplers;
• inserting a nonreciprocal element (isolator) between
• direct connection of the driver and output stages with an
interstage matching network.
The latter approach is followed in this paper, as it eliminates the
loss due to couplers/isolator, reduces the required real estate,
and allows a monolithically integrated circuit.
It is clear from the analysis in Figs. 2 and 3 that the efficiency
of the second stage should be maximized. Class-E operation is
chosen in this work since it requires slower devices than other
switched modes and it is relatively insensitive to parameter variations [7], [8].
A. Class-E Output Stage
Class-E theory applied to microwave amplifier design is presented in [1] and [9], assuming the active device is behaving
as an ideal switch. For the microwave class-E amplifier design,
a general-purpose GaAs MESFET (AFM04P2) manufactured
by Skyworks Solutions, Inc., Woburn, MA, is chosen. It has a
gate length of 0.25 m, with total gate periphery of 400 m and
of 30 GHz. According to the device specifications, the
MESFET is able to deliver around 21 dBm of output power at
18 GHz, with a gain of 9 dB, while operating in class-A mode.
Using given -parameters of the active device, a small-signal
model is derived and the output capacitance is estimated to be
pF. From the design formula given in [1]
and known output capacitance, the optimal class-E impedance is
calculated at 10 GHz:
. This assumes ideal
Fig. 5. (a) Output stage class-E PA. (b) Hybrid two-stage class-E PA after
interstage matching network tuning. Both PAs are fabricated on Rogers TMM6
substrate ( = 6; h = 0:635 mm, t = 35 m).
(“open”) termination of the active device output at all higher
harmonics. The operation of a realistic active device deviates
from the ideal case, mainly due to the finite switching time, finite ON and OFF resistances, and presence of numerous parasitics in the active device output (transistor pad inductances and
capacitances, mounting area parasitics, bond wire inductances,
etc.). The available (TOM2) nonlinear model for the MESFET
does not adequately model switched mode of operation, therefore, a harmonically terminated load–pull characterization was
performed in the neighborhood of the theoretically determined
load impedance. For the selected device, it is empirically determined [9] that it is sufficient to terminate the second harmonic
frequency for approximate class-E operation.
In the load– and source–pull measurements the reference
plane is set to include packaging parasitics due to bonding and
mounting. The resulting load and source-pull contours at 10
GHz are shown in Fig. 4. Based on impedances in Fig. 4, a
class-E output stage PA, Fig. 5(a), was designed on Rogers
m). No
TMM6 substrate (
additional post-production tuning was necessary. Measured
power sweep characteristics of the connectorized PA are shown
in Fig. 6. The input return loss for an input power of 13 dBm is
measured to be 16 dB.
of the switch voltage has to be equal to the dc drain supply
Due to the perfect harmonic termination in ideal class-E
mode, the power delivered to the output matching network is
is the real part of the optimal class-E load impedance
is the magnitude of the output
. Substituting
from (7) into (8), the power delivered to the matching network is found to be
Fig. 6. Measured power sweep characteristics of the output stage class-E PA
at 10 GHz for a bias point V = 1:55 V and V = 4:2 V.
Fig. 7. Equivalent class-E output circuit, assuming the transistor is an ideal
switch with a shunt output capacitance. The ideal RF choke provides a constant
and bias voltage V
for the transistor. The output matching
bias current I
network transforms the load resistance R into the optimal impedance Z
required for class-E mode of operation. It also provides ideal harmonic
terminations resulting in purely sinusoidal load current.
B. High-Efficiency Driver Stage
Fig. 2 shows the efficiency tradeoffs in drive-stage operating
mode choice. For this hybrid two-stage PA, a class-E driver
stage is chosen, using the same GaAs MESFET as the output
stage. However, a decrease in input power will cause a significant drop in the amplifier efficiency. This is a common problem
for all high-efficiency classes of operation. Nevertheless, it can
be shown that the bias point can be adjusted to maintain class-E
operation at lower output power levels. Consider the output circuit of a typical ideal class-E amplifier, shown in Fig. 7. From
the derivation presented in [1] the open-switch voltage is found
as the time integral of the current through the output capacitor,
under the assumption of soft turn-on and 50% current/voltage
duty cycles
is the average drain curwhere
is the angular switching frequency. If the dc supply
rent, and
voltage is provided through an ideal RF choke, the average value
If the output matching network is lossless, the output power
is equal to the power delivered to the resistive load
. Therefore, the voltage across the load is proportional to
. As a result, the output power of a class-E PA can be varied by varying
the bias with the following properties.
• The power can theoretically range between zero and maximal available power.
• For a realistic transistor, the drain bias should be kept
above threshold to avoid significant power gain degradation [10], giving a lower limit to the power range;
• The upper power range limit is given by the max V/I peak
handling capability of the device, which also depends on
the nonlinearity of the output capacitance [10].
• The optimal (ideal) efficiency is not affected when the
bias is varied. Namely, the transistor voltage and current
amplitudes change with bias voltage, but not their shape in
time domain. Since the waveform shape is responsible for
the high efficiency in class-E mode, the efficiency remains
the same.
• For the same reason, the optimal class-E load impedance
remains the same.
The lower power limitation is a practical constraint that can
be avoided by using a smaller periphery device for the driver
stage amplifier, which was not commercially available for the
MESFET used in this work. However, this method is used in
the monolithic PA presented in the next section, while the biascontrolled power method is used for the hybrid PA.
In order to select an optimal bias point an automatic
bias/power sweep measurement is performed. The required
output power of the driver stage is between 12–13 dBm. The
, and
contours for
dBm are
is not
shown in Fig. 8. This approach assumes that the
component of
a function of bias voltage. Although the
varies with drain bias [11] these variations are small in
the range of voltages chosen for the measurements in Fig. 8,
and efficiency remains high even for low drain bias voltages.
C. Two-Stage Switched-Mode Amplifier
The block diagram of the directly coupled two-stage amplifier
is shown in Fig. 1 and the fabricated two-stage hybrid amplifier
is shown in Fig. 5(b). The interstage matching network transforms the input impedance of the output stage into the optimal
PAJIĆ et al.:
Fig. 8. Bias/power sweep contours of the designed class-E PA for input power
(solid) and of 5 dBm at 10 GHz. Shown are contours of constant P
(dashed). Gain contours are omitted from the plot for the clarity and can be
and P . As a result of a compromise between these
inferred from the P
three parameters the bias point for the driver stage is selected (arrows): V =
1:3 V and V
= 1:8 V, resulting in expected G
7:5 dB, P
12:5 dBm and 0
Fig. 10.
Measured second and third harmonic power sweeps of the two-stage
Fig. 11. Frequency sweep of the two-stage amplifier characteristics. The P
is adjusted to maintain the maximal PAE at each frequency point.
Fig. 9. Measured power sweep of the two-stage switched-mode PA at 10 GHz.
= 1:3 V and V
= 1:8 V while
The bias point for the first stage is V
= 1:55 V and V
= 4:2 V.
the second stage is biased at V
class-E impedance for the first stage, and provides the second
harmonic termination. For the initial interstage matching netis used.
work design, the complex conjugate of
Results of power-sweep characterization of the optimized
two-stage PA are shown in Fig. 9. The data are measured for
connectorized amplifier. During the optimization process, the
fundamental frequency load impedance of the first stage is
slightly changed from the initial class-E value. Therefore, the
first stage operates in an alternative class-E mode, or perhaps
in deeply saturated AB class, with an “open” termination at the
second harmonic frequency. The two-stage amplifier has excellent input return loss of 18 dBc at the nominal input power
level of 4 dBm, and second and third harmonic levels of 41
and 25 dBc, respectively (Fig. 10). High suppression of the
second harmonic in the output signal is a result of the harmonic
traps applied in both amplifier stages. The intermodulation
products are measured with a two-tone test signal at 10 GHz
with 100-kHz frequency spacing. As expected, the class-E PA
is nonlinear with third-, fifth-, and seventh-order products of
11, 19.7, and 32 dBc, respectively. The frequency sweep
of amplifier parameters for maximum PAE is shown in Fig. 11.
Table I summarizes measured performance of the two-stage
PA. The performance comparison of the two stages when characterized separately is given in Table II. The output power of the
first stage is estimated.
From the given data it can be concluded that the main
amplifier parameters of both stages are preserved after direct
Fig. 12.
Monolithic InP DHBT class-E output stage.
A. Active Device
The device technology utilized for the MMIC class-E amplifier has been detailed in [12] and [13]. Briefly, the device
is based on NGST indium-phosphide double heterojunction
bipolar transistor (InP DHBT) technology and possesses many
essential characteristics for high-efficiency amplifier operation,
including low offset voltage, low knee voltage, high breakdown
voltage, and high gain. Class-E operating characteristics at
-band of a typical 1.5 m 30 m 4 emitter finger unit
cell are detailed in [6] and [12]. Of primary importance is the
high gain capability of the device, possessing
values of 80 and 150 GHz, respectively. The device is capable
of 16-dB linear gain at 20 GHz. Higher gain translates to
reduced input signal drive requirements in order to obtain
switching behavior from the active device, as is required for
class-E operation.
A modified Gummel–Poon model was used to simulate the
large-signal performance of the DHBT device. Model parameters were fit to measured dc and -parameter data across various bias conditions. Device model verification, under class-E
operating conditions, is presented in [12]. The model appears to
predict large-signal performance with reasonable accuracy.
B. Two-Stage Amplifier Design
For many pulsed radar applications, prime power is limited,
leading to a need for highly efficient transmitter amplifiers.
However, amplitude flatness is also required in order to keep
Measured power characteristics of the class-E output stage at V =
= 4 V. (a) Frequency sweep at P = 13 dBm. (b) Input
power sweep at 8 GHz.
Fig. 13.
0:55 V and V
range side lobes below an acceptable level. For this investigation, a two-stage MMIC class-E amplifier was designed to
provide 24 0.5 dBm ( 250 mW) output power from 8 to
10 GHz, while maintaining high PAE. In order to maintain the
required amplitude flatness, maximum PAE cannot be maintained over the entire bandwidth as compared to narrow-band
amplifier performance.
The class-E output stage consists of two 1.5 m 30 m 4
finger devices combined in parallel, resulting in a total emitter
area of 360 m . The devices are combined reactively, taking
care to provide odd-mode instability suppression resistors
PAJIĆ et al.:
Fig. 14. Monolithic high-efficiency InP DHBT two-stage PA.
between the base and collector of each transistor. Based upon
the device model and estimates of device output resistance
and capacitance (
pF), an output
matching network provides adequate high-impedance terminations over the range of second harmonic values [6], while
simultaneously providing the required fundamental matching
over the frequency band of interest. A single-stage amplifier
is designed to test the output stage performance by providing
input matching to maximize gain. A photograph of the designed
single-stage class-E monolithic PA is shown in Fig. 12.
Measured power results for the output stage matched to 50
are shown in Fig. 13. Greater than 43% PAE and 10-dB gain are
maintained over a 7.5–10-GHz bandwidth. A maximum PAE
of 55% with a corresponding 11.7 dB of gain was achieved at
8 GHz.
Based on the analysis given in Section II, in order to maintain
a high overall gain, a class-AB mode of operation is deemed
appropriate for the driver stage. The active component for the
driver stage was chosen to be 1.5 m 30 m 2 finger device
with a total emitter area of 90 m , providing a 4 : 1 ratio in
emitter area between the driver stage and output stage. With this
ratio, a PAE above 40% for the driver stage is maintained, while
simultaneously providing adequate power to push the output
stage deep into compression as required for switched-mode
The driver and output stages are combined utilizing appropriate impedance transforming networks. The main function
of the interstage matching network is to transform the input
impedance of the output stage to the required output impedance
of the driver stage. The input of the driver stage is matched for
maximum gain. Bias for both stages is provided on chip.
Nonlinear modeling was utilized extensively to obtain the
required output power flatness, while maintaining high PAE,
over the frequency range of interest. A photograph of the
two-stage class-E monolithic PA is shown in Fig. 14. Measured
power results are shown in Fig. 15. Greater than 40% PAE is
maintained over a 7.7–10.5-GHz bandwidth with a maximum
of 52% at 8 GHz. The gain of the two-stage amplifier ranges
from 24.6 to 23.7 dB over an 8–10-GHz bandwidth.
Fig. 15. Measured power characteristics of the two-stage class-E MMIC
= 0:62 V, V
= 4 V, V
= 0:55 V, and
power amplifier at V
= 4 V. (a) Frequency sweep at P = 0 dBm. (b) Input power sweep
at 8 GHz.
Comparing the single-stage to the two-stage amplifier an average reduction in PAE of only 3% over 8–10 GHz is observed,
with a maximum reduction of 5% at 8.5 GHz. However, over
the same bandwidth, the average gain improves from 11.1 dB,
for the single-stage amplifier, to 24.2 dB for the two-stage amplifier. Characteristics of single-stage and two-stage monolithic
PAs at 8.5 GHz are compared in Table III.
This paper has presented the design of two-stage directly cascaded high-efficiency -band PAs. The following two methods
are employed to maintain high efficiency while optimizing gain:
1) using the same device for both stages of a hybrid
MESFET class-E PA with backed-off first-stage bias;
2) using a smaller periphery class-AB driver PA with a
class-E larger-periphery device for the second stage in a
monolithic high-efficiency PA fabricated by NGST.
Table IV shows a comparison of measured results for the two
1) Both PAs demonstrate around 52% PAE and well-preserved individual-stage characteristics. Note that the the
measurements of the hybrid PA include connector loss,
while the monolithic PA was measured using a probe station.
2) The compressed gain of the monolithic PA is higher due
to the higher linear gain of the HBT devices compared to
the MESFET gain.
3) Due to the larger , InP DHBTs are well suited for this
mode of operation.
4) The monolithic PA is designed using harmonic balance
% with minimal gain
simulations to have a
and power variations over 31% bandwidth. In contrast,
the hybrid PA is designed using basic theory augmented
by load–pull at a single frequency. Although not designed
to be broadband, it exhibits a 15% bandwidth for PAE
The general conclusions that can be drawn as a result of
this work, including some recommendations for two-stage
efficiency-optimized PA design, are as follows.
1) Although the driver stage consumes less power than the
output stage, it is important to optimize its efficiency, as
it directly determines the total PAE.
2) The class of operation of the driver stage should be determined by the gain requirement: for higher gain, class AB
will give optimal overall efficiency performance, while
for highest overall efficiency, class E is recommended.
3) If different periphery devices are not available, it is possible to achieve very high total efficiency by bias adjustment of the driver stage, due to the unique properties of
the class-E mode of operation.
4) Efficiency is optimized when the two amplifier stages are
directly cascaded with an interstage network. The design
of this network is not straightforward due to the bilateral
character of both stages.
5) Hybrid and monolithic versions with different device
types (e.g., MESFET and HBT in this study) can give
comparable efficiency results if all parasitics in the hybrid
design are modeled appropriately.
6) The efficiency-optimized two-stage PA is nonlinear. Wellknown linearization techniques, such as envelope elimination and restoration (EER) [4], can be modified to apply
to two stages.
In summary, this paper experimentally demonstrated at
-band that the total efficiency of a two-stage PA can approach
that of a high-efficiency output stage, both for hybrid and
monolithic amplifiers. Such amplifiers are good candidates
for active antenna array transmit modules in radar, as well as
communication transmitters in which the signals have constant
envelope. By adding dynamic bias control [4], these amplifiers
can also be used for signals with varying envelopes.
The authors are grateful to A. Gutierrez, D. Sawdai,
E. Kaneshiro, W. Lee, and A. Oki, all of Northrop Grumman
Space Technology, Redondo Beach, CA, for monolithic PA
fabrication and many useful discussions.
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Srdjan Pajić (S’02) received the Dipl. Ing. degree
from the University of Belgrade, Belgrade, Serbia
and Montenegro, in 1995, and the Ph.D. degree
in electrical and computer engineering from the
University of Colorado, Boulder, in 2005.
From 1995 to 2000, he was a Research and Design
Engineer with IMTEL Microwaves, Belgrade, Serbia
and Montenegro, where he was involved with the development of PAs for radio and TV broadcast systems. His research interests include high-efficiency
microwave PAs for active antennas, linear PAs for
wireless communications, and spatial power-combining techniques.
Narisi Wang (S’00) received the B.S. degree in
electrical engineering from the Beijing University
of Posts and Telecoms, Beijing, China, in 1999,
the M.S. degree in electrical engineering from
Colorado State University, Fort Collins, in 2001, and
is currently working toward the Ph.D. degree at the
University of Colorado at Boulder. Her master’s research concerned mathematical modeling of coaxial
probe crack detection. Her doctoral research is in
dynamic biasing of high-efficiency microwave PAs.
Paul M. Watson (M’01) received the B.S. and M.S.
degrees from the University of Utah, Salt Lake City,
in 1991 and 1993, respectively, and the Ph.D. degree
from the University of Colorado at Boulder, in 1998,
all in electrical engineering.
He is currently a Research Engineer with the
Sensors Directorate, Air Force Research Laboratory,
Wright-Patterson AFB, OH. His research interests include microwave/millimeter-wave PAs and
low-noise amplifier techniques.
Tony K. Quach (M’98) received the B.S.E.E. degree from Wright State University, Dayton, OH, in
1988, and the M.S.E.E. degree from the University
of Dayton, Dayton, OH, in 1994.
Since 1989, he has been involved with the research
and development of solid-state microwave devices
and integrated circuits at the Sensors Directorate,
Air Force Research Laboratory, Wright-Patterson
AFB, OH. He has been involved in the development
of ultrahigh-efficiency PAs and low-power-drain/robust low-noise amplifiers for space-based radar
applications. He is currently the Principal Investigator of the RFIC project
for the Air Force Research Laboratory, engaging in the demonstration of
receiver-on-a-chip for future U.S. Department of Defense phase array systems.
He has authored or coauthored over 50 publications. He holds 12 patents on
microwave device fabrication.
Zoya Popović (S’86–M’90–SM’99–F’02) received
the Dipl. Ing. degree from the University of Belgrade,
Belgrade, Serbia, in 1985, and the Ph.D. degree from
the California Institute of Technology, Pasadena, in
She is currently a Full Professor of electrical and
computer engineering at the University of Colorado,
Boulder. Her research interests include microwave
and millimeter-wave quasi-optical techniques,
high-efficiency microwave circuits, intelligent RF
front ends, smart antenna arrays, RF-optical techniques, and wireless powering of sensor arrays and implanted sensors. She
has coauthored (with her father) Introductory Electromagnetics (Upper Saddle
River, NJ: Prentice-Hall, 2000) for the junior-level core course for electrical
and computer engineering students.
Dr. Popović was the recipient of the 1993 IEEE Microwave Prize presented
by the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) for the
best journal paper. She was the NSF Presidential Faculty Fellow in 1993, and received the 1996 URSI Issac Koga Gold Medal and the 2001 ASEE/HP Terman
Award for combined teaching and research excellence. In 2000, she spent six
months at the Technical University of Munich as a recipient of the Humboldt Research Award for Senior U.S. Scientists from the German Alexander von Humboldt Stiftung.
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