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WM8958

Multi-Channel Audio Hub CODEC for Smartphones

DESCRIPTION FEATURES

The WM8958

[1]

is a highly integrated ultra-low power hi-fi

CODEC designed for smartphones and other portable devices rich in multimedia features.

An integrated stereo class D/AB speaker driver and class W headphone driver minimize power consumption during audio playback.

The device requires only two voltage supplies, with all other internal supply rails generated from integrated LDOs.

Stereo full duplex asynchronous sample rate conversion and multi-channel digital mixing combined with powerful analogue mixing allow the device to support a huge range of different architectures and use cases.

A multiband compressor and programmable parametric EQ provide volume maximisation and speaker compensation in the digital playback paths. The dynamic range controller can be used in record or playback paths for maintaining a constant signal level, maximizing loudness and protecting speakers against overloading and clipping.

A smart digital microphone interface provides power regulation, a low jitter clock output and decimation filters for up to four digital microphones. Microphone activity detection with interrupt is available. Impedance sensing and measurement is provided for external accessory / push-button detection.



24-bit 4-channel hi-fi DAC and 2-channel hi-fi ADC



100dB SNR during DAC playback (‘A’ weighted)



Smart MIC interface

- Power, clocking and data input for up to four digital MICs

- High performance analogue MIC interface

- MIC activity detect & interrupt allows processor to sleep



2W stereo (2 x 2W) class D/AB speaker driver



Capless Class W headphone drivers

- Integrated charge pump

- 5.3mW total power for DAC playback to headphones



4 Line outputs (single-ended or differential)



BTL Earpiece driver



Digital audio interfaces for multi-processor architecture

- Asynchronous stereo duplex sample rate conversion

- Powerful mixing and digital loopback functions

 ReTune

TM

Mobile 5-band, 6-channel parametric EQ



Multiband compressor and dynamic range controller



Dual FLL provides all necessary clocks

- Self-clocking modes allow processor to sleep

- All standard sample rates from 8kHz to 96kHz



Active noise reduction circuits

- DC offset correction removes pops and clicks

- Ground loop noise cancellation



Integrated LDO regulators



72-ball W-CSP package (4.516 x 4.258 x 0.698mm)

APPLICATIONS

Fully differential internal architecture and on-chip RF noise filters ensure a very high degree of noise immunity. Active ground loop noise rejection and DC offset correction help prevent pop noise and suppress ground noise on the headphone outputs.



Smartphones and music phones navigation

 Tablets

 eBooks



Portable Media Players

WOLFSON MICROELECTRONICS plc Product Brief, August 2012, Rev 3.2

[1] This product is protected by Patents US 7,622,984, US 7,626,445,US 7,765,019 and GB 2,432,765

To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Copyright

2012 Wolfson Microelectronics plc

WM8958

Pre-Production

TABLE OF CONTENTS

DESCRIPTION ....................................................................................................... 1

 

FEATURES ............................................................................................................ 1

 

APPLICATIONS ..................................................................................................... 1

 

TABLE OF CONTENTS ......................................................................................... 2

 

PIN CONFIGURATION .......................................................................................... 3

 

ORDERING INFORMATION .................................................................................. 3

 

PIN DESCRIPTION ................................................................................................ 4

 

ABSOLUTE MAXIMUM RATINGS ........................................................................ 7

 

RECOMMENDED OPERATING CONDITIONS ..................................................... 8

 

DEVICE DESCRIPTION ........................................................................................ 9

 

RECOMMENDED EXTERNAL COMPONENTS .................................................. 11

 

PACKAGE DIMENSIONS .................................................................................... 12

 

IMPORTANT NOTICE ......................................................................................... 13

 

ADDRESS: ..................................................................................................................... 13 

REVISION HISTORY ........................................................................................... 14

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PIN CONFIGURATION

WM8958

ORDERING INFORMATION

ORDER CODE

WM8958ECS/R

TEMPERATURE RANGE PACKAGE MOISTURE

SENSITIVITY LEVEL

-40

C to +85C 72-ball

(Pb-free, Tape and reel)

PEAK SOLDERING

TEMPERATURE

MSL1 260

C

Note:

Reel quantity = 5000 w

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PIN DESCRIPTION

A description of each pin on the WM8958 is provided below.

Note that a table detailing the associated power domain for every input and output pin is provided on the following page.

Note that, where multiple pins share a common name, these pins should be tied together on the PCB.

PIN NO NAME TYPE DESCRIPTION

Audio interface 1 ADC digital audio data

Audio interface 2 ADC digital audio data

2-wire (I2C) address select

D7, E6 AGND

Supply Analogue ground (Return path for AVDD1, AVDD2 and LDO1VDD)

Analogue core supply / LDO1 Output

Output

Bandgap reference, analogue class D and FLL supply

F2 BCLK1 Audio interface 1 bit clock

G3 BCLK2 Audio interface 2 bit clock

Charge pump fly-back capacitor pin

Charge pump fly-back capacitor pin

Charge pump ground (Return path for CPVDD)

Charge pump supply

Charge pump negative supply decoupling pin (HPOUT1L, HPOUT1R)

Charge pump positive supply decoupling pin (HPOUT1L, HPOUT1R)

Audio interface 1 DAC digital audio data

E4 DACDAT2 Audio interface 2 DAC digital audio data

Digital buffer (I/O) supply (core functions and Audio Interface 1)

Digital buffer (I/O) supply (for Audio Interface 2)

Digital buffer (I/O) supply (for Audio Interface 3)

Digital core supply / LDO2 output

Output

Digital ground (Return path for DCVDD, DBVDD1, DBVDD2, DBVDD3)

Digital MIC clock output

H1 GPIO1/ General Purpose pin GPIO 1 /

ADCLRCLK1 Audio interface 1 ADC left / right clock

F5 GPIO10/ General Purpose pin GPIO 10 /

LRCLK3 Audio interface 3 left / right clock

E5 GPIO11/

General Purpose pin GPIO 11 /

BCLK3 Audio interface 3 bit clock

H3 GPIO6/

General Purpose pin GPIO 6 /

ADCLRCLK2

Audio interface 2 ADC left / right clock

G4 GPIO8/

General Purpose pin GPIO 8 /

DACDAT3

Audio interface 3 DAC digital audio data

H4 GPIO9/ General Purpose pin GPIO 9 /

ADCDAT3

Audio interface 3 ADC digital audio data w

HPOUT1L and HPOUT1R ground loop noise rejection feedback

Left headphone output

Right headphone output

Earpiece speaker inverted output

Earpiece speaker non-inverted output

Left channel single-ended MIC input /

Left channel negative differential MIC input

Left channel line input /

Left channel positive differential MIC input

Right channel single-ended MIC input /

Right channel negative differential MIC input

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PIN NO NAME

DMICDAT1

DMICDAT2

TYPE

Digital Input

Digital Input

DESCRIPTION

Right channel line input /

Right channel positive differential MIC input

Left channel line input /

Left channel negative differential MIC input /

Digital MIC data input 1

Left channel line input /

Left channel positive differential MIC input /

Mono differential negative input (RXVOICE -)

Right channel line input /

Right channel negative differential MIC input /

Digital MIC data input 2

Left channel line input /

Left channel positive differential MIC input /

Mono differential positive input (RXVOICE +)

Enable pin for LDO1

Supply for LDO1

Enable pin for LDO2

Negative mono line output / Positive left or right line output

Positive mono line output / Positive left line output

Negative mono line output / Positive left or right line output

Positive mono line output / Positive left line output

Line output ground loop noise rejection feedback

D4 LRCLK1 Audio interface 1 left / right clock

H2 LRCLK2 Audio interface 2 left / right clock

Master clock 1

Master clock 2

Microphone bias 1

Microphone bias 2

Microphone & accessory sense input

Analogue ground

Control interface clock input

G2 SDA

Control interface data input and output / acknowledge output

Ground for speaker driver (Return path for SPKVDD1)

Ground for speaker driver (Return path for SPKVDD2)

Mono / Stereo speaker mode select

Left speaker negative output

Left speaker positive output

Right speaker negative output

Right speaker positive output

Supply for speaker driver 1 (Left channel)

Supply for speaker driver 2 (Right channel)

Midrail voltage decoupling capacitor

Bandgap reference decoupling capacitor

WM8958

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The following table identifies the power domain and ground reference associated with each of the input / output pins.

PIN NO NAME POWER DOMAIN GROUND DOMAIN

CPGND

CPGND

MICBIAS1 (DMICDAT1)

MICBIAS1 (DMICDAT2)

AGND

AGND (IN2RN) or

DGND (DMICDAT2) w

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WM8958

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.

Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30

C / 85% Relative Humidity. Not normally stored in moisture barrier bag.

MSL2 = out of bag storage for 1 year at <30

C / 60% Relative Humidity. Supplied in moisture barrier bag.

MSL3 = out of bag storage for 168 hours at <30

C / 60% Relative Humidity. Supplied in moisture barrier bag.

The Moisture Sensitivity Level for each package type is specified in Ordering Information.

Supply voltages (AVDD1, DBVDD2, DBVDD3)

Supply voltages (AVDD2, DCVDD, DBVDD1)

Supply voltages (CPVDD)

Supply voltages (SPKVDD1, SPKVDD2, LDO1VDD)

Voltage range digital inputs (DBVDD1 domain)

Voltage range digital inputs (DBVDD2 domain)

Voltage range digital inputs (DBVDD3 domain)

Voltage range digital inputs (DMICDATn)

Voltage range analogue inputs (AVDD1 domain)

Voltage range analogue inputs (MICDET, LINEOUTFB)

Voltage range analogue inputs (HPOUT1FB)

Ground (DGND, CPGND, SPKGND1, SPKGND2, REFGND, HP2GND)

Operating temperature range, T

A

Junction temperature, T

JMAX

Storage temperature after soldering

-0.3V +4.5V

-0.3V +2.5V

-0.3V +2.2V

-0.3V +7.0V

AGND -0.3V

AGND -0.3V

DBVDD1 +0.3V

DBVDD2 +0.3V

AGND -0.3V

AGND - 0.3V

AGND -0.3V

AGND - 0.3V

AGND - 0.3V

DBVDD3 +0.3V

AVDD1 + 0.3V

AVDD1 +0.3V

AVDD1 + 0.3V

AGND + 0.3V

AGND - 0.3V AGND + 0.3V

-40ºC +85ºC

-40ºC +150ºC

-65ºC +150ºC w

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RECOMMENDED OPERATING CONDITIONS

Digital supply range (Core)

See notes 7,8

Digital supply range (I/O)

Digital supply range (I/O)

Analogue supply 1 range

See notes 3,4,5,6

Analogue supply 2 range

Charge Pump supply range

Speaker supply range

LDO1 supply range

Ground

DBVDD2, DBVDD3

AVDD1

1.62 1.8 3.6 V

2.4 3.0 3.3 V

LDO1VDD 2.7 5.0 5.5 V

DGND, AGND, CPGND,

SPKGND1, SPKGND2,

REFGND, HP2GND

0 V

All supplies 1

s

Power supply rise time

(notes 6, 7 and 8)

Operating temperature range T

A

-40

Notes:

1. Analogue, digital and speaker grounds must always be within 0.3V of AGND..

2. There is no power sequencing requirement; the supplies may be enabled in any order.

3. AVDD1 must be less than or equal to SPKVDD1 and SPKVDD2.

4. An internal LDO (powered by LDO1VDD) can be used to provide the AVDD1 supply.

5. When AVDD1 is supplied externally (not from LDO1), the LDO1VDD voltage must be greater than or equal to AVDD1.

6. The WM8958 can operate with AVDD1 tied to 0V; power consumption may be reduced, but the analogue audio functions will not be supported.

7. An internal LDO (powered by DBVDD1) can be used to provide the DCVDD supply.

8. When DCVDD is supplied externally (not from LDO2), the DBVDD1 voltage must be greater than or equal to DCVDD.

9. DCVDD and AVDD1 minimum rise times do not apply when these domains are powered using the internal LDOs.

10. The specified minimum power supply rise times assume a minimum decoupling capacitance of 100nF per pin.

However, Wolfson strongly advises that the recommended decoupling capacitors are present on the PCB and that appropriate layout guidelines are observed (see “Applications Information” section).

11. The specified minimum power supply rise times also assume a maximum PCB inductance of 10nH between decoupling capacitor and pin. w

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WM8958

DEVICE DESCRIPTION

The WM8958 is a low power, high quality audio codec designed to interface with a wide range of processors and analogue components. A high level of mixed-signal integration in a very small footprint makes it ideal for portable applications such as mobile phones. Fully differential internal architecture and on-chip RF noise filters ensure a very high degree of noise immunity.

Three sets of audio interface pins are available in order to provide independent and fully asynchronous connections to multiple processors, typically an application processor, baseband processor and wireless transceiver. Any two of these interfaces can operate totally independently and asynchronously while the third interface can be synchronised to either of the other two and can also provide ultra low power loopback modes to support, for example, wireless headset voice calls.

Four digital microphone input channels are available to support advanced multi-microphone applications such as noise cancellation. An integrated microphone activity monitor is available to enable the processor to sleep during periods of microphone inactivity, saving power.

Four DAC channels are available to support use cases requiring up to four simultaneous digital audio streams to the output drivers.

Eight highly flexible analogue inputs allow interfacing to up to four microphone inputs (single-ended or differential), plus multiple stereo or mono line inputs. Connections to an external voice CODEC, FM radio, line input, handset MIC and headset MIC are all fully supported. Signal routing to the output mixers and within the CODEC has been designed for maximum flexibility to support a wide variety of usage modes. A ‘Direct Voice’ path from a voice CODEC directly to the Speaker or Earpiece output drivers is included.

Nine analogue output drivers are integrated, including a stereo pair of high power, high quality

Class D/AB switchable speaker drivers; these can support 2W each in stereo mode. It is also possible to configure the speaker drivers as a mono output, giving enhanced performance. A mono earpiece driver is provided, providing output from the output mixers or from the low-power differential ‘Direct

Voice’ path.

One pair of ground-referenced headphone outputs is provided; these are powered from an integrated

Charge Pump, enabling high quality, power efficient headphone playback without any requirement for

DC blocking capacitors. A DC Servo circuit is available for DC offset correction, thereby suppressing pops and reducing power consumption. Four line outputs are provided, with multiple configuration options including 4 x single-ended output or 2 x differential outputs. The line outputs are suitable for output to a voice CODEC, an external speaker driver or line output connector. Ground loop feedback is available on the headphone outputs and the line outputs, providing rejection of noise on the ground connections. All outputs have integrated pop and click suppression features.

Internal differential signal routing and amplifier configurations have been optimised to provide the highest performance and lowest possible power consumption for a wide range of usage scenarios, including voice calls and music playback. The speaker drivers offer low leakage and high PSRR; this enables direct connection to a Lithium battery. The speaker drivers provide eight levels of AC and DC gain to allow output signal levels to be maximised for many commonly-used SPKVDD/AVDD1 combinations.

The ADCs and DACs are of hi-fi quality, using a 24-bit low-order oversampling architecture to deliver optimum performance. A flexible clocking arrangement supports mixed sample rates, whilst integrated ultra-low power dual FLLs provide additional flexibility. A high pass filter is available in all ADC and digital MIC paths for removing DC offsets and suppressing low frequency noise such as mechanical vibration and wind noise. A digital mixing path from the ADC or digital MICs to the DAC provides a sidetone of enhanced quality during voice calls. DAC soft mute and un-mute is available for pop-free music playback.

The integrated Multiband Compressors (MBC), Dynamic Range Controllers (DRC) and ReTune

TM

Mobile 5-band parametric equaliser (EQ) provide further processing capability of the digital audio paths. The MBC enables the loudness of the digital playback path to be maximised without overdriving the loudspeakers. The RMS Limiter within the MBC function enables the maximum signal level to be matched to the application requirements and/or power rating of the loudspeaker. The DRC provides compression and signal level control to improve the handling of unpredictable signal levels.

‘Anti-clip’ and ‘quick release’ algorithms improve intelligibility in the presence of transients and impulsive noises. The EQ provides the capability to tailor the audio path according to the frequency characteristics of an earpiece or loudspeaker, and/or according to user preferences. w

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WM8958

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I

The WM8958 has highly flexible digital audio interfaces, supporting a number of protocols, including

2

S, DSP, MSB-first left/right justified, and can operate in master or slave modes. PCM operation is supported in the DSP mode. A-law and

-law companding are also supported. Time division multiplexing (TDM) is available to allow multiple devices to stream data simultaneously on the same bus, saving space and power. The four digital MIC and ADC channels and four DAC channels are available via four TDM channels on Digital Audio Interface 1 (AIF1).

A powerful digital mixing core allows data from each TDM channel of each audio interface and from the ADCs and digital MICs to be mixed and re-routed back to a different audio interface and to the 4

DAC output channels. The digital mixing core can operate synchronously with either Audio Interface 1 or Audio Interface 2, with asynchronous stereo full duplex sample rate conversion performed on the other audio interface as required.

The system clock (SYSCLK) provides clocking for the ADCs, DACs, DSP core, digital audio interface and other circuits. SYSCLK can be derived directly from one of the MCLK1 or MCLK2 pins or via one of two integrated FLLs, providing flexibility to support a wide range of clocking schemes, including self-clocking FLL modes. Typical portable system MCLK frequencies, and sample rates from 8kHz to

96kHz are all supported. A low frequency (eg. 32.768kHz) clock can be used as the input reference to the FLLs, providing further flexibility. Automatic configuration of the clocking circuits is available, derived from the sample rate and from the MCLK / SYSCLK ratio.

The WM8958 uses a standard 2-wire control interface, providing full software control of all features, together with device register readback. An integrated Control Write Sequencer enables automatic scheduling of control sequences; commonly-used signal configurations may be selected using readyprogrammed sequences, including time-optimised control of the WM8958 pop suppression features. It is an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs.

Unused circuitry can be disabled under software control, in order to save power; low leakage currents enable extended standby/off time in portable battery-powered applications.

Versatile GPIO functionality is provided, with support for button/accessory detect inputs, or for clock, system status, or programmable logic level output for control of additional external circuitry. Interrupt logic, status readback and de-bouncing options are supported within this functionality. w

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RECOMMENDED EXTERNAL COMPONENTS

WM8958

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WM8958

PACKAGE DIMENSIONS

Pre-Production

B: 72 BALL W-CSP PACKAGE 4.516

X

4.258

X

0.698 mm BODY, 0.50 mm BALL PITCH

DETAIL 1 g A2

2

A

9 8 7 6 5 4 3 2 1

A

B

C

4

A1

CORNER

D

E

F

G e

5

E1

H

DETAIL 2 e ddd

M

Z A B

D1

BOTTOM VIEW

2 X

2 X aaa B aaa A f1

6

D

TOP VIEW

SOLDER BALL

DM119.A

A

E

B bbb Z h f2

1

Z ccc Z

A1

DETAIL 2

Symbols

A

A1

A2

D

D1

E

E1 e f1 f2 g

MIN

0.658

0.206

0.418

4.491

4.233

0.246

0.367

Dimensions (mm)

NOM

0.698

0.242

0.434

4.516

4.00 BSC

4.258

3.50 BSC

0.50 BSC

MAX

0.738

0.278

0.450

4.541

4.283

NOTE

5

8

9

h aaa bbb ccc

0.264

0.022

0.314

0.025

0.060

0.030

0.364

ddd

0.015

NOTES:

1. PRIMARY DATUM -Z- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.

2. THIS DIMENSION INCLUDES STAND-OFF HEIGHT ‘A1’ AND BACKSIDE COATING.

3. A1 CORNER IS IDENTIFIED BY INK/LASER MARK ON TOP PACKAGE.

4. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY.

5. ‘e’ REPRESENTS THE BASIC SOLDER BALL GRID PITCH.

6. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

7. FOLLOWS JEDEC DESIGN GUIDE MO-211-C.

8. f1 = NOMINAL DISTANCE OF BALL CENTRE TO DIE EDGE X AXIS (AS PER POD) – APPLICABLE TO ALL CORNERS OF DIE.

9. f2 = NOMINAL DISTANCE OF DIE CENTRE TO DIE EDGE IN Y AXIS (AS PER POD) – APPLICABLE TO ALL CORNERS OF DIE.

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IMPORTANT NOTICE

Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.

Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.

Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.

Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.

In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.

Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.

Any use of products by the customer for such purposes is at the customer’s own risk.

Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute

Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.

Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.

Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.

ADDRESS:

Wolfson Microelectronics plc

26 Westfield Road

Edinburgh

EH11 2QB

United Kingdom

Tel :: +44 (0)131 272 7000

Fax :: +44 (0)131 272 7001

Email :: [email protected]

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WM8958

REVISION HISTORY

DATE REV

27/09/10 2.0 Initial

14/10/10 2.1

Pre-Production

DESCRIPTION OF CHANGES

Tablets, EBooks and PMP added to Applications

04/04/11 2.2

07/04/11 3.0

04/10/11 3.1

25/04/12 3.1

25/04/12 3.1

25/04/12 3.1

25/04/12 3.1

25/04/12 3.1

09/08/12 3.2

2W Stereo (into 4ohms) now specified.

Noted RF suppression on analogue inputs.

Reel order quantity updated

Revision updated to reflect datasheet revision / production status change

Pin Description table re-ordered (by Pin Name), noting that any pins with a common name (eg.

AGND) should be tied together on the PCB.

Added Table of Contents

Front page updated

Power domain table added, p6

Additional details in Absolute Maximum Ratings.

Recommended Operating Conditions updated

Device Description, 10 th

para updated.

Package Diagram changed to DM119.A w

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