RD151TS3312ARP RD151TS3322ARP Datasheet

RD151TS3312ARP RD151TS3322ARP Datasheet
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RD151TS3312ARP, RD151TS3322ARP
Spread Spectrum Clock for EMI Solution
REJ03D0793-0100
Rev.1.00
May 11, 2006
Description
RD151TS3312ARP and RD151TS3322ARP is a high-performance Spread Spectrum Clock generator. It is suitable for
EMI solution of electric systems.
Features
• Supports 10 MHz to 20 MHz operations. Multiple rate (XIN: SSCOUT) = 1: 1
Input frequency 10 MHz to 20 MHz
• Spread spectrum modulation ; RD151TS3312ARP : ±1.5%, ±0.5% (Central spread modulation)
RD151TS3322ARP : –3.0%, –1.0% (Down spread modulation)
Key Specifications
•
•
•
•
•
Supply voltages: VDD = 3.3 V ±0.3 V
Cycle to cycle jitter = ±100 ps typ.
Clock output duty cycle = 50 ±5%
Output slew rate = 0.7 V/ns typ.
Ordering Information
Part Name
RD151TS3312ARPH0
RD151TS3322ARPH0
Package Code
(Previous Code)
Package Type
SOP-8 pin
(JEDEC)
PRSP0008DD-C
(FP-8DCV)
Package
Abbreviation
RP
Taping Abbreviation
(Quantity)
H (2,500 pcs / Reel)
Block Diagram
VDD
GND
NC
XIN
R = 1 MΩ
OSC
1/M
Synthesizer
XOUT
1/N
SSC Modulator
SEL
R = 350 kΩ
SSN
R = 350 kΩ
Rev.1.00 May 11, 2006 page 1 of 8
Mode Control
SSCOUT
RD151TS3312ARP, RD151TS3322ARP
Pin Arrangement
XIN
1
8
VDD
XOUT
2
7
SEL
NC
3
6
SSCOUT
SSN
4
5
GND
(Top view)
Pin Descriptions
Pin name
GND
VDD
NC
SSCOUT
XIN
XOUT
SEL
No.
5
8
3
6
1
2
7
Type
Ground
Power
NC
Output
Input
Output
Input
SSN
4
Input
Description
GND pin
Power supply pin.
Don’t connect any VDD or GND.
Spread spectrum modulated clock output.
Oscillator input.
Oscillator output.
SSC% mode select pin. LVCMOS level input.
Pull-down by internal resistor (350 kΩ).
SSC ON/OFF select pin. LVCMOS level input.
Pull–down by internal resistor (350 kΩ).
SSC Function Table
STB
0
0
1
1
Note:
SEL
0
1
0
1
RD151TS3312ARP(Central spread)
±1.5%*1
±0.5%
RD151TS3322ARP(Down spread)
–3.0%*1
–1.0%
OFF
OFF
1. ±1.5%(TS3312ARP) / -3.0%(TS3322ARP) SSC is selected for default by internal pull-down resistors.
Clock Frequency Table
PRODUCT
RD151TS3312ARP
RD151TS3322ARP
Rev.1.00 May 11, 2006 page 2 of 8
XIN(MHz)
10 to 20
10 to 20
SSCOUT(MHz)
10 to 20
10 to 20
Multiply rate (XIN: SSCOUT)
1:1
1:1
RD151TS3312ARP, RD151TS3322ARP
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Output voltage *1
Input clamp current
Output clamp current
Continuous output current
Maximum power dissipation
Storage temperature
Symbol
VDD
VI
VO
IIK
IOK
IO
Ratings
–0.5 to 4.6
–0.5 to 4.6
–0.5 to VDD+0.5
–50
–50
±50
0.7
–65 to +150
Tstg
Unit
V
V
V
mA
mA
mA
W
°C
Conditions
VI < 0
VO < 0
VO = 0 to VDD
Ta = 55°C (in still air)
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
Recommended Operating Conditions
Item
Supply voltage
Symbol
VDD
Min
3.0
Typ
3.3
Max
3.6
Unit
V
VIH
–0.3
0.7×VDD
—
—
VDD+0.3
VDD+0.3
V
V
–0.3
45
–20
—
50
—
0.3×VDD
55
85
V
%
°C
DC input signal voltage
High level input voltage
Low level input voltage
Input clock duty cycle
Operating temperature
VIL
Ta
Conditions
DC Electrical Characteristics
Ta = –20 to 85 °C, VDD = 3.0 to 3.6 V
Item
Input current
Input capacitance
Symbol
II
CI
Min
—
Typ
—
Max
±20
—
—
±100
—
3
—
Unit
µA
pF
Test Conditions
VI = 0 V or 3.6 V, VDD = 3.6 V,
XIN pin
VI = 0 V or 3.6 V, VDD = 3.6 V,
SEL, SSN pins
SEL, SSN pins
DC Electrical Characteristics / SSC Clock Output
Ta = –20 to 85 °C, VDD = 3.0 to 3.6 V
Item
Output voltage
Output current
Symbol
VOH
VOL
IOH
IOL
Output impedance
Min
VDD–0.2
—
—
—
—
Typ
—
—
–13
13
40
Max
—
200
—
—
—
Unit
V
mV
mA
Note: Parameters are target of design. Not 100% tested in production.
Rev.1.00 May 11, 2006 page 3 of 8
Ω
Test Conditions
IOH = –1 mA
IOL = 1 mA
VOH = 1.5 V, VDD = 3.3 V
VOL = 1.5 V, VDD = 3.3 V
RD151TS3312ARP, RD151TS3322ARP
AC Electrical Characteristics / SSC Clock Output
Ta = 25°C, VDD = 3.3 V, CL = 15 pF
Item
Operating current
Symbol
IDD
Min
—
Typ
12
Max
17
Unit
mA
Cycle to cycle jitter *1
tCCS
—
|100|
—
ps
Slew rate
tSL
—
0.7
4.0
V/ns
Test Conditions
VDD = 3.3 V, CL = 15 pF,
XIN = 20 MHz
SEL = 0, CL = 0 pF
SSC = ±1.5% (TS3312ARP)
SSC = –3.0% (TS3322ARP)
Notes
Figure 1
VDD = 3.3 V,
0.2 × VDD to 0.8 × VDD
Clock duty cycle
45
50
55
%
Stabilization time *2
—
—
2
ms
Notes: Parameters are target of design. Not 100% tested in production.
1. Cycle to cycle jitter is included spread spectrum modulation.
2. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after
power up.
SSCOUT
tcycle n
tcycle n+1
tCCS = (tcycle n) – (tcycle n+1)
Figure 1 Cycle to cycle jitter
Rev.1.00 May 11, 2006 page 4 of 8
RD151TS3312ARP, RD151TS3322ARP
Application Information
1. Recommended Circuit Configuration
The power supply circuit of the optimal performance on the application of a system should refer to Figure 2.
VDD decoupling is important to both reduce Jitter and EMI radiation.
The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace
inductance will negate its decoupling capability.
XIN
(Crystal or Reference input)
1
8
XOUT
(Crystal or Not connection)
2
7
C1
SEL
C2
GND GND
R1
NC
3
6
SSN
4
5
SSCOUT
GND
Notes:
C1 = High frequency supply decoupling capacitor.
(0.1 µF recommended)
C2 = Low frequency supply decoupling capacitor.
(22 µF recommended)
R1 = Match value to line impedance.
Figure 2 Recommended circuit configuration
Rev.1.00 May 11, 2006 page 5 of 8
VDD
RD151TS3312ARP, RD151TS3322ARP
2. Example Board Layout Configuration
VDD
(+3.3V Supply)
P
22 µF
FB
G
0.1 µF
Crystal connection
or Reference input
1
Crystal connection
or No connection
2
7
3
6
4
5
G
R1
Note:
G
G Via to GND plane
R1 = Match value to line impedance.
FB = Ferrite bead.
Figure 3 Example Board Layout
Rev.1.00 May 11, 2006 page 6 of 8
SSCOUT
RD151TS3312ARP, RD151TS3322ARP
3. Example of TS33XX EMI Solution IC’s Application
Spread Spectrum
Modulated Clock
XIN
XOUT
CPU & ASIC
TS33XXA
SSCOUT
System BUS
XTAL
Memory
Graphics
System Cont.
Ref.
Clock
3.3 V CMOS level ref. Clock
Figure 4 Ref. Clock Input Example
XIN
XTAL
XOUT
CPU & ASIC
TS33XXA
SSCOUT
System BUS
Spread Spectrum
Modulated Clock
Memory
Graphics
System Cont.
Figure 5 XTAL Ref. Clock Input Example
Rev.1.00 May 11, 2006 page 7 of 8
RD151TS3312ARP, RD151TS3322ARP
Package Dimensions
JEITA Package Code
P-SOP8-3.95x4.9-1.27
RENESAS Code
PRSP0008DD-C
*1
Previous Code
FP-8DCV
MASS[Typ.]
0.085g
F
D
8
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
5
c
*2
E
HE
bp
Index mark
Terminal cross section
( Ni/Pd/Au plating )
1
Z
Reference Dimension in Millimeters
Symbol
4
e
*3
bp
x
M
A
L1
A1
θ
L
y
Detail F
Rev.1.00 May 11, 2006 page 8 of 8
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Min Nom Max
4.90 5.30
3.95
0.10 0.14 0.25
1.75
0.34 0.40 0.46
0.15 0.20 0.25
0°
8°
5.80 6.10 6.20
1.27
0.25
0.10
0.75
0.40 0.60 1.27
1.08
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