datasheet for CH7024 by Chrontel

datasheet for CH7024 by Chrontel
CH7023/CH7024
Chrontel
Advance Information
CH7023/CH7024 TV Encoder
Features
General Description
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The CH7023/CH7024 is a TV encoder device targeting
handheld, portable video applications such as digital
still cameras and similar portable embedded systems.
The device is able to encode the video signals and
generate synchronization signals for NTSC and PAL
standards.
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TV encoder targeting handheld and similar systems
Support for NTSC, PAL
Video output support for CVBS or S-video
Macrovision™ 7.1.L1 copy protection support for
SDTV (CH7023 only)
Programmable 24-bit/18-bit/16-bit/15-bit/12-bit/8-bit
digital input interface supporting various RGB and
YCrCb (e.g. RGB565, RGB666, RGB888, ITU656
like YCrCb, etc.) input data formats
Support for input resolutions up to 720x480 and
720x576 (e.g. 220x176, 320x240, 640x480, 720x480,
720x576, etc.)
Adjustable brightness, contrast, hue and saturation.
Detect TV / Monitor connection
Two high quality10-bit video DAC outputs
Fully programmable through serial port
Flexible pixel clock frequency from graphics
controller (2.3MHz—64MHz)
Flexible input clock on the crystal or oscillator
(2.3MHz—64MHz)
Flexible up and down scaling on the display
Master and slave mode
Offered in 48-pin LQFP and 49-pin TFBGA Package
IO voltage and SPC/SPD from 1.2V to 3.3V
Programmable power management
Power down current less than 20uA typical
Power consumption of <150mW for one CVBS
output, single terminated and <350mW for two DAC
outputs, double terminated.
Supported TV output formats are NTSC-M, NTSC-J,
NTSC-433, PAL-B/D/G/A/I, PAL-M, PAL-N and PAL60.
The device accepts different data formats including
RGB and YCrCb (e.g. RGB565, RGB666, RGB888,
ITU656 like YCrCb, etc.) via 24 bit/18 bit/15 bit /12 bit
/8 bit multiplexed digital inputs. Most embedded
controllers are supported. The I/O interface voltage
between CH7023/CH7024 and digital video source
controller can be selected by the I/O supply voltage
(VDDIO). The I/O supply voltage range is from 1.2V to
3.3V. The digital input voltage will follow the I/O
supply voltage.
CH7023/CH7024 is offered in both 48-pin LQFP
package (7 x 7 mm) and 49-pin TFBGA package (6 x 6
mm). CH7023/CH7024 48-pin LQFP package comes
with fixed single serial port address while 49-pin
TFBGA package provide two user selectable serial port
addresses via AS pin pull up or pull down option. Refer
to application note AN-98 for more information.
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Figure 1: CH7023/CH7024 Block Diagram
209-0000-063
Rev. 1.14,
6/8/2007
1
CH7023/CH7024
CHRONTEL
Table of Contents
1.0
Pin-Out ___________________________________________________________________ 4
1.1
Package Diagram
4
1.1.1
The 48-pin LQFP Package Diagram............................................................................................... 4
1.1.2
The 49-pin TFBGA Package Diagram............................................................................................ 5
1.2
Pin Description
6
1.2.1
The 48-pin LQFP Pin Description .................................................................................................. 6
1.2.2
The 49-pin TFBGA Pin Description............................................................................................... 8
2.0
Functional Description______________________________________________________ 10
2.1
Modes of Operation
10
2.1.1
Graphics Controller to SDTV Encoder ......................................................................................... 10
2.1.2
ITU-R BT.601/656 TV Encoder ................................................................................................... 10
2.2
Input Interface
12
2.2.1
Overview....................................................................................................................................... 12
2.2.2
Input Clock and Data Timing Diagram......................................................................................... 12
2.2.3
Input data voltage.......................................................................................................................... 12
2.2.4
Input data formats ......................................................................................................................... 13
2.3
TV Output
17
2.3.1
TV Output Format ........................................................................................................................ 17
2.3.2
Video DAC Outputs...................................................................................................................... 17
2.3.3
DAC single/double termination .................................................................................................... 17
2.3.4
TV connection detect .................................................................................................................... 17
2.3.5
TV picture adjustment .................................................................................................................. 17
2.3.6
TV reference clock output ............................................................................................................ 18
2.3.7
Color Sub-carrier Generation........................................................................................................ 18
2.3.8
ITU-R BT.470 Compliance .......................................................................................................... 18
3.0
3.1
3.2
3.3
3.4
3.5
3.6
2
Electrical Specifications _____________________________________________________ 19
Absolute Maximum Ratings
Recommended Operating Conditions
Electrical Characteristics
Digital Inputs / Outputs
AC Specifications
ESD Rating
19
19
20
20
21
21
4.0
Package Dimensions ________________________________________________________ 22
5.0
Revision History ___________________________________________________________ 24
209-0000-063
Rev. 1.14,
6/8/2007
CH7023/CH7024
CHRONTEL
Figures and Tables
List of Figures
Figure 1: CH7023/CH7024 Block Diagram .......................................................................................................................1
Figure 2: 48-LQFP Package (top view) ..............................................................................................................................4
Figure 3: 49-Pin TFBGA Package (top view) ....................................................................................................................5
Figure 4: Interlaced Sync Input/Output Timing................................................................................................................11
Figure 5: Clock, Data and Interface Timing .....................................................................................................................12
Figure 6: 12-bit Multiplexed Input Data Formats.............................................................................................................16
Figure 7: 48 Pin LQFP Package .......................................................................................................................................22
Figure 8: 49 Pin TFBGA Package ....................................................................................................................................23
List of Tables
Table 1: Pin Description (48-pin LQFP) ............................................................................................................................6
Table 2: Pin Description (49-pin TFBGA) .........................................................................................................................8
Table 3: Operating Modes ................................................................................................................................................10
Table 4: Typical Input Resolution ....................................................................................................................................10
Table 5: ITU-R BT.601/656 TV Encoder Operating Modes ............................................................................................11
Table 6: Interlaced Sync Input/Output Timing.................................................................................................................11
Table 7: Input Data Formats in single data rate mode (MULTI = 0, see Register 0Dh)...................................................13
Table 8: Multiplexed Input Data Formats (MULTI = 1, see Register 0Dh) ....................................................................16
Table 9: Supported SDTV standards ................................................................................................................................17
Table 10: Video DAC Configurations for CH7023/CH7024 ...........................................................................................17
209-0000-063
Rev. 1.14,
6/8/2007
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CH7023/CH7024
CHRONTEL
PIN-OUT
1.0
There are two major differences between CH7023/CH7024 48-pin LQFP and 49-pin TFBGA in pin-out: the video
DACs output and the serial port address option using AS pin.
The CH7023/CH7024 48-pin LQFP comes with three video output pins, primary CVBS (pin 28), S-video Y (pin 27)
and secondary CVBS or S-video C (pin 26). The CH7023/CH7024 49-pin TFBGA comes with two video outputs,
primary CVBS or S-video Y (pin E5) and secondary CVBS or S-video C (pin F6).
The CH7023/CH7024 48-pin LQFP package comes with fixed single serial port address (76h – 7 bit address) while the
CH7023/CH7024 49-pin TFBGA package provides two user selectable serial port addresses via AS pin pull up or pull
down option.
1.1 Package Diagram
1.1.1
The 48-pin LQFP Package Diagram
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24
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25
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13
28
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11
26
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12
29
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Figure 2: 48-LQFP Package (top view)
.
4
209-0000-063
Rev. 1.14,
6/8/2007
CH7023/CH7024
CHRONTEL
1.1.2
The 49-pin TFBGA Package Diagram
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Figure 3: 49-Pin TFBGA Package (top view)
209-0000-063
Rev. 1.14,
6/8/2007
5
CH7023/CH7024
CHRONTEL
1.2 Pin Description
1.2.1
The 48-pin LQFP Pin Description
The 48-pin LQFP Package does not have AS pin to select second serial port address option. Refer to application note
AN-98 for device address byte (DAB) details. The serial port device address for the read and write operation is fixed at
ECh and EDh respectively.
It has internal switch to provide separate primary CVBS (pin 28) and S-video Y (pin27) outputs. Refer to section 2.3.2
Video DAC output and the Control Register 0Ah for the video DAC output control.
Table 1: Pin Description (48-pin LQFP)
Pin #
42-48,
1-15,
17,19
Type
In
Symbol
D[0]-D[23]
Description
Data[0] through Data[23] Inputs
These pins accept 24 data input lines from a digital video port of a
graphics controller. The swing is defined by VDDIO.
40
In/Out
H
Horizontal Sync Input / Output
When the SYO control bit is low, this pin accepts a horizontal sync
input for use with the input data. The amplitude will be 0 to
VDDIO.
When the SYO control bit is high, the device will output a
horizontal sync pulse. The amplitude will be 0 to VDDIO.
39
In/Out
V
Vertical Sync Input / Output
When the SYO control bit is low, this pin accepts a vertical sync
input for use with the input data. The amplitude will be 0 to
VDDIO.
When the SYO control bit is high, the device will output a vertical
sync pulse. The amplitude will be 0 to VDDIO.
20
In
DE
24
–
NC
23
In
RESET*
21
In/Out
SPD
22
In
SPC
28
Out
CVBS
27
Out
Y
6
Data Enable
When the pin is high, the input data is active.
When the pin is low, the input data is blanking.
–
Reset * Input
This pin is internally pulled high.
When this pin is low, the device is held in the power-on reset
condition. When this pin is high, reset is controlled through the
serial port.
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port
and operates with input level from 0 to VDDIO. Outputs are driven
from 0 to VDDIO.
Serial Port Clock Input
This pin functions as the clock pin of the serial port and operates
with input level from 0 to VDDIO.
Composite Video
This is a primary composite vide output when S-video Y (pin 27) is
not used. This output is turned off when S-video Y output is used.
Luma Output
The output is S-video luminance when the primary CVBS output
(pin 28) is not used.
209-0000-063
Rev. 1.14,
6/8/2007
CH7023/CH7024
CHRONTEL
Table 1: Pin Description (cont’d)
Pin #
26
Type
Out
Symbol
C/CVBS
30
In
ISET
37
Out
P-Out
34
In
XI/FIN
35
Out
XO
Crystal Output
For master mode and some situation of the slave mode, a parallel
resonance crystal (±20 ppm) should be attached between this pin
and XI/FIN. However, if an external CMOS clock is attached to
XI/FIN, XO should be left open.
41
In
XCLK
External Clock Inputs
The input is the clock signal input to the device for use with the H,
V, DE and D[23:0] data.
38
16
Power
Power
VDDIO
DVDD
IO Supply Voltage (1.2-3.3V)
Digital Supply Voltage (1.8V)
18
Power
DGND
Digital Ground
25
Power
AVDD_DAC DAC Supply Voltage (2.5-3.3V)
29
Power
AGND_DAC DAC Ground
32
Power
AVDD_PLL
PLL Supply Voltage (1.8V)
31
Power
AGND_PLL
PLL Ground
33
Power
AVDD
Crystal Supply Voltage (2.5-3.3V)
36
Power
AGND
Crystal Ground
209-0000-063
Rev. 1.14,
6/8/2007
Description
Chroma/CVBS Output
The output is S-video chrominance when S-video is used.
But, when dual CVBS outputs are needed, this out pin can be used
for secondary CVBS output in addition to the primary CVBS
output (pin 28).
Current Set Resistor
This pin sets the DAC current. A 1.2k ohm, 1% tolerance resistor
should be connected between this pin and AGND_DAC (pin 29)
using short and wide traces.
Pixel Clock Output
This pin provides a clock signal to the graphics controller, which
can be used as a reference frequency. The output driver is driven
from the VDDIO supply. This output has a programmable tri-state.
The capacitive loading on this pin should be kept to a minimum.
Crystal Input / External Reference Input
For master mode and some situation of the slave mode, a parallel
resonance crystal (±20 ppm) should be attached between this pin
and XO. However, an external 3.3V CMOS compatible clock can
drive the XI/FIN input.
7
CH7023/CH7024
CHRONTEL
1.2.2
The 49-pin TFBGA Pin Description
The 49-pin TFBGA Package has AS pin to select second serial port address. Refer to application note AN-98 for device
address byte (DAB). The device address for read operation can be either ECh or EAh based on external pull-down or
pull-up with AS pin respectively. The device address for write operation can be either EDh or EBh.
It does not has internal switch to provide separate primary CVBS and S-video Y outputs. Instead, it has single or dual
CVBSs or S-video C and Y output. Refer to section 2.3.2 Video DAC output and the Control Register 0Ah for the
video DAC output control.
Table 2: Pin Description (49-pin TFBGA)
BGA Pin #
A1-4,B1-B4,C1C4,D1-D3,E1-E4,
F1-F4,G1
B5
D4
8
Type
In
Symbol
D[0]-D[23]
In/Out
H
In/Out
V
G4
In
DE
F7
In
AS
G7
–
NC
G6
In
RESET*
F5
In/Out
SPD
G5
In
SPC
E6
–
NC
E5
Out
CVBS/Y
Description
Data[0] through Data[23] Inputs
These pins accept 24 data input lines from a digital video port
of a graphics controller. The swing is defined by VDDIO.
Horizontal Sync Input / Output
When the SYO control bit is low, this pin accepts a horizontal
sync input for use with the input data. The amplitude will be 0
to VDDIO.
When the SYO control bit is high, the device will output a
horizontal sync pulse. The output is driven from the VDDIO
supply.
Vertical Sync Input / Output
When the SYO control bit is low, this pin accepts a vertical
sync input for use with the input data. The amplitude will be 0
to VDDIO.
When the SYO control bit is high, the device will output a
vertical sync pulse. The output is driven from the VDDIO
supply.
Data Enable
When the pin is high, the input data is active.
When the pin is low, the input data is blanking.
Serial Port Address Select
This pin is internally pulled low.
When AS is high, the address is 75h – 7 bit address.
Otherwise, the address is 76h – 7 bit address.
–
Reset * Input
This pin is internally pulled high.
When this pin is low, the device is held in the power-on reset
condition. When this pin is high, reset is controlled through
the serial port.
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial
port and operates with input level from 0 to VDDIO. Outputs
are driven from 0 to VDDIO.
Serial Port Clock Input
This pin functions as the clock pin of the serial port and
operates with input level from 0 to VDDIO.
–
Luma Output
The output can be either a primary CVBS or S-video
luminance.
209-0000-063
Rev. 1.14,
6/8/2007
CH7023/CH7024
CHRONTEL
Table 2: Pin Description (cont’d)
BGA Pin #
F6
Type
Out
D5
Out
A7
Out
C5
In
B6
Out
A5
In
A6
G2
G3
E7
D7
C6
D6
C7
B7
Power
Power
Power
Power
Power
Power
Power
Power
Power
209-0000-063
Rev. 1.14,
Symbol
CVBS/C
Description
Chroma Output
The output can be either secondary CVBS when dual CVBSs
are needed or S-video chrominance when S-video is
selected. In single CVBS output mode, this output is turned
off to save power.
ISET
Current Set Resistor
This pin sets the DAC current. A 1.2k ohm, 1% tolerance
resistor should be connected between this pin and
AGND_DAC (pin D7) using short and wide traces.
P-Out
Pixel Clock Output
This pin provides a clock signal to the graphics controller,
which can be used as a reference frequency. The output
driver is driven from the VDDIO supply. This output has a
programmable tri-state. The capacitive loading on this pin
should be kept to a minimum.
XI/FIN
Crystal Input / External Reference Input
For master mode and some situation of the slave mode, a
parallel resonance crystal (±20 ppm) should be attached
between this pin and XO. However, an external +3.3V
CMOS compatible clock can drive the XI/FIN input.
XO
Crystal Output
For master mode and some situation of the slave mode, a
parallel resonance crystal (±20 ppm) should be attached
between this pin and XI/FIN. However, if an external
CMOS clock is attached to XI/FIN, XO should be left open.
XCLK
External Clock Inputs
The input is the clock signal input to the device for use with
the H, V, DE and D[23:0] data.
VDDIO
IO Supply Voltage (1.2-3.3V)
VDD
Digital Supply Voltage (1.8V)
GND
Digital Ground
AVDD_DAC DAC Supply Voltage (2.5-3.3V)
AGND_DAC DAC Ground
AVDD_PLL PLL Supply Voltage (1.8V)
AGND_PLL PLL Ground
AVDD
Crystal Supply Voltage (2.5-3.3V)
AGND
Crystal Ground
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CH7023/CH7024
CHRONTEL
2.0
2.1
FUNCTIONAL DESCRIPTION
Modes of Operation
Table 3: Operating Modes describes the possible operating modes for CH7023/CH7024 TV encoder. An ‘i’ following
a number in the Input Scan Type column indicates an interlaced input where the number indicates the active number of
lines per frame. Basically, CH7023/CH7024 can take non-interlaced data from graphics controller and encode it to
analog NTSC and PAL waveforms. It can also take interlaced data from sources and perform SDTV encoding.
Table 3: Operating Modes
Input Scan Type
Non-Interlaced
Interlaced
(480i, 576i)
2.1.1
Input Data
Format
RGB /
YCrCb
RGB /
YCrCb
Output scan
Type
Interlaced
Interlaced
Output
Format
CVBS,
S-video
CVBS,
S-video
Operating Mode
SDTV encoder (NTSC / PAL) with
non-interlaced input
SDTV encoder (NTSC / PAL) with
interlaced input
Described
In section
2.1.1
2.1.2
Graphics Controller to SDTV Encoder
CH7023/CH7024 is mainly designed as an SDTV encoder targeting handheld device market. In this mode, the graphics
controller of the handheld system will send non-interlaced data, sync and clock signals to CH7023/CH7024.
CH7023/CH7024 can run in clock master mode or clock slave mode. In clock master mode, an accurate (less than
20ppm) crystal is required between XI/FIN and XO pins or an accurate CMOS clock signal is needed on the XI/FIN pin.
The frequency of the crystal or the clock has to be between 2.3MHz and 64MHz. CH7023/CH7024 will generate a
reference clock signal (P-Out) according to the requirement of the graphics controller. However, the range of this clock
reference signal is between 2.3MHz and 64MHz. In clock slave mode, no reference clock is output to the graphics
controller. So, the crystal becomes may only be necessary for color sub-carrier generation in the slave mode. However,
if the clock from the graphics controller cannot meet the requirement of color sub-carrier generation, the crystal is still
required, which will discuss in the latter part of this document. Horizontal and vertical sync signals are normally sent to
the device from the graphics controller, but can be embedded into the data stream in YCrCb input data formats, or can
be output to the graphics controller. However, the DE signal is NOT generated inside. Data can be unitary or 2X
multiplexed, and the XCLK clock signal can be 1X or 2X times the pixel rate. Input data will be scaled, scan converted
and filtered, then encoded into the selected video standard and output from the video DACs. NTSC and PAL formats
are supported. The device can output data in S-video and CVBS format. The graphics resolutions supported are from
220x176 to 720x576. The typical resolutions are shown in Table 4.
Table 4: Typical Input Resolution
Typical Input
Resolution
TV Output
Standard
2.1.2
220x176
320x240
512x384
640x400
640x480
720x400
720x480
720x576
NTSC,PAL
ITU-R BT.601/656 TV Encoder
In interlaced data, sync and clock signals are input to the CH7023/CH7024 from a graphics controllers digital output
port, or the output of an MPEG decoder device. The YCrCb data format is most commonly used in these modes. A
clock signal (P-Out) can be output as a frequency reference to the graphics device. Horizontal and vertical sync signals
are normally sent to the CH7023/CH7024 from the graphics device, but can be embedded into the data stream in
YCrCb input data formats, or can be output to the graphics controller. Data can be unitary or 2X multiplexed, and the
XCLK clock signal can be 1X or 2X times the pixel rate. Input data bypasses the scaling, scan conversion and filtering
blocks, is encoded into the selected video standard and output from the video DACs. NTSC and PAL formats are
supported. The device can output data in S-video and CVBS format. The graphics resolutions supported for ITU-R
BT.601/656 TV output are shown in Table 5 below. The CH7023 is capable of adding Macrovision™ encoding to the
output signal. CH7024 is non-Macrovision™ part. The timing of the sync signals is shown in Figure 4 below. Note
that the alignment of the VSYNC signal to the HSYNC signal changes from field 1 to field 2 to allow the
CH7023/CH7024 to identify the correct field.
10
209-0000-063
Rev. 1.14,
6/8/2007
CH7023/CH7024
CHRONTEL
Table 5: ITU-R BT.601/656 TV Encoder Operating Modes
Input Resolution
720x480i
720x576i
TV Output Standard
NTSC
PAL
WH
TH
H In/Out
T1
V Out
(Odd Field
Master Mode)
T2
V Out
(Even Field
Master Mode)
T3
V In
(Odd Field
Slave Mode)
T4
V In
(Even Field
Slave Mode)
Figure 4: Interlaced Sync Input/Output Timing
Table 6: Interlaced Sync Input/Output Timing
Symbol Parameter
Min
Typ
Max
Unit
TPCK
Input clock period
6.73
47.62
us
TH
Total Line Period
SDTV
63.5
63.5
us
WH
Hsync Width
When output from CH7023/CH7024
When input to CH7023/CH7024
T1
T2
T3
Odd Field (Field 1) V SYNC in to H SYNC in alignment
0
WH - TPCK
us
T4
Even Field (Field 2) V SYNC in delay from H SYNC in
WH
TH - TPCK
us
64
64
Pixel clocks
Pixel clocks
Odd Field (Field 1) V SYNC out to H SYNC out alignment
0
us
Even Field (Field 2) V SYNC out delay from H SYNC out
0.5*TH
us
209-0000-063
Rev. 1.14,
6/8/2007
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11
CH7023/CH7024
CHRONTEL
2.2 Input Interface
2.2.1
Overview
Three distinct methods of transferring data to the CH7023/CH7024 are described. They are:
Unitary data, clock input at 1X the pixel rate
Multiplexed data, clock input at 1X the pixel rate
Multiplexed data, clock input at 2X the pixel rate
For the multiplexed data, clock at 1X pixel rate, the data applied to the CH7023/CH7024 is latched with both edges of
the clock (also referred to as dual edge transfer mode or DDR). For the multiplexed data, clock at 2X pixel rate the data
applied to the CH7023/CH7024 is latched with one edge of the clock (also known as single edge transfer mode or SDR).
For the unitary data, clock at 1X pixel rate, the data applied to the CH7023/CH7024 is latched with one edge of the
clock .The polarity of the pixel clock can be reversed under serial port control.
2.2.2
Input Clock and Data Timing Diagram
Figure 5 below shows the timing diagram for input data and clocks. The first XCLK waveform represents the input
clock for single edge transfer (SDR) methods. The second XCLK waveform represents the input clock for the dual
edge transfer (DDR) method. The timing requirements are given in section 3.5.
XCLK(X2)
XCLK(X1)
D[23:0]
HW
H
VW
HO
V
VO
DE
HB
VB
Figure 5: Clock, Data and Interface Timing
2.2.3
Input data voltage
The voltage level of input pins D[23:0], H, V, DE, SPC, SPD are from 0 to VDDIO. These pins support two input mode,
one is CMOS mode, and the other is pseudo differential mode. The default is CMOS mode with CMOS level on these
pins. When control bit DIFFEN(Control Register 0Eh) is high, the input is pseudo differential mode which use a
reference voltage to compare with input voltage and decide input logic value. The pseudo differential mode can accept
the wide range of the input voltage level from 1.2V to 3.3V, while the CMOS mode can accept 1.8V to 3.3V Input
voltage.
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CH7023/CH7024
CHRONTEL
2.2.4
Input data formats
The device accepts different data formats including RGB and YCrCb (e.g. RGB565, RGB666, RGB888, ITU656 like
YCrCb, etc.) via 24 bit/18 bit/ 15 bit /12 bit / 8 bit multiplexed digital inputs to support most of existing industry
Embedded controller to provide TV encoder solution.
CH7023/CH7024 Input Data Format (IDF) are grouped into two major group. These are unitary IDF modes and
multiplexed IDF modes. In the unitary IDF mode (Control Register 0Ch, control bit MULTI = 0), all of control bits
SWAP, REVERSE and HIGH bit of the control register 0Dh can be used. While, in the multiplexed IDF mode (Control
Register 0Ch, control bit MULTI = 1), only REVERSE and HIGH bits are used for IDF5, YCrCb 4:2:2 mode.
For the unitary IDF mode, refer to Table 7 and note for more description or refer to Table 8 for the multiplexed IDF
mode.
Table 7: Input Data Formats in single data rate mode (MULTI = 0, see Register 0Dh)
IDF=
0
1
2
3
4
5
5
6
RGB88
8
DVO
RGB66
6
RGB56
5
RGB55
5
YCrCb4:2:2
(CBCRSW =0)
YCbCr4:4:
4
P0
R[7]
R[6]
R[5]
R[4]
R[3]
G[7]
G[6]
G[5]
R[2]
R[1]
R[0]
G[1]
G[4]
G[3]
G[2]
B[7]
B[6]
P0
P0
P0
P0
P1
D[23]
D[22]
D[21]
D[20]
D[19]
D[18]
D[17]
D[16]
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
P0
R[7]
R[6]
R[5]
R[4]
R[3]
R[2]
R[1]
R[0]
G[7]
G[6]
G[5]
G[4]
G[3]
G[2]
G[1]
G[0]
B[7]
YCbCr4:2:2
(CBCRSW
=1)
P0
P1
R[5]
R[4]
R[3]
R[2]
R[1]
R[0]
R[4]
R[3]
R[2]
R[1]
R[0]
R[4]
R[3]
R[2]
R[1]
R[0]
D[6]
B[6]
B[5]
D[5]
B[5]
B[4]
B[5]
D[4]
B[4]
B[3]
B[4]
B[4]
B[4]
D[3]
B[3]
G[0]
B[3]
B[3]
B[3]
D[2]
B[2]
B[2]
B[2]
B[2]
B[2]
D[1]
B[1]
B[1]
B[1]
B[1]
B[1]
D[0]
B[0]
B[0]
B[0]
B[0]
B[0]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
Cr0[7
]
Cr0[6
]
Cr0[5
]
Cr0[4
]
Cr0[3
]
Cr0[2
]
Cr0[1
]
Cr0[0
]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Cb0[7
]
Cb0[6
]
Cb0[5
]
Cb0[4
]
Cb0[3
]
Cb0[2
]
Cb0[1
]
Cb0[0
]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
Cb0[
7]
Cb0[
6]
Cb0[
5]
Cb0[
4]
Cb0[
3]
Cb0[
2]
Cb0[
1]
Cb0[
0]
PIN
Format
=
Pixel#
Busdata
G[5]
G[4]
G[3]
G[2]
G[1]
G[0]
G[5]
G[4]
G[3]
G[2]
G[1]
G[0]
G[4]
G[3]
G[2]
G[1]
G[0]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Cr0[7
]
Cr0[6
]
Cr0[5
]
Cr0[4
]
Cr0[3
]
Cr0[2
]
Cr0[1
]
Cr0[0
]
P0
Y[7]
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
Y[0]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Cr[1]
Cr[0]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Cb[1]
Cb[0]
Note: In IDF = 0 mode, 24 bits digital inputs D[23:0]can be assigned to the CH7023/CH7024 internal RGB registers
by either SWAP[2:0] or REVERSE bit via Control Register (Address = 0Dh) . SWAP controls R, G, B
register byte order from the input D[23:0], while REVERSE bit controls reverse 7 bits assignment order within
R,G, B registers.
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For examples, If REVERSE bit = 0 and SWAP[2:0] = 000 , then D[23:0] = R[7:0]G[7:0]B[7:0],
else if REVERSE bit = 1 and SWAP[2:0] = 000 , then D[23:0] = R[0:7]G[0:7]B[0:7];
The HIGH control bit is used in the unitary mode only. For the HIGH bit usage , refer to IDF 2, 3, 4 in the
unitary IDF mode.
1. In unitary IDF = 0 mode, RGB888 , from input D[23:0] to internal RGB register as shown below:
If REVERSE bit = 0 and SWAP[2:0] = 000 , then D[23:0] = R[7:0]G[7:0]B[7:0];
001 , then D[23:0] = R[7:0]B[7:0]G[7:0];
010 , then D[23:0] = G[7:0]R[7:0]B[7:0];
011 , then D[23:0] = G[7:0]B[7:0]R[7:0];
100 , then D[23:0] = B[7:0]R[7:0]G[7:0];
101 , then D[23:0] = B[7:0]G[7:0]R[7:0].
If REVERSE bit = 1 and SWAP[2:0] = 000 , then D[23:0] = R[0:7]G[0:7]B[0:7];
001 , then D[23:0] = R[0:7]B[0:7]G[0:7];
010 , then D[23:0] = G[0:7]R[0:7]B[0:7];
011 , then D[23:0] = G[0:7]B[0:7]R[0:7];
100 , then D[23:0] = B[0:7]R[0:7]G[0:7];
101 , then D[23:0] = B[0:7]G[0:7]R[0:7].
.
2. In unitary IDF = 1, DVO (see Control Register 0Dh)
{D[23:19],D[15:13],D[18:16],D[11:9],D[12],D[3],D[8:4],D[2:0]} = {R[7:0], G[7:0], B[7:0]}
3. In non-multiplexed IDF = 2, RGB666 (see Control Register 0Dh)
High bit of the Control Register (0Dh), controls insertion of logical value ‘1’ into blank bit within R,G and B
registers when input data bits width is less than 8 bit wide. When the High bit = 0, value ‘1’ is inserted to bit 7 and bit
6 of internal R, G and B registers. If High bit = 1 is selected, value ‘1’ is inserted to bit 1 and bit 0 of the
CH7023/CH7024 internal R, G and B registers. ( 2’b11 means assign corresponding 2 bits with logical value 1 in
binary number.)
SWAP: (see Control Register 0Dh)
000 , then {D[21:16],2’b11, D[13:8],2’b11, D[5:0],2b’11} = {R[7:0], G[7:0], B[7:0]};
001 , then {D[21:16],2’b11, D[13:8],2’b11, D[5:0],2’b11} = {R[7:0], B[7:0], G[7:0]};
010 , then {D[21:16],2’b11, D[13:8],2’b11, D[5:0],2’b11} = {G[7:0], R[7:0], B[7:0]};
011 , then {D[21:16],2’b11, D[13:8],2’b11, D[5:0],2’b11} = {G[7:0], B[7:0], R[7:0]};
100 , then {D[21:16],2’b11, D[13:8],2’b11, D[5:0],2’b11} = {B[7:0], R[7:0], G[7:0]};
101 , then {D[21:16],2’b11, D[13:8],2’b11, D[5:0],2’b11} = {B[7:0], G[7:0], R[7:0]}.
110: then {D[17:12],2’b11, D[11:6],2’b11, D[5:0],2’b11} = {R[7:0], G[7:0], B[7:0]};
111: then {D[21:16],2’b11, D[15:14],D[11:8],2’b11, D[5:0],2’b11} = {R[7:0]G[7:0]B[7:0]}.
REVERSE: (see Control Register 0Dh)
0: {D[21:16],2’b11,D[13:8],2’b11,D[5:0],2’b11} = {R[7:0],G[7:0],B[7:0]};
1: {2’b11, D[21:16],2’b11,D[13:8],2’b11,D[5:0]} ={R[0:7],G[0:7],B[0:7]};
HIGH: (see Control Register 0Dh)
0: {2’b11,D[21:16], 2’b11,D[13:8], 2’b11,D[5:0]} = {R[7:0], G[7:0], B[7:0]};
1: {D[23:18],2’b11,D[15:10],2’b11,D[7:2],2’b11} = {R[7:0], G[7:0], B[7:0]};
4. In unitary IDF = 3, RGB565 (see Control Register 0Dh)
( Note: 2’b11 means assign corresponding 2 bits with logical value 1 in binary number.
3’B111 means assign corresponding 3 bits with logical value 1 in binary number.)
SWAP: (see Control Register 0Dh)
000: {D[20:16],3’b111, D[13:8],2’b11, D[4:0],3’b111} = {R[7:0], G[7:0], B[7:0]};
001: {D[20:16],3’b111, D[13:8],2’b11, D[4:0],3’b111} = {R[7:0], B[7:0], G[7:0]};
010: {D[20:16],3’b111, D[13:8],2’b11, D[4:0],3’b111} = {G[7:0], R[7:0], B[7:0]};
011: {D[20:16],3’b111, D[13:8],2’b11, D[4:0],3’b111} = {G[7:0], B[7:0], R7:0]};
100: {D[20:16],3’b111, D[13:8],2’b11, D[4:0],3’b111} = {B[7:0], G[7:0], G[7:0]};
101: {D[20:16],3’b111, D[13:8],2’b11, D[4:0],3’b111} = {B[7:0], G[7:0], B[7:0]};
110: {D[15:11],3’b111,D[10:5],2’b11,D[4:0],3’b111} = {R[7:0], G[7:0], B[7:0]};
111: {D[20:16],3’b111,D[15:14],D[11:8],2’b11,D[4:0],3’b111} = {R[7:0], G[7:0], B[7:0]}.
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CHRONTEL
REVERSE: (see Control Register 0Dh)
0: {D[20:16],3’b111, D[13:8],2’b11, D[4:0],3’b111} = {R[7:0], G[7:0], B[7:0]};
1: {3’b111, D[20:16], 2’b11, D[13:8], 3’b111,D[4:0]} = {R[0:7], G[0:7], B[0:7]};
HIGH: (see Control Register 0Dh)
0: {3’b111,D[20:16], 3’b11,D[13:8], 3’b111,D[4:0]} = {R[7:0], G[7:0], B[7:0]};
1: {D[23:19],3’b111, D[15:10],2’b11, D[7:3],3’b111} = {R[7:0], G[7:0], B[7:0]};
5. In unitary IDF = 4, RGB555 (see Control Register 0Dh)
(3’B111 means assign corresponding 3 bits with logical value 1 in binary number.)
SWAP: (see Control Register 0Dh)
000: {D[20:16],3’b111, D[12:8],3’b111, D[4:0],3’b111} = {R[7:0], G[7:0], B[7:0]};
001: {D[20:16],3’b111, D[13:8],3’b111, D[4:0],3’b111} = {R[7:0], B[7:0], G[7:0]};
010: {D[20:16],3’b111, D[13:8],3’b111, D[4:0],3’b111} = {G[7:0], R[7:0], B[7:0]};
011: {D[20:16],3’b111, D[13:8],3’b111, D[4:0],3’b111} = {G[7:0], B[7:0], R7:0]};
100: {D[20:16],3’b111, D[13:8],3’b111, D[4:0],3’b111} = {B[7:0], G[7:0], G[7:0]};
101: {D[20:16],3’b111, D[13:8],3’b111, D[4:0],3’b111} = {B[7:0], G[7:0], B[7:0]};
110: {D[14:10],3’b111, D[9:5],3’b111, D[4:0],3’b111} = {R[7:0], G[7:0], B[7:0]};
111: {D[20:16],3’b111, D[14],D[11:8],3’b111, D[4:0],3’b111} = {R[7:0],G[7:0],B[7:0]}.
REVERSE: (see Control Register 0Dh)
0: {D[20:16],3’b111,D[12:8],3’b111,D[4:0],3’b111} = {R[7:0], G[7:0], B[7:0]};
1: {3’b111,D[20:16], 3’b111,D[12:8], 3’b111,D[4:0]} = {R[0:7], G[0:7], B[0:7]};
HIGH: (see Control Register 0Dh)
0: {3’b111,D[20:16], 3’b111,D[12:8], 3’b111,D[4:0]} = {R[7:0], G[7:0], B[7:0]};
1: {D[23:19],3’b111, D[15:11],3’b111, D[7:3],3’b111} = {R[7:0], G[7:0], B[7:0]};
6. In unitary IDF = 5, YCbCr 4:2:2 (see Control Register 0Dh)
Note that only the SWAP[0] bit is used in this mode.
SWAP: (see Control Register 0Dh)
xx0: D[15:0] = Y[7:0]C[7:0];
xx1: D[15:0] = C[7:0]Y[7:0];
REVERSE: (see Control Register 0Dh)
0: D[15:0] = Y[7:0]C[7:0];
1: D[15:0] = Y[0:7]C[0:7];
HIGH: (see Control Register 0Dh)
0: D[15:0] = Y[7:0]C[7:0]; (non-multiplexed format only)
1: D[23:8] = Y[0:7]C[0:7]; (non-multiplexed format only)
7. In unitary IDF = 6, YCbCr 4:4:4 (see Control Register 0Dh)
SWAP: (see Control Register 0Dh)
000: D[23:0] = Y[7:0], Cr[7:0], Cb[7:0];
001: D[23:0] = Y[7:0], Cb[7:0], Cr[7:0];
010: D[23:0] = Cr[7:0], Y[7:0], Cb[7:0];
011: D[23:0] = Cr[7:0], Cb[7:0], Y[7:0];
100: D[23:0] = Cb[7:0], Y[7:0], Cr[7:0];
101: D[23:0] = Cb[7:0], Cr[7:0], Y[7:0];
REVERSE: (see Control Register 0Dh)
0 : D[23:0] = Y[7:0], Cr[7:0], Cb[7:0].
1 : D[23:0] = Y[0:7], Cr[0:7], Cb[0:7].
In RGB666, RGB565, RGB555, the RGB data are continuously distributed when SWAP[2:0] = 110 .
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CH7023/CH7024
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Table 8: Multiplexed Input Data Formats (MULTI = 1, see Register 0Dh)
IDF =
Format =
Pixel #
Bus Data
PIN
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0
12-bit RGB
1
DVO
P0a
G[3]
G[2]
G[1]
G[0]
B[7]
B[6]
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
P0a
G[4]
G[3]
G[2]
B[7]
B[6]
B[5]
B[4]
B[3]
G[0]
B[2]
B[1]
B[0]
P0b
R[7]
R[6]
R[5]
R[4]
R[3]
R[2]
R[1]
R[0]
G[7]
G[6]
G[5]
G[4]
P0b
R[7]
R[6]
R[5]
R[4]
R[3]
G[7]
G[6]
G[5]
R[2]
R[1]
R[0]
G[1]
5
YCrCb4:2:2
(CBCRSW =0)
P1a
P1b
5
YCbCr4:2:2
(CBCRSW =1)
P0a
P0b
Cr0[7]
Cr0[6]
Cr0[5]
Cr0[4]
Cr0[3]
Cr0[2]
Cr0[1]
Cr0[0]
Cb0[7]
Cb0[6]
Cb0[5]
Cb0[4]
Cb0[3]
Cb0[2]
Cb0[1]
Cb0[0]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
6
12-bit YCbCr
P1a
Y[3]
Y[2]
Y[1]
Y[0]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Cb[1]
Cb[0]
P1b
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Cr[1]
Cr[0]
Y[7]
Y[6]
Y[5]
Y[4]
1. In multiplexed IDF = 5, YCbCr 4:2:2 (see Control Register 0Dh)
Note that only the SWAP[0] bit is used in this mode.
SWAP: (see Control Register 0Dh)
xx0: D[15:0] = Y[7:0]C[7:0];
xx1: D[15:0] = C[7:0]Y[7:0];
REVERSE: (see Control Register 0Dh)
0: D[7:0] = Y[7:0]/C[7:0];
1: D[7:0] = Y[0:7]/C[0:7];
The multiplexed input data format is shown in Figure 6 below. The Pixel Data bus represents a 12-bit or 8-bit
multiplexed data stream, which contains either RGB or YCrCb formatted data. The input data rate is 2X the pixel rate,
and each pair of Pn values (e.g.; P0a and P0b) will contain a complete pixel.
It is assumed that the first clock cycle following the leading edge of the incoming horizontal sync signal contains the
first word (Pxa) of a pixel, if an active pixel was present immediately following the horizontal sync. This does not
mean that active data should immediately follow the horizontal sync, however. When the input is a YCrCb data stream
the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence being set as
Cb, Y, Cr, Y, where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples and the following Y1 byte
refers to the next luminance sample, per ITU-R BT.656 standards (the clock frequency is dependent upon the current
mode, and is not 27MHz as specified in ITU-R BT.656). All non-active pixels should be 0 in RGB formats, and 16 for
Y, 128 for Cr and Cb in YCrCb formats.
Hx
XCLK
(2X)
SAV
XCLK
(1X)
D[11:0]
P0a
P0b
P1a
P1b
P2a
P2b
Figure 6: 12-bit Multiplexed Input Data Formats
In YCbCr 4:2:2 with embedded sync mode, the hardware can detect the connect error and correct it automatically, for
example, if the input P14 and P15 are a group, but you take P13 and P14 as a group, the hardware can detect this error
and correct it by run-in code.
16
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CHRONTEL
2.3 TV Output
2.3.1
TV Output Format
The CH7023/CH7024 support the following output formats:
Table 9: Supported SDTV standards
No.
0
1
2
3
4
5
6
7
2.3.2
Standards
NTSC-M
NTSC-J
NTSC-443
PAL-B/D/G/H/I
PAL-M
PAL_N
PAL-Nc
PAL_60
Field Rate (Hz)
60/1.001
60/1.001
60/1.001
50
50
50
50
60/1.001
Total
858x525
858x525
858x525
864x625
864x625
864x625
864x625
858x525
Scan Type
Interlaced
Interlaced
Interlaced
Interlaced
Interlaced
Interlaced
Interlaced
Interlaced
Video DAC Outputs
Table 10 below lists the DAC output configurations of the CH7023/CH7024.
Table 10: Video DAC Configurations for CH7023/CH7024
Output Type
of
48 pin LQFP
Single CVBS
Dual CVBS
S-video
Output Type
of
49 pin BGA
Single CVBS
Dual CVBS
S-video
2.3.3
DACA0=CVBS
or
DACA0=Y
CVBS
CVBS
Y
DACB0 =CVBS/Y
DAC1-C/CVBS
off
CVBS
C
DAC1=CVBS/C
CVBS
CVBS
Y
off
CVBS
C
DAC single/double termination
The DAC output of CH7023/CH7024 can be single terminated or double terminated. Using single termination will save
power consumption while double termination is likely to minimize the effect of the cable. See also the description of
SEL_R bit of the Control Register 63h
2.3.4
TV connection detect
CH7023/CH7024 support detecting the TV connection by setting the SENSEEN bit of the Control Register 62h. It can
detect which DAC are connected, short to ground or not connected. So it can distinguish single CVBS connected with
other connection, but it can not distinguish dual CVBS connected with S-video connected. See also the DUCVBS bit
description of the Control Register 0Ch and the SVD/DDAC bit description of the Control Register 0Ah.
2.3.5
TV picture adjustment
The CH7023/CH7024 has the capability of vertical and horizontal output picture position adjustment. The
CH7023/CH7024 will automatically put the picture in the display center, and the position is also programmable through
user input. The CH7023/CH7024 also provides brightness/sharpness/contrast, hue and saturation adjustments.
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Rev. 1.14,
6/8/2007
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CH7023/CH7024
CHRONTEL
2.3.6
TV reference clock output
The CH7023/CH7024 support operating in Clock Master Mode. The CH7023/CH7024 integrates the low jitter PLL to
generate a reference clock for the graphics controller for reference.
2.3.7
Color Sub-carrier Generation
The CH7023/CH7024 has two ways to generate the color sub-carrier frequency. If the XCLK from the graphics
controller has a steady center frequency and very small jitters, the sub-carrier can be derived from the XCLK. However,
since even a ±0.01% sub-carrier frequency variation is enough to cause some TV to lose color lock, CH7023/CH7024
has the ability to generate the sub-carrier frequency from the crystal when the XCLK from the graphics device cannot
meet the requirement. In this case, the crystal has to be present. In other words, the only configuration where the offchip crystal can be removed is when slave mode is used and the graphics controller provides XCLK with required
characteristics.
In addition, the CH7023/CH7024 has the capability to genlock the color sub-carrier with Vsync. Also,
CH7023/CH7024 has the ability to operate in a “stop dot crawl” mode for NTSC CVBS output when the first subcarrier generation method is used.
2.3.8
ITU-R BT.470 Compliance
The CH7023/CH7024 is mostly compliant with ITU-R BT.470 standard except for the items below.
•
•
•
•
18
The frequencies of horizontal sync, vertical sync, and color sub-carrier depend on the quality of XCLK from
graphics controller and/or the off-chip crystal.
It is assumed that gamma correction, if required, is performed in the graphics device.
Pulse widths and rise/fall times for sync pulses, front/back porches, and equalizing pulses are designed to
approximate ITU-R BT.470 requirements. However, they may have a small variation depending on the actual input
and output format.
The actual bandwidths of the luminance and chrominance signals depend on the filter selection.
209-0000-063
Rev. 1.14,
6/8/2007
CH7023/CH7024
CHRONTEL
3.0 ELECTRICAL SPECIFICATIONS
3.1
Absolute Maximum Ratings
Symbol
VDD18
Description
Min
Typ
Max
Units
All 1.8V power supplies relative to GND
-0.5
2.5
V
VDD33
VDDIO
All 3.3V power supplies relative to GND
-0.5
5.0
V
TSC
Input voltage of all digital pins (see note)
GND – 0.5
VDDIO+0.5
V
Analog output short circuit duration
TAMB
Ambient operating temperature
-55
125
°C
TSTOR
Storage temperature
-65
150
°C
TJ
Junction temperature
150
°C
TVPS
Vapor phase soldering (5 seconds)
260
°C
Vapor phase soldering (11 seconds)
245
°C
Vapor phase soldering (60 seconds)
225
°C
Indefinite
Sec
Note: Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These
are stress ratings only. Functional operation of the device at these or any other conditions above those indicated under the
recommended operating condition of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive device. Voltage
on any signal pin that exceeds the power supply voltages by more than ± 0.5V may cause permanent damage to the device.
The digital input voltage will follow the I/O supply voltage (VDDIO). The I/O supply voltage range is from 1.2V to 3.3V
3.2
Recommended Operating Conditions
Symbol
Description
Min
Typ
Max
Units
AVDD
Crystal and I/O Power Supply Voltage
3.3
3.5
V
AVDD_DAC
DACs Power Supply Voltage
3.3
3.5
V
AVDD_PLL
PLL Power Supply Voltage
3.1
3.1
2.5 1
1.71
1.8
1.89
V
DVDD
Digital Power Supply Voltage
1.71
1.8
1.89
V
VDDIO
Data I/O supply voltage
1.1
3.5
V
RL1
Output load to DAC Current Reference Pin ISET
RL2
Output load to DAC Outputs, Pins CVBS, Y, and C
VDD18
Generic for all 1.8V supplies
1.71
VDD33
Generic for all 3.3V supplies
3.1
Note
Note
Note
◇
◇
◇
1
2
3
Ambient operating temperature
: TFBGA package only.
: Single terminated.
: Except otherwise indicated.
209-0000-063
Rev. 1.14,
6/8/2007
◇
1.2k
37.5
75 2
1.8
1.89
V
3.3
3.5
V
70
°C
Ω
◇
◇
0
3
Ω
19
CH7023/CH7024
CHRONTEL
3.3
Electrical Characteristics
(Operating Conditions: TA = 0°C – 70°C, VDD18=1.8V± 5%, VDD33=3.3V± 5%)
Symbol
Description
Min
Video D/A Resolution
10
Full scale output current
Video level error
IVDD18
Total VDD18 supply current (1.8V supplies)
IVDD33
Total VDD33 supply current (3.3V supplies)
(See Note)
IPD
Total Power Down Current
Typ
10
34
Max
10
32
Units
bits
mA
%
mA
25
mA
< 20
uA
10
Note: The VDD33 supply current is 18mA for one DAC single 75-Ohm termination. The current will be 35mA for one DAC
double 75-Ohm termination (37.5Ohm). For two DACs, the current will be doubled according to different termination.
3.4
Digital Inputs / Outputs
Symbol
Description
Test Condition
Min
Typ
Max
Unit
GND-0.5
0.4
V
VSDOL
SPD (serial port data) Output Low
Voltage
VSPIH
Serial Port (SPC, SPD) Input High
Voltage
1.0
VDD33 + 0.5
V
VSPIL
Serial Port (SPC, SPD) Input Low
Voltage
GND-0.5
0.4
V
VHYS
Hysteresis of Serial Port Input
VDATAIH
Data Input High Voltage (see Note 1)
VDATAIL
Data Input Low Voltage
VMISCIH
IOL = 3.0 mA
0.25
V
VDDIO/2+0.25
VDDIO + 0.5
V
GND-0.5
VDDIO/2-0.25
V
Miscellaneous Input High Voltage
(see Note 2)
2.7
VDD33 + 0.5
V
VMISCIL
Miscellaneous Input Low Voltage
GND-0.5
0.6
V
IMISCPU
Miscellaneous input Pull Up Current
VIN = 0V
0.5
5.0
uA
VP-OUTOH
P-OUT Output High Voltage
IOH = - 0.4mA
VP-OUTOL
P-OUT Output Low Voltage
IOL = 4 mA
VDD18-0.2
V
0.2
V
Note :
1. Data input means the following pins: D[23:0], XCLK, H, V and DE. VDDIO is the I/O supply voltage. The range
is from 1.2V to 3.3V.
2. Vmisc means the following pins: AS, RESET*.
20
209-0000-063
Rev. 1.14,
6/8/2007
CH7023/CH7024
CHRONTEL
3.5
AC Specifications
Symbol
Description
fCRYSTAL
Input (CRYSTAL) frequency
fXCLK
Input (XCLK) frequency
DCXCLK
Input (XCLK) Duty Cycle
tXJIT
TS + TH < 1.2ns
Min
Max
Unit
2.3
64
MHz
2.3
64
MHz
30
70
%
XCLK clock jitter tolerance
Typ
2
ns
tS
Setup Time: D[23:0], H, V and DE to
XCLK
XCLK to D[23:0], H,
V, DE = Vref
0.35
ns
tH
Hold Time: D[23:0], H, V and DE to
XCLK
D[23:0], H, V, DE =
Vref to XCLK
0.5
ns
Pout, Output Rise Time
15pF load
(20% - 80%)
VDD33=
VDD18=1.8V
Pout Output Fall Time
15pF load
(20% - 80%)
VDD33=3.3V,
VDD18=1.8V
tR
tF
tSTEP
3.6
Test Condition
De-skew time increment
3.3V,
50
1.50
ns
1.50
ns
80
ps
ESD Rating
2KV HBM per JEDEC standard JESD22-A114C.
209-0000-063
Rev. 1.14,
6/8/2007
21
CH7023/CH7024
CHRONTEL
4.0
PACKAGE DIMENSIONS
Figure 7: 48 Pin LQFP Package
Table of Dimensions
No. of Leads
48 (7 X 7 mm)
MilliMIN
meters
MAX
22
A
B
C
9
7
0.5
D
0.17
0.27
SYMBOL
E
F
1.35
0.05
1.45
0.15
G
1.00
209-0000-063
H
0.45
0.75
I
0.09
0.20
Rev. 1.14,
J
0°°
7°°
6/8/2007
CH7023/CH7024
CHRONTEL
Figure 8: 49 Pin TFBGA Package
Table of Dimensions
No. of Leads
49 (6 X 6 mm)
MilliMIN
meters
MAX
A
B
C
D
6.00
6.00
4.80
0.80
SYMBOL
E
F
4.80
0.80
G
1.20
H
0.22
0.32
I
J
0.26
0.53
Notes:
1. All dimensions conform to JEDEC standard MO-216.
209-0000-063
Rev. 1.14,
6/8/2007
23
CH7023/CH7024
CHRONTEL
5.0
REVISION HISTORY
Rev. #
1.0
1.1
1.11
Date
6/6/2006
12/15/2006
1/15/2007
Section
1.2.1, 1.2.2
4.1, 4.2
1.12
2/8/2007
3.3.1
1.13
4/25/2007
5.0
1.14
6/8/2007
2.2.4
24
Description
Official release.
Updated Pin Description.
Updated Section 4.1 and 4.2
Corrected Register 0Fh YCV[1] and Register 1Ch BSTADJ bit
corrected to Bits[3:1].
Updated Figure 8, 49-Pin TFBGA package drawing.
Corrected Table 8: Multiplexed Input Data Formats (MULTI = 1,
see Register 0Dh).
209-0000-063
Rev. 1.14,
6/8/2007
CH7023/CH7024
CHRONTEL
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at any time
without notice to improve and supply the best possible product and is not responsible and does not assume any liability
for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our
products and assume no liability for errors contained in this document. The customer should make sure that they have
the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does
not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or
assist others to infringe upon such rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as
directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Part Number
Package Type
Copy
Protection
Output
Video
Switch
Shipping Format
CH7023B-GF
49TFBGA, Lead-free
Macrovision™
No
Tray, 4290 per dry pack bag
CH7023B-GF-TR
49TFBGA, Lead-free,
Tape & reel
Macrovision™
No
T&R, 2000 per dry pack bag
CH7023B-DF
48LQFP, Lead-free
Macrovision™
Yes
Tray, 2500 per dry pack bag
CH7023B-DF-TR
48LQFP, Lead-free,
Tape & reel
Macrovision™
Yes
T&R, 1000 per dry pack bag
CH7024B-GF
49TFBGA, Lead-free
None
No
Tray, 4290 per dry pack bag
CH7024B-GF-TR
49TFBGA, Lead-free,
Tape & reel
None
No
T&R, 2000 per dry pack bag
CH7024B-DF
48LQFP, Lead-free
None
Yes
Tray, 2500 per dry pack bag
CH7024B-DF-TR
48LQFP, Lead-free,
Tape & reel
None
Yes
T&R, 1000 per dry pack bag
Chrontel
2210 O’Toole Avenue, Suite 100,
San Jose, CA 95131-1326
Tel: (408) 383-9328
Fax: (408) 383-9338
www.chrontel.com
E-mail: sales@chrontel.com
2007 Chrontel, Inc. All Rights Reserved.
Printed in the U.S.A.
209-0000-063
Rev. 1.14,
6/8/2007
25
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