Errata Sheet Overview

Errata Sheet Overview

Errata Sheet

Rel. 1.0, 2015-10

Device XMC1400

Marking/Step EES-AA, ES-AA

Package PG-VQFN-40/48/64, PG-LQFP-64

Overview

This “Errata Sheet” describes product deviations with respect to the user documentation listed below.

Table 1

Document

Current User Documentation

XMC1400 Reference Manual AA-step

XMC1400 Data Sheet AA-step

Version Date

V1.0

V0.3

Oct. 2015

Oct. 2015

Make sure that you always use the latest documentation for this device listed in category “Documents” at

http://www.infineon.com/xmc1000

.

Notes

1. The errata described in this sheet apply to all temperature and frequency versions and to all memory size and configuration variants of affected devices, unless explicitly noted otherwise.

2. Devices marked with EES or ES are engineering samples which may not be completely tested in all functional and electrical characteristics, therefore they must be used for evaluation only. The specific test conditions for EES and ES are documented in a separate “Status Sheet”.

XMC1400, EES-AA, ES-AA 1/23

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Rel. 1.0, 2015-10

Errata Sheet

Conventions used in this Document

Each erratum is identified by Module_Marker.TypeNumber:

Module

: Subsystem, peripheral, or function affected by the erratum.

Marker

: Used only by Infineon internal.

Type

: type of deviation

(none): Functional Deviation

P: Parametric Deviation

H: Application Hint

D: Documentation Update

Number

: Ascending sequential number. As this sequence is used over several derivatives, including already solved deviations, gaps inside this enumeration can occur.

XMC1400, EES-AA, ES-AA 2/23

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1

Table 2

Version

1.0

Errata Sheet

History List / Change Summary

History List / Change Summary

History List

Date

2015-10

Remark

Initial version

Table 3

Errata

- none -

Errata fixed in this step

Short Description

Table 4

Functional

Deviation

Functional Deviations

Short Description

Change

Chg Pg

ACMP_CM.001

ADC_AI.008

ADC_AI.016

BCCU_CM.008

BCCU_CM.009

Operating range of the

Analog Comparator

Reference Divider function

Wait-for-Read condition for register GLOBRES not detected in continuous auto-scan sequence

X X New

7

X X X X New

7

X X X X New

8 No Channel Interrupt in

Fast Compare Mode with

GLOBRES

X X New

8 Linear walk starts with a delay after an aborted linear walk

X X New

9 Dimming level not immediately changed for first dimming operation

XMC1400, EES-AA, ES-AA 3/23

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Table 4

Functional

Deviation

Functional Deviations

Short Description

Errata Sheet

History List / Change Summary

Chg Pg

CCU_AI.007

Automatic shadow transfer feature does not work when system PCLK is faster than MCLK

X X X X New

9

CCU8_AI.005

PWM outputs from

Compare Channel 2 are disabled in asymmetric mode

X X New

10

CPU_CM.002

Watchpoint PC functions can report false execution

X X X X New

12

CPU_CM.003

Prefetch faulting instructions can erroneously trigger breakpoints

X X X X New

13

Firmware_CM.002 Calculate Target Level for

Temperature Comparison

User Routine returns zero for valid temperature input parameter

X X X X New

14

Firmware_CM.003 BMI installation of CAN

BSL with external oscillator is not supported

X X New

14

Firmware_CM.004 SSC BSL is not supported

X X X X New

14

Firmware_CM.005 Last byte of SRAM is not available for ASC BSL

X X X X New

15

X X X X New

15 Firmware_CM.006 Header resend not supported for incorrect

ASC BSL header byte

XMC1400, EES-AA, ES-AA 4/23

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Table 4

Functional

Deviation

Functional Deviations

Short Description

Errata Sheet

History List / Change Summary

Chg Pg

USIC_AI.008

USIC_AI.014

USIC_AI.017

USIC_AI.018

SSC delay compensation feature cannot be used

X X X X New

16

No serial transfer possible while running capture mode timer

Clock phase of data shift in

SSC slave cannot be changed

X X X X New

16

X X X X New

16

X X X X New

17 Clearing PSR.MSLS bit immediately deasserts the

SELOx output signal

Table 5

Hint

Application Hints

Short Description Chg Pg

ADC_AI.H007

ADC_AI.H010

BCCU_CM.H001

BCCU_CM.H004

Ratio of Sample Time t

S to SHS Clock f

SH

Disabling the ORWD

X X X X New

18

X X

X

X X

X

New

New

19

19 Additional dimming clocks after dimming curve switch

X X New

19 Packer threshold

(CHCONFIGy.PKTH) accepted values

XMC1400, EES-AA, ES-AA 5/23

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Table 5

Hint

Application Hints

Short Description

Errata Sheet

History List / Change Summary

Chg Pg

BCCU_CM.H005

Enable a dimming engine for global dimming

MultiCAN_AI.H005

TxD Pulse upon short disable request

MultiCAN_AI.H006

Time stamp influenced by resynchronization

X

X

X

X

X

X

New

New

New

20

20

20

MultiCAN_AI.H007

Alert Interrupt

Behavior in case of

Bus-Off

MultiCAN_TC.H003

Message may be discarded before transmission in STT mode

X

X

X

X

New

New

20

21

MultiCAN_TC.H004

Double remote request

SCU_CM.H001

Temperature Sensor

Functionality

USIC_AI.H004

I2C slave transmitter recovery from deadlock situation

X X New

22

X X X X New

22

X X X X New

23

XMC1400, EES-AA, ES-AA 6/23

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Errata Sheet

Functional Deviations

2 Functional Deviations

The errata in this section describe deviations from the documented functional behavior.

ACMP_CM.001 Operating range of the Analog Comparator Reference Divider function

The Analog Comparator Reference Divider function is not available when V

DDP is below 3 V. To use this function, V

DDP

must be between 3 V to 5.5 V.

Workaround

None

ADC_AI.008 Wait-for-Read condition for register GLOBRES not detected in continuous auto-scan sequence

In the following scenario:

• A continuous auto-scan is performed over several ADC groups and channels by the Background Scan Source, using the global result register

(GLOBRES) as result target (GxCHCTRy.RESTBS=1

B

), and

• The Wait-for-Read mode for GLOBRES is enabled (GLOBRCR.WFR=1

B

), each conversion of the auto-scan sequence has to wait for its start until the result of the previous conversion has been read out of GLOBRES.

When the last channel of the auto-scan is converted and its result written to

GLOBRES, the auto-scan re-starts with the highest channel number of the highest ADC group number. But the start of this channel does not wait until the result of the lowest channel of the previous sequence has been read from register GLOBRES, i.e. the result of the lowest channel may be lost.

Workaround

If either the last or the first channel in the auto-scan sequence does not write its result into GLOBRES, but instead into its group result register (selected via bit

XMC1400, EES-AA, ES-AA 7/23

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Errata Sheet

Functional Deviations

GxCHCTRy.RESTBS=0

B

), then the Wait-for-Read feature for GLOBRES works correctly for all other channels of the auto-scan sequence.

For this purpose, the auto-scan sequence may be extended by a “dummy” conversion of group x/ channel y, where the Wait-for-Read mode must not be selected (GxRCRy.WFR=0

B read.

) if the result of this “dummy” conversion is not

ADC_AI.016 No Channel Interrupt in Fast Compare Mode with GLOBRES

In fast compare mode, the compare value is taken from bitfield RESULT of the global result register GLOBRES and the result of the comparison is stored in the respective bit FCR.

The channel event indicating that the input becomes higher or lower than the compare value, is not generated.

The comparison is executed correctly, the target bit is stored correctly, source events and result events are generated.

Workaround

The result bit FCR can be evaluated if the input is higher or lower than the compare value.

BCCU_CM.008 Linear walk starts with a delay after an aborted linear walk

If a linear walk is previously aborted, the subsequent linear walk starts with a delay. The maximum delay is one linear clock.

Workaround

None.

XMC1400, EES-AA, ES-AA 8/23

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Errata Sheet

Functional Deviations

BCCU_CM.009 Dimming level not immediately changed for first dimming operation

For the first dimming operation, the dimming level is not immediately incremented or decremented upon a shadow bit (DES) assertion.

Workaround

None.

CCU_AI.007 Automatic shadow transfer feature does not work when system PCLK is faster than MCLK

Each CCU8 or CCU4 Timer Slice has a set of registers that have an associated shadow transfer mechanism. This shadow transfer mechanism works like a buffer where the application software can load new data, and when needed, request the load of this data into the register (this mechanism of loading new data into the current used register is called shadow transfer).

The shadow transfer can be applied to several data registers: compare values

(that control the PWM duty cycle), timer period value or dead-time, in case of

CCU8 (CCU4 does not have a dead-time feature).

To request the shadow transfer operation, the application software has two possibilities:

• do a software request by writing a 1

B

into a specific bitfield

• or enable an automatic request feature, that will allow the hardware to request the shadow transfer in an automatic way (saving this way one software operation)

The automatic shadow transfer request be enabled for the following conditions:

• after the software writes a value into the shadow period register - enabled by setting the CC8ySTC.ASPC = 1

B

(in CCU8) or CC4ySTC.ASPC = 1

B

(in

CCU4)

• after the software writes a value into the shadow compare register - enabled by setting the CC8ySTC.ASCC1 = 1

B

(in CCU8) or CC4ySTC.ASCC = 1

B

(in CCU8) or CC8ySTC.ASCC2 = 1

(in CCU4)

B

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Functional Deviations

• after the software writes a value into the passive level register - enabled by setting the CC8ySTC.ASLC = 1

B

(in CCU8) or CC4ySTC.ASLC = 1

B

• after the software writes a value into the dither shadow register - enabled by setting the CC8ySTC.ASDC = 1

B

(in CCU8) or CC4ySTC.ASDC = 1

B

• after the software writes a value into the floating prescaler shadow register

- enabled by setting the CC8ySTC.ASFC = 1

B

(in CCU8) or

CC4ySTC.ASFC = 1

B

None of these automatic shadow transfer features work when the system PCLK frequency is higher than the MCLK frequency.

The PCLK can, in XMC1400 device(s), be configured to be 2x faster than the

MCLK by setting the CLKCR.PCLKSEL = 1

B

.

Whenever the PCLKSEL = 1

B

, then none of the automatic shadow transfer request functions work.

Note that the rest of the shadow transfer mechanism/features are still usable as specified.

Workaround

None

CCU8_AI.005 PWM outputs from Compare Channel 2 are disabled in asymmetric mode

Each CCU8 Timer Slice offers an asymmetric PWM mode. This mode is enabled whenever the CC8yCHC.ASE bitfield is set to 1

B

.

If the asymmetric mode is not selected (ASE = 0

B

), then each compare channel works independently, and can generate each, two complementary PWM signals. The PWM signal information for compare channel 1 is stored in the

CC8yST1. The PWM signal information for compare channel 2 is stored in

CC8yST2. CC8yST1 and CC8yST2 can then be forward to the PWM outputs.

This is depicted in

Figure 1

a).

If the asymmetric mode is selected, the timer slice will generate two complementary asymmetric PWM signals, using the compare channel 1 for setting the PWM and the compare channel 2 for clearing the PWM. The

XMC1400, EES-AA, ES-AA 10/23

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Errata Sheet

Functional Deviations

asymmetric PWM signal is stored in CC8yST1 and then can be forward to the outputs. This is depicted in

Figure 1

b).

The asymmetric mode has a bug, where the PWM signal of Compare Channel

2 is not stored in CC8yST2. This means that from the Compare Channel 2 the timer cannot generate any PWM signal - depicted by the cross on

Figure 1

b).

Note that the asymmetric PWM is still stored in CC8yST1 and can be used normally by the application.

Figure 1

Workaround

None

CCU8 simplifier PWM generation scheme - a) normal mode; b) asymmetric mode

XMC1400, EES-AA, ES-AA 11/23

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Errata Sheet

Functional Deviations

CPU_CM.002 Watchpoint PC functions can report false execution

In the presence of interrupts including those generated by the SVC instruction, it is possible for both the data watchpoint unit's PC match facility and PC sample-register to operate as though the instruction immediately following the interrupted or SVC instruction had been executed.

Conditions

Either:

1. Halting debug is enabled via C_DEBUGEN = 1

2. Watchpoints are enabled via DWTENA = 1

3. A watchpoint is configured for PC sampling DWT_FUNCTION = 0x4

4. The same watchpoint is configured to match a `target instruction`

5. And either: a) The `target instruction` is interrupted before execution, or b) The `target instruction` is preceded by a taken SVC instruction

6. The DWT will unexpectedly match the `target instruction`

7. The processor will unexpectedly enter debug state once inside the exception handler

Or:

1. The debugger performs a read access to the DWT_PCSR

2. A `non-committed instruction` is preceded by a taken SVC instruction

3. The DWT_PCSR value unexpectedly matches the `non-committed instruction`

Implications

If halting debug is enabled and PC match watchpoints are being used, then spurious entry into halted debug state may occur under the listed conditions.

If the DWT_PCSR is being used for coarse grain profiling, then it is possible that the results can include hits for the address of an instruction immediately after an SVC instruction, even if said instruction is never executed.

Workaround

This errata does not impact normal execution of the processor.

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Errata Sheet

Functional Deviations

A debug agent may choose to handle the infrequent false positive Debug state entry and erroneous PCSR values as spurious events.

CPU_CM.003 Prefetch faulting instructions can erroneously trigger breakpoints

External prefetch aborts on instruction fetches on which a BPU breakpoint has been configured, will cause entry to Debug state. This is prohibited by revision

C of the ARMv6-M Architecture Reference Manual. Under this condition, the breakpoint should be ignored, and the processor should instead service the prefetch-abort by entering the HardFault handler.

Conditions

1. Halting debug is enabled via CDEBUG_EN == '1'

2. A BPU breakpoint is configured on an instruction in the first 0.5GB of memory

3. The fetch for said instruction aborts via an AHB Error response

4. The processor will erroneously enter Debug state rather than entering

HardFault.

Implications

If halting debug is enabled and a BPU breakpoint is placed on an instruction with faults due to an external abort, then a non-compliant entry to Debug state will occur.

Workaround

This errata does not impact normal execution of the processor.

A debug agent may choose to avoid placing BPU breakpoints on addresses that generate AHB Error responses, or may simply handle the Debug state entry as a spurious debug event.

XMC1400, EES-AA, ES-AA 13/23

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Functional Deviations

Firmware_CM.002 Calculate Target Level for Temperature Comparison

User Routine returns zero for valid temperature input parameter

In Calculate Target Level for Temperature Comparison User Routine in

Firmware, the temperature sensor threshold value is expected to be returned for a valid range of temperature input parameter of 233K to 388K. This user function typically returns zero value for input parameter out of the valid range, also for some input parameters within the valid range.

Workaround

If user function returns zero for input parameter within the valid range, increase or decrease the input parameter by 1 degree Kelvin in order to use this user function.

Firmware_CM.003 BMI installation of CAN BSL with external oscillator is not supported

For the start-up mode selection of CAN BSL and CAN BSL with timeout mode, the Request BMI Installation User Routine with CAN clock source via external oscillator is not supported for EES samples.

Workaround

Use CAN clock source via internal oscillator in the Request BMI Installation

User Routine for the CAN BSL start-up modes.

Firmware_CM.004 SSC BSL is not supported

SSC Bootstrap Loader start-up mode is not supported for EES and ES samples.

Workaround

None.

XMC1400, EES-AA, ES-AA 14/23

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Errata Sheet

Functional Deviations

Firmware_CM.005 Last byte of SRAM is not available for ASC BSL

For start-up mode selection of ASC BSL and ASC BSL with timeout modes, the last byte of available SRAM is not available for user application code.

Application length error (BSL_NOK) is transmitted back to the host for application code length of available SRAM size.

Workaround

Host to send application code length of available SRAM size - 1 Byte or less.

Firmware_CM.006 Header resend not supported for incorrect ASC BSL header byte

For start-up mode selection of ASC BSL and ASC BSL with timeout modes, the baud rate detection is performed based on the Start Byte (00

H

) received from

the host. Next, the Header Byte defined in

Table 6

is expected from the host.

An incorrect Header Byte received leads to a hang-up of the device.

Table 6

Name

Header Byte definition in ASC BSL

Length,

Byte

Data sent by the Host:

BSL_ASC_F 1

Value Description

6C

H

BSL_ASC_H

BSL_ENC_F

BSL_ENC_H

1

1

1

12

93

H

H

ED

H

Header requesting full duplex ASC mode with the current baud rate

Header requesting half duplex ASC mode with the current baud rate

Header requesting full duplex ASC mode with a request to switch the baud rate

Header requesting half duplex ASC mode with a request to switch the baud rate

Workaround

None.

XMC1400, EES-AA, ES-AA 15/23

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Errata Sheet

Functional Deviations

USIC_AI.008 SSC delay compensation feature cannot be used

SSC master mode and complete closed loop delay compensation cannot be used. The bit DX1CR.DCEN should always be written with zero to disable the delay compensation.

Workaround

None.

USIC_AI.014 No serial transfer possible while running capture mode timer

When the capture mode timer of the baud rate generator is enabled

(BRG.TMEN = 1) to perform timing measurements, no serial transmission or reception can take place.

Workaround

None.

USIC_AI.017 Clock phase of data shift in SSC slave cannot be changed

Setting PCR.SLPHSEL bit to 1 in SSC slave mode is intended to change the clock phase of the data shift such that reception of data bits is done on the leading SCLKIN clock edge and transmission on the other (trailing) edge.

However, in the current implementation, the feature is not working.

Workaround

None.

XMC1400, EES-AA, ES-AA 16/23

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Errata Sheet

Functional Deviations

USIC_AI.018 Clearing PSR.MSLS bit immediately deasserts the SELOx output signal

In SSC master mode, the transmission of a data frame can be stopped explicitly by clearing bit PSR.MSLS, which is achieved by writing a 1 to the related bit position in register PSCR.

This write action immediately clears bit PSR.MSLS and will deassert the slave select output signal SELOx after finishing a currently running word transfer and respecting the slave select trailing delay (T td

) and next-frame delay (T nf

).

However in the current implementation, the running word transfer will also be immediately stopped and the SELOx deasserted following the slave select delays.

If the write to register PSCR occurs during the duration of the slave select leading delay (T ld

) before the start of a new word transmission, no data will be transmitted and the SELOx gets deasserted following T td

and T nf

.

Workaround

There are two possible workarounds:

• Use alternative end-of-frame control mechanisms, for example, end-offrame indication with TSCR.EOF bit.

• Check that any running word transfer is completed (PSR.TSIF flag = 1) before clearing bit PSR.MSLS.

XMC1400, EES-AA, ES-AA 17/23

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Errata Sheet

Application Hints

3 Application Hints

The errata in this section describe application hints which must be regarded to ensure correct operation under specific application conditions.

ADC_AI.H007 Ratio of Sample Time t

S

to SHS Clock f

SH

The sample time t

S

is programmable to the requirements of the application.

To ensure proper operation of the internal control logic, t

S

must be at least four cycles of the prescaled converter clock f

SH

, i.e. t

S

≥ 4 t

CONV

x (DIVS+1).

(1) With SHS*_TIMCFGx.SST > 0, the sample time is defined by

t

S

= SST x t

ADC

.

In this case, the following relation must be fulfilled:

• SST ≥ 4 x t

CONV

/t

ADC

– Example:

x (DIVS+1), i.e. SST ≥ 4 x f

ADC

/f

CONV

x (DIVS+1).

with the default setting DIVS=0 and f

ADC

= f

MCLK

32 MHz (for DIVS = 0):

= 32 MHz, f

SH

= f

CONV

= select SST ≥ 4.

(2) With SHS*_TIMCFGx.SST = 0, the sample time is defined by

t

S

= (2+STC) x t

ADCI

, with t

ADCI

= t

ADC

x (DIVA+1)

In this case, the following relation must be fulfilled:

• [(2+STC) x (DIVA+1)] / (DIVS+1) ≥ 4 x t

CONV

– Example:

/t

ADC

= 4 x f

ADC

/f

CONV

.

With the default settings STC=0, DIVA=1, DIVS=0 and f

ADC

32 MHz, f

SH

= f

CONV

= 32 MHz (for DIVS = 0),

= f

MCLK

= this relation is fulfilled.

Note: In addition, the condition f

ADC

= f

MCLK

≥ 0.55 f

SH

must be fulfilled.

Note that this requirement is more restrictive than the requirement in

ADC_AI.H006.

Definitions

DIVA: Divider Factor for the Analog Internal Clock, resulting from bit field

GLOBCFG.DIVA (range: 1..32

D

)

XMC1400, EES-AA, ES-AA 18/23

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Errata Sheet

Application Hints

DIVS: Divider Factor for the SHS Clock, resulting from bit field

SHS*_SHSCFG.DIVS (range: 1..16

D

)

STC: Additional clock cycles, resulting from bit field STCS/STCE in registers

GxICLASS*, GLOBICLACSSy (range: 0..256

D

)

SST: Short Sample Time factor, resulting from bit field SHS*_TIMCFGx.SST

(range: 1..63

D

)

Recommendation

Select the parameters such that the sample time t

S

is at least four cycles of the prescaled converter clock f

SH

, as described above.

ADC_AI.H010 Disabling the ORWD

When the ORWD is disabled while detecting an overvoltage, i.e. while its output signal is high, the output will not always return to zero, but may remain high after disabling.

It is therefore recommended to disable the connected units (ERU, interrupt generation) before disabling the corresponding out-of-range comparator.

BCCU_CM.H001 Additional dimming clocks after dimming curve switch

If the dimming curve is switched (from coarse to fine or vice versa), the next dimming process takes additional dimming clocks.

BCCU_CM.H004 Packer threshold (CHCONFIGy.PKTH) accepted values

CHCONFIGy.PKTH is defined as 3-bits wide. However, only values 1-4 are accepted.

XMC1400, EES-AA, ES-AA 19/23

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Errata Sheet

Application Hints

BCCU_CM.H005 Enable a dimming engine for global dimming

When using global dimming as the source of dimming input (CHCONFIG.DSEL

= 111

B

), enable at least one of the dimming engines (DEEN != 0).

MultiCAN_AI.H005 TxD Pulse upon short disable request

If a CAN disable request is set and then canceled in a very short time (one bit time or less) then a dominant transmit pulse may be generated by MultiCAN module, even if the CAN bus is in the idle state.

Example for setup of the CAN disable request:

CAN_CLC.DISR

=1 and then CAN_CLC.DISR=0

Workaround

Set all INIT bits to 1 before requesting module disable.

MultiCAN_AI.H006 Time stamp influenced by resynchronization

The time stamp measurement feature is not based on an absolute time measurement, but on actual CAN bit times which are subject to the CAN resynchronization during CAN bus operation.The time stamp value merely indicates the number of elapsed actual bit times. Those actual bit times can be shorter or longer than nominal bit time length due to the CAN resynchronization events.

Workaround

None.

MultiCAN_AI.H007 Alert Interrupt Behavior in case of Bus-Off

The MultiCAN module shows the following behavior in case of a bus-off status:

XMC1400, EES-AA, ES-AA 20/23

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Errata Sheet

Application Hints

TEC=0x60 or

REC=0x60

EWRN

REC=0x1,

TEC=0x1

BOFF

INIT

REC=0x60,

TEC=0x1

EWRN+BOFF

INIT

REC=0x0,

TEC=0x0

ALERT

INIT

Figure 2 Alert Interrupt Behavior in case of Bus-Off

When the threshold for error warning (EWRN) is reached (default value of Error

Warning Level EWRN = 0x60), then the EWRN interrupt is issued. The bus-off

(BOFF) status is reached if TEC > 255 according to CAN specification, changing the MultiCAN module with REC and TEC to the same value 0x1, setting the INIT bit to 1

B

, and issuing the BOFF interrupt. The bus-off recovery phase starts automatically. Every time an idle time is seen, REC is incremented.

If REC = 0x60, a combined status EWRN+BOFF is reached. The corresponding interrupt can also be seen as a pre-warning interrupt, that the bus-off recovery phase will be finished soon. When the bus-off recovery phase has finished (128 times idle time have been seen on the bus), EWRN and BOFF are cleared, the

ALERT interrupt bit is set and the INIT bit is still set.

MultiCAN_TC.H003 Message may be discarded before transmission in

STT mode

If MOFCRn.STT=1 (Single Transmit Trial enabled), bit TXRQ is cleared

(TXRQ=0) as soon as the message object has been selected for transmission and, in case of error, no retransmission takes places.

Therefore, if the error occurs between the selection for transmission and the real start of frame transmission, the message is actually never sent.

Workaround

In case the transmission shall be guaranteed, it is not suitable to use the STT mode. In this case, MOFCRn.STT shall be 0.

XMC1400, EES-AA, ES-AA 21/23

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Errata Sheet

Application Hints

MultiCAN_TC.H004 Double remote request

Assume the following scenario: A first remote frame (dedicated to a message object) has been received. It performs a transmit setup (TXRQ is set) with clearing NEWDAT. MultiCAN starts to send the receiver message object (data frame), but loses arbitration against a second remote request received by the same message object as the first one (NEWDAT will be set).

When the appropriate message object (data frame) triggered by the first remote frame wins the arbitration, it will be sent out and NEWDAT is not reset. This leads to an additional data frame, that will be sent by this message object (clearing

NEWDAT

).

There will, however, not be more data frames than there are corresponding remote requests.

C A N B u s

r e m o t e r e q u e s t r e m o t e r e q u e s t d a t a d a ta

M u ltiC A N

Figure 3

s e tu p lo s s o f a rb itra tio n

d a t a o b je c t

c le a r

N E W D A T b y H W

Loss of Arbitration

s e tu p c le a r s e t

N E W D A T b y H W

d a t a o b je c t

s e tu p c le a r

N E W D A T b y H W

d a ta o b je c t

SCU_CM.H001 Temperature Sensor Functionality

EES samples are not temperature tested, therefore the temperature sensor functionality is not supported.

Workaround

None

XMC1400, EES-AA, ES-AA 22/23

Subject to Agreement on the Use of Product Information

Rel. 1.0, 2015-10

Errata Sheet

Application Hints

USIC_AI.H004 I2C slave transmitter recovery from deadlock situation

While operating the USIC channel as an IIC slave transmitter, if the slave runs out of data to transmit before the master receiver issues clock pulses, for example due to an error in the application flow, it ties the SCL infinitely low.

Recommendation

To recover and reinitialize the USIC IIC slave from such a deadlock situation, the following software sequence can be used:

1. Switch the SCL and SDA port functions to be general port inputs for the slave to release the SCL and SDA lines: a) Write 0 to the two affected Pn_IOCRx.PCy bit fields.

2. Flush the FIFO buffer: a) Write 1

B

to both USICx_CHy_TRBSCR.FLUSHTB and FLUSHRB bits.

3. Invalidate the internal transmit buffer TBUF: a) Write 10

B

to USICx_CHy_FMR.MTDV.

4. Clear all status bits and reinitialize the IIC USIC channel if necessary.

5. Reprogram the Pn_IOCRx.PCy bit fields to select the SCL and SDA port functions again.

At the end of this sequence, the IIC slave is ready to communicate with the IIC master again.

XMC1400, EES-AA, ES-AA 23/23

Subject to Agreement on the Use of Product Information

Rel. 1.0, 2015-10

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