Voltage Regulator-Down (VRD) 11.1 September 2009 Processor Power Delivery Design Guidelines

Voltage Regulator-Down (VRD) 11.1  September 2009 Processor Power Delivery Design Guidelines
Voltage Regulator-Down (VRD) 11.1
Processor Power Delivery Design Guidelines
September 2009
Document Number: 322172-001
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2
Processor Power Delivery Design Guidelines
Contents
1
VRD 11.1 Common Information .......................................................................... 11
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
Applications .......................................................................................... 11
Terminology .......................................................................................... 12
Processor VCC Requirements .................................................................... 14
1.3.1
Voltage and Current (REQUIRED) ............................................... 14
1.3.2
Loadline Definitions (REQUIRED) ................................................ 14
1.3.3
VRD Output Filter (REQUIRED) ................................................... 16
1.3.4
TOB — Voltage Tolerance Band (REQUIRED) ................................ 18
1.3.5
Stability (REQUIRED) ................................................................ 20
1.3.6
Dynamic Voltage Identification (REQUIRED)................................. 20
1.3.7
Processor VCC Overshoot (REQUIRED) ......................................... 25
1.3.8
Example: Socket VCC Overshoot Test ........................................... 28
Power Sequencing (REQUIRED) ............................................................... 29
1.4.1
VR_ENABLE ............................................................................. 29
1.4.2
Vboot Voltage Level (REQUIRED) ................................................ 29
1.4.3
Under Voltage Lock Out (UVLO) (REQUIRED) ............................... 29
1.4.4
Soft Start (SS) (REQUIRED) ....................................................... 30
1.4.5
Power-off Timing Sequence (REQUIRED) ..................................... 30
VRD Current Support (Required) .............................................................. 33
1.5.1
Phase Count Requirement .......................................................... 33
Control Inputs to VRD ............................................................................ 34
1.6.1
Voltage Identification (VID [7:0]) (REQUIRED) ............................. 34
1.6.2
Differential Remote Sense Input (REQUIRED)............................... 38
1.6.3
Power State Indicator (PSI#) (Required) ..................................... 39
Input Voltage and Current....................................................................... 39
1.7.1
Input Voltages (EXPECTED) ....................................................... 39
Output Protection .................................................................................. 41
1.8.1
Over-Voltage Protection (OVP) (PROPOSED) ................................ 41
1.8.2
Over-Current Protection (OCP) (PROPOSED) ................................ 41
Output Indicators................................................................................... 42
1.9.1
VR_READY — VCC Regulator Is ‘ON’ (REQUIRED) ........................... 42
1.9.2
Load Current Signal (Iout) (REQUIRED) ....................................... 43
1.9.3
Thermal Monitoring ................................................................... 44
LGA1366 Information ........................................................................................ 47
2.1
2.2
2.3
2.4
2.5
Introduction .......................................................................................... 47
2.1.1
Applications ............................................................................. 47
Processor VCC Requirements .................................................................... 47
2.2.1
Loadline Definitions (REQUIRED) ................................................ 47
VTT Requirements (REQUIRED) ................................................................ 53
2.3.1
Electrical Specifications ............................................................. 53
LGA 1366 Specific Signals ....................................................................... 56
2.4.1
Power-on Configuration (POC) Signals on VID (REQUIRED) ............ 56
MB Power Plane Layout (REQUIRED) ........................................................ 57
2.5.1
Minimize Power Path DC Resistance ............................................ 57
2.5.2
Minimize Power Delivery Inductance ........................................... 57
2.5.3
Six-Layer Boards ...................................................................... 57
Processor Power Delivery Design Guidelines
3
2.6
2.7
3
LGA775 Information .......................................................................................... 77
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4
2.5.4
Resonance Suppression ............................................................. 64
Electrical Simulation (EXPECTED) ............................................................. 65
LGA1366 Voltage Regulator Configuration Parameters ................................ 76
2.7.1
1366_VR_CONFIG_08B ............................................................. 76
Introduction .......................................................................................... 77
Processor VCC Requirements .................................................................... 77
3.2.1
Socket Loadline Definitions (REQUIRED) ...................................... 77
PSI# Operation ..................................................................................... 90
VTT Requirements (REQUIRED) ................................................................ 91
3.4.1
Electrical Specifications ............................................................. 91
MB Power Plane Layout (REQUIRED) ........................................................ 92
3.5.1
Minimize Power Path DC Resistance ............................................ 92
3.5.2
Minimize Power Delivery Inductance ........................................... 92
3.5.3
Four-Layer Boards .................................................................... 92
3.5.4
Six-Layer Boards ...................................................................... 96
3.5.5
Resonance Suppression ............................................................. 96
Electrical Simulation (EXPECTED) ............................................................. 97
LGA775 Voltage Regulator Configuration Parameters................................ 106
3.7.1
775_VR_CONFIG_04A ............................................................. 106
3.7.2
775_VR_CONFIG_04B ............................................................. 107
3.7.3
775_VR_CONFIG_05A ............................................................. 107
3.7.4
775_VR_CONFIG_05B ............................................................. 108
3.7.5
775_VR_CONFIG_06 ............................................................... 108
LGA1156 Information ...................................................................................... 109
4.1
4.2
4.3
4.4
4.5
4.6
Introduction ........................................................................................ 109
4.1.1
Applications ........................................................................... 109
Processor VCC Requirements .................................................................. 109
4.2.1
Loadline Definitions (REQUIRED) .............................................. 109
LGA 1156 Specific Signals ..................................................................... 114
4.3.1
Power-on Configuration (POC) Signals on VID (REQUIRED) .......... 114
MB Power Plane Layout (REQUIRED) ...................................................... 114
4.4.1
Minimize Power Path DC Resistance .......................................... 114
4.4.2
Minimize Power Delivery Inductance ......................................... 115
4.4.3
Four-Layer Boards .................................................................. 115
4.4.4
Six-layer Boards ..................................................................... 118
4.4.5
Resonance Suppression ........................................................... 118
Electrical Simulation (EXPECTED) ........................................................... 119
LGA1156 Voltage Regulator Configuration Parameters .............................. 127
Appendix A
Z(f) Impedance References .............................................................................. 129
Appendix B
Audible Noise Reduction .................................................................................. 131
4
Processor Power Delivery Design Guidelines
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1-1. Examples of High Volume Manufacturing Loadline Violations .................. 16
1-2. High Volume Manufacturing Compliant Loadline ................................... 16
1-3. Processor D-VID Loadline Transition States ......................................... 21
1-4. VRD11.1 D-VID Transition Timing States (6.25 mV VID Resolution)........ 23
1-5. Overshoot and Undershoot During Dynamic VID Validation .................... 23
1-6. VRD11 DVID Transition Timing States (12.5 mV VID Resolution)............ 24
1-7 Overshoot and Undershoot during Dynamic VID Validation ..................... 25
1-8. Graphical Representation of Overshoot Parameters .............................. 27
1-9. Processor Overshoot in High Volume Manufacturing .............................. 27
1-10. Example VCC Overshoot Waveform .................................................... 28
1-11. Start Up Sequence (Timing is not to scale, details in Table 1-7) ........... 30
1-12 Power-off timing sequence (Timing is not to scale, details in Table 1-7) . 31
1-13. TD7 Reference Levels...................................................................... 31
1-14. Start Up Sequence Functional Block Diagram ..................................... 32
1-15. D-VID Bus Topology ....................................................................... 34
1-16. PROCHOT# Load External to Processor.............................................. 45
2-1. Loadline Window for 1366_VR_CONFIG_08B ....................................... 49
2-2. 200 Hz, 100 A Step Droop Waveform.................................................. 51
2-3. 250 kHz, 100 A Step Waveform ......................................................... 51
2-4. Power Distribution Impedance versus Frequency .................................. 52
2-5. Window for VTT Voltage on LGA1366 Platforms ..................................... 54
2-6. Reference Board Layer Stack-up ........................................................ 58
2-7. Layer 1 VCC Shape for Intel® Reference Six-layer Motherboard ............... 59
2-8. Layer 2 VSS Routing for Intel® Reference Six-layer Motherboard ............. 60
2-9. Layer 3 VCC Routing for Intel® Reference Six-layer Motherboard ............. 61
2-10. Layer 4 VCC Shape for Intel® Reference Six-layer Motherboard ............. 62
2-11. Layer 5 VSS Shape for Intel® Reference Six-layer Motherboard ............. 63
2-12. Layer 6 VCC Shape for Intel® Reference Six-layer Motherboard ............. 64
2-13. Simplified Reference Block Diagram .................................................. 65
2-14. Example Voltage Droop Observed At Node ‘Sense’ .............................. 67
2-15. Current Step Observed Through I_PWL ............................................. 68
2-16. Schematic Diagram for the Six-Layer Intel® Reference Motherboard ..... 69
2-17. Node Location for the Schematic of Figure 2-16 ................................. 70
2-18. Schematic Representation of Bulk Decoupling Capacitors .................... 71
2-19. Schematic Representation of Mid-frequency Decoupling Capacitors ....... 72
2-20. Schematic Representation of Socket Model ........................................ 74
2-21. Current Load Step Profile for I_PWL .................................................. 75
3-1. Socket Loadline Window for 775_VR_CONFIG_04A ............................... 79
3-2. Piece-wise Linear Socket Loadline ...................................................... 80
3-3. Socket Loadline Window for 775_VR_CONFIG_04B, 05A, 05B
(0–100 kHz loadstep rate) ................................................................. 81
3-4. Socket Loadline Window for 775_VR_CONFIG_04B, 05A, 05B
(>100 kHz–1 MHz loadstep Rate) ...................................................... 82
3-5. Socket Loadline Window for Design Configurations 775_VR_CONFIG_06
(0–100 kHz Loadstep Rate) ................................................................ 83
3-6. Socket Loadline Window for Design Configurations 775_VR_CONFIG_06
(>100 kHz-1 MHz Loadstep Rate) ...................................................... 84
3-7. VRD Phase Orientation ...................................................................... 85
Processor Power Delivery Design Guidelines
5
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3-8. Examples of High Volume Manufacturing Loadline Violations .................. 86
3-9. High Volume Manufacturing Compliant Loadline ................................... 87
3-10. 200 Hz, 100 A Step Droop Waveform ................................................ 88
3-11. 250 kHz, 100 A Step Waveform........................................................ 88
3-12. Power Distribution Impedance versus Frequency ................................ 89
3-13. Reference Board Layer Stack-up....................................................... 93
3-14. Layer 1 VCC Shape for Intel® Reference Four-layer Motherboard ........... 94
3-15. Layer 2 VSS Routing for Intel® Reference Four-layer Motherboard ......... 95
3-16. Layer 3 VSS Routing for Intel® Reference Four-layer Motherboard ......... 95
3-17. Layer 4 VCC Shape for Intel® Reference Four-layer Motherboard ........... 96
3-18. Simplified Reference Block Diagram .................................................. 97
3-19. Example Voltage Droop Observed At Node ‘N2’ .................................. 99
3-20. Current Step Observed Through I_PWL ........................................... 100
3-21. Schematic Diagram for the Four-layer Intel® Reference Motherboard .. 101
3-22. Node Location for the Schematic of Figure 3-21 ............................... 102
3-23. Schematic Representation of Decoupling Capacitors ......................... 103
3-24. Schematic Representation of Decoupling Capacitors ......................... 104
3-25. Current Load Step Profile for I_PWL ................................................ 105
4-1. Loadline Window for 1156_VR_CONFIG_09B ..................................... 110
4-2. Power Distribution Impedance versus Frequency ................................ 113
4-3. Reference Board Layer Stack-up ...................................................... 115
4-4. Layer 1 VCC Shape for Intel® Reference Four-layer Motherboard ........... 116
4-5. Layer 2 VSS Routing for Intel® Reference Four-layer Motherboard ......... 117
4-6. Layer 3 VSS Routing for Intel® Reference Four-layer Motherboard ......... 117
4-7. Layer 4 VCC Shape for Intel® Reference Four-layer Motherboard ........... 118
4-8. Simplified Reference Block Diagram.................................................. 119
4-9. Example Voltage Droop Observed At Node ‘Sense’ ............................. 121
4-10. Current Step Observed Through I_PWL ........................................... 121
4-11. Schematic Diagram for the Four-layer Intel® Reference Motherboard .. 122
4-12. Node Location for the Schematic of Figure 4-11 ............................... 123
4-13. Schematic Representation of Mid-frequency Decoupling Capacitors ..... 123
4-14. Schematic Representation of VR Test Tool Model .............................. 125
4-15. Current Load Step Profile for I_PWL ................................................ 126
4-16. Effect of Output Change on Input Currents ...................................... 132
4-17 Input Voltage Drop Caused by di/dt Event at the Output .................... 132
Processor Power Delivery Design Guidelines
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1-1. Feature Support Terminology .............................................................. 12
1-2. Glossary ........................................................................................... 12
1-3. Loadline Equations ............................................................................ 15
1-4. VCC Overshoot Terminology Table ........................................................ 25
1-5. VCC Overshoot Specifications ............................................................... 25
1-6. Intel® Processor Current Release Values For Overshoot Testing............... 26
1-7. Start Up Sequence Timing .................................................................. 32
1-8. Interface Signal Parameters................................................................ 35
1-9. VR11.1 VID Table (Same as VR11.0 VID Table)..................................... 36
1-10. 1366_VR Efficiency Guidelines ........................................................... 40
1-11. LGA1156_VR Efficiency Guidelines ..................................................... 40
1-12. LGA775_VR Efficiency Guidelines ....................................................... 40
1-13. VR_Ready output signal Specifications ............................................... 42
1-14. Iout Analog Output Requirements ...................................................... 43
1-15. Iout Gain and POC Settings............................................................... 43
1-16. Iout Accuracy Requirements ............................................................. 44
1-17. Thermal Monitor Specifications .......................................................... 45
2-1. Loadline Equations ............................................................................ 48
2-2. VCC Regulator Design Parameters ........................................................ 48
2-3. Loadline Window for 1366_VR_CONFIG_08B......................................... 49
2-4. Loadline Reference Lands for the LGA1366 Socket ................................. 50
2-5. Intel® Processor Current Step Values for Transient Loadline Testing ........ 50
2-6. Impedance Measurement Parameters .................................................. 53
2-7. Window for VTT Voltage on LGA1366 Platforms ...................................... 54
2-8 VTT Parameters................................................................................... 55
2-9. VTT Measurement Lands ..................................................................... 55
2-10. VTT VID Lands ................................................................................. 55
2-11. VTT VID Voltage ............................................................................... 56
2-12. Reference Board Layer Thickness (Prepreg 1080) ................................ 58
2-13. Parameter Values for the Schematic of Figure 2-16 .............................. 69
2-14. Recommended Parameter Values for the Capacitors Models .................. 73
2-15. Recommended Parameter Values for the Socket Model in Figure 2-20 .... 74
2-16. I_PWL Current Parameters for Figure 2-21.......................................... 75
2-17. 1366_VR_CONFIG_08B Specification Input Parameters ........................ 76
3-1. Socket Loadline Equations .................................................................. 77
3-2. VCC Regulator Design Parameters ........................................................ 78
3-3. Socket Loadline Window for 775_VR_CONFIG_04A ................................ 79
3-4. Socket Loadline Window for 775_VR_CONFIG_04B, 05A, 05B
(0–100 kHz loadstep rate) ................................................................. 81
3-5. Socket Loadline Window for 775_VR_CONFIG_04B, 05A, 05B
(>100 kHz-1 MHz loadstep Rate) ....................................................... 82
3-6. Socket Loadline Window for 775_VR_CONFIG_06
(0–100 kHz Loadstep Rate) ................................................................ 83
3-7. Socket Loadline Window for 775_VR_CONFIG_06
(>100 kHz–1 MHz Loadstep Rate) ...................................................... 84
3-8. Socket Loadline Reference Lands ......................................................... 85
3-9. Intel® Processor Current Step Values for Transient Socket loadline
Testing ............................................................................................. 85
Processor Power Delivery Design Guidelines
7
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3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
Impedance Measurement Parameters................................................. 90
VTT Specifications............................................................................. 91
VTT Measurement Lands .................................................................... 91
Reference Board Layer Thickness (Prepreg 1080) ................................ 93
Parameter Values for the Schematic of Figure 3-21 ............................ 101
Recommended Parameter Values for the Capacitors Models
in Figure 3-23 .............................................................................. 103
3-16 Recommended Parameter Values for the Capacitor Models
in Figure 3-23 ............................................................................... 104
3-17. I_PWL Current Parameters for Figure 3-25........................................ 105
3-18. 775_VR_CONFIG_04A Specification Input Parameters ........................ 106
3-19. 775_VR_CONFIG_04B Specification Input Parameters ........................ 107
3-20. 775_VR_CONFIG_05A Specification Input Parameters ........................ 107
3-21. 775_VR_CONFIG_05B Specification Input Parameters ........................ 108
3-22. 775_VR_CONFIG_06 Specification Input Parameters .......................... 108
4-1. Loadline Equations .......................................................................... 109
4-2. VCC Regulator Design Parameters ...................................................... 110
4-3. Loadline Window for 1156_VR_CONFIG_09B....................................... 111
4-4. Loadline Reference Lands for the LGA1156 Socket ............................... 111
4-5. Intel® Processor Current Step Values for Transient Loadline Testing ...... 111
4-6. Impedance Measurement Parameters ................................................ 113
4-7. Reference Board Layer Thickness (Prepreg 1080) ................................ 116
4-8. Parameter Values for the Schematic of Figure 4-11 ............................. 122
4-9. Recommended Parameter Values for the Capacitors Models .................. 124
4-10. Recommended Parameter Values for the Socket Model in Figure 4-14 .. 125
4-11. I_PWL Current Parameters for Figure 4-15........................................ 126
4-12. 1156_VR_CONFIG_09A Specification Input Parameters ...................... 127
4-13. 1156_VR_CONFIG_09B Specification Input Parameters ...................... 127
Processor Power Delivery Design Guidelines
Revision History
Revision
Number
-001
Description
•
Initial release.
Date
September 2009
§
Processor Power Delivery Design Guidelines
9
10
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
1
VRD 11.1 Common Information
This chapter contains information common to all platforms implementing VRD 11.1.
Chapters 2 and beyond contain VRD11.1 information unique to a given platform. Refer
to both chapters 1 and the appropriate follow-on chapter relevant to the platform
under design.
1.1
Applications
This document defines the power delivery feature set necessary to support Intel
processor VCC power delivery requirements for desktop and UP server/workstation
computer systems using the LGA1366, LGA1156, and LGA775 sockets. This includes
design recommendations for DC to DC regulators, which convert the input supply
voltage to a processor consumable VCC voltage along with specific feature set
implementation such as thermal monitoring and dynamic voltage identification.
Hardware solutions for the VCC regulator are dependent upon the processors to be
supported by a specific motherboard. VCC regulator design on a specific board must
meet the specifications of all processors supported by that board. The voltage
regulator configuration for a given processor is defined in that processor datasheet. In
some instances, this data is not published and the proper mapping of processor to
VRD configuration can be found from an authorized Intel representative.
The voltage regulator-down (VRD) designation of this document refers to a regulator
with all components mounted directly on the motherboard for intent of supporting a
single processor.
VR11.1 incorporates all of the VR11 functions with the following changes:
• Iout feature to support LGA1366, and LGA1156 processors.
• Power on configuration (POC), market segment identification (MSID) functions
multiplexed onto VID lines during start up.
• VID_SELECT, VR_FAN and VR10 VID support are removed.
• A Power State Indicator (PSI#) input has been added.
• Single step D-VID added for processor C-state entry and exit.
Processor Power Delivery Design Guidelines
11
VRD 11.1 Common Information
1.2
Terminology
Table 1-1. Feature Support Terminology
Categories
Description
REQUIRED
An essential feature of the design that must be supported to ensure
correct processor and VRD functionality.
EXPECTED
A feature to ensure correct VRD and processor functionality that can
be supported using an alternate solution. The feature is necessary for
consistency among system and power designs and is traditionally
modified only for custom configurations. The feature may be modified
or expanded by system OEMs if the intended functionality is fully
supported.
PROPOSED
A feature that adds optional functionality to the VRD and, therefore, is
included as a design target. May be specified or expanded by system
OEMs.
OPTIONAL
A feature that is not required for processor operation; however,
specific platforms or OEMs may request this feature or function.
Table 1-2. Glossary
Term
12
Description
AVP
Adaptive voltage positioning
BJT
Bi-Polar Junction Transistor
CMRR
Common-mode rejection ratio.
DAC
Digital to Analog Converter.
DCR
Direct Current Resistance.
D-VID
Dynamic Voltage Identification. A low power mode of operation where
the processor instructs the VRD to operate at a lower voltage.
ESL
Effective series inductance.
ESR
Effective series resistance.
FET
Field Effect Transistor.
FR4
A type of printed circuit board (PCB) material.
HVM
High volume manufacturing.
ICC
Processor current.
Itt
Bus current associated with the VTT supply.
LGA1156 socket
The surface mount Zero Insertion Force (ZIF) socket designed to
accept the processors in LGA1156 land grid array packages.
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
Term
Description
LGA1366 socket
The surface mount Zero Insertion Force (ZIF) socket designed to
accept the processors in LGA1366 land grid array packages.
LGA775 socket
The surface mount Zero Insertion Force (ZIF) socket designed to
accept the processors in LGA775 land grid array packages.
A mathematical model that describes voltage current relationship given
system impedance (RLL). The loadline equations is VCC = VID – I*RLL. In
this document, the loadline is referenced at the socket unless otherwise
stated.
Loadline
The loadline defines the characteristic impedance of the motherboard
power delivery circuit to the node of regulation. In conjunction with
mid-frequency decoupling, bulk decoupling, and robust power plane
routing, design compliance to this parameter ensures that the
processor voltage specifications are satisfied.
MLCC
Multi-layer ceramic capacitor.
MOSFET
Metal Oxide Semiconductor Field Effect Transistor.
OCP
Over current protection.
OVP
Over voltage protection.
Processor Datasheet
A document that defines the processor electrical, mechanical, and
thermal specifications.
PROCHOT#
Under thermal monitoring, the VRD asserts this processor input to
indicate an over-temperature condition has occurred. Assertion of this
signal places the processor in a low power state, thereby cooling the
voltage regulator.
PWM
Pulse width modulation.
RDS-ON
FET source to drain channel resistance when bias on.
RLL
Loadline impedance. Defined as the ratio: Voltage droop/current step.
This is the loadline slope.
RSS
Root Sum Square. A method of adding statistical variables.
Slope
Loadline resistance. See RLL.
Static Loadline
DC resistance at the defined regulation node. Defined as the quotient of
voltage and current (V/I) under steady state conditions. This value is
configured by proper tuning of the PWM controller voltage positioning
circuit.
Thermal Monitor
A feature of the voltage regulator that places the processor in a low
power state when critical VRD temperatures are reached, thereby
reducing power and VRD temperature.
TOB
Vcc regulation tolerance band. Defines the voltage regulator’s 3-σ
voltage variation across temperature, manufacturing variation, and
aging factors. Must be ensured by design through component selection.
Defined at processor maximum current and maximum VID levels.
Processor Power Delivery Design Guidelines
13
VRD 11.1 Common Information
Term
Description
Transient Loadline
Equal to dV/di or Vdroop/Istep and is controlled by switching
frequency, decoupling capacitor selection, motherboard layout
parasitics.
UVLO
Under-voltage lock-out
Vcc
Processor core voltage defined in the processor datasheet.
VID
Voltage Identification: A code supplied by the processor that
determines the reference output voltage to be delivered to the
processor Vcc lands. At zero amperes and the tolerance band at + 3-σ,
VID is the voltage at the processor.
VR_TDC
Voltage Regulator Thermal Design Current. The sustained DC current
which the voltage regulator must support under the system defined
cooling solution.
VRD
Voltage regulator down. A VR circuit resident on the motherboard.
VRM
Voltage regulator module that is socketed to a motherboard.
VTT
Voltage provided to the processor to initiate power up and drive I/O
buffer circuits.
1.3
Processor VCC Requirements
1.3.1
Voltage and Current (REQUIRED)
An 8-bit VID code supplied by the processor to the VRD determines a reference output
voltage as described in Section 1.6.1. The loadlines described in subsequent parts of
this document show the relationship between VCC and ICC for the processor.
Intel performs testing against multiple software applications and software test vectors
to identify valid processor VCC operating ranges. Failure to satisfy the loadline, loadline
tolerance band, and overshoot voltage specifications may invalidate Intel warranties
and lead to premature processor failure, intermittent system lock-up, and/or data
corruption.
1.3.2
Loadline Definitions (REQUIRED)
To maintain processor reliability and performance, platform DC voltage regulation and
transient-droop noise levels must always be contained within the Vccmin and Vccmax
loadline boundaries (known as the loadline window). Loadline compliance must be
ensured across component manufacturing tolerances, thermal variation, and age
degradation. Loadline boundaries are defined by the following equations in conjunction
with the VCC regulator design parameter values defined in the subsequent sections of
this document. Loadline voltage tolerance is defined in Section 1.3.4. In these
equations, VID, RLL, and TOB are known. Plotting VCC while varying ICC from 0 A to
Iccmax establishes the Vccmax and Vccmin loadlines. Vccmax establishes the
maximum DC loadline boundary. Vccmin establishes the minimum AC and DC voltage
14
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
boundary. Short transient bursts above the Vccmax loadline are permitted; this
condition is defined in Section 1.3.7.
Table 1-3. Loadline Equations
Loadline
Equation
Equation 1: Vccmax Loadline
VCC = VID – (RLL* Icc)
Equation 2: Vcctyp Loadline
VCC = VID – TOB – (RLL* Icc)
Equation 3: Vccmin loadline
VCC = VID – 2*TOB – (RLL* Icc)
Loadline recommendations are established to provide guidance for satisfying
processor loadline specifications, which are defined in processor datasheets. Loadline
requirements must be satisfied at all times and may require adjustment in the loadline
value. The processor loadlines are defined in the applicable processor datasheet.
VRD designs must be loadline compliant across the full tolerance band window to
avoid data corruption, system lock-up, and reduced performance. When validating a
system’s loadline, a single measurement is statistically insignificant and cannot
represent the response variation seen across the entire high volume manufacturing
population of VRD designs. A typical loadline may fit in the specification window;
however, designs residing elsewhere in the tolerance band distribution may violate the
specifications. Figure 1-1 Example A shows a loadline that is contained in the
specification window and, this single instance, complies with Vccmin and Vccmax
specifications. The positioning of this loadline will shift up and down as the tolerance
drifts from typical to the design limits. Figure 1-1 Example B shows that Vccmax limits
will be violated as the component tolerances shift the loadline to the upper tolerance
band limits. Figure 1-1 Example C shows that the Vccmin limits will be violated as the
component tolerances shift the loadline to the lower tolerance band limits.
To satisfy specifications across high volume manufacturing variation, a typical loadline
must be centered in the loadline window and have a slope equal to the value specified
in the subsequent sections of this document that apply to the processor being used.
Figure 1-2 Example A shows a loadline that meets this condition. Under full 3-σ
tolerance band variation, the loadline slope will intercept the Vccmax loadline
(Figure 1-2 Example B) or Vccmin loadline (Figure 1-2 Example C) limits.
Processor Power Delivery Design Guidelines
15
VRD 11.1 Common Information
Figure 1-1. Examples of High Volume Manufacturing Loadline Violations
Measured Load Line
VID
Vccmax LL VID
3-σ Manufacturing LL
Vccmax LL
Vccmin LL
Vccmin LL
Example A: This load line
satisfies voltage limits, but will
violate specifications as the VR
TOB varies across the minimum
to maximum range
VID
Vccmax
Violation
3-σ Manufacturing LL
Vccmax LL
Vccmin LL
Vccmin
Violation
Example C: Vccmin violation
Example B: Vccmax violation
when component tolerance shift when component tolerance shift
Load Line to the lower TOB
Load Line to the upper TOB
limits
limits
Figure 1-2. High Volume Manufacturing Compliant Loadline
3-σ Manufacturing LL
Measured Load Line
VID
Vccmax LL
VID
Vccmin LL
Example A: Measured load line
satisfies slope specification
and is centered in the LL
window
1.3.3
Vccmax LL
3-σ Manufacturing LL
Vccmax LL
VID
Vccmin LL
Vccmin LL
Example B: When component
tolerances shift the load line to
the lower TOB limits, the 3-σ
manufacturing LL is bounded by
the Vccmin LL
Example C: When component
tolerances shift the load line to
the upper TOB limits, the 3-σ
manufacturing load line is
bounded by the Vccmax LL
VRD Output Filter (REQUIRED)
Desktop processor voltage regulators include an output filter consisting of large bulk
decoupling capacitors to compensate for large transient voltage swings and small
value ceramic capacitors to provide mid-frequency decoupling. This filter must be
designed to stay within loadline specifications across tolerances due to age
degradation, manufacturing variation, and temperature drift.
The VRD output filter needs to be designed for the VR controller that is used. Different
controllers can have different filter requirements for meeting the loadline
requirements.
16
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
1.3.3.1
Bulk Decoupling
Bulk decoupling is necessary to maintain VCC within loadline limits prior to the VRD
controller response. Design analysis shows that bulk decoupling requirements will vary
with the number of VRD phases and the FET switching frequency.
The D-VID mode of operation is directly impacted by the choice of bulk capacitors and
output inductor value in the VRD output filter. It is necessary to minimize VCC settling
time during D-VID operation to hasten the speed of core power reduction. The speed
of recovery is directly related to the RCL time constant of the output filter. To ensure
an adequate thermal recovery time, it is recommended to design the output filter with
a minimal output inductor value and a minimal amount of bulk capacitance with
minimum ESR, while providing a sufficient amount of decoupling to maintain loadline
and ripple requirements. At this time, high-density aluminum poly capacitors with
5 mΩ average ESR have been identified as the preferred solution. Failure to satisfy
the VCC settling time requirements defined in Section 1.3.6 may invalidate processor
thermal modes.
1.3.3.2
Mid-frequency Decoupling
The output filter includes mid-frequency decoupling to ensure ripple and package
noise is suppressed to specified levels. Ripple limits are defined in Section 1.3.4.4 and
package noise limits are defined in appropriate processor datasheets in the form of a
processor loadline.
High Mid-frequency noise and ripple suppression are best minimized by 10 µF, 22 µF,
or 47 µF multi-layer ceramic capacitors (MLCCs). It is recommended to maximize the
MLCC count in the socket cavity to help suppress transients induced by processor
packaging hardware. Remaining MLCCs should be first placed adjacent to the socket
edge in the region between the socket cavity and the voltage regulator.
Intel recommends a mid-frequency filter consisting of MLCCs distributed uniformly
through the socket cavity region. The cavity-capacitor ESL value needs to be low
enough to ensure the VR filter impedance is at or below the loadline target up to Fbreak
frequency as described in subsequent sections of this document relating to the
processor the VR is being designed for. To ensure functionality with all Intel
processors, adoption of the reference solution accompanied by full processor loadline
validation is strongly recommended.
Noise is directly dependent upon the processor core frequency, so the filter must
ensure adequate decoupling to support all frequencies the board is to support.
Impedance measurements as described in subsequent sections of this document
relating to the processor the VR is being designed for will help the designer analyze
the MLCC decoupling solution.
Processor Power Delivery Design Guidelines
17
VRD 11.1 Common Information
1.3.4
TOB — Voltage Tolerance Band (REQUIRED)
Processor loadline specifications must be ensured across component process variation,
system temperature extremes, and age degradation limits. The VRD topology and
component selection must maintain a 3-σ tolerance of the VRD Tolerance Band around
the typical loadline. The critical parameters include voltage ripple, VRD controller
tolerance, and current sense tolerance under both static and transient conditions.
Individual tolerance components will vary among designs; the processor requires only
that the total error stack-up stay within the defined VR configuration tolerance band
under the conditions defined in the subsequent sections of this document relating to
the processor the VR is being designed for.
1.3.4.1
PWM Controller Requirements
To ensure designers can satisfy the required VRD tolerance band across all modes of
operation, PWM controller vendors must publish data and collateral that is critical for
satisfying design requirements. This includes support of the following:
• The PWM vendor is to define equations for calculating the VRD TOB with Inductor
DCR sensing and resistor sensing. The equation is to include all parameter
dependencies such as AVP tolerance, age degradation, thermal drift, sense
element DC and AC accuracy, etc under 3-σ variation. These equations are to be
published in the PWM controller data sheet. The vendor is to distribute and
support a tolerance band calculator that communicates the VRD TOB for each
valid VID under each VID table.
• Total PWM controller DC set point accuracy is typically <0.5% over temperature,
component age, and lot to lot variation over the 1.0–1.6 V VID range. DAC error
may be larger for voltages below 1 V under the assumption that the required Vmin
TOB requirements are always satisfied. Typical low voltage accuracy is ± 5 mV for
0.8 V – 1.0 V VID and ± 8 mV for 0.5–0.8 V VID. Each vendor is to publish PWM
controller DAC accuracy by VID value in the component data sheet.
• The PWM controller must support voltage amplitudes read across sense elements
with a DCR of 0.1–2.0 mΩ. PWM controller vendors must define the minimum
sense signal voltage necessary to satisfy PWM signal to noise ratio requirements.
These requirements are to be published by the vendor in their PWM controller
datasheet.
1.3.4.2
Loadline Thermal Compensation (REQUIRED)
Thermal compensation allows the voltage regulator to respond to temperature drift in
VRD electrical parameters. It is required to ensure that regulators using inductor
current sensing maintain a stable voltage over the full range of load current and
system temperatures.
If thermal compensation is not included, the output voltage of the regulator will droop
as the resistance of the sense element increases with temperature. With the increased
resistance, the regulator falsely detects an increase in load current and regulates to a
lower voltage. Thermal compensation prevents this thermally induced voltage droop
by adjusting the feedback path based on the temperature of the regulator. This is
accomplished by placing a thermistor in the feedback network, tuned with a resistor
network to negate the effects of the increased resistance of the sense element.
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Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
The thermal compensation circuit is to be validated by running the regulator at the
Voltage Regulator Thermal Design Current (VRTDC) and minimum required air flow for
30 to 45 minutes. This is to ensure the board is thermally stable and system
temperatures have reached a maximum steady state condition. If the thermal
compensation has been properly implemented, the output voltage will only drift
1–2 mV from its coolest temperature condition. If the thermal compensation has not
been properly implemented, the voltage can droop in the tens of mV range.
1.3.4.3
Dynamic Voltage Identification (D-VID) TOB
During the D-VID (see Section 1.3.6) mode of operation, VRD tolerance band
requirements must be satisfied. Minimum voltage cannot fall below the values
predicted by Equation 3 assuming any possible VID setting along with the RLL a TOB
values defined in the VCC Regulator Design Parameters Tables in the appropriate
subsequent sections of this document. Current values to be used for assessing TOB
during dynamic VID should be linearly scaled with voltage. For example, if a 90 A of
current is defined at a VID of 1.1 V and the functional VID value is 0.6 V, then the
TOB should be calculated assuming (0.6 V/1.1 V) x 90 A = 49 A.
Vccmax VRD TOB can be relaxed during dynamic VID. Positive tolerance variation is
permitted and is to be bounded by the voltages predicted by Equation 1, where VID is
the standard VID value in regulation when not in the D-VID mode.
1.3.4.4
Ripple Voltage (Required)
To meet tolerance band specifications, high and low frequency ripple is to be limited
to 10 mV peak to peak. Measurements must be taken carefully to ensure that
superposition of high frequency with low frequency oscillations do not sum to a value
greater than 10 mV peak to peak. Measurements are to be taken with a 20 MHz band
limited oscilloscope. Ripple testing is to be performed at 5 A minimum loading and at
VR TDC. When PSI# is asserted and the VR is operating in the PSI# mode, the ripple
voltage can be 20 mV peak to peak.
1.3.4.5
Sense Topology Requirements
VRD designers must construct a sense topology that ensures compliance to tolerance
band specifications under standard operation and under the D-VID mode of operation.
This includes selection of sense elements and supporting components that satisfy
tolerance requirements with the chosen PWM controller and ripple amplitude.
Inductor DCR or resistor sensing topologies are required to satisfy tolerance band
requirements. Current sensing across MOSFET Rds-on is not suitable for loadline AVP
functions due to the large variation in this parameter. Evaluation of this sense method
has shown that the TOB requirements cannot be satisfied unless expensive, <10%
tolerance MOSFETs are chosen.
1.3.4.6
Error Amplifier Specification (EXPECTED)
The PWM error amplifier should be designed with a sufficient gain bandwidth product
to ensure duty cycle saturation does not occur with large signal current transients.
Typical target closed loop VR bandwidths of 30–200 kHz (20% of switching frequency
target) are expected in VR11.1 system designs. The output of the error amplifier
should also have high slew rates to avoid duty cycle saturation. Performance
limitations must be included in the VRD TOB equations.
Processor Power Delivery Design Guidelines
19
VRD 11.1 Common Information
1.3.4.7
PWM Operating Frequency (EXPECTED)
VR11.1 PWM must be designed to work across a wide range of switching frequencies.
For the desktop and UP server/workstation market, this can range from 200 kHz up to
1 MHz and corresponding loop bandwidths of 30 kHz to 250 kHz respectively. The
tolerance of the PWM oscillator should be <10%. Performance limitations must be
included in the VRD TOB equations.
1.3.5
Stability (REQUIRED)
The VRD must be unconditionally stable under all DC and transient conditions across
the voltage and current ranges defined in the VCC Regulator Design Parameters Tables
in the appropriate subsequent sections of this document. The VRD must also operate
in a no-load condition.
1.3.6
Dynamic Voltage Identification (REQUIRED)
1.3.6.1
Dynamic-Voltage Identification Functionality
VRD11.1 architecture includes the Dynamic Voltage Identification (D-VID) feature set,
which enables the processor to reduce power consumption and processor
temperature. Reference VID codes are dynamically updated by the processor to the
VRD controller using the VID bus when a low power state is initiated. VID codes are
updated sequentially in either 12.5 mV or 6.25 mV steps. The 6.25 mV steps can be
transmitted every 1.25 µs and 12.5 mV steps can be transmitted every 2.5 µs until
the final voltage code is encountered. The VR should settle within 5 mV of the final
value within 15 µs for a D-VID event over 50 mV and within 5 µs for events less than
50 mV in magnitude.
LGA775 processors that will use VR11.1 based PWM controllers will have single step
upward DVID jumps on the order of 100s of mV up to a maximum of 250 mV .
Downward DVID jumps should decay with the processor load current, the VR is not
required to pull down the output voltage. If the PWM receives a single step upward
DVID jump, it should regulate to the new output voltage target with a minimum slew
rate of 10 mV/us. The PWM should not false trip the OCP or OVP monitors during
walking or single step DVID events. The output voltage shall settle to within 5 mV of
the target voltage in less than 8 us. For the 250 mV step, the VR must complete the
transition in 25 us (transition time) + 8 us (settling time) = 33 us total time.
During a D-VID event, the processor load may not be capable of absorbing output
capacitor energy when the VID reference is lowered. As a result, reverse current may
flow into the AC-DC regulator’s input filter, potentially charging the input filter to a
voltage above the over voltage value. Upon detection of this condition, the AC-DC
regulator will react by shutting down the AC-DC regulator supply voltage. The VRD
and AC-DC filter must be designed to ensure this condition does not occur. In
addition, reverse current into the AC-DC regulator must not impair the operation of
the VRD, the AC-DC supply, or any other part of the system.
Under all functional conditions, including D-VID, the VCC supply must satisfy loadline
and overshoot constraints to avoid data corruption, system lock-up events, or system
blue-screen failures.
20
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
Figure 1-3. Processor D-VID Loadline Transition States
Vmax Load Line
2
3
Vcc (Voltage)
Vmin Load Line
1
Original VID
Load Line Window
D-VID Vmax
Load Line
5
4
Low Voltage VID
Load Line Window
D- VID Vmin Load Line
Icc (Amperes)
1.3.6.2
D-VID Validation
Intel processors are capable of generating numerous D-VID states and the VRD must
be designed to properly transition to and function at each possible VID voltage.
However, exhaustive validation of each state is unnecessary and impractical.
Validation can be simplified by verifying the VRD conforms to socket loadline
requirements, tolerance band specifications, and D-VID timing requirements. Then, by
default, each processor D-VID state will be valid. The key variables for VCC under DVID conditions are processor loading, starting VID, ending VID, and VCC slew rate. The
VCC slew rate is defined by VRD bulk decoupling, the output inductors, the switching
FET resistance and the processor load. This indicates that the VCC slewing will have an
exponential behavior, where the response to code ‘n+1’ takes longer to settle than
code ‘n’. As a result, a test from maximum to minimum and from minimum to
maximum will be sufficient to ensure slew rate requirements and VID code regulation.
To ensure support for any valid VID reference, testing should be performed from the
maximum table entry of 1.6 V to the minimum VID table value. For VR11.1, use 0.5 V
for the minimum value. The VRD must ensure that the full table transition occurs
within 15 microseconds of the final VID code transmission. Slew rate timing is
referenced from 0.4 V on the rising edge of the initial VID code to the time the final
voltage is settled within 5 mV of the final VCC value. Intel testing has noted a 10%
change to the VCC slew rate between VRD no load (5 A) and full load (VR TDC)
conditions. For this reason, the VCC slewing must be tested under both loading
conditions.
During the D-VID test defined in the previous paragraph, VCC droop and undershoot
amplitudes must be limited to avoid processor damage and performance failures. If
the processor experiences a voltage undershoot due to D-VID transitions, an
application initiated di/dt droop can superimpose with this event and potentially
violate minimum voltage specifications. Droop during this D-VID test must be limited
to 5 mV. This value was derived by calculating VRD tolerance band improvements at
the low D-VID current and voltage values.
Processor Power Delivery Design Guidelines
21
VRD 11.1 Common Information
1.3.6.2.1
VR11.1 Validation Summary for 6.25 mV VID Resolution
This exercise tests VRD11.1 functionality with 6.25 mV VID resolution. Consult
Figure 1-4 and Figure 1-5 for graphic representation of validation requirements.
1. Constraints:
a.
1.1 V ±5 mV transition must occur within 233.75 μs (see Figure 1-4).
b.
Start time is referenced to 0.4 V on the rising edge of the initial D-VID
code.
c.
End time is referenced to the steady state Vcc voltage after the final
D-VID code.
d.
Undershoot during maximum to minimum VID transition must be
limited to 5 mV. This 5 mV is included within the ±5 mV tolerance on
the final VID value defined under test condition a.
e.
Care must be taken to avoid motherboard and component heat
damage resulting from extended operations with high current draw.
2. Validation exercises:
22
a.
D-VID transition must be validated against above constraints from a
starting VID of 1.6 V to an ending VID of 0.5 V with an applied 5 A
Load.
b.
D-VID transition must be validated against above constraints from a
starting VID of 1.6 V to an ending VID of 0.5 V with an applied VR TDC
Load.
c.
D-VID transition must be validated against above constraints from a
starting VID of 0.5 V to an ending VID of 1.6 V with an applied 5 A
Load.
d.
D-VID transition must be validated against above constraints from a
starting VID of 0.5 V to an ending VID of 1.6 V with an applied VR TDC
Load.
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
Figure 1-4. VRD11.1 D-VID Transition Timing States (6.25 mV VID Resolution)
Transition from Min to Max VID
Transition from Max to Min VID
1.6 V
1.6 V
Vcc Voltage
Response
Vcc Voltage
Response
1.1 V
Vcc
1.1 V
Vcc
0.5 V
218.75 µs
15 µs
0.5 V
Initial
VID Code
Final
VID Code
218.75 µs
15 µs
Time (µs)
Time (µs)
Initial
VID Code
Final
VID Code
233.75 µs maximum
233.75 µs maximum
Figure 1-5. Overshoot and Undershoot During Dynamic VID Validation
Transition From Max to Min VID
1.6 V
Transition From Min to Max VID
1.6 V
Limit undershoot of DC
transition to 5 mV
Vcc
Vcc
Must be compliant to
overshoot specifications
0.5 V
0.5 V
Time (µs)
Processor Power Delivery Design Guidelines
Time (µs)
23
VRD 11.1 Common Information
1.3.6.2.2
VR11 Validation Summary for 12.5 mV VID Resolution
This exercise tests VRD11 functionality with 12.5 mV VID resolution. Consult
Figure 1-6 and Figure 1-7 for graphic representation of validation requirements.
1. Constraints:
a.
0.7625 V ±5 mV transition must occur within 350 μs (see Figure 1-6).
b.
Start time is referenced to 0.4 V on the rising edge of the initial D-VID
code.
End time is referenced to the steady state VCC voltage after the final
D-VID code.
Undershoot during maximum to minimum VID transition must be
limited to 5 mV. This 5 mV is included within the ±5 mV tolerance on
the final VID value defined under test condition a.
Care must be taken to avoid motherboard and component heat
damage resulting from extended operations with high current draw.
c.
d.
e.
2. Validation exercises
a.
D-VID transition must be validated against above constraints from a
starting VID of 1.6 V to an ending VID of 0.8375 V with an applied 5A
Load.
D-VID transition must be validated against above constraints from a
starting VID of 1.6 V to an ending VID of 0. 8375 V with an applied VR
TDC Load.
D-VID transition must be validated against above constraints from a
starting VID of 0.8375 V to an ending VID of 1.6 V with an applied 5 A
Load.
D-VID transition must be validated against above constraints from a
starting VID of 0.8375 V to an ending VID of 1.6 V with an applied VR
TDC Load.
b.
c.
d.
Figure 1-6. VRD11 DVID Transition Timing States (12.5 mV VID Resolution)
Transition from Max to Min VID
1.6 V
1.6 V
50 µs
0.7625 V
Vcc
Vcc
300 µs
0.7625 V
Vcc Voltage
Response
0.8375 V
Transition from Min to Max VID
0.8375 V
Time (µs)
Initial
VID Code
Final
VID Code
350 µs maximum
24
Vcc Voltage
Response
300 µs
50 µs
Time (µs)
Initial
VID Code
Final
VID Code
350 µs maximum
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
Figure 1-7 Overshoot and Undershoot during Dynamic VID Validation
Transition From Min To Max VID
Transition From Max To Min VID
1.6V
1.6V
Limit undershoot of DC
transition to 5mV
Vcc
Vcc
Must be compliant to
overshoot specifications
0.8375V
0.8375V
Time (µs)
1.3.7
Processor VCC Overshoot (REQUIRED)
1.3.7.1
Specification Overview
Time (µs)
Intel desktop processors in VRD11.1 systems are capable of tolerating short transient
overshoot events above VID on the VCC supply that will not impact processor lifespan
or reliability. Maximum processor VCC overshoot, VOS, cannot exceed VID+VOS-MAX.
Overshoot duration, TOS, cannot stay above VID for a time more than TOS-MAX. See
Table 1-4 and Table 1-5 for details.
Table 1-4. VCC Overshoot Terminology Table
Parameter
Definition
VOS
Measured peak overshoot voltage
VOS-MAX
Maximum specified overshoot voltage allowed above VID
TOS
Measured overshoot time duration
TOS-MAX
Maximum specified overshoot time duration above VID
Vzc
Zero current voltage: The voltage where the measured loadline intercepts
the voltage axis
Vzco
Zero current offset from VID: Vzco = VID – Vzc
Table 1-5. VCC Overshoot Specifications
Parameter
Specification
VOS_MAX
50 mV
TOS_MAX
25 µs
VOS
Maximum = VID + VOS_MAX
TOS
Maximum = TOS_MAX
Maximum overshoot is validated by monitoring the voltage across the recommended
test lands (defined in Section 1.3.2) while applying a current load release across the
Processor Power Delivery Design Guidelines
25
VRD 11.1 Common Information
socket VCC and VSS land field. Amperage values for performing this validation under
each VRD design configuration are identified in Table 1-6. The platform voltage
regulator output filter must be stuffed with a sufficient quality and number of
capacitors to ensure that overshoot stays above VID for a time no longer than
TOS-MAX and never exceeds the maximum amplitude of VID+VOS_MAX.
Measurements are to be taken using an oscilloscope with a 20 MHz bandwidth. Boards
in violation must be redesigned for compliance to avoid processor damage.
Table 1-6. Intel® Processor Current Release Values For Overshoot Testing
VR Configuration
Starting Current
Ending Current
Dynamic Current
Step
1156_VR_CONFIG_09A
55 A
5A
50 A
1156_VR_CONFIG_09B
80 A
5A
75 A
1366_VR_CONFIG_08B
105 A
5A
100 A
775_VR_CONFIG_04A
60 A
5A
55 A
775_VR_CONFIG_04B
100 A
5A
95 A
775_VR_CONFIG_05A
70 A
5A
65 A
775_VR_CONFIG_05B
100 A
5A
95 A
55 A
5A
50 A
775_VR_CONFIG_06
To prevent processor damage, VRD designs should comply to overshoot specifications
across the full loadline tolerance band window (see Section 1.3.2). When validating a
system’s overshoot, a single measurement is statistically insignificant and cannot
represent the response variation seen across the entire high volume manufacturing
population of VRD designs. A typical design may fit in the loadline window; however
designs residing elsewhere in the tolerance band distribution may violate the VCC
overshoot specifications. Figure 1-9 provides an illustration of this concept. A typical
board will have the VCC zero current voltage (Vzc) centered in the loadline window at
VID-TOB; for this example consider waveform A and assume TOB is 19 mV. Now
assume that the VRD has maximum overshoot amplitude of VOS_MAX = 50 mV above
VID. Under this single case, the overshoot aligns with the specification limit and there
is zero margin to violation. Under manufacturing variation Vzc can drift to align with
VID (waveform B). This drift will shift the overshoot waveform by the same voltage
level. Since waveform A has zero overshoot amplitude margin, this increase in Vzc
due to manufacturing drift will yield a 19 mV overshoot violation which will reduce the
processor life span. To address this issue in validation, a voltage margining technique
can be employed to ensure overshoot amplitudes stay below a safe value. This
technique translates the specification baseline from VID to a VRD validation baseline
of Vzc + VOS_MAX, which defines a test limit for specification compliance across the
full TOB range:
Equation 4. Overshoot Voltage Limit
VOS < Vzc + VOS_MAX
This equation is to be used during validation to ensure overshoot is in compliance to
specifications across high volume manufacturing variation. In addition, the overshoot
duration must be reference to Vzc and cannot exceed this level for more than 25 µs.
26
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
Figure 1-8. Graphical Representation of Overshoot Parameters
Figure 1-9. Processor Overshoot in High Volume Manufacturing
VID
VOS_MAX = VID+50mV
Waveform “B”
Vccmax Load Line
Vcctyp Load Line
Vcc
Vcc
vzco
VID-Vzc
Icc
Processor Power Delivery Design Guidelines
TOFF
Waveform “A”
Time
27
VRD 11.1 Common Information
Figure 1-10. Example VCC Overshoot Waveform
1.3.8 Example: Socket VCC Overshoot Test
To pass the overshoot specification, the amplitude constraint of Equation 4 and time
duration requirement of TOS_MAX must be satisfied. This example references
Figure 1-10.
Amplitude Test Constraint: Overshoot amplitude, VOS, must be less than Vzc +
VOS_MAX
Input parameters
• VOS= 1.325 V – Obtained from direct measurement
• VZC = 1.285 V – Obtained from direct measurement
• VOS_Max = 0.050 V – An Intel specified value
Amplitude Analysis
• VZC + VOS_MAX = 1.285 V + 0.050 V = 1.335 V
• VOS = 1.325 < 1.335 V
Amplitude Test Satisfied
Time Duration Test Constraint: Overshoot duration above Vzc must be less than
25 µs
Input Parameters
• Initial crossing of overshoot: 15 µs – Obtained from direct measurement
• Final crossing of overshoot: 35 µs – Obtained from direct measurement
• TOS_MAX = 25µs – An Intel specified value
Overshoot Duration Analysis
• TOS = Final Crossing of Vzc – Initial Crossing of Vzc
• TOS = 35 µs – 15 µs = 20 µs < 25 µs = TOS_MAX
Time duration test passed
Amplitude and Time Duration Tests Passed => Overshoot specification is
satisfied.
28
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
1.4
Power Sequencing (REQUIRED)
VR11.1 features a power sequence that is compatible with both VR11 and VR11.1
processors.
Desktop and UP server/workstation VR11.1 systems use a pull-up resistor tied to the
VTT supply as an enable signal. Once the PWM VCC voltage is above its under voltage
lockout (UVLO) threshold, out of configuration states such as reset, and a valid enable
signal is received, the PWM is to initiate the start up sequence with TD1.
The PWM should ramp VCC to the default ‘Vboot’ value and start a timer. It will remain
at the Vboot voltage during Tc and then read in the VID lines and ramp to the
programmed VID voltage. See Figure 1-11 timing diagram for details on the power-on
sequence requirements.
1.4.1
VR_ENABLE
To ensure the that VTTA and VTTD are valid prior to processor VCC, Vtt_PG (the VTTA/VTTD
regulator power good output) should be used as an enable signal for VRD11.1. See
Figure 1-11.
1.4.2
Vboot Voltage Level (REQUIRED)
Vboot is a default power-on VCC value. Upon detection of a valid VTT supply
(VTTPWRGOOD asserted), the PWM controller is to regulate the VRD to this value until
VID codes are read. The Vboot voltage is 1.1 V. During Vboot, the output should
operate with a loadline as if the VID=1.1 V.
1.4.3
Under Voltage Lock Out (UVLO) (REQUIRED)
The PWM IC should detect its voltage rail and remain in the disabled state until a valid
voltage level is available or reached. The voltage level is typically 3.0 V in a 3.3 V
system, 4.0 V in a 5 V system or 7-8 V in a 12 V system. Ultimately the PWM vendor
should set the level to meet his market segment requirements. However, the PWM
and MOSFET driver components should coordinate start up such that both the PWM
input voltage rail and power conversion input voltage rail (typically +12 V) of the buck
converter are both up and valid prior to enabling the PWM function. The PWM and
MOSFET driver component combinations need to be tolerant of any sequencing
combination of 3.3 V, 5 V or 12 V input rails. If the PWM IC voltage rail, MOSFET
driver voltage rail or power conversion rail fall below the UVLO thresholds, the PWM
should shut down in an orderly manner and restart the start up sequence.
Processor Power Delivery Design Guidelines
29
VRD 11.1 Common Information
1.4.4
Soft Start (SS) (REQUIRED)
The PWM controller should have a soft start function to limit inrush current into the
output capacitor bank and prevent false over current protection (OCP) trips. The soft
start should have a ramp of 500 μs as an internally programmed default. A SS pin for
user programmability of SS ramp to extend the ramp to 1–5 ms is required. Consult
Td and Te parameters in Figure 1-11 for further details.
Figure 1-11. Start Up Sequence (Timing is not to scale, details in Table 1-7)
SKTOCC# (ref.)
(socket occupied)
VTT_PG (ref.)
OUTEN asserted after BOTH:
SKTOCC# and VTT_PG are asserted
(to CPU)
VR11.1 OUTEN
Ta
Tc
VBOOT=1.1V
Vcc_CPU
Te
Td
Tb
VR_READY
POC (ref.)
VID [7:0]
1.4.5
VID code read by PWM
at the end of Tc
VID valid
Power-off Timing Sequence (REQUIRED)
There can be a normal or an abnormal power-off, the typical cases are:
1. Normal power-off by de-asserting OUTEN (non-latching)
2. Abnormal power-off due to:
30
•
PWM _Vcc falling out of regulation, below its UVLO threshold
•
VID Off-code sent by CPU
•
OVP condition
•
OCP condition
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
Figure 1-12 Power-off timing sequence (Timing is not to scale, details in Table 1-7)
OUTEN
OR
VID [7:0]
OFF code
Valid
OR
UVL threshold,
PWM IC specific
PWM_Vcc
VR_READY
Tk
VccP
Figure 1-13. TD7 Reference Levels
VTTPWRGOOD
VTTPWRGOOD(min)
VR_READY
VOH(min)
TD7
Processor Power Delivery Design Guidelines
31
VRD 11.1 Common Information
Table 1-7. Start Up Sequence Timing
Start up Delay Parameters
Parameter
Minimum
Typical, Default
Maximum
Ta
0 ms
-
5 ms
Tb
50 µs
500 µs
5 ms
Tc
50 µs
-
3 ms
Td
0 µs
250 µs
3.5 ms
Te
50 µs
-
3 ms
Tk
0 ms
-
500 ms
TD7
0 ms
-
1 ms
Figure 1-14. Start Up Sequence Functional Block Diagram
Vcc
VR11.1 PWM
Enable
+
Vtt_PG
UVLO
-
1ms
Delay
Soft Start
1 V CMOS
SS timer
MSID 110
shown
Vtt
CPU
POC 110
shown
Vtt
Vboot
timer
Vboot
Switch
Vtt
VID0
VID1
VID2
VID
Logic
Vref
PWM logic
VR Ready
VID3
VID4
VID5
VID6
VID7
Note: Pull-up, Pull-dn resistors on VID(0:7) program POC and MSID values to the CPU
NOTE:
32
MSID and POC settings shown are for example only.
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
1.5
VRD Current Support (Required)
System boards supporting Intel processors must have voltage regulator designs
compliant to electrical and thermal standards defined in the VCC Regulator Design
Parameter table in the section specific for the processor being supported. This
includes full electrical support of Iccmax specifications and robust cooling solutions to
support defined thermal design current (VR TDC) indefinitely within the envelope of
system operating conditions. This includes regulator layout, processor fan selection,
ambient temperature, chassis configuration, etc. Consult the VCC Regulator Design
Parameter table in the section specific for the processor being supported for processor
VCC and VTT current limits.
Intel processor VR TDC is the sustained (DC equivalent) current that is to be used for
voltage regulator thermal design with supporting Thermal Monitor circuitry (see
Section 1.9.2). At VR TDC, components such as switching FETs and inductors reach
maximum temperature, heating the motherboard layers and neighboring components
to the pass/fail boundary of thermal limits. Thermal analysis must include current
contributions of both the VCC and VTT regulators. In some instances the processor VRD
will also power other motherboard components. Under this condition the VRD will
supply current above the VR TDC limits; system designers must budget this additional
current support in final VRD designs while remaining compliant to electrical and
thermal specifications.
To avoid heat related failures, desktop computer systems should be validated for
thermal compliance under the envelope of system operating conditions.
1.5.1
Phase Count Requirement
The PWM controller will be used in DC-DC converters that support processors from
30 A to 145 A TDC. It is expected that the PWM chip manufacturer will determine the
optimal number of phases for a low cost design and allow for flexible implementations
to meet various market segment requirements.
Processor Power Delivery Design Guidelines
33
VRD 11.1 Common Information
1.6
Control Inputs to VRD
1.6.1
Voltage Identification (VID [7:0]) (REQUIRED)
The VRD must accept an 8-bit code transmitted by the processor to establish the
reference VCC operating voltage.
When an ‘OFF’ VID code appears at the input to the PWM controller, the DC-DC is to
turn off the VCC output within 0.5 seconds and latch off until power is cycled.
While operating in the D-VID mode, Intel processors can transmit VID codes across
the eight bit bus with a data transmission rate of up to 1.25 µs. To properly design
this bus against timing and signal integrity requirements (Table 1-8), the following
information is provided. The VID buffer circuit is a push-pull CMOS circuit
configuration. The worst-case settling time requirement for code transmission at each
load is 200 nanoseconds, including line-to-line skew. VRD controller VID inputs should
contain circuitry to detect a change and prevent false tripping or latching of VID codes
during this 200-nanosecond window.
Intel recommends use of the D-VID bus topology described in Figure 1-15 and
Table 1-8. Under these conditions, traces can be routed with micro strip, strip line, or
a combination with a maximum of four layer transitions. The main trace length can
vary between ½ inch and 15 inches with a maximum recommended line to line skew
of 1 inch. Pull-up/down resistors are only necessary for MSID and/or POC
requirements.
Some designs may require additional VID bus loads. In this case, care should be taken
to design the topology to avoid excessive undershoot and overshoot at each load.
Failure to comply with these limits may lead to component damage or cause
premature failure. The responsible engineer must identify minimum and maximum
limits of each component and design a topology that ensures voltages stay within
these limits at all times.
Figure 1-15. D-VID Bus Topology
VTT or VSS
VID lines should be pulled up or down
for MSID and/or POC as required
MSID and/or POC
L2
Processor
PWM Controller
VID
L1
34
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
Table 1-8. Interface Signal Parameters
Design Parameter
Minimum
Typical
Maximum
—
VTT 1
—
- 0.100 V
—
VTT 2
VIH
0.8 V
—
—
VIL
—
—
0.3 V
L1, VID trace length
0.5 inch
—
15 inches
L2, VTT Stub Length
0 inch
—
1 inch
—
1.0 inch
—
5 mils
—
—
5 mils
—
—
950 Ω
1 kΩ
1050 Ω
20 µA
—
200 µA
VID Bus Voltage
Voltage Limits At Processor VID Lands
VID trace length skew
VID trace width
VID trace separation
MSID and/or POC Resistors (RTT)
4
Processor CMOS driver leakage current
NOTES:
1.
2.
3.
4.
VTT specifications are listed in the processor specific sections of this document
Consult the processor datasheet for signal overshoot limits
VRD11.1 PWM leakage should be 10 µA maximum.
Not Applicable to LGA775 designs
Processor Power Delivery Design Guidelines
35
VRD 11.1 Common Information
Table 1-9. VR11.1 VID Table (Same as VR11.0 VID Table)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
Voltage
0
0
0
0
0
0
0
0
OFF
0
1
0
1
1
0
1
1
1.04375
0
0
0
0
0
0
0
1
OFF
0
1
0
1
1
1
0
0
1.03750
0
0
0
0
0
0
1
0
1.60000
0
1
0
1
1
1
0
1
1.03125
0
0
0
0
0
0
1
1
1.59375
0
1
0
1
1
1
1
0
1.02500
0
0
0
0
0
1
0
0
1.58750
0
1
0
1
1
1
1
1
1.01875
0
0
0
0
0
1
0
1
1.58125
0
1
1
0
0
0
0
0
1.01250
0
0
0
0
0
1
1
0
1.57500
0
1
1
0
0
0
0
1
1.00625
0
0
0
0
0
1
1
1
1.56875
0
1
1
0
0
0
1
0
1.00000
0
0
0
0
1
0
0
0
1.56250
0
1
1
0
0
0
1
1
0.99375
0
0
0
0
1
0
0
1
1.55625
0
1
1
0
0
1
0
0
0.98750
0
0
0
0
1
0
1
0
1.55000
0
1
1
0
0
1
0
1
0.98125
0
0
0
0
1
0
1
1
1.54375
0
1
1
0
0
1
1
0
0.97500
0
0
0
0
1
1
0
0
1.53750
0
1
1
0
0
1
1
1
0.96875
0
0
0
0
1
1
0
1
1.53125
0
1
1
0
1
0
0
0
0.96250
0
0
0
0
1
1
1
0
1.52500
0
1
1
0
1
0
0
1
0.95625
0
0
0
0
1
1
1
1
1.51875
0
1
1
0
1
0
1
0
0.95000
0
0
0
1
0
0
0
0
1.51250
0
1
1
0
1
0
1
1
0.94375
0
0
0
1
0
0
0
1
1.50625
0
1
1
0
1
1
0
0
0.93750
0
0
0
1
0
0
1
0
1.50000
0
1
1
0
1
1
0
1
0.93125
0
0
0
1
0
0
1
1
1.49375
0
1
1
0
1
1
1
0
0.92500
0
0
0
1
0
1
0
0
1.48750
0
1
1
0
1
1
1
1
0.91875
0
0
0
1
0
1
0
1
1.48125
0
1
1
1
0
0
0
0
0.91250
0
0
0
1
0
1
1
0
1.47500
0
1
1
1
0
0
0
1
0.90625
0
0
0
1
0
1
1
1
1.46875
0
1
1
1
0
0
1
0
0.90000
0
0
0
1
1
0
0
0
1.46250
0
1
1
1
0
0
1
1
0.89375
0
0
0
1
1
0
0
1
1.45625
0
1
1
1
0
1
0
0
0.88750
0
0
0
1
1
0
1
0
1.45000
0
1
1
1
0
1
0
1
0.88125
0
0
0
1
1
0
1
1
1.44375
0
1
1
1
0
1
1
0
0.87500
0
0
0
1
1
1
0
0
1.43750
0
1
1
1
0
1
1
1
0.86875
0
0
0
1
1
1
0
1
1.43125
0
1
1
1
1
0
0
0
0.86250
0
0
0
1
1
1
1
0
1.42500
0
1
1
1
1
0
0
1
0.85625
0
0
0
1
1
1
1
1
1.41875
0
1
1
1
1
0
1
0
0.85000
0
0
1
0
0
0
0
0
1.41250
0
1
1
1
1
0
1
1
0.84375
36
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
Voltage
0
0
1
0
0
0
0
1
1.40625
0
1
1
1
1
1
0
0
0.83750
0
0
1
0
0
0
1
0
1.40000
0
1
1
1
1
1
0
1
0.83125
0
0
1
0
0
0
1
1
1.39375
0
1
1
1
1
1
1
0
0.82500
0
0
1
0
0
1
0
0
1.38750
0
1
1
1
1
1
1
1
0.81875
0
0
1
0
0
1
0
1
1.38125
1
0
0
0
0
0
0
0
0.81250
0
0
1
0
0
1
1
0
1.37500
1
0
0
0
0
0
0
1
0.80625
0
0
1
0
0
1
1
1
1.36875
1
0
0
0
0
0
1
0
0.80000
0
0
1
0
1
0
0
0
1.36250
1
0
0
0
0
0
1
1
0.79375
0
0
1
0
1
0
0
1
1.35625
1
0
0
0
0
1
0
0
0.78750
0
0
1
0
1
0
1
0
1.35000
1
0
0
0
0
1
0
1
0.78125
0
0
1
0
1
0
1
1
1.34375
1
0
0
0
0
1
1
0
0.77500
0
0
1
0
1
1
0
0
1.33750
1
0
0
0
0
1
1
1
0.76875
0
0
1
0
1
1
0
1
1.33125
1
0
0
0
1
0
0
0
0.76250
0
0
1
0
1
1
1
0
1.32500
1
0
0
0
1
0
0
1
0.75625
0
0
1
0
1
1
1
1
1.31875
1
0
0
0
1
0
1
0
0.75000
0
0
1
1
0
0
0
0
1.31250
1
0
0
0
1
0
1
1
0.74375
0
0
1
1
0
0
0
1
1.30625
1
0
0
0
1
1
0
0
0.73750
0
0
1
1
0
0
1
0
1.30000
1
0
0
0
1
1
0
1
0.73125
0
0
1
1
0
0
1
1
1.29375
1
0
0
0
1
1
1
0
0.72500
0
0
1
1
0
1
0
0
1.28750
1
0
0
0
1
1
1
1
0.71875
0
0
1
1
0
1
0
1
1.28125
1
0
0
1
0
0
0
0
0.71250
0
0
1
1
0
1
1
0
1.27500
1
0
0
1
0
0
0
1
0.70625
0
0
1
1
0
1
1
1
1.26875
1
0
0
1
0
0
1
0
0.70000
0
0
1
1
1
0
0
0
1.26250
1
0
0
1
0
0
1
1
0.69375
0
0
1
1
1
0
0
1
1.25625
1
0
0
1
0
1
0
0
0.68750
0
0
1
1
1
0
1
0
1.25000
1
0
0
1
0
1
0
1
0.68125
0
0
1
1
1
0
1
1
1.24375
1
0
0
1
0
1
1
0
0.67500
0
0
1
1
1
1
0
0
1.23750
1
0
0
1
0
1
1
1
0.66875
0
0
1
1
1
1
0
1
1.23125
1
0
0
1
1
0
0
0
0.66250
0
0
1
1
1
1
1
0
1.22500
1
0
0
1
1
0
0
1
0.65625
0
0
1
1
1
1
1
1
1.21875
1
0
0
1
1
0
1
0
0.65000
0
1
0
0
0
0
0
0
1.21250
1
0
0
1
1
0
1
1
0.64375
0
1
0
0
0
0
0
1
1.20625
1
0
0
1
1
1
0
0
0.63750
0
1
0
0
0
0
1
0
1.20000
1
0
0
1
1
1
0
1
0.63125
0
1
0
0
0
0
1
1
1.19375
1
0
0
1
1
1
1
0
0.62500
Processor Power Delivery Design Guidelines
37
VRD 11.1 Common Information
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
Voltage
0
1
0
0
0
1
0
0
1.18750
1
0
0
1
1
1
1
1
0.61875
0
1
0
0
0
1
0
1
1.18125
1
0
1
0
0
0
0
0
0.61250
0
1
0
0
0
1
1
0
1.17500
1
0
1
0
0
0
0
1
0.60625
0
1
0
0
0
1
1
1
1.16875
1
0
1
0
0
0
1
0
0.60000
0
1
0
0
1
0
0
0
1.16250
1
0
1
0
0
0
1
1
0.59375
0
1
0
0
1
0
0
1
1.15625
1
0
1
0
0
1
0
0
0.58750
0
1
0
0
1
0
1
0
1.15000
1
0
1
0
0
1
0
1
0.58125
0
1
0
0
1
0
1
1
1.14375
1
0
1
0
0
1
1
0
0.57500
0
1
0
0
1
1
0
0
1.13750
1
0
1
0
0
1
1
1
0.56875
0
1
0
0
1
1
0
1
1.13125
1
0
1
0
1
0
0
0
0.56250
0
1
0
0
1
1
1
0
1.12500
1
0
1
0
1
0
0
1
0.55625
0
1
0
0
1
1
1
1
1.11875
1
0
1
0
1
0
1
0
0.55000
0
1
0
1
0
0
0
0
1.11250
1
0
1
0
1
0
1
1
0.54375
0
1
0
1
0
0
0
1
1.10625
1
0
1
0
1
1
0
0
0.53750
0
1
0
1
0
0
1
0
1.10000
1
0
1
0
1
1
0
1
0.53125
0
1
0
1
0
0
1
1
1.09375
1
0
1
0
1
1
1
0
0.52500
0
1
0
1
0
1
0
0
1.08750
1
0
1
0
1
1
1
1
0.51875
0
1
0
1
0
1
0
1
1.08125
1
0
1
1
0
0
0
0
0.51250
0
1
0
1
0
1
1
0
1.07500
1
0
1
1
0
0
0
1
0.50625
0
1
0
1
0
1
1
1
1.06875
1
0
1
1
0
0
1
0
0.50000
0
1
0
1
1
0
0
0
1.06250
1
1
1
1
1
1
1
0
OFF
0
1
0
1
1
0
0
1
1.05625
1
1
1
1
1
1
1
1
OFF
0
1
0
1
1
0
1
0
1.05000
1.6.2
Differential Remote Sense Input (REQUIRED)
The PWM controller must include differential sense inputs (remote sense, remote
sense return) to compensate for an output voltage offset of ≤ 100 mV in the power
distribution path and in the return path loop. The remote sense lines should draw no
more than 1.0 mA to minimize offset errors. The remote sense input needs to have
sufficient CMRR to not pass and amplify high frequency processor noise to the VR
output. Refer to the processor specific sections of this document for measurement
locations.
38
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
1.6.3
Power State Indicator (PSI#) (Required)
The processor will provide an output signal to the VR controller to indicate when the
processor is in a low power state. The VR PWM controller can use this signal to change
its operating state (phase shedding) to maximize efficiency at light loads or optimize
the efficiency curve for system idle power reduction. The PSI# signal will be a 1 V
CMOS compliant signal. See the Table 1-8.
PSI# will be asserted when the processor is in a power state such that the current
draw is within the range of a single phase current rating – typically < 20 A. The PSI#
signal will de-assert 3.3 µs prior to moving to a normal power state. Refer to the
appropriate processor datasheet for specific details on the current threshold for PSI#
assertion. If an increasing voltage DVID event occurs while PSI# is asserted, the PWM
should change to normal power mode.
PSI# is high for normal power mode and is asserted low for low power mode.
Note that PSI# operation is different for LGA775 platforms. Please refer to that
section for more information on unique PSI# operation.
1.7
Input Voltage and Current
1.7.1
Input Voltages (EXPECTED)
VRD output voltage is supplied via DC-to-DC power conversion. To ensure proper
operation, the input supplies to these regulators must satisfy the following conditions.
1.7.1.1
Desktop Input Voltages
The main power source for the VCC VRD is 12 V ±15% and 3.3 V ±5% for the VTT
supply. These voltages are supplied by an AC-DC power supply through a dedicated
12 V cable to the motherboard VRD input. For input voltages outside the normal
operating range, the VRD should either operate properly or shut down. Intel
recommends a DC-DC regulator input filter with a minimum 1000 µF to ensure proper
loading of the 12 V power source.
Processor Power Delivery Design Guidelines
39
VRD 11.1 Common Information
1.7.1.2
Efficiency (OPTIONAL)
The following tables show the expected VR efficiency for each of the VR
configurations. The input voltage of efficiency testing should be 11 VDC. This input
voltage will represent the worst case input voltage to the VRD under a high load
condition.
Voltage regulator efficiency is measured from the 12 V voltage regulator input to the
loadline reference node. See the processor specific sections for more details on the
loadline reference nodes.
Table 1-10. 1366_VR Efficiency Guidelines
VR Efficiency per loading level
Configuration
2–5 A
6–20 A
VR_TDC
1366_VR_CONFIG_08B
> 70%
> 80%
> 75%
Table 1-11. LGA1156_VR Efficiency Guidelines
VR Efficiency per loading level
Configuration
2–5 A
6–20 A
VR_TDC
1156_VR_CONFIG_09A/B
> 70%
> 80%
> 75%
Table 1-12. LGA775_VR Efficiency Guidelines
VR Efficiency per loading level
40
Configuration
Idle (20% of ICC
(max))
VR_TDC
ICC (max)
775_VR_CONFIG_04A
—
75%
—
775_VR_CONFIG_04B
—
75%
—
775_VR_CONFIG_05A
—
75%
—
775_VR_CONFIG_05B
—
75%
75% (80%
preferred)
775_VR_CONFIG_06
75%
—
—
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
1.8
Output Protection
This section describes features built into the DC-DC regulator to prevent damage to
itself, the processor, validation tools, or other system components.
1.8.1
Over-Voltage Protection (OVP) (PROPOSED)
OVP is proposed to protect the processor from high voltage damage that may lead to
failure, or a reduced processor life span. The OVP circuit is to monitor VCC for an overvoltage condition at the defined regulation lands. This voltage must never exceed
maximum VID+200 mV (that is, 1.6 V + 200 mV) under any condition and operation
above this level defines an OVP violation. In the event of an OVP violation, the VCC VR
low side MOSFETs should be driven on to protect the processor and the VR should deassert VR_READY to shut down the core supply voltage. Power cycling is required to
re-start the system.
OVP at start-up should be fully functional with a trip level referenced to the boot VID
of 1.1 V.
Operating at lower VID codes during Dynamic VID establishes low (invalid) OVP
thresholds which must not be used to initiate a system shut down. For example, there
is a time delay from transmission of a VID code to the VR reaction; this time lag may
result in a 200 mV delta from the reference VID at a functional voltage that will not
damage the processor. Because of these conditions, OVP functionality must be
blanked during the Dynamic VID state.
1.8.2
Over-Current Protection (OCP) (PROPOSED)
The DC-DC should be capable of withstanding a continuous, abnormally low resistance
on the output without damage or over-stress to the DC-DC. The OCP trip level should
be programmable by the DC-DC designer, typically 130% of rated output current. If
an OCP fault is detected, the VR should fold back or shut down, de-assert VR_READY
and reset the start up sequence.
Output current under this condition must be limited to avoid component damage and
violation of the VRD thermal specifications.
Processor Power Delivery Design Guidelines
41
VRD 11.1 Common Information
1.9
Output Indicators
1.9.1
VR_READY — VCC Regulator Is ‘ON’ (REQUIRED)
VR_READY is an active high output that indicates the start up sequence is complete
and the output voltage has moved to the programmed VID value. This signal will be
used for start up sequencing for other voltage regulators, the clock, microprocessor
reset, etc. This signal should not be de-asserted by low voltages that occur during DVID operation. The signal should remain asserted during normal DC-DC operating
conditions and only de-assert for fault or shutdown conditions. This signal is not a
representation of the accuracy of the DC output to its VID value; it is simply a flag to
indicate the VRD is functioning. See Figure 1-11 for timing and Table 1-13 for signal
specifications.
Table 1-13. VR_Ready output signal Specifications
Signal Type
Open Collector/Drain Logic output from PWM IC, with
external pull-up resistor and reference voltage.
VR_Ready = HIGH
Active / Asserted
VR_Ready = LOW
Not Active / De-Asserted
Symbol
Parameter
Max
Units
VOH
Output
Voltage High
0.8
3.3
VDC
VOL
Output
Voltage Low
0
0.3
VDC
IOL
Output Low
Sink Current
1.0
4.0
mA DC
—
150
ns
Transition
Edge Rate
42
Min
Remarks
VTT rail is expected; Open Coll. /Drain
Trans. OFF, Imp. >100 kΩ depending on
system implementation
With external pull-up resistor;
Open Coll./Drain Trans. ON
Current limit set by external pull-up
resistor
From 10-90% rise
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
1.9.2
Load Current Signal (Iout) (REQUIRED)
Iout load current measurement is required for power management features of the
processor. This signal will be connected directly to the processor.
The VR11.1 PWM should have an analog output that varies linearly and represents the
total output current from the voltage regulator. Voltage on this pin will be linearly
proportional to the output current. Proportional gain will be platform specific and
needs to be externally programmable. The dc-dc regulator on the platform will provide
gain setting to processor using Power On Configuration (POC) lines (3 bit information
to select one of 8 different gain options). The POC levels are multiplexed onto the VID
lines with pull-up and pull-down resistors and read by the processor during the TD0
time (between VTT being valid and Vtt_PG asserting). After Vtt_PG is asserted the VID
CMOS drivers override the MSID, POC pull-up and pull-down resistors. See Table 1-8,
“Interface Signals Parameters” for more information.
The information for total output current can come from the circuit blocks that
generate the loadline droop. Iout is expected to be temperature compensated in the
same manner as the loadline Vdroop. See the following tables for gain definitions.
Table 1-14. Iout Analog Output Requirements
Iout (mV)
VR Output Current (A)
0
0
900
IMAX
NOTES:
1.
IMAX is the VR maximum current corresponding to the processor’s POC gain setting not
the OCP level.
Table 1-15. Iout Gain and POC Settings
Processor ICC (max)
IMAX
Iout gain: 900 mV = IMAX
POC Gain Setting
Disabled
-
000
ICC (max) ≤ 40 A
40 A
001
40 A < ICC (max) ≤ 60 A
60 A
010
60 A < ICC (max) ≤ 80 A
80 A
011
80 A < ICC (max) ≤ 100 A
100 A
100
100 A < ICC (max) ≤ 120 A
120 A
101
120 A < ICC (max) ≤ 140 A
140 A
110
140 A < ICC (max) ≤ 180 A
180 A
111
NOTES:
1.
Warning! Under any operating or fault condition, voltage on Iout must not exceed
1.15 V to prevent damage to the processor input gate.
The processor receiver will be referenced to VSS_SENCE. To minimize offset errors
between different reference potentials Iout from the PWM should be referenced to this
Processor Power Delivery Design Guidelines
43
VRD 11.1 Common Information
pin (VSS_SENCE). Regardless of implementation method, current draw on reference
(VSS_SENCE) pin must not exceed a 1 mA for both Iout and remote sense bias
currents.
Iout signal must be filtered with a filter time constant of >300 us to prevent ADC
aliasing in the processor. This value should be well below the L/R time constant of the
motherboard inductors.
The controller inaccuracy contribution should be minimized. Total solution accuracy
will be defined by controller, inductor DCR accuracy (if solution implements inductor
current sensing) and external passive components. The tightest accuracy is expected
at full load. Linearity must be supported.
The Iout accuracy requirements are shown in Table 1-16.
Table 1-16. Iout Accuracy Requirements
Accuracy
Current
-0 / +20%
100% x ICC (max)
-0 / +40%
50% x ICC (max)
-0 / +60%
25% x ICC (max)
It is highly recommended the IMON linearity and accuracy will be maximized. Less
accurate IMON reporting will have negative performance impact on the processor.
Total solution accuracy will be defined by the PWM controller, inductor DCR accuracy
(if solution implements inductor current sensing) and the external passive
components. The tightest accuracy is expected at full load. It will be left to the MB
designer to specify the VR’s IMON accuracy for the optimal design point. Vendors
should provide the accuracy graphs to the MB designer to aid in component and
vendor selection.
1.9.3
Thermal Monitoring
1.9.3.1
VR_HOT (EXPECTED)
Each customer is responsible for identifying maximum temperature specifications for
all components in the voltage regulator design and ensuring that these specifications
are not violated while continuously drawing specified VR TDC levels. In the event of a
catastrophic thermal failure, the thermal monitoring circuit is to assert the VR_HOT
signal to drive the processor PROCHOT# inputs immediately prior to exceeding
maximum temperature ratings to prevent heat damage. Assertion of these signals will
lower processor power consumption and reduce current draw through the voltage
regulator, resulting in lower component temperatures. Assertion of PROCHOT#
degrades system performance and must never occur when drawing less than specified
thermal design current. The tolerance on VR_HOT should be ±4% or approximately
±4 degrees Celsius with 10 degree Celsius hysteresis.
VR_HOT is an active high output. See PWM IC vendor’s data sheets for signal interface
specifications (open drain or push-pull). VR_HOT cannot be tied directly to
PROCHOT#; the signals must be inverted and buffered. See Table 1-17 for PROCHOT#
signal requirements.
44
Processor Power Delivery Design Guidelines
VRD 11.1 Common Information
Figure 1-16. PROCHOT# Load External to Processor
Vtt
3.3 V
49.9 Ω
2 kΩ
PROCHOT#
VR_HOT
130 Ω
VR11.1
Processor
Table 1-17. Thermal Monitor Specifications
Parameter
Minimum
Typical
Maximum
VTT
—
VTT 1
—
Q1 ‘on’ resistance
—
—
11 Ω
PROCHOT# leakage current
—
—
200 µA
PROCHOT# transition time
1.10 ns
100 ns
—
—
—
0.4 V
0.5 ms
—
—
PROCHOT# VOL (Maximum low voltage
threshold)
Minimum time to toggle in and out of D-VID
NOTE:
1.
Consult the appropriate processor datasheet for the VTT specifications.
§
Processor Power Delivery Design Guidelines
45
VRD 11.1 Common Information
46
Processor Power Delivery Design Guidelines
LGA1366 Information
2
LGA1366 Information
2.1
Introduction
This chapter focuses on information unique to platforms designed with the LGA 1366.
2.1.1
Applications
Previously in the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines the motherboard regulation loadline was defined at the socket. Specifically
the loadline was referenced to the VCC_MB_REGULATION and VSS_MB_REGULATION
lands on the LGA775 socket. This is still the case when VRD11.1 is used for platforms
with the LGA775 socket. However, platforms using the LGA1366 socket will use a
different loadline definition and reference point. The loadline for LGA1366 socket
platforms is referenced to the VCC_SENSE and the VSS_SENSE lands. The implication
of this is that the slope of the loadline at the VCC_SENSE/VSS_SENSE point is not the
same as the socket loadline. The loadline at the VCC_SENSE/VSS_SENSE lands is
0.8 mΩ. This is equivalent to a socket loadline slope of 0.5 mΩ.
2.2
Processor VCC Requirements
2.2.1
Loadline Definitions (REQUIRED)
To maintain processor reliability and performance, platform DC voltage regulation and
transient-droop noise levels must always be contained within the Vccmin and Vccmax
loadline boundaries (known as the loadline window). Loadline compliance must be
ensured across component manufacturing tolerances, thermal variation, and age
degradation. Loadline boundaries are defined by the following equations in conjunction
with the VCC regulator design parameter values defined in Table 2-2. In these
equations, VID, RLL, and TOB are known. Plotting VCC while varying ICC from 0 A to
Iccmax establishes the Vccmax and Vccmin loadlines. Vccmax establishes the
maximum DC loadline boundary. Vccmin establishes the minimum AC and DC voltage
boundary. Short transient bursts above the Vccmax loadline are permitted; this
condition is defined in Section 1.3.7.
Processor Power Delivery Design Guidelines
47
LGA1366 Information
Table 2-1. Loadline Equations
Loadline
Equation
Equation 5: Vccmax Loadline
VCC = VID – (RLL* ICC)
Equation 6: Vcctyp Loadline
VCC = VID – TOB - (RLL* ICC)
Equation 7: Vccmin loadline
VCC = VID – 2*TOB - (RLL* ICC)
Loadline recommendations are established to provide guidance for satisfying
processor loadline specifications, which are defined in processor datasheets. Loadline
requirements must be satisfied at all times and may require adjustment in the loadline
value. The processor loadlines are defined in the applicable processor datasheet.
Table 2-2. VCC Regulator Design Parameters
VR Configuration
1366_VR_CONFIG_
08B
Iccmax
VR
TDC
Dynamic
ICC
RLL
TOB
Maximum
VID
145 A
110 A
100 A
0.8 mΩ
± 19 mV
TBD V
Table 2-2 provides a list of VRD11.1 LGA1366 voltage regulator design configurations.
The configurations to be adopted by VRD hardware will depend on the specific
processors the design is intended to support. It is common for a motherboard to
support processors that require different VR configurations. In this case, the VCC
regulator design must meet the specifications of all processors supported by that
board.
The following tables and figures show minimum and maximum voltage boundaries for
each loadline design configuration defined in Table 2-2. VCCTYP loadlines are provided
for design reference; designs should calibrate the loadline to this case (centered in the
loadline window, at the mean of the tolerance band). Different processors discussed in
this design guide can be shipped with different VID values. The reader should not
assume that processors with similar characteristics will have the same VID value. A
single loadline chart and figure for each VRD design configuration can represent
functionality for each possible VID value. Tables and figures presented as voltage
deviation from VID provide the necessary information to identify voltage requirements
at any reference VID. This avoids the redundancy of publishing tables and figures for
each of the multiple cases.
48
Processor Power Delivery Design Guidelines
LGA1366 Information
2.2.1.1
Loadline Definition for 1366_VR_CONFIG_08B
Figure 2-1. Loadline Window for 1366_VR_CONFIG_08B
0
20
40
60
80
100
120
140
160
0.0000
Deviation from VID (V)
-0.0190
-0.0380
-0.0570
-0.0760
-0.0950
-0.1140
-0.1330
-0.1520
-0.1710
Icc (A)
Vmax Loadline
Vmin Loadline
Vtyp Loadline
NOTES:
1.
Presented as a deviation from VID
2.
Loadline Slope = 0.8 mΩ, TOB = ±19 mV
3.
Consult Table 2-2 for VR configuration parameter details
Table 2-3. Loadline Window for 1366_VR_CONFIG_08B
ICC
Maximum (V)
Typical (V)
Minimum (V)
0A
0.0000
-0.0190
-0.0380
10 A
-0.0080
-0.0270
-0.0460
20 A
-0.0160
-0.0350
-0.0540
30 A
-0.0240
-0.0430
-0.0620
40 A
-0.0320
-0.0510
-0.0700
50 A
-0.0400
-0.0590
-0.0780
60 A
-0.0480
-0.0670
-0.0860
70 A
-0.0560
-0.0750
-0.0940
80 A
-0.0640
-0.0830
-0.1020
90 A
-0.0720
-0.0910
-0.1100
100 A
-0.0800
-0.0990
-0.1180
110 A
-0.0880
-0.1070
-0.1260
120 A
-0.0960
-0.1150
-0.1340
130 A
-0.1040
-0.1230
-0.1420
140 A
-0.1120
-0.1310
-0.1500
145 A
-0.1160
-0.1350
-0.1540
NOTES:
1.
Presented as a deviation from VID
2.
Loadline Slope = 0.8 mΩ, TOB = ±19 mV
3.
Consult Table 2-2 for VR configuration parameter details
Processor Power Delivery Design Guidelines
49
LGA1366 Information
VRD layout studies indicate that the phases are best located north of the processor
with the controller to the northeast.
Table 2-4. Loadline Reference Lands for the LGA1366 Socket
Name
Land
VCC_SENSE
AR9
VSS_SENSE
AR8
To properly calibrate the loadline parameter, the VR designer must excite the
processor socket with a current step that generates a voltage droop which must be
checked against the loadline window requirements. Table 2-5 identifies the steady
state and transient current values to use for this calibration.
Table 2-5. Intel® Processor Current Step Values for Transient Loadline Testing
VR Configuration
1366_VR_CONFIG_08B
2.2.1.2
Starting
Current
Ending
Current
Dynamic
Current Step
ICC Rise
Time
ICC Fall
Time
45 A
145 A
100 A
200 ns
200 ns
Time Domain Validation
To ensure processor reliability and performance, platform transient-droop and
overshoot noise levels must always be contained within the Vccmin and Vccmax
loadline boundaries (known as the loadline window). The load generates a voltage
droop, or overshoot, which must be checked against the loadline window
requirements. The current step must have a fast enough slew rate to excite the
impedance across the frequency range of the VR. In addition, the VR needs to be
tested at different load frequencies and load steps to prevent any non-linear,
resonant, or beating effects that could cause functional issues or loadline violations.
Intel recommends sweeping the load frequency from DC to 1 MHz, using two different
load steps.
Intel recommends testing using different VID levels for each of the supported VR
configurations. In particular the highest and lowest VIDs should be checked. The VID
ranges for each processor is available in the processor datasheet.
50
Processor Power Delivery Design Guidelines
LGA1366 Information
Figure 2-2. 200 Hz, 100 A Step Droop Waveform
NOTE:
The cursor indicates the droop area of interest. A falling edge with a width less than
100 ns can be ignored.
Figure 2-3. 250 kHz, 100 A Step Waveform
NOTE:
The cursor indicates the droop area of interest. A falling edge with a width less than
100 ns can be ignored.
Processor Power Delivery Design Guidelines
51
LGA1366 Information
2.2.1.3
Platform Impedance Measurement and Analysis (Expected)
In addition to the tuning of the loadline with Vdroop testing and DC loadline testing,
the decoupling capacitor selection needs to be analyzed to make sure the impedance
of the decoupling is below the loadline target up to the frequency Fbreak as defined in
Figure 2-4. This analysis can be done with impedance testing or through power
delivery simulation if the designer can extract the parasitic resistance and inductance
of the power planes on the motherboard and they have good models for the
decoupling capacitors.
Measured power delivery impedance should be with in the tolerance band shown in
Figure 2-4. For loadline compliance, time domain validation is required and the VR
tolerance band must be met at all times. Above 500 kHz, the minimum impedance
tolerance is not defined and is determined by the MLCC capacitors required to get the
ESL low enough to meet the loadline impedance target at the Fbreak frequency. At
1 MHz, the Zmax tolerance drops to the loadline target impedance. Any resonance
points that are above the Zmax line need to be carefully evaluated with time domain
method defined in Section 2.2.1.2 by applying transient loads at that frequency and
looking for Vmin violations. Maintaining the impedance profile up to Fbreak is important
to ensure the package level decoupling properly matches the motherboard impedance.
After Fbreak, the impedance measurement is permitted to rise at a inductive slope. The
motherboard VR designer does not need to design for frequencies over Fbreak as the
processor package decoupling takes over in the region above Fbreak.
Figure 2-4. Power Distribution Impedance versus Frequency
Ω
Zone 2
Output Filter
Bulk & MLCC
Zone 1
PWM Droop control
& compensation
bandwidth
ZLL Max
Zone 3
Inductive effects
MLCC ESL +
Socket
Z target = ZLL
ZLL Min
Hz
VR BW
Fbreak
500 kHz
1 MHz
NOTES:
1.
See Table 2-6. Impedance Measurement Parameters definitions
2.
Zone 1 is defined by the VR closed loop compensation bandwidth (VR BW) of the
voltage regulator. Typically 30–40 kHz for a 300 kHz voltage regulator design.
3.
Zones 2 and 3 are defined by the output filter capacitors and interconnect parasitic
resistance and inductance. The tolerance is relaxed over 500 kHz allowing the VR
designer freedom to select output filter capacitors. The goal is to keep Z(f) below ZLL
up to Fbreak and as flat as practical, by selection of bulk capacitor values and type and
number of MLCC capacitors. The ideal impedance would be between ZLL and ZLL Min
but this may not be achieved with standard decoupling capacitors.
52
Processor Power Delivery Design Guidelines
LGA1366 Information
Table 2-6. Impedance Measurement Parameters
2.3
Parameter
Value
Notes
ZLL
0.8 mΩ
LGA1366 Desktop LL target
ZLL max
1.0 mΩ
Based on VR11.1 PWM tolerance band
ZLL min
0.6 mΩ
Based on VR11.1 PWM tolerance band
Fbreak
2.0 MHz
—
VTT Requirements (REQUIRED)
The VTT regulator provides power to the non-core sections of the processor. The
VTTPWRGOOD signal from this regulator begins power sequencing. Valid output
voltage of the VTT regulator must be ensured by the timing protocol defined in the
Power Sequencing section.
2.3.1
Electrical Specifications
A VR11.0 based regulator is recommended for the VTT supply with adequate
decoupling capacitors to ensure the sum of AC bus noise and DC tolerance satisfy
limits identified in Table 2-7. The processor VTT supply must be maintained within
these tolerance limits across full operational thermal limits, part-to-part component
variation, age degradation, and regulator accuracy. Full bandwidth bus noise
amplitude must be ensured across the land pairs defined in Table 2-9.
The VTT supply must be unconditionally stable under all DC and transient conditions
across the voltage and current ranges defined in Table 2-7. The VTT supply must also
operate in a no-load condition; that is, with no processor installed.
Processor Power Delivery Design Guidelines
53
LGA1366 Information
Figure 2-5. Window for VTT Voltage on LGA1366 Platforms
Deviation from Zero Current Setpoint (V)
0
5
10
15
20
25
0.0600
0.0400
0.0200
0.0000
-0.0200
-0.0400
-0.0600
-0.0800
-0.1000
-0.1200
-0.1400
-0.1600
-0.1800
-0.2000
-0.2200
Icc (A)
Vtt Loadline
Vtt Max
Vtt Min
NOTES:
1.
Presented as a deviation from VTT zero current setpoint.
Table 2-7. Window for VTT Voltage on LGA1366 Platforms
54
ICC (A)
Maximum (V)
VTT Loadline (V)
6.0 mΩ
Minimum (V)
0
0.0315
0.0000
-0.0315
1
0.0255
-0.0060
-0.0375
2
0.0195
-0.0120
-0.0435
3
0.0135
-0.0180
-0.0495
4
0.0075
-0.0240
-0.0555
5
0.0015
-0.0300
-0.0615
6
-0.0045
-0.0360
-0.0675
7
-0.0105
-0.0420
-0.0735
8
-0.0165
-0.0480
-0.0795
9
-0.0225
-0.0540
-0.0855
10
-0.0285
-0.0600
-0.0915
11
-0.0345
-0.0660
-0.0975
12
-0.0405
-0.0720
-0.1035
13
-0.0465
-0.0780
-0.1095
14
-0.0525
-0.0840
-0.1155
15
-0.0585
-0.0900
-0.1215
16
-0.0645
-0.0960
-0.1275
Processor Power Delivery Design Guidelines
LGA1366 Information
ICC (A)
Maximum (V)
VTT Loadline (V)
6.0 mΩ
Minimum (V)
17
-0.0705
-0.1020
-0.1335
18
-0.0765
-0.1080
-0.1395
19
-0.0825
-0.1140
-0.1455
20
-0.0885
-0.1200
-0.1515
21
-0.0945
-0.1260
-0.1575
22
-0.1005
-0.1320
-0.1635
23
-0.1065
-0.1380
-0.1695
24
-0.1125
-0.1440
-0.1755
25
-0.1185
-0.1500
-0.1815
26
-0.1245
-0.1560
-0.1875
27
-0.1305
-0.1620
-0.1935
28
-0.1365
-0.1680
-0.1995
NOTES:
1.
Presented as a deviation from VTT zero current setpoint.
Table 2-8 VTT Parameters
ICC Max
ICC TDC
Istep
Istep Slew Rate
Ripple
28A
28 A
10 A
10A / us
15mV pk-pk
Table 2-9. VTT Measurement Lands
Device
Supply
Land
Processor
VTTD_SENSE
AE36
Processor
VSS_SENSE_VTTD
AE37
Table 2-10. VTT VID Lands
Processor Land
VTT VID
VR11 VID Input
AV6
Vtt_VID4
VID4
AF7
Vtt_VID3
VID3
AV3
Vtt_VID2
VID2
Processor Power Delivery Design Guidelines
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LGA1366 Information
Table 2-11. VTT VID Voltage
VR11 VID Input
DAC
Voltage
VTT Zero Current
Setpoint
(DAC+20 mV)
7
6
5
VTT _
VID4
VTT _
VID3
VTT _
VID2
1
0
0
1
0
0
0
0
1
0
1.200 V
1.220 V
0
1
0
0
0
1
1
0
1.175 V
1.195 V
0
1
0
0
1
0
1
0
1.150 V
1.170 V
0
1
0
0
1
1
1
0
1.125 V
1.145 V
0
1
0
1
0
0
1
0
1.100 V
1.120 V
0
1
0
1
0
1
1
0
1.075 V
1.095 V
0
1
0
1
1
0
1
0
1.050 V
1.070 V
0
1
0
1
1
1
1
0
1.025 V
1.045 V
2.4
LGA 1366 Specific Signals
2.4.1
Power-on Configuration (POC) Signals on VID
(REQUIRED)
All 8 VID lines will serve a second function: the Power On Configuration (POC) logic
levels are multiplexed onto the VID lines with 1 kΩ pull-ups and pull-downs and they
will be read by the processor during the time - as shown in the Power Sequencing
section. The POC configuration programs the processor as to the platform VR
capabilities. The VR does not read POC configuration resistors. After OUTEN is
asserted the processor VID CMOS drivers override the POC pull-up, and pull-down
resistors. See the Power Sequencing section for more information.
The POC bits (Multiplexed with 8 VID lines) are allocated is as follows:
• POC/(VID)[2:0] = MSID (Market Segment ID) bits, refer to the datasheet.
• POC/(VID)[5:3] = Current Sense Config bits, Iout gain setting, see Table 1-15.
• POC/(VID)[6] = RESERVED (pull-down resistors installed, unless stated otherwise
in the datasheet).
• POC/(VID)[7] = VR11.1 Select signal, with pull-down resistor installed for VR11.1,
refer to the datasheet.
56
Processor Power Delivery Design Guidelines
LGA1366 Information
2.5
MB Power Plane Layout (REQUIRED)
The motherboard layer stack-up must be designed to ensure robust, noise-free power
delivery to the processor. Failure to minimize and balance power plane resistance may
result in non-compliance to the loadline specification. A poorly planned stack-up or
excessive holes in the power planes may increase system inductance and generate
oscillation on the VCC voltage rail at the processor. Both of these types of design
errors can lead to processor failure and must be avoided by careful VCC and VSS plane
layout and stack-up. The types of noise introduced by these errors may not be
immediately observed on the processor power lands or during system-board voltage
transient validation, so issues must be resolved by design, prior to layout, to avoid
unexpected failures.
Following basic layout rules can help avoid excessive power plane noise. All
motherboard layers in the area surrounding the processor socket should be used for
VCC power delivery; copper shapes that encompass the power delivery region of the
processor land field are required. A careful motherboard design will help ensure a
well-functioning system that minimizes the noise profile at the processor. The
following subsections provide further guidance.
2.5.1
Minimize Power Path DC Resistance
Power path resistance can be minimized by ensuring that the copper layout area is
balanced between VCC and VSS planes. A good six layer board design will have three
VCC layers and three VSS layers. Because there is generally more VSS copper in the
motherboard stack-up, care should be taken to maximize the copper in VCC floods.
This includes care to minimize unnecessary plane splits and holes when locating
through hole components, vias, and connection pads. Refer to Table 2-12 for more
details on the reference board layer stackup.
2.5.2
Minimize Power Delivery Inductance
At higher frequencies the ordering of the motherboard layers becomes critical as it is
VCC/ VSS plane pairs which carry current and determine power plane inductance. The
layer stack-up should maximize adjacent (layer-to-layer) planes at a minimized
spacing to achieve the smallest possible inductance. Care must be taken to minimize
unnecessary plane splits and holes when locating through-hole components, vias, and
connection pads. Minimized inductance will ensure that the board does not develop
low frequency noise which may cause the processor to fail (loadline violation).
2.5.3
Six-Layer Boards
A well-designed 6-layer board will feature generous VCC shapes on the outer layers
and large VSS shapes on the inner layers. The VSS -reference requirements for the
front side bus are best accommodated with this layer ordering. The power plane area
should be maximized and cut-out areas should be carefully placed to minimize
parasitic resistance and inductance. Examples power plane layout of the Intel
reference board are provided in Table 2-12 and Figure 2-6 through Figure 2-10.
Processor Power Delivery Design Guidelines
57
LGA1366 Information
Figure 2-6. Reference Board Layer Stack-up
A
B
C
D
E
Prepreg
Ground Layer
Power/Ground
Layer
Total
Thickness
62.0 mils
Prepreg and/or Core
Signal Layer
F
Core
G
Signal Layer
H
I
NOTE:
Signal Layer
Prepreg and/or Core
Ground Layer
J
Prepreg
K
Signal Layer
Drawing is not to scale
Table 2-12. Reference Board Layer Thickness (Prepreg 1080)
Layer
Minimum (mil)
Typical (mil)
Maximum (mil)
A
1.10
1.90
2.75
B
2.00
2.70
3.50
C
1.00
1.20
1.40
D
3.25
4.00
4.75
E
1.00
1.20
1.40
F
Adjusted to meet overall board thickness of 62 mils
G
1.00
1.20
1.40
H
3.25
4.00
4.75
I
1.00
1.20
1.40
J
2.00
2.70
3.50
K
1.10
1.90
2.75
NOTES:
1.
Consult Figure 2-6 for layer definition
2.
Impedance Target: 50 Ω ± 15%; based on nominal 4 mil trace
3.
Overall board thickness is 62 mils +8, -5 mils
58
Processor Power Delivery Design Guidelines
LGA1366 Information
Figure 2-7. Layer 1 VCC Shape for Intel® Reference Six-layer Motherboard
Processor Power Delivery Design Guidelines
59
LGA1366 Information
Figure 2-8. Layer 2 VSS Routing for Intel® Reference Six-layer Motherboard
60
Processor Power Delivery Design Guidelines
LGA1366 Information
Figure 2-9. Layer 3 VCC Routing for Intel® Reference Six-layer Motherboard
Processor Power Delivery Design Guidelines
61
LGA1366 Information
Figure 2-10. Layer 4 VCC Shape for Intel® Reference Six-layer Motherboard
62
Processor Power Delivery Design Guidelines
LGA1366 Information
Figure 2-11. Layer 5 VSS Shape for Intel® Reference Six-layer Motherboard
Processor Power Delivery Design Guidelines
63
LGA1366 Information
Figure 2-12. Layer 6 VCC Shape for Intel® Reference Six-layer Motherboard
2.5.4
Resonance Suppression
VCC power delivery designs can be susceptible to resonance phenomena capable of
creating droop amplitudes in violation of loadline specifications. This is due to the
interleaved levels of inductively-separated decoupling capacitance. Furthermore, these
resonances may not be detected through standard validation and require engineering
analysis to identify and resolve. If not identified and corrected in the design process,
these resonant phenomena may yield droop amplitudes in violation of loadline
specifications by superimposing with standard VRD droop behavior. Frequencydependent power delivery network impedance simulations and validation are strongly
recommended to identify and resolve power delivery resonances before board are
actually built. Careful modeling and validation can help to avoid voltage violations
responsible for data corruption, system lock-up, or system ‘blue-screening’.
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Processor Power Delivery Design Guidelines
LGA1366 Information
2.6
Electrical Simulation (EXPECTED)
The following electrical models are enclosed to assist with VRD design analysis and
component evaluation for loadline compliance. The block diagram shown in
Figure 2-13 is a simplified representation of the VCC power delivery network of the
Intel six-layer reference board). The board model, detailed in Figure 2-16,
characterizes the power plane layout of Figure 2-7 to Figure 2-10. The multiphase
buck regulator and capacitor models should be obtained from each selected vendor.
When fully integrated into electrical simulation software, this model can be used to
evaluate PWM controller, capacitor, and inductor performance against the loadline and
tolerance band requirements detailed in Section 1.3.2. To obtain accurate results, it is
strongly recommended to create and use a custom model that represents the specific
board design, PWM controller, and passive components that are under evaluation.
Figure 2-13. Simplified Reference Block Diagram
NOTE:
Consult Figure 2-7 to Figure 2-12 for reference layout.
The motherboard model of Figure 2-16 represents the power delivery path of the Intel
reference six-layer motherboard design. Input and output node locations are identified
in Figure 2-17. Feedback to the PWM controller error amplifier should be tied to node
Processor Power Delivery Design Guidelines
65
LGA1366 Information
‘Sense’, the socket-motherboard interface. Node ‘B1’ is the location where the output
inductors of the buck regulator ties to the motherboard power plane. ‘North’ bulk
capacitors, C1, are also connected to node ‘B1’. C1 represents the parallel
combination of all capacitors and capacitor parasitics at this location. Node ‘B2’ is the
location where the ‘north’ bulk capacitors, C1, connect to the ‘south’ bulk capacitors,
C2. C2 represents the parallel combination of all capacitors and capacitor parasitics at
this location. Nodes ‘MLCC1’, ‘MLCC2’, and ‘MLCC3’ represent the socket cavity and is
connected to the mid-frequency filter, C3, C4 and C5. MLCC1, MLCC2 and MLCC3
represent the parallel combination of all capacitors and capacitor parasitics at the
‘north’, ‘center’ and ‘south’ of the socket cavity, respectively.
Typical capacitor models are identified in Figure 2-18. Each model represents the
parallel combination of the local capacitor placement as identified in the previous
paragraph. Recommended parallel values of each parameter are identified in
Table 2-14. Consult Section 1.1 for further details regarding bulk and mid-frequency
capacitor selection.
The LGA1366 socket is characterized by two impedance paths that connect to the
motherboard at ‘SktN’ (‘north’ connection), and ‘SktS’ (‘south’ cavity connection).
I_PWL is a piece-wise linear current step that is used to stimulate the voltage droop
as seen at the motherboard-socket interface and is defined in Figure 2-21 and
Table 2-16. This load step approximates the low frequency current spectrum that is
necessary to evaluate bulk capacitor, mid-frequency capacitor and PWM controller
performance. It does not provide high frequency content to excite package noise. The
cavity capacitor solution, MLCC1, MLCC2 and MLCC3, are, are used as a reference for
designing processor packaging material and should not be modified except to reduce
ESR/ESL or increase total capacitance. Failure to observe this recommendation may
make the motherboard incompatible with some processor designs.
The primary purpose of the simulation model is to identify options in supporting the
loadline specification. Evaluation of the full power-path model will allow the designer
to perform what-if analysis to determine the cost optimal capacitor and PWM
controller configuration. This is especially useful in determining the capacitor
configuration that can support loadline specifications across variation such as
manufacturing tolerance, age degradation, and thermal drift. The designer is
encouraged to evaluate different capacitor configurations and PWM controller designs.
However, the designer should be aware that the feedback compensation network of
most PWM controllers requires modification when the capacitor solution changes.
Consult the PWM controller datasheet for further information.
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Processor Power Delivery Design Guidelines
LGA1366 Information
Figure 2-14. Example Voltage Droop Observed At Node ‘Sense’
Figure 2-14 provides an example voltage droop waveform at node ‘Sense’, the socketmotherboard interface. The loadline value is defined as ∆V/∆I with ∆V measured at
this node and the current step observed through I_PWL. The voltage amplitude is
defined as the difference in the steady state voltage (prior to the transient) and the
minimum voltage droop (consult Figure 2-14). Care must be taken to remove all
ripple content in this measurement to avoid a pessimistic loadline calculation that will
require additional capacitors (cost) to correct. Figure 2-15 provides an example
current stimulus. The amplitude is measured as the difference in maximum current
and steady state current prior to initiation of the current step. With ∆V and ∆I known,
the loadline slope is simply calculated using Ohm’s Law: RLL = ∆V/∆I.
Processor Power Delivery Design Guidelines
67
LGA1366 Information
Figure 2-15. Current Step Observed Through I_PWL
NOTE:
68
To avoid excessive ringing in simulation, the system current should be slowly ramped
from zero amps to the minimum recommended DC value prior to initiating the current
step.
Processor Power Delivery Design Guidelines
LGA1366 Information
Figure 2-16. Schematic Diagram for the Six-Layer Intel® Reference Motherboard
NOTE:
Consult Figure 2-7 to Figure 2-10 for reference layout.
Table 2-13. Parameter Values for the Schematic of Figure 2-16
Parameter
Value
RMB1
0.12 mΩ
‘North’ power plane parasitic resistance from the buck regulator
output inductor to the south power plane.
RMB2
0.36 mΩ
Power plane parasitic resistance from ‘south’ power plane from
the south bulk capacitors to the ‘north’ LGA1366 socket
connection.
RMB3
0.1 mΩ
Power plane parasitic resistance from the ‘north’ LGA1366 socket
connection to the ‘south’ LGA1366 socket connection.
RMB4
0.21 mΩ
Power plane parasitic resistance from the ‘south’ LGA1366 socket
connection to the ‘north’ of the LGA1366 socket cavity.
RMB5
0.12 mΩ
Power plane parasitic resistance from the ‘north’ of the LGA1366
socket cavity to the ‘center’ of the LGA1366 socket cavity.
RMB6
0.1 mΩ
Power plane parasitic resistance from the ‘center’ of the LGA1366
socket cavity to the ‘south’ of the LGA1366 socket cavity.
LMB1
15 pH
‘North’ power plane parasitic inductance from the buck regulator
output inductor to the south power plane.
Processor Power Delivery Design Guidelines
Comments
69
LGA1366 Information
Parameter
Value
Comments
LMB2
46 pH
Power plane parasitic inductance from ‘south’ power plane from
the south bulk capacitors to the ‘north’ LGA1366 socket
connection.
LMB3
12 pH
Power plane parasitic inductance from the ‘north’ LGA1366
socket connection to the ‘south’ LGA1366 socket connection.
LMB4
42 pH
Power plane parasitic inductance from ‘south’ LGA1366 socket
connection to the ‘north’ of the LGA1366 socket cavity.
LMB5
18 pH
Power plane parasitic inductance from the ‘north’ of the LGA1366
socket cavity to the ‘center’ of the LGA1366 socket cavity.
LMB6
10 pH
Power plane parasitic inductance from the ‘center’ of the
LGA1366 socket cavity to the ‘south’ of the LGA1366 socket
cavity.
Figure 2-17. Node Location for the Schematic of Figure 2-16
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Processor Power Delivery Design Guidelines
LGA1366 Information
Figure 2-18. Schematic Representation of Bulk Decoupling Capacitors
Processor Power Delivery Design Guidelines
71
LGA1366 Information
Figure 2-19. Schematic Representation of Mid-frequency Decoupling Capacitors
NOTES:
1.
C1 represents the
2.
C2 represents the
3.
C3 represents the
the socket cavity.
4.
C4 represents the
the socket cavity.
5.
C5 represents the
the socket cavity.
72
parallel model for ‘north’ location bulk decoupling.
parallel model for ‘south’ location bulk decoupling.
parallel model for mid-frequency decoupling located in the north of
parallel model for mid-frequency decoupling located in the center of
parallel model for mid-frequency decoupling located in the south of
Processor Power Delivery Design Guidelines
LGA1366 Information
Table 2-14. Recommended Parameter Values for the Capacitors Models
Parameter
Value
Ca
120 µF2
Single bulk capacitor 5-element model.
Ra
80 mΩ
Single bulk capacitor 5-element model.
Cb
380 µF
Single bulk capacitor 5-element model.
Rb
6 mΩ2
Single bulk capacitor 5-element model.
La
3 nH
Single bulk capacitor 5-element model.
C3
129 µF2
Parallel equivalent for ‘north cavity’ capacitors prior to age,
thermal, and manufacturing degradation.
R3
556 µΩ2
Parallel equivalent for ‘north cavity’ capacitor maximum ESR.
L3
2
1, 2
61.2 pH
1, 2
Comments
Parallel equivalent for ‘north cavity’ capacitor maximum ESL.
C4
100 µF2
Parallel equivalent for ‘center cavity’ capacitors prior to age,
thermal, and manufacturing degradation.
R4
714 µΩ2
Parallel equivalent for ‘center cavity’ capacitor maximum ESR.
L4
78.7 pH
C5
57 µF2
R5
1.25 mΩ2
Parallel equivalent for ‘south cavity’ capacitor maximum ESR.
L5
138 pH
Parallel equivalent for ‘south cavity’ capacitor maximum ESL.
1, 2
1, 2
Parallel equivalent for ‘center cavity’ capacitor maximum ESL.
Parallel equivalent for ‘south cavity’ capacitors prior to age,
thermal, and manufacturing degradation.
NOTES:
1.
Higher values of ESL may satisfy design requirements.
2.
Contact capacitor vendors to identify values for the specific components used in your
design
Processor Power Delivery Design Guidelines
73
LGA1366 Information
Figure 2-20. Schematic Representation of Socket Model
Table 2-15. Recommended Parameter Values for the Socket Model in Figure 2-20
Parameter
Value
Comments
RSKT1
0.4 mΩ
LGA1366 ‘north’ segment resistance
RSKT2
0.4 mΩ
LGA1366 ‘south’ segment resistance
RVTT1
0.42
mΩ
Resistance of VTT Tool load board
RVTT2
0.91
mΩ
Resistance of VTT Tool socket adapter (interposer)
RS
100 kΩ
LSKT1
50 pH
LGA1366 ‘north’ segment inductance
LSKT2
40pH
LGA1366 ‘south’ segment inductance
LVTT1
240 pH
LVTT2
42 pH
VTT Tool current source resistance
Inductance of VTT Tool load board
Inductance of VTT Tool socket adapter (interposer)
NOTES: These values are from the LGA 775 VTT Tool load board. The values will be updated
with values from the LGA 1366 VTT Tool load board when they become available.
74
Processor Power Delivery Design Guidelines
LGA1366 Information
Figure 2-21. Current Load Step Profile for I_PWL
Icc
IMAX
IMIN
t0
t1
t2
Time
Table 2-16. I_PWL Current Parameters for Figure 2-21
Parameter
Value
t0
0s
t1
100 µs
t2
t1 + 200 ns
Istep
100 A
Imin
45 A
Minimum current for simulation analysis1
Imax
145 A
Maximum current for simulation analysis1
NOTE:
1.
Comments
Simulation ‘time zero’
Time to initiate the current step. This parameter must be
chosen at a time that the VCC rail is residing at steady state.
Time of maximum current1
Current step for loadline testing1
See Table 2-5. Intel® Processor Current Step Values for Transient Loadline Testing
Processor Power Delivery Design Guidelines
75
LGA1366 Information
2.7
LGA1366 Voltage Regulator Configuration
Parameters
2.7.1
1366_VR_CONFIG_08B
Table 2-17. 1366_VR_CONFIG_08B Specification Input Parameters
Definition
Variable Name
Value
LL_SLOPE
0.8 mΩ
TOB
19 mV
Maximum Overshoot Above VID
OS_AMP
50 mV
Maximum Overshoot Time Duration Above VID
OS_TIME
25 us
RIPPLE
10 mV
THERMAL_DRIFT
2 mV
Iccmax
Iccmax
145 A
Dynamic Current Step
I_STEP
100 A
Maximum DC Test Current
I_DC_MAX
45 A
Minimum DC Test Current
I_DC_MIN
5A
Voltage Regulator Thermal Design Current
VR_TDC
110 A
Current step rise time
I_RISE
200 ns
Current step fall time for overshoot
I_FALL
200 ns
Loadline Slope
Loadline Tolerance Band
Peak To Peak Ripple Amplitude
Thermal Compensation Voltage Drift
§
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Processor Power Delivery Design Guidelines
LGA775 Information
3
LGA775 Information
3.1
Introduction
This chapter focuses on information unique to platforms designed with the LGA 775.
3.2
Processor VCC Requirements
3.2.1
Socket Loadline Definitions
(REQUIRED)
To maintain processor reliability and performance, platform DC voltage regulation and
transient-droop noise levels must always be contained within the Vccmin and Vccmax
socket loadline boundaries (known as the loadline window). Socket loadline
compliance must be ensured across 3-σ component manufacturing tolerances, thermal
variation, and age degradation. Socket loadline boundaries are defined by the
following equations in conjunction with the VCC regulator design parameter values
defined in Table 3-2. In these equations, VID, RLL, and TOB are known. Plotting VCC
while varying ICC from 0 A to Iccmax establishes the Vccmax and Vccmin socket
loadlines. Vccmax establishes the maximum DC socket loadline boundary. Vccmin
establishes the minimum AC and DC voltage boundary. Short transient bursts above
the Vccmax loadline are permitted; this condition is defined in Section 1.3.7.
Table 3-1. Socket Loadline Equations
Socket loadline
Equation
Equation 8: Vccmax Socket loadline
VCC = VID – (RLL* ICC)
Equation 9: Vcctyp Socket loadline
VCC = VID – TOB - (RLL* ICC)
Equation 10: Vccmin Socket loadline
VCC = VID – 2*TOB - (RLL* ICC)
Socket loadline recommendations are established to provide guidance for satisfying
processor die loadline specifications, which are defined in processor datasheets. Die
loadline requirements must be satisfied at all times and may require adjustment in the
socket loadline value. The processor die loadlines are defined in the applicable
processor datasheet.
Processor Power Delivery Design Guidelines
77
LGA775 Information
Table 3-2. VCC Regulator Design Parameters
Iccmax
VR
TDC
Dynamic
ICC
RLL
TOB
Max
VID
775_VR_CONFIG_04A
78 A
68 A
55 A
1.40 mΩ
±25 mV
1.4 V
775_VR_CONFIG_04B
119 A
101 A
95 A
1.00 mΩ
±19 mV
1.4 V
775_VR_CONFIG_05A
100 A
85 A
65 A
1.00 mΩ
±19 mV
1.4 V
775_VR_CONFIG_05B
125 A
115 A
95 A
1.00 mΩ
±19 mV
1.4 V
75 A
60 A
50 A
1.00 mΩ
±19 mV
1.425 V
VR Configuration
775_VR_CONFIG_06
VRD transient socket loadline circuits should be designed to meet or exceed rated
conditions defined in Table 3-2. For example, 775_VR_CONFIG_04A requires a socket
loadline slope of 1.40 mΩ. A transient socket loadline slope of 1.0 mΩ will satisfy this
requirement without adversely impacting system performance or processor lifespan.
This condition may be necessary when supporting multiple processors with a single
VRD design. However, the static loadline condition must be set to the recommended
value unless explicitly stated otherwise in the processor datasheet. Operating at a low
loadline resistance will result in higher processor operating temperature, which may
result in damage or a reduced processor life span. Processor temperature rise from
higher functional voltages may lead to operation at low power states which directly
reduces processor performance. Operating at a higher loadline resistance will result in
minimum voltage violations which may result in system lock-up, “blue screening”, or
data corruption.
Table 3-2 provides a comprehensive list of VRD11 LGA775 voltage regulator design
configurations. The configurations to be adopted by VRD hardware will depend on the
specific processors the design is intended to support. It is common for a motherboard
to support processors that require different VR configurations. In this case, the VCC
regulator design must meet the specifications of all processors supported by that
board. For example, If a motherboard is targeted to support processors that require
775_VR_CONFIG_04A and 775_VR_CONFIG_04B, then the voltage regulator must
have the ability to support 101 A of VR TDC, 119 A of electrical peak current, satisfy
overshoot requirements of the Processor VCC Overshoot Section with a dynamic load
step of 95 A, satisfy a VRD tolerance band of ±19 mV.
The following tables and figures show minimum and maximum voltage boundaries for
each socket loadline design configuration defined in Table 3-2. VCCTYP socket loadlines
are provided for design reference; designs should calibrate the socket loadline to this
case (centered in the loadline window, at the mean of the tolerance band). Different
processors discussed in this design guide can be shipped with different VID values.
The reader should not assume that processors with similar characteristics will have
the same VID value. Typical values will range from 1.1 V to 1.6 V in 6.25 mV
increments. A single loadline chart and figure for each VRD design configuration can
represent functionality for each possible VID value. Tables and figures presented as
voltage deviation from VID provide the necessary information to identify voltage
requirements at any reference VID. This avoids the redundancy of publishing tables
and figures for each of the multiple cases.
78
Processor Power Delivery Design Guidelines
LGA775 Information
3.2.1.1
Socket Loadline Definition for 775_VR_CONFIG_04A
Figure 3-1. Socket Loadline Window for 775_VR_CONFIG_04A
0A
10 A
20 A
30 A
40 A
50 A
60 A
70 A
80 A
0.00 V
-0.05 V
-0.10 V
-0.15 V
-0.20 V
Vmax Load Line
Vtyp Load Line
Vmin Load Line
NOTES:
1.
Presented as a deviation from VID
2.
Socket loadline Slope = 1.4 mΩ, TOB = ±25 mV
3.
Consult Table 3-2 for VR configuration parameter details
Table 3-3. Socket Loadline Window for 775_VR_CONFIG_04A
ICC
Maximum
Typical
Minimum
0A
0.000 V
-0.025 V
-0.050 V
10 A
-0.014 V
-0.039 V
-0.064 V
20 A
-0.028 V
-0.053 V
-0.078 V
30 A
-0.042 V
-0.067 V
-0.092 V
40 A
-0.056 V
-0.081 V
-0.106 V
50 A
-0.070 V
-0.095 V
-0.120 V
60 A
-0.084 V
-0.109 V
-0.134 V
70 A
-0.098 V
-0.123 V
-0.148 V
78 A
-0.111 V
-0.134 V
-0.159 V
NOTES:
1.
Presented as a deviation from VID
2.
Socket loadline Slope = 1.4 mΩ, TOB = ±25 mV
3.
Consult Table 3-2 for VR configuration parameter details
Processor Power Delivery Design Guidelines
79
LGA775 Information
3.2.1.2
Socket Loadline Definition for 775_VR_CONFIG_04B, 05A, 05B, 06
The socket loadline for 775_VR_CONFIG_04B, 05A, 05B and 06 can be implemented
in a piece-wise linear fashion. The socket loadline should have a 1 mΩ slope when the
load frequency content is in the range of 0 to 100 kHz. When the load frequency is in
the range of >100 kHz to 1 MHz, a loadline slope of up to 1.2 mΩ is allowed. See
Figure 3-2.
Figure 3-2. Piece-wise Linear Socket Loadline
1.25
Loadline Slope (mΩ)
1.2
1.15
Allowable Region
1.1
1.05
1
0.95
0
10 kHz
100 kHz
1 MHz
Load Frequency
80
Processor Power Delivery Design Guidelines
LGA775 Information
Figure 3-3. Socket Loadline Window for 775_VR_CONFIG_04B, 05A, 05B (0–100 kHz
loadstep rate)
0A
20 A
40 A
60 A
80 A
100 A
120 A
0.00 V
-0.02 V
-0.04 V
-0.06 V
-0.08 V
-0.10 V
-0.12 V
-0.14 V
-0.16 V
-0.18 V
Vmax Load Line
Vtyp Load Line
Vmin Load Line
NOTES:
1.
Presented as a deviation from VID
2.
Socket loadline Slope = 1.0 mΩ, TOB = ±19 mV
3.
Consult Table 3-2 for VR configuration parameter details
Table 3-4.
Socket Loadline Window for 775_VR_CONFIG_04B, 05A, 05B (0–100 kHz
loadstep rate)
ICC
Maximum
Typical
Minimum
0A
0.000 V
-0.019 V
-0.038 V
20 A
-0.020 V
-0.039 V
-0.058 V
40 A
-0.040 V
-0.059 V
-0.078 V
60 A
-0.060 V
-0.079 V
-0.098 V
80 A
-0.080 V
-0.099 V
-0.118 V
100 A
-0.100 V
-0.119 V
-0.138 V
120 A
-0.120 V
-0.139 V
-0.158 V
125 A
-0.125 V
-0.144 V
-0.163 V
NOTES:
1.
Presented as a deviation from VID
2.
Socket loadline Slope = 1.0 mΩ, TOB = ±19 mV
3.
Consult Table 3-2 for VR configuration parameter details
Processor Power Delivery Design Guidelines
81
LGA775 Information
Figure 3-4. Socket Loadline Window for 775_VR_CONFIG_04B, 05A, 05B
(>100 kHz–1 MHz loadstep Rate)
0A
20 A
40 A
60 A
80 A
100 A
120 A
0.00 V
-0.05 V
-0.10 V
-0.15 V
-0.20 V
Vmax Load Line
Vtyp Load Line
Vmin Load Line
NOTES:
1.
Presented as a deviation from VID
2.
Socket loadline Slope = 1.2 mΩ, TOB = ±19 mV
3.
Consult Table 3-2 for VR configuration parameter details
Table 3-5. Socket Loadline Window for 775_VR_CONFIG_04B, 05A, 05B
(>100 kHz-1 MHz loadstep Rate)
ICC
Maximum
Typical
Minimum
0A
0.000 V
-0.019 V
-0.038 V
20 A
-0.024 V
-0.043 V
-0.062 V
40 A
-0.048 V
-0.067 V
-0.086 V
60 A
-0.072 V
-0.091 V
-0.110 V
80 A
-0.096 V
-0.115 V
-0.134 V
100 A
-0.120 V
-0.139 V
-0.158 V
120 A
-0.144 V
-0.163 V
-0.182 V
125 A
-0.150 V
-0.169 V
-0.188 V
NOTES:
1.
Presented as a deviation from VID
2.
Socket loadline Slope = 1.2 mΩ, TOB = ±19 mV
3.
Consult Table 3-2 for VR configuration parameter details
82
Processor Power Delivery Design Guidelines
LGA775 Information
Figure 3-5. Socket Loadline Window for Design Configurations 775_VR_CONFIG_06 (0–
100 kHz Loadstep Rate)
0A
10 A
20 A
30 A
40 A
50 A
60 A
70 A
80 A
0.00 V
-0.02 V
-0.04 V
-0.06 V
-0.08 V
-0.10 V
-0.12 V
-0.14 V
Vmax Load Line
Vtyp Load Line
Vmin Load Line
NOTES:
1.
Presented as a deviation from VID
2.
Socket loadline Slope = 1.0 mΩ, TOB = ±19 mV
3.
Consult Table 3-2 for VR configuration parameter details
Table 3-6. Socket Loadline Window for 775_VR_CONFIG_06 (0–100 kHz Loadstep
Rate)
ICC
Maximum
Typical
Minimum
0A
0.000 V
-0.019 V
-0.038 V
20 A
-0.020 V
-0.039 V
-0.058 V
40 A
-0.040 V
-0.059 V
-0.078 V
60 A
-0.060 V
-0.079 V
-0.098 V
80 A
-0.080 V
-0.099 V
-0.118 V
NOTES:
1.
Presented as a deviation from VID
2.
Socket loadline Slope = 1.0 mΩ, TOB = ±19 mV
3.
Consult Table 3-2 for VR configuration parameter details
Processor Power Delivery Design Guidelines
83
LGA775 Information
Figure 3-6. Socket Loadline Window for Design Configurations 775_VR_CONFIG_06
(>100 kHz-1 MHz Loadstep Rate)
0A
10 A
20 A
30 A
40 A
50 A
60 A
70 A
80 A
0.00 V
-0.02 V
-0.04 V
-0.06 V
-0.08 V
-0.10 V
-0.12 V
-0.14 V
-0.16 V
Vmax Load Line
Vtyp Load Line
Vmin Load Line
NOTES:
1.
Presented as a deviation from VID
2.
Socket loadline Slope = 1.2 mΩ, TOB = ±19 mV
3.
Consult Table 3-2 for VR configuration parameter details
Table 3-7. Socket Loadline Window for 775_VR_CONFIG_06 (>100 kHz–1 MHz
Loadstep Rate)
ICC
Maximum
Typical
Minimum
0A
0.000 V
-0.019 V
-0.038 V
20 A
-0.024 V
-0.043 V
-0.062 V
40 A
-0.048 V
-0.067 V
-0.086 V
60 A
-0.072 V
-0.091 V
-0.110 V
80 A
-0.096 V
-0.115 V
-0.134 V
NOTES:
1.
Presented as a deviation from VID
2.
Socket loadline Slope = 1.2 mΩ, TOB = ±19 mV
3.
Consult Table 3-2 for VR configuration parameter details
Reference nodes for socket loadline measurements and voltage regulation are located
in the land field between the socket cavity and the voltage regulator region. See
Figure 3-7 VRD Phase Orientation. References for north phase configurations are
identified in Table 3-8. It is recommended to place motherboard test points at this
location to enable loadline calibration.
VRD layout studies indicate that the highest phase count is best located north of the
processor with the controller to the southeast.
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Processor Power Delivery Design Guidelines
LGA775 Information
Table 3-8. Socket Loadline Reference Lands
Orientation
Land
VCC_MB_SENSE (North Vcc)
U27
VSS_MB_SENSE (North VSS)
V26
VCC_MB_REGULATION (SE Vcc Jumper)
AN5
VSS_MB_REGULATION (SE VSS Jumper)
AN6
VCC_DIE_SENSE
AN3
VSS_DIE_SENSE
AN4
Figure 3-7. VRD Phase Orientation
PHASES
Reference
Node
CAVITY
North
West
SOCKET
East
South
To properly calibrate the socket loadline parameter, the VR designer must excite the
processor socket with a current step that generates a voltage droop which must be
checked against the loadline window requirements. Table 3-9 identifies the steady
state and transient current values to use for this calibration.
Table 3-9. Intel® Processor Current Step Values for Transient Socket loadline Testing
VR Configuration
Starting
Current
Ending
Current
Dynamic Current
Step
ICC Rise
Time
775_VR_CONFIG_04A
23 A
78 A
55 A
83 A/µs
775_VR_CONFIG_04B
24 A
119 A
95 A
83 A/µs
775_VR_CONFIG_05A1
20 A
85 A
65 A
50 ns
775_VR_CONFIG_05B1
30 A
125 A
95 A
50 ns
775_VR_CONFIG_061
25 A
75 A
50 A
50 ns
NOTES:
1.
775_VR_CONFIG_05A and 775_VR_CONFIG_05B configurations may be used with
some board configurations
Processor Power Delivery Design Guidelines
85
LGA775 Information
VRD designs must be socket loadline compliant across the full tolerance band window
to avoid data corruption, system lock-up, and reduced performance. When validating
a system’s socket loadline, a single measurement is statistically insignificant and
cannot represent the response variation seen across the entire high volume
manufacturing population of VRD designs. A typical socket loadline may fit in the
specification window; however designs residing elsewhere in the tolerance band
distribution may violate the specifications. Figure 3-8 Example A shows a loadline that
is contained in the specification window and, this single instance, complies with
Vccmin and Vccmax specifications. The positioning of this socket loadline will shift up
and down as the tolerance drifts from typical to the design limits. Figure 3-8 Example
B shows that Vccmax limits will be violated as the component tolerances shift the
loadline to the upper tolerance band limits. Figure 3-8 Example C shows that the
Vccmin limits will be violated as the component tolerances shift the loadline to the
lower tolerance band limits.
To satisfy specifications across high volume manufacturing variation, a typical socket
loadline must be centered in the loadline window and have a slope equal to the value
specified in Table 3-2. Figure 3-9 Example A shows a socket loadline that meets this
condition. Under full 3-σ tolerance band variation, the loadline slope will intercept the
Vccmax loadline (Figure 3-9 Example B) or Vccmin loadline (Figure 3-9 Example C)
limits.
Figure 3-8. Examples of High Volume Manufacturing Loadline Violations
Measured Load Line
VID
Vccmax LL VID
Vccmin LL
Example A: This load line
satisfies voltage limits, but will
violate specifications as the VR
TOB varies across the minimum
to maximum range
86
3-σ Manufacturing LL
Vccmax LL
Vccmin LL
Vccmax
Violation
VID
3-σ Manufacturing LL
Vccmax LL
Vccmin LL
Vccmin
Violation
Example C: Vccmin violation
Example B: Vccmax violation
when component tolerance shift when component tolerance shift
Load Line to the lower TOB
Load Line to the upper TOB
limits
limits
Processor Power Delivery Design Guidelines
LGA775 Information
Figure 3-9. High Volume Manufacturing Compliant Loadline
3-σ Manufacturing LL
Measured Load Line
VID
Vccmax LL
VID
Vccmin LL
Example A: Measured load line
satisfies slope specification
and is centered in the LL
window
3.2.1.3
Vccmax LL
3-σ Manufacturing LL
Vccmax LL
VID
Vccmin LL
Example B: When component
tolerances shift the load line to
the lower TOB limits, the 3-σ
manufacturing LL is bounded by
the Vccmin LL
Vccmin LL
Example C: When component
tolerances shift the load line to
the upper TOB limits, the 3-σ
manufacturing load line is
bounded by the Vccmax LL
Time Domain Validation
To ensure processor reliability and performance, platform transient-droop and
overshoot noise levels must always be contained within the Vccmin and Vccmax
socket loadline boundaries (known as the loadline window). The load generates a
voltage droop, or overshoot, which must be checked against the loadline window
requirements. The current step must have a fast enough slew rate to excite the
impedance across the frequency range of the VR. In addition, the VR needs to be
tested at different load frequencies and load steps to prevent any non-linear,
resonant, or beating effects that could cause functional issues or loadline violations.
Intel recommends sweeping the load frequency from DC to 1 MHz, using two different
load steps.
Intel recommends testing using different VID levels for each of the supported VR
configurations. In particular the highest and lowest VIDs should be checked. The VID
ranges for each processor is available in the processor datasheet.
Processor Power Delivery Design Guidelines
87
LGA775 Information
Figure 3-10. 200 Hz, 100 A Step Droop Waveform
NOTE:
The cursor indicates the droop area of interest. A falling edge with a width less than
100 ns can be ignored.
Figure 3-11. 250 kHz, 100 A Step Waveform
NOTE:
88
The cursor indicates the droop area of interest. A falling edge with a width less than
100 ns can be ignored.
Processor Power Delivery Design Guidelines
LGA775 Information
3.2.1.4
Platform Impedance Measurement and Analysis (Expected)
In addition to the tuning of the loadline with Vdroop testing and DC loadline testing,
the decoupling capacitor selection needs to be analyzed to make sure the impedance
of the decoupling is below the loadline target up to the frequency Fbreak as defined in
Figure 2-4. This analysis can be done with impedance testing or through power
delivery simulation if the designer can extract the parasitic resistance and inductance
of the power planes on the motherboard and they have good models for the
decoupling capacitors.
Measured power delivery impedance should be with in the tolerance band shown in
Figure 3-12. For Loadline compliance, time domain validation is required and the VR
tolerance band must be met at all times. Above 500 kHz, the minimum impedance
tolerance is not defined and is determined by the MLCC capacitors required to get the
ESL low enough to meet the loadline impedance target at the Fbreak frequency. At
1 MHz, the Zmax tolerance drops to the loadline target impedance. Any resonance
points that are above the Zmax line need to be carefully evaluated with time domain
method defined in Section 3.2.1.3 by applying transient loads at that frequency and
looking for Vmin violations. Maintaining the impedance profile up to Fbreak is important
to ensure the package level decoupling properly matches the motherboard impedance.
After Fbreak, the impedance measurement is permitted to rise at a inductive slope. The
motherboard VR designer does not need to design for frequencies over Fbreak as the
processor package decoupling takes over in the region above Fbreak.
Figure 3-12. Power Distribution Impedance versus Frequency
Ω
Zone 1
PWM Droop control
& compensation
bandwidth
Zone 2
Output Filter
Bulk & MLCC
ZLL Max
Zone 3
Inductive effects
MLCC ESL +
Socket
Z target = ZLL
ZLL Min
Hz
VR BW
Fbreak
500 kHz
1 MHz
NOTES:
1.
See Table 3-10. Impedance Measurement Parameters definitions
2.
Zone 1 is defined by the VR closed loop compensation bandwidth (VR BW) of the
voltage regulator. Typically 30–40 kHz for a 300 kHz voltage regulator design.
3.
Zones 2 and 3 are defined by the output filter capacitors and interconnect parasitic
resistance and inductance. The tolerance is relaxed over 500 kHz allowing the VR
designer freedom to select output filter capacitors. The goal is to keep Z(f) below ZLL
up to Fbreak and as flat as practical, by selection of bulk capacitor values and type and
number of MLCC capacitors. The ideal impedance would be between ZLL and ZLL Min
but this may not be achieved with standard decoupling capacitors.
Processor Power Delivery Design Guidelines
89
LGA775 Information
Table 3-10. Impedance Measurement Parameters
3.3
Parameter
Value
Notes:
ZLL
1 mΩ
LGA775 Desktop LL target
ZLL max
1.2 mΩ
Based on VR11 PWM tolerance band
ZLL min
0.8 mΩ
Based on VR11 PWM tolerance band
Fbreak
2.0 MHz
-
PSI# Operation
PSI# from an LGA775 platform with a Intel® Core™2 Duo processor or Intel® Core™2
Quad processor will be asserted when the processor enters the C4 state. Additionally,
a large step DVID jump as much as 250 mV will occur at the same time. The VR will
recover from this event within the timeframe specified for large DVID jumps, which is
within 10 us per 100 mV. The timing diagram below shows a 250 mV step.
GNS Clock on
BCLK
PSI# & DPRSTP# = C4
Low Current
PSI#
VID
VID = C4
VID =C0 / VID_Hi
VID = VID_Lo
VID =C0 / VID_Hi
50
usec
1ms, 10ms, 15.6ms
Start State
25uS VCC-CORE Caps
Charge
DPRSTP#
Vcc= Voltage Hi
Vcc= Voltage Hi
Capac
VCC-CORE
itors d
C0
90
C2 ..
C3
ischarg
Vcc= Voltage Lo
e
C4
C3
C0
Processor Power Delivery Design Guidelines
LGA775 Information
3.4
VTT Requirements (REQUIRED)
The VTT regulator provides power to the processor VID circuitry, the chipset processor front side bus, and miscellaneous buffer signals. This rail voltage must
converge to the amplitude defined in Table 3-11 to begin power sequencing. The VR11
PWM controller will sense the amplitude of the VTT rail and initiate power sequencing
upon crossing a defined threshold voltage. The VTT regulator controller does not
include an enable signal; valid output voltage of Table 3-11 must be ensured by the
timing protocol defined in the Start-up Sequence diagram.
3.4.1
Electrical Specifications
A linear regulator is recommended for the VTT supply with adequate decoupling
capacitors to ensure the sum of AC bus noise and DC tolerance satisfy limits identified
in Table 3-11. The processor and chipset VTT supply must be maintained within these
tolerance limits across full operational thermal limits, part-to-part component
variation, age degradation, and regulator accuracy. Full bandwidth bus noise
amplitude must be ensured across all Vcc/ VSS land pairs defined in Table 3-12.
The VTT supply must be unconditionally stable under all DC and transient conditions
across the voltage and current ranges defined in Table 3-11. The VTT supply must also
operate in a no-load condition (that is, with no processor installed).
Vtt_SEL is an output from the processor that indicates to the VTT regulator the
appropriate output voltage. The Vtt_SEL output is either an open circuit (Vtt_SEL = 1)
or directly tied to the processor VSS (Vtt_SEL = 0).
Table 3-11. VTT Specifications
Processor
775_VR_CONFIG_04A
775_VR_CONFIG_04B
775_VR_CONFIG_05A
775_VR_CONFIG_05B
775_VR_CONFIG_06
VTT
Min
VTT Typ
VTT
Max
Itt Min
Itt Typ
Itt
Max
1.140 V
1.200 V1
1.260 V
0.15 A
3.4 A
5.25 A2
1.045 V
1.100 V1
1.155 V
0.15 A
3.4 A
5.25 A2
Vtt_SEL = 1
Future LGA775
configurations
Vtt_SEL = 0
NOTES:
1.
Combined DC and Transient voltage tolerance is 5%, with a maximum 2% DC
tolerance.
2.
Itt can be up to 7.5 A at power-up. This is applicable when VCC is low and VTT is high.
Table 3-12. VTT Measurement Lands
Device
Supply
Land
Processor
VTT
D25
Processor
VSS
E25
Processor Power Delivery Design Guidelines
91
LGA775 Information
3.5
MB Power Plane Layout (REQUIRED)
The motherboard layer stack-up must be designed to ensure robust, noise-free power
delivery to the processor. Failure to minimize and balance power plane resistance may
result in non-compliance to the die loadline specification. A poorly planned stack-up or
excessive holes in the power planes may increase system inductance and generate
oscillation on the VCC voltage rail at the processor. Both of these types of design
errors can lead to processor failure and must be avoided by careful VCC and VSS plane
layout and stack-up. The types of noise introduced by these errors may not be
immediately observed on the processor power lands or during system-board voltage
transient validation, so issues must be resolved by design, prior to layout, to avoid
unexpected failures.
Following basic layout rules can help avoid excessive power plane noise. All
motherboard layers in the area surrounding the processor socket should be used for
VCC power delivery; copper shapes that encompass the power delivery region of the
processor land field are required. A careful motherboard design will help ensure a
well-functioning system that minimizes the noise profile at the processor die. The
following subsections provide further guidance.
3.5.1
Minimize Power Path DC Resistance
Power path resistance can be minimized by ensuring that the copper layout area is
balanced between VCC and VSS planes. A good four-layer board design will have two
VCC layers and two VSS layers. Because there is generally more VSS copper in the
motherboard stack-up, care should be taken to maximize the copper in VCC floods.
This includes care to minimize unnecessary plane splits and holes when locating
through hole components, vias, and connection pads. Refer to Table 3-13 for more
details on the reference board layer stackup.
3.5.2
Minimize Power Delivery Inductance
At higher frequencies the ordering of the motherboard layers becomes critical as it is
VCC/ VSS plane pairs which carry current and determine power plane inductance. The
layer stack-up should maximize adjacent (layer-to-layer) planes at a minimized
spacing to achieve the smallest possible inductance. Care must be taken to minimize
unnecessary plane splits and holes when locating through-hole components, vias, and
connection pads. Minimized inductance will ensure that the board does not develop
low frequency noise which may cause the processor to fail (loadline violation).
3.5.3
Four-Layer Boards
A well-designed 4-layer board will feature generous VCC shapes on the outer layers
and large VSS shapes on the inner layers. The VSS -reference requirements for the
front side bus are best accommodated with this layer ordering. The power plane area
should be maximized and cut-out areas should be carefully placed to minimize
parasitic resistance and inductance. Examples power plane layout of the Intel
reference board are provided in Table 3-13 and Figure 3-13 through Figure 3-17.
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Processor Power Delivery Design Guidelines
LGA775 Information
Figure 3-13. Reference Board Layer Stack-up
L1 Solder mask
Layer L1: Plated 1/2 oz Copper
L1-2 FR4
Layer L2: Unplated 1 oz Copper
CORE
Layer L3: Unplated 1 oz Copper
L3-4 FR4
Layer L4: Plated 1/2 oz Copper
L4 Solder mask
NOTE:
Drawing is not to scale
Table 3-13. Reference Board Layer Thickness (Prepreg 1080)
Layer
Minimum
Typical
Maximum
L1 Solder mask
0.2 mils
0.7 mils
1.2 mils
L1
1.1 mils
1.9 mils
2.7 mils
L1-2 FR4
2.0 mils
2.7 mils
3.5 mils
L2
1.0 mils
1.2 mils
1.4 mils
Core
45 mils
50 mils
55 mils
L3
1.0 mils
1.2 mils
1.4 mils
L3-4 FR4
2.0 mils
2.7 mils
3.5 mils
L4
1.1 mils
1.9 mils
2.7 mils
L4 Solder mask
0.2 mils
0.7 mils
1.2mils
NOTES:
1.
Consult Figure 2-6 for layer definition
2.
Impedance Target: 50 Ω ± 15%; based on nominal 4 mil trace
3.
Overall board thickness is 62 mils +8, -5 mils
Processor Power Delivery Design Guidelines
93
LGA775 Information
Figure 3-14. Layer 1 VCC Shape for Intel® Reference Four-layer Motherboard
.
94
Processor Power Delivery Design Guidelines
LGA775 Information
Figure 3-15. Layer 2 VSS Routing for Intel® Reference Four-layer Motherboard
Figure 3-16. Layer 3 VSS Routing for Intel® Reference Four-layer Motherboard
Processor Power Delivery Design Guidelines
95
LGA775 Information
Figure 3-17. Layer 4 VCC Shape for Intel® Reference Four-layer Motherboard
3.5.4
Six-Layer Boards
Six layer boards provide layout engineers with greater design flexibility compared to
the four-layer standard. Adjacent plane pairs of the same potential are not useful at
higher frequencies, so the best approach is to maximize adjacent, closely spaced VCC/
VSS plane pairs. The plane pair separated by the PCB core material is of lesser
importance since it is generally an order of magnitude larger in spacing than other
plane pairs in the stack-up. Because the VSS planes are typically full floods of copper,
an example of a well-designed 6-layer stack-up will have 4 VCC layers and 2 layers for
VSS. The DC resistive requirements (Section 3.5.1) of the power delivery loop can still
be met because the VSS floods are larger than the VCC floods, and the higher frequency
needs are considered as there are 4 VCC/ VSS plane pairs to deliver current and reduce
inductance.
3.5.5
Resonance Suppression
VCC power delivery designs can be susceptible to resonance phenomena capable of
creating droop amplitudes in violation of loadline specifications. This is due to the
interleaved levels of inductively-separated decoupling capacitance. Furthermore, these
resonances may not be detected through standard validation and require engineering
analysis to identify and resolve. If not identified and corrected in the design process,
these resonant phenomena may yield droop amplitudes in violation of loadline
specifications by superimposing with standard VRD droop behavior. Frequencydependent power delivery network impedance simulations and validation are strongly
96
Processor Power Delivery Design Guidelines
LGA775 Information
recommended to identify and resolve power delivery resonances before board are
actually built. Careful modeling and validation can help to avoid voltage violations
responsible for data corruption, system lock-up, or system ‘blue-screening’.
3.6
Electrical Simulation (EXPECTED)
The following electrical models are enclosed to assist with VRD design analysis and
component evaluation for loadline compliance. The block diagram shown in
Figure 3-18 is a simplified representation of the VCC power delivery network of the
Intel four-layer reference board). The board model, detailed in Figure 3-21,
characterizes the power plane layout of Figure 3-14 to Figure 3-17. The multiphase
buck regulator and capacitor models should be obtained from each selected vendor.
When fully integrated into electrical simulation software, this model can be used to
evaluate PWM controller, capacitor, and inductor performance against the loadline and
tolerance band requirements detailed in Section 3.2.1. To obtain accurate results, it is
strongly recommended to create and use a custom model that represents the specific
board design, PWM controller, and passive components that are under evaluation.
Figure 3-18. Simplified Reference Block Diagram
North Phase Inductors
Multi-Phase Buck
Regulator
Output: North Phases
Output: East Phases
East Phase Inductors
Error Amplifier Input
N5
Motherboard
N1
N2
N2
N4
N4
N6
N6
Socket
And
VTT Tool
N3
C1
C3
C2
North
Bulk
Caps
East
Bulk
Caps
High
Frequency
Filtering
Capacitance
NOTE:
Consult Figure 3-14 to Figure 3-17 for reference layout.
The motherboard model of Figure 3-21 represents the power delivery path of Intel’s
reference four-layer motherboard design. Input and output node locations are
Processor Power Delivery Design Guidelines
97
LGA775 Information
identified in Figure 3-22. Feedback to the PWM controller error amplifier should be
tied to node ‘N2’, the socket-motherboard interface. Node ‘N1’ is the location where
the ‘north’ phase inductors of the buck regulator ties to the ‘north’ motherboard power
plane. If the design incorporates more than one ‘north’ phase, the inductors of each
should be tied to this node. ‘North’ bulk capacitors, C1, are also connected to node
‘N1’. C1 represents the parallel combination of all capacitors and capacitor parasitics
at this location. Node ‘N5’ is the location where the output inductors of the ‘east’ side
phases tie to the ‘east’ motherboard power plane. If the design incorporates more
than one ‘east’ phase, the inductors of each should be tied to this node. ‘East’ bulk
capacitors, C3, are also connected to ‘N5’. C3 represents the parallel combination of
all capacitors and capacitor parasitics at this location. Node ‘N3’ represents the socket
cavity and is connected to the mid-frequency filter, C2. C2 represents the parallel
combination of all capacitors and capacitor parasitics at this location.
Typical capacitor models are identified in Figure 3-23. Each model represents the
parallel combination of the local capacitor placement as identified in the previous
paragraph. Recommended parallel values of each parameter are identified in
Table 3-15.
The LGA775 socket is characterized by three impedance paths that connect to the
motherboard at ‘N2’ (‘north’ connection), ‘N4’ (‘south’ cavity connection), and ‘N6’
(‘east’ connection). I_PWL is a piece-wise linear current step that is used to stimulate
the voltage droop as seen at the motherboard-socket interface and is defined in
Figure 2-21 and Table 2-16. This load step approximates the low frequency current
spectrum that is necessary to evaluate bulk capacitor, mid-frequency capacitor and
PWM controller performance. It does not provide high frequency content to excite
package noise. The cavity capacitor solution, C2, is used as a reference for designing
processor packaging material and should not be modified except to reduce ESR/ESL or
increase total capacitance. Failure to observe this recommendation may make the
motherboard incompatible with some processor designs.
The primary purpose of the simulation model is to identify options in supporting the
socket loadline specification. Evaluation of the full power-path model will allow the
designer to perform what-if analysis to determine the cost optimal capacitor and PWM
controller configuration. This is especially useful in determining the capacitor
configuration that can support loadline specifications across variation such as
manufacturing tolerance, age degradation, and thermal drift. The designer is
encouraged to evaluate different capacitor configurations and PWM controller designs.
However, the designer should be aware that the feedback compensation network of
most PWM controllers requires modification when the capacitor solution changes.
Consult the PWM controller datasheet for further information.
98
Processor Power Delivery Design Guidelines
LGA775 Information
Figure 3-19. Example Voltage Droop Observed At Node ‘N2’
∆V
Figure 2-14 provides an example voltage droop waveform at node ‘N2’, the socketmotherboard interface. The loadline value is defined as ∆V/∆I with ∆V measured at
this node and the current step observed through I_PWL. The voltage amplitude is
defined as the difference in the steady state voltage (prior to the transient) and the
minimum voltage droop (consult Figure 2-14). Care must be taken to remove all
ripple content in this measurement to avoid a pessimistic loadline calculation that will
require additional capacitors (cost) to correct. Figure 2-15 provides an example
current stimulus. The amplitude is measured as the difference in maximum current
and steady state current prior to initiation of the current step. With ∆V and ∆I known,
the loadline slope is simply calculated using Ohm’s Law: RLL =
Processor Power Delivery Design Guidelines
∆V/∆I.
99
LGA775 Information
Figure 3-20. Current Step Observed Through I_PWL
∆I
NOTE:
100
To avoid excessive ringing in simulation, the system current should be slowly ramped
from zero amps to the minimum recommended DC value prior to initiating the current
step.
Processor Power Delivery Design Guidelines
LGA775 Information
Figure 3-21. Schematic Diagram for the Four-layer Intel® Reference Motherboard
N1
N2
RMB1
LMB1
RMB2
LMB2
N4
N3
RMB3
LMB3
LMB4
RMB4
RMB5
N5
NOTE:
LMB5
N6
Consult Figure 3-14 to Figure 3-17 for reference layout.
Table 3-14. Parameter Values for the Schematic of Figure 3-21
Parameter
Value
RMB1
0.64 mΩ
‘North’ power plane parasitic resistance from the buck regulator
output inductor to the LGA775 socket connection.
RMB2
0.56 mΩ
Power plane parasitic resistance from ‘north’ LGA775
motherboard connection to the center of the LGA775 cavity.
RMB3
0.59 mΩ
Power plane parasitic resistance from the center of the LGA775
cavity to the ‘south’ LGA775 socket connection.
RMB4
0.59 mΩ
Power plane parasitic resistance from the center of the LGA775
cavity to the ‘east’ LGA775 socket connection.
RMB5
0.58 mΩ
‘East’ power plane parasitic resistance from the buck regulator
output inductor to the LGA775 connection.
LMB1
120 pH
‘North’ power plane parasitic inductance from the buck regulator
output inductor to the LGA775 socket connection
LMB2
166 pH
Power plane parasitic inductance from ‘north’ LGA775
motherboard connection to the center of the LGA775 cavity.
LMB3
166 pH
Power plane parasitic inductance from the center of the LGA775
cavity to the ‘south’ LGA775 socket connection.
LMB4
247 pH
Power plane parasitic inductance from ‘east’ LGA775
motherboard connection to the center of the LGA775 cavity.
LMB5
138 pH
‘East’ power plane parasitic inductance from the buck regulator
output inductor to the LGA775 connection.
Processor Power Delivery Design Guidelines
Comments
101
LGA775 Information
Figure 3-22. Node Location for the Schematic of Figure 3-21
North
N1
West
N2
N4 N3
N6
South
N5
East
102
Processor Power Delivery Design Guidelines
LGA775 Information
Figure 3-23. Schematic Representation of Decoupling Capacitors
N5
N3
N1
C1
C2
C3
R1
R2
R3
L1
L2
L3
NOTES:
1.
C1 represents the parallel model for ‘north’ location bulk decoupling.
2.
C2 represents the parallel model for mid-frequency decoupling located in the socket
cavity.
3.
C3 represents the parallel model for ‘east’ location bulk decoupling.
Table 3-15. Recommended Parameter Values for the Capacitors Models in Figure 3-23
Parameter
Value
C1
2800 µF2
R1
1.2 mΩ
L1
1, 2
600 pH
Comments
Parallel equivalent for ‘north’ capacitors prior to age, thermal,
and manufacturing degradation.
Parallel equivalent for ‘north’ capacitor maximum ESR.
Parallel equivalent for ‘north’ capacitor maximum ESL.
C2
328 µF2
Parallel equivalent for ‘cavity’ capacitors prior to age, thermal,
and manufacturing degradation.
R2
16.7 µΩ2
Parallel equivalent for ‘cavity’ capacitor maximum ESR.
L2
1, 2
29 pH
Parallel equivalent for ‘cavity’ capacitor maximum ESL.
C3
2800 µF2
Parallel equivalent for ‘east’ capacitors prior to DC bias, age,
thermal, and manufacturing degradation.
R3
1.2 mΩ2
Parallel equivalent for ‘east’ capacitor maximum ESR.
L3
1, 2
600 pH
Parallel equivalent for ‘east’ capacitor maximum ESL.
NOTES:
1.
Higher values of ESL may satisfy design requirements.
2.
Contact capacitor vendors to identify values for the specific components used in your
design
Processor Power Delivery Design Guidelines
103
LGA775 Information
Figure 3-24. Schematic Representation of Decoupling Capacitors
N2
RSKT1
LSKT1
RSKT2
LSKT2
RSKT3
LSKT3
N4
N6
RVTT1
I_PWL
LVTT1
RVTT2
LVTT2
RS
Table 3-16 Recommended Parameter Values for the Capacitor Models in Figure 3-23
104
Parameter
Value
Comments
RSKT1
0.38 mΩ
LGA775 ‘north’ segment resistance
RSKT2
1.13 mΩ
LGA775 ‘center’ segment resistance
RSKT3
0.29 mΩ
LGA775 ‘east’ segment resistance
RVTT1
0.42 mΩ
Resistance of VTT Tool load board
RVTT2
0.91 mΩ
Resistance of VTT Tool socket adapter (interposer)
RS
100 kΩ
VTT Tool current source resistance
LSKT1
40 pH
LGA775 ‘north’ segment inductance
LSKT2
120pH
LGA775 ‘center’ segment inductance
LSKT3
30 pH
LGA775 ‘east’ segment inductance
LVTT1
240 pH
Inductance of VTT Tool load board
LVTT2
42 pH
Inductance of VTT Tool socket adapter (interposer)
Processor Power Delivery Design Guidelines
LGA775 Information
Figure 3-25. Current Load Step Profile for I_PWL
Current (A)
Imax
Imin
t0
t1
t2
Time
Table 3-17. I_PWL Current Parameters for Figure 3-25
Parameter
Value
t0
0s
t1
250 µs
t2
t1 + 50 ns
Istep
95 A
Current step for loadline testing1
Imin
30 A
Minimum current for simulation analysis1
Imax
125 A
Maximum current for simulation analysis1
NOTE:
1.
Comments
Simulation ‘time zero’
Time to initiate the current step. This parameter must be
chosen at a time that the VCC rail is residing at steady state.
Time of maximum current1
See Table 3-9. Intel® Processor Current Step Values for Transient Socket loadline
Testing
Processor Power Delivery Design Guidelines
105
LGA775 Information
3.7
LGA775 Voltage Regulator Configuration
Parameters
This section provides the parameter for loadline testing used to characterize the
performance of the voltage regulator for the main board supporting LGA775
processor.
3.7.1
775_VR_CONFIG_04A
Table 3-18. 775_VR_CONFIG_04A Specification Input Parameters
Definition
Variable Name
Value
SKT_LL
1.40 mΩ
Socket Loadline Tolerance Band
TOB
25 mV
Maximum Overshoot Above VID
OS_AMP
50 mV
Maximum Overshoot Time Duration Above VID
OS_TIME
25 us
RIPPLE
10 mV
THERMAL_DRIFT
4 mV
Iccmax
Iccmax
78 A
Dynamic Current Step
I_STEP
55 A
Maximum DC Test Current
I_DC_MAX
23 A
Minimum DC Test Current
I_DC_MIN
5A
Voltage Regulator Thermal Design Current
VR_TDC
68 A
Current step rise time
I_RISE
83 A/µs
Socket Loadline Slope
Peak To Peak Ripple Amplitude
Thermal Compensation Voltage Drift
106
Processor Power Delivery Design Guidelines
LGA775 Information
3.7.2
775_VR_CONFIG_04B
Table 3-19. 775_VR_CONFIG_04B Specification Input Parameters
Definition
Variable Name
Value
SKT_LL
1.00 mΩ
Socket Loadline Tolerance Band
TOB
19 mV
Maximum Overshoot Above VID
OS_AMP
50 mV
Maximum Overshoot Time Duration Above VID
OS_TIME
25 us
RIPPLE
10 mV
THERMAL_DRIFT
4 mV
Iccmax
Iccmax
119 A
Dynamic Current Step
I_STEP
95 A
Maximum DC Test Current
I_DC_MAX
24 A
Minimum DC Test Current
I_DC_MIN
5A
Voltage Regulator Thermal Design Current
VR_TDC
101 A
Current step rise time
I_RISE
83 A/µs
Socket Loadline Slope
Peak To Peak Ripple Amplitude
Thermal Compensation Voltage Drift
3.7.3
775_VR_CONFIG_05A
Table 3-20. 775_VR_CONFIG_05A Specification Input Parameters
Definition
Variable Name
Value
SKT_LL
1.0 mΩ
Socket Loadline Tolerance Band
TOB
19 mV
Maximum Overshoot Above VID
OS_AMP
50 mV
Maximum Overshoot Time Duration Above VID
OS_TIME
25 us
RIPPLE
10 mV
THERMAL_DRIFT
4 mV
Iccmax
Iccmax
100 A
Dynamic Current Step
I_STEP
65 A
Maximum DC Test Current
I_DC_MAX
35 A
Minimum DC Test Current
I_DC_MIN
5A
Voltage Regulator Thermal Design Current
VR_TDC
85 A
Current step rise time
I_RISE
50 ns
Socket Loadline Slope
Peak To Peak Ripple Amplitude
Thermal Compensation Voltage Drift
Processor Power Delivery Design Guidelines
107
LGA775 Information
3.7.4
775_VR_CONFIG_05B
Table 3-21. 775_VR_CONFIG_05B Specification Input Parameters
Definition
Variable Name
Value
SKT_LL
1.00 mΩ
Socket Loadline Tolerance Band
TOB
19 mV
Maximum Overshoot Above VID
OS_AMP
50 mV
Maximum Overshoot Time Duration Above
VID
OS_TIME
25 us
RIPPLE
10 mV
THERMAL_DRIFT
4 mV
Iccmax
Iccmax
125 A
Dynamic Current Step
I_STEP
95 A
Maximum DC Test Current
I_DC_MAX
30 A
Minimum DC Test Current
I_DC_MIN
5A
Voltage Regulator Thermal Design Current
VR_TDC
115 A
Current step rise time
I_RISE
50 ns
Socket Loadline Slope
Peak To Peak Ripple Amplitude
Thermal Compensation Voltage Drift
3.7.5
775_VR_CONFIG_06
Table 3-22. 775_VR_CONFIG_06 Specification Input Parameters
Definition
Variable Name
Value
SKT_LL
1.00 mΩ
Socket Loadline Tolerance Band
TOB
19 mV
Maximum Overshoot Above VID
OS_AMP
50 mV
Maximum Overshoot Time Duration Above VID
OS_TIME
25 us
RIPPLE
10 mV
THERMAL_DRIFT
4 mV
Iccmax
Iccmax
75 A
Dynamic Current Step
I_STEP
50 A
Maximum DC Test Current
I_DC_MAX
25 A
Minimum DC Test Current
I_DC_MIN
5A
Voltage Regulator Thermal Design Current
VR_TDC
60 A
Current step rise time
I_RISE
50 ns
Socket Loadline Slope
Peak To Peak Ripple Amplitude
Thermal Compensation Voltage Drift
§
108
Processor Power Delivery Design Guidelines
LGA1156 Information
4
LGA1156 Information
4.1
Introduction
This chapter focuses on information unique to platforms designed with the LGA1156.
4.1.1
Applications
LGA1156 designs will use the VCC and VSS sense points to determine the loadline. The
loadline at these points will be 1.4 mOhm.
4.2
Processor VCC Requirements
4.2.1
Loadline Definitions (REQUIRED)
To maintain processor reliability and performance, platform DC voltage regulation and
transient-droop noise levels must always be contained within the Vccmin and Vccmax
loadline boundaries (known as the loadline window). Loadline compliance must be
ensured across component manufacturing tolerances, thermal variation, and age
degradation. Loadline boundaries are defined by the following equations in conjunction
with the VCC regulator design parameter values defined in Table 4-2. In these
equations, VID, RLL, and TOB are known. Plotting VCC while varying ICC from 0 A to
Iccmax establishes the Vccmax and Vccmin loadlines. Vccmax establishes the
maximum DC loadline boundary. Vccmin establishes the minimum AC and DC voltage
boundary. Short transient bursts above the Vccmax loadline are permitted; this
condition is defined in Section 1.3.7.
Table 4-1. Loadline Equations
Loadline
Equation
Equation 11: Vccmax Loadline
VCC = VID – (RLL* ICC)
Equation 12: Vcctyp Loadline
VCC = VID – TOB - (RLL* ICC)
Equation 13: Vccmin loadline
VCC = VID – 2*TOB - (RLL* ICC)
Loadline recommendations are established to provide guidance for satisfying
processor loadline specifications, which are defined in processor datasheets. Loadline
requirements must be satisfied at all times and may require adjustment in the loadline
value. The processor loadlines are defined in the applicable processor datasheet.
Processor Power Delivery Design Guidelines
109
LGA1156 Information
Table 4-2. VCC Regulator Design Parameters
VR Configuration
Iccmax
VR TDC
Dynamic ICC
RLL
TOB
Maximum VID
1156_VR_CONF_09A
75 A
60 A
50 A
1.4 mΩ
± 19 mV
TBD V
1156_VR_CONF_09B
110A
90 A
75 A
1.4 mΩ
± 19 mV
TBD V
Table 4-2 provides a list of VRD11.1 LGA1156 voltage regulator design configurations.
The configurations to be adopted by VRD hardware will depend on the specific
processors the design is intended to support. It is common for a motherboard to
support processors that require different VR configurations. In this case, the VCC
regulator design must meet the specifications of all processors supported by that
board.
The following tables and figures show minimum and maximum voltage boundaries for
each loadline design configuration defined in Table 4-2. VCCTYP loadlines are provided
for design reference; designs should calibrate the loadline to this case (centered in the
loadline window, at the mean of the tolerance band). Different processors discussed in
this design guide can be shipped with different VID values. The reader should not
assume that processors with similar characteristics will have the same VID value. A
single loadline chart and figure for each VRD design configuration can represent
functionality for each possible VID value. Tables and figures presented as voltage
deviation from VID provide the necessary information to identify voltage requirements
at any reference VID. This avoids the redundancy of publishing tables and figures for
each of the multiple cases.
4.2.1.1
Loadline Definition for 1156_VR_CONFIG_09B
Figure 4-1. Loadline Window for 1156_VR_CONFIG_09B
Deviation from Zero Current Setpoint (V)
0
10
20
30
40
50
60
70
80
90
100
110
120
0.0000
-0.0200
-0.0400
-0.0600
-0.0800
-0.1000
-0.1200
-0.1400
-0.1600
-0.1800
-0.2000
-0.2200
Icc (A)
Vtyp Loadline
Vmax
VMin
NOTES:
1.
Presented as a deviation from VID
2.
Loadline Slope = 1.4 mΩ, TOB = ±19 mV
3.
Consult Table 4-2 for VR configuration parameter details
110
Processor Power Delivery Design Guidelines
LGA1156 Information
Table 4-3. Loadline Window for 1156_VR_CONFIG_09B
ICC
Maximum (V)
Typical (V)
Minimum (V)
0A
0.0000
-0.0190
-0.0380
10 A
-0.0140
-0.0330
-0.0520
20 A
-0.0280
-0.0470
-0.0660
30 A
-0.0420
-0.0610
-0.0800
40 A
-0.0560
-0.0750
-0.0940
50 A
-0.0700
-0.0890
-0.1080
60 A
-0.0840
-0.1030
-0.1220
70 A
-0.0980
-0.1170
-0.1360
80 A
-0.1120
-0.1310
-0.1500
90 A
-0.1260
-0.1450
-0.1640
100 A
-0.1400
-0.1590
-0.1780
110 A
-0.1540
-0.1730
-0.1920
120 A
-0.1680
-0.1870
-0.2060
NOTES:
1.
Presented as a deviation from VID
2.
Loadline Slope = 1.4 mΩ, TOB = ±19 mV
3.
Consult Table 4-2 for VR configuration parameter details
VRD layout studies indicate that the phases are best located north of the processor
with the controller to the northeast.
Table 4-4. Loadline Reference Lands for the LGA1156 Socket
Name
Land
VCC_SENSE
T35
VSS_SENSE
T34
To properly calibrate the loadline parameter, the VR designer must excite the
processor socket with a current step that generates a voltage droop, which must be
checked against the loadline window requirements. Table 4-5 identifies the steady
state and transient current values to use for this calibration.
Table 4-5. Intel® Processor Current Step Values for Transient Loadline Testing
ICC Rise
Time
Starting
Current
Ending
Current
Dynamic
Current
Step
1156_VR_CONF_09A
25 A
75 A
50 A
100 ns
1
100 ns
1
1156_VR_CONF_09B
45 A
110A
75 A
100 ns
1
100 ns
1
VR Configuration
ICC Fall
Time
NOTES:
1.
ICC Rise and Fall times are subject to change pending validation
Processor Power Delivery Design Guidelines
111
LGA1156 Information
4.2.1.2
Time Domain Validation
To ensure processor reliability and performance, platform transient-droop and
overshoot noise levels must always be contained within the Vccmin and Vccmax
loadline boundaries (known as the loadline window). The load generates a voltage
droop, or overshoot, which must be checked against the loadline window
requirements. The current step must have a fast enough slew rate to excite the
impedance across the frequency range of the VR. In addition, the VR needs to be
tested at different load frequencies and load steps to prevent any non-linear,
resonant, or beating effects that could cause functional issues or loadline violations.
Intel recommends sweeping the load frequency from DC to 1 MHz, using two different
load steps.
Intel recommends testing using different VID levels for each of the supported VR
configurations. In particular the highest and lowest VIDs should be checked. The VID
ranges for each processor is available in the processor datasheet.
4.2.1.3
Platform Impedance Measurement and Analysis (Expected)
In addition to the tuning of the loadline with Vdroop testing and DC loadline testing,
the decoupling capacitor selection needs to be analyzed to make sure the impedance
of the decoupling is below the loadline target up to the frequency Fbreak as defined in
Figure 4-2. This analysis can be done with impedance testing or through power
delivery simulation if the designer can extract the parasitic resistance and inductance
of the power planes on the motherboard and they have good models for the
decoupling capacitors.
Measured power delivery impedance should be with in the tolerance band shown in
Figure 4-2. For Loadline compliance, time domain validation is required and the VR
tolerance band must be met at all times. Above 500 kHz, the minimum impedance
tolerance is not defined and is determined by the MLCC capacitors required to get the
ESL low enough to meet the loadline impedance target at the Fbreak frequency. At 1
MHz, the Zmax tolerance drops to the loadline target impedance. Any resonance
points that are above the Zmax line need to be carefully evaluated with time domain
method defined in Section 4.2.1.2 by applying transient loads at that frequency and
looking for Vmin violations. Maintaining the impedance profile up to Fbreak is important
to ensure the package level decoupling properly matches the motherboard impedance.
After Fbreak, the impedance measurement is permitted to rise at a inductive slope. The
motherboard VR designer does not need to design for frequencies over Fbreak as the
processor package decoupling takes over in the region above Fbreak.
112
Processor Power Delivery Design Guidelines
LGA1156 Information
Figure 4-2. Power Distribution Impedance versus Frequency
Ω
Zone 2
Output Filter
Bulk & MLCC
Zone 1
PWM Droop control
& compensation
bandwidth
ZLL Max
Zone 3
Inductive effects
MLCC ESL +
Socket
Z target = ZLL
ZLL Min
Hz
VR BW
Fbreak
500 kHz
1 MHz
NOTES:
1.
See Table 4-6. Impedance Measurement Parameters definitions
2.
Zone 1 is defined by the VR closed loop compensation bandwidth (VR BW) of the
voltage regulator. Typically 30-40 kHz for a 300 kHz voltage regulator design.
3.
Zones 2 and 3 are defined by the output filter capacitors and interconnect parasitic
resistance and inductance. The tolerance is relaxed over 500 kHz allowing the VR
designer freedom to select output filter capacitors. The goal is to keep Z(f) below ZLL
up to Fbreak and as flat as practical, by selection of bulk capacitor values and type and
number of MLCC capacitors. The ideal impedance would be between ZLL and ZLL Min
but this may not be achieved with standard decoupling capacitors.
Table 4-6. Impedance Measurement Parameters
Parameter
Value
ZLL
1.4 mΩ
LGA1156 Desktop LL target
ZLL max
1.6 mΩ
Based on VR11.1 PWM tolerance band
ZLL min
1.2 mΩ
Based on VR11.1 PWM tolerance band
Fbreak
2.0 MHz
Processor Power Delivery Design Guidelines
Notes
-
113
LGA1156 Information
4.3
LGA 1156 Specific Signals
4.3.1
Power-on Configuration (POC) Signals on VID
(REQUIRED)
All 8 VID lines will serve a second function: the Power On Configuration (POC) logic
levels are multiplexed onto the VID lines with 1 kΩ pull-ups and pull-downs and they
will be read by the processor during the time — as shown in Section 1.4, Power
Sequencing (REQUIRED). The POC configuration programs the processor as to the
platform VR capabilities. The VR does not read POC configuration resistors. After
OUTEN is asserted the processor VID CMOS drivers override the POC pull-up, and pulldown resistors. See the Power Sequencing section for more information.
The POC bits (multiplexed with 8 VID lines) are allocated is as follows:
• POC/(VID)[2:0] = MSID (Market Segment ID) bits, refer to the datasheet.
• POC/(VID)[5:3] = Current Sense Config bits, Iout gain setting.
• POC/(VID)[6] = RESERVED (pull-down resistors installed, unless stated otherwise
in the datasheet).
• POC/(VID)[7] = VR11.1 Select signal, with pull-down resistor installed for VR11.1,
refer to the datasheet.
4.4
MB Power Plane Layout (REQUIRED)
The motherboard layer stack-up must be designed to ensure robust, noise-free power
delivery to the processor. Failure to minimize and balance power plane resistance may
result in non-compliance to the die loadline specification. A poorly planned stack-up or
excessive holes in the power planes may increase system inductance and generate
oscillation on the VCC voltage rail at the processor. Both of these types of design
errors can lead to processor failure and must be avoided by careful VCC and VSS plane
layout and stack-up. The types of noise introduced by these errors may not be
immediately observed on the processor power lands or during system-board voltage
transient validation, so issues must be resolved by design, prior to layout, to avoid
unexpected failures.
Following basic layout rules can help avoid excessive power plane noise. Copper
shapes that encompass the power delivery region of the processor land field are
required. A careful motherboard design will help ensure a well-functioning system that
minimizes the noise profile at the processor die. The following subsections provide
further guidance.
4.4.1
Minimize Power Path DC Resistance
Power path resistance can be minimized by ensuring that the copper layout area is
balanced between VCC and VSS planes. A good four-layer board design will have two
VCC layers and two VSS layers. Because there is generally more VSS copper in the
motherboard stack-up, care should be taken to maximize the copper in VCC floods.
This includes care to minimize unnecessary plane splits and holes when locating
through hole components, vias, and connection pads. Refer to Table 4-7 for more
details on the reference board layer stack up.
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4.4.2
Minimize Power Delivery Inductance
At higher frequencies the ordering of the motherboard layers becomes critical as it is
VCC/ VSS plane pairs, which carry current and determine power plane inductance. The
layer stack-up should maximize adjacent (layer-to-layer) planes at a minimized
spacing to achieve the smallest possible inductance. Care must be taken to minimize
unnecessary plane splits and holes when locating through-hole components, vias, and
connection pads. Minimized inductance will ensure that the board does not develop
low frequency noise which may cause the processor to fail (loadline violation).
4.4.3
Four-Layer Boards
A well-designed four-layer board will feature generous VCC shapes on the outer layers
and large VSS shapes on the inner layers. The VSS -reference requirements for the
front side bus are best accommodated with this layer ordering. The power plane area
should be maximized and cut-out areas should be carefully placed to minimize
parasitic resistance and inductance. Examples power plane layout of the Intel
reference board are provided in Table 4-7 and Figure 4-3 through Figure 4-7.
Figure 4-3. Reference Board Layer Stack-up
L1 Solder mask
Layer L1: Plated 1/2 oz Copper
L1-2 FR4
Layer L2: Unplated 1 oz Copper
CORE
Layer L3: Unplated 1 oz Copper
L3-4 FR4
Layer L4: Plated 1/2 oz Copper
L4 Solder mask
NOTE:
Drawing is not to scale
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Table 4-7. Reference Board Layer Thickness (Prepreg 1080)
Layer
Minimum
Typical
Maximum
L1 Solder mask
0.2 mils
0.7 mils
1.2 mils
L1
1.1 mils
1.9 mils
2.7 mils
L1-2 FR4
2.0 mils
2.7 mils
3.5 mils
L2
1.0 mils
1.2 mils
1.4 mils
Core
45 mils
50 mils
55 mils
L3
1.0 mils
1.2 mils
1.4 mils
L3-4 FR4
2.0 mils
2.7 mils
3.5 mils
L4
1.1 mils
1.9 mils
2.7 mils
L4 Solder mask
0.2 mils
0.7 mils
1.2 mils
NOTES:
1.
Consult Figure 4-3 for layer definition.
2.
Impedance Target: 50 Ω ± 15%; based on nominal 4 mil trace.
3.
Overall board thickness is 62 mils +8, -5 mils.
Figure 4-4. Layer 1 VCC Shape for Intel® Reference Four-layer Motherboard
V_Axg
Vcc
Vtt
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Figure 4-5. Layer 2 VSS Routing for Intel® Reference Four-layer Motherboard
Figure 4-6. Layer 3 VSS Routing for Intel® Reference Four-layer Motherboard
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Figure 4-7. Layer 4 VCC Shape for Intel® Reference Four-layer Motherboard
V_Axg
Vcc
Vtt
4.4.4
Six-layer Boards
Six-layer boards provide layout engineers with greater design flexibility compared to
the four-layer standard. Adjacent plane pairs of the same potential are not useful at
higher frequencies, so the best approach is to maximize adjacent, closely spaced VCC/
VSS plane pairs. The plane pair separated by the PCB core material is of lesser
importance since it is generally an order of magnitude larger in spacing than other
plane pairs in the stack-up. Because the VSS planes are typically full floods of copper,
an example of a well-designed six-layer stack-up will have 4 VCC layers and two layers
for VSS. The DC resistive requirements (Section 4.4.1) of the power delivery loop can
still be met because the VSS floods are larger than the VCC floods, and the higher
frequency needs are considered as there are 4 VCC/ VSS plane pairs to deliver current
and reduce inductance.
4.4.5
Resonance Suppression
VCC power delivery designs can be susceptible to resonance phenomena capable of
creating droop amplitudes in violation of loadline specifications. This is due to the
interleaved levels of inductively-separated decoupling capacitance. Furthermore, these
resonances may not be detected through standard validation and require engineering
analysis to identify and resolve. If not identified and corrected in the design process,
these resonant phenomena may yield droop amplitudes in violation of loadline
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specifications by superimposing with standard VRD droop behavior. Frequencydependent power delivery network impedance simulations and validation are strongly
recommended to identify and resolve power delivery resonances before board are
actually built. Careful modeling and validation can help to avoid voltage violations
responsible for data corruption, system lock-up, or system ‘blue-screening’.
4.5
Electrical Simulation (EXPECTED)
The following electrical models are enclosed to assist with VRD design analysis and
component evaluation for loadline compliance. The block diagram shown in Figure 4-8
is a simplified representation of the VCC power delivery network of the Intel four-layer
reference board. The board model, detailed in Figure 4-11, characterizes the power
plane layout. The multiphase buck regulator and capacitor models should be obtained
from each selected vendor. When fully integrated into electrical simulation software,
this model can be used to evaluate PWM controller, capacitor, and inductor
performance against the loadline and tolerance band requirements detailed in
Section 4.2.1. To obtain accurate results, it is strongly recommended to create and
use a custom model that represents the specific board design, PWM controller, and
passive components that are under evaluation.
Figure 4-8. Simplified Reference Block Diagram
Multi-Phase Buck
Regulator
North Phase Inductors
Output:
North
Phases
East Phase Inductors
Output:
East
Phases
Error Amplifier input
Motherboard
Socket
Sense
North
East
SKT
SKT
MLCC
NOTE:
C1
C2
C3
North
Bulk
Caps
East
Bulk
Caps
High
Frequency
Filtering
Caps
Consult Figure 4-4 to Figure 4-7 for reference layout.
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The motherboard model of Figure 4-11 represents the power delivery path of the Intel
reference four-layer motherboard design. Input and output node locations are
identified in Figure 4-12. Feedback to the PWM controller error amplifier should be
tied to node ‘Sense’, the socket-motherboard interface. Nodes ‘North’ and ‘East’ are
the locations where the output inductors of the buck regulator tie to the motherboard
power plane. ‘North’ bulk capacitors, C1, are also connected to node ‘North’. C1
represents the parallel combination of all capacitors and capacitor parasitics at this
location. Node ‘East’ is the location where the ‘east’ bulk capacitors, C2, connect to
the motherboard power plane. C2 represents the parallel combination of all capacitors
and capacitor parasitics at this location. Node ‘MLCC’ represents the parallel
combination of all capacitors and capacitor parasitics in the socket cavity and is
connected to the mid-frequency filter, C3.
Typical capacitor models are identified in Figure 4-13. Each model represents the
parallel combination of the local capacitor placement as identified in the previous
paragraph. Recommended parallel values of each parameter are identified in
Figure 4-11. Consult Section 1.1 for further details regarding bulk and mid-frequency
capacitor selection.
The LGA1156 socket is characterized by two impedance paths that connect to the
motherboard at ‘North’ (‘north’ connection), and ‘East’ (‘east’ connection). I_PWL is a
piece-wise linear current step that is used to stimulate the voltage droop as seen at
the motherboard-socket interface and is defined in Figure 4-15 and Table 4-11. This
load step approximates the low frequency current spectrum that is necessary to
evaluate bulk capacitor, mid-frequency capacitor and PWM controller performance. It
does not provide high frequency content to excite package noise. The cavity capacitor
solution, MLCC, is used as a reference for designing processor packaging material and
should not be modified except to reduce ESR/ESL or increase total capacitance.
Failure to observe this recommendation may make the motherboard incompatible with
some processor designs.
The primary purpose of the simulation model is to identify options in supporting the
loadline specification. Evaluation of the full power-path model will allow the designer
to perform what-if analysis to determine the cost optimal capacitor and PWM
controller configuration. This is especially useful in determining the capacitor
configuration that can support loadline specifications across variation such as
manufacturing tolerance, age degradation, and thermal drift. The designer is
encouraged to evaluate different capacitor configurations and PWM controller designs.
However, the designer should be aware that the feedback compensation network of
most PWM controllers requires modification when the capacitor solution changes.
Consult the PWM controller datasheet for further information.
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Figure 4-9. Example Voltage Droop Observed At Node ‘Sense’
Figure 4-9 provides an example voltage droop waveform at node ‘Sense’, the socketmotherboard interface. The loadline value is defined as ∆V/∆I with ∆V measured at
this node and the current step observed through I_PWL. The voltage amplitude is
defined as the difference in the steady state voltage (prior to the transient) and the
minimum voltage droop (consult Figure 4-9). Care must be taken to remove all ripple
content in this measurement to avoid a pessimistic loadline calculation that will
require additional capacitors (cost) to correct. Figure 4-10 provides an example
current stimulus. The amplitude is measured as the difference in maximum current
and steady state current prior to initiation of the current step. With ∆V and ∆I known,
the loadline slope is simply calculated using Ohm’s Law: RLL = ∆V/∆I.
Figure 4-10. Current Step Observed Through I_PWL
NOTE:
To avoid excessive ringing in simulation, the system current should be slowly ramped
from zero amps to the minimum recommended DC value prior to initiating the current
step.
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Figure 4-11. Schematic Diagram for the Four-layer Intel® Reference Motherboard
North
RMB1
0.48m
East
RMB2
0.7m
LMB1
80p
SKT
LMB2
135p
RMB3
0.3m
LMB3
61p
MLCC
NOTE:
Consult Figure 4-4 to Figure 4-7 for reference layout.
Table 4-8. Parameter Values for the Schematic of Figure 4-11
122
Parameter
Value
Comments
RMB1
0.48 mΩ
‘North’ power plane parasitic resistance from the buck regulator
north output inductors to the LGA1156 socket connection.
RMB2
0.7 mΩ
Power plane parasitic resistance from ‘east’ power plane from
the buck regulator east output inductor to the LGA1156 socket
connection.
RMB3
0.3 mΩ
Power plane parasitic resistance from the LGA1156 socket
cavity to the LGA1156 socket connection.
LMB1
80 pH
LMB2
135 pH
LMB3
61 pH
‘North’ power plane parasitic inductance from the buck
regulator north output inductors to the LGA1156 socket
connection.
Power plane parasitic inductance from ‘east’ power plane from
the buck regulator east output inductor to the LGA1156 socket
connection.
Power plane parasitic inductance from the LGA1156 socket
cavity to the LGA1156 socket connection.
Processor Power Delivery Design Guidelines
LGA1156 Information
Figure 4-12. Node Location for the Schematic of Figure 4-11
Figure 4-13. Schematic Representation of Mid-frequency Decoupling Capacitors
North
C1
East
MLCC
C2
C3
R1
R2
R3
L1
L2
L3
NOTES:
1.
C1 represents the parallel model for ‘north’ location bulk decoupling.
2.
C2 represents the parallel model for ‘east’ location bulk decoupling.
3.
C3 represents the parallel model for mid-frequency decoupling located in the northeast
corner of the socket cavity.
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Table 4-9. Recommended Parameter Values for the Capacitors Models
Parameter
Value
Comments
C1
2240 µF2
Parallel equivalent for ‘north’ capacitors prior to age, thermal,
and manufacturing degradation.
R1
1.75 mΩ2
Parallel equivalent for ‘north’ capacitor maximum ESR.
L1
1, 2
500 pH
Parallel equivalent for ‘north’ capacitor maximum ESL.
C2
1680 µF2
Parallel equivalent for ‘east’ capacitors prior to DC bias, age,
thermal, and manufacturing degradation.
R2
2.33 mΩ2
Parallel equivalent for ‘east’ capacitor maximum ESR.
L2
1, 2
667 pH
Parallel equivalent for ‘east’ capacitor maximum ESL.
C3
243.1 µF2
Parallel equivalent for ‘cavity’ capacitors prior to age, thermal,
and manufacturing degradation.
R3
294 µΩ2
Parallel equivalent for ‘cavity’ capacitor maximum ESR.
L3
32 pH1, 2
Parallel equivalent for ‘cavity’ capacitor maximum ESL.
NOTES:
1.
Higher values of ESL may satisfy design requirements.
2.
Contact capacitor vendors to identify values for the specific components used in your
design.
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Figure 4-14. Schematic Representation of VR Test Tool Model
LSKT
SKT
RSKT
Sense
LVTT1
RVTT1
LVTT2
RVTT2
RS
I_PWL
Table 4-10. Recommended Parameter Values for the Socket Model in Figure 4-14
Parameter
Value
Comments
RSKT
0.42 mΩ
LGA1156 ‘south’ segment resistance
RVTT1
0.42 mΩ
Resistance of VTT Tool load board
RVTT2
0.91 mΩ
Resistance of VTT Tool socket adapter (interposer)
RS
100 kΩ
LSKT
40 pH
LVTT1
240 pH
LVTT2
42 pH
VTT Tool current source resistance
LGA1156 ‘north’ segment inductance
Inductance of VTT Tool load board
Inductance of VTT Tool socket adapter (interposer)
NOTES: These values are from the LGA 775 VTT Tool load board. The values will be updated
with values from the LGA 1156 VTT Tool load board when they become available.
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LGA1156 Information
Figure 4-15. Current Load Step Profile for I_PWL
Icc
IMAX
IMIN
t0
t1
t2
Time
Table 4-11. I_PWL Current Parameters for Figure 4-15
Parameter
Value
t0
0s
t1
100 µs
t2
t1 + 50 ns
Istep
75 A
Current step for loadline testing1
Imin
45 A
Minimum current for simulation analysis1
Imax
120 A
Maximum current for simulation analysis1
NOTE:
1.
126
Comments
Simulation ‘time zero’
Time to initiate the current step. This parameter must be
chosen at a time that the VCC rail is residing at steady state.
Time of maximum current1
See Table 4-5. Intel® Processor Current Step Values for Transient Loadline Testing
Processor Power Delivery Design Guidelines
LGA1156 Information
4.6
LGA1156 Voltage Regulator Configuration
Parameters
Table 4-12. 1156_VR_CONFIG_09A Specification Input Parameters
Definition
Variable Name
Value
LL_SLOPE
1.4 mΩ
TOB
19 mV
Maximum Overshoot Above VID
OS_AMP
50 mV
Maximum Overshoot Time Duration Above
VID
OS_TIME
25 us
RIPPLE
10 mV
THERMAL_DRIFT
2 mV
Iccmax
Iccmax
75 A
Dynamic Current Step
I_STEP
50 A
Voltage Regulator Thermal Design Current
VR_TDC
60 A
Current step rise time
I_RISE
100 ns
Current step fall time for overshoot
I_FALL
100 ns
Loadline Slope
Loadline Tolerance Band
Peak To Peak Ripple Amplitude
Thermal Compensation Voltage Drift
Table 4-13. 1156_VR_CONFIG_09B Specification Input Parameters
Definition
Variable Name
Value
LL_SLOPE
1.4 mΩ
TOB
19 mV
Maximum Overshoot Above VID
OS_AMP
50 mV
Maximum Overshoot Time Duration Above
VID
OS_TIME
25 us
RIPPLE
10 mV
THERMAL_DRIFT
2 mV
Iccmax
Iccmax
110A
Dynamic Current Step
I_STEP
75 A
Voltage Regulator Thermal Design Current
VR_TDC
90 A
Current step rise time
I_RISE
100 ns
Current step fall time for overshoot
I_FALL
100 ns
Loadline Slope
Loadline Tolerance Band
Peak To Peak Ripple Amplitude
Thermal Compensation Voltage Drift
§
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Z(f) Impedance References
Appendix A Z(f) Impedance
References
"Microprocessor Platform Impedance Characterization using VTT tools” by S
Chickamenahalli, K. Aygün, M.J. Hill, K. Radhakrishnan, K. Eilert, E. Stanford in the
proceedings of the 20th Annual IEEE Applied Power Electronics Conference and
Exposition, Vol. 3. pp. 1466-1469, March 2005.
§
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Z(f) Impedance References
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Audible Noise Reduction
Appendix B Audible Noise Reduction
Audible noise frequency (pitch) is the fundamental plus several harmonics of the
stimulus frequency. Presence of multiple harmonics, both odd and even, results in
complex and very annoying noise characteristics. Audible noise amplitude (loudness)
increases with larger VR output voltage change [dv] and faster output voltage change
ramp Rate [dv/dt].
Simple math: I = C * dv / dt. Three conditions that need to be present simultaneously
for acoustic noise. They are periodic dv/dt in audible range, large dv, and MLCC
capacitors.
On the MCH, the processors have the C4 state enabled with VID changes up to 250 mV
in one step when it enters/exits C4. These changes could be periodical at 1 KHz during
an idle state. The minimum slew rate dv/dt requirement is 7.6mV/uS. Most designs would
need a faster dv/dt for meeting latency requirement of 33 uS. At this fast slew rate and
periodical entry/exit, the VR could potentially create audible noise which may be detected
by end user in normal operation. There are steps that need to be taken for suppressing
the audible noise.
The primary cause is from large inrush current due to high output capacitance. The first
step is controlling the output capacitance by sizing output capacitor just enough to meet
the transient requirement. A VR controller that has slew rate control with external pin is
preferred for optimizing the dv/dt setting. Consult the controller datasheet or vendor FAE
on how to program dv/dt. If the slew rate is not set properly, Vccp can slew faster than
needed thus worsening the audible noise.
The second step is careful selection of output inductors to prevent inductor buzzing noise.
The supplier can provide characterization noise given material selection and construction.
In general, ferrite is noisier than metal composite. Make sure the inductor construction is
rigid. The core has to be glued well together and cavity should be filled with epoxy.
Last but not least is MLCC, which is well known for making audible noise when exposed
to large dv/dt. This is called the Piezo effect. The noise magnitude is proportional to
number of MLCC in parallel. The input filter MLCCs should be (2) 4.7 uF X5R per phase.
Avoid Y5V type since it is much more susceptible to Piezo effect. Place them on both
sides of the input FET, not side by side. Increase the capacitance to 10uF if needed for
minimizes the noise. The input bulk capacitors should be (2) 680 uF or larger for reducing
dv/dt of the rail. For output high frequency decoupling, use 22 uF MLCC or bigger value
to reduced number of needed capacitors. Use polymer chip capacitor in conjunction with
MLCC when possible. Placing MLCC symmetrically on top and bottom side of the
motherboard cancels out the vibration; thus, helping the noise.
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Audible Noise Reduction
Figure 4-16. Effect of Output Change on Input Currents
CIN
V_DC
NMOS
DRIVER
Output Vcc
TG
Lout
NMOS
BG
+
CO
Cout
RLoad
SCHOTTKY
Regulator
Controller
Feed back
Figure 4-17. Input Voltage Drop Caused by di/dt Event at the Output
VCC_CORE
Vin
§
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