AN 325: Interfacing RLDRAM II with Stratix II, Stratix Stratix GX Devices

AN 325: Interfacing RLDRAM II with Stratix II, Stratix Stratix GX Devices
Interfacing RLDRAM II with
Stratix II, Stratix,&
Stratix GX Devices
Application Note 325
November 2005, ver. 3.1
Introduction
Reduced latency DRAM II (RLDRAM II) is a DRAM-based point-to-point
memory device designed for communications, imaging, and server
systems requiring high density, high memory bandwidth, and low
latency. The fast random access speeds in RLDRAM II devices make them
a viable alternative to SRAM devices at a lower cost.
There are two types of RLDRAM II devices: common I/O (CIO) and
separate I/O (SIO). CIO devices share a single data I/O bus which is
similar to the double data rate (DDR) SDRAM interface. SIO devices, with
separate data read and write buses, have an interface similar to SRAM.
Compared to DDR SDRAM, RLDRAM II has simpler bank management
and lower latency inside the memory. RLDRAM II devices are divided
into eight banks instead of the typical four banks in most memory
devices, providing a more efficient data flow within the device.
RLDRAM II offers up to 2.4 Gigabytes per second (Gbps) aggregate
bandwidth.
Stratix® II devices in the -3 speed grade support RLDRAM II at up to
300 MHz and 600 Megabits per second (Mbps). Stratix and Stratix GX
devices in the -5 speed grade in the flip-chip package (except EP1S60 and
EP1S80 devices) support RLDRAM II at up to 200 MHz and 400 Mbps.
Table 1 shows the RLDRAM II support in Stratix II devices.
Table 1. RLDRAM II Maximum Clock Rate Support in Stratix II Devices Notes (1),(2), (3)
Speed Grade
DLL-Based Implementation
PLL-Based Implementation
-3
300 MHz
200 MHz
-4
250 MHz (4)
175 MHz (5)
-5
200 MHz
175 MHz (5)
Notes to Table 1:
(1)
This analysis is based on the EP2S60F1020. Ensure you perform a timing analysis for your chosen FPGA.
(2)
These numbers are from Quartus® II software, version 5.1. Altera recommends using the latest version of the
Quartus II software for your design.
These numbers apply to both commercial and industrial devices.
Although there are no 250-MHz RLDRAM II devices, you can underclock 300-MHz RLDRAM II devices at
250 MHz.
This is the lowest frequency a RLDRAM II device can operate.
(3)
(4)
(5)
Altera Corporation
AN-325-3.1
1
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Table 2 shows the Stratix EP1S10 through EP1S40 devices, and Stratix GX
EP1SGX10 through EP1SGX40 devices.
Table 2. RLDRAM II Maximum Clock Frequency Support in EP1S10 through
EP1S40 & EP1SGX10 through EP1SGX40 Devices Note (1)
Speed Grade
DLL-Based Implementation (2)
-5
200 MHz(3)
-6
N/A (4)
-7
N/A (4)
Notes to Table 2:
(1)
(2)
(3)
(4)
Stratix EP1S60 and EP1S80 do not support RLDRAM II.
Stratix devices do not offer PLL-based implementation RLDRAM II interfaces.
This frequency is only supported in flip-chip packages and is based on read
capture and write timing analysis. You have to perform your own
resynchronization timing analysis.
RLDRAM II memory is not supported in this speed grade.
This application note describes an example RLDRAM II interface with
Stratix II, Stratix, and Stratix GX devices. It discusses the electrical and
timing analysis for the interface and also describes the Altera Stratix
series memory board and lists the general board guidelines when
interfacing RLDRAM II memory with a Stratix-series device. In general,
this application note is applicable for both RLDRAM II CIO and SIO
devices.
This application note focuses on the timing analysis that you need to
create a successful interface. In order to do so, you need to use the Altera
recommended data path, available from the RLDRAM II Controller
MegaCore® function from the Quartus II MegaCore Intellectual Property
(IP) Library CD. After compiling the controller and ensuring that the
design meets the targeted core fmax, you need to perform the following
timing analysis: read capture, write capture, command and address, bus
turnaround, and round trip delay (for RLDRAM II interfaces in Stratix
devices).
f
RLDRAM II
Overview
2
Use this application note together with the External Memory Interfaces
chapter of the Stratix II Device Handbook or Stratix Device Handbook.
RLDRAM II uses a DDR scheme, performing two data transfers per clock
cycle. RLDRAM II CIO devices use the bidirectional data pins (DQ) for
both read and write data, while RLDRAM II SIO devices use D pins for
write data (input to the memory) and Q pins for read data (output from
the memory). Both types use two pairs of uni-directional free-running
Altera Corporation
RLDRAM II Overview
clocks. The memory uses DK and DK# pins during write operations, and
generates QK and QK# pins during read operations. In addition,
RLDRAM II uses the system clocks (CK and CK# pins) to sample
commands and addresses and generate the QK and QK# read clocks.
Address ports are shared for write and read operations.
The RLDRAM II SIO devices are available in ×9 and ×18 data bus width
configurations, while the RLDRAM II CIO devices are available in ×9,
×18, and ×36 data bus width configurations. RLDRAM II CIO devices
require an extra cycle for bus turnaround time for switching read and
write operations.
Write and read operations are burst oriented and all the data bus width
configurations of RLDRAM II support burst lengths of two and four. In
addition, RLDRAM II devices with data bus width configurations of ×9
and ×18 also support burst length of eight.
The read latency is the time between when the read command is clocked
into the memory and the time data is presented at the memory pins. There
is a similar latency for write operations called the write latency. The write
latency is equal to the read latency plus one clock cycle. The RLDRAM
devices have up to three programmable configuration settings that
determine the row cycle times, read latency, and write latency of the
interface at a given frequency of operation.
RLDRAM II devices use either the 1.5-V HSTL or 1.8-V HSTL I/O
standard. Altera recommends the 1.8-V HSTL I/O standard for
maximum performance. Each RLDRAM II device is divided into eight
banks, where each bank has a fixed number of rows and columns. Only
one row per bank is accessed at a time. The memory (instead of the
controller) controls the opening and closing of a row, which is similar to
an SRAM interface.
RLDRAM II also offers programmable impedance output buffers and ondie termination. The programmable impedance output buffers are for
impedance matching and are guaranteed to produce 25- to 60-Ω output
impedance. The on-die termination is dynamically switched on during
read operations and switched off during write operations. Since Stratix II,
Stratix, and Stratix GX devices do not offer a similar dynamic on-die
termination, perform an IBIS simulation to observe the effects of this
dynamic termination on your system. IBIS simulation can also show the
effects of different drive strengths, termination resistors, and capacitive
loads on your system.
f
Altera Corporation
For more information on the RLDRAM II specifications, go to
www.rldram.com.
3
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Interface
Description
This section provides a detailed description of the interface between the
FPGA and the RLDRAM II devices. It describes the interface signals and
how Altera FPGA pins should be configured to meet the strict
RLDRAM II electrical and timing requirements, listing the number of
possible interfaces based on the number of DQS and DQ pins available in
the FPGA. In addition, this section also describes the architecture of the
interface between the FPGA and the RLDRAM II memory.
Understanding how complicated the interface can be, Altera offers a
complete solution that will create the memory controller within minutes.
The Altera RLDRAM II controller MegaCore function allows you to use
the Altera recommended data path whether or not you are using the
Altera core. When you use this provided data path, you are ensured a
working system as the RLDRAM II IP tool bench constraints your
interface pins and data path logic for optimal operation. Figure 1 shows
the block diagram for the FPGA to RLDRAM II interface.
Figure 1. Block Diagram for the FPGA to RLDRAM II Interface
FPGA
Pass
or Fail
RLDRAM II Controller
Local
Interface
Example Driver
Note (1)
Control
Logic
(Encrypted)
RLDRAM II
Interface
RLDRAM II
Input
Clock
Write Clock
PLL
Data Path
(Clear-Text)
Read Clock
(DLL/PLL)
Notes to Figure 1:
(1)
4
You can either use the DLL-based implementation (for top and bottom I/O banks) or the PLL-based implementation
(for any I/O bank) for your RLDRAM II interface with Stratix II devices. Only the DLL-based implementation is
available in Stratix devices.
Altera Corporation
Interface Description
Interface Signals
Table 3 shows a summary of the RLDRAM II interface pins and how to
connect them to Stratix II, Stratix, and Stratix GX devices.
Table 3. RLDRAM II Interface Pins Summary
Description
Pins
DQ
RLDRAM II CIO bidirectional
read and write data
D
Note (1)
Stratix II Device Pin
Utilization (DLL-Based
Implementation)
DQ
Stratix II Device Pin
Utilization
(PLL-Based
Implementation)
Stratix or Stratix GX
Device Pin Utilization
(DLL-Based
Implementation)
User I/O pin (2)
DQ
RLDRAM II SIO unidirectional User I/O pin
write data
User I/O pin
User I/O pin
Q
RLDRAM II SIO unidirectional DQ
read data
User I/O pin (2)
DQ
DK
Unidirectional write clock for
the RLDRAM II device to
sample data
User I/O pin (3)
User I/O pin (3)
External clock buffer
(4)
DK#
Unidirectional write clock for
the RLDRAM II device to
sample data
User I/O pin (3)
User I/O pin (3)
External clock buffer
(4)
QK
Unidirectional read clock from
the RLDRAM II device
DQS
PLL dedicated clock
input
DQS
QK#
Unidirectional read clock from
the RLDRAM II device
Not used (5)
Not used (5)
Not used (5)
CK
System clock for the RLDRAM User I/O pin (3)
II device to sample address
and command
User I/O pin (3)
External clock buffer
(4)
CK#
System clock for the RLDRAM User I/O pin (3)
II device to sample address
and command
User I/O pin (3)
External clock buffer
(4)
QVLD(6)
Optional read data valid pin
DQVLD
User I/O pin (2)
User I/O pin
DM
Write data mask pin
User I/O pin
User I/O pin (2)
User I/O pin
All other
Address, control, etc.
User I/O pin
User I/O pin
User I/O pin
Notes to Table 3:
(1)
(2)
(3)
(4)
(5)
(6)
Stratix and Stratix GX devices do not offer PLL-based RLDRAM II interface implementation.
Refer to the Stratix II pin table for the recommended pins for PLL-based (non-DQS) implementation.
Use the same pin to drive CK and DK signals and another pin for CK# and DK# signals. You can use two different
pins if Quartus II reported skew between these pins meet the RLDRAM II device's tCKDK specification.
In order to meet the RLDRAM II tCKDK and input slew rate specification, Stratix devices requires external clock
buffer for the CK/CK# and DK/DK# signals generation.
Stratix II, Stratix, and Stratix GX devices do not use QK# signals for read operation.
Quartus II labels this pin as DQ pins in the top and bottom I/O banks.
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5
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Clock Signals
RLDRAM II devices use CK and CK# signals to clock the command and
address bus in single data rate (SDR). There is one pair of CK and CK#
pins per RLDRAM II device.
Instead of a strobe, RLDRAM II devices use two sets of free-running
differential clocks to accompany the data. The DK and DK# clocks are the
differential input data clocks used during writes while the QK or QK#
clocks are the output data clocks used during reads. Even though QK and
QK# signals are not differential signals according to the RLDRAM II data
sheets, Micron treats these signals as such for their testing and
characterization. Each pair of DK and DK# or QK and QK# clocks are
associated with either 9 or 18 data bits.
The exact clock-data relationships are as follows:
■
■
■
For ×36 data bus width configuration, there are 18 data bits
associated with each pair of write and read clocks. So, there are two
pairs of DK and DK# pins and two pairs of QK or QK# pins.
For ×18 data bus width configuration, there are 18 data bits per one
pair of write clocks and nine data bits per one pair of read clocks. So,
there is one pair of DK and DK# pins, but there are two pairs of QK
and QK# pins.
For ×9 data bus width configuration, there are nine data bits
associated with each pair of write and read clocks. So, there is one
pair of DK and DK# pins and one pair of QK and QK# pins each.
QK pins are connected to the DQS pins in Stratix II, Stratix, and
Stratix GX devices. Even though the QK signal is an input-only signal to
the Stratix II, Stratix, and Stratix GX device, you need to configure it as
bidirectional and tie the OE pin to ground to achieve the input-only
operation in the Quartus II software. The QK# pins are not used to
capture data in Stratix II, Stratix, and Stratix GX devices and can be left
unconnected.
There are tCKDK timing requirements for skew between CK and DK or
CK# and DK#. For optimal performance, use the same pair of user I/O
pins to generate CK and DK or CK# and DK# (using double data
registers) in Stratix II devices to minimize skew between these signals.
When interfacing RLDRAM II SIO devices with Stratix II devices, you
should place the CK and CK# and DK and DK# signals in the same I/O
bank as the D signals to minimize skew between these signals. You can
use two different pins for CK and DK (and similarly CK# and DK#) if the
Quartus II reported skew (the difference between the tCO times) meets the
memory’s tCKDK requirement. Use an external clock buffer to generate CK,
6
Altera Corporation
Interface Description
CK#, DK, and DK# when interfacing RLDRAM II devices with Stratix or
Stratix GX devices to meet the required RLDRAM II device input slew
rate specifications.
1
Make sure that the pin pairs for CK and CK# (and DK and DK#)
have matched tCO. You can use any unused DQS and DQS# pins
for interfaces on top and bottom I/O banks or use LVDS pin-pair
for interfaces on the side I/O banks.
Due to the loads on these I/O pins, the maximum frequency you can
achieve depends on the number of RLDRAM II devices you are
connecting to the Stratix II, Stratix, or Stratix GX device. Perform SPICE
or IBIS simulations to analyze the loading effects of the pin-pair on
multiple RLDRAM II devices.
Data, DM & QVLD Signals
When interfacing with a CIO device, connect the DQ pins with the
Stratix II, Stratix, or Stratix GX device DQ pins. For DLL-based
implementation, use the ×8 and ×9 DQS and DQ groups in Stratix II
devices and ×16 DQS and DQ groups in Stratix and Stratix GX devices for
RLDRAM II devices with data bus width configurations of ×9 and ×18.
Use ×16 and ×18 DQS and DQ groups in Stratix II devices and ×32 DQS
and DQ groups in Stratix and Stratix GX devices for RLDRAM II devices
with data bus width configuration of ×36. This is because there are nine
data bits associated with one QK pin in RDLRAM II devices in ×9 and ×18
data bus width configuration, and there are 18 data bits associated with
one QK pin in RDLRAM II devices in ×36 data bus width configuration.
1
The DQS and DQ groups in Stratix II, Stratix, and Stratix GX
devices indicate how many DQ pins one DQS pin can drive. For
example, a ×8 DQS and DQ group means that the DQS pin can
drive up to eight DQ pins in that group.
1
If you only use eight bits of the RLDRAM II device with data bus
width configurations of ×9 and ×18, then you can use the ×8
DQS and DQ groups in the Stratix or Stratix GX devices.
Similarly, if you are only using 16 bits of the RLDRAM II devices
with data bus width configuration of ×36, you can use the Stratix
or Stratix GX device’s ×16 DQS and DQ groups.
1
For PLL-based implementation, refer to the Stratix II pin tables
for the available DQS/DQ groups in the device.
When interfacing with RLDRAM II SIO devices, the memory device’s
Q ports must be connected to the DQ pins of the Stratix II device in a
similar fashion as when interfacing with RLDRAM II CIO devices. You
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7
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
can use any of the Stratix II, Stratix, or Stratix GX user I/O pins as outputs
to drive the D ports of the RLDRAM II SIO device. Altera recommends
the D, CK, CK#, DK, and DK# pins be in the same I/O bank to minimize
skew between these signals.
The write data is center-aligned with the DK and DK# clocks while the
read data is edge-aligned with the QK or QK# clocks (see Figures 2 and 3).
The memory controller shifts the DK or DK# signal to center align the DQ
and DK or DK# signal during a write and to shift the QK signal during a
read, so that read data (DQ or Q signals) and QK clock is center-aligned
at the capture register. Stratix II, Stratix, and Stratix GX devices use
dedicated DQS phase-shift circuitry to shift the incoming QK signal
during reads and use a PLL to center-align the DK and DK# signals with
respect to the DQ signals during writes.
Figure 2. DQ & QK Relationship During a RLDRAM II Read
Note (1)
DQS Pin to
Register Delay (2)
QK at
FPGA Pin
DQ at
FPGA Pin
QK at DQ
LE Registers
DQ at DQ
LE Registers
90 Degree Shift
DQ Pin to
Register Delay (2)
Notes to Figure 2:
(1)
(2)
This is an example of a 90° shift. The required phase shift for your system should be based on your timing analysis
and may not be 90°.
The delay from the QK pin to the register and from the DQ pin to the register can be configured to minimize
additional skew between the two signals at the IOE register in Stratix II devices. In Stratix and Stratix GX devices,
the delay from the QK pin to the register may not match the delay from the DQ pin to the register.
Figure 3. DQ & DK Relationship During RLDRAM II Write
DK at
FPGA Pin
DQ at
FPGA Pin
8
Altera Corporation
Interface Description
Tables 4 through 6 shows the number of DQ and DQS groups supported
in each Stratix II, Stratix, and Stratix GX device density and package
combination. Each column denotes the maximum number of DQ pins
that can be driven by one DQS pin per device. These pins are used for
DLL-based implementation. Refer to the Stratix II pin tables for DQS/DQ
groups used in PLL-based implementation.
Table 4. DQS & DQ Bus Mode Support in Stratix II
Number of
×4 Groups(1)
Number of
×8/×9 Groups
484-pin FineLine BGA
8
4
0
672-pin FineLine BGA
18
8
4
0
EP2S30
484-pin FineLine BGA
8
4
0
0
672-pin FineLine BGA
18
8
4
0
EP2S60
484-pin FineLine BGA
8
4
0
0
Device
EP2S15
EP2S90
Package
Number of
Number of
×16/×18 Groups ×32/×36 Groups
0
672-pin FineLine BGA
18
8
4
0
1,020-pin FineLine BGA
36
18
8(2)
4
484-pin Hybrid FineLine BGA
8
4
0
0
780-pin FineLine BGA
18
8
4
0
1,020-pin FineLine BGA
36
18
8(2)
4
1,508-pin FineLine BGA
36
18
8(2)
4
EP2S130 780-pin FineLine BGA
1,020-pin FineLine BGA
18
8
4
0
36
18
8(2)
4
1,508-pin FineLine BGA
36
18
8(2)
4
EP2S180 1,020-pin FineLine BGA
36
18
8(2)
4
1,508-pin FineLine BGA
36
18
8(2)
4
Notes to Table 4:
(1)
(2)
This mode is not used for RLDRAM II interfaces.
There are two extra ×8 and ×9, DQS and DQ groups in addition to the listed numbers: one in I/O bank 4 and one
in I/O bank 7.
Altera Corporation
9
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Table 5. DQS & DQ Bus Mode Support in Stratix Devices
Note (1)
Number of ×8
Groups (2)
Number of ×16
Groups (3)
Number of ×32
Groups (4)
672-pin BGA
672-pin FineLine BGA
12 (5)
0
0
484-pin FineLine BGA
780-pin FineLine BGA
16 (6)
0
4
484-pin FineLine BGA
18 (7)
7 (8)
4
672-pin BGA
672-pin FineLine BGA
16 (6)
7 (8)
4
780-pin FineLine BGA
20
7 (8)
4
672-pin BGA
672-pin FineLine BGA
16 (6)
8
4
780-pin FineLine BGA
1,020-pin FineLine BGA
20
8
4
EP1S30
956-pin BGA
780-pin FineLine BGA
1,020-pin FineLine BGA
20
8
4
EP1S40
956-pin BGA
1,020-pin FineLine BGA
1,508-pin FineLine BGA
20
8
4
EP1S60 (9)
956-pin BGA
1,020-pin FineLine BGA
1,508-pin FineLine BGA
20
8
4
EP1S80 (9)
956-pin BGA
1,508-pin FineLine BGA
1,923-pin FineLine BGA
20
8
4
Device
EP1S10
EP1S20
EP1S25
Package
Notes to Table 5:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
10
See the Using Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook, Volume 2
for VREF guidelines.
This mode can be used for RLDRAM II ×9 and ×18 data bus width configuration if parity is not used (i.e., the
design only uses 8 of the 9 data pins).
This mode is for RLDRAM II ×9 and ×18 data bus width configuration. It can also be used for ×36 data bus width
configuration if only 16 data pins are used.
This mode is for RLDRAM II ×36 data bus width configuration.
These packages have six groups in I/O banks 3 and 4 and six groups in I/O banks 7 and 8.
These packages have eight groups in I/O banks 3 and 4 and eight groups in I/O banks 7 and 8.
This package has nine groups in I/O banks 3 and 4 and nine groups in I/O banks 7 and 8.
These packages have three groups in I/O banks 3 and 4 and four groups in I/O banks 7 and 8.
These devices do not support RLDRAM II devices.
Altera Corporation
Interface Description
Table 6. DQS & DQ Bus Mode Support in Stratix GX Devices
Device
Package
Note (1)
Number of
×8 Groups (2)
Number of
×16 Groups (3)
Number of
×32 Groups (4)
EP1SGX10
672-pin
FineLine BGA
12 (5)
0
0
EP1SGX25
672-pin
FineLine BGA
16 (6)
8
4
1,020-pin
FineLine BGA
20
8
4
1,020-pin
FineLine BGA
20
8
4
EP1SGX40
Notes to Table 6:
(1)
(2)
(3)
(4)
(5)
(6)
See the Using Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook, Volume 2
for VREF guidelines.
This mode can be used for RLDRAM II ×9 and ×18 data bus width configuration if parity is not used (i.e., the
design only uses 8 of the 9 data pins).
This mode is for RLDRAM II ×9 and ×18 data bus width configuration. It can also be used for ×36 data bus width
configuration if only 16 data pins are used.
This mode is for RLDRAM II ×36 data bus width configuration.
These packages have six groups in I/O banks 3 and 4 and six groups in I/O banks 7 and 8.
These packages have eight groups in I/O banks 3 and 4 and eight groups in I/O banks 7 and 8.
Altera Corporation
11
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
The maximum number of RLDRAM II CIO devices that the Stratix II,
Stratix, or Stratix GX device can interface with is partially dependent on
the number of DQS and DQ groups available in that particular Altera
device. When interfacing with the RLDRAM II SIO devices or when
having multiple controllers in the FPGA for each RLDRAM II device, you
also need to consider the available number of user I/O pins that support
1.8-V HSTL class I or class II, depending on SIO or CIO mode, I/O
standard. Tables 7 through 9 show the maximum number of RLDRAM II
devices that can be supported in Stratix II, Stratix, and Stratix GX devices
using both available DLLs in the FPGA. These tables only consider the
number of DQS and DQ groups in that particular device and do not take
into account pin availability for the address and command pins, the
loading effect on the address and command pins, VREF pad placement
guidelines, or simultaneous switching noise.
Table 7. Maximum Number of RLDRAM II Devices That Can Be Supported in Stratix II Devices
Note (1)
Data Bus Width Configuration
Device
Package
×9
×18
×36
4
2
0
EP2S15
484-pin FineLine BGA
672-pin FineLine BGA
8
4
2
EP2S30
484-pin FineLine BGA
4
2
0
672-pin FineLine BGA
8
4
2
EP2S60
484-pin FineLine BGA
4
2
0
672-pin FineLine BGA
8
4
2
1,020-pin FineLine BGA
18
8(2)
4(2)
EP2S90
1,020-pin FineLine BGA
1,508-pin FineLine BGA
18
8(2)
4(2)
EP2S130
1,020-pin FineLine BGA
1,508-pin FineLine BGA
18
8(2)
4(2)
EP2S180
1,020-pin FineLine BGA
1,508-pin FineLine BGA
18
8(2)
4(2)
Note to Table 7:
(1)
(2)
12
This is for DLL-based implementation. These numbers are preliminary and only take into account the number of
DQS and DQ groups available in the device. You still need to make sure that there are enough pins for the address
and command signals and that the address and command signals are not degraded from the multiple RLDRAM II
loads. You should also consider the VREF pad placement guidelines and simultaneous switching noise. For the
maximum number of interfaces using just one DLL, divide the number by two.
You can also have two extra ×9 RLDRAM II interfaces, one in I/O bank 4 and one in I/O bank 7.
Altera Corporation
Interface Description
Table 8. Maximum Number of RLDRAM II Devices that Can Be Supported in Stratix Devices
(2), (3)
Notes (1),
Data Bus Width Configuration
Device
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
Package
×9
×18
×36
672-pin BGA (4)
672-pin FineLine BGA (4)
0
0
0
484-pin FineLine BGA (4)
780-pin FineLine BGA (4)
0
0
2
484-pin FineLine BGA
7
3
2
672-pin BGA
672-pin FineLine BGA
7
3
2
780-pin FineLine BGA
7
3
2
672-pin BGA
672-pin FineLine BGA
8
4
2
780-pin FineLine BGA
1,020-pin FineLine BGA
8
4
2
956-pin BGA
780-pin FineLine BGA
1,020-pin FineLine BGA
8
4
2
956-pin BGA
1,020-pin FineLine BGA
1,508-pin FineLine BGA
8
4
2
Notes to Table 8:
(1)
(2)
(3)
(4)
This is for DLL-based implementation. These numbers only take into account the number of DQS and DQ groups
in that particular device and do not consider pin availability for the address and command pins, the loading effect
on the address and command pins, VREF pad placement guidelines, or simultaneous switching noise. For the
maximum number of interfaces using just one DLL, divide the number by two.
If you are not using the parity bits in the RLDRAM II devices, you can interface with more RLDRAM II devices by
using the ×8 mode for RLDRAM II devices in the ×9 and ×18 data bus width configurations and the ×16 mode for
RLDRAM II devices in the ×36 data bus width configuration.
EP1S60 and EP1S80 devices do not support RLDRAM II memory.
This device can support RLDRAM II devices in ×9 and ×18 bus width configurations if the interface does not use
any parity bits by using the Stratix ×8 DQS and DQ mode.
Altera Corporation
13
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Table 9. Maximum Number of RLDRAM II Devices that Can Be Supported in Stratix GX Devices
Notes (1), (2)
Data Bus Width Configuration
Device
Package
×8
×16
×32
EP1SGX10 (3)
672-pin FineLine BGA
0
0
0
EP1SGX25
672-pin FineLine BGA
8
4
2
1,020-pin FineLine BGA
8
4
2
1,020-pin FineLine BGA
8
4
2
EP1SGX40
Notes to Table 9:
(1)
(2)
(3)
This is for DLL-based implementation. These numbers only take into account the number of DQS and DQ groups
in that particular device and do not consider account pin availability for the address and command pins, the
loading effect on the address and command pins, VREF pad placement guidelines, or simultaneous switching noise.
For the maximum number of interfaces using just one DLL, divide the number by two.
If you are not using the parity bits in the RLDRAM II devices, you can interface with more RLDRAM II devices by
using the ×8 mode for RLDRAM II devices in the ×9 and ×18 data bus width configurations and the ×16 mode for
RLDRAM II devices in the ×36 data bus width configuration.
This device can support RLDRAM II devices in x9 and x18 bus width configurations if the interface does not use
any parity bits by using the Stratix GX ×8 DQS and DQ mode.
Similar to DDR SDRAM or DDR2 SDRAM, the RLDRAM II data mask
(DM) pins are only used during a write. The memory controller drives the
DM signal low when the write is valid and drives it high to mask the DQ
signals. There is one DM pin per RLDRAM II device. When interfacing
with RLDRAM II CIO devices, you can use any of the I/O pins in the
same bank as the associated DQ pins to generate the DM signals. When
interfacing with RLDRAM II SIO devices, connect the DM pins to any of
the Stratix II, Stratix, or Stratix GX device user I/O pins in the same bank
as the D pins.
The DM timing requirements at the input to the RLDRAM II are identical
to those for DQ data. The DDR registers, clocked by the write clock, create
the DM signals. This reduces any skew between the DQ and DM signals.
The RLDRAM II device’s setup time (tDS) and hold (tDH) time for the write
DQ and DM pins are relative to the edges of the DK or DK# clocks. The
DK and DK# signals are generated on the positive edge of system clock,
so that the positive edge of CK or CK# is aligned with the positive edge
of DK or DK# respectively to meet the RLDRAM II tCKDK requirement.
The DQ and DM signals are clocked using a shifted clock so that the edges
of DK or DK# are center-aligned with respect to the DQ and DM signals
when they arrive at the RLDRAM II device.
14
Altera Corporation
Interface Description
1
Perform timing analysis to calculate the optimal phase shift for
the data and data mask signals.
The clocks, data, and DM board trace lengths should be tightly matched
to minimize the skew in the arrival time of these signals.
RLDRAM II devices also have a QVLD pin indicating valid read data. The
QVLD signal is edge-aligned with QK or QK# and is high approximately
half a clock cycle before data is output from the memory. Connect the
QVLD pin from the RLDRAM II device to the Stratix II device DQVLD
pin.
The DQVLD pins in Stratix II devices are treated like DQ pins as signals
coming into the DQVLD pins can be captured by the shifted DQS signal.
1
Stratix devices do not use the RLDRAM II QVLD pins.
Resynchronization in this interface uses a feedback clock
scheme.
Commands & Addresses
The CK and CK# signals clock the commands and addresses into
RLDRAM II devices. These pins operate at single data rate using only one
clock edge. RLDRAM II devices have 18 to 21 address pins, depending on
the data bus width configuration and burst length. RLDRAM II supports
both non-multiplexed and multiplexed addressing. Multiplexed
addressing allows you to save a few user I/O pins while non-multiplexed
addressing allows you to send the address signal within one clock cycle
instead of two clock cycles. CS#, REF#, and WE# pins are input commands
to the RLDRAM II device.
The commands and addresses must meet the memory address and
command setup (tAS, tCS) and hold (tAH, tCH) time requirements. You can
use any I/O pins to generate the commands and addresses for
RLDRAM II.
Altera Corporation
15
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Interface Architecture
Altera provides two different methods to implement the read-side
interface to RLDRAM II devices. Stratix II, Stratix, and Stratix GX devices
use a read-side DLL to center align the QK read clock with the read data
(DQ or Q). In addition to that method, Stratix II devices also offer the PLLbased implementation, using a PLL to center align the QK read clock with
read data. Stratix devices do not offer the PLL-based implementation.
The write-side implementation is identical for both PLL- and DLL-based
implementations. A write-side PLL outputs two clocks that generate the
write data (DQ or D) and center-aligned write clocks (DK and DK#) using
the dedicated double data rate input/output (DDIO) circuits. This
implementation results in matched propagation delays for clock and data
signals from the FPGA to the RLDRAM II, minimizing skew.
f
For detailed information about the DDR I/O and DLL circuits, refer to
the External Memory Interface chapter of the Stratix II Device Handbook or
the External Memory Interface chapter of the Stratix Device Handbook.
DLL-Based Data-Path Architecture
The RLDRAM II interface implementation in Stratix II devices uses the
following:
■
■
A write-side PLL to generate CK and CK# system clocks, DK and
DK# write clocks, and clock out address, command, and data signals.
A read-side DLL-based phase-shift circuitry to register read data
from the memory read clocks QK and QK#.
This implementation is also called DQS mode or DLL-based read
implementation.
There are separate DQS phase shift circuits available on the top side and
on the bottom side of the FPGA. Each DQS phase shift circuit needs an
input reference clock. In Stratix and Stratix GX devices, the input
reference clock must come from an input clock pin, while in Stratix II
devices, the input reference can come from an input clock pin or PLL 5 or
PLL 6. The DQS phase shift circuitry shifts the QK signal to center-align
the signal with the DQ signal at the IOE register, ensuring the data gets
latched at the IOE register. The QK signal is then inverted before going to
the DQ IOE registers clock ports as described in the External Memory
Interfaces chapter of the Stratix II Device Family Handbook or the Stratix
Device Family Handbook.
16
Altera Corporation
Interface Description
Figure 4 shows a summary of how the data (D, Q, or DQ), CK, CK#, DK,
DK#, QK, and QK# pins are connected in Stratix II devices. The write PLL
generates the system clock and write clock. The system clock and write
clock have the same frequency as the DQS signal. The write clock is
shifted –105° from the system clock, which is the default in the
RLDRAM II controller MegaCore function. You should perform your
own timing analysis to calculate the optimal write phase shift for your
system.
The example in Figure 4 uses the QVLD signal to synchronize the data to
the system clock. The board trace length for QVLD should match closely
with the data (D, Q, or DQ) and QK signal board trace lengths. The QVLD
signal is captured as if it is data and then it is routed into the FPGA cores
as a FIFO write enable. The FIFO is used as a buffer where the write clock
is connected to the delayed DQS signal and the read clock is connected to
the system clock. The overflow and underflow checking for the FIFO
should be turned on to avoid reading garbage data from the FIFO.
Altera Corporation
17
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Figure 4. DLL-Based RLDRAM II Data Path Interface for Stratix II Devices
LE
IOE
DM
DDR
length = l2
DQ Write (1)
D or DQ
Shifted −105˚
DDR
length = l2
CK/DK (2)
length = l1
Write
Clock
CK#/DK# (2)
Write PLL
input_clk
System
Clock
DDR
length = l1
RLDRAM II
Device
QK (4)
Input
Reference
Clock (3)
DQS Phase-Shift
Circuitry
length = l2
DQS Logic
Block
DQ Read (1)
D
Q
Read Clock
Q or DQ
DDR
length = l2
Write Clock
DQVLD
Write Enable
DDR
QVLD
length = l2
Dual-Clock FIFO
Notes to Figure 4:
(1)
(3)
(4)
RLDRAM CIO device data is bidirectional on the DQ pins. RLDRAM SIO device data is sent on two separate
unidirectional lines (D for write data and Q for read data). For RLDRAM II SIO interfaces, connect Q to the DQ pins
in the Stratix II device and use any of the user I/O pins in I/O banks 3, 4, 7, or 8 for the D ports.
If loading may be an issue, you can use two different pins to generate CK and DK (and similarly CK# and DK#).
However, please make sure that the skew reported by the Quartus II software meets the RLDRAM II device’s tCKDK
specification.
The input reference clock can either be from input_clk, another clock pin, or a PLL 5 or 6 output.
Connect the RLDRAM II device QK pin to the DQS pins in Stratix II devices.
18
Altera Corporation
(2)
Interface Description
In Stratix II devices, the shifted DQS signal is routed to the FPGA logic
array to clock the resynchronization FIFO and any read-side registers
using regular routing. When using the resynchronization FIFOs, your
memory controller needs to account for any additional latency from
routing the DQS signals to the FPGA logic array.
Figure 5 shows the RLDRAM II interface data path for Stratix and
Stratix GX devices. Figure 5 also uses a feedback clock and a second PLL
to simplify resynchronization. Stratix II, Stratix, and Stratix GX devices
use an external clock buffer to generate CK, CK#, DK, and DK# signals to
meet the required 2-V/ns slew rate at the RLDRAM II device. The
external clock buffer is a zero-delay clock buffer. The clock buffer
loop-back trace length (l1) is equal to the CK, CK#, DK, and DK# trace
lengths from the clock buffer to the RLDRAM device such that the
effective trace length for the CK, CK#, DK, and DK# signals from the
FPGA to the RLDRAM II device is equal to l2. Currently, the Altera
RLDRAM II controller MegaCore function does not support the Stratix
and Stratix GX device family.
1
Altera Corporation
Micron preliminary guidelines says that the required setup and
hold time of the RLDRAM II device may double if the slew rate
of the driving device is 1 V/ns.
19
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Figure 5. DLL-Based RLDRAM II Data Path Interface for Stratix & Stratix GX Devices
length = l1 + l2
LE
IOE
DM
length = l2
DDR
Shifted −90˚
DQ Write (1)
length = l2
DDR
CK
Write
Clock
Write PLL (7)
input_clk
System
Clock
D or DQ
length = l2
External
Clock
Buffer (2)
CK#
DK
DK#
DDR
length = l1
RLDRAM II
Device
length = l1
Read PLL (7)
Δt
QK (4)
length = l2
Input
Reference
Clock (3)
DQS Phase-Shift
Circuitry
DQ Read (1)
Q or DQ
length = l2
DDR
DDR
(6)
DDR
(5)
Notes to Figure 5:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
20
RLDRAM CIO device data is bidirectional on the DQ pins. RLDRAM SIO device data is sent on two separate,
unidirectional lines (D for write data and Q for read data). For RLDRAM II SIO interfaces, connect Q to the DQ pins
in the Stratix and Stratix GX device and use any of the user I/O pins in I/O Banks 3, 4, 7, or 8 for the D ports.
The external clock buffer is in external feedback mode. Its feedback input is in phase to the signals going into the
RLDRAM II device minus any trace length skew, jitter, and offset error.
The input reference clock must come from an input clock pin in Stratix and Stratix GX devices. You must use a PLL
output clock to feed the DLL and must be able to only enable the input reference clock to the DLL during refresh
and initialization cycle.
Connect QK from the RLDRAM II devices to the DQS pins in Stratix and Stratix GX devices.
The clock to the resynchronization register can be from the system clock, write clock, and extra clock output from
the write PLL or from the read PLL.
The clock to this register can either be the system clock or another clock output of the write PLL. If another clock
output of the write PLL is needed, another register is needed to transfer the data back to the system clock domain.
The PLL is in normal mode. You should only use even M and N PLL counter values to avoid excessive duty cycle
distortion.
Altera Corporation
Interface Description
PLL-Based Data-Path Architecture
The RLDRAM II interface implementation without using dedicated DQS
circuitry uses the following:
■
■
A write-side PLL to generate CK and CK# system clocks DK and DK#
write clocks, and clock out address, command, and data signals.
A read-side PLL-based phase-shift to register read data from the
memory.
This implementation is also called PLL-based read implementation (or
non-DQS mode). The read PLL is in source synchronous mode in this
implementation. You need to ensure that the read PLL is in the same side
of the device as the data pins are in because Quartus II associates a
particular PLL with a particular I/O bank for source synchronous
operation. The clock delay to the worst case I/O registers in this I/O bank
are fully compensated and result in closely matched data delays and
clock delays from pin to the I/O registers across PVT. When using I/O
registers in the non-compensated I/O banks, clock delays and data delays
are less closely matched. Use a Fast PLL for implementing the interface in
side I/O banks, and use an Enhanced PLL for implementing the interface
on top or bottom I/O banks for best clock and data delay matching. You
also need to set the input pin delay to register option to 0 in Quartus II.
Figure 6 shows a summary of how Stratix II devices generate the DQ,
DQS, CK, and CK# signals. The write PLL generates system clock and
write clock. The read clock QK from the RLDRAM II device goes to a PLL
input pin which generates the proper phase shift to capture read data.
Altera Corporation
21
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Figure 6. PLL-Based RLDRAM II Data Path Interface in Stratix II Devices
LE
IOE
DM
DDR
length = l2
DQ Write (1)
D or DQ
Shifted −90˚
DDR
length = l2
CK/DK (2)
length = l1
Write
Clock
CK#/DK# (2)
Write PLL
input_clk
System
Clock
DDR
length = l1
QK (and QK#) (3)
RLDRAM II
Device
length = l2
Read PLL
DQ Read (1)
Q or DQ
D
Q
Read Clock
DDR
length = l2
Write Clock
DQVLD
Enable
DDR
QVLD
length = l2
Dual-Clock FIFO
Notes to Figure 6:
(1)
(2)
(3)
22
RLDRAM CIO device data is bidirectional on the DQ pins. RLDRAM SIO device data is sent on two separate
unidirectional lines (D for write data and Q for read data). For RLDRAM II SIO interfaces, connect Q to the DQ pins
in the Stratix II device and use any of the user I/O pins in I/O banks 3, 4, 7, or 8 for the D ports.
If loading may be an issue, you can use two different pins to generate CK and DK (and similarly CK# and DK#).
However, please make sure that the skew reported by the Quartus II software meets the RLDRAM II device’s tCKDK
specification.
Connect the RLDRAM II QK to the input clock pin of the read PLL. You can also connect the differential QK/QK#
to the differential input clock pins of the read PLL.
Altera Corporation
Interface Description
Altera Memory Controller IP
The RLDRAM II Controller MegaCore function allows you to instantiate
a simplified interface to the industry-standard RLDRAM II memory. The
RLDRAM II Controller initializes the memory devices and manages the
read and write operations. The MegaCore function translates read and
write requests from the local interface into all the necessary RLDRAM II
command signals.
The RLDRAM II Controller contains encrypted control logic as well as an
clear-text data path that you can use in your design without a license.
Download this MegaCore function whether you plan to use the Altera
RLDRAM II controller or not to get the clear-text data path, logic and pin
placement constraints.
You can download the RLDRAM II Controller MegaCore function from
www.altera.com. Alternatively, the MegaCore function is also available in
the IP library CD as part of the Quartus II CD pack.
The MegaCore function is accessible through the RLDRAM II IP Tool
Bench. When you parameterize your custom RLDRAM II interface, the
RLDRAM II IP Tool Bench automatically decides the best-read phase shift
for your frequency of operation and FPGA settings to give you the best
margin for your RLDRAM II interface. It then generates an example
instance that instantiates a PLL, an example driver, and your RLDRAM II
Controller custom variation as shown in Figure 1 on page 4.
After downloading and installing the RLDRAM II Controller MegaCore
function, you need to create a project before launching the RLDRAM II IP
Tool Bench. Figure 7 shows the Parameterize page of the RLDRAM II IP
tool bench. You need to pick the RLDRAM II memory, the frequency of
operation, and the configuration that you are implementing. You can also
set the location constraints and generate the simulation model from the
RLDRAM II IP Tool Bench. The RLDRAM II IP Tool bench generates a
fully functional example design that can be simulated, synthesized, and
used in hardware. The example driver in the example design issues read
and writes to the controller and compares the read data with the
previously written data to generate pass-fail and test-complete signals. If
you do not want to use the Altera RLDRAM II controller encrypted
control logic, you can replace it with your own custom logic. This allows
you to use the Altera supported data path with your own logic. For more
detailed information on the usage of the RLDRAM II Controller
MegaCore function, please download the RLDRAM II Controller
MegaCore User Guide at www.altera.com.
Altera Corporation
23
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Figure 7. RLDRAM II Controller MegaCore Function
Interface Timing
Analysis
When designing an external memory interface for your FPGA, you have
to analyze timing margins for several paths. All memory interfaces
require analysis of the read and write capture timing paths. Additionally,
some interfaces might require analysis of the resynchronization timing
paths and other memory-specific paths (such as postamble timing).
This application note describes Altera's recommended timing
methodology using write and read capture timing paths as examples. You
should use this methodology for analyzing timing for all applicable
timing paths (including address/command and resynchronization for
Stratix and Stratix GX interfaces). While these analyses account for all
FPGA related timing effects, you should design in adequate margin to
account for board level effects.
The following presents an analysis of the read and write capture timing
margins for the Micron MT49H8M36FM-33 RLDRAM II interface with
the Stratix II EP2S60F1020C3. This is a sample interface that shows you
24
Altera Corporation
Interface Timing Analysis
the proper methodology for this timing analysis to ensure you include the
proper timing specifications for your preferred FPGA and memory
device.
Methodology
To analyze timing paths you need to consider the data and clock arrival
times at the destination register. Figure 8 illustrates a simplified block
diagram to analyze timing at any register. The setup time margin is
defined as the time between “earliest clock arrival time” and “latest valid
data arrival time” at the register ports. Similarly, hold time margin is
defined as the time between “earliest invalid data arrival time” and the
“latest clock arrival time” at the register ports. These arrival times are
calculated based on propagation delay information with respect to a
common reference point (such as a memory clock edge or system clock
edge). Figure 9 shows how a data valid window is derived based on
arrival times.
Figure 8. Simplified Block Diagram for Timing Analysis
Data Delay
D
Q
CLK
Clock Delay
Figure 9. Data Valid Window Timing Waveform
tH
tSU
Altera Corporation
25
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
FPGA Timing Information
If your design is required to work under all conditions (between 0° C to
85° C for commercial FPGAs), the timing margins should be evaluated at
all process, voltage, and temperature (PVT) conditions. To facilitate this,
Altera provides two device timing models in the Quartus II software:
slow corner model and fast corner model.
■
■
The slow corner model provides timing delays between two nodes
within the FPGA with slow silicon for that speed grade, high
temperature, and low voltage. In other words, the model provides
the slowest possible delay for that timing path on any device for that
particular speed grade.
The fast corner model provides timing delays between two nodes
within the FPGA with fast silicon, low temperature, and high
voltage. In other words, the model provides the fastest possible delay
for that timing path on any device in that density.
Note that while almost all FPGA timing delays and uncertainties are
modeled in the Quartus II software, a handful of factors are not modeled
and should be accounted for during margin analysis. Some examples
include clock jitter on PLL and DLL outputs. These uncertainties are
described in the Stratix II device data sheet. These timing uncertainties or
adder terms, when used in conjunction with the Quartus II software
reported timing data, provide the most accurate device timing
information. The following analysis will detail the use of these timing
adder terms.
Read Timing Margins for DLL-Based Implementation
During read operations, the RLDRAM II memory device provides a read
clock (QK) that is edge-aligned with the data bus (Q or DQ). The memory
controller (FPGA) is required to shift the clock edge to the center of the
data valid window and capture the DQ input data. See Figure 2 on page 8
for the relationship between DQ and QK during a read.
Figure 10 shows the DLL-based read data path from the Stratix II device.
The QK signal goes to the DQS phase-shift circuitry and gets shifted. The
shifted QK signal goes to the DQS bus and gets inverted before it clocks
the DQ input registers. The register outputs then go to a dual-clock FIFO
with the captured QVLD signal as the write enable.
26
Altera Corporation
Interface Timing Analysis
Figure 10. RLDRAM II DLL-Based Read Data Path in Stratix II Devices
LEs
IOEs
(1)
dq_oe
dq_out
dataout[35..0]
Q
DQ[35..0] or Q [35..0] (2)
Q
D
Q
D
D
Q
D
ena
FIFO
latch
system clock
ena
QVLD (4)
QK[1..0] (3)
DQS Phase-Shift Circuitry
DQS
Local Bus
Notes to Figure 10:
(1)
(2)
(3)
(4)
The dq_oe signals are active low in silicon. However, the Quartus II software implements it as active high and adds
the inverter automatically during compilation.
The RLDRAM II device may have the same or separate ports for data read and data. If separate, connect Q of the
RLDRAM II device to the DQ pins of the Stratix II, Stratix, or Stratix GX device and connect dq_oe to GND. You
can use any of the user I/O pins in I/O banks 3, 4, 7, or 8 to connect to the D pins of the RLDRAM II device.
The DQS pins in Stratix II, Stratix, or Stratix GX devices must be connected to the QK signals of the RLDRAM II
device.
This QVLD signal has been captured in the IOE by the shifted QK signal.
Altera Corporation
27
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Figure 11 shows the DLL-based read data path from the Stratix or
Stratix GX device. The QK signal goes to the DQS phase-shift circuitry
and gets shifted. The shifted QK signal goes to the DQS bus and gets
inverted before it clocks the DQ input registers. The register outputs then
go to the resynchronization register in the logic array, sampled by the
resynch_clock signal. You can use the system clock, the write clock, or
another clock output of the PLL as the resynch_clock signal.
Figure 11. RLDRAM II Read Data Path in Stratix or Stratix GX Devices
LEs
IOEs
(1)
dq_oe
dq_out
dataout[17..0]
DQ[17..0] or Q [17..0] (2)
Q
D
Q
Q
D
Q
D
D
Q
D
ena
latch
resynch_clock
QK (3)
DQS Phase-Shift Circuitry
DQS
Local Bus
Notes to Figure 11:
(1)
(2)
(3)
The dq_oe signals are active low in silicon. However, the Quartus II software implements it as active high and adds
the inverter automatically during compilation.
The RLDRAM II device may have the same or separate ports for data read and data. If separate, connect Q of the
RLDRAM II device to the DQ pins of the Stratix II, Stratix, or Stratix GX device and connect dq_oe to GND. You
can use any of the user I/O pins in I/O banks 3, 4, 7, or 8 to connect to the D pins of the RLDRAM II device.
The DQS pins in Stratix II, Stratix, or Stratix GX devices must be connected to the QK signals of the RLDRAM II
device.
Memory Timing Parameters
You would start the read timing analysis by obtaining the timing
relationship between the DQ and DQS outputs from the RLDRAM II
memory device. The following describes the timing analysis for the
300-MHz RLDRAM II interface in a Stratix II EP2S60F1020C3 device. For
300-MHz clock speeds or 600-Mbps data rates, the read data clock high or
low time is 1349 ps after accounting for duty cycle distortion on the input
clock to the memory and the read data clock itself. This is specified as tQKH
28
Altera Corporation
Interface Timing Analysis
in the memory data sheet and is 0.9 × 0.45 x 3333 ps. Apart for tQKH, the
memory also specifies tQKQ0/QKQ1, which specifies the maximum time
from a QK edge to the last Q or DQ valid. For 300 MHz operation,
tQKQ0/QKQ1 is specified to be ± 250 ps.
With these memory timing parameters, the data valid window at the
memory to be equal to tQKH –2 × tQKQ0/QKQ1 = 849 ps. Assuming the board
trace length variations amongst all DQ and DQS traces are not more than
± 20ps, the data valid window present at the FPGA input pins is 809 ps.
FPGA Timing Parameters
FPGA timing parameters are obtained from two sources: the Quartus II
software timing analyzer and the Stratix II data sheet. While the former
provides all clock/data propagation delays, the data sheet specifies all
clock uncertainties and skew adder terms.
The timing analysis methodology outlined earlier suggests the use of the
earliest and latest arrival times for clock and data. The following details
timing analysis for the clock (QK).
The Stratix II features dedicated phase-shift circuitry in the top/bottom
IO banks of the device, which will center-align the DQS edge with respect
to the DQ input signals. This phase shift circuitry has a coarse and fine
delay resolution. The coarse delay feature is self-compensating over PVT
and has a resolution of 22.5° to 36° of the reference clock frequency (based
on the DLL mode of operation). For 300 MHz, you can select between
DLL modes 2 (high) and 3 (very high). DLL mode 2 gives a 30° coarse
phase resolution, while mode 3 gives 36° resolution. You can further
fine-tune this phase shift with a DLL phase-shift offset implement using
uncompensated delay chains. This example analyzes timing with a 72°
phase shift on the DQS strobe (DLL mode 3), knowing that the phase shift
(and DLL mode) can always be adjusted at the end of this timing analysis
for balanced setup and hold margins on the read capture register.
Altera Corporation
29
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Table 10 shows the default DQS phase shifts in the Altera RLDRAM II
Controller MegaCore function.
Table 10. Default Phase Shifts in the Altera RLDRAM II Controller MegaCore
Function
RLDRAM II Clock Frequency
Default DQS Phase Shift Note (1)
241 – 300 MHz
72°
230 – 240 MHz
90°
175 – 229 MHz
67.5°
Notes to Table 10:
(1)
You should calculate your read capture margin and reconfirm that the default
DQS phase shift is acceptable for your system.
The DQS phase shift circuitry uses a DLL to provide the selfcompensating coarse delay shift. This means you have to account for any
jitter and phase shift error on the DQS signal. To achieve 72° phase shift
in DLL mode 3, two DQS delay buffer stages are used in the DQS logic
block. The data sheet shows tDQS_JITTER is ± 55 ps and tDQS_PSERR is ± 25 ps
timing parameters when using two DQS delay buffer stages.
After encountering the phase shift circuitry, the DQS signal travels on a
dedicated DQS bus to the DQ capture registers. The fan-out of this bus
could range from ×4 to ×36. While the Quartus II software provides clock
propagation delays to each of these DQ register clock ports, you still need
to account for additional uncertainties with the tDQS_SKEW_ADDER adder
term listed in the data sheet. For the ×18 mode used by this Micron
RLDRAM II device, the skew adder is ± 37.5 ps.
To obtain the Quartus II software timing data for the target device,
instantiate and compile the RLDRAM II Controller MegaCore function. If
you are using your own controller logic, you should instantiate the cleartext RLDRAM II data path instead to obtain timing delays. For the read
interface, the Quartus II software reports individual setup and hold times
for each DQ pin. Select the “List Paths” option in the timing report to get
the data and clock propagation delays for that DQ pin. Select the worstcase setup and hold DQ registers to extract the minimum and maximum
propagation delays.
For example, Figure 12 shows a “List Paths” example on the setup time
for DQ[18]. This path shows propagation delays of 1.815 ns on the DQ pin
to register path, and 2.407 ns on the DQS clock pin to register path.
30
Altera Corporation
Interface Timing Analysis
Figure 12. List Paths
Using this approach, minimum and maximum propagation delays on the
clock and data path are extracted and presented in Table 11. This timing
extraction is done twice, once with each device model (fast model and
slow model). Observe that the difference between minimum and
maximum delays is very small due to the matched routing paths within
the die and package.
Table 11. Minimum and Maximum Propagation Delays for EP2S60F1020C3 Device
FPGA Timing Delays
Fast Model
Slow Model for C3 Speed Grade
Data Delay (minimum)
1.152 ns
1.755 ns
Data Delay (maximum)
1.212 ns
1.815 ns
Clock Delay (minimum)
1.808 ns
2.407 ns
Clock Delay (maximum)
1.826 ns
2.430 ns
Micro Setup
0.068 ns
0.122 ns
Micro Hold
0.037 ns
0.072 ns
Setup & Hold Margins Calculations
You can calculate the read setup and hold time margins of the DQ capture
register after obtaining all relevant timing information from the memory,
FPGA, and board.
Earliest clock arrival time = Minimum clock delay within FPGA – DQS
uncertainties
= Clock delay (minimum) – tDQS_JITTER –
tDQS_PSERR – tDQS_SKEW_ADDER
= 2407 – 30 – 25 – 37.5
= 2314.5 ps (with slow timing model)
Altera Corporation
31
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Latest data valid time
= Memory DQS-to-DQ valid +
maximum data delay in FPGA
= tQKQ0/tQKQ1 + data delay (maximum)
= 250 + 1815
= 2065 ps (with slow timing model)
Setup time margin
= Earliest clock arrival – latest data valid –
micro setup – board uncertainty
= tEARLY_CLOCK – tLATE_DATA_VALID –
µtSU – tEXT
= 2314.5 – 2065 – 122 – 20
= 107.5 ps (with slow timing model)
When repeating these calculations with the fast timing model, the
derived setup margin is 166 ps.
Latest clock arrival time
= Maximum clock delay within FPGA + DQS
uncertainties
= Clock delay (maximum) + tDQS_JITTER +
tDQS_PSERR + tDQS_SKEW_ADDER
= 2430 + 30 + 25 + 37.5
= 2522.5 ps
Earliest data invalid time = Memory clock-to-data invalid + minimum
data delay in FPGA
= (tQKH – tQKQ0/QKQ1) + data delay (minimum)
= (1349 – 250) + 1755
= 2854 ps (with slow timing model)
Hold time margin
= Latest clock arrival time –
earliest data_Latest clock arrival time
invalid time – micro hold – board
uncertainty
= tEARLY_DATA_INVALID –
tLATE_CLOCK – µtH – tEXT
= 2854 – 2522.5 – 72 – 20
= 239.5 ps (with slow timing model)
You also need to repeat the hold timing margin calculation with the fast
timing model. Using the fast model numbers in Table 11, the margin is
276 ps.
Table 12 shows the read timing margin analysis at 300 MHz for the
RLDRAM II interface in Stratix II EP2S60F1020C3 devices, when the
board trace variations for the DQ and DQS pins is ± 20 ps (approximately
± 0.12 inches of FR4 trace length variations) using the methodology that
was just described. Table 13 shows the RLDRAM II read timing margins
32
Altera Corporation
Interface Timing Analysis
analysis with Stratix or EP1S25F780C5 at 200 MHz. You can perform a
similar timing analysis for your interface with another RLDRAM II
memory, by replacing the tQKQ0/QKQ1 and tQKH values in the table below
with those from your memory data sheet and by replacing the FPGA
specification for your particular device. This timing analysis applies for
both RLDRAM II CIO and SIO interfaces.
Table 12. Read Data Timing Analysis for 300-MHz RLDRAM II Interface in EP2S60F1020C3 with the DQS
Phase-Shift Circuitry
(Part 1 of 2)
Parameter
Memory Specifications
(1)
FPGA Specifications (2)
Board Specifications
Altera Corporation
Fast
Slow
Corner Corner
Model Model
Description
tQ K H
1.349
1.349
Half period as specified by the memory
data sheet (including memory clock duty
cycle distortion)
tQ K Q 0 / t Q K Q 1
0.250
0.250
QK edge to output data edge skew
tD Q S _ P H A S E _ J I T T E R
0.030
0.030
This is the peak-to-peak digital-phase
jitter on the DQS clock network with the
DLL used
tD Q S _ P S E R R
0.025
0.025
Phase shift error on DQS output delayed
by DLL
tD Q S _ S K E W _ A D D E R
0.038
0.038
Clock delay skew adder for x16/x18
DQS/DQ group
Minimum Clock Delay
(Input) (3), (4)
1.808
2.407
Minimum DQS pin to IOE register delay
from Quartus II (with 72° DLL-based
phase shift)
Maximum Clock Delay 1.826
(Input) (3), (4)
2.430
Maximum DQS pin to IOE register delay
from Quartus II (with 72° DLL-based
phase shift)
Minimum Data Delay
(Input) (3), (4)
1.152
1.755
Minimum DQ pin to IOE register delay
from Quartus II
Maximum Data Delay
(Input) (3), (4)
1.212
1.815
Maximum DQ pin to IOE register delay
from Quartus II
µtS U (3)
0.068
0.122
Intrinsic setup time of the IOE register
µtH (3)
0.037
0.072
Intrinsic hold time of the IOE register
tE X T
0.020
0.020
Board trace variations on the DQ and
DQS lines
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Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Table 12. Read Data Timing Analysis for 300-MHz RLDRAM II Interface in EP2S60F1020C3 with the DQS
Phase-Shift Circuitry
(Part 2 of 2)
Fast
Slow
Corner Corner
Model Model
Parameter
Timing Calculations
Results
Description
tE A R LY _ C L O C K
1.716
2.315
Earliest possible clock edge after DQS
phase-shift circuitry and uncertainties
(minimum clock delay – tD Q S _ J I T T E R –
tD Q S _ P S E R R – t D Q S _ S K E W _ A D D E R )
tL AT E _ C L O C K
1.919
2.523
Latest possible clock edge after DQS
phase-shift circuitry and uncertainties
(maximum clock delay + tD Q S _ J I T T E R +
tD Q S _ P S E R R + t D Q S _ S K E W _ A D D E R )
tE A R LY _ D ATA _ I N VA L I D
2.251
2.854
Time for earliest data to become invalid
for sampling at FPGA flop (tQ K H – tQ K Q +
minimum data delay)
tL AT E _ D ATA _ VA L I D
1.462
2.065
Time for latest data to become valid for
sampling at FPGA flop (tQ K Q + maximum
data delay)
Read setup timing
margin
0.166
0.108
tE A R LY _ C L O C K – tL AT E _ D ATA _ VA L I D –
µtS U – tE X T
Read hold timing
margin
0.276
0.240
tE A R LY _ D ATA _ I N VA L I D – tL AT E _ C L O C K –
µtH – tE X T
Total margin
0.441
0.347
Setup margin + hold margin
Notes for Table 12:
(1)
(2)
(3)
(4)
The memory numbers used here come from Micron MT49H8M36FM-33.
This analysis is performed with FPGA timing parameters for Stratix II EP2S60F1020C3. You should use this
template to analyze timing for your preferred Stratix II density-package combination. For more information on
FPGA specifications, refer to the DC & Switching Characteristics in Volume 1 of the Stratix II Handbook.
These numbers are from the Quartus II software version 5.1.
Package trace skews are modeled by the Quartus II software.
Table 13. Read Analysis When Using DQS Circuitry in Stratix & Stratix GX -5 Speed Grade Devices
(Part 1 of 2)
Parameter
Memory
specifications
34
Specification
200 MHz (1)
Description
tQ K H
2.025 ns
Minimum output data clock high time as specified by
the memory data sheet
tQ K Q
0.350 ns
QK edge to any output data edge as specified by the
memory data sheet
Altera Corporation
Interface Timing Analysis
Table 13. Read Analysis When Using DQS Circuitry in Stratix & Stratix GX -5 Speed Grade Devices
(Part 2 of 2)
Parameter
FPGA
specifications
Specification
200 MHz (1)
Description
DLL phase shift (2)
1.000 ns
tD L L J I T T E R (3)
0.100 ns
Stratix device DLL jitter
tP S E R R
0.082 ns
DLL phase shift error
tD Q S 2 I O E _ M I N (4)
0.579 ns
Minimum DQS pin to IOE register delay
Ideal DLL phase shift
tD Q S 2 I O E _ M A X (4)
1.021 ns
Maximum DQS pin to IOE register delay
tD Q 2 I O E _ M I N (4)
0.549 ns
Minimum DQ pin to IOE register delay
tD Q 2 I O E _ M A X (4)
0.939 ns
Maximum DQ pin to IOE register delay
tD Q S Q I N T
0.150 ns
DQS–DQ internal skew inside Stratix device
µtS U
0.280 ns
Intrinsic setup time of the IOE register (rounded up)
µtH
0.070 ns
Intrinsic hold time of the IOE register (rounded up)
Board
specification
tE X T
0.050 ns
Board trace variations for the DQ and DQS lines
Timing
calculations
tS H I F T _ M I N
0.918 ns
Minimum shift provided by the DQS phase-shift
circuitry (DLL Shift – tP S E R R – tD L L J I T T E R )
tS H I F T _ M A X
1.082 ns
Maximum shift provided by the DQS phase-shift
circuitry (DLL Shift + tP S E R R + tD L L J I T T E R )
tD E LTA _ M I N
0.976 ns
Minimum difference between the DQS and the DQ
signals paths (tD Q S 2 I O E _ M I N + tS H I F T _ M I N –
tD Q 2 I O E _ M I N )
tD E LTA _ M A X
1.182 ns
Maximum difference between the DQS and the DQ
signals paths (tD Q S 2 I O E _ M A X + tS H I F T _ M A X –
tD Q 2 I O E _ M A X )
Read setup timing
margin
0.118 ns
tD E LTA _ M I N – tQ K Q – tE X T – tD Q S Q I N T – µtS U
Read hold timing
margin
0.241 ns
tQ K H – tQ K Q – µtH – tE X T – tD Q S Q I N T – tD E LTA _ M A X
Results
Notes to Table 13:
(1)
(2)
(3)
(4)
The memory numbers used here come from Micron MT49H16M18/C-5. Assume the external clock buffer does not
add any skew to the DK and D or DQ signals.
This example uses 72º phase shift.
This example uses tDLLJITTER equal to 0, because the DLL is on only during refresh and initialization cycles.
Numbers are taken from the Quartus II software. Use the latest version of the Quartus II software for the most
current information.
Altera Corporation
35
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Read Timing Margins for PLL-Based Implementation
Timing margin analysis for a PLL-based implementation is very similar
to the previously described DLL-based implementation. The only
differences are the capture clock used and related clock uncertainties. In
this mode, the write clock, QK signal is fed into a PLL inside the FPGA.
The timing margin analysis presented here uses Stratix II EP2S60F1020C3
devices.
Figure 11 shows the PLL-based read data path from the Stratix II device.
The QK signal goes to the PLL and the PLL generates a phase shifted read
clock to capture the read data. The outputs of the DQ registers then go to
a dual-clock FIFO with the capture QVLD signal as the write enable.
Alternatively, you can also take the differential QK and QK# signals and
use the PLL differential inputs for the write PLL to take advantage of the
differential signaling from the RLDRAM II devices.
Figure 13. PLL-Based Read Data Path
LEs
Notes (1), (2), (3), (4)
IOEs
(1)
dq_oe
dq_out
dataout[17..0]
Q
DQ[17..0] or Q [17..0] (2)
Q
D
Q
D
D
Q
D
ena
FIFO
latch
system clock
write ena
QVLD (4)
PLL
QK (3)
Global Clock Network
Notes to Figure 13:
(4)
The dq_oe signals are active low in silicon. However, the Quartus II software implements it as active high and adds
the inverter automatically during compilation.
The RLDRAM II device may have the same or separate ports for data read and data. If separate, connect Q of the
RLDRAM II device to the DQ pins of the Stratix II, Stratix, or Stratix GX device and connect dq_oe to GND. You
can use any of the user I/O pins in I/O banks 3, 4, 7, or 8 to connect to the D pins of the RLDRAM II device.
The QK (or QK and QK#) signals from the RLDRAM II device must be connected to an input PLL clock pin. Use a
Fast PLL for RLDRAM II interfaces on the side I/O banks. Use an enhanced PLL for RLDRAM II interfaces on the
top and bottom I/O banks.
This QVLD signal has been captured in the IOE by the shifted QK signal.
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Altera Corporation
(1)
(2)
(3)
Interface Timing Analysis
Memory Timing Parameters
The timing relationship of data (Q or DQ) with respect to the read clock
QK is governed by the tQKQ. For the RLDRAM II memory device under
consideration, this timing parameter is ± 500ps.
FPGA Timing Parameters
When the read clock, QK is fed into the PLL for read capture,
uncertainties introduced on this clock include jitter and phase shift error.
PLL-based read implementation uses a single global clock network to
distribute the phase shifted clock signal to DQ capture registers in the
IOE. The difference in clock arrival times to these registers (clock skew) is
modeled in the Quartus II software, and is reflected in the
minimum/maximum propagation delays for the clock. Additionally, the
Quartus II software models the package trace delays for every pin in the
device. Hence, you do not account for such skews separately in our
timing margin analysis. The extracted minimum/maximum clock and
data delays account for these uncertainties. Table 14 shows the read
timing margin calculation for the PLL-based RLDRAM II interface using
an EP2S60F1020C3 device.
Table 14. Read Timing Analysis for 200-MHz DDR2 SDRAM Interface in EP2S60F1020C3 Non-DQS Mode
(Part 1 of 3)
Parameter
Memory
Specifications (1)
Altera Corporation
Specification
Fast Model
Slow Model
Description
tQKH
2.025
2.025
Half period as specified by the
memory data sheet (including
memory clock duty cycle
distortion)
tQKQ (2)
0.400
0.400
QK edge to output data edge
skew
37
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Table 14. Read Timing Analysis for 200-MHz DDR2 SDRAM Interface in EP2S60F1020C3 Non-DQS Mode
(Part 2 of 3)
Parameter
Specification
Fast Model
Slow Model
Description
tPLL_JITTER (2)
0.125
0.125
Stratix II PLL jitter
tPLL_COMP_ERROR (3)
0.100
0.100
PLL Compensation Error (high
bandwidth)
tPLL_PSERR (3)
0.030
0.030
PLL Phase Shift Error
Minimum Clock Delay (4),
(5)
1.725
2.161
Minimum feedback clock pin to
IOE register delay from Quartus
II (75° PLL phase shift)
Maximum Clock Delay (4),
(5)
1.756
2.213
Maximum feedback clock pin to
IOE register delay from Quartus
II (75° PLL phase shift)
Minimum Data Delay (4)
0.621
0.974
Minimum DQ pin to IOE register
delay from Quartus II
Maximum Data Delay (4),
(5), (6)
0.695
1.050
Maximum DQ pin to IOE
register delay from Quartus II
µtSU (5), (6)
0.068
0.122
Intrinsic setup time of the IOE
register
µtH
0.037
0.068
Intrinsic hold time of the IOE
register
Board
Specifications
tEXT_SKEW
0.020
0.020
Board trace variations on the
DQ and DQS lines
Timing
Calculations
tEARLY_CLOCK
1.470
1.906
Earliest possible clock edge
after DQS phase-shift circuitry
and uncertainties (minimum
clock delay + PLL phase shift –
tPLL_PSERR – tPLL_JITTER tPLL_COMP_ERROR)
tLATE_CLOCK
2.011
2.468
Latest possible clock edge after
DQS phase-shift circuitry and
uncertainties (maximum clock
delay + PLL phase shift +
tPLL_PSERR + tPLL_JITTER +
tPLL_COMP_ERROR)
tEARLY_DATA_INVALID
2.246
2.599
Time for earliest data to
become invalid for sampling at
FPGA flop (tHP - tAC + minimum
data delay)
tLATE_DATA_VALID
1.095
1.450
Time for latest data to become
valid for sampling at FPGA flop
(tAC + maximum data delay)
FPGA
Specifications
38
Altera Corporation
Interface Timing Analysis
Table 14. Read Timing Analysis for 200-MHz DDR2 SDRAM Interface in EP2S60F1020C3 Non-DQS Mode
(Part 3 of 3)
Parameter
Results
Specification
Fast Model
Slow Model
Description
Read setup timing margin
0.287
0.314
tEARLY_CLOCK - tLATE_DATA_VALID Tsu(micro) - tEXT
Read hold timing margin
0.178
0.043
tEARLY_DATA_INVALID - tLATE_CLOCK Th(micro) - tEXT
Total margin
0.465
0.357
Setup + hold time margin
Notes to Table 14:
(1)
(2)
(3)
(4)
(5)
(6)
The memory numbers used here come from Micron MT49H8M36FM-33.
Only one QK signal is connected to the PLL, while there are 2 in the device. You cannot use the tQ K Q 0 /tQ K Q 1
parameter due to this.
Value may change pending final characterization.
PLL phase shift is adjustable if you need to balance the setup and hold time margin.
These numbers are from the Quartus II software, version 5.1 using the RLDRAM II MegaCore function version
1.0.0.
Package trace length skew is modeled in Quartus II version 5.0 and higher. There is no additional adder required.
1
If you need more hold time margin, then you need less PLL
phase shift. Similarly if you need more setup margin, you need
more phase shift. In the example in Table 14, you can balance the
setup and hold margin by using a PLL phase shift that is lower
than 75°.
Write Data Timing Margins
For write operations, the RLDRAM II memory requires the write clock
(DK) to be center-aligned with the data bus (Q or DQ). This is
implemented in Stratix II using the PLL phase shift feature. Two output
clocks are created from the PLL, with a relative phase offset. The leading
clock edge is used to clock out the DQ write data output pins to the
memory, while the lagging clock edge is used to generate the DK/DK#
write clock and CK/CK# memory output clocks. See Figure 3 on page 8
for the relationship between DQ and DK during a write.
Altera Corporation
39
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Figure 4 on page 18 shows that the write side uses a PLL to generate the
clocks listed in Table 15.
Table 15. Write Side PLL Clocks
Clock
Description
System clock
This is used for the memory controller and to
generate the DK/DK# and CK/CK# signals.
Write clock (leading system
clock) (1)
This is used in the data path to generate the
DQ write signals.
Note to Table 15:
(1)
Perform write timing calculation to determine the phase shift required for this
write clock.
Figure 14 shows the RLDRAM II write data path in Stratix II devices. For
best performance, you should use the same pin to generate both CK and
DK signals or CK# and DK# signals so that the skew between CK and DK
signals or CK# and DK# signals are minimized. You can generate these
signals with two different pins after making sure that the Quartus II
reported skew (from the tCO times) meets the memory’s tCKDK
specification. You can use any unused DQS/DQS# or LVDS pin-pair to
generate CK/CK# (and DK/DK#) signals.
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Altera Corporation
Interface Timing Analysis
Figure 14. RLDRAM II Write Data Path in Stratix II Devices
LE
VCC
Gnd
IOE
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
VCC
DK (1)
CK (2)
VCC
Gnd
VCC
DK# (1)
CK# (2)
clk
dq_oe (3)
datain[17..0]
D
Q
D
Q
[17..9]
Q or DQ[8..0] (4)
Write Clock
[8..0]
dq_in
Notes to Figure 14:
(1)
(2)
(3)
(4)
RLDRAM II does not use the DQS pin during writes. Instead, DK and DK# are used and generated by user I/O pins
via the DDR registers.
To meet the tCKDK specification from the RLDRAM II device, use the same pin pair to generate both CK and DK or
CK# and DK#. You can use two different pins to generate CK and DK (and similarly CK# and DK#) if the tC O
difference between these two pins meet the tCKDK specification. Perform IBIS simulation for loading effects on these
signals when interfacing with multiple RLDRAM II devices.
The dq_oe is active low in silicon. However, the Quartus II software implements it as active high and adds the
inverter automatically during compilation.
The RLDRAM II device may have the same or separate ports for data read and data. If separate, connect Q of the
RLDRAM II device to the DQ pins of the Stratix II device and connect dq_oe to GND. You can use any of the user
I/O pins in I/O banks 3, 4, 7, or 8 to connect to the D pins of the RLDRAM II device.
Altera Corporation
41
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Figure 15 shows the RLDRAM II write data path in Stratix and Stratix GX
devices. The CK, CK#, DK, and DK# are generated by an external clock
buffer in this interface.
Figure 15. RLDRAM II Write Data Path in Stratix & Stratix GX Devices
CK
CK#
DK
External Clock Buffer
CK#
Stratix
LE IOE
dq_oe
datain[35..0]
D
Q
D
Q
(1)
[35..18]
D
Q
D
Q
D
Q
Q or DQ[17..0] (2)
clk
[17..0]
clk_shifted
dq_in
Notes to Figure 15:
(1)
(2)
The dq_oe is active low in silicon. However, the Quartus II software implements
it as active high and adds the inverter automatically during compilation.
The RLDRAM II device may have the same or separate ports for data read and
data. If separate, connect Q of the RLDRAM II device to the DQ pins of the
Stratix II device and connect dq_oe to GND. You can use any of the user I/O pins
in I/O banks 3, 4, 7, or 8 to connect to the D pins of the RLDRAM II device.
Memory Timing Parameters
When writing to a memory, the FPGA needs to ensure that setup and hold
times are met. These specifications (tDS and tDH) are obtained from the
data sheet (300 ps for the 300 MHz RLDRAM II example). Additionally,
the FPGA needs to provide a memory clock (CK/CK#) that meets the
clock high/low time specifications. And finally, the skew between the DK
write clock and CK output clock cannot exceed limits set by the memory.
While the last parameter does not affect timing margins, it needs to be
met for successful memory operation.
42
Altera Corporation
Interface Timing Analysis
FPGA Timing Parameters
The timing paths within the FPGA for the DQ and DK outputs to memory
are matched by design. Dedicated clock networks drive DDR IO
structures to generate DQ and DQS. This results in minimal skew
between these outputs. There are three skew parameters to be considered
phase shift error, clock skew, and package skew.
The two clock networks used are driven by the same PLL, however with
a relative phase-shift. The system (0°) clock is used to generate DK/DK#
write clock, while a leading clock is used to generate DQ. You should
perform a similar timing analysis like the one described below to
calculate the write clock phase shift. Typical PLL uncertainties such as
jitter and compensation error affect both clock networks equally, so these
timing parameters do not affect write timing margins. However, since the
clock generating DQ is phase-shifted, you need to account for the PLL
phase-shift uncertainty (tPLL_PSERR = ± 30 ps), listed in the Stratix II device
data sheet when calculating DQ arrival times at the memory pins.
The Quartus II software models intra-clock skew, skew between nodes
driven by the same dedicated clock network. However, skew between
two such clock networks is not modeled and specified in the data sheet as
an adder term. You should add this skew component to the propagation
delays extracted from the Quartus II software.
For our RLDRAM II interface, the clock skew adder between two clock
networks is specified as ± 50 ps (tCLOCK_SKEW_ADDER). This uncertainty is
accounted while calculating DQS arrival times at the memory pins.
The final skew component is package skew. As noted earlier, the
Quartus II software (starting from version 5.0) models package trace
delay for each pin on the device. Extracted propagation delays reflect any
skew between output signals to the memory.
You need to perform this write timing analysis to find the optimum phase
shift to generate your data pins. As a rule of thumb, you need a more
negative phase shift if you want more setup time margin and vice versa.
You need a more positive phase shift if you want more hold time margin.
Altera Corporation
43
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Setup & Hold Margins Calculations
Table 16 shows the RLDRAM II write timing margin analysis when
interfacing with Stratix II devices at 300 MHz. The board trace variations
for the DQ and DQS pins is ± 20 ps (approximately ±0.12 inches of FR4
trace length variations). You can perform a similar timing analysis for our
interface with another RLDRAM II memory by replacing the tDS and tDH
values in Table 16 with those from your memory data sheet. This timing
analysis applies for both RLDRAM II CIO and SIO devices.
Table 16. Write Timing Analysis for 300 MHz RLDRAM II Interface in EP2S60F1020C3
Parameter
Fast
Corner
Model
Slow
Corner
Model
(Part 1 of 2)
Description
Memory
specifications (1)
tD S
0.300
0.300
Memory data setup requirement
tD H
0.300
0.300
Memory data hold requirement
FPGA
specifications(2)
tH P
1.485
1.485
Ideal half period minus 5% duty cycle
distortion
tP L L _ J I T T E R
0.000
0.000
Does not affect margin as the same PLL
generates both write clocks (0° and –75°)
tP L L _ P S E R R
0.030
0.030
PLL Phase Shift Error
tC L O C K _ S K E W _ A D D E R
0.050
0.050
Clock skew between two dedicated clock
networks feeding IO banks on same side
of the FPGA
Minimum Clock Delay
(Output) (3), (4), (5)
0.849
1.626
Minimum DQS tC O from Quartus II (0°
PLL output clock)
Maximum Clock Delay
(Output) (3), (4), (5)
0.849
1.626
Maximum DQS tC O from Quartus II (0°
PLL output clock)
Minimum Data Delay
(Output) (3), (4)
–0.096
0.526
Minimum DQ tC O from Quartus II (–105°
PLL output clock)
Maximum Data Delay
(Output) (3), (4)
0.077
1.096
Maximum DQ tC O from Quartus II (–105°
PLL output clock)
Board
specifications
tE X T
0.020
0.020
Board trace variations on the DQ and
DQS lines
Timing
calculations
tE A R LY _ C L O C K
0.799
1.576
Earliest possible clock edge seen by
memory device (minimum clock delay –
tP L L _ J I T T E R – tC L O C K _ S K E W _ A D D E R )
tL AT E _ C L O C K
0.849
1.676
Latest possible clock edge seen by
memory device (maximum clock delay +
tP L L _ J I T T E R + t C L O C K _ S K E W _ A D D E R )
tE A R LY _ D ATA _ I N VA L I D
1.539
2.161
Time for earliest data to become invalid
for sampling at the memory input pins
(tH P + minimum data delay – tP L L _ P S E R R )
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Altera Corporation
Interface Timing Analysis
Table 16. Write Timing Analysis for 300 MHz RLDRAM II Interface in EP2S60F1020C3
Fast
Corner
Model
Slow
Corner
Model
tL AT E _ D ATA _ VA L I D
0.107
1.126
Time for latest data to become valid for
sampling at the memory input pins
(maximum data delay + tP L L _ P S E R R )
Write setup timing
margin
0.372
0.130
tE A R LY _ C L O C K – tL AT E _ D ATA _ VA L I D – tD S
– tE X T
Write hold timing
margin
0.320
0.165
tE A R LY _ D ATA _ I N VA L I D – tL AT E _ C L O C K –
tD H – t E X T
Total margin
0.692
0.295
Setup margin + hold margin
Parameter
Results
(Part 2 of 2)
Description
Notes for Table 16:
(1)
(2)
(3)
(4)
(5)
The memory numbers used here come from Micron MT49H8M36FM-33.
This analysis is performed with FPGA timing parameters for an EP2S60F1020C3. You should use this template to
analyze timing for your preferred Stratix II density-package combination. For more information on FPGA
specifications, refer to the DC & Switching Characteristics in Volume 1 of the Stratix II Handbook.
These numbers are from the Quartus II software version 5.1 using the Altera RLDRAM II MegaCore function
version 1.0.0.
Package trace skews are modeled by the Quartus II software.
For CK/CK# signals, choose pins with matched tC O . You can use any unused DQS/DQS# or LVDS pin-pairs.
Altera Corporation
45
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Table 17 shows the RLDRAM II example write timing margin analysis for
a Stratix EP1S25 device.
Table 17. Write Timing Analysis for a Stratix EP1S25 -5 Speed Grade Device
Parameter
Memory
specifications
FPGA
specifications
Specification
tC K
200 MHz
5 ns
tD S = tD H (1)
0.4 ns
Description
Clock period
DQ and DM setup and hold time from the memory data
sheet
tI O S K E W
0.160 ns
Absolute value of the difference in clock-to-out times (tC O )
between any two output registers on the top/bottom of the
device fed by a common clock source
tC L K S K E W
0.150 ns
Skew between two PLL outputs
tD C D
0.250 ns
Duty cycle distortion (5% of clock period)
tE X T
0.05 ns
Board trace variations for the DQ and DQS lines (166 ps
per inch for an FR4 trace)
Timing calculation tS H I F T _ M I N
1.1 ns
Minimum shift from the PLL (0.25 × tC K (90° phase shift) –
tC L K S K E W )
tS H I F T _ M A X
1.4 ns
Maximum shift from the PLL (0.25 × tC K (90° phase shift) +
tC L K S K E W )
Board
specification
Results
Write setup timing
margin
0.240 ns
tS H I F T _ M I N – tD C D – tI O S K E W – tE X T – tD S
Write hold timing
margin
0.240 ns
0.5 × tC K – tS H I F T _ M A X – tC D C D – tI O S K E W – tE X T – tD H
Note for Table 17:
(1)
The memory numbers used here come from Micron MT49H16M18/C-5.
Command & Address Timing
Command and address signals are generated from the system clock (or
another clock) in single data rate. The command and address signals must
meet the setup and hold time requirement with respect to the rising edge
of the CK signal at the RLDRAM II device. The FPGA also generates the
CK signal from the system clock either directly or via an external clock
buffer. Depending on the location of the registers for the commands and
addresses, you may need to use a different system clock edge or add a
phase shift on the system clock to make sure that these signals meet the
setup and hold time requirement at the RLDRAM II device. This section
outlines the commands and addresses timing considerations.
46
Altera Corporation
Interface Timing Analysis
For example, if you place the command and address registers clocked by
the system clock in the IOE, the command and address signals at the
FPGA change at the same time as the CK signal since they are both
generated from the system clock either directly or via an external clock
buffer. The delays from the IOE registers to the pins are then similar
(exactly the same if there is no clock skew). The Altera RLDRAM II
controller MegaCore constrains the command and address registers in the
IOE.
In this example, the command and address signals are edge-aligned with
the CK signal (if there are no variations in the package or board trace
length of the system for the different signals). This means that the address
and command signals cannot meet the setup time requirement of the
RLDRAM II device. In order to meet the setup and hold time
requirement, you have to use the negative edge of the system clocks to
generate the command and address signals if you want to place the
command and address registers in the IOE. Figure 16 shows the
command and address timing and how the system clock edge affects how
the signals meet the RLDRAM II tAS/tCS and tAH/tCH requirements.
Figure 16. Command & Address Timing Using the IOE Registers
Note (1)
System Clock
CK
RLDRAM II
SDRAM Write Requirement
DK/DK# Write (at FPGA Pin)
RLDRAM II Address/Command
Input Timing to the DDR
SDRAM Device
tAS / tCS
(RLDRAM II)
tCO
(FPGA)
tAH / tCH
(RLDRAM II)
Address/Command Pins
(positive edge)
Address/Command Pins
(negative edge)
tCO (FPGA)
Note to Figure 16:
(1)
In this waveform, there is no clock skew or any variations in package and board trace length.
You can perform timing analysis for command and address signals
similar to the write data timing analysis to find the optimal phase shift to
generate the command and address signals. The only difference between
Altera Corporation
47
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
the write data timing analysis and the command and address timing
analysis is that the command and address timing signals are single data
rate whereas the data signals are double data rate.
The default clock for the command and address signals in the
RLDRAM II MegaCore function is the falling edge of the system clock.
Quartus II reports the tCO does not automatically verify sourcesynchronous outputs will meet the setup/hold requirements at the
destination, so you will need to subtract ½ clock cycle from the tCO
reported. Table 18 shows the tCO reported by Quartus II and the actual tCO
if you relate this tCO with the CK/CK# tCO.
Table 18. Reported and Adjusted Command/Address tco Note (1)
Fast Timing Slow Timing
Model
Model
Units
Quartus II reported minimum
command/address tC O
0.971
1.720
ps
Quartus II reported maximum
command/address tC O
1.044
1.792
ps
Adjusted minimum command/address tC O
-0.696
0.053
ps
Adjusted maximum command/address tC O
-0.623
0.126
ps
Note to Table 18:
(1)
Quartus II does not automatically verify source-synchronous output will meet
the setup/hold requirements at the destination. Since this is a system timing
analysis, you need to find the actual tCO compared to the tCO for the CK/CK#
signals. The adjusted tCO numbers show the ½ clock cycle reported from the
Quartus II reported tCO to account for the falling edge signal.
Table 19 shows an example of the command and address timing analysis
for an EP2S60F1020C3 interfacing with 300-MHz RLDRAM II device.
Table 19. Command/Address Timing Analysis for 300-MHz RLDRAM II Interface in EP2S60F1020C3
(Part 1 of 3)
Parameter
tDS
Memory
Specifications
(1)
tDH
48
Fast
Slow
Corner Corner
Model Model
Description
0.500
0.500
Memory Command/Address Setup
Requirement
0.500
0.500
Memory Command/Address Hold
Requirement
Altera Corporation
Interface Timing Analysis
Table 19. Command/Address Timing Analysis for 300-MHz RLDRAM II Interface in EP2S60F1020C3
(Part 2 of 3)
Parameter
Fast
Slow
Corner Corner
Model Model
Description
tCK
FPGA
Specifications
tP L L _ J I T T E R
(2)
2.997
2.997
Clock period - 10% duty cycle distortion
0.000
0.000
Does not affect margin as the same clock
is used to generate CK and
command/address signals
tP L L _ P S E R R
0.030
0.030
PLL Phase Shift Error (On –90° clock
output)
tC L O C K _ S K E W _ A D D E R (3)
0.000
0.000
Same clock is used to generate CK and
command/address signals, so the skew
should be accounted for in Quartus II
Minimum Clock Delay (Output)
(4), (5)
0.849
1.626
Minimum CK tC O from Quartus II
Maximum Clock Delay (Output)
(4), (5)
0.849
1.626
Maximum CK tC O from Quartus II
Minimum Command/Address
Delay (Output) (5), (6)
-0.696
0.053
Minimum Command/Address tC O
Board
Maximum Command/Address
Specifications Delay (Output) (5), (6)
-0.623
0.126
Maximum Command/Address tC O
Timing
Calculations
tE X T
0.020
0.020
Board trace variations on the DQ and
command/address lines
tE A R LY _ C L O C K
0.849
1.626
Earliest possible clock edge seen by
memory device (minimum clock delay –
tP L L _ J I T T E R – tC L O C K _ S K E W _ A D D E R )
tL AT E _ C L O C K
0.849
1.626
Latest possible clock edge seen by
memory device (maximum clock delay +
tP L L _ J I T T E R + tC L O C K _ S K E W _ A D D E R )
tE A R LY _ C M D _ A D D _ I N VA L I D
2.272
3.021
Time for earliest command/address to
become invalid for sampling at the memory
input pins (tH P + Minimum Data Delay –
tP L L _ P S E R R )
tL AT E _ C M D _ A D D _ VA L I D
-0.593
0.156
Time for latest command/address to
become valid for sampling at the memory
input pins (Maximum Data Delay +
tP L L _ P S E R R )
Command/address setup timing
margin
0.922
0.951
tE A R LY _ C L O C K – tL AT E _ C M D _ A D D _ VA L I D –
tD S – t E X T
Command/address hold timing
margin
0.903
0.875
tE A R LY _ C M D _ A D D _ I N VA L I D – tL AT E _ C L O C K
– tD H – tE X T
Results
Altera Corporation
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Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Table 19. Command/Address Timing Analysis for 300-MHz RLDRAM II Interface in EP2S60F1020C3
(Part 3 of 3)
Parameter
Total margin
Fast
Slow
Corner Corner
Model Model
1.824
1.825
Description
Setup margin + Hold margin
Notes to Table 19:
(1)
(2)
(3)
(4)
(5)
(6)
The memory numbers used here come from Micron MT49H8M36FM-33.
This analysis is performed with FPGA timing parameters for an EP2S60F1020C3. You should use this template to
analyze timing for your preferred Stratix II density-package combination. Refer to the DC & Switching Characteristics
chapter in Volume 1 of the Stratix II Handbook.
If you are using a dedicated clock to generate command and address signals, then this parameter is not 0. Refer to
the DC & Switching Characteristics chapter in Volume 1 of the Stratix II Handbook for the most up-to-date clock skew
adder specification.
Command and Address signals are generated on the falling edge of the system clock in this example. This value is
adjusted from Quartus II reported tC O as Quartus II reports the tC O based on the rising edge of the input clock
regardless of how the signal is generated.
These numbers are from the Quartus II software, version 5.1 using the Altera RLDRAM II MegaCore function
version 1.0.0.
Package trace skews are modeled by the Quartus II software.
Bus Turnaround Timing Analysis
When using Stratix II, Stratix, or Stratix GX devices to interface with
RLDRAM II CIO devices, you need to insert a no-operation command
when switching from read to write or from write to read since the
Stratix II device cannot turn the bus around fast enough.
Figure 17 shows a timing waveform of an example of read and write
operations for RLDRAM II CIO devices when burst length equals two.
The figure shows a read, followed by a write and then another read. You
need to calculate whether you need to insert a no-operation command in
between a read to write or a write to read transition.
1
50
For RLDRAM II CIO devices operating in burst length of four,
you always need to insert a no-operation per memory
specification when switching from read to write and write to
read for uninterrupted read and write operations. You still need
to insert one extra no-operation command if the bus turnaround
of the FPGA is going to cause contention.
Altera Corporation
Interface Timing Analysis
Figure 17. Bus Turnaround in RLDRAM II Interfaces When Burst Length Equals Two
0
1
2
3
4
5
6
7
CMD
RD
WR
NOP
RD
NOP
NOP
NOP
NOP
ADDR
A
BA0
A
BA1
CK#
CK
A
BA2
RL = 4
WL = 5
RL = 4
DKx#
DK×
DQ
(1)
(1)
Q0a
Q0b
(1)
D1a
(1)
(1)
D1b
Q2a
RD to WR
turnaround
WR to RD
turnaround
QVLD
QK×
QK×#
Note to Figure 17:
(1)
The gray section shows when data is changing. The blue section shows data valid.
As shown in Figure 17, the read-to-write transition (RD to WR
turnaround) is about 0.75 clock cycle maximum and the write-to-read
transition (WR to RD turnaround) is about 0.25 clock cycle maximum.
You need to make sure that the FPGA can turn off and turn on the bus
quickly enough to avoid contention. The following sections describe the
calculation in detail for burst-of-two operations.
Read-to-Write Transition
In order to calculate the fastest (worst) bus turnaround time during a
read-to-write transition, use the maximum RLDRAM II timing delays
and the minimum FPGA timing delays. Figure 18 shows part of the
timing waveform shown in Figure 17, focusing on the read-to-write
transition part.
Altera Corporation
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Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Figure 18. Worst Case Read-to-Write Transition Timing Waveform
CK#
CK
QK× (maximum)
tCKDK
(minimum)
(1)
tCKQK
(maximum)
DKx# (minimum)
DK× (minimum)
DQ
(2)
(2)
(2)
(2)
Q0a
Q0b
D1a
D1b
tQKQ
(maximum)
Bus
transition
90˚shift
(minimum)
(3)
Notes to Figure 18:
(1)
(2)
(3)
Even though CK and DK signals are derived the same way, there may be skew
either from the board or from the external clock buffer if you are using Stratix or
Stratix GX devices.
The gray section shows when data is changing. The blue section shows that data is
valid.
The minimum 90º phase shift accounts for PLL output skew, I/O output skew,
offset error from the external clock buffer, and board trace length mismatch.
As shown in Figure 18, when you use the maximum RLDRAM II timing
delays, the read data is shifted to the right. Figure 18 also shows that
when you use the minimum FPGA timing delays, the write data is shifted
to the left. As a result, the bus transition time shrinks from the optimal
0.75 clock cycle maximum transition width. To determine whether a
no-operation command needs to be inserted when switching from a read
to a write operation, you need to calculate the actual bus transition width
of the interface.
For example, consider a 200 MHz RLDRAM II interface in a Stratix device
using a burst length of two with the following RLDRAM II specifications:
■
■
■
■
tCKQK: 0.5 ns
tQKQ: 0.4 ns
Maximum data width: (1.1 x 0.55 × tCK) + (2 × tQKQ)
Longest board trace length skew: + 20 ps
Using CK as the reference clock, the read data is invalid after a time
period as calculated below:
52
Altera Corporation
Interface Timing Analysis
Read data invalid period=
tCKQK + tQKQ + burst length × maximum data width =
0.5 ns + 0.4 ns + 2 × 3.825 ns + 0.020 ns = 8.57 ns
To determine how long after the first CK edge the invalid time occurs,
divide the time period from the previous equation by the time it takes to
send the data burst.
Invalid time = Read data invalid period / (burst length / 2 × tCK)
8.57 ns/ 5 ns per clock cycle = 1.714 clock cycles
This means that read data can be valid 0.714 clock cycles later than when
it is supposed to end.
On the write side of the transition, the DK signal can arrive earlier than
CK by tCLKBUFVAR (variations from the external clock buffer) which
consists of:
■
■
■
1
tCLKBUFSKEW (the skew between two outputs from the external clock
buffer)
tCLKBUFJITTER (jitter from the external clock buffer)
tCLKBUFDCD (duty cycle distortion from the external clock buffer).
If your design interfaces Stratix II devices with RLDRAM II
devices, it will not have a tCLKBUFVAR parameter. Instead, you
should account for the Stratix II PLL jitter and duty cycle
distortion.
The 90º phase-shifted clock from the FPGA that generates the write data
can also be skewed from its ideal phase by tPLLSKEW (the skew between
two outputs of the PLL in the FPGA).
IDT clock buffer IDT5T2110 has the following specifications (from its data
sheet):
■
■
■
tCLKBUFSKEW: ± 0.1 ns
tCLKBUFJITTER: ± 0.125 ns
tCLKBUFDCD: ± 0.1 ns
In addition, read data can also be skewed by the I/O output skew
specification from the FPGA (tIOSKEW), and the board trace length
variations (tEXT).
Altera Corporation
53
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Stratix EP1S25 characterization data shows the following:
■
■
tPLLSKEW: ± 0.150 ns
tIOSKEW: ± 0.160 ns
Use the following equation to determine the earliest the data can arrive at
the DQ pins to drive the bus from its ideal time:
tCLKBUFSKEW + tCLKBUFJITTER + tCLKBUFDCD + tPLLSKEW + tIOSKEW =
0.1 ns + 0.125 ns + 0.1 ns + 0.150 ns + 0.160 ns = 0.635 ns
This means that the data can come earlier by 0.127 clock cycle (0.635 ns/
5 ns clock period)
Based on this example, you need an extra no-operation command
because you have a maximum of 0.75 clock cycle turnaround time and the
variations require 0.841 clock cycles (0.714 + 0.127 clock cycles).
Therefore, you need to add a no-operation command when switching
from a read to a write.
You can perform a similar calculation for Stratix II FPGAs in C3 speed
grade interfacing with 300-MHz RLDRAM II devices using the following
parameters:
■
■
■
■
■
tCLOCK_SKEW_ADDER (clock skew between two dedicated clock
networks feeding I/O banks on the same side of the FPGA) = ± 50 ps
tPLL_PSERR (PLL phase-shift error) = ± 30 ps
Quartus reported I/O skew (by getting the tCO differences for the OE
signals for the DQ pins): 73 ps
Quartus reported clock skew (if you are using two different pins to
generate CK and DK). In this example, the design has 0 ps skew.
tDCD (duty cycle distortion from the PLL) = 167 ps (5% of 300 MHz)
The earliest data arrival is the summation of all the parameters above. In
this example, the total is 320 ps. This means data can come earlier by 0.096
clock cycle. The read data invalid for 300-MHz RLDRAM II is 5.6 ns (1.682
clock cycles). With this example, you need an extra no-operation
command in 300-MHz RLDRAM II interfaces since data can come as
early as 0.778 clock cycles (0.682 + 0.0946 clock cycles), which exceeds the
0.75 clock cycle turn-around time.
1
54
PLL jitter in the Stratix II timing calculation is considered zero
since data and clock are generated the same way and so they will
jitter together.
Altera Corporation
Interface Timing Analysis
Write-to-Read Transition
Similarly, in order to calculate the fastest (worst) bus turnaround time
during a write-to-read transition, you need to use the maximum FPGA
timing delays and the minimum RLDRAM II timing delays. Figure 19
shows part of the timing waveform shown in Figure 17, focusing on the
write-to-read transition part.
Figure 19. Worst Case Write-to-Read Transition Timing Waveform
CK#
CK
tCKDK
(maximum)
(1)
tCKQK
(minimum)
QK× (minimum)
DKx# (maximum)
DK× (maximum)
DQ
(2)
(2)
(2)
(2)
D1a
D1b
Q2a
Q2b
tQKQ
(minimum)
90˚shift
(maximum)
(3)
Bus
transition
Notes to Figure 19:
(1)
(2)
(3)
Even though CK and DK are derived the same way, there may be skew either from
the board or from the external clock buffer.
The gray section shows when data is changing. The blue section shows that data is
valid.
The maximum 90º phase shift accounts for PLL output skew, I/O output skew,
offset error from the external clock buffer, and board trace length mismatch.
As shown in Figure 19, when you use the maximum FPGA timing delays,
the write data is shifted to the right. Figure 18 also shows that when you
use the minimum RLDRAM II timing delays, the read data is shifted to
the left. As a result, the bus transition period shrinks from the optimal
0.25 clock cycle maximum transition width. To determine whether a nooperation command needs to be inserted when switching from a read to
a write operation, you need to calculate the bus transition width of the
interface.
Using the same RLDRAM II and FPGA specification as in the “Read-toWrite Transition” section as an example, you can calculate whether you
need an extra no-operation when switching from a write to a read.
Altera Corporation
55
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Using CK as the reference clock, the write data is invalid after a time
period for Stratix devices interfacing with 200-MHz RLDRAM II devices,
as calculated below:
tCLKBUFSKEW + tCLKBUFJITTER + tCLKBUFDCD + tIOSKEW + tPLLSKEW + tEXT +
burst length × maximum data width = 0.1 ns + 0.125 ns + 0.1 ns +
0.150 ns + 0.160 ns + 0.02 ns + (2 × 1.1 x 0.55 × 5 ns)= 6.705 ns
To determine how long after the first CK edge the invalid time occurs,
divide the time period from the previous equation by the clock period.
6.735 ns/5 ns per clock cycle = 1.347 clock cycles
This means that read data can be valid 0.347 clock cycles later than when
it is supposed to end. This already exceeds the ideal 0.25 clock cycles bus
transition period so you need to add one no-operation command every
time you switch from a write to a read.
Similarly, the calculation for Stratix II devices interfacing with 300-MHz
RLDRAM II devices would be as follows:
tCLOCK_SKEW_ADDER + tPLL_PSERR + Quartus reported I/O skew +
Quartus reported clock skew + tEXT + tDCD = 0.050 ns + 0.030 ns +
0.073 ns + 0.00 ns + 0.020 ns + 0.167 + (2 × 1.1 × 0.55 × 3.33 ns) =
4.369 ns
This means data can be valid 0.312 clock cycles later (4.369/4.369 – 1 clock
cycle) than when it is supposed to end. You also need an extra nooperation command here as it exceeds the 0.25 clock cycle bus transition
period.
1
56
The same parameters mentioned in the “Read-to-Write
Transition” on page 51 section for Stratix II are also applicable
here.
Altera Corporation
Interface Timing Analysis
Round Trip Delay Calculation
Read data is captured into the DDR registers using the QK signal as a
clock. Therefore, data must be transferred from the QK clock domain to
the system clock domain (resynchronization), to present data from the
input registers synchronously at the local-side interface. To determine the
point at which the data can be reliably resynchronized, calculate the
minimum and maximum round trip delay. You can then determine what
resynchronization logic to use for your system.
This timing analysis applies for RLDRAM II interface with Stratix and
Stratix GX devices. In the RLDRAM II interface with Stratix II devices,
QVLD signal is used with a dual-clock FIFO for resynchronization and its
timing is analyzed by the Quartus II software.
Figure 20 shows the round trip delay for Stratix and Stratix GX devices.
Figure 20 shows the path from the FPGA clock to the RLDRAM II and
back to the Stratix or Stratix GX device (input to register B). This analysis
is required to reliably transfer data from register A (in the IOE) to register
B (in the LE). You can also use the shifted DQS signals for
resynchronization, but this method is not discussed in this application
note.
Altera Corporation
57
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Figure 20. RLDRAM II Round Trip Delay Illustration in Stratix & Stratix GX Devices
Note (1)
dqs_ref_clk (2)
FPGA
RLDRAM II
DQS Phase
Shift
Circuit
Write
PLL
(8)
clock_source
tPD (Clock Trace)
tPD (clk_ext to pin)
e1
D
(D)
Q
FPGA CLK
clk (4)
c0
(C)
(B)
clk_shifted (3)
c1
FB_CLK
CK
External
Clock
Buffer
tCKDK
(A)
(F')
DK
Read
PLL
(8)
c0
tPD (Clock Trace)
D
(5)
tPD (Routing)
D
(J)
data_out
Q
D
B
tPD (Routing)
tSU (Resynchronization)
tH (Resynchronization)
Address/
Command Pins
Q
DQ (6)
(I)
Q
(J')
tCKQK
Q
Q or DQ
D
(7)
A
(H)
tCQ (Capture)
QK
QK
(G)
DQS
Logic Block
(E)
(F)
tPD (DQS Trace)
tPD (Capture)
Notes to Figure 20:
(1)
(2)
(3)
(8)
The nodes for the round trip delay analysis are marked with letters (A) through (I).
The dqs_ref_clk input for Stratix and Stratix GX devices must come from an input clock pin.
The clk_shifted signal is shown for completeness, but it is not needed in the timing analysis for round-trip delay
or address/command timing.
clk is the system clock.
You can clock the address/command register with either a rising edge or falling edge of the clk signal.
You can either connect the RLDRAM II CIO DQ pins to the Stratix or Stratix GX DQ pins or connect the RLDRAM II
SIO Q pins to the Stratix or Stratix GX DQ pins.
The DQS phase-shift reference circuit controls the phase shift on the DQS signal dynamically. The control path is not
shown and its operation is user transparent.
This PLL is in normal mode.
58
Altera Corporation
(4)
(5)
(6)
(7)
Interface Timing Analysis
Register A in Figure 20 represents the DDR capture logic. The Q output
from register A represents the point at which the read data has been
converted from DDR to single data rate (SDR). At the output of register
A, the data is already at single data rate, but is still in the QK clock
domain. DQH (DQ data during QK high) is sampled on the positive edge
of the phase-shifted QK pulse, but re-sampled on the negative edge of the
phase-shifted QK pulse, to align it with DQL (DQ data during DQS low).
Once sampled by the negative edge of the phase-shifted QK signal, DQL
and DQH are available for resynchronization. To sample the Q output of
register A into register B, you need the time relationship between register
B’s clock input and the D input. This time relationship depends on the
phase relationship between QK and clock and involves the following
steps:
1.
Calculate the system’s round-trip delay (described below).
2.
Select a resynchronization phase of the system clock or other
available clock that reliably samples the Q output of register A,
based on the calculated safe resynchronization window.
3.
Apply the correct clock edge for the resynchronization logic in the
memory controller.
The feedback clock and the read PLL shown in Figure 20 improve the
resynchronization process. This feedback clock is from the external clock
buffer that is also used to provide CK, CK#, DK, and DK# signals to the
RLDRAM II devices.
The read PLL needs to be in normal mode such that its output is in phase
with the input to the PLL (if there is no phase-shifting). The PLL input is
skewed by the RLDRAM II ± tCKQK value plus any board trace skew
between QK or CK and the FB_CLK traces. The PLL can then be used to
compensate for the delay between IOE register to the LE register and be
used to synchronize the data from the QK clock domain to the feedback
clock domain.
The feedback clock lags the system clock by the board trace length for the
CK signal plus the board trace length for the QK signal delay. You can
calculate whether register outputs clocked by the feedback clock need
another resynchronization stage before getting to the system clock
domain.
To determine the data timing at the D input of register B relative to the
clock, you have to know when the following occur:
Altera Corporation
59
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
■
■
■
■
■
CK input clock arrives at the RLDRAM II memory
FB_CLK signal arrives at the clock input of the read PLL
Data arrives at the Q output of register A
Data arrives at the D input of register B
Clock arrives at the clock input of register B
There are two round trip delays to consider: one for the CK signal going
to the RLDRAM II devices and the QK signal coming back to the Stratix II
devices and another one for the FB_CLK signal.
You need the maximum and minimum values (taking into account PVT
variations) to calculate the following delays:
■
■
■
■
■
Clock-to-out delays for the CK signal from the FPGA
CK board trace lengths
The external clock buffer jitter and compensation error from the
external clock buffer
QK board trace lengths
Register to register delays between the registers in the feedback clock
domain and the registers in the system clock domain
For the FB_CLK signal round trip delay, you need the maximum and
minimum values (taking into account PVT variations) to calculate the
following delays:
■
■
■
■
Clock-to-out delays for the CK signal from the FPGA
Board trace lengths from the CK pin to the FB_CLK pin
The external clock buffer jitter and compensation error from the
external clock buffer
Delays from the FB_CLK input to input register B
To determine the point at which the data can be reliably resynchronized,
calculate the minimum and maximum round-trip delay, and then
determine what resynchronization logic to use for your system.
Remember to take into account PVT variations.
Delay (A) to (B) is the clock-to-out time to generate the clock signals to the
RLDRAM II device.
Delay (B) to (C) is the trace delay for the external clock buffer.
Delay (C) to (D) is the trace delay from the external clock buffer to the
RLDRAM II device. Since the clock is an external feedback clock buffer,
the signal going into the RLDRAM II device should be aligned with the
feedback clock going into the clock buffer. However, you should account
60
Altera Corporation
Interface Timing Analysis
for any trace length mismatch, the clock buffer jitter, and compensation in
the round trip delay calculation. The jitter and compensation error are
shown in Figure 20.
Delay (D) to (E) is the relationship between the clock and the QK clock
timing during reads. This is tCKQK in RLDRAM II specifications,
nominally 0, but typically varies by ±0.3 ns for 300 MHz RLDRAM II
devices. The QK output strobe is only guaranteed to be within ±tCKQK of
the clock input. So use tCKQK (maximum) for calculating the maximum
round trip delay; tCKQK (minimum) for calculating the minimum delay.
Delay (E) to (F) is the trace delay for QK, which typically matches the
trace delay for the Q or DQ signals in the same byte group. To calculate
the maximum round trip delay, use the byte group with the longest trace
lengths; for the minimum use the shortest. Trace lengths between
different byte groups do not have to be tightly matched, but a difference
between the longest and shortest decreases the safe resynchronization
window within which the data can be reliably resynchronized. PLL jitter
and clock duty cycle also affect the round trip delay. Add each of these
delays to the maximum value and subtract from the minimum. PLL jitter
and clock duty cycle are not shown in Figure 20.
Delay (F) to (G) is the 90° phase shift delay including the DLL jitter and
DLL phase shift error.
Delay (G) to (H) is the delay from the QK pin to the IOE register.
Delay (H) to (I) is the micro clock-to-out time for the IOE registers
Delay (I) to (J) is the delay from the IOE registers to the LE
resynchronization registers. To calculate the maximum round trip delay,
use the longest delay for the whole interface and use the shortest delay for
the whole interface for the minimum round trip delay.
Delay (B) to (F’) is the delay that mimics the CK trace length to the
RLDRAM II device and QK trace length back to the FPGA.
Delay (F’) to (J’) is the delay from the FB_CLK pin to the clock port of the
LE resynchronization registers. This delay includes the PLL
compensation delay.
Altera Corporation
61
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Board Design
Guidelines
This section provides general guidelines for board design when using the
Stratix II, Stratix, and Stratix GX devices to interface with RLDRAM II
devices. It also provides information about decoupling capacitance. The
following general guidelines apply when designing with Stratix II,
Stratix, and Stratix GX devices and RLDRAM II devices.
■
■
Keep the memory component and the Stratix II, Stratix, and
Stratix GX devices close together. The routing length between
Stratix II, Stratix, and Stratix GX devices and the memory component
should be within 4.5 inches. The total distance between the Stratix II
device to the VTT termination resistor must not exceed six inches
when routed as fly-by.
Pull-up resistors RT to VTT (0.90 V) are required for data, data strobe,
data mask, address, and control signals and should be located after
the end of the memory structure in a fly-by termination scheme.
Routing length to the pull-ups is less critical, but most designs
require 0.5 to 1 inch to route. Figure 21 shows this termination
scheme.
1
These termination instructions are guidelines only. The best
way to predict that the termination arrangement meets
your requirements is to simulate your design, including the
PCB and device packages.
Figure 21. Termination Scheme for RLDRAM II CIO Devices
VTT
RT = 56 Ω
Address
and Control
Signals
RS = 16 Ω
VTT
VTT
Memory Pin
RT = 50 Ω
Data Strobe,
Data Mask,
and Data Signals
(CIO Devices)
62
50 Ω
RT = 56 Ω
50 Ω
Altera Corporation
Board Design Guidelines
Figure 22. Termination Scheme for RLDRAM II SIO Devices
VTT
RT = 56 Ω
Address
and Control
Signals
RS = 16 Ω
50 Ω
VTT
DIMM Pin
RT = 56 Ω
Data Strobe,
Data Mask,
and Data Signals
■
■
■
■
■
Altera Corporation
50 Ω
Match routing for data byte-groups as closely as possible on the PCB.
For example, you should match the timing skews for data groups
(including data strobe and data mask signals) as closely as possible.
These should be 17 ps (0.1 inch). Altera also recommends matching
the timing skews of different data byte-groups. These should also be
17 ps (0.1 inch) to 85 ps (0.5 inch). To match the routing, take the
longest trace and match the rest of the signals with the longest trace.
Also, you should account for vias, which have electrical length, in all
trace balancing configurations. Proper routing topology is best
achieved when all point-to-point connections match not only in
physical length but also in electrical length.
Keep each clock trace segment length as short as possible. The total
length of a clock trace (all segments), including passive components,
should be less than three inches.
Series resistors in a clock network must be as close to the source as
possible.
Route clocks with differential pairs next to each other throughout the
trace length. The trace width should be five mils, and spacing
between the positive and negative traces should be five mils. Spacing
between these traces and other signals should be a minimum of
30 mils, and they should be matched in length.
Avoid routing signals across split planes. Altera recommends
controlling returns at high frequencies. Also, avoid routing memory
signals any closer than 0.025 inches from PCI or system clocks. Avoid
routing memory signals close to system reset signals to reduce
crosstalk.
63
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
■
■
■
■
■
When using resistor networks, Altera recommends confining the
address and control signals to separate physical packages from data
signals. To eliminate crosstalk within R-pack resistors, the address,
control, and data lines should not share R-pack series resistors. Use
series and pull-up resistors with 1 to 2% network tolerances.
The distance between the RLDRAM II device pin and the
termination resistor pack (to 0.90 V) less than 1.25 inches.
The lengths that all signals must travel should be within
±0.250 inches. The spacing between signal traces must be 5 mils for
parallel traces less than 0.5 inches long, 10 mils for parallel runs
between 0.5 and 1.0 inches, and 15 mils for parallel runs between 1.0
and 6.0 inches.
Maintain 25 mils of space between all RLDRAM II signal traces.
The spacing between RLDRAM II address lines must be 10 mils for
parallel traces less than 0.5 inches long, 15 mils for parallel runs
between 0.5 and 1.0 inches, and 20 mils for parallel runs between 1.0
and 6.0 inches.
Decoupling Capacitance
Traditional methods for providing decoupling involve placing capacitors
in locations that are convenient based on the routing of the board, and
applying some predetermined ratio of capacitors to driver pins.
However, the higher switching speeds of DDR make typical ratios less
useful. Perform careful planning and analysis to ensure that sufficient
decoupling is provided. The amount of capacitance on a board is usually
not the critical limiting factor in designing a decoupling system. Typically,
the amount of inductance in the capacitor leads and the vias attaching the
capacitors to the power and ground planes creates limitations. Altera
recommends using 0.1-µF capacitors in an 0603-sized package to provide
sufficient capacitance without adding too much inductance. Make VTT
voltage decoupling on the motherboard close to the parallel pull-up
resistors. Connect the decoupling capacitors between VTT and ground.
The Stratix II, Stratix, and Stratix GX memory interface board has a 0.1-µF
capacitor for every other VTT pin. The Stratix and Stratix GX memory
interface board also has 0.1- and 0.01-µF capacitors for every VDD and
VDDQ pin.
64
Altera Corporation
Stratix-Series Memory Board I
Stratix-Series
Memory Board I
Altera produces the Stratix II memory board I and Stratix memory
board I to demonstrate DDR SDRAM and RLDRAM II interfaces with the
Stratix-series device family. The Stratix II memory board I includes a
Stratix II EP2S60F1020C4 device interfacing with the following external
memory devices:
■
■
■
■
Altera Corporation
Four DDR SDRAM ×16 devices connected to the Stratix II side I/O
banks of banks 1 and 2. The boards will use one of the following
third-party memory devices: Micron MT46V16M16TG-5B, Infineon
HYB25D25616OBT-5A, or Samsung K4H561638F-TCCC.
One DDR SDRAM module connected to the Stratix II I/O banks 7
and 8. The boards will use one of the following third-party memory
devices: Micron MT9VDDT3272AG-40B, Infineon
HYS72D32300GU-5-B, or Samsung M381L3223ETM-CCC.
One RLDRAM-II SIO ×18 device connected to the Stratix II I/O
bank 3. The boards will use the Micron MT49H16M18CFM-2.5 thirdparty memory device.
Two RLDRAM-II CIO ×18 devices connected to the Stratix II I/O
bank 4 that support 400 MHz double data rate (DDR). The boards
will use one of the following third-party memory devices: Micron
MT49H16M18FM-2.5 or Infineon HYB18RL28818AC-2.5.
65
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Figure 23 shows the Stratix II memory board I. The Stratix memory
board I has the same components interfacing with a Stratix
EP1S40F1020C5 device.
Figure 23. Stratix II Memory Board I
The Stratix-series memory board I is powered by a a single DC input with
on-board regulators generating the other required lower voltages. In
addition to the on-board regulators, fuse-isolated banana jacks will be
provided for all unique voltages for characterization purposes. The
incoming DC voltage will be regulated down to 3.3 V and 1.2 V using a
dual switching power supply in order to efficiently support the fairly
large DC drop from the input to the output. All other board voltages are
generated from this 3.3-V rail. There are fuse sockets to isolate planes
from regulators to allow bench supplies to power these sections using
banana jacks. The following regulators are available on the Stratix
memory board:
66
Altera Corporation
Stratix-Series Memory Board I
■
■
■
■
Linear Technology LTC2901—Programmable supply monitor for
monitoring board voltages
National Semiconductor LP2996MR—DDR SDRAM and
RLDRAM II termination regulator for generating the termination
voltage (VTT) and reference voltage (VREF)
Linear Technology LTC1778EGN—Synchronous DC/DC controller
to generate 3.3-V outputs.
Micrel Semiconductor MIC29502BU—High-current low-dropout
regulator for generating the power for the memory devices and the
Stratix PLL.
The following regulators are available on the Stratix II memory board:
■
■
■
■
■
Altera Corporation
Linear Technology LTC3728—Dual-output regulator for generating
the Stratix II device’s VCCINT and 3.3-V outputs.
Micrel Semiconductor MIC29502BU—High-current low-dropout
regulator for generating the power for the memory devices and the
Stratix PLL.
National Semiconductor LP2996MR—DDR SDRAM and
RLDRAM II termination regulator for generating the termination
voltage (VTT) and reference voltage (VREF).
Micrel Semiconductor MIC94300—Low-voltage low-dropout
regulator for generating the Stratix II PLL power.
Linear Technology LTC1872B—Step-up DC/DC controller for
generating power for the fan circuit.
67
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Figure 24 shows the Stratix-series memory board I block diagram.
Figure 24. Stratix Series Memory Board I Block Diagram
RLDRAM II
CIO Devices
(1)
CE
Header
SRAM
Clock
Buffer (2)
CPLD
RLDRAM II
SIO Device
16
16
16
JTAG
32
MAC/
PHY
DDR SDRAM
Devices
(1)
1,020-Pin
FineLine BGA
Stratix-Series
Device
16-MB
Flash
Memory
72
RJ45
Clocks
DDR SDRAM DIMM
RS-232
Debug Header
Buttons
Switches
LEDs
Notes to Figure 24:
(1)
(2)
68
The Stratix series memory board I has multiple RLDRAM II CIO and DDR SDRAM devices.
The clock buffer is only required for Stratix and Stratix GX devices.
Altera Corporation
Conclusion
Figure 25 shows the address termination scheme between Stratix-series
and RLDRAM CIO devices for the shared address and control lines.
Figure 25. Address Termination Scheme between Stratix II & RLDRAM CIO
Devices in Stratix-Series Memory Board I
RLDRAM II
Device
50 Ω
VTT
Stratix
Device
50 Ω
16 Ω
50 Ω
56 Ω
50 Ω
RLDRAM II
Device
Conclusion
RLDRAM II devices bridge the performance gap between DDR SDRAM
and SRAM devices. With DRAM memory densities and SRAM-like low
latency, RLDRAM II is ideal for communications, imaging, and server
applications. The versatile memory interface in Stratix, Stratix GX and
Stratix II FPGA devices enables designers to quickly and easily interface
to RLDRAM II and take advantage of these enhanced features.
References
MT49H16M18, 288 CIO Reduced Latency RLDRAM II advance data sheet,
Micron Technology, Inc.
MT49H16M18C, 288 SIO Reduced Latency RLDRAM II advance data sheet,
Micron Technology, Inc.
Revision History
The information contained in version 3x.x of AN 325: Interfacing
RLDRAM II with Stratix II, Stratix & Stratix GX Devices supersedes
information published in previous versions.
The following changes were made to AN 325: Interfacing RLDRAM II with
Stratix II, Stratix & Stratix GX Devices version 3.x:
■
■
Altera Corporation
Introduction - updated
Interface Description
●
Block Diagram - updated
●
Interface Signals - updated text and table
●
Interface Architecture - updated
●
DLL-Based Data-Path Architecture - updated
●
PLL-Based Data-Path Architecture - added section and figure
●
Altera Memory Controller IP - updated and added figure
69
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Read Timing Margins for DLL-Based Implementation- added
figure
●
Memory Timing Parameters - updated
●
FPGA Timing Parameters - updated, added table and figure
●
Setup & Hold Margins Calculations - updated text and table
Read Timing Margins for PLL-Based Implementation - added section
Write Data Timing Margins - updated
●
FPGA Timing Parameters - updated
●
Setup & Hold Margins Calculations - updated table
●
Command and Address Timing - updated and added table
●
Bus Turnaround Timing Analysis/Read-to-Write - updated
●
Bus Turnaround Timing Analysis/Write-to-Read - updated
●
■
■
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
www.altera.com
Applications Hotline:
(800) 800-EPLD
Literature Services:
literature@altera.com
70
Copyright © 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company,
the stylized Altera logo, specific device designations, and all other words and logos that are identified as
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to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability
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