Toggle and Spin-Torque MRAM: Status and Outlook, by Jon Slaughter,, Everspin

Toggle and Spin-Torque MRAM: Status and Outlook, by Jon Slaughter,, Everspin
Preprint: J. Magnetic Society of Japan, v.5, p. 171 (2010)
Toggle and SpinSpin-Torque MRAM: Status and Outlook
J. M. Slaughter, N. D. Rizzo, F. B. Mancoff, R. Whig, K. Smith, S. Aggarwal and S. Tehrani
Everspin Technologies, Inc., 1300 N. Alma School Road, Chandler, Arizona 85224, USA
We review the development of MRAM technology at Everspin, focusing on both toggle MRAM, which is used in
our current commercial products, and spin-torque MRAM, which offers significant potential for cell size reduction
that could enable higher memory densities. Toggle MRAM uses magnetic fields for programming the bits with a
particular free layer structure, bit orientation, and write pulse sequence to avoid the half-select disturbs present in
other field-writing techniques. We find excellent read, write, and reliability performance with toggle MRAM and the
potential for continued scaling beyond our current 16Mb memory size. Next, we describe spin-torque MRAM, its
development challenges and expected performance attributes, and the results of our sub-100 nm spin-torque bits,
with both CoFeB and NiFe free layers, integrated into 16kb CMOS arrays. We measure an intrinsic array
separation between the spin-torque switching and breakdown voltage distributions >12σ for bits with a magnetic
stability against thermal disturbs Eb / kbT ≈ 52 sufficient for a 10 year data retention lifetime.
Key words: toggle MRAM, spin-torque MRAM, spin-transfer, magnetic tunnel junction, nonvolatile memory
1. Introduction*
Magnetoresistive random access memory (MRAM)
employs ferromagnetic storage devices integrated with
semiconductor circuitry to provide a nonvolatile random
access memory with fast read and write as well as
virtually unlimited read and write cycles. Each MRAM
bit contains a magnetic tunnel junction (MTJ) consisting
of two ferromagnetic layers separated by a thin (~ 1 nm)
insulating layer.
Data is stored in terms of the
magnetization direction of one of the ferromagnets (the
free layer) either parallel or antiparallel to the other (the
fixed layer). A tunnel magnetoresistance (MR) that is
low (high) for parallel (antiparallel) magnetizations
provides the read-out signal. The first MRAM product
used toggle-mode writing as a form of magnetic-field
induced switching and became commercially available in
2006 (the 4Mb Everspin Technologies MR2A16A, then
produced by Freescale Semiconductor). This part was
followed by a family of related parts, the most recent
being a 16Mb circuit. Spin-torque MRAM is currently
under development and uses electric current-induced
switching as an alternative writing scheme with
potentially higher density, lower power operation.
2. Toggle MRAM: Operation
Operation and attributes
A toggle-mode MRAM is shown by cross-section
transmission electron microscopy (TEM) in Figure 1(a).
The memory uses one transistor and one MTJ
(1T/1MTJ) for each bit cell. The transistor provides the
current flow through the MTJ needed for reading the
MR. Each MTJ is located at the intersection of two
orthogonal conductive lines, the bit line above the MTJ
and the digit line below it, which are energized to switch
the bit. The selected bit experiences magnetic fields
from both lines, whereas other bits along the energized
lines, called half-selected bits, experience only one of the
two fields. One of the fundamental problems of
field-switched MRAM is designing the bit and the field
pulses so that the selected bit always switches, and the
half-selected bits never switch.
Toggle MRAM avoids the half-select disturb problem
through the use of a switching mode, dubbed
“Savtchenko switching” after its late inventor1), which
employs a free layer synthetic antiferromagnet (SAF)
and a bit orientation rotated 45° with respect to the bit
and digit lines (as shown by top-down SEM in Figure
1(b)) combined with a specific current pulse sequence.
The selectivity using this mode is greatly enhanced
because a single current line pulse alone does not lower
the energy barrier to reversal, and even large single-line
fields cannot switch the bit. This unique behavior results
in a wide operating region with a threshold onset for
The programming pulse sequence and resulting
Bit cell
Bit line
Digit line
Fig. 1: (a) Cross-section TEM of the bit cell for
toggle MRAM, including
the MTJ, bit line, digit line,
and underlying CMOS circuitry. (b) Top-down SEM
of toggle MRAM MTJ bits and their underlying
bottom electrode.
H1 + H2
10 3
# bits
10 4
10 2
Fig. 2: Schematic of a toggle MRAM bit with the
field sequence used to switch the free layer from one
state to the other. The fields H1, H1 + H2, and H2 are
produced by passing currents, i1 and i2, through the
write lines. (From B. N. Engel et al., IEEE Trans.
41 132 (2005). © 2005 IEEE).
Magn. 41,
magnetic behavior are depicted in Figure 2. The black
and white arrows represent the magnetic moment of the
two sublayers in the SAF free layer, where the white
represents the layer that is in contact with the tunnel
barrier. To toggle the bit from an initial “0” to a final “1”,
the currents i1 and i2 are pulsed with the phase
relationship shown in the figure such that the vector
sum of the two magnetic fields begins 45° from the easy
axis and then effectively rotates through 90°. The SAF
responds by orienting nominally orthogonal to this field
and rotating with it such that when i2 is turned off, the
moments relax to their easy-axis with each oriented 180º
from its initial state. Because the MR only depends on
the direction of the layer that is in contact with the
tunnel barrier (white), the resistance has switched from
the low to the high state, i.e., from “0” to “1”.
Since the two magnetic sublayers are identical, if the
process is repeated with the same polarity pulses, the
free layer will reverse again in the same manner.
Because the same pulse sequence makes the bit
alternate between the “0” and “1” state, it is said to
toggle between the two states. This toggle-write mode
requires that the memory operates with a decision write
scheme, where the bit state is read first and only toggled
if the new data differ from the existing. This approach
has benefits in limiting the overall power consumption,
and the unipolar current allows the use of smaller
transistors, thereby improving array efficiency.
If only a single-line current is applied (half-selected
bits), the 45º field angle cannot switch the state. In fact,
the single-line field raises the switching energy barrier
of those bits so that they are stabilized against reversal
during the field pulse. This is in marked contrast to the
conventional field-switching approach, where all of the
half-selected bits have their switching energy reduced
and are, therefore, more susceptible to disturbance. The
phase relationship of the pulses is, therefore, required
for switching resulting in significantly improved bit
selectivity in an array.
3. Toggle
write, and
Bit resistance (kΩ)
Fig. 3: Low- and high-state resistance distributions
measured at operating bias and with series
transistor resistance. Data are from a 64kb sample
of a 4Mb device. (From B. N. Engel et al., IEEE
Trans. Magn. 41,
41 132 (2005). © 2005 IEEE).
Proper uniformity control of both the MTJ MR and
the resistance-area product (RA) is important for
functional read-out from a memory array.
exponential thickness dependence of RA on the very thin
barrier creates a challenge for producing MTJ material
that is repeatable and uniform over the 200 mm
diameter wafers used in production. However, 1σ
resistance uniformity of 5% and MR uniformity of 1%
over 200 mm wafers have been achieved3). These
submicron patterned bits have average values of MR =
45% and RA = 10.2 kΩ−µm2. The metal layers were
formed by sputter deposition, and an oxygen plasma was
used to oxidize a thin Al layer to form the AlOx tunnel
barrier. This uniformity is achieved through a deposition
process with a 1σ Al thickness uniformity of 0.5%. The
AlOx tunnel barrier can be engineered by optimizing the
Al thickness and oxidation time to have MR = 40% - 50%
for the range of RA > 200 Ω−µm2 4).
A number of factors can contribute to the resistance
distribution. Bit area variations, e.g., owing to
lithography or etch variations, will directly cause
variations in bit resistance. Process damage or veils
created during the etch process also may contribute.
However, we have found that with an optimized
patterning process, the quality of the MTJ material
itself plays a major role in determining the resistance
Figure 3 shows measured array
distributions for a 4Mb circuit, with MTJ material
optimized for MRAM, having 23σ separation between
the mean high and low resistances5), significantly
greater than the targeted 12σ for functionality. The
main factors that led to this result were the high-quality
patterning process to minimize area variation and
optimized MTJ materials and processes to make the
tunnel barrier more uniform.
For the write performance of a 4Mb toggle MRAM,
the large operating region is seen in Figure 4. Within
i bit
Resistance [Ω]
T=175 C
Time [s]
0% switching region
Fig. 4: Switching map for a 4Mb toggle MRAM
array. (From B. N. Engel et al., IEEE Trans. Magn.
41 132 (2005). © 2005 IEEE).
the operating region, 100% of the bits are successfully
written by the combined bit and digit line fields.
Outside the operating region at lower fields, 0% of the
bits are written, thus avoiding half-select disturbs. A
narrow but finite transition width between the two
regions is apparent due to the variation of the switching
field for different bits in the array. Nevertheless, the
operating region is greatly increased compared to the
much narrower operating point of conventional
field-switched MRAM that results from the distribution
of switching fields and the related half-select disturbs.
For product reliability, the two MTJ barrier failure
modes that must be controlled are time-dependent
dielectric breakdown (TDDB) and resistance drift.
Dielectric breakdown is detected as an abrupt increase
of junction current owing to a short forming through the
tunneling barrier. Resistance drift is a gradual reduction
of the junction resistance over time that can eventually
lead to reduced read margin and increased error rate.
The amount of drift that can be tolerated is determined
by a combination of the MR, the original resistance
distribution and the capability of the read-out circuit to
handle small signals. Both failure modes are strongly
accelerated by voltage bias and temperature (Figure 5).
Their effect on lifetime at operating conditions can be
deduced using stress testing methods6). In addition, the
resistance drift was found to have a strong favorable
frequency dependence7), greatly increasing the lifetime
at the operating frequency of the part. Rigorous
reliability analysis done for the Everspin 4Mb MRAM
product has shown that both lifetimes far exceed the
reliability requirements of industrial and automotive
Scalability is also crucial for continued MRAM
competitiveness. Write scalability is influenced by the
increased switching field caused by a decreasing bit area
and the increasing free layer thickness needed to
Fig. 5: Time-dependent dielectric breakdown (TDDB)
and resistance drift failure modes accelerated by
voltage bias (0.6 V solid line, 0.8 V dash-dot line, 1 V
dashed line) and temperature (175°C).
maintain 10 year stability against thermal disturbs.
However, as the feature size scales, the bit line and digit
line widths decrease as well as the interlayer dielectric
spacing between them and the bit. Thus, the field
experienced by the bit can increase along with the
switching field, while sufficient thermal stability is
generated for operation down to the 45 nm node. In
addition, the mean switching field at these nodes may be
decreased by alternative toggle configurations10)-11).
For scaling the read performance, the higher MR
available with MgO compared to AlOx can enable faster
read and help overcome the increasing resistance
variability inherent in scaling interconnects and devices
to smaller sizes, as demonstrated in an MRAM array
using MgO integrated with 90 nm CMOS in an 8kb
4. SpinOperation
Spin-torque MRAM:
Operation and expected
The spin-torque effect13)-14) is a result of conservation
of angular momentum in layered magnetic devices (for
an excellent review15)-17)). Electrons flowing through
the device acquire a spin polarization from a first layer,
referred to as the fixed layer, which then exerts a
spin-torque on a second layer, the free layer. At large
current densities (~106 - 107 A/cm2), the spin-torque can
cause the free layer to reverse its magnetization,
forming the basis for writing bits in spin-torque MRAM
(ST-MRAM). For ST-MRAM, the simplest free layer
consists of a single ferromagnetic layer, as opposed to
the SAF used for toggle MRAM. Spin torque switching
has been observed in MTJ’s18)-19) and is under
examination at a number of industrial companies for the
purpose of programming MRAM bits20)-29). The critical
current density for spin torque switching in zero field
can be shown to be approximately13):
Al bit line
to thermal fluctuations. The energy barrier to
magnetization reversal caused by thermal fluctuations
is Eb ∝ NdMs2A•t, where A is the bit area and Nd is the
effective demagnetizing factor of the free layer. For a
memory with a typical 10 year nonvolatility requirement,
where ћ is Planck’s constant, e is the electron charge, α
is the Gilbert damping constant of the free layer, Ms is
the saturation magnetization, t is the free layer
thickness, η is the spin torque efficiency, and Hk is the
intrinsic anisotropy of the free layer. For typical
spin-torque devices, 2πMs >> Hk.
Due to the simple cell structure, ST-MRAM has the
potential to reduce the MRAM cell size and thus extend
MRAM technology to higher memory densities. For
ST-MRAM, a single conductive line makes electrical
contact to the top of the bit, and a single pass transistor
beneath the bit is used for programming and reading.
The elimination of the digit line, used to write toggle
MRAM, will result in a smaller cell size if the pass
transistor can be made small enough. A typical logic
transistor can pass approximately 600 µA per µm of
transistor width, almost independent of technology node.
In general, the goal is to reduce the switching current Isw
so that a minimum-size transistor can be used at each
technology node, thus achieving the highest possible
memory density. For example, it would be desirable to
achieve Jsw ~ 1 MA/cm2 to enable Isw ~ 100 µA for a 90
nm wide bit. The decreasing spin torque write current
required for decreasing free layer volume is beneficial
for scaling the bit for future CMOS generations.
Further areas must be addressed to bring ST-MRAM
from development to production. The spin torque
switching current density Jsw needs to be significantly
reduced from the current state-of-the-art for two reasons.
First, the required switching current is directly
proportional to the size of the CMOS pass transistor
below the bit, so reduced Jsw is needed to reach the
desired high memory density for commercial production.
Second, low Jsw is needed to prevent tunnel barrier
damage or breakdown due to the write voltage bias
across the bit and to ensure memory reliability.
From Equation (1), one path to lower Jsw is to reduce
the free layer thickness t or magnetization Ms. This
path is limited for several reasons. First, t cannot be
than ≈ 2
t hinner
 2eαM st  (H k + 2πM s )
(1) t h e
n m o r J sw = 
magnetic properties of the film degrade. Second,
reducing Ms or t increases the likelihood of data loss due
MR (%)
Fig. 6: Cross-section TEM (a) and top down SEM (b)
images of MTJ’s for ST-MRAM in a short flow
Fig. 7: MR vs. RA for MTJ’s with an MgO barrier
2 layer
4 of either
8 or10
and a free
RA (Ω-µm 2)
Eb ≥ 50kbT, where kb is Boltzmann’s constant and T is
5. SpinSpin-torque MRAM: Device and array properties
We have fabricated MTJ’s designed for ST-MRAM
using a naturally oxidized MgO tunnel barrier, for which
a metallic Mg precursor layer is exposed to an O2
ambient, and a single free layer of either CoFeB or NiFe
(with composition close to Ni80Fe20). The MTJ bits are
patterned across 200 mm diameter Si wafers using
standard optical lithography followed by reactive ion
etching. Figure 6 shows examples of these MTJ’s as
integrated in a short-flow test vehicle, in which only the
MTJ layer itself and the top electrical contact line are
patterned in order to provide a rapid turnaround time
for fabrication. Figure 6(a) shows a cross-section TEM
image. The MTJ, with its brightly colored MgO tunnel
barrier, is sandwiched between top and bottom
electrodes. Figure 6(b) shows a top-down SEM view of
the MTJ’s following the reactive ion etch. The bit size
is roughly 0.09 µ m × 0.21 µm. We also fabricated
similar MTJ’s into 16kb sized arrays integrated with a
1T/1MTJ CMOS test vehicle.
Figure 7 shows the measured MR vs. RA for MTJ’s in
the short-flow process. Each data point in Figure 7
represents the median values over a single wafer, and
the variation in RA from 3 – 12 Ω−µm2 was produced by
varying the MgO barrier oxidation time for different
wafers. The dashed lines are guides to the eye. The
circles show data for a NiFe free layer, and the triangles
show data for a CoFeB free layer with a magnetization
close to the NiFe. The MR increases only slowly with
RA in this resistance range and reaches a value as high
as 78% for CoFeB and 65% for the NiFe. Even higher
MR up to 135% was also observed in the same RA range
for a somewhat higher magnetization CoFeB alloy.
According to Equation (1), the CoFeB might at first
be expected to show lower Jsw than NiFe due to its
higher MR and resulting large spin-torque efficiency η.
V (mV)
(b) 1
Pulse duration tp (ns)
Fig. 9: Switching voltage Vsw vs. pulse time tp for
NiFe and CoFeB free layer MTJ’s in the ST-MRAM
CMOS circuit.
• Data
– Fit
V (mV)
• Data
– Fit
Vsw (mV)
NiFe, Vsw increases monotonically as a function of
Time (ns)
Fig. 8: Voltage output signal vs. time from pulsed
inductive microwave magnetometer. The solid line
fit determines the magnetic damping parameter for
NiFe and CoFeB free layers.
However, another important consideration for Jsw in
Equation (1) is given by the magnetic damping
parameter α. We measured α in unpatterned free layer
films of NiFe and the CoFeB with comparable
magnetization by using a pulsed inductive microwave
magnetometer30), as shown in Figures 8(a) and 8(b)
respectively. In this measurement, an unpatterned
film of the free layer is exposed to a fast magnetic field
pulse generated by a coplanar waveguide, and the
subsequent ringing of the free layer magnetic moment in
response to the field is measured in the time domain
according to the voltage that the moment induces in the
waveguide. The dots in Figures 8(a) and 8(b) show the
measured voltage signal, and the solid black lines are
fits to the data using a Landau-Lifshitz-Gilbert form for
the magnetization ringing in response to a fast field
pulse. We can intuitively see that the damping is lower
for NiFe in Figure 8(b) since the ringing of its
magnetization persists for a longer time than for the
CoFeB. From the fits, we determine values of α ≈ 0.007
for NiFe and α ≈ 0.013 for CoFeB.
Based on this data from the unpatterned films and
the short flow MTJ’s, we integrated both the CoFeB and
NiFe free layers into CMOS arrays. Figure 9 shows
measurements of the voltage required for spin-torque
switching Vsw from antiparallel to parallel (AP → P) free
and fixed layer magnetizations as a function of the
voltage pulse time tp ranging from 20 ns up to 100 ms.
Data for CoFeB (NiFe) is given by the triangles (circles).
Each data point in Figure 9 represents the median Vsw at
a particular tp measured for all the CMOS arrays across
a single representative wafer. For both CoFeB and
decreasing tp, with two different regimes that cross over
at a pulse
 k bT  t p 
(2) 100
Vsw = Vsw
ln  
1 −
Eb  t 0 
t p,
For long
increases relatively slowly with decreasing tp and can be
well fit by the theoretical form from a thermal activation
represents the intrinsic switching voltage
extrapolated to a short time t0 = 1 ns. The black dashed
lines in Figure 9 give the fits to this form and match the
data well for tp > 100 ns. From the fits, we determine
Eb / kbT ≈ 52 for both CoFeB and NiFe, which is
sufficient to meet a 10 year thermal stability
requirement of Eb / kbT > 50. Also, we see that the
required switching voltage V0sw is lower for the NiFe free
layers than for the CoFeB, as determined by Equation
(1) using the MR and magnetic damping α measured in
Figs. 7-8, along with the other free layer parameters.
Finally, for tp < 100 ns, Vsw increased more rapidly as a
function of decreasing tp, as the spin-torque switching
transitioned from a thermally activated mode to a
magnetodynamical regime which requires increased Vsw
to drive the switching more rapidly. Vsw increases more
quickly with tp for NiFe in this range and begins to
converge with CoFeB.
For adequate electrical reliability of the ST-MRAM
tunnel barrier, a large separation of the switching
voltage Vsw distribution from the breakdown voltage Vbd
distribution is critical. The Vsw and Vbd distributions in
the AP → P bias direction for a CMOS array using a
CoFeB free layer are shown in Figure 10 at a pulse time
tp = 100 ns. The plot shows the probability for either
switching (diamonds) or breaking down (squares) the
many bits across the array as a function of the applied
voltage. The median switching voltage in the array
(given by 50% probability) is well separated from the
median breakdown voltage by roughly 700 mV in this
case. Fitting the data in Figure 10 to error functions,
we find relative standard deviations for the spin-torque
switching and breakdown distributions of σswrel ≈ 4% and
σbdrel ≈ 4%. Defining the separation of switching and
breakdown as S = (Vbd -Vsw)/(σsw + σbd)/2, we find S > 12σ
for this data (where σ is the average of the absolute
standard deviations σsw and σbd), as needed for a fully
> 12σ
Vapplied (mV)
Fig. 10: Spin-torque switching and breakdown
distributions for CoFeB free layers in the ST-MRAM
CMOS circuit.
functioning memory. This data provides an important
proof of concept for ST-MRAM reliability.
6. Conclusions
Toggle mode writing has enabled commercial
production at Everspin of a family of MRAM products, as
large as 16Mb so far, with excellent read, write, and
reliability performance.
Continued toggle MRAM
development will advance the technology to greater
memory sizes and a further expanded market. At the
same time, MRAM with spin-torque switching also is
under development and offers potential for higher
density MRAM circuits. We integrated arrays of MTJ
bits designed for spin-torque MRAM into a 16kb CMOS
test vehicle using both CoFeB and NiFe free layers,
demonstrating good separation (>12σ) between the
switching and breakdown distributions.
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Received Jan.
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