PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution Application Note

PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution Application Note
PD6729 — A PCI Motherboard PC
Card (PCMCIA) Controller
Solution
Application Note
May 2001
As of May 2001, this document replaces the Basis Communications Corp. document AN-PD7.
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Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
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The PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. Current characterized errata are available on request.
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Copyright © Intel Corporation, 2001
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Application Note
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
Contents
1.0
Introduction .................................................................................................................. 5
2.0
Overview ........................................................................................................................ 6
3.0
Hardware Description ............................................................................................... 7
3.1
3.2
3.3
3.4
3.5
4.0
Power-Saving Modes ..............................................................................................14
4.1
4.2
4.3
5.0
Memory Windows................................................................................................16
I/O Windows ........................................................................................................18
Timing Registers ......................................................................................................21
6.1
6.2
7.0
Automatic Low-Power Dynamic Mode ................................................................14
Suspend Mode ....................................................................................................14
Additional Notes on PC Card Subsystem Power Reduction ...............................15
Windows ......................................................................................................................16
5.1
5.2
6.0
PCI Bus Interface .................................................................................................. 7
3.1.1 Optional Pins ............................................................................................ 7
3.1.2 Optional Signals ....................................................................................... 8
PC Card Socket Interface...................................................................................... 9
PC Card Socket Power Control............................................................................. 9
Power Distribution ...............................................................................................10
Power Sequencing ..............................................................................................12
Setting the Timing Registers for SRAM Card Example.......................................22
Programming the Timing 1 Register Set .............................................................22
Appendix A .................................................................................................................26
7.1
PD6729 PCI Bus Demonstration Board PC Card Solution — Schematics .........26
1
2
3
4
5
6
7
ISA or PCI Interrupt Connections .......................................................................... 8
External Clock Connection ....................................................................................8
Block Diagram of Card-Socket Power Supply/Switching Circuit ........................... 9
PD6729 Powering of Internal Logic.....................................................................11
Typical Power Distribution for the PD6729..........................................................12
Power Plane ........................................................................................................13
Window Mapping Example of System Memory Address to
PC Card Socket Memory Address ......................................................................17
Window Mapping Example of System I/O Addresses
Without Offset to PC Card I/O Address...............................................................19
Setup, Command, and Recovery Timing Diagram..............................................22
Timing Diagram of Example SRAM Card Write Timing Setting ..........................24
Figures
8
9
10
Application Note
3
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
Tables
1
2
3
4
Programmable Timing Set 0 Default Setting....................................................... 21
Prescalar Values ................................................................................................. 23
Example of SRAM Card Write Timing Settings ................................................... 23
Application Note
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
1.0
Introduction
The PD6729 is a single-chip PCMCIA interface controller capable of controlling two PCMCIA or
compact Flash sockets, respectively. It is designed for use in embedded applications and notebook
systems where reduced form factor and low power consumption are critical design objectives.
Current typical application examples include:
■
Routers
■
Integrated access devices
■
Access network servers
■
DSLAMs
■
PBXs
■
Terminal servers
■
Vending machines
■
Point of Sale terminals
■
Portable handheld systems
■
Navigation systems
■
Data acquisition systems
■
Measurement equipment
■
Settop boxes
With the PD6729, a complete dual-socket PCMCIA solution with power-control circuitry can
occupy less than 2 square inches (13 square centimeters) of board space.
The PD6729 controller is completely compatible with the standards of PCMCIA (Personal Card
Memory International Association) Release 2.0 Standard as well as JEIDA (Japan Electronic
Industry Development Association) Version 4.1 Standard, and PCI 2.1. The PD6729 controller also
offers special power-saving features such as Automatic Low-power Dynamic Mode and Suspend
Mode. The PD6729 is a true mixed-voltage device that can operate at +5 volts, +3.3 volts, or a
combination of these at various interfaces. The controllers have full internal buffering and require
no additional circuitry to interface to the PCI Bus or to PCMCIA sockets.
Application Note
5
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
2.0
Overview
This application note provides information to help system designers interface the PD6729 to the
PCI bus. For information on how to design the PD6729 PC Card (PCMCIA) Controller in a nonIntel environment, contact an applications engineer.
This application note presents specific pin connection information for motherboard and PCI bus
solutions. The following PD6729 controller interfaces are detailed:
•
•
•
•
PCI bus interface
PC Card socket interface
PC Card socket power control signals
Power distribution pins
Section 3.0, “Hardware Description” on page 7 describes the PD6729 PCI bus and PC Card socket
interfaces with enough detail to permit a successful interface between the PCI bus and a PC Card
connector. The power-saving modes of the PD6729 are discussed in Section 4.0, “Power-Saving
Modes” on page 14.
Section 5.0, “Windows” on page 16 discusses PC Card address windowing basics, and Section 6.0,
“Timing Registers” on page 21 presents an example of how the timing register is set up for a
SRAM card.
“Appendix A” on page 26 presents schematics of a PD6729 PCI bus implementation, including the
power-control circuitry.
Note:
These sample circuits are provided for demonstration purposes only and do not represent the
minimum component count achievable in a motherboard solution.
An OrCAD 4.1 database of this implementation is available. Customers can modify this database
to meet the specific needs of their design.
6
Application Note
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
3.0
Hardware Description
This section describes the signals of the PCI bus interface, PC Card socket interface, PC Card
socket power control, and power distribution.
3.1
PCI Bus Interface
The PD6729 PCI bus interface signals are compliant with the PCI Specification Version 2.1, for
drive capability and can be directly connected to the PCI bus. The PD6729 PCI pins are given the
same as (or similar) conventional PCI bus signal names so that connections can be easily identified.
In the PCI architecture, there are four required signal groups: address and data, interface control,
error reporting, and system signals. Arbitration signals are only required if the device is master
capable (and the PD6729 is a slave device). The following section describes how to interface these
PCI pins to the PD6729.
• The following pins, with the exception of the Arbitration pins, are directly connected to the
PCI bus:
• Address and data pins: AD[31:0], C/BE[3:0], and PAR
• Interface control pins are directly connected to corresponding PCI bus signals: FRAME#,
TRDY#, IRDY#, STOP#, DEVSEL#, and IDSEL#
• System pins: CLK and RST#
• Error reporting pins: PERR# and SERR#
• Arbitration pins: REQ# and GNT# (not required because the PD6729 is a slave device)
3.1.1
Optional Pins
Interrupts
The PD6729 can be configured to support either PCI (active-low) or ISA (active-high) interrupts.
The configurable pins are: INTA#/IRQ3, INTB#/IRQ4, INTC#/IRQ5, and INTD#/IRQ7. In ISA
interrupt mode, the PD6729 can support an additional six ISA interrupts, for a total of ten.
Depending on the system design, the designer can elect to support either ISA or PCI interrupts.
One reason the ISA-interrupt scheme is more practical is that some software may not require
modification. Most software applications expect each specific device to use specific interrupts.
Take as an example, a modem configured to operate at COM2. The software application program
would expect a COM2 device to use IRQ3. The software program may provide another ISA
interrupt to be selected instead of IRQ3, but typically the selection of a PCI interrupt is not
allowed. Figure 1 illustrates the PCI and ISA interrupt schemes.
Application Note
7
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
Figure 1. ISA or PCI Interrupt Connections
ISA IRQ[XX]
PD6729
PD6729
OR
INT[A–D]
PIC OR ISA IRQ
PCI BUS
The PCI_CLK signal from the PD6729 is directly connected to the system clock, which provides
the timing for the transaction that occurs on the bus.
The PCI Specification Version 2.1 states that the clock can operate in a range from 0–33 MHz and
that, when bus transactions are complete, the system could stop the clock. This may pose a problem
for the PD6729 controller because the PD6729 incorporates a write FIFO. Data can be stored in
this FIFO when the system determines to stop the clock.
To incorporate this functionality, implement one of the following steps:
1. Ensure that all PD6729 operations complete before stopping the system clock (check the
FIFO status to ensure that it is empty).
2. Add an external clock for when the system stops the PCI clock.
When the system clock is stopped, the PD6729 has the capability to finish FIFO cycles with an
external clock. The multiplex pin, IRQ14/EXT_CLK, can be configured as either an interrupt or
an external clock input. When configured as an external clock, this input to the PD6729 uses the
external clock to provide the internal timing to finish transactions to the PC Card socket when the
system clock is stopped. This configuration is diagrammed in Figure 2.
Figure 2. External Clock Connection
EXTERNAL
OSC
PD6729
IRQ14/EXT_CLK
PCI_CLK
3.1.2
Optional Signals
The PD6729 provides additional signals that a system designer can elect to implement in the
system design. These signals are described below.
The IRQ[15,14,12:10] signals are ISA interrupts that indicate either Management or General
Control interrupts. These interrupt lines are an alternative method to service interrupts generated by
the host or card, but not through normal PCI interrupt requests.
SPKR_OUT* functions as an output to drive a speaker. On the PD6729, the output of
SPKR_OUT* is the logical XNOR of the speaker inputs from each socket interface. In this mode,
SPKR_OUT* can be used as an amplifier input to drive a speaker.
8
Application Note
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
LED_OUT* functions as an open-drain driver to show when there is activity to/from the PC Card
sockets.
3.2
PC Card Socket Interface
The PD6729 host controller has a fully buffered PC Card socket interface. There is no need for
additional socket buffering. All socket interface signals can be directly connected to the PC Card
connector.
3.3
PC Card Socket Power Control
The PD6729 power-control signals control the PC Card socket power circuits. The signals enable
the power from the PC Card socket power source to the socket VCC (the power to the card) and
VPP (the programming and peripheral voltage) power pins. A description of these signals and how
they are used is discussed in this section. Figure 3 is a block diagram of the VCC and VPP signals.
Figure 3. Block Diagram of Card-Socket Power Supply/Switching Circuit
CONTROL
SIGNALS
FROM
PD6729



VPP_PGM
VPP_VCC
−VCC_3
−VCC_5
SOCKET VPP
SWITCHING OR GENERATION
CIRCUITRY
VPP
SOCKET VCC
SWITCHING OR GENERATION
CIRCUITRY
SOCKET_VCC
−VCC_3 and −VCC_5
The PD6729 −VCC_3 and −VCC_5 control signals enable the power-switching circuitry that
selects the power source applied to VCC pins 17 and 51 of each PC Card socket. Both -VCC_3 and
-VCC_5 are active-low signals, mutually exclusive of each other. The Miscellaneous Control 1
(Index 16h) and the Power Control (Index 2h) registers control -VCC_3 and -VCC_5. (See the
PD6729 Data Sheet for more information about registers and register function.) A low on -VCC_3
causes the PC Card socket power-supply circuit to provide +3.3 volts to the card socket VCC pins
17 and 51; a low on -VCC_5 enables +5 volts to be provided to card socket VCC pins 17 and 51.
When both −VCC_3 and −VCC_5 on the socket interface are inactive (high), the PC Card power
supply disconnects power sources from the card socket VCC pins. Unlike other PC Card host
controllers, there is no need to clamp a card socket VCC pins to ground when both −VCC_3 and −
VCC_5 are inactive (high); special interface circuitry in the PD6729 prevents card damage in this
situation.
Application Note
9
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
VPP_VCC and VPP_PGM
The PD6729 card socket interface VPP_VCC and VPP_PGM signals control the voltage level to
the VPP pins at the associated PC Card socket. To be PC Card-compatible and function with both
memory and I/O cards, the VPP switching/generation circuitry should be able to supply 0 volts, the
selected card VCC voltage of +3.3 or +5 volts, and +12 volts to the card socket VPP pins. Both the
VPP_VCC and VPP_PGM signals are active-high signals, mutually exclusive of each other. A
high on VPP_VCC enables the PC Card socket VPP switching/generation circuit to provide the
card socket current VCC voltage (as determined by the −VCC_3 and −VCC_5 control signals) to
the card socket pins 18 and 52; a high on VPP_PGM enables +12 volts to be provided to card
socket pins 18 and 52.
The PCMCIA Standard requires that a card socket VPP supply pins be logic ‘0’ when programming
voltages are not being applied. To accomplish this select a VPP switching or generation circuit that
forces the VPP output to 0 volts when the card socket interface VPP_VCC and VPP_PGM signals
are inactive (low). Alternatively, a bleed resistor can be placed from the card socket VPP pins to
ground, although this method may create unwanted power consumption for power-sensitive
applications.
The schematics in Appendix A show a sample design on implementing the power-control supply
logic for VCC and VPP to the PC Card socket in a system where +12 volts is already available.
VS1 and VS2
The PD6729 host controller provides two voltage sense pins per socket, VS1 and VS2. These pins
determine the card voltage level. The state of these pins is stored in the PD6729 internal registers
and used by software to determine the voltage level applied to the card. No external resistors are
required for the board design; these pins are internally pulled-up by the PD6729 host controller. If
VS1 and VS2 are the voltage selects, the pins are connected as follows: VS1 directly connects to
pin 43 of the PC Card socket; VS2 directly connects to pin 57 of the PC Card socket.
For further explantation of the VS1 and VS2 levels, refer to the PC Card Standard Specification.
3.4
Power Distribution
The PD6729 has four types of power-distribution pins that provide power to various parts of the
circuitry (Figure 4). These power-distribution pins are the PCI_VCC, CORE_VDD, and
SOCKET_VCC power pins, and the +5V power pin.
Having separate types of power pins allows the PD6729 to be used in a wide variety of applications
where PC Card voltages are dynamically changing between +3.3 and +5 volts or are powered on
and off.
10
Application Note
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
Figure 4. PD6729 Powering of Internal Logic
PCI_VCC CORE_VDD
+5V
SOCKET_VCC
SIGNAL PROTECTION
CIRCUITRY
CORE
CIRCUITRY
PCI BUS INTERFACE
CIRCUITRY
PC CARD SOCKET
INTERFACE CIRCUITRY
PCI_VCC
The PCI_VCC power pins power the PCI bus interface circuitry. Connect the PCI_VCC power
pins to the same power source that drives other PCI bus signals. When PCI_VCC is at +3.3 volts,
the PCI bus interface signals operate at +3.3 volts. When PCI_VCC is at +5 volts, the PCI-businterface signals operate at +5 volts.
CORE_VDD
The CORE_VDD power pins supply power to the main core circuitry of the PD6729. Since
CORE_VDD can be set at +3.3 or +5 volts independent of the operating voltage at the PCI bus or
card socket interfaces, set CORE_VDD to +3.3 volts to reduce system power consumption. If there
is no +3.3-volt supply available in the system, a regulator or diode circuit can step-down the VDD
voltage for power saving. The PD6729 PCI signals are CMOS, and the voltage applied to
CORE_VDD determines the threshold levels to the PCI bus signals. If TTL threshold levels are
required on the system PCI bus, the CORE_VDD (core voltage) is set to +3.3 volts. This makes the
CMOS threshold level equivalent to TTL threshold levels.
SOCKET_VCC
The SOCKET_VCC power pins supply power to the socket-interface pins and should be powered
from the same card power circuit output routed to the corresponding socket VCC pins. This allows
the respective socket interface signals to operate at the same voltage as the card operating voltage.
The PD6729 has two separate socket interfaces, each SOCKET_VCC pin can operate independent
of the other socket interface. This prevents signal mismatch problems when, for example, a card in
socket A is operating at +5 volts while a card in socket B is operating at +3.3 volts or is powered
off.
Application Note
11
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
+5V
The power pin labeled +5V must be connected to the system +5-volt power supply. While the
system +5-volt supply is not always powered on, the +5V pin must be connected to a supply where
the voltage is at the same or higher than any of the voltages provided to the PD6729 other power
pins.
Caution:
If the other supply voltages (PCI_VCC, CORE_VDD, or SOCKET_VCC) are raised more than
+0.5 volts above the voltage applied to the +5V pin, latch-up and/or damage to the PD6729 may
result. Connect the PD6729 power pins as previously described to prevent any potential
problematic situations. However, carefully analyze each design for the possibility of latch-up
conditions.
Figure 5 is a block diagram of the host and socket interfaces.
Figure 5. Typical Power Distribution for the PD6729
+12 V
+5 V
CONNECT TO
PCI BUS VCC SUPPLY
+3.3 OR +5 VOLTS
+3.3- OR +5-V
+3.3 V
CARD SOCKET
POWER SWITCHING
OR SUPPLY
CIRCUIT
(1 PER SOCKET)
SOCKET_VPP
SUPPLY
CORE_VDD
CARD SOCKET
PCI_VCC
VPP1
+5V
VPP2
−VCC_3
PC CARD
−VCC_5
PD6729
VPP_VCC
VPP_PGM
VS1
VS2
SOCKET_VCC
VCC PINS
SOCKET_VCC
VS1
3.5
VS2
Power Sequencing
The correct power sequencing of the +5V, CORE_VDD, and PCI_VCC lines ensures that the +5V
line is not more than 300 mV below any of the other pins on the device. This means that as the
voltage supplies ramp-up, the +5V line should start concurrent to or before the other power
supplies and ramp with or faster than the other power supplies. There is no timing requirement for
this level difference so it is not necessary to bring the +5V line up and hold it for a length of time
12
Application Note
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
and then apply the other power supplies. Instead, the +5V line must stay at or ahead of (or a
maximum of 300 mV behind) the other power supplies. Figure 6 is an example of the PD6729
power plane.
Note:
All signals input and output must not exceed +0.5 V above the voltage applied to the +5V pin.
Figure 6. Power Plane
+5 VOLTS
+5 V
CORE_VDD, PCI_VCC
+3.3 V
0V
Application Note
13
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
4.0
Power-Saving Modes
In addition to the normal operating mode, which consumes very little power, the PD6729 supports
two power-saving modes to further reduce power consumption of the PC Card (PCMCIA)
Controller. Refer to the PD6729 Data Sheet for a full description of power-management features.
4.1
Automatic Low-Power Dynamic Mode
The Automatic Low-Power Dynamic mode is transparent to normal system operation and is
enabled after chip reset by default. After reset, the host is configured for Automatic Low-Power
Dynamic mode. This mode can be turned off by a write of ‘0’ to bit 1 of Miscellaneous Control 2
register (Index 1Eh). When system is inactive in Automatic Low-Power Dynamic mode, the
internal clock is turned off to most of the device, and the PC Card address lines are held at static
values; the socket VCC and VPP power control signals are not affected. Once activity occurs at the
card socket (for example, -INTR activation or status pins change) or PCI bus cycles occur to either
valid card addresses or in the PD6729 registers, the PD6729 restarts the internal clock. When PCI
bus cycles stop accessing valid card address windows or the PD6729 internal registers, the PD6729
automatically stops the internal clocks again and holds the card socket interface outputs static.
Shown below is an example of a code segment that enable Automatic Low-Power Dynamic mode.
#define
#define
#define
#define
67xxbase
67xxindex
67xxdata
miscntrl2
0xXXX
// XXX is value of configuration index 10h
67xxbase
67xxindex + 1
0x1e
// code fragment
outp (67xxindex, miscntrl2);
x = inp (67xxdata);
x |= 0x2;
outp (67xxdata, x);
4.2
Suspend Mode
When no card or device accesses are requested, Suspend mode increases power savings. The
PD6729 is put into Suspend mode by a write of ‘1’ to bit 2 of the Misc Control 2 register (Index
1Eh). In Suspend mode, the internal synthesizer and all internal clocks are turned off. The VCC and
VPP power control pins to each card socket power-switching/supply chip set are left unchanged
(the system power-management software must suspend power to the card socket before Suspend
mode is initiated). When in Suspend mode, card socket status changes and card interrupts are still
detected and system interrupts are still generated.
To power up from Suspend mode, set bit 2 of the Misc Control 2 register to ‘0’.
Shown below is an example of a code segment that enable Suspend mode
#define
#define
#define
#define
14
67xxbase
67xxindex
67xxdata
miscntrl2
0xXXX
// XXX is value of configuration index 10h
67xxbase
67xxindex + 1
0x1e
Application Note
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
// code fragment
outp (67xxindex, miscntrl2);
x = inp (67xxdata);
x |= 0x4;
outp (67xxdata, x);
.
4.3
Additional Notes on PC Card Subsystem Power Reduction
The PD6729 strictly controls power consumption during power-saving modes. The following
measures can further minimize power consumption at the system level of the entire PC Card
subsystem (including the PC Card power-switching/supply circuit and card).
1. Controlling power to the cards (Power Control register bits 5:0)
2. Enabling and disabling card interfaces (Power Control register bit 7)
3. External shut down of clock sources to the PD6729
Application Note
15
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
5.0
Windows
The PD6729 provides both memory and I/O windows, allowing access to address regions suitable
for use with PC Card memory and I/O cards. These address translation features are organized as
five independent memory windows per socket, and two independent I/O windows per socket.
Typical memory and I/O windows are configured using PC Card- and socket-service software or
setup utilities provided by the card vendor.
5.1
Memory Windows
The PD6729 is configurable for up to five memory windows. These windows are accessed through
the socket service software. The following is a typical example of how a window is defined and
accessed.
Memory window sizes can be programmed on 4-Kbyte increment boundaries. Offsets for these
windows are provided so that the actual PC Card access address is different than the system PCI
bus address. For example, assume it is necessary to access a memory card in the PC Card socket.
The memory card has accessible memory at PC Card addresses 0–0FFFF (64 Kbytes). A memory
window could be specified in the computer space to start at 0D0000 (0D000:0000) and continue
through 0DFFFF (0D000:FFFF). This allocates the memory space in the host (assuming it was not
being used by the computer) to the PC Card (PCMCIA) Controller. To program the PC Card socket
memory addresses to start at location 0000000h for PCI-bus-memory addresses starting at 0D0000
(0D0000:0000), an offset needs to be computed so that the PCI bus memory address, plus the
window memory-mapped offset, equals the PC Card address (0000000h). To accomplish this, take
the two’s complement of D0000 (0D000:0000) to create the desired negative offset.
Note:
The 4-Kbyte increment window resolution causes A[11:0] to map directly.
This computed offset value is then programmed into the selected window Memory-Mapped
Address Offset High and Memory-Mapped Address Offset Low registers. PCI bus memory
accesses are then at address 0D0000 (0D000:0000) (for example) to occur at PC Card address 0,
and so on through the PCI bus memory map up to 0DFFFF (0D000:FFFF). Figure 7 demonstrates
how the mapping is accomplished.
16
Application Note
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
Figure 7. Window Mapping Example of System Memory Address to
PC Card Socket Memory Address
SYSTEM MEMORY
ADDRESS SPACE
PC CARD SOCKET MEMORY
ADDRESS SPACE
3FF FFFFH = 64M
SYSTEM MEMORY WINDOW:
MEMORY MAP END ADDRESS
0DFFFF0 (D000:FFFF)
MEMORY MAP START ADDRESS
0D0000 (D000:0000)
RESULTING PC CARD
SOCKET MEMORY WINDOW:
MAPPING
END ADDRESS
000 FFFFH
START ADDRESS
000 0000H
MEMORY MAP ADDRESS
OFFSET = 3F30XXXH
= −00D0000H
(TWO’S COMPLEMENT WHEN NEGATIVE OFFSET)
Below is a code segment (related to the example in Figure 7) to program the PD6729 socket
interface Memory Window 0 as a 1-Mbyte window with a starting system address at location
0D0000 (D000:0000h), and a negative offset to create a 1-Mbyte socket memory window starting
at PC Card address 000 0000h:
#define
#define
#define
#define
67xxbase
67xxindex
67xxdata
miscntrl2
0xXXX
// XXX is value of configuration index 10h
67xxbase
67xxindex + 1
0x1e
// code fragment
// Set socket power to Auto-power on when card is installed
Application Note
17
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
outp (67xxindex, 0x02);
outp (67xxdata, 0xb0);
// Disable memory window 0 during memory map window programming
outp (67xxindex, 0x06);
x = inp(67xxdata);
x &= 0xfe;
outp (67data, x);
// Program Memory Map 0 Start Address Low Byte (address lines A19-A12)
outp (67xxindex, 0x10);
outp (67xxdata, 0xd0)
// Program Memory Map 0 Start Address High Byte (address lines A23-A20) to all
zeros
// and enable 16-bit card memory cycles
outp (67xxindex, 0x11);
outp (67xxdata, 0x80);
// Program Memory Map 0 End Address Low Byte (address lines A19-A12)
outp (67xxindex, 0x12);
outp (67xxdata, 0xdf);
// Program Memory Map 0 End Address High Byte (A23-A20) and select card cycle
// Timing Register Set 0 for memory operations in this window
outp (67xxindex, 0x13);
outp (67xxdata, 0x00);
// Program Memory Map 0 Address Offset Low Byte (A19-A12)
outp (67xxindex, 0x14);
outp (67xxdata, 0x30);
// Program Memory Map 0 Address Offset High Byte (address lines A25-A20) and
// program Memory Window 0 to be common memory; clear Write Protect to allow
// writes to card memory in Memory Window 0
outp (67xxindex, 0x15);
outp (67xxdata, 0x3f);
// Enable Memory Map 0, leave all other bits unchanged.
outp (67xxindex, 0x06);
x = inp (67xxdata);
x |= 1;
outp (67xxdata, x);
5.2
I/O Windows
The PD6729 supports up to two I/O windows per card socket. I/O-window mapping is similar to
mapping memory windows. I/O window sizes are specified in even addresses increments on word
boundaries. Offsets are provided from I/O windows so the actual address used to access I/O on a
PC Card can be different than the system I/O address. A typical example of I/O window definition
and access is described below.
Figure 8 shows two I/O windows programmed for IDE drive support with I/O-map offsets of zero.
The first I/O window has a start address at 01F0h and a stop address at 01F7h. The second I/O
window has a start address at 03F6h and a stop address at 03F7h.
18
Application Note
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
Figure 8. Window Mapping Example of System I/O Addresses
Without Offset to PC Card I/O Address
SYSTEM I/O
ADDRESS SPACE
PC CARD I/O
ADDRESS SPACE
FFFFH = 64K
FFFFH = 64K
WINDOW 1
MAPPING
03F7H
03F6H
03F7H
03F6H
01F7H
01F7H
WINDOW 0
MAPPING
01F0H
0000H
01F0H
I/O MAP
ADDRESS
OFFSETS = 0000H
0000H
Following is a code segment related to the example in Figure 8.
#define
#define
#define
#define
67xxbase
67xxindex
67xxdata
miscntrl2
0xXXX
// XXX is value of configuration index 10h
67xxbase
67xxindex + 1
0x1e
// code fragment
// Set socket power to Auto-power on when card is installed
outp (67xxindex, 0x02);
outp (67xxdata, 0xb0);
// Disable I/O windows 0 and 1 during I/O map window programming
outp (67xxindex, 0x06);
x = inp(67xxdata);
x &= 0x3f;
outp (67data, x);
// Program I/O Map 0 Start Address Low
outp (67xxindex, 0x08);
outp (67xxdata, 0xf0);
// Program I/O Map 0 Start Address High
outp (67xxindex, 0x09);
outp (67xxdata, 0x01);
//Program I/O Map 0 End Address Low
outp (67xxindex, 0x0a);
outp (67xxdata, 0xf7);
Application Note
19
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
//Program I/O Map 0 End Address High
outp (67xxindex, 0x0b);
outp (67xxdata, 0x01);
// Program I/O Map 1 Start Address Low
outp (67xxindex, 0x0c);
outp (67xxdata, 0xf6);
// Program I/O Map 1 Start Address High
outp (67xxindex, 0x0d);
outp (67xxdata, 0x03);
//Program I/O Map 1 End Address Low
outp (67xxindex, 0x0e);
outp (67xxdata, 0xf7);
//Program I/O Map 1 End Address High
outp (67xxindex, 0x0f);
outp (67xxdata, 0x03);
// Enable I/O Map 0 and I/O Map 1
outp (67xxindex, 0x06);
x = inp (67xxdata);
x |= 0xcf;
outp (67xxdata, x);
20
Application Note
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
6.0
Timing Registers
The timing registers program PC Card access timing for the following timing parameters: Setup,
Command, and Recovery. When the PD6729 timing registers are programmed for card-specific
requirements, meeting the card-specific timing is ensured.
The PD6729 has two timing register sets: Timing 0 and Timing 1. Each timing register set has a
Setup Timing register, a Command Timing register, and a Recovery Timing register. Memory and
I/O windows are individually programmable to use card access timing from either of the
programmable timing register sets (Timing 0 or Timing 1).
Note:
Do not modify the timing-set register values during PC Card bus cycles. Timing registers should
not be changed until the Write FIFO is empty because the timing changes begin immediately and
can corrupt any cycles in progress. This is verifiable by checking that the Empty Write FIFO bit (7)
of the FIFO Control register (Index 17h) is set to ‘1’.
After reset, the Timing 0 register set defaults to the values shown in Table 1. The Command signals
(that is, −WE, −OE, −IOWR, and −IORD) control Setup, Command, and Recovery. The window
widths are derived from the falling and rising edges of these signals. The register setting for the
Timing Set 0 register after reset is shown in Table 1. The timing diagram is shown in Figure 9 on
page 22.
Table 1.
Programmable Timing Set 0 Default Setting
Parameter
Register
Value
Time
Setup
3A
01
80 ns
Command
3B
06
280 ns
Recovery
3C
00
40 ns
NOTES:
1. Internal timing granularity = 1 ÷ PCI_CLK = 1 ÷ 25 MHz = 40 ns. If the PCI_CLK input is > 25
MHz, the Clock ÷ 2 bit in Index 1Eh, bit 4 must be set to ‘1’. The slot control interface is not
designed to operate at frequencies above 25 MHz. Setting the Clock ÷ 2 bit to ‘1’ accommodates
PCI bus speeds > 25 KHz, but £ 33 Mhz. This doubles the timing to the PC Card socket.
for example,
PCI_CLK = 33 MHz (PCI_CLK > 25 MHz)
Index 1Eh, bit 4 = 1
Internal timing granularity = 1 ÷ (33 MHz ÷ 2) = 60 ns
2. The timing for this example is derived from a 25 MHz PCI_CLK input to the PD6729 controller.
Application Note
21
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
Figure 9. Setup, Command, and Recovery Timing Diagram
PROGRAMMABLE
SETUP TIME
(80 ns DEFAULT)
PC CARD
ADDRESS
VALID
PC CARD DATA
(WRITE CYCLE)
VALID
PROGRAMMABLE
RECOVERY TIME
(40 ns DEFAULT)
−CE1, −CE2
−REG
PROGRAMMABLE
COMMAND TIME
(280 ns DEFAULT)
−IORD, −IOWR
−OE, −WE
PC CARD DATA
(READ CYCLE)
VALID
MIN 90 ns
REQUIRED
6.1
Setting the Timing Registers for SRAM Card Example
The values in the timing registers can be altered to vary the width of the Setup, Command, and
Recovery times for a particular application.
For example, consider programming a SRAM memory card that requires a minimum address setup
time of 30 ns, a write pulse width of 150 ns, and a data recovery time of 50 ns.
6.2
Programming the Timing 1 Register Set
Each timing register has two variable fields to control the scale and duration of the timing
parameter: prescalar value and the multiplier value. By using the prescalar value and the multiplier
value, the timing parameter is calculated as follows:
Timing parameter = (Npres × Nval) + 1
22
Application Note
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
Prescalar values are determined by bits 7 and 6 of each of the three timing registers comprising
Timing Set 0 and Timing Set 1. These possible values are shown in Table 2.
.
Table 2.
Prescalar Values
Timing Parameter Register
Prescalar Value
Bit 7
Bit 6
0
0
0
1
16
1
0
256
1
1
4096
1
The multiplier increases the timing parameter by a factor of the selected prescalar. The multiplier
value is determined by bits 5:0 of the three timing registers comprising Timing Set 0 and Timing
Set 1. These six bits permit integer values from 0–63.
Based on the range of prescalar and multiplier values, the minimum timing parameter window
width is 40 ns, and the maximum timing parameter window width is slightly greater than 20 ms.
To select a setup time parameter close to 30 ns, set bits 7 and 6 to ‘00’ (corresponding to a prescalar
value of 40 ns) and, with a multiplier of zero, an address setup time of 40 ns is attainable.
Setup Time = (40 ns) × (0)
+ 40 ns = 40 ns
TCP = 1 ÷ PCI_CLK frequency
The Command and Recovery registers are similarly configured. After setting up the Timing 1
registers for the example described, the Setup, Command, and Recovery registers have the values
shown in Table 3 and Figure 10.
Table 3.
Example of SRAM Card Write Timing Settings
Parameter
Register
Value
Time
Setup
3D
00
40 ns
Command
3E
04
200 ns
Recovery
3F
01
80 ns
NOTE:
1. The above example assumes a 25 MHz PCI CLK.
2. The internal clock period is the same as the PCI_CLK or EXT_CLK period if the MISC Control 2
register, bit 4 is ‘0’ and doubles the PCI_CLK or EXT_CLK if this bit is ‘1’.
Note:
If PCI_CLK operates at a frequency > 25 MHz, the MISC Control 2 register, bit 4 must be set to
‘1’.
Application Note
23
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
Figure 10. Timing Diagram of Example SRAM Card Write Timing Setting
RECOVERY TIME
80 ns
SETUP TIME
40 ns
PC CARD
ADDRESS
−CE1, −CE2
COMMAND TIME
200 ns
−IOWR
OR −WE
PC CARD
DATA
Following is a code segment shows the code needed to program the Timing 1 register for SRAM
timing examples:
#define
#define
#define
#define
#define
#define
67xxbase
67xxindex
67xxdata
miscntrl2
TRUE
FALSE
0xXXX
// XXX is value of configuration index 10h
67xxbase
67xxindex + 1
0x1e
(1 ==1)
!TRUE
// code fragment
// function to check the fifo busy bit
BOOL check_fifo (void)
{
int I, x;
outp (67xxindex, 0x17);
for (I=0; I < 0x400; I++)
{
x = inp (67xxdata);
x &= 0x80;
if ( xxx == 0x80) return (TRUE);
}
return (FALSE);
}
// main code
if (check_fifo())
{
// Set Setup Time window of 40 ns.
Outp (67xxindex, 0x3d);
Outp (67xxdata, 0x00);
24
Application Note
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
// Set Command Time window of 200 ns
Outp (67xxindex, 0x3e);
Outp (67xxdata, 0x04);
// Set Recovery Time window of 80 ms
Outp (67xxindex, 0x3f);
Outp (67xxdata, 01);
// Set up Memory Window 0 to use Timing 1 register
outp (67xxindex, 0x13);
x = inp (67xxdata);
x |= 0x40;
outp (67xxdata, x);
}
Application Note
25
PD6729 — A PCI Motherboard PC Card (PCMCIA) Controller Solution
7.0
Appendix A
7.1
PD6729 PCI Bus Demonstration Board PC Card Solution —
Schematics
The schematics in this appendix show sample circuits. The signal connections used in evaluation
board schematics can be applied to a motherboard solution. The evaluation board schematics
provided include the following:
• Sample circuitry for the PD6729
— Power-control logic
— PCI bus interface
— PC Card bus interface
26
Application Note
1
2
3
4
5
6
5V
13
25
36
47
STOP#
IRDY#
T R D Y#
RST#
DEVSEL#
FRAME#
IDSEL
32
29
30
207
31
27
15
LED
SPKR
133
132
1
PCI_CLK
203
204
205
206
58
59
60
61
62
63
195
197
199
141
143
145
147
149
196
198
200
144
146
148
150
152
B_D0
B _ D1
B _ D2
B _ D3
B _ D4
B_D5
B _ D6
B _ D7
B _ D8
B _ D9
B_D10
B_D11
B_D12
B_D13
B_D14
B_D15
193
191
190
187
185
183
181
179
162
159
153
157
176
164
166
174
172
163
165
167
169
171
173
175
178
180
B_A0
B_A1
B_A2
B_A3
B_A4
B_A5
B_A6
B_A7
B_A8
B_A9
B_A10
B_A11
B_A12
B _ A13
B_A14
B_A15
B_A16
B_A17
B _ A18
B_A19
B_A20
B_A21
B_A22
B _ A23
B_A24
B_A25
139
131
3#
2#
1#
0#
STOP#
IRDY#
T R D Y#
RST#
DEVSEL#
FRAME#
IDSEL
A_SOCKET_VCC
A_SOCKET_VCC
LED OUT*
SPKR OUT*
A_VPP_PGM
A_VPP_VCC
A_VCC_3
A_VCC_5
PCI CLK
CORE
RING
RING
RING
RING
RING
RING
RING
2
3
208
D
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AA25
AA24
AA23
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
AA12
AA11
AA10
AA9
AA8
AA7
AA6
AA5
AA4
AA3
AA2
AA1
AA0
G N T#
REQ#
J10
PCI_CLK_REQ
188
161
1
2
C O RE_VCC
C30
0.1uF
3V
134
135
136
138
5V_VCC
J4
1
2
3
B_VPP_PGM
B _ VPP_VCC
B_VCC_3
B_VCC_5
109
111
113
81
107
125
83
85
80
93
118
116
66
126
75
79
95
64
CORE_VCC
B
J3
1
2
3
A_RESET
A_WAIT
A_INPACK
A_VS1
A_VS2
A_W P
A_IORD
A_IOWR
A_OE
A_W E
A_BVD1
A_BVD2
A _ C D1
A _ C D2
A_CE1
A_CE2
A_RDY
A_REG
78
102
PCI_VCC
5V_VCC
J5
5V
1
GND
GND
GND
GND
GND
GND
GND
GND
C
J6
AVCC
A_VPP_PGM
A _ V P P _ VCC
A _ V C C_3
A _ V C C_5
2
AVCC
1
LINK ETCH
J9
26
177
137
91
56
44
28
14
2
BVCC
1
LINK ETCH
|LINK
|6729SA.SCH
|6729SB.SCH
|6729P.SCH
|6729PCI.SCH
6 7 29
D
Cirrus Logic Inc.
Title
P D 6 7 2 9 Pin Interface
AD[15..0]
Size
B
Date:
5
2
LINK ETCH
AVCC
127
128
129
130
A A [ 2 5 . .0]
4
C33
0.1uF
C O N3A
2
3
5V
C27
0.1uF
BVCC
CON2
1
PCI_VCC
BVCC
IRQ3/INTA#
IRQ4/INTB#
IRQ5/INTC#
IRQ7/INTD#
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14/EXT_CLK
IRQ15
NC
NC
NC
IR3
IR4
IR5
IR7
IR9
IR10
IR11
IR12
IR14
IR15
A RESET
A -WAIT
A -INPACK
A VS1
A VS2
A WP/-IOIS16
A -IORD
A -IOWR
A -OE
A -WE
A BVD1/-STSCHG
A BVD2/-SPKR
A -CD1
A -CD2
A -CE1
A -CE2
A RDY/-IRQ
A -REG
PAR
SERR#
PERR#
C/BE
C/BE
C/BE
C/BE
A
B_RESET
B _ WAIT
B_INPACK
B_VS1
B_VS2
B_WP
B_IORD
B_IOWR
B_OE
B_WE
B_BVD1
B_BVD2
B_CD1
B_CD2
B_CE1
B_CE2
B_RDY
B_REG
A_D0
A_D1
A_D2
A_D3
A_D4
A_D5
A_D6
A_D7
A_D8
A_D9
A_D10
A_D11
A_D12
A_D13
A_D14
A_D15
C/BE3#
C/BE2#
C/BE1#
C/BE0#
B RESET
B -WAIT
B -INPACK
B VS1/GPIO1
B VS2/GPIO2
B WP/-IOIS16
B -IORD
B -IOWR
B -OE
B -WE
B BVD1/-STSCHG
B BVD2/-SPKR
B -CD1
B -CD2
B -CE1
B -CE2
B RDY/-IRQ
B -REG
184
186
189
156
182
201
158
160
155
168
194
192
142
202
151
154
170
140
C O N3A
119
121
123
65
67
69
71
73
120
122
124
68
70
72
74
76
35
34
33
C31
0.1uF
U?
B_VPP_PGM
B_VPP_VCC
B -VCC_3
B -VCC_5
PD6729
BVCC
C32
0.1uF
B SOCKET VCC
B SOCKET VCC
A_A0
A_A1
A_A2
A_A3
A_A4
A_A5
A_A6
A_A7
A_A8
A_A9
A_A10
A_A11
A_A12
A_A13
A_A14
A_A15
A_A16
A_A17
A_A18
A_A19
A_A20
A_A21
A_A22
A_A23
A_A24
A_A25
PAR
SERR#
PERR#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
A D 10
A D 11
A D 12
A D 13
A D 14
A D 15
A D 16
A D 17
A D 18
A D 19
A D 20
A D 21
A D 22
A D 23
A D 24
A D 25
A D 26
A D 27
A D 28
A D 29
A D 30
A D 31
117
115
114
112
110
108
106
104
86
84
77
82
101
88
90
99
97
87
89
92
94
96
98
100
103
105
C
57
55
54
53
52
51
49
48
46
45
43
42
41
40
39
38
24
23
22
20
19
18
17
16
12
11
10
9
8
7
5
4
CORE VDD
+5V
6
21
37
50
PCI VCC
PCI VCC
PCI VCC
PCI VCC
AD[31..0]
B
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AVCC
B D [ 1 5..0]
BD15
BD14
BD13
BD12
BD11
BD10
BD9
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
BA25
BA24
BA23
BA22
BA21
BA20
BA19
BA18
BA17
BA16
BA15
BA14
BA13
BA12
BA11
BA10
BA9
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
PCI_VCC
AD[31..0]
8
B A [25..0]
CORE_VCC
A
7
6
Document Number
CL-PD6729 Demo Board
T u e s d a y , D e c e m b e r 0 5, 1995S h e e t
7
Rev
1.1
1
of
8
5
1
2
AVCC
3
4
5
6
7
8
AVCC
5V_VCC
J7
C39
0.1uF
R26
100K
AD3T
AD5T
AD7T
ACE1
AOE
A A 11
AA8
A A 14
AWE
AVCC
AVPP
A A 16
A A 15
AA7
AA5
AA3
AA2
AA0
AD1T
AWP
J14
AVPP
A
1
2
3
A V PP
C38
0.1uF
AVS1
CON3A
J13
1
2
3
AVS2
CON3A
A A [ 2 5 ..0]
AD[15..0]
AA[25..0]
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
AD4T
AD6T
AA10
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
A
AA9
AA13
ARDY
AVCC
AA12
AA6
AA4
120
120
120
120
120
120
120
120
R10
R11
R12
R14
R15
R16
R17
R42
AD0
AD1
AD2
AD7
AD5
AD6
AD4
AD3
AD0T
AD1T
AD2T
AD7T
AD5T
AD6T
AD4T
AD3T
AA1
AD0T
AD2T
C O N 40A
AD[15..0]
CON1
B
C
AA0
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
29
28
27
26
25
24
23
22
12
11
8
10
21
13
14
20
19
46
47
48
49
50
53
54
55
56
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
30
31
32
2
3
4
5
6
64
65
66
37
38
39
40
41
D
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
CE1
CE2
WE
OE
IORD
IOWR
BVD1
BVD2
WP/IOIS16
RDY/BSY
RESET
WAIT
INPACK
REG
CD1
CD2
VS1
VS2
VCC
VCC
VPP
VPP
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
GND
GND
GND
GND
B
7
42
15
9
44
45
ACE1
ACE2
AWE
AOE
AIORD
AIOWR
A _ CE1
A _ CE2
A_W E
A_OE
A_IORD
A_IOWR
63
62
33
16
58
59
60
61
ABVD1
ABVD2
AWP
A R E S ET
A R E S ET
AWAIT
AINP
AREG
A_BVD1
A_BVD2
A_W P
A_RDY
A_RESET
A_WAIT
A_INP
A_REG
36
67
ACD1
ACD2
A_CD1
A_CD2
43
57
AVS1
AVS2
C35
CAP
J8
ACD1
A D 1 1T
A D 1 3T
A D 1 5T
ACE2
AIORD
AIOWR
AA18
AA20
ARDY
AVCC
AA22
AA24
AWAIT
AINP
ABVD2
AD8T
A D 1 0T
ACD2
A_VS1
A_VS2
17
51
AVCC
18
52
AVPP
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
A D 1 2T
A D 1 4T
A A 17
A A 19
A A 21
AVPP
AD10
AD8
AD15
AD13
R18
R19
R20
R21
120
120
120
120
AD10T
AD8T
AD15T
AD13T
AD11
AD14
AD12
R23
R24
R25
120
120
120
AD11T
AD14T
AD12T
A A 23
A A 25
ARESET
AREG
ABVD2
AD9
C
C O N 4 0A
C34
CAP
1
34
35
68
D
S L OT-68
Cirrus Logic, Inc.
Title
P C M C I A S o c k e t A Interface
Size
B
Date:
1
2
3
4
5
6
Document Number
CL-PD6729 DEMO BOARD
T u e s d a y , D e c e m b e r 0 5, 1995S h e e t
7
Rev
1.0
2
of
8
5
1
2
BVCC
C29
0.1uF
R13
100K
3
4
5
6
7
8
B V CC
BVPP
BVPP
C28
0.1uF
A
A
B A [25..0]
B D [ 15..0]
BA[25..0]
BD[15..0]
CON2
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
BA8
BA9
BA10
BA11
BA12
BA13
BA14
BA15
BA16
BA17
BA18
BA19
BA20
BA21
BA22
BA23
BA24
BA25
B
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BD8
BD9
BD10
BD11
BD12
BD13
BD14
BD15
C
29
28
27
26
25
24
23
22
12
11
8
10
21
13
14
20
19
46
47
48
49
50
53
54
55
56
30
31
32
2
3
4
5
6
64
65
66
37
38
39
40
41
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
CE1
CE2
WE
OE
IORD
IOWR
BVD1
BVD2
WP/IOIS16
RDY/BSY
RESET
WAIT
INPACK
REG
CD1
CD2
VS1
VS2
VCC
VCC
VPP
VPP
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
7
42
15
9
44
45
B_CE1
B_CE2
B_OE
B_WE
B_IORD
B_IOWR
63
62
33
16
58
59
60
61
B_BVD1
B_BVD2
B_WP
B_RDY
B_RESET
B _ WAIT
B_INPACK
B_REG
36
67
43
57
BVS1
BVS2
17
51
BVCC
18
52
BVPP
B
5V_VCC
J12
1
2
3
BVS1
B_CD1
B_CD2
C O N3A
B_VS1
B_VS2
1
2
3
J11
BVS2
C O N3A
C
GND
GND
GND
GND
1
34
35
68
S L OT-68
D
D
Cirrus Logic, Inc.
Title
P C M C I A S o c k et B Interface
Size
B
Date:
1
2
3
4
5
6
Document Number
CL-PD6729 DEMO BOARD
T u e s d a y , D e c e m b e r 0 5, 1995S h e e t
7
Rev
1.0
3
of
8
5
1
2
5V_VCC
3
4
5V_VCC
Q1A
SI9953DY
8
3
A _ V C C_5
6
8
5V_VCC
BVCC
B_VCC_5
A_SLOT_VCC
R3
470
B _ S L O T _VCC
A
B_VCC_3
Q2B
3
6
8
SI9953DY
2
2
3V
AVCC
3V
C3
10uF
1
Q4A
1
8
6
SI9953DY
Q2A
SI9953DY
D1
LED
BVCC
4
A _ V C C_3
4
A
7
4
BVCC
6
Q1B
SI9953DY
2
1
5
C9
10uF
3
5V_VCC
LED
J15
Q4B
SI9953DY
1
2
3
4
5
6
7
8
9
10
POWER CONTROL VCC
3.3 VOLT OR 5 VOLT SWITCH
20
19
18
17
16
15
14
13
12
11
(OPTIONAL)
SPARE
LED CIRCUIT
ATA MODE ONLY
B
B
SPARE 20 PIN
5V_VCC
12V_VCC
U1
1
2
3
4
5
6
7
A _ VPP
A_SLOT_VCC
B _ S L O T_VCC
B_VPP
VPPOUT1
NC
+ V C C1
VPPIN
+ V C C2
GND
VPPOUT2
VDD
HI-Z/LOW1
EN0-1
EN1-1
HI-Z.LOW2
EN0-2
EN1-2
14
13
12
11
10
9
8
A _ V P P _ VCC
A_VPP_PGM
5V_VCC
10uF
J1
SPKR
MIC2558
C
C5
B _ VPP_VCC
B_VPP_PGM
1
2
R1
3
4
10K POT
AVPP
A V PP
BVPP
GAIN 1
GAIN 2
-INPUT
BYPASS
+INPUT
VS
GND
VOUT
8
C6
22uF
6
C7
C11
10uF
BVPP
C10
10uF
LS1
5
22uF
C4
0.05uF
LM386
C23
1.0uF
C
7
C22
0.1uF
SPEAKER
R4
15
(OPTIONAL)
POWER CONTROL VPP
5 VOLT OR 12 VOLT SWITCH
SPEAKER CIRCUIT
D
D
Note: The CL-PD6720-A-DM1-2 EVAL board uses the 12V supplied from the
ISA bus as the 12V input for the VPP circuit.
CIRRUS LOGIC, INC.
PCMCIA 2.01 specification
Title
requires a VPP voltage level of 12V +\- 5%. In actual applications we suggest
P O W E R CONTROL LOGIC
that the designer use a 12V regulator circuit to guareent that the VPP voltage is
Size
B
Document Number
CL-PD6729 DEMO BOARD
Rev
1.1
within the PCMCIA 2.01 specification.
Date:
1
2
3
4
5
6
T u e s d a y , D e c e m b e r 0 5, 1995S h e e t
7
4
of
8
5
1
2
3
4
5
6
7
8
ADD IN CONFIGURATION 25 WATT MAX.
PRSNT#1 (pin B9) GND
PRSNT#2 (pin B11) OPEN
3V_SYS
3V_SYS
3V
12V_VCC
Q5
2N6034
A
J25
INTB#
INTD#
CLK
REQ#
AD31
AD29
AD27
AD25
B
C/BE3#
AD23
AD21
AD19
AD17
C/BE2#
IRDY#
DEVSEL#
PERR#
SERR#
C/BE1#
AD14
AD12
AD10
C
AD8
AD7
AD5
AD3
AD1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
KEYWAY
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
KEYWAY
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
AD[31..0]
3
R6
AD[31..0]
J2
VIN
C25
0.1uF
R7
1K
10K
ADJ
12V_VCC
U2
LM317T
VOUT
1
2
3
2
C O N3A
1
5V_VCC
A
R9
240
C12
10uF
INTA#
INTC#
5V_VCC
C26
1.0uF
R5
Q3
2N4401
R8
390
R2
1K
4.7 K
RST#
D2
GNT#
2.1V ZEINER
AD30
AD28
AD26
B
NOTE: INSTALL EITHER R2 OR R8
DO NOT INSTALL BOTH RESISTORS
AD24
IDSEL
AD22
AD20
AD18
AD16
3.3V Volt Regulator
FRAME#
T R DY#
STOP#
PAR
AD15
AD13
AD11
5V_VCC
C
J16
AD9
1
CLK
14
5V_VCC
J17
C/BE0#
AD6
AD4
7
CON4
AD2
AD0
8
3
2
1
PCI_CLK
C36
0.1uF
CON3A
PCI CONN
EXTERNAL CLOCK SOURCE
D
D
CIRRUS LOGIC, INC.
3V
3V
3V
3V_SYS
3V_SYS
12V_VCC
12V_VCC
5V_VCC
5V_VCC
5V_VCC
5V_VCC
5V_VCC
5V_VCC
Title
ISA BUS INTERFACE
C2
10uF
C8
10uF
C20
0.1uF
C16
10uF
C17
0.1uF
C14
10uF
C21
0.1uF
C1
10uF
C13
10uF
C15
10uF
C18
0.1uF
C24
0.1uF
C37
0.1uF
Size
B
Date:
1
2
3
4
5
6
Document Number
CL-PD6729 DEMO BOARD
T u e s d a y , D e c e m b e r 0 5, 1995S h e e t
7
Rev
1.0
5
of
8
5
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