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ATJ2256/ATJ2257/
ATJ2257B Datasheet
Latest Version: 1.0
2009-12-10
ATJ2256/ATJ2257/ATJ2257B DATASHEET
Declaration
Circuit diagrams and other information relating to products of Actions Semiconductor
Company, Ltd. (“Actions”) are included as a means of illustrating typical applications.
Consequently, complete information sufficient for construction is not necessarily given.
Although the information has been examined and is believed to be accurate, Actions makes
no representations or warranties with respect to the accuracy or completeness of the
contents of this publication and disclaims any responsibility for inaccuracies. Information in
this document is provided solely to enable use of Actions’ products. The information
presented in this document does not form part of any quotation or contract of sale. Actions
assumes no liability whatsoever, including infringement of any patent or copyright, for sale
and use of Actions’ products, except as expressed in Actions’ Terms and Conditions of Sale
for. All sales of any Actions products are conditional on your agreement of the terms and
conditions of recently dated version of Actions’ Terms and Conditions of Sale agreement
Dated before the date of your order.
This information does not convey to the purchaser of the described semiconductor
devices any licenses under any patent rights, copyright, trademark rights, rights in trade
secrets and/or know how, or any other intellectual property rights of Actions or others,
however denominated, whether by express or implied representation, by estoppel, or
otherwise.
Information Documented here relates solely to Actions products described herein
supersedes, as of the release date of this publication, all previously published data and
specifications relating to such products provided by Actions or by any other person
purporting to distribute such information. Actions reserves the right to make changes to
specifications and product descriptions at any time without notice. Contact your Actions
sales representative to obtain the latest specifications before placing your product order.
Actions product may contain design defects or errors known as anomalies or errata which
may cause the products functions to deviate from published specifications. Anomaly or
“errata” sheets relating to currently characterized anomalies or errata are available upon
request. Designers must not rely on the absence or characteristics of any features or
instructions of Actions’ products marked “reserved” or “undefined.” Actions reserves these
for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.
Actions’ products are not designed, intended, authorized or warranted for use in any life
support or other application where product failure could cause or contribute to personal
injury or severe property damage. Any and all such uses without prior written approval of an
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
Officer of Actions and further testing and/or modification will be fully at the risk of the
customer.
Copies of this document and/or other Actions product literature, as well as the Terms
and Conditions of Sale Agreement, may be obtained by visiting Actions’ website at
http://www.actions-semi.com/ or from an authorized Actions representative. The word
“ACTIONS”, the Actions’ LOGO, whether used separately and/or in combination, and the
phase “ATJ2256/ATJ2257/ATJ2257B”, are trademarks of Actions Semiconductor Company,
Ltd., Names and brands of other companies and their products that may from time to time
descriptively appear in this product data sheet are the trademarks of their respective
holders; no affiliation, authorization, or endorsement by such persons is claimed or implied
except as may be expressly stated therein.
ACTIONS DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT
LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL ACTIONS BE RELIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT,
SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS
OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT; TORT; NEGLIGENCE OF ACTIONS OR OTHERS; STRICT LIABILITY; BREACH OF
WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE
FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER ACTIONS HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES OR NOT.
Additional Support:
Additional product and company information can be obtained by visiting the Actions
website at: http://www.actions-semi.com
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
Contents
Declaration......................................................................................................................1
Contents ..........................................................................................................................3
Revision History ........................................................................................................... 10
1
2
3
Introduction........................................................................................................... 11
1.1
Overview.......................................................................................................................... 11
1.2
Features .......................................................................................................................... 11
Functional Block and Memory Map ................................................................... 13
2.1
Functional Block Diagram ............................................................................................13
2.2
Memory Map ..................................................................................................................13
Clock Management Unit (CMU) ...........................................................................16
3.1
CMU/HOSC Register List ..............................................................................................16
3.1.1
CMU_COREPLL........................................................................................................... 17
3.1.2
CMU_DSPPLL ............................................................................................................. 17
3.1.3
CMU_AUDIOPLL .........................................................................................................18
3.1.4
CMU_BUSCLK .............................................................................................................19
3.1.5
CMU_SDRCLK.............................................................................................................20
3.1.6
CMU_NANDCLK.......................................................................................................... 21
3.1.7
CMU_SDCLK ............................................................................................................... 21
3.1.8
CMU_MHACLK ............................................................................................................22
3.1.9
CMU_BTCLK ................................................................................................................22
3.1.10 CMU_UARTxCLK .........................................................................................................23
3.1.11 CMU_DMACLK ............................................................................................................23
3.1.12 CMU_FMCLK ............................................................................................................... 24
3.1.13 CMU_DEVCLKEN ........................................................................................................ 24
3.1.14 CMU_DEVRST .............................................................................................................26
3.2
RTC/LOSC/Watch Dog/Timers Block Description.................................................... 27
3.3
RTC/LOSC/Watch Dog Register List........................................................................... 27
3.3.1
RTC_CTL ......................................................................................................................28
3.3.2
RTC_DHMS..................................................................................................................29
3.3.3
RTC_YMD ....................................................................................................................29
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3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.3.9
3.3.10
4
RTC_DHMSALM..........................................................................................................30
RTC_YMDALM.............................................................................................................30
RTC_WDCTL................................................................................................................ 31
RTC_T0CTL.................................................................................................................. 31
RTC_T0 ........................................................................................................................32
RTC_T1CTL..................................................................................................................32
RTC_T1 ........................................................................................................................33
Interrupt Controller............................................................................................... 34
4.1
Interrupt Controller Description...................................................................................34
4.2
Interrupt Controller Register List .................................................................................35
4.2.1
INTC_PD ......................................................................................................................35
4.2.2
INTC_MSK ...................................................................................................................36
4.2.3
INTC_CFGx................................................................................................................... 37
4.2.4
INTC_EXTCTL ..............................................................................................................38
5
PMU/DC-DC Converter......................................................................................... 40
5.1
Description...................................................................................................................... 40
5.2
Register List.................................................................................................................... 41
5.3
Register Description ...................................................................................................... 41
5.3.1
PMU_CTL ..................................................................................................................... 41
5.3.2
PMU_LRADC ...............................................................................................................44
5.3.3
PMU_CHG....................................................................................................................44
5.3.4
PMU_USBPDR ............................................................................................................46
6
32-BIT RISC Core .................................................................................................. 48
6.1
7
Coprocessor 0 Description ...........................................................................................48
SDRAM Interface.................................................................................................. 49
7.1
SDRAM Interface Description ......................................................................................49
7.2
SDRAM Interface Register List ....................................................................................49
7.2.1
SDR_CTL .....................................................................................................................50
7.2.2
SDR_EN .......................................................................................................................51
7.2.3
SDR_CMD ................................................................................................................... 51
7.2.4
SDR_STAT ...................................................................................................................52
7.2.5
SDR_AUTORFC ...........................................................................................................52
7.2.6
SDR_MODE .................................................................................................................52
7.2.7
SDR_MOBILE ..............................................................................................................53
8
DMA/Bus Arbiter .................................................................................................. 55
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8.1
Description...................................................................................................................... 55
8.1.1
DMA Architecture.......................................................................................................55
8.2
Register List.................................................................................................................... 56
8.2.1
DMA_CTL..................................................................................................................... 57
8.2.2
DMA_IRQEN................................................................................................................58
8.2.3
DMA_IRQPD ...............................................................................................................59
8.2.4
DMA_MODEx ..............................................................................................................60
8.2.5
DMA_SRCx..................................................................................................................63
8.2.6
DMA_DSTx ..................................................................................................................63
8.2.7
DMA_CNTx ..................................................................................................................63
8.2.8
DMA_REMx .................................................................................................................63
8.2.9
DMA_CMDx.................................................................................................................64
9
SD/MMC Interface ............................................................................................... 65
9.1
10
Description...................................................................................................................... 65
NAND FLASH/SMC State Machine ................................................................. 66
10.1
11
Description...................................................................................................................... 66
BT.656&601 Interface ..................................................................................... 67
11.1
Description...................................................................................................................... 67
11.2
Video Encoder/Decoder/CMOS Sensor/TS Interface ..............................................67
11.2.1 Register List................................................................................................................67
11.2.2 Register Description..................................................................................................68
11.3
Internal Video Encoder..................................................................................................80
11.3.1 Registers List..............................................................................................................80
11.3.2 Registers Description................................................................................................ 81
12
YUV2RGB Interface........................................................................................... 85
12.1
Description...................................................................................................................... 85
12.2
Register List.................................................................................................................... 85
12.2.1 YUV2RGB_CTL ............................................................................................................85
12.2.2 YU2RGB_DAT..............................................................................................................88
12.2.3 YUV2RGB_CLKCTL .....................................................................................................88
12.2.4 YUV2RGB_FrameCount.............................................................................................88
13
USB2.0 SIE (OTG) .............................................................................................. 89
13.1
14
General Description.......................................................................................................89
I2C (2) Interface................................................................................................ 90
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14.1
Description...................................................................................................................... 90
14.2
Register List.................................................................................................................... 90
14.2.1 I2Cx_CTL ..................................................................................................................... 91
14.2.2 I2Cx_CLKDIV...............................................................................................................92
14.2.3 I2Cx_STAT ...................................................................................................................92
14.2.4 I2Cx_ADDR .................................................................................................................94
14.2.5 I2Cx_DAT .....................................................................................................................94
15
SPI Interface...................................................................................................... 95
15.1
Description...................................................................................................................... 95
15.2
Register List.................................................................................................................... 95
15.2.1 SPI_CTL .......................................................................................................................95
15.2.2 SPI_CLKDIV.................................................................................................................98
15.2.3 SPI_STAT .....................................................................................................................98
15.2.4 SPI_RXDAT................................................................................................................100
15.2.5 SPI_TXDAT ................................................................................................................100
16
UART (2) Interface .......................................................................................... 101
16.1
Description....................................................................................................................101
16.2
Register List..................................................................................................................101
16.2.1 UART1_CTL ...............................................................................................................102
16.2.2 UART1_RXDAT..........................................................................................................104
16.2.3 UART1_TXDAT ..........................................................................................................104
16.2.4 UART1_STAT .............................................................................................................104
16.2.5 UART2_CTL ...............................................................................................................106
16.2.6 UART2_RXDAT..........................................................................................................108
16.2.7 UART2_TXDAT ..........................................................................................................108
16.2.8 UART2_STAT .............................................................................................................109
17
IR Interface...................................................................................................... 111
17.1
Description................................................................................................................... 111
17.2
Register List................................................................................................................. 111
17.2.1 IR_PL ........................................................................................................................ 112
17.2.2 IR_RBC ..................................................................................................................... 112
18
SPDIF Interface...............................................................................................112
18.1
Register List................................................................................................................. 112
18.1.1 SPDIF_CTL ................................................................................................................113
18.1.2 SPDIF_STAT ..............................................................................................................114
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18.1.3
18.1.4
18.1.5
18.1.6
19
SPIDF_TXDAT............................................................................................................116
SPDIF_RXDAT ...........................................................................................................116
SPDIF_TXCSTAT........................................................................................................116
SPDIF_RXCSTAT .......................................................................................................117
Key Scan ..........................................................................................................118
19.1
Description................................................................................................................... 118
19.2
Register List................................................................................................................. 120
19.2.1 KEY_CTL ................................................................................................................... 120
19.2.2 KEY_DAT0 ................................................................................................................ 122
19.2.3 KEY_DAT1 ................................................................................................................ 122
19.2.4 KEY_DAT2 ................................................................................................................ 122
19.2.5 KEY_DAT3 ................................................................................................................ 122
20
GPIO and Multi-function Configuration ........................................................ 123
20.1
Description................................................................................................................... 123
20.1.1 Multi-function .......................................................................................................... 123
20.1.2 GPIO/Function pin .................................................................................................. 123
20.1.3 Pad with Built-in Resistance ................................................................................. 123
20.2
Register List..................................................................................................................124
20.2.1 GPIO_AOUTEN ..........................................................................................................124
20.2.2 GPIO_AINEN..............................................................................................................124
20.2.3 GPIO_ADAT .............................................................................................................. 125
20.2.4 GPIO_BOUTEN ......................................................................................................... 125
20.2.5 GPIO_BINEN............................................................................................................. 125
20.2.6 GPIO_BDAT .............................................................................................................. 125
20.2.7 GPIO_MFCTL0 ......................................................................................................... 126
20.2.8 GPIO_MFCTL1 ..........................................................................................................127
21
DAC and Headphone Driver........................................................................... 129
21.1
Description................................................................................................................... 129
21.2
Register List................................................................................................................. 130
21.2.1 DAC_CTL....................................................................................................................131
21.2.2 DAC_FIFOCTL............................................................................................................132
21.2.3 DAC_DAT ...................................................................................................................133
21.2.4 DAC_Debug...............................................................................................................133
21.2.5 DAC_ANALOG ...........................................................................................................134
22
ADC................................................................................................................... 136
22.1
Description................................................................................................................... 136
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22.2
Register List................................................................................................................. 136
22.2.1 ADC_CTL....................................................................................................................136
22.2.2 ADC_FIFOCTL............................................................................................................138
22.2.3 ADC_DAT ...................................................................................................................139
22.2.4 ADC_Analog..............................................................................................................140
22.2.5 ADC_Debug...............................................................................................................141
23
Electrical Characteristics ............................................................................... 143
23.1
Absolute Maximum Ratings.......................................................................................143
23.2
Capacitance..................................................................................................................144
23.3
DC Characteristics .......................................................................................................144
23.4
Reset Characteristics ..................................................................................................145
23.5
PMU................................................................................................................................145
23.6
AC Characteristics........................................................................................................149
23.6.1 AC Test Input Waveform .........................................................................................149
23.6.2 Output Measuring Points........................................................................................149
23.7
Reset Parameter..........................................................................................................149
23.8
Initialization Parameter ............................................................................................. 150
23.9
GPIO Interface Parameter ......................................................................................... 150
23.10
Ordinary ROM Parameter .......................................................................................... 152
23.11
External System Bus Parameter............................................................................... 153
23.12
Bus Operation.............................................................................................................. 154
23.13
SPI Parameter ............................................................................................................. 156
23.14
SPDIF Interface Parameter ........................................................................................157
23.15
I2C Interface Parameter .............................................................................................157
23.16
A/D Converter Characteristics .................................................................................. 158
23.17
DAC Characteristics .....................................................................................................161
23.18
Headphone Driver Characteristics ............................................................................162
23.19
LCM Driver Parameter.................................................................................................165
23.20
NAND Flash IF...............................................................................................................166
23.21
SD Card..........................................................................................................................169
23.22
SDRAM IF ......................................................................................................................171
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24
Ordering Information...................................................................................... 183
24.1
Recommended Soldering Conditions...................................................................... 183
24.2
Precaution against ESD for Semiconductors ......................................................... 183
24.3
Handling of Unused Input Pins for CMOS................................................................ 184
24.4
Status before Initialization of MOS Devices ........................................................... 184
25
Pin Description................................................................................................185
25.1
ATJ 2256....................................................................................................................... 185
25.1.1 Pin Definition........................................................................................................... 185
25.1.2 Pin Assignment........................................................................................................193
25.2
ATJ 2257....................................................................................................................... 193
25.2.1 Pin Definition............................................................................................................193
25.2.2 Pin Assignment........................................................................................................202
25.3
ATJ2257B ..................................................................................................................... 202
25.3.1 Pin Definition............................................................................................................202
25.3.2 Pin Assignment........................................................................................................217
26
Package Drawing............................................................................................ 219
26.1
ATJ2256.........................................................................................................................219
26.2
ATJ2257........................................................................................................................ 220
26.3
ATJ2257B ......................................................................................................................221
27
Appendix .......................................................................................................... 222
27.1
Acronym and Abbreviations ...................................................................................... 222
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Revision History
Date
Revision
2009-12-10
1.0
Description
Initial version released;
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
1 Introduction
1.1 Overview
ATJ2256/ATJ2257/ATJ2257B is a highly integrated 32bit RISC-based SoC for digital media
solution. The RISC architecture and high speed bus controller are capable of achieving high
performance with low power consumption. With a built-in JPEG co-processor, this media
platform is capable of processing both JPEG and MJPEG format with higher efficiency. The
integrated high-speed USB 2.0 SIE enables the platform to act as a mass storage device at
the speed up to 480Mbps. The audio codec in the SoC is based on sigma-delta modulation,
providing high performance with low power consumption as well as allowing the flexible
adjustment of sample rates from 8k to 96k. The built-in audio codec is able to switch inputs
within headphones, microphones, FM radios and direct drive for low impedance earphones.
ATJ2256/ATJ2257/ATJ2257B also provides integrated SDRAM and Flash interfaces; IIC, IR
and UART etc. interfaces for changeable control and transfer modes, therefore the chips can
provide a true “ALL-IN-ONE” solution that is ideally suited for highly optimized digital media
devices.
1.2 Features
z
z
z
z
z
z
z
z
z
z
z
z
Audio playing support: WMA, OGG, APE, WAV, ASF, FLAC
Audio recording support: WAV
Video playing support: AMVB, XVID, WMV, FLV, MJPEG QVGA
Image view support: JPEG, BMP, GIF, PNG
High-speed USB 2.0 Device
High-Speed NAND I/F
Support SLC & MLC NAND FLASH with 8-bit Error Correction
Support SD/MMC FLASH Card
Support OLED, TFT, STN
Integrated stereo DAC & ADC
Li-Ion battery charger
6bit battery monitoring ADC
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
ATJ2256
ATJ2257
ATJ2257B
LQFP128
LQFP144
TFBGA144
(14mmX14mm)
(20mmX20mm)
(10.2mm×10.2mm)
Memory
Nand, SD/MMC
Nand, SD/MMC
Nand, SD/MMC
Display
CPU Interface LCM
TVOUT/CPU Interface
LCM
TVOUT/CPU Interface
LCM
Extension
Interface
I2C/UART1/IR/SPI
I2C/UART1/IR/SPI
I2C/UART1&2/IR/SPI
Key-press
4×3/Remote
3×3/Remote
4×3/Remote
USB
Slave
OTG/Host/Slave
OTG/Host/Slave
CMOS sensor
Not supported
Supported
Supported
TV OUT
Supported
Supported
Supported
TV IN
Not supported
Supported
Supported
TP
External
External
External
Package
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2 Functional Block and Memory Map
2.1 Functional Block Diagram
2.2 Memory Map
Altogether 4G memory map; user mode 512M: 00000000~1FFFFFFF
Physical Memory Map
Start
End
Size(M)
Function
0x00000000
0x0FFFFFFF
256
SDRAM Space
0x10000000
0x11FFFFFF
32
IO Device
0x12000000
0x13FFFFFF
32
Reserved
0x14000000
0x17FFFFFF
64
IO Device/MEM
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0x18000000
0x1FFFFFFF
128
MEM (boot)
IO Map
Start
End
Size(K)
Function
0x10000000
0x1000FFFF
64
PMU/LRADC
0x10010000
0x10017FFF
32
CMU/HOSC
0x10018000
0x1001FFFF
32
RTC/LOSC/WD
0x10020000
0x1002FFFF
64
Interrupt Controller
0x10030000
0x10037FFF
32
SRAM on Chip
0x10038000
0x1003BFFF
16
Reserved
0x1003C000
0x1003FFFF
16
32BitRisc Core Performance CNT
0x10040000
0x1004FFFF
64
Reserved
0x10050000
0x1005FFFF
64
DSP Control
0x10060000
0x1006FFFF
64
DMA Controller
0x10070000
0x1007FFFF
64
SDRAM Controller
0x10080000
0x1008FFFF
64
SPI controller
0x10090000
0x1009FFFF
64
Reserved
0x100A0000
0x100AFFFF
64
FLASH I/F
0x100B0000
0x100BFFFF
64
SD IF
0x100C0000
0x100CFFFF
64
MHA(MJPEG)
0x100D0000
0x100DFFFF
64
BT656 Port
0x100E0000
0x100EFFFF
64
USBOTG
0x100F0000
0x100FFFFF
64
YVU2RGB
0x10100000
0x1010FFFF
64
DAC+PA
0x10110000
0x1011FFFF
64
ADC
0x10120000
0x1012FFFF
64
Reserved
0x10130000
0x1013FFFF
64
Reserved
0x10140000
0x1014FFFF
64
SPDIF
0x10150000
0x1015FFFF
64
Reserved
0x10160000
0x1016FFFF
64
UART-2
0x10160000
IR
0x10170000
0x1017FFFF
64
Reserved
0x10180000
0x1018FFFF
64
IIC
0x10190000
0x1019FFFF
64
Reserved
0x101A0000
0x101AFFFF
64
Key Scan
0x101B0000
0x101BFFFF
64
Reserved
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0x101C0000
0x101CFFFF
64
GPIO
0x101D0000
0x101DFFFF
64
Reserved
0x101E0000
0x101EFFFF
64
Reserved
0x101F0000
0x101FFFFF
64
Reserved
2048
SUM
0x10200000
0x11FFFFFF
Reserved
IO/MEM Map
Start
End
Function
Size(K)
0x14000000
0x1403FFFF
256k
Reserved
0x14040000
0x1405FFFF
128k/96k
DSP mode 24bit Wide (128k)
MIPS mode 32bit Wide (96k)
0x140600000
0x17FFFFFF
Reserved
MEM (LCD and LAN) Map
Start
End
Size(M)
Function
0x18000000
0x18FFFFFF
16M
Reserved
0x19000000
0x19FFFFFF
16M
Reserved
0x1A000000
0x1AFFFFFF
16M
Reserved
0x1B000000
0x1BFFFFFF
16M
Reserved
0x1C000000
0x1CFFFFFF
16M
CE3 (LCD)
0x1D000000
0x1DFFFFFF
16M
CE2
0x1E000000
0x1EFFFFFF
16M
CE1
0x1F000000
0x1FFFFFFF
16M
CE0 (BROM)
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3 Clock Management Unit (CMU)
The chips support two oscillator inputs: 24M and 32.768K.
Clock Management Unit (CMU) can be driven by a 24M high oscillator and a 32.768k
low oscillator.
It provides:
¾ Four main clocks: MIPS core clock, DSP clock, AHB bus clock, APB bus clock;
¾ A low oscillator and a real time clock (RTC) module with alarm function.
The chips have a built-in Watch-Dog circuit.
Two 24bit timers are integrated in this IC. User may select either low or high oscillator
as the source.
3.1 CMU/HOSC Register List
CMU Base Address
Block Name
CMU
Physical Base Address
0x10010000
KSEG1 Base Address
0xB0010000
HOSC/CMU Register Address
REG Name
Offset
Description
CMU_COREPLL
0x0000
Core PLL Control Register
CMU_DSPPLL
0x0004
DSP PLL Control Register
CMU_AUDIOPLL
0x0008
Audio PLL Control Register
CMU_BUSCLK
0x000C
Bus CLK Control Register
CMU_SDRCLK
0x0010
SDRAM Interface CLK Control Register
--
0x0014
Reserved
CMU_NANDCLK
0x0018
NAND Interface CLK Control Register
CMU_SDCLK
0x001C
SD Interface CLK Control Register
CMU_MHACLK
0x0020
MHA CLK Control Register
CMU_BTCLK
0x0024
BT Clk Control Register
CMU_UART1CLK
0x0028
Uart1 Clk Control Register
CMU_UART2CLK
0x002C
Uart2 CLK Control Register
CMU_DMACLK
0x0030
DMA CLK Control Register
CMU_FMCLK
0x0034
FM CLK Control Register
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
--
0x0038
Reserved
CMU_DEVCLKEN
0x0080
Device CLK Enable Control Register
CMU_DEVRST
0x0084
Device Reset Control Register
3.1.1 CMU_COREPLL
Core PLL Control Register
Offset=0x0000
Bit
Name
31:10
-
9:8
CPBI
7
6
5:0
Description
R/W Reset
Reserved
R
0
Core PLL Bias
RW
0
CPEN
Core PLL Enable
0: Disable, 1: Enable
RW
0
HOEN
High Oscillator Enable.
0: Disable, 1: Enable
RW
1
RW
0
Core PLL Clock Control
Formula: 6M* CPCK,
Range: 12~ 378M,
COREPLLCLK Definition: 6M
If CPCK is less than 0x02, the Core PLL will be
unstable.
DPCK value must be more than 0x02.
3.1.2 CMU_DSPPLL
DSP PLL Control Register
Offset=0x0004
Bit
Name
31:9
-
8:7
6
Description
RW
Reset
Reserved
R
0
DPBI
DSP PLL Bias
RW
0
DPEN
DSP PLL Enable
0: Disable, 1: Enable
RW
0
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DSP PLL Clock Control
Formula: 6M* DPCK,
DSPPLLCLK Range:12~378M,
Definition: 6M
DPCK value must be more than 0x02.
5:0
RW
0
3.1.3 CMU_AUDIOPLL
Audio PLL Control Register
Offset=0x0008
Bit
Name
-
31:13
Description
Reserved
12
SRSEL
Audiopll 44.1kHz series Div Ratio selection:
0: 24M×32/34
1: 24M×47/50
11
ADCPLL
Audio PLL CLk Control,
0: 24.576M
1: 22.5792M
ADCCLK
ADC Clock Divisor, output is FS*256
PLL CLK: 24.576M,
22.5792M
000:/1
96k
000: useless
001:/2
48k
001: 44.1k
010:/3
32k
010: useless
011:/4
24k
011: 22.05k
100:/6
16k
100: useless
101:/8
12k
101:11.025k
110:/12
8k
110: Useless
111: Reserved
111: Useless
10:8
7
6:5
-
Reserved
APBI
R/W
Reset
RW
0
RW
RW
0
0
0
R
0
Audio PLL Bias
RW
0
4
APEN
Audio PLL Enable
0: Disable, 1: Enable
RW
0
3
DACPLL
DAC PLL CLk Control,
0: 24.576M
1: 22.5792M
RW
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
2:0
DACCLK
DAC Clock Divisor, output is FS*256
PLL CLK: 24.576M,
22.5792M
000:/1
96k
000: useless
001:/2
48k
001:44.1k
010:/3
32k
010: useless
011:/4
24k
011:22.05k
100:/6
16k
100: useless
101:/8
12k
101: 11.025k
110:/12
8k
110: useless
111: reserved
111: useless
RW
0
Note:
1. AUDIOPLLCLK maps to DSP port 3FEE DAC_FREQ_SELECT and ADC_FREQ_SELECT field.
The other field will be changed when operating one of these fields,
2. DSP & MIPS can both operate ADCCLK & DACCLK. The latter operation will decide
register’s value.
3.1.4 CMU_BUSCLK
Bus CLK Control Register
Offset=0x000C
Note: it may take a while before MCU Clock Changes. When the MCU clock is DC_En, there
are several ways to recover the clock to non-divided LOSC clock (32kHz) source:
1. Push Reset button
2. POWER ON RESET
3. Key Board IRQ
4. Alarm IRQ
5. SIRQ
6. USB wake up IRQ
Bits
Name
31
KEYE
30
Description
R/W
Reset
Key Wakeup Enable
R/W
0
ALME
Alarm Wakeup Enable
R/W
0
29
SIRE
SIRQ Wakeup Enable
R/W
0
28
-
Reserved
R/W
0
27
USBE
Usb Wakeup Enable
R/W
0
26:12
-
R
0
Reserved
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
11:8
7:6
5:4
3:2
PCLKDIV
Peripheral CLK Divisor
Div 2~16
0, 1: /2
2: /3
3: /4
……
15: /16
RW
0
RW
01
SCLKDIV
System CLK Divisor
00
/1
01
/2
10
/3
11
/4
Duty 50%
RW
0
CCLKDIV
CPU Clock Divisor
00
/1 (default)
01
/2
10
/3
11
/4
duty 50%
RW
0
Core CLK DC Enable
1: enable DC
When set 1, Core_Clk equal DC.
RW
0
R
0
Core Clock Selection
00: 32.768k
CORECLKS 01: 24M
10: Core_Clk
11: DSP PLL
1
DCEN
0
-
Reserved
3.1.5 CMU_SDRCLK
SDRAM Interface CLK Control Register
Offset=0x0010
Bit
31:2
Name
-
Description
Reserved
R/W
R
Reset
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
1:0
SDRDIV
SDRAM Clock Divisor
00
/1 (default)
01
/2
10
/3
11
/4
RW
0
3.1.6 CMU_NANDCLK
NAND Interface CLK Control Register
Offset=0x0018
Bit
31:4
3:0
Name
Description
R/W
Reset
-
Reserved
R
0
NANDDIV
NAND Interface Clock Division
0: /1
1: /2
2: /3
……
15: /16
RW
0
3.1.7 CMU_SDCLK
SD Interface CLK Control Register
Offset=0x001C
Bit
31:6
5
4
Name
-
Description
R/W
Reset
Reserved
R
0
CKEN
SD Interface Clock Enable
1: Enable
0: Disable
RW
0
D128
Enable Divide 128 circuit
1: Enable Div 128
0: Disable Div 128
RW
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
3:0
SD Interface Clock Divisor
0: /1
1: /2
2: /3
……
15: /16
SDDIV
RW
0
3.1.8 CMU_MHACLK
MHA CLK Control Register
Offset=0x0020
Bit
Name
31:4
-
3:0
MHADIV
Description
Reserved
MHA Clock Divisor
0: /1
1: /2
2: /3
……
15:/16
R/W
Reset
R
0
RW
0
3.1.9 CMU_BTCLK
BT Clk Control Register
Offset=0x0024
Bits
31..6
5..4
3..0
Name
-
Description
Reserved
BT Interface Clock Source Selection
0: Core_Clk
BTCSSEL 1: D_CLK
2: HOSC
3: reserved
BTDIV BT Clock Division
0: /1
1: /2
2: /3
……
15:/16
R/W Reset
R
0
RW
0
R
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
3.1.10 CMU_UARTxCLK
Uart1 Clk Control Register
Offset=0x0028
Uart2 Clk Control Register
Offset=0x002C
Bit
Name
31:17
-
16
UxEN
15:0
UARTxDIV
Description
Reserved
R/W Reset
R
0
Uartx Clock Enable
1: Enable
0: Disable
RW
0
Uartx Clock Divisor
Uartx_CLK*8=C_CLK/(UARTxDIV +1)
RW
0
3.1.11 CMU_DMACLK
DMA CLK Control Register
Offset=0x0030
Bit
31:4
Name
-
Description
Reserved
R/W
Reset
R
0
3
DMA 7 (Special Channel) Clock Enable
D7EN 1: Enable
0: Disable
R/W
0
2
DMA 6 (Special Channel) Clock Enable
D6EN 1: Enable
0: Disable
R/W
0
1
DMA 5 (Special Channel) Clock Enable
D5EN 1: Enable
0: Disable
R/W
0
0
DMA 4 (Special Channel) Clock Enable
D4EN 1: Enable
0: Disable
R/W
0
NOTE: DMA controller bus clock control bit is in CMU_DEVCLEEN register
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
3.1.12 CMU_FMCLK
FM CLK Control Register
Offset= 0x0034
Bits
Name
31..6
-
Description
reserved
R/W Reset
R
0
5
PWM Back Light clock Enable
BCKE 0:disable
1:enable
RW
0
4
Back Light CLK source select
BCKS 0:LOSC 32k
1:HOSC/8 3M
RW
0
RW
0
1
FM Clock Output Selection
CLKS 0:32.768k
1:24M
RW
00
0
FM Clock Output Enable(From Test Pin)
OUTE 1:Enable test pin output Clock
0:Disable test pin output
RW
00
Divided PWM Back Light Special Clock Control
LOSC HOSC/8
00: 32k 3M
BCKCON
01: 16k 1.5M
10: 8k
750k
11: 4k
375k
3:2
Note: Test pin can be configured to output oscillator clock 32k or 24M.
When OUTE is set to 0, test pin has the “test” function. When it is set to 1, test pin has the
clock out function.
3.1.13 CMU_DEVCLKEN
Device CLK Control Register
Offset=0x0080
Bits
Name
31..27
-
26
GPIO
Description
R/W Reset
Reserved
R
GPIO control reg clock enable.
Switch APB clock
RW
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0
0
ATJ2256/ATJ2257/ATJ2257B DATASHEET
25
Key
KEY control reg clock enable.
Switch APB clock.
RW
24
SPI
SPI control reg clock enable.
Switch AHB clock.
RW
23
IIC
IIC control reg clock enable.
Switch APB clock.
RW
22
UART
UART control reg clock enable.
Switch APB clock and UART special clock.
RW
21
-
Reserved
RW
20
SPDF
SPDIF control reg clock enable.
Switch APB clock and Audio special clk.
RW
19
__
Reserved
RW
18
ADC
ADC control reg clock enable.
Switch APB clock and Audio special clk.
RW
17
DAC
DAC control reg clock enable.
Switch APB clock and Audio special clk.
RW
16
DSPC
DSP control reg clock enable.
Switch APB clock and dsp special clk.
RW
15
-
Reserved
RW
14
MHA
MHA interface clock enable.
Switch AHB clock and MHA special clk.
RW
13
USBC
USB Controler interface clock enable.
Switch AHB clock.
RW
12
BT
BT656 interface clock enable.
Switch AHB clock and Bt656 special clk.
RW
11
SD
SD interface clock enable.
Switch AHB clock and SD special clk.
RW
10
--
Reserved
RW
9
NAND
Nand Flash interface clock enable.
Switch AHB clock and FLASH special clk.
RW
8
DMAC
DMA control block clock enable
Switch AHB clock and DMAC clock.
RW
7
--
Reserved
RW
6
SDRM
SDRAM mem block clock enable.
Switch AHB Clock And sdram special clk.
RW
5
SDRC
Sdram Control reg clock enable
Switch AHB Clock.
RW
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Page 25
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ATJ2256/ATJ2257/ATJ2257B DATASHEET
4
DSPM
3
-
2
RMOC
1
YUV
0
--
Dsp mem block clock enable
Switch AHB clock
1
RW
Reserved
0
R
Sram on chip Control reg clcok enable
Switch AHB clock.
RW
YUV2RGB block clock enable.
Switch AHB clock.
RW
Reserved
RW
1
0
1
NOTE: Some other clocks are always on, including APB_En (APB bridge clock), PMU_En,
CMU_En, RTC_En, INTC_En.
3.1.14 CMU_DEVRST
Device Reset Control Register
Offset=0x0084
Bits
Name
31
-
30
GPIO
29
Description
Reserved
R/W Reset
R
1
GPIO control Block reset
RW
1
Key
KEY control Block reset.
RW
1
28
SPI
SPI Block reset.
RW
1
27
IIC
IIC control Block reset.
RW
1
26
UART
UART control Block reset.
RW
1
25
-
Reserved
RW
1
24
SPDF
SPDIF control reg Block reset.
RW
1
23
_
Reserved
RW
1
22
ADC
ADC control Block reset k.
RW
1
21
DAC
DAC control Block reset
RW
1
20
DSPC
DSP control block reset.
RW
1
19
INTC
Interrupt control Reset
RW
1
18
RTC
RTC block Reset
RW
1
17
PMU
PMU block Reset
RW
1
16..15
-
R
1
14
OTG
13
DSPM
SRAM dspmem reset
RW
1
12
TVEC
TVENC reset
RW
1
Reserved
OTG PHY reset
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
YUV2RGB block Reset.
RW
1
Reserved
RW
1
USB interface Reset
RW
1
BT656 interface Reset.
RW
1
MHA interface Reset.
RW
1
SD interface Reset.
RW
1
Flash interface Reset.
RW
1
Reserved
RW
1
DMA control block Reset
RW
1
--
Reserved
RW
1
1
-
Reserved
RW
1
0
SDR
Sdram Control Reg and sdram block Reset,
RW
1
11
YUV
10
-
9
USB
8
BT
7
MHA
6
SD
5
NAND
4
--
3
DMAC
2
Note: Write ‘0’ to reset the block
3.2 RTC/LOSC/Watch Dog/Timers Block Description
The chips have a low frequency oscillator, which can choose a built-in source or an
external one. Meanwhile the chip also has RTC (Real Time Clock) with alarm IRQ. The alarm
IRQ can wake up the system. For this purpose, the chip also has the watch dog circuit.
There are two Timers, namely, Timer0 and Timer1, which can only count down. The
clock of the Timer is P_Clk.
3.3 RTC/LOSC/Watch Dog Register List
RTC Base Address
Name
RTC
Physical Base Address
0x10018000
KSEG1 Base Address
0xB0018000
HOSC/CMU Register Address
Control Register Name
Offset Address
Description
RTC_CTL
0x0000
RTC Control Register
RTC_DHMS
0x0004
RTC Day Hour Minute and Second Register
RTC_YMD
0x0008
RTC Year Month Date Register
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
RTC_DHMSALM
0x000C
RTC Day Hour Minute and Second Alarm Register
RTC_YMDALM
0x0010
RTC Year Month Date Alarm Register
RTC_WDCTL
0x0014
RTC Watch Dog Control register
RTC_T0CTL
0x0018
RTC Timer0 Control register
RTC_T0
0x001C
RTC Timer0 Value
RTC_T1CTL
0x0020
RTC Timer1 Control register
RTC_T1
0x0024
RTC Timer1 Value
NOTE 1: When reading Register DAY_HOUR_MIN_SEC, YEAR_MON_DATE YEAR_MON_DATE,
the program can get the real value until reading the same value for 3 successive times.
NOTE 2: When setting the RTC, WD, COUNT0/1, the program shall disable the corresponding
enable bit at first and then enable it after setting the value.
3.3.1 RTC_CTL
RTC Control Register
Offset=0x0000
Bit
Name Description
31..12
R/W
Reset
-
Reserved
R
11
RST
RTC Reset
1: Normal
0: Reset
RW
1
10
-
Reserved
RW
0
RTC Leap Year bit
LEAP 1: leap year
0: non leap year
R
1
Reserved.
RW
0
9
8:7
--
0
6
EOSC
External Crystal OSC enable,
0: Disable, 1: Enable
RW
1
5
Low Frequency Clock Source Select,
CKSS 0: Built-in OSC (about 32K),
1: External Crystal OSC
RW
0
4
RTC Enable,
RTCE 0: Disable,
1: Enable
RW
1
RW
0
3
2HIE
2Hz IRQ Enable
0: Disable,
1: Enable
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
Alarm IRQ Enable,
0: Disable,
1: Enable (POR- RESET)
2
ALIE
1
2HIP 2Hz IRQ Pending bit, writing 1 to this bit will clear it
0
ALIP
Alarm IRQ Pending bit (POR- RESET),writing 1 to this bit will
clear it
RW
0
RW
0
RW
0
Note: To changing RTC register, it must set RTCE to “0” first and then set it back to “1”.
Alarm Irq in order to wake the system.
3.3.2 RTC_DHMS
RTC Day Hour Minute and Second Register
Offset=0x0004
Bit
Name
31:27
-
26:24
Description
R/W
Reset
Reserved
R
0
DAY
01H-07H
RW
-
23:21
-
Reserved
R
0
20:16
HOUR
00H-17H
RW
-
15:14
-
Reserved
R
0
13:8
MIN
00H-3BH
RW
-
7:6
-
Reserved
R
0
5:0
SEC
00H-3BH
RW
-
R/W
Reset
Binary code
Note: This register is reset by RST bit in RTC_Con Register.
3.3.3 RTC_YMD
RTC Year Month Date Register
Offset=0x0008
Description
Bit
Name
31
-
Reserved
R
0
CENT
00H-63H
RW
-
-
Reserved
R
0
30:24
23
Binary code
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
22:16
YEAR
00H-63H
RW
-
15:12
-
Reserved
R
0
MON
01H-0CH
RW
-
7:5
-
Reserved
R
0
4:0
DATE
01H-1FH
RW
-
11:8
Note: It can detect the leap year and month.
This register is reset by RST bit in RTC_Con Register.
3.3.4 RTC_DHMSALM
RTC Day Hour Minute and Second Alarm Register
Offset=0x000C
Bit
Name
31:21
-
20:16
Description
R/W
Reset
Reserved
R
0
HOURAL
00H-17H
RW
-
15:14
-
Reserved
R
0
13:8
MINAL
00H-3BH
RW
-
7:6
-
Reserved
R
0
5:0
SECAL
00H-3BH
RW
-
R/W
Reset
Binary code
3.3.5 RTC_YMDALM
RTC Year Month Date Alarm Register
Offset=0x0010
Description
Bit
Name
31:23
-
Reserved
R
0
22:16
YEARAL
00H-63H
RW
-
15:12
-
Reserved
R
0
11:8
MONAL
01H-0CH
RW
-
7:5
-
Reserved
R
0
4:0
DATEAL
01H-1FH
RW
-
Binary code
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
3.3.6 RTC_WDCTL
RTC Watch Dog Control Register
Offset=0x0014
Bit
Name
31:7
Description
-
Reserved
IRQP
5
SIGS
4
6
3:1
0
R/W Reset
R
0
Watch dog IRQ pending bit, writing 1 to this bit will clear it
RW
0
Watchdog Signal (IRQ or Reset-) Select. 0: Irq, 1: Reset-.
1: Send Reset signal when watchdog overflow.
0: Send IRQ signal when watchdog overflow.
RW
0
Watch Dog timer enable, when WD timer is enabled and the
WDEN WD timer overflows, an internal reset (WDRST-) is generated to RW
force the system into reset status and then reboot.
0
Watch Dog timer Clock Select,
WDCKS Clock Selected Watch Dog Length
000
1 KHz
176 ms
001
512 Hz
352 ms
010
128 Hz
1.4 s
CLKSEL
011
32 Hz
5.6 s
100
8 Hz
22.2 s
101
4 Hz
45 s
110
2 Hz
90 s
111
1 Hz
180 s
RW
0
RW
0
CLR
Clear bit, writing 1 to clear WD timer; it is cleared
automatically.
3.3.7 RTC_T0CTL
RTC Timer0 Control Register
Offset=0x0018
Bit Name
31:6
-
5
EN
4:3
-
Description
R/W Reset
Reserved
R
0
Timer 0 Enable
0: Disable, 1:Enable
RW 0
Reserved
R
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
Timer 0 Reload.
0: Not reload,1:Reload
2
RELO
RW 0
1
Timer0 Zero IRQ Enable
ZIEN When this bit is enabled, TIMER0_Zero_IRQ sent out the IRQ signal
until the pending bit was cleared.
0
ZIPD
RW 0
Timer0 IRQ Pending,
Writing 1 to clear this bit.
RW 0
Note: The Count only can count down. When the count is zero, IRQ will be sent.
3.3.8 RTC_T0
RTC Timer0 value Register
Offset=0x001C
Bit
Name
Description
31:24
--
Reserved
23:0
T0
Read or write current Timer0 value
R/W
Reset
R
0
RW
-
3.3.9 RTC_T1CTL
RTC Timer1 Control Register
Offset=0x0020
Bit
Name
31:6
-
5
Description
RW Reset
Reserved
Timer0 Enable
0: Disable,1:Enable
En
4:3
-
Reserved
2
RELO
1
Timer1 Zero IRQ Enable
ZIEN When this bit is enabled, TIMER1_Zero_IRQ sent out the IRQ signal
until the pending bit was cleared.
0
ZIPD
Timer1 Reload
0: Not reload,1:Reload
Timer1 IRQ Pending,
Writing 1 to clear this bit.
R
0
RW
0
R
0
RW
0
RW
0
RW
0
Note: The Count can only count down. When count becomes zero, IRQ will be sent.
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
3.3.10 RTC_T1
RTC Timer1 Value
Offset=0x0024
Bit
Name
31:24
23:0
Description
R/W
Reset
Read or write current Timer1 value
RW
0
Reserved
T1
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4 Interrupt Controller
4.1 Interrupt Controller Description
Interrupt controller supports 32 interrupt sources. It can generate five outputs as
interrupt requests 0, 1, 2, 3 and 4. Each of these outputs is connected to CPU core; the
following table shows the interrupt controller’s connections to CPU.
Table 1: Interrupt Controller Connects to CPU
Interrupt Controller Requests
CPU Interface
CPU Interrupt Request
Request 0
SI_INT[0]
IP2
Request 1
SI_INT[1]
IP3
Request 2
SI_INT[2]
IP4
Request 3
SI_INT[3]
IP5
Request 4
SI_INT[4]
IP6
Table 2: Interrupt Sources
Interrupt Number
Sources
Type
0
Reserved
High Level
1
Reserved
High Level
2
SD/MMC
High Level
3
MHA
High Level
4
USB
High Level
5
DSP
High Level
6
BT656
High Level
7
PC (Performance Counter)
High Level
8
2Hz/WatchDog
High Level
9
TIMER1
High Level
10
TIMER0
High Level
11
RTC
High Level
12
DMA
High Level
13
Key
High Level
14
External
High Level
15
Reserved
High Level
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16
SPI
High Level
17
IIC2
High Level
18
IIC1
High Level
19
UART2
High Level
20
UART1
High Level
21
ADC
High Level
22
DAC
High Level
23
SPDIF
High Level
24
NAND
High Level
25
Reserved
High Level
26
YUV2RGB
High Level
27
Reserved
High Level
28
Reserved
High Level
29
Reserved
High Level
30
Reserved
High Level
31
Reserved
High Level
4.2 Interrupt Controller Register List
Table 3: INTC Base Address
Name
Physical Base Address
KSEG1 Base Address
INTC
0x10020000
0xB0020000
Table 4: INTC Register Address
Register Name
Offset
Description
INTC_PD
0x0000
Interrupt Pending register
INTC_MSK
0x0004
Interrupt Mask register
INTC_CFG0
0x0008
Interrupt Config register 0
INTC_CFG1
0x000C
Interrupt Config register 1
INTC_CFG2
0x0010
Interrupt Config register 2
INTC_EXTCTL
0x0014
External Interrupt control and status register
4.2.1 INTC_PD
Interrupt Pending Register.
CPU can access to the status of interrupt sources by read this register.
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Offset=0x0000
Bit
31:0
Name
INTC_PD[n]
Description
Interrupt Pending bit. Interrupt name “n” is in
accordance with the Interrupt Sources Table.
0: Interrupt source n request is not active;
1: Interrupt source n request is active.
R/W
Reset
R
0
4.2.2 INTC_MSK
Interrupt MASK Register. CPU can enable or disable by writing this register.
Offset=0x0004
Interrupt Mask.
0: Interrupt is disabled.
1: Interrupt is enabled.
Bit
Name
31:27
-
Description
Reserved
R/W
Reset
R
0
26
YUV
YUV2RGB Interrupt Mask Bit
RW
0
25
--
Reserved
RW
0
RW
0
SPDIF Interface Interrupt Mask Bit
RW
0
24
NAND NAND Interface Interrupt Mask Bit
23
SPDF
22
DAC
DAC Interrupt Mask Bit
RW
0
21
ADC
ADC Interrupt Mask Bit
RW
0
20
URT1
URT1 Interrupt Mask Bit
RW
0
URT2 URT2 Interrupt Mask Bit
RW
0
IIC1 Interrupt Mask Bit
RW
0
19
18
IIC1
17
IIC2
IIC2 Interrupt Mask Bit
RW
0
16
SPI
SPI Interrupt Mask Bit
RW
0
15
--
Reserved
RW
0
14
EXT
External IRQ Interface Interrupt Mask Bit
RW
0
13
KEY
KEY Interrupt Mask Bit
RW
0
12
DMA DMA Interrupt Mask Bit
RW
0
11
RTC
RTC Interrupt Mask Bit
RW
0
10
T0
T0 Interrupt Mask Bit
RW
0
9
T1
T1 Interrupt Mask Bit
RW
0
8
WD
Watchdog Interrupt Mask Bit/2Hz
RW
0
7
PCNT Performance Count Interrupt Mask Bit
RW
0
6
BT
BT Interrupt Mask Bit
RW
0
5
DSP
DSP Interrupt Mask Bit
RW
0
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4
USB
USB Interrupt Mask Bit
RW
0
3
MHA MHA Interrupt Mask Bit
RW
0
2
SD
SD Interface Interrupt Mask Bit
RW
0
1
--
Reserved
RW
0
0
-
Reserved
RW
0
4.2.3 INTC_CFGx
Interrupt Config Registers. CPU can assign any interrupt source to one of the five interrupt
requests.
INTC_CFG0: Offset=0x0008 INTC_CFG1: Offset=0x000C
INTC_CFG2: Offset=0x0010
INTC_CFGx List
Bit
INTC_CFG2[n]
0
0
0
0
1
INTC_CFG1[n]
0
0
1
1
x
INTC_CFG0[n]
0
1
0
1
x
The interrupt request assigned
0
1
2
3
4
Name
Description
31:27
-
Reserved
26
YUV
25
R/W
Reset
R
0
YUV2RGB Interrupt CFGx Bit
RW
0
--
Reserved
RW
0
24
NAND
NAND Interface Interrupt CFGx Bit
RW
0
23
SPDF
SPDIF Interface Interrupt CFGx Bit
RW
0
22
DAC
DAC Interrupt CFGx Bit
RW
0
21
ADC
ADC Interrupt CFGx Bit
RW
0
20
URT1
URT1 Interrupt CFGx Bit
RW
0
19
URT2
URT2 Interrupt CFGx Bit
RW
0
18
IIC1
IIC1 Interrupt CFGx Bit
RW
0
17
IIC2
IIC2 Interrupt CFGx Bit
RW
0
16
SPI
SPI Interrupt CFGx Bit
RW
0
15
--
Reserved
RW
0
14
EXT
External IRQ Interface Interrupt CFGx Bit
RW
0
13
KEY
KEY Interrupt CFGx Bit
RW
0
12
DMA
DMA Interrupt CFGx Bit
RW
0
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11
RTC
RTC Interrupt CFGx Bit
RW
0
10
T0
T0 Interrupt CFGx Bit
RW
0
9
T1
T1 Interrupt CFGx Bit
RW
0
8
WD
WatchDog Interrupt CFGx Bit/2Hz
RW
0
7
PCNT
Performance Count Interrupt CFGx Bit
RW
0
6
BT
BT Interrupt CFGx Bit
RW
0
5
DSP
DSP Interrupt CFGx Bit
RW
0
4
USB
USB Interrupt CFGx Bit
RW
0
3
MHA
MHA Interrupt CFGx Bit
RW
0
2
SD
SD Interface Interrupt CFGx Bit
RW
0
1
--
Reserved
RW
0
Reserved
RW
0
0
-
4.2.4 INTC_EXTCTL
External Interrupt Control and Status Register.
Offset=0x0014
Bits
Name
31:27
-
Read/Write
Reset
R
0
RW
00
E1TYPE
External Interrupt 1 Type
00 High level active.
01 Low level active.
10 rising edge-triggered.
11 Falling edge-triggered.
RW
0
E1EN
Enable External interrupt 1
0 Disable
1 Enable
R
0
R/W
-
26:25
24
23:17
-
16
E1PD
Description
Reserved
Reserved
External Interrupt 1 Pending
0 External interrupt source 0 is not active.
1 External interrupt source 0 is active.
Write 1 to the bit will clear it. If external interrupt
source 1 is edge-triggered, this bit must be cleared
by software after detected.
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15:11
R/W
0
E0TYPE
External interrupt 0 type
00 High level active.
01 Low level active.
10 rising edge-triggered.
11 Falling edge-triggered.
R/W
0
E0EN
Enable external interrupt 0
0 Disable
1 Enable
R
0
R/W
0
10:8
7:1
-
0
E0PD
Reserved.
External Interrupt 0 Pending
0 External interrupt source 0 is not active.
1 External interrupt source 0 is active.
Write 1 to the bit will clear it. If external interrupt
source 0 is edge-triggered, this bit must be cleared
by software after detected.
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
5 PMU/DC-DC Converter
5.1 Description
The PMU includes:
z ATJ2256 & ATJ2257B have only one DC/DC converter working in buck & boost
mode. Their output voltage is 1.6V, which can be programmed. For ATJ2257, it has
two DC/DC converters; both can work in buck mode, and the output voltages are
3.1V and 1.6V, and programmable.
z Two regulators, whose output voltages are 3.1V and 1.6V, can be programmed.
z A bias current generator.
z An Oscillator, outputs a 600KHz for DC-DC converters and a 32KHz for RTC.
z
z
z
6bits low speed ADC, whose input range is from 0V to 3.1V,monitors remote
control signal.
Battery charger, all support Li+ battery
VCC voltage detector, VDD voltage detector, Power OK signal (PWROK) generator.
PIN in PMU
z DC-DC1 PIN: LX_VCC, IO_VCC. (for ATJ2257 only)
z DC-DC2 PIN: LX_VDD, IO_VDD.
z High voltage regulator input and output PIN: respectively DC5V and VCC.
z Low voltage regulator output PIN: VDD
z Battery input/output PIN: BAT
z DC-DC NMOS ground: PGND
z Remote controller ADC Input: REM_CON
z ECL PFM DC/DC PIN: BL_NDR
z External power PIN: VCCOUT
z
z
z
z
PMU Working Mode
Li+ Battery, 2 Inductor (for ATJ2257 only)
Li+ Battery, 1 Inductor for VDD
Li+ Battery, No Inductor
External power
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5.2 Register List
CMU Block Base Address
Module name
Physical Bass Address
KSEG1 Base Address
PMU
0x10000000
0xB0000000
Configuration Registers Offset
Offset
Register Name
Description
0x00
PMU_CTL
PMU Control Register
0x04
PMU_LRADC
PMU Low Resolution ADC Register
0x08
PMU_CHG
PMU Charge Control Register
0x40
PMU_USBPDR
USB Power Detect Register
5.3 Register Description
5.3.1 PMU_CTL
DC/DC Converter and Regulator’s register
Offset=0x0000
Bits
Name
Description
R/W
Reset
R/W
1
R/W
0x7
LBRM
Low Battery Reset Mask bit
LB_ mask, “1”,OPEN
30:28
VCVS
VCC Voltage Set Register
3.3V*
111
3.2V
110
3.1V
101
3.0V
100
2.9V
011
2.8V
010
2.7V
001
2.6V
000
27
LBNM
Low Battery Non-masked Interrupt Mask bit
LBNMI_ mask, “1”, OPEN
R/W
1
VDD Voltage Set Register
2.0V
111
1.9V
110
R/W
0x5
31
26:24
VDVS[3:1]
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1.8V*
1.7V
1.6V
1.5V
1.4V
1.3V
101
100
011
010
001
000
VCDE
VCC Detect Enable
“1”, enable
R/W
0
22:20
VCVD
VCC Voltage Detect Register
111
2.9V
110
2.8V
101
2.7V
100
2.6V
011
2.5V
010
2.4V
001
2.3V
000
2.2V
R/W
0x5
19
VDDE
VDD Detect Enable
“1”, enable
R/W
0
18:16
VDVD
VDD voltage Detect Register
1.8V
111
1.7V
110
1.6V
101
1.5V
100
1.4V
011
1.3V
010
1.2V
001
1.1V
000
R/W
0x3
15
-
Reserved
R/W
0
VCOE
VCCOUT Enable
1: Enable
0: Disable
R/W
0
BATADC
BATADC Enable
1: Enable
0: Disable
R/W
0
12
REMADC
REMADC Enable
1: Enable
0: Disable
R/W
0
11:10
IBIAS
Current bias control
R/W
0x2
23
14
13
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
00: 0.92uA
01: 0.96uA
10: 1.0uA
11: 1.04uA
9:8
7
OSCFREQ
DC1M
6
5-3
DC2M
BLCS
2
VDV0
1:0
PWRM
PMU Oscillator Frequency Set
Freq.
Current
00
470KHz
1.5uA
01
600kHz
2.0uA
10
750kHz
2.5uA
11
880kHz
3.0uA
R/W
Ox1
DCDC1 Mode
1:PWM
0:PFM
R/W
1
DCDC Mode
1: PWM
0: PFM
R/W
1
R/W
0x101
R/W
0
R
0x3
Back Light Current Set
BLCS[3..0]
BL_FB
0000
0.4V
0001
0.39
0010
0.38
0011
0.37
0100
0.36
0101
0.35
0110
0.34
0111
0.33
1000
0.32
1001
0.31
1010 *
0.30
1011
0.29
1100
0.28
1101
0.27
1110
0.26
1111
0.25
BLCS[3..1] is mapped PMU_CTL [5..3]
BLCS[0] is mapped PMU_CHG[6]
VDD Voltage Set bit0
1: +50mV for VDD
Power Mode
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
1*----Li+
Note: bit0 for test
5.3.2 PMU_LRADC
Low Resolution ADC Data Register
Offset=0x0004
Bits
Name
Descriptions
R/W
Reset
31
DC5V
DC5V available for charge.
1:available
0:unavailable
R
0
30
RemADC_Average
RemADC Average slect
0—— no average
1—— 2 times average
R/W
0
29-28
RemADCSample
Remote ADC sample frequency select
00——64Hz
01——128Hz
10——256Hz
11——512Hz
R/W
00
27-22
REMOADC6
Remote Control 6bit Voltage ADC
Range:0-AVCC
R
x
21-16
BATADC6
Battery 6bit Voltage ADC
Range:
Li+:2.1-4.5V
R
-
15-14
Reserved
R
0
13-8
-
---
Reserved
R
-
7-0
-
Reserved
R
0
5.3.3 PMU_CHG
PMU Charger Control and Status register
Offset=0x0008
Bits
31
Name
EN
Description
R/W
Reset
Enable Charge Circuit
1: Enable charge circuit
0: Disable charge circuit. Charge circuit will not
R/W
0
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work, and consume little power.
30-28
CURRENT
27
STAT
Charge Current Configure
000:50mA
001:100mA
010:150mA
011:200mA
100:250mA
101*:300mA
110:400mA
111:500mA
R/W
0x5
Charging Status.
0: not charging, 1: charging.
R
0
Charging phase
00 Reserved
01 Pre-charging
10 Constant current
11 Constant voltage
The two bits will be available only when bit 31
of this register is set, or will be always read 00.
R
00
26-25
CHGPHASE
24
-
Reserved
R/W
0x1
23:20
--
Reserved
R/W
0
19-16
--
Reserved
R/W
1
15
PBLS
PWM OR BL_NDR select
0: BL_NDR output
1: PWM pulse output
R/W
0
14
PPHS
PWM FHASE SELECT, this bit in effect only when
PBLS is 1
0: LOW IS SELECT
1: HIGH IS SELECT
R/W
0
13
-
reserved
R/W
0
R/W
01111
R/W
0
12-8
7
PDUT
-
PWM Back Light Duty
00000
00001
00010
.
11110
11111
reserved
0/32
1/32
2/32
30/32
31/32
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
Back Light Current Set bit 0
R/W
0
TMPSET
Temperature Monitor’s Maxim Temperature
Setting:
55C
11
50C
10
45C *
01
40C
00
R/W
1
LBNMIVS
Low Battery Non-mask Interrupt Voltage Setting
Li+
00*
2.9V
01
3.1V
10
3.3V
11
3.5V
R/W
0
Low Battery Reset Voltage setting
Li+
00
2.7V
01
2.9V
10
3.1V
11
3.3V
R/W
1
6
BLC0
5-4
3-2
1-0
LBRVS
5.3.4 PMU_USBPDR
USB Power Detect Register
offset: 0x0040
Bits
Name
Description
R/W Reset
31:12 -
reserved
R/W 0
11
bvalid
USB bvalid. When vbus is higher than 1.65V, this signal is 1.
R
x
10
vbus
Vbusvalid. The vbus detection threshold is determined by
R
vbusth, when vbus is higher than threshold, vbusvalid will be 1.
x
9:8
ls
USB linestate[1:0].
R
x
7:4
-
reserved
R/W 0
3
dmpuen 500Kohm DM pull up resistor enable.
R/W 0
2
dppuen 500Kohm DP pull up resistor enable.
R/W 0
1
dmpddis DM pull down disable.
R/W 0
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0
dppddis DP pull down disable.
R/W 0
This register used for USB vbus detection threshold setting, and charger/USB Host
detection.
According to USB specification, USB host should supply VBUS, the voltage should be
4.75V~5.25V, and USB function should work only if VBUS is higher than 4.4V (for bus
powered USB function). However, in this application, some exception may happen. For
example, some host cannot supply VBUS voltage between 4.75V~5.25V, or VBUS ripple is
over specification; in these cases, adjustable VBUS detection threshold will promote the
compliance of USB function.
Another application requirement is that the firmware shall be notified whether it is
connecting to a USB host or a USB charger. To achieve this, assuming the firmware enabled
vbus wakeup function, then once vbus wakeup interrupt happens, it shows a USB host or a
USB charger connecting to us. The firmware disables DP and DM pulldown, and enables
DP/DM 500Kohm pullup, then check linestate[1:0] status, if 00, it is connecting to a USB
Host, otherwise, to a charger.
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
6 32-BIT RISC Core
The core follows MIPS 4KEc SPEC. This Chapter describes the features of RISC Core
which are not implemented or different from MIPS 4KEc SPEC.
6.1 Coprocessor 0 Description
In the MIPS architecture, CP0 is responsible for the virtual-to-physical address
translation and cache protocols, the exception control system, the processor’s diagnostics
capability, the operating modes (kernel, user, and debug), and whether interrupts are
enabled or disabled.
ATJ2256/ATJ2257/ATJ2257B DATASHEET
7 SDRAM Interface
7.1 SDRAM Interface Description
SDRAM interface can support both SDRAM (Synchronous DRAM) and Mobile SDRAM. It
has the following features:
¾ Supports SDRAM and Mobile SDRAM
¾ Separate I/O power supply supporting 1.8V, 2.5V and 3.3V
¾ Supports 3.3V SDRAM of clock frequency up to PC100
¾ Supports 3.3V SDRAM of capacity up to 512Mbits
¾ Supports 3.3V/2.5V/1.8V Mobile SDRAM of Clock frequency up to PC100
¾ Supports 3.3V/2.5V/1.8V Mobile SDRAM of capacity up to 512Mbits
¾ Thirteen address signals and two bank address signal
¾ Access to SDRAM in Byte, Half or Word are supported
¾ Supports up to 23 address bits, 13 for row address, and 10 for column address
¾ Three clock sources to be chosen for different application
¾ Priority of transferring through special channel or AHB bus is programmable
¾ Supports random read or write operation
7.2 SDRAM Interface Register List
SDR Base Address
Name
Physical Base Address
KSEG1 Base Address
SDR
0x10070000
0xB0070000
SDRAM Interface Configuration Registers
Register Name
Offset
Description
SDR_CTL
0x0000
SDRAM control
SDR_ADDRCFG
0x0004
SDRAM addresses configure
SDR_EN
0x0008
SDRAM Enable
SDR_CMD
0x000C
SDRAM command
SDR_STAT
0x0010
SDRAM status
SDR_RFSH
0x0014
SDRAM Auto Refresh control register
SDR_MODE
0x0018
Mode register of SDRAM
SDR_MOBILE
0x001C
Extended Mode Register of Mobile SDRAM
ATJ2256/ATJ2257/ATJ2257B DATASHEET
7.2.1 SDR_CTL
SDRAM Control Register
Offset=0000
Bit
Name
31:21
-
20
19:18
17:16
15
14:12
9:8
7
6:4
VPDE
PADDRV
VPDET
-
PRIO
BUSW
-
CAP
Description
R/W
Reset
Reserved
R/W
0
SDRAM VP Voltage Detect enable
0 Detect circuit disable
1 Detect circuit enable
R/W
0x0
SDRAM Pad Drive Control
00
Reserved
01
Reserved
10
Reserved
11
3.3V
R/W
0x0
SDRAM_VP Voltage Detect
00
Reserved
01
Reserved
10
Error
11
3.3V
R/W
Depend on
SDRAM_VP
pin
Reserved
R/W
0
BUS & Special DMA Priority
Bus access can halt Equal or Lower Priority
Special DMA, "0" is the highest:
0: BUS>DMA4>DMA5>DMA6>DMA7
1: DMA4>BUS>DMA5>DMA6>DMA7
2: DMA4>DMA5>BUS>DMA6>DMA7
3: DMA4>DMA5>DMA6>BUS>DMA7
4~7:DMA4>DMA5>DMA6>DMA7>BUS
0x0
SDRAM Bus width
00
8bit
01
16bit
10
Reserved
11
Reserved
0x1
Reserved
R/W
0
SDRAM Capacity
000
16Mbits
001
32Mbits
010
64Mbits
R/W
0x0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
011
100
101
111
3:2
1:0
-
TYPE
128Mbits
256Mbits
512Mbits
Reserved
Reserved
R/W
0
SDRAM Type:
00
SDRAM
01
Mobile SDRAM
Others reserved
R/W
0x0
7.2.2 SDR_EN
SDRAM Enable Register
Offset=0x0008
Bit
Name
31:1
-
EN
0
Description
R/W
Reset
Reserved
R/W
0
SDRAM Enable:
Disable
Enable
R/W
0x0
7.2.3 SDR_CMD
SDRAM Command Register
Offset=0x0010
Bit
31:1
6
15:
0
Name
-
CMD
Description
Reserved
Writing this register to make the responded
command of SDRAM to be issued.
CMD ID
CMD action
10h
self refresh
12h
exit self refresh
14h
pre-charge all
18h
auto refresh
20h
OCD decrease by 1
22h
OCD increase by 1
40h
burst read
R/W
Reset
R/W
0
RW
0x00
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44h
burst write
80h
command inhibit
84h
power down
88h
exit power down
A0h
power up
A2H
MRS
A4H
EMRS
Other value reserved.
7.2.4 SDR_STAT
SDRAM Status Register
Offset=0x0014
Bit
31:1
0
Name
Description
R/W
Reset
-
Reserved
R
0
ICF
Initiation Completed Flag,
0
not completed
1
completed
Write 1 to clear it.
R/W
0x0
7.2.5 SDR_AUTORFC
SDRAM Auto Refresh Cycles Register
Offset=0018
Bit
31:0
Name
ARFC
Description
Auto Refresh Cycles
R/W
Reset
R/W
0xaf
7.2.6 SDR_MODE
SDRAM Mode Register
Offset=0x0018
Bit
Name
Description
31:16
-
Reserved
15:13
BA
Bank Address.
When setting SDRAM Mode Register, the
R/W
R
Reset
0
R/W
0x0
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three bits must always be 0.
12:10
-
Reserved
9
WBM
Write Burst Mode
0 burst write
1 Reserved
R/W
0x0
8:7
--
Reserved
R/W
0x0
CL
CAS Latency
A6 A5 A4 Latency
010 2
011 3
Others reserved.
R/W
0x2
BT
Burst Type
A3 Burst Type
0 Sequential
1 Reserved
R/W
0x0
BL
Burst Length
A2 A1 A0 BL
000
reserved
001
reserved
010
4
011
8
111
reserved
Others reserved
R/W
0x3
6:4
3
2:0
R/W
0
7.2.7 SDR_MOBILE
SDRAM Extended Mode Register
Offset=0x001C
Bit
Name
31:16
-
Description
R/W
Reset
Reserved
R/W
0
R/W
0x2
15:13
BA
Bank Address.
When setting SDRAM Extended Mode Register, these
three bits must always be 01.
12:7
-
Reserved
R/W
0
DS
Driver Strength
A6 A5
0 0 Full Strength Driver3
0 1 Half Strength Driver
R/W
0x0
6 :5
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1
1
4:3
2:0
0
1
Quarter Strength Driver
One-eight Strength Driver
TCSR
Temperature Compensated Self Refresh
R/W
0x00
PASR
Partial Array Self Refresh Coverage
A2 A1 A0
0 0 0 Full Array (All Banks)3
0 0 1 Half Array (BA1 = 0)
0 1 0 Quarter Array (BA1 = BA0 = 0)
0 1 1 Reserved
1 0 0 Reserved
1 0 1 One-eighth array (BA1 = BA0 = Row Address
MSB = 0)
1 1 0 One-sixteenth array (BA1 = BA0 = Row
Address MSB = 0)
1 1 1 Reserved
R/W
0x00
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8
DMA/Bus Arbiter
8.1 Description
The chips’ DMA controller contains 8 tasks, which are divided into two types, bus DMA
and special channel DMA. System bus adopts the subset of AMBA bus protocol.
8.1.1 DMA Architecture
DMA controller in the chips is a special master, for it has 4 independent special
channel to high speed AHB slaves, and these 9 special slaves have two access port, so the
slave has to decide which port has the higher priority. In the slave there is a reg to set which
is higher priority.
Each DMA task can be set the priorities.
DMA0~DMA3 can transfer through bus only, DMA4~DMA7 can only transfer through
the special channel.
DRQ Trig Source
Drq
source
DRQ_Trig
Field(5bit)
DRQ_line
connect
Simultaneous
Task num
Fifo
depth
Fifo
Wide
Operation
wide
Block/
Demand
Uart0_t
0
DRQ0
1(DST)
8
8
8/16/32
B
Uart0_r
1
DRQ1
1(SRC)
8
8
8/16/32
B
Uart1_t
2
DRQ2
1(DST)
8
8
8/16/32
B
Uart1_r
3
DRQ3
1(SRC)
8
8
8/16/32
B
SPDIF_t
4
DRQ4
1(DST)
8
24
32
B
SPDIF_r
5
DRQ5
1(SRC)
8
24
32
B
DAC/I2S_t
6
DRQ6
1(SRC|DST)
4|16
24
32
D
ADC/I2S_r
7
DRQ7
1(SRC)
16
24
32
D
SPI_t
8
DRQ8
1(DST)
8
16
16/32
B/D
SPI_r
9
DRQ9
1(SRC)
8
16
16/32
B/D
PCM_t
10
DRQ10
1(DST)
8
16
16/32
B/D
PCM_r
11
DRQ11
1(SRC)
8
16
16/32
B/D
reserved
12~15
note
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SDRAM
16
DRQ16
>2(SRC&DST)
DSPMEM
17
DRQ17
>2(SRC&DST)
NOR
18
DRQ18
Reserved
19
NAND
20
BT656_R
-
8/16/32
-
-
-
8/16/32
-
>2(SRC&DST)
-
-
8/16/32
-
DRQ20
1(SRC|DST)
8
32
8/16/32
B/D
21
DRQ21
1(SRC)
16
32
8/16/32
B/D
SD
22
DRQ22
1(SRC|DST)
16
32
8/16/32
B/D
USB
23
DRQ23
1(SRC|DST)
2k
32
8/16/32
D
YUV
24
DRQ24,25
2(SRC&DST)
8
32
8/16/32
B/D
BT656_T
26
DRQ26
1(DST)
16
32
8/16/32
B/D
Reserved
25~31
-
Note: IIC0,IIC1,SPI,use only IRQ mode.
If selecting the reserved DRQ, DRQ is always valuable.
In normal application, DAC is DRQ DST and ADC is DRQ SRC, which FIFO depth is 16.
For auto test, DAC is DRQ SRC when DAC_Debug FIFO depth is 4, and DMA Burst Length
should be single. ADC debug data cannot be accessed by DMA.
8.2 Register List
DMA Base Address
Module name
Physical Bass Address
KSEG1 Base Address
DMA
0x10060000
0xB0060000
Bus Controller and DMA Control Register Address
Control register name
Offset
Description
DMA_CTL
0x0000
DMA Control Register
DMA_IRQEN
0x0004
DMA IRQ Enable
DMA_IRQPD
0x0008
DMA IRQ Pending
General DMA Channel Registers Block Base Address
General DMA Channel
REGS BLOCK Base Address Offset
DMA0
0x0100
DMA1
0x0120
DMA2
0x0140
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DMA3
0x0160
DMA4
0x0180
DMA5
0x01A0
DMA6
0x01C0
DMA7
0x01E0
General DMA Channel Configuration Registers
Register Name
Offset From Block Base Address
Description
DMA_MODE
0x0000
Mode register
DMA_SRC
0x0004
Source address
DMA_DST
0x0008
Destination address
DMA_CNT
0x000C
Count byte
DMA_REM
0x0010
Remain count byte
DMA_CMD
0x0014
Start DMA command
8.2.1 DMA_CTL
DMA Control Register
Offset=0x0000
Bit
Name
31:24
-
23
RST7
22
Description
R/W Reset
Reserved
R
0
Write “1” to reset the relevant DMA task
RW
0
RST6
Write “1” to reset the relevant DMA task
RW
0
21
RST5
Write “1” to reset the relevant DMA task
RW
0
20
RST4
Write “1 to reset the relevant DMA task
RW
0
19
RST3
Write “1” to reset the relevant DMA task
RW
0
18
RST2
Write “1” to reset the relevant DMA task
RW
0
17
RST1
Write “1” to reset the relevant DMA task
RW
0
16
RST0
Write “1” to reset the relevant DMA task
RW
0
15:4
-
R
0
Reserved
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3:0
CPU Priority
CPU can halt Equal or Lower Priority DMA, “0” is the highest,
it is shown as follows:
0: CPU>DMA0>DMA1>DMA2>DMA3
CPUPRIO
1: DMA0>CPU>DMA1>DMA2>DMA3
2: DMA0>DMA1>CPU>DMA2>DMA3
3: DMA0>DMA1>DMA2>CPU>DMA3
4~15: DMA0>DMA1 >DMA2>DMA3>CPU
RW
0
8.2.2 DMA_IRQEN
DMA IRQ Enable
Offset=0x0004
Bit
31:16
Name
Description
R/W
-
Reserved
15
D7HE
DMA7 Half-transfer Complete
IRQ Enable.
14
D7TE
DMA7 Transfer Complete
IRQ Enable.
RW
13
D6HE
DMA6 Half-transfer Complete
IRQ Enable.
RW
12
D6TE
DMA6 Transfer Complete
IRQ Enable.
RW
11
D5HE
DMA5 Half-transfer Complete
IRQ Enable.
RW
10
D5TE
DMA5 Transfer Complete
IRQ Enable.
RW
9
D4HE
DMA4 Half-transfer Complete
IRQ Enable.
RW
8
D4TE
DMA4 Transfer Complete
IRQ Enable.
RW
7
D3HE
DMA3 Half-transfer Complete
IRQ Enable.
RW
6
D3TE
DMA3 Transfer Complete
IRQ Enable.
RW
5
D2HE
DMA2 Half-transfer Complete
IRQ Enable.
RW
Reset
R
0
RW
0
0
0
0
0
0
0
0
0
0
0
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4
D2TE
DMA2 Transfer Complete
IRQ Enable.
RW
3
D1HE
DMA1 Half-transfer Complete
IRQ Enable.
RW
2
D1TE
DMA1 Transfer Complete
IRQ Enable.
RW
1
D0HE
DMA0 Half-transfer Complete
IRQ Enable.
RW
0
D0TE
DMA0 Transfer Complete
IRQ Enable.
RW
0
0
0
0
0
8.2.3 DMA_IRQPD
DMA IRQ Pending
Offset=0x0008
Bit
Name
31:16
-
15
Description
R/W
Reset
Reserved
R
0
D7HP
DMA7 Half-transfer Complete
IRQ Pending.
RW
0
14
D7TP
DMA7 Transfer Complete
IRQ Pending.
RW
0
13
D6HP
DMA6 Half-transfer Complete
IRQ Pending.
RW
0
12
D6TP
DMA6 Transfer Complete
IRQ Pending.
RW
0
11
D5HP
DMA5 Half-transfer Complete
IRQ Pending.
RW
0
10
D5TP
DMA5 Transfer Complete
IRQ Pending.
RW
0
9
D4HP
DMA4 Half-transfer Complete
IRQ Pending.
RW
0
8
D4TP
DMA4 Transfer Complete
IRQ Pending.
RW
0
7
D3HP
DMA3 Half-transfer Complete
IRQ Pending.
RW
0
6
D3TP
DMA3 Transfer Complete
IRQ Pending.
RW
0
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5
D2HP
DMA2 Half-transfer Complete
IRQ Pending.
RW
0
4
D2TP
DMA2 Transfer Complete
IRQ Pending.
RW
0
3
D1HP
DMA1 Half-transfer Complete
IRQ Pending.
RW
0
2
D1TP
DMA1 Transfer Complete
IRQ Pending.
RW
0
1
D0HP
DMA0 Half-transfer Complete
IRQ Pending.
RW
0
0
D0TP
DMA0 Transfer Complete
IRQ Pending.
RW
0
Note: For pending bit, write “1” to clear it.
8.2.4 DMA_MODEx
DMAx Mode Register
Offset=0x0100+x*0x0020
Note: In the register description, the postfix “_x” means each task has the register.
Bit
Name
Description
R/W Reset
Destination Burst Length.
*: Burst must not cross a 1kB address boundary.
000: single
001: reserved
010: reserved
011: incr4
100: reserved
31:29 DBURLEN
RW 0
101: incr8
110: reserved
111: reserved
Mainly for SDRAM.
If DST_Burst_Len is burst 4or8, DST_Dir must be 0, DST_Fix
must be 0, DST_DSP must be 0, DST_Colloum_Mode must
be 0.
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RELO
DMA Reload Bit
When DMA transmission finishes, DMA starts again with
RW 0
current setting.
1: Reload, 0: can NOT reload
DDSP
Destination DSP mode
1: enable DSP mode
0: disable DSP mode
Valuable when DST_Collum_Mode =0 and
DST_Tran_Wide=0, DST_Burst_Len=0, DST_Fix=0.
RW 0
25
DDIR
Destination address direction;
0: increase, 1: decrease
Valuable when DST_Fix=0 .
If DST_Burst_Len is burst 4or8, DST_Dir must increase.
RW 0
24
DFXA
Destination Fix Address(IO) or Not;
0: Not fixed, 1: Fix
RW 0
DCOL
Destination Column Mode
0: enable row mode
1: Enable column mode
Valuable when DST_Burst_Len=0 and DST_Fix=0.
RW 0
Destination DRQ Trig Source
RW 0
28
27
26
23:19 DTRG
Destination Transfer wide:
00: 8
18:17 DTRANWID 01: 16
10: 32
11: reserved
16
DFXS
RW 0
Destination Fix Size bit
0: not fixed, 1: fixed
If DST_FixedSize=0, DMA will transfer in 8bit mode when
remain counter is less than DST_Tran_Wide.
If DST_FixedSize=1, DMA will always transfer in
DST_Tran_Wide.
RW 0
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15:13 SBURLEN
Source Burst Length.
*: Burst must not cross a 1kB address boundary.
000: single
001: reserved
010: reserved
011: incr4
100: reserved
101: incr8
110: reserved
111: reserved
Mainly for SDRAM.
If SRC_Burst_Len is burst 4or8, SRC_Dir must be 0,
SRC_Fix must be 0, SRC_DSP must be 0,
SRC_Colloum_Mode must be 0.
12
-
Reserved
SDSP
Source DSP Mode
1: enable DSP mode
0: disable DSP mode
Valuable when SRC_Collum_Mode =0 and
SRC_Tran_Wide=0, SRC_Burst_Len=0, SRC_Fix=0.
RW 0
SCOL
Source Column Mode
0: enable row mode
1: enable column mode
Valuable when SRC_Burst_Len=0, SRC_Fix=0.
RW 0
9
SDIR
Source address direction;
0: increase, 1: decrease
Valuable when SRC_Fix=0.
If SRC_Burst_Len is burst 4or8 SRC_Dir must increase.
RW 0
8
SFXA
Source Fix Address (IO) or not (MEM)
0: not fixed, 1:fixed
RW 0
7:3
STRG
DRQ trig source:
can select always trig
RW 0
2:1
Source Transfer Width:
00: 8
STRANWID 01: 16
10: 32
11: reserved
11
10
RW 0
0
RW 0
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0
Source Fix Size
0: not fixed, 1: fixed
If SRC_FixedSize=0, DMA will transfer in 8bit mode when
remain counter is less than DST_Tran_Wide.
If SRC_FixedSize=1, DMA will always transfer in
SRC_Tran_Wide.
SFXS
RW 0
8.2.5 DMA_SRCx
DMAx SRC Register
Offset=0x0104+x*0x0020
Bit
Name
31:0
SRC
Description
DMA Source Address
R/W
Reset
RW
0
8.2.6 DMA_DSTx
DMAx DST Register
Offset=0x0108+x*0x0020
Bit
Name
31:0
DST
Description
DMA Destination Address
R/W
Reset
RW
0
8.2.7 DMA_CNTx
DMAx CNT Register
Offset=0x010C+x*0x0020
Bit
Name
31:20
-
19:0
CNT
Description
R/W
Reset
Reserved
R
0
DMA Count byte
RW
0
8.2.8 DMA_REMx
DMAx Remain Register
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Offset=0x0110+x*0x0020
Bit
Name
31:20
-
19:0
REMAIN
Description
Reserved
DMA Remain Byte
R/W
Reset
-
0
RW
0
8.2.9 DMA_CMDx
DMAx CMD Register
Offset=0x0114+x*0x0020
Bit
Name
31:6
-
Description
R/W Reset
Reserved
-
0
WAIT
Wait state
0~7
Wait bit is valuable only in Block mode.
RW
0
4
BLOC
DMA block mode enable
0: demand mode
1: block mode
There is no block mode for special DMA.
RW
Special DMA4 and 5 only support burst transmission of one
side at most; both sides burst transmission is not supported.
Special DMA6 and 7 only support single to single
transmission.
0
3:2
-
7:5
1
0
Reserved
PAUS
Write “1” to Pause the relevant DMA task.
When the task pauses, it will not request system and
response to the relevant DRQ sources.
RW
0
STAR
After DMA Transmission finishes, the bit will be cleared. The
low-go-high edge of this bit will load SRC start address, DST
start address, byte count into current working counters.
RW
0
Note: SpecDMA cannot work normally in non-single-single mode
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9
SD/MMC Interface
9.1 Description
SD/MMC Interface is based on MMC card SPEC 4.1 and is compatible with SD memory card
physical layer SPEC version 1.01. Multimedia Card/SD is a serial input/output interface to
send command and receive data. Its features are as follows:
1. Supports SD memory card, MMC memory card.
2. Supports 1bit, 4bit, 8bit, bus mode.
3. Clock max rate up to 52MHz.
4. Data transfer FIFO and DMA control.
5. Read /Write CRC Status Hardware checked automatically.
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10NAND FLASH/SMC State Machine
10.1 Description
The general purpose Nand Flash Interface controller is a State Machine configurable
interface to external Nand Flash. The flash data bus width only support 8bit .
The flash State machine provides automatic timing control for the using data read and write
access signal line. The Controller will transfer the data between the Int_RAM Mem and
ext_Flash Mem by AHB or DMA.
The Controller module can monitor the relatively interval transitions of the NAND flash
device’s Ready/Busy signal. This include an interrupt that can monitor the rising edge of the
busy signal and that can be set generate a interrupt if the NAND flash device hang up, etc.
The forward error correction module is used to provide Actions GL5006 applications with a
reliable interface to various storage media, especially storage media that would otherwise
have nacceptable bit error rates. The ECC module comprises two different error correcting
code processors:
• 8-BCH correcting encoder/decoder.
• 12-BCH correcting encoder/decoder.
The purpose of the 8-BCH decoder is to process a coded block (data block followed by
“parity” check data) to determine if there is an error and, if there are errors, where they are
located and how to correct them. The purpose of the BCH encoder is to read a block of
512-symbols from RAM, alculate and append 13-parity symbols to form a 516-symbol
BCH-codeword.
The purpose of the 12-BCH decoder is to process a coded block (data block followed by
“parity” check data) to determine if there is an error and, if there are errors, where they are
located and how to correct them. The purpose of the BCH encoder is to read a block of
512-symbols from RAM, alculate and append 20-parity symbols to form a 516-symbol
BCH-codeword.
Six byte address support for new NAND Flash support
SLC & MLC NAND Flash support
8bit/12bit Error Correction support
8 bit wide NAND support
Monitor the NAND flash Ready/Busy signal by HW support
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11 BT.656&601 Interface
11.1
Description
The BT.656 & 601 Interface consists of two parts: Video Encoder & Decoder & CMOS
Sensor & TS Interface and Internal Video Encoder.
11.2 Video Encoder/Decoder/CMOS Sensor/TS
Interface
Video encoder interface connects to digital video encode IC, which can display NTSC or
PAL mode on TV. The output format of the video encoder interface can be configured to
BT.656 or BT.601 format.
Video decoder & CMOS Sensor interface connects to digital video decoder IC or CMOS
sensor, which can record TV or sample picture. The input format of the video decoder &
CMOS sensor interface can be configured to BT.656 or BT.601 format.
Video Encoder & CMOS Sensor & Decoder Interface has the following features:
¾ Supports 8bit digital pixel data bus.
¾ Supports 16-level by 32bit FIFO.
¾ Supports BT.656 and BT.601 protocol for NTSC/PAL mode.
11.2.1 Register List
BT Registers Block Base Address
Block Name
Physical Bass Address
KSEG1 Base Adress
VEDCSTI
0x100D0000
0xB00D0000
VEDCSTI: Video Encoder & Decoder & CMOS Sensor & TS Interface
BT Registers list---for output part, including external and internal TV-Encoder
Offset
Register Name
Description
0x0000 BTO_MODESEL
TV-encoder Interface Mode Select Register
0x0004 BT_FIFO_ODAT
TV-encoder Interface FIFO Data Register; 16 level * 32 bit FIFO
0x0008 BT_VEICTL
TV-encoder Interface Control Register
TV-encoder Interface active line start and end position(Odd
0x000C BT_VEIALSEOF
Field) register
0x0010 BT_VEIALSEEF
TV-encoder Interface active line start and end position (Even
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0x0014
BT_VEIADLSE
0x0018
0x001C
BT_VEIFTP
BT_VEIFIFOCTL
Field )register
TV-encoder Interface active data in every line start and end
position register
TV-encoder Interface Field Transition Position Register
TV-encoder Interface FIFO Control Register
BT Registers List---for input parts, including External TV-Decoder, External CMOS Sensor and
TS.
Offset
Register Name
Description
TV- Decoder/ CMOS Sensor/ TS Interface Mode Select
0x0020 BTI_MODESEL
Register
TV_Decoder/ CMOS Sensor /TS Interface FIFO Data Register;
0x0024 BT_FIFO_IDAT
16 level * 32 bit FIFO.
BT_VDICTL
TV-decoder Interface Control Register
0x0028 BT_CSICTL
CMOS Sensor Interface Control Register
BT_TSICTL
TS Interface Control Register
TV-decoder Interface Hsync Start Position Register and active
BT_VDIHSPOS
data in every line
0x002C
CMOS Sensor Interface Hsync Start Position Register and
BT_CSIHSPOS
active pixel number in every line
BT_VDIVSEPOF
TV-decoder Interface VSYNC Start/size(Odd Field) Register
0x0030
CMOS Sensor Interface active lines start position and size
BT_CSIVSEPOF
Register
0x0034 BT_VDIVSEPEF
TV-decoder Interface VSYNC Start/size (Even Field) Register
BT_VDIIRQSTAT
TV-decoder Interface IRQ Status Register
0x0038
BT_CSIRQSTAT
CMOS Sensor Interface IRQ Status Register
BT_VDIFIFOCTL
Video Decoder Interface FIFO Control Register
CMOS Sensor Interface FIFO Control Register
0x003C BT_CSIFIFOCTL
BT_TSIFIFOCTL
TS Interface FIFO Control Register
11.2.2 Register Description
11.2.2.1
Output Interface Register (External & Internal TV-Encoder)
11.2.2.1.1 BTO_MODESEL
TV-encoder Interface Mode Select Register
Offset=0x00
Bits
Name
Description
31:2
Reserved
DMA Mode Select
1
DMS
0: demand mode
1:block mode
Encoder Interface Enable
0
EIEN
0:disable,
1:enable
R/W
R
Default
0
RW
0
RW
0
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11.2.2.1.2 BT_FIFO_ODAT
TV-encoder Interface FIFO Data Register
Offset=0x04
Bits
Name
31:0
FIFOD
FIFO Data
Description
R/W
W
Default
x
R/W
R
Default
0
Rw
0
R
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
11.2.2.1.3 BT_VEI_CTL
TV-encoder Interface Control Register
Offset=0x08
Bits
Name
Description
31:11 Reserved
Horizontal Pixel Scaler
10
HPS
0:
1: 1
1:
1: 2
9:8
Reserved
Data Format Select.
0: Y3Y2Y1Y0, Cb3Cb2Cb1Cb0, Y7Y6Y5Y4,
7
DFS
Cr3Cr2Cr1Cr0…
1: Y1Cr0Y0Cb0, Y3Cr1Y2Cb1 …
Encoder Interface Output Enable
6
EIOE
0: disable, no data or sync signal will output from IC pin.
1: enable
Vsync or Field Select --- BT601 only
0: Vsync
5
FVS
1: Field
Hsync Active Select --- BT601 only
0: Hsync active low,
4
HAS
1: Hsync active high
Vsync/Field Active Select. --- BT601 only
3
VFAS
0: Vsync active low or Odd field active low.
1: Vsync active high or Even field active low
Pclk Active Edge Select.
0: PCLK positive edge
2
PAES
1: PCLK negative edge.
PAL/NTSC Mode Select
1
PNMS 0: PAL --625 line, 50 field/s
1: NTSC--525 line, 60 field/s
Video Format Select.
0: BT.656
0
VFS
1: BT.601
Note: Vsync/Hsync active low means the signal is a negative pulse.
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11.2.2.1.4 BT_VEIALSEOF
TV-encoder Interface active line start and end position (Odd Field) register
Offset=0x0C
Bits
Name
Description
31:17 Reserved
16:8
LEPO
active Line End Position in Odd field
7:0
LSPO
active Line Start Position in Odd field
Note: Active line start position must be counted from the 1st line.
R/W
R
RW
RW
Default
0
x
x
R/W
R
RW
R
RW
Default
0
x
0
x
11.2.2.1.5 BT_VEIALSEEF
TV-encoder Interface active line start and end position (Even Field) register
Offset=0x10
Bits
Name
Description
31:22
Reserved
21:12
LEPE
Active Line End Position in Even field.
11:10
Reserved
9:0
LSPE
active Line Start Position in Even field
Note: Active line start position must be counted from the 1st line.
11.2.2.1.6 BT_VEIADLSE
TV-encoder Interface active data in every line start and end position register
Offset=0x14
Bits Name
Description
R/W Reset
31:27
----- Reserved
R
0
26:16 ADEP Active Data bytes End Position in each line
RW xxx
15:11
10:0
-----
Reserved
ADSP Active Data bytes Start Position in each line
R
0
RW
xxx
11.2.2.1.7 BT_VEIFTP
TV-encoder Interface of Field Transition Position Register
Offset=0x18
Bits
Name
Description
31:26 Reserved
25:16 FTPE
Field Transition Position(Even field)
15:10
Reserved
9:0
FTPO
Field Transition Position(Odd field)
Note: The register is active only in BT.601 format.
R/W
R
RW
R
RW
Default
0
x
0
x
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11.2.2.1.8 BT_VEIFIFOCTL
TV-encoder Interface FIFO Control Register
Offset=0x1c
Bits
Name
Description
31:8
Reserved
FIFO FUll flag.
0: Not Full
7
FFU
1: Full
FIFO Access Channel Select.
6
ACS
0: Special Channel
1: AHB Bus
FIFO Empty IRQ interrupt Mask Enable.
0: Mask Enable. No Interrupt will occur
5
EIME
1: Mask Disable.
FIFO empty DRQ Enable.
0: Disable
4
FDE
1: Enable
FIFO Empty IRQ Enable.
3
EIE
0: Disable
1: Enable
FIFO Empty Condition.
00: 7/16 Empty, means there is 7 level of data
when report empty
2:1
FEC
01: 8/16 Empty(Half Empty)
10: 9/16 Empty
11: 10/16 Empty
FIFO Empty IRQ Pending bit.
0: No IRQ
0
EIP
1: IRQ
Write 1 to the bit, clear the bit.
Note: The register is active for BT.656 & BT.601 format.
R/W
R
Default
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
01
RW
0
11.2.2.2
Input Interface General Register (External TV-Decoder,
External CMOS Sensor and TS)
11.2.2.2.1 BTI_MODESEL
Decoder & CMOS Sensor & TS Interface Mode Select Register
Offset=0x20
Bits
Name
Description
31:6
Reserved
DMA Mode Select
5
DMS
0: demand mode
1: block mode
CLKOUT Enable.
0: Disable
4
CKOE
1: Enable
R/W
R
Default
0
RW
0
RW
0
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3
-
2:1
VFS
0
IIE
reserved
Video Format Select.
00: BT.656
01: BT.601
10: Ts
11: Sensor
Input Interface Enable
0:disable
1:enable
R
0
RW
00
RW
0
R/W
R
Default
X
R/W
R
Default
0
RW
0
RW
00
RW
00
RW
0
R
0
RW
0
11.2.2.2.2 BT_FIFO_IDAT
TV_Decoder/ CMOS Sensor /TS Interface FIFO Data Register
Offset=0x24
Bits
31:0
Name
FIFOD
11.2.2.3
Description
FIFO Data.
TV Decoder Interface Register
11.2.2.3.1 BT_VDICTL
TV-decoder Interface Control Register
Offset=0x28
Bits
Name
Description
31:13 Reserved
Receive 1 field or 2 field for 1 frame for TV-decoder
HalfF
0: 2 field for 1 frame
12
1: 1 field for 1 frame
TV-decoder input vertical Sub-sample ratio
00: 1:1
01: 2:1
VSbuS
11:10
10: 4:1
11: reserved
TV-decoder input horizontal sub-sample ratio
00: 1:1
01: 2:1
HSubS
9:8
10: 4:1
11: reserved
Data Format Select.
0:Y3Y2Y1Y0, Cb3Cb2Cb1Cb0, Y7Y6Y5Y4,
7
DATF
Cr3Cr2Cr1Cr0,…
1:Y1Cr0Y0Cb0, Y3Cr1Y2Cb1…
---Reserved
6
VSYNC or FIELD select, --- BT601 only
0:VSYNC
FVS
5
1:FIELD
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4
HAS
3
FVAS
2
PAES
1:0
-
Hsync Active Select, --- BT601 only
0: Hsync active low
1: Hsync active high
Vsync/Field Active Select. ---refer to BT_VDICTL_bit5.
0: Vsync active low or Odd field active low.
1: Vsync active high or Even field active low
PCLK Active Edge Select.
0: PCLK positive edge
1: PCLK negative edge.
reserved
RW
0
RW
0
RW
0
R
0
11.2.2.3.2 BT_VDIHSPOS
TV decoder Interface Hsync Start Position Register and active data in every line (in PCLK)
Offset=0x2c
Bits
Name
Description
R/W Default
Reserved
31:25 R
0
Active
Data
in
Every
Line
RW
x
24:12 ADEL
Reserved
11
R
0
Hsync Start Position
HSP
RW
x
10:0
Note: The register is active only for BT.601 format.
11.2.2.3.3 BT_VDIVSEPOF
TV decoder Interface active lines start position and size (Odd Field) Register (in Hsync)
Offset=0x30
Bits
Name
Description
R/W Default
Reserved
31:25
R
0
Active Lines of Odd Field.
RW
x
24:12 ALOF
11
Reserved
R
0
Active Lines Start Position in Odd field
ALSPO
RW
x
10:0
Note: The register is active only for BT.601 format.
11.2.2.3.4 BT_VDIVSEPEF
TV decoder Interface active lines start position and size (Even Field) Register (in Hsync)
Offset=0x34
Bits
Name
Description
R/W Default
Reserved
31:25
R
0
Active Lines of Even Field.
RW
x
24:12 ALEF
11
Reserved
R
0
10:0
ALSPE
Active Lines Start Position in Even field
RW
x
Note:
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Hsync start and end position are calculated from its active area position.
Vsync start and end position are calculated from its active area position.
The register is active only for BT.601 format.
11.2.2.3.5 BT_VDIIRQSTAT
TV-decoder Interface IRQ status Register
Offset=0x38
Bits Name
Description
31:9 Reserved
Finish-flag Interrupt Mask Enable.
8
FSIM 0: Mask Enable. No Interrupt will occur
1: Mask Disable
Vsync Edge or SAV IRQ Interrupt Mask Enable.
7
VSIM 0: Mask Enable. No Interrupt will occur
1: Mask Disable
Hsync Edge or EAV IRQ Interrupt Mask Enable.
6
HEIM 0: Mask Enable. No Interrupt will occur
1: Mask Disable
Finish-flag IRQ Enable.
5
FSIE 0: Disable
1: Enable
Vsync Edge or SAV IRQ Enable.
4
VSIE 0: Disable
1: Enable
Hsync Edge or EAV IRQ Enable.
3
HEIE 0: Disable
1: Enable
Finish-flag IRQ Pending Bit.
0: No IRQ
2
FSIP
1: IRQ
Writing 1 to the bit will clear it.
Vsync Edge or SAV IRQ Pending Bit.
0: No IRQ
1
VSIP
1: IRQ
Writing 1 to the bit will clear it.
Hsync Edge or EAV IRQ pending Bit.
0: No IRQ
0
VEIP
1: IRQ
Writing 1 to the bit will clear it.
R/W Reset
R
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
11.2.2.3.6 BT_VDIFIFOCTL
TV decoder Interface FIFO Control Register
Offset=0x3C
Bits
Name
Description
31:8
Reserved
R/W
R
Default
0
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7
FEF
6
ACS
5
FIME
4
FDE
3
FIE
2:1
FFC
0
FIP
FIFO Empty Flag.
0: Not Empty
1: Empty
FIFO Access Channel Select.
0: Special Channel
1: AHB Bus
FIFO Full IRQ interrupt Mask Enable.
0: Mask Enable. No Interrupt will occur
1: Mask Disable.
FIFO Full DRQ Enable.
0: Disable
1: Enable
FIFO Full IRQ Enable.
0: Disable
1: Enable
FIFO Full Condition.
00: 9/16 Full
01: 8/16 Full
10: 7/16 Full
11: 6/16 Full
FIFO Full IRQ Pending bit. Write 1 to the bit, clear the bit.
0: No IRQ
1: IRQ
11.2.2.4
R
0
RW
0
RW
0
RW
0
RW
0
RW
01
RW
0
CMOS Sensor Interface Register
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11.2.2.4.1 BT_CSICTL
CMOS Sensor Interface Control Register
Offset=0x28
Bits
Name
31:12
-
11:10
9:8
7
6:5
Description
R/W
Default
Reserved
R
0
VSbuS
CMOS Sensor input vertical sub-sample ratio
00: 1:1
01: 2:1
10: 4:1
11: reserved
RW
00
HSubS
CMOS Sensor input horizontal sub-sample ratio
00: 1:1
01: 2:1
10: 4:1
11: reserved
RW
00
Data Format Select.
0:Y3Y2Y1Y0, Cb3Cb2Cb1Cb0, Y7Y6Y5Y4,
Cr3Cr2Cr1Cr0…
1: Y1Cr0Y0Cb0, Y3Cr1Y2Cb1 …
RW
0
Reserved
R
0
RW
0
DATF
----
4
HAS
Hsync Active Select --- BT601 only
0: Hsync active low
1: Hsync active high
3
VAS
Vsync Active Select--- BT601 only.
0: Vsync active low
1: Vsync active high
RW
0
PAES
PCLK Active Edge Select.
0: PCLK positive edge
1: PCLK negative edge.
RW
0
Reserved
R
0
2
-
1:0
11.2.2.4.2 BT_CSIHSPOS
CMOS Sensor Interface Hsync Start Position Register and active data in every line (in PCLK)
Offset=0x2c
Bits
Name
31:25
-
24:12
ADEK
Description
R/W
Default
Reserved
R
0
Active Pixel Number in Every Line
RW
x
ATJ2256/ATJ2257/ATJ2257B DATASHEET
-
11
HSP
10:0
Reserved
R
0
Active Pixel Start Position in Every Line
RW
x
11.2.2.4.3 BT_CSIVSEPOF
CMOS Sensor Interface TV decoder Interface active lines start position and size(Odd Field)
Register (in Hsync)
BT_CSIVSEPOF
Offset=0x30
Bits
Name
31:25
-
24:12
ALOF
11
ALSPO
10:0
Description
R/W
Default
Reserved
R
0
Active Lines number in Every Frame
RW
x
Reserved
R
0
Active Line Start Position in Every Frame
RW
x
R/W
Reset
Notes:
The register is active only for BT.601 format.
Hsync start and end position are calculated from its active area position.
Vsync start and end position are calculated from its active area position.
11.2.2.4.4 BT_CSIRQSTAT
CMOS Sensor Interface IRQ status Register
Offset=0x38
Bits
31:8
Name
Description
-
Reserved
R
0
VSIM
Vsync Edge or SAV IRQ Interrupt Mask Enable.
0: Mask Enable. No Interrupt will occur
1: Mask Disable
RW
0
6
HEIM
Hsync Edge or EAV IRQ Interrupt Mask Enable.
0: Mask Enable. No Interrupt will occur
1: Mask Disable
RW
0
5
-
Reserved
R
0
VSIE
Vsync Edge or SAV IRQ Enable.
0: Disable
1: Enable
RW
0
7
4
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3
HEIE
Hsync Edge or EAV IRQ Enable.
0: Disable
1: Enable
2
-
Reserved
R
0
VSIP
Vsync Edge or SAV IRQ Pending Bit.
0: No IRQ
1: IRQ
Writing 1 to the bit will clear it.
RW
0
VEIP
Hsync Edge or EAV IRQ pending Bit.
0: No IRQ
1: IRQ
Writing 1 to the bit will clear it.
RW
0
1
0
RW
0
11.2.2.4.5 BT_CSIFIFOCTL
CMOS Sensor Interface FIFO Control Register
Offset=0x3C
Bits
31:8
Name
Description
R/W
Default
-
Reserved
R
0
EMF
FIFO Empty Flag.
0: Not Empty
1: Empty
R
0
ACS
FIFO Access Channel Select.
0: Special Channel
1: AHB Bus
RW
0
FIME
FIFO Full IRQ Interrupt Mask Enable.
0: Mask Enable. No Interrupt will occur
1: Mask Disable.
RW
0
4
FDE
FIFO Full DRQ Enable.
0: Disable
1: Enable
RW
0
3
FIE
FIFO Full IRQ Enable.
0: Disable
1: Enable
RW
0
FTH
FIFO Full Condition.
00: 9/16 Full
01: 8/16 Full
10: 7/16 Full
RW
01
7
6
5
2:1
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11: 6/16 Full
0
FIP
FIFO Full IRQ Pending Bit. Write 1 to the bit, clear the bit.
0: No IRQ
1: IRQ
11.2.2.5
RW
0
TS Interface Register
11.2.2.5.1 BT_TSICTL
TS Interface Control Register
Offset=0x28
Bits
Name
31:8
-
7
6:5
R/W
Default
Reserved
R
0
DATF
Data Format Select.
0:Y3Y2Y1Y0, Cb3Cb2Cb1Cb0, Y7Y6Y5Y4, Cr3Cr2Cr1Cr0…
1:Y1Cr0Y0Cb0, Y3Cr1Y2Cb1…
RW
0
-
Reserved
R
0
HAS
Hsync Active Select --- BT601 only
0: Hsync active low
1: Hsync active high
RW
0
3
VAS
Vsync Active Select--- BT601 only.
0: Vsync active low
1: Vsync active high
RW
0
2
PAES
PCLK Active Edge Select.
0: PCLK positive edge
1: PCLK negative edge.
RW
0
1:0
-
Reserved
R
0
R/W
Default
4
Description
11.2.2.5.2 BT_TSIFIFOCTL
TS Interface FIFO Control Register
Offset=0x40
Bits
31:8
7
Name
Description
-
Reserved
R
0
EMF
FIFO Empty Flag.
0: Not Empty
1: Empty
R
0
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6
5
4
3
2:1
0
ACS
FIFO Access Channel Select.
0: Special Channel
1: AHB Bus
RW
0
FIME
FIFO Full IRQ Interrupt Mask Enable.
0: Mask Enable. No Interrupt will occur
1: Mask Disable.
RW
0
FDE
FIFO Full DRQ Enable.
0: Disable
1: Enable
RW
0
FIE
FIFO Full IRQ Enable.
0: Disable
1: Enable
RW
0
FTH
FIFO Full Condition.
00: 9/16 Full
01: 8/16 Full
10: 7/16 Full
11: 6/16 Full
RW
01
FIP
FIFO Full IRQ Pending Bit. Write 1 to the bit, clear the bit.
0: No IRQ
1: IRQ
RW
0
11.3
Internal Video Encoder
The integrated video encoder can directly connect to TV to display all kinds of modes.
The integrated video encoder has the following features:
¾ Supports NTSC-M, -J and –4.43 modes.
¾ Supports PAL-B, -D, -G, -H, -I, -M, -N, -Nc modes.
¾ Supports CVBS (Composite Video Broadcasting Signal) output.
¾ Supports outputting blue color when no data input.
11.3.1 Registers List
Internal Video Encoder Registers Block Base Address
Block Name
Internal Video Encoder
Physical Bass Address
0x100D0000
KSEG1 Base Address
0xB00D0000
VEDCSTI Registers Offset Address
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Offset
Register Name
Description
0x0050
BT_IVECTL
0x0054
BT_IVEOUTCTL
Internal Video Encoder Output Control Register
0x0058
BT_IVECOTCTL
Internal Video Encoder Contrast Control Register
0x005c
BT_IVEBRGCTL
Internal Video Encoder Brightness Control Register
0x0060
BT_IVECSATCTL
Internal Video Encoder Color Saturation Control Register
0x0064
BT_IVECBURCTL
Internal Video Encoder Color Burst Control Register
0x0068
BT_IVESYNCAMCTL
Internal Video Encoder Control Register
Internal Video Encoder SYNC Amplitude Control Register
11.3.2 Registers Description
11.3.2.1
BT_IVECTL
Internal Video Encoder Control Register
Offset=0x0050
BT_IVECTL Bit Field Description
Bits
Name
31:7
-
Description
Reserved
R/W
Reset
R
0
8
Palnc colorburst length
PCBL 0: 2.22us
1: 2.51us
RW
0
7
-
R
0
6
Reserved
IVEN
Integrated Video Encoder Enable.
1:Enable
0:Disable
5
-
Reserved
4
Clock Mode Select.
CLKS 0:27MHzPLL+24MHz
1:27MHzPLL
RW
0
-
0
RW
0
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3:0
TVFS
TV Format Select.
0000: NTSC-M
0001: NTSC-J
0010: PAL-Nc
0011: PAL-B,G,H
0100: PAL-D
0101: PAL-I
0110: PAL-M
0111: PAL-N
Others: PAL-D
RW
0100
Note: When PAL-Nc mode is selected, bit4 of IVECTL must be set to 1.
11.3.2.2
BT_IVEOUTCTL
Internal Video Encoder Output Control Register
Offset=0x0054
BT_IVEOUTCTL Bit Field Description
Bits
Name
Description
31:3
-
2:1
CVBS Output.
00: Blue color(default)
CVBSOUT
01: Black color
1x: Color bar signal
0
R/W
Reserved
DACT
DAC Close/Open Control.
0: Close
1: Open.
Reset
R
0
RW
0
RW
0
NOTE: When encoder is enabled & no pixel data input, CVBS outputs blue color & black color.
When color bar outputs, Pixel data path is closed.
11.3.2.3
BT_IVECOTCTL
Internal Video Encoder Contrast Control Register
Offset=0x0058
BT_IVECOTCTL Bit Field Description
Bits
31:4
Name
-
Description
Reserved
R/W
R
Reset
0
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Contrast control.
0000: 75%
…
COTCTL 0111: 100%
…
1110: 125%
1111: Reserve
3:0
RW
0111
Note: Contrast Control Register[3:0]=(X-0.75)×28; X is 75% to 125%.
11.3.2.4
BT_IVEBRGCTL
Internal Video Encoder Brightness Control Register
Offset=0x005c
BT_IVEBRGCTL Bit Field Description
Bits
Name
Description
31:8
-
7:0
Brightness control.
00H:0LSB
…
7FH:127LSB
BRGCTL
80H:0LSB
81H:-127LSB
…
FFH:-1LSB
R/W
Reserved
Reset
R
0
RW
0
Note: The MSB of Brightness Control Register[7:0] is sign bit. The unit is LSB of DAC. The
value is calculated with 2-complement.
11.3.2.5
BT_IVECSATCTL
Integrated Video Encoder Color Saturation Control Register
Offset=0x0060
Bits
Name
Description
31:4
-
Reserved
3:0
Color Saturation control.
0000:75%
…
CSATCTL 0111:100%
…
1110:125%
1111:Reserve
R/W
Reset
R
0
RW
0111
Note:: Color Saturation Control Register[3:0]=(X-0.75)×28; X is 75% to 125%.
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11.3.2.6
BT_IVECBURCTL
Integrated Video Encoder Color Burst Control Register
Offset=0x0064
Bits
Name
31:12 -
11:0
Description
R/W Reset
Reserved
R
The Phase of Color Burst Phase Compensate.
00H: 0 degree
CBURPH
…
3FFH: 360 degree
0
RW 0
Note: The register value of the phase of color burst phase compensate is X×360/4096. X is
the wanted phase of color burst phase compensate.
11.3.2.7
BT_IVESYNCAMCTL
Integrated Video Encoder SYNC Amplitude Control Register
Offset=0x0068
Bits
Name
Description
31:4
-
Reserved
3:0
SYNC Pedestal Level Amplitude.
0000: 0LSB
SYNCAM
…
1111: 15LSB
R/W
Reset
R
0
RW
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
12 YUV2RGB Interface
12.1
Description
The Module performs image data transfer from frame buffer to LCD panel. It
accelerates the frame data display by hardware operation. It is optional and mainly used in
movie decoding. The processes include:
1. Up-sampling from YUV 422 to YUV 444
2. Change from YUV / YCbCr to RGB (8, 8, 8) format
YCbCr to RGB:
R = Y + 1.402 *(Cr-128)
G = Y - 0.34414*(Cb-128) - 0.71414*(Cr-128)
B = Y + 1.772 *(Cb-128)
YUV to RGB:
R = Y + 1.14V
G = Y - 0.39U - 0.58V
B = Y + 2.03U
3. Cut down RGB (8, 8, 8) to the RGB format required in LCD Panel.
12.2
Register List
YUV2RGB Registers Block Base Address
Block Name
Physical Base Address
KSEG1 Base Address
YUV2RGB
0x100F0000
0xB00F0000
TYUV2RGB Registers Offset Address
Offset
Register Name
Description
0x0000
YUV2RGB_CTL
YUV2RGB Control Register
0x0004
YUV2RGB_FIFODAT
YUV2RGB FIFO Data Register
0x0008
YUV2RGB_CLKCTL
YUV2RGB Clock Control Register
0x000c
YUV2RGB_FrameCount
YUV2RGB Frame Count Register
12.2.1 YUV2RGB_CTL
YUV2RGB Control Register
Offset=0x0000
ATJ2256/ATJ2257/ATJ2257B DATASHEET
Bit
Name
R/W
Reset
R
0
RFBM
Read FIFO Block Mode
0: Normal Mode
1: Block Mode
RW
0
WFBM
Write FIFO Block Mode
0: Normal Mode
1: Block Mode
RW
0
EN
RGB Decoder Enable.
0: Disable
1: Enable
RW
0
FES
FIFO Empty Status
0: Not Empty
1: Empty
R
1
RW
0
31:22
21
20
19
18
-
Description
Reserved
Write Data/Command Select
17:16
15
14
13:11
10
WDCS
00:Write Command (Write LCD register address)
01: Write Data (Write LCD register data)
10: RGB(565) Data FrameBuffer Transfer
11: YCbCr/YUV Data FrameBuffer Transfer
DEST
RGB Decoder Destination.
0: LCD interface
1: Frame buffer
RW
0
INS
Input YUV/YCbCr Select.
0: YCbCr
1: YUV
RW
0
RGB Format Select:
000: 16bit (RGB 565 1transfer)
001:18bit (RGB 666 1transfer)
010:8bit (RGB 565 2transfer)
011:9bit (RGB 666 2transfer)
100: 8bit (RGB 888 3transfer)
101:6bit (RGB 666 3transfer)
110: Reserved
111: Reserved
RW
0
RGB Sequence.
0: RGB
1: BGR
RW
0
FORMATS
SEQ
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FWCS
FIFO Write Channel Select.
0: Special Channel
1: AHB Bus
RW
0
8
FRCS
FIFO Read Channel Select.
0: Special Channel
1: AHB Bus
RW
0
7
EMDE
FIFO Empty (Write) DRQ Enable.
0: Disable
1: Enable
RW
0
EMIE
FIFO Empty (Write) IRQ Enable.
0: Disable
1: Enable
RW
0
FUDE
FIFO Full (Read) DRQ Enable.
0: Disable
1: Enable
RW
0
FUIE
FIFO Full (Read) IRQ Enable.
0: Disable
1: Enable
RW
0
EMCO
FIFO Empty (Write) Condition.
0: 4/8 Empty
1: 0/8 Empty
RW
0
EMIP
FIFO Empty (Write) IRQ Pending Bit.
0: No IRQ
1: IRQ
Write 1 to the bit to clear it.
RW
1
FUIP
FIFO Full (Read) IRQ Pending Bit.
0: No IRQ
1: IRQ
Write 1 to the bit to clear it.
RW
0
ERP
FIFO Error Pending Bit.
0: No Error
1: Error
Write 1 to the bit to clear it and reset the FIFO.
RW
0
9
6
5
4
3
2
1
0
Note: When RGB decoder destination (Bit15) selects LCD interface, LCD color depth can
select RGB565, RGB666 and RGB888 format.
When RGB decoder destination selects frame buffer, LCD color depth can only select
RGB565 format.
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
12.2.2 YU2RGB_DAT
YUV2RGB FIFO Data Register
Offset=0x0004
Bit
Name
Description
R/W
Reset
31:0
DAT
FIFO Data
RW
x
12.2.3 YUV2RGB_CLKCTL
YUV2RGB Clock Control Register
Offset=0x0008
Bit
Name
31:15
-
Description
R/W Reset
Reserved
14:8 RWCLKHDIV
7
-
6:0
RWCLKLDIV
R
R/W Clock High Cycle Division (from AHB Bus).
Divide from 1~128
0
RW 0x7f
Reserved
R
R/W Clock Low Cycle Division (from AHB Bus)
Divide from 1~128
0
RW 0x7f
12.2.4 YUV2RGB_FrameCount
YUV2RGB Frame Count Register
Offset=0x000c
Bit
Name
31:17
-
16:8
FCOLC
7:0
FROWC
Description
R/W
Reset
R
0
Frame Column Counter.
RW
0
Frame Row Counter.
RW
0
Reserved
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
13
USB2.0 SIE (OTG)
13.1 General Description
OTG controller is designed to support all tasks specified in OTG Supplement. AOTG uses
hardware implementation of Host Negotiation Protocol (HNP) and Session Request Protocol
(SRP). Special Function Registers are provided for the control of HNP and SRP.
AOTG can be used as a dual-role device and can act as a USB host or a USB peripheral
device. The ID input pin controls the default role. If the ID=1, it means that the mini-B plug
has connected and AOTG becomes a B-device. When the ID=0, it means that a mini-A plug
has connected and AOTG becomes an A-device. See On-The-Go Supplement to the USB2.0
SPEC Rev 1.0a for the details.
Please refer to OTG specification –AOTG_v04.pdf
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14 I2C (2) Interface
14.1
Description
The chips have two I2C Interfaces, which can be configured as either master or slave
device. In master mode, it generates the clock (I2C_SCL) and initiates transactions on the
data line (I2C_SDA). Data on the I2C bus is byte oriented. Multi-Master mode, 10-bit
address and Hi-speed mode are not supported. See I2C_Bus_Specification_1995 for
detailed information.
Pull-up resistors are required on both of the I2C lines as all of the I2C drivers are open
drain. Typically external 2k-Ohm resisters are used to pull the signals up to VCC.
tSU:STA
I2C Interface Timing
1/
tLO t HIGH
W
fSCL
SCL
tf
tf
tBUF
SDA
t HD:ST
A
14.2
tHD:DAT
tHD:DA
t SU:ST
T
O
Register List
I2C Register Block Base Address
Block Name
Physical Base Address
KSEG1 Base Address
I2C1
0x10180000
0xB0180000
I2C2
0x10180020
0xB0180020
The register block contains the registers.
I2C Registers Offset Address
Offset
Register Name
Description
0x0000
I2Cx_CTL
I2Cx Control Register
0x0004
I2Cx_CLKDIV
I2Cx Clock Divide Register
ATJ2256/ATJ2257/ATJ2257B DATASHEET
0x0008
I2Cx_STAT
I2Cx Status Register
0x000c
I2Cx_ADDR
I2Cx Address Register
0x0010
I2Cx_DAT
I2Cx Data Register
14.2.1 I2Cx_CTL
I2Cx Control Register
Offset=0x0000
Bit Name
31:9
R/W Reset
R
0
RW
0
7
Enable.
EN 0: Disable
1: Enable
RW
0
6
START Condition Generates IRQ Enable (only for slave mode).
SIE 0: Disable
1: Enable
RW
0
RW
0
RW
0
RW
0
Release Bus.
Writing 1 to this bit will release the clock and data line to idle. MCU
RB
RW
should write 1 to this bit after transmitting or receiving the last bit of
the whole transfer.
0
8
5
4
-
Description
Reserved
Internal Pull-up Resistor (4.7k) Enable.
PUEN 0: Disable
1: Enable
IRQ Enable.
IRQE 0: Disable
1: Enable
Mode Select.
MS 0: Master mode
1: Slave mode
Generating Bus Control Condition (only for master mode).
00: No effect
3:2 GBCC 01: Generating START condition
10: Generating STOP condition
11: Generating Repeated START condition
1
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0
Generating/Receiving Acknowledge Signal.
In receiving mode:
0: generate the ACK signal to the transmitter at 9th clock of SCL
1: do not generate the ACK signal at 9th clock of SCL
GRAS
In transmitting mode:
0: has not received the ACK signal
1: has received the ACK signal. This bit will be cleared when the 9th
clock of next SCL arrives
RW
0
14.2.2 I2Cx_CLKDIV
I2Cx Clock Divide Control Register
Offset=0x0004
Bit
Name
31:8
-
Description
R/W Reset
Reserved
Clock Divider Factor (only for master mode).
I2Cx clock (SCL) can select standard (100kbps) mode and fast
7:0 CLKDIV
(400kbps) mode. Calculating SCL is as follows:
SCL=PCLK/(CLKDIV*16)
R
0
RW
0
14.2.3 I2Cx_STAT
I2CX Status Register
Offset=0x0008
Bit
Name
31:8
-
7
TRC
Description
Reserved
Transmit/Receive Complete Bit.
The bit is automatically set when the buffer is empty in
transmit mode or when the buffer is full in receive mode.
Writing 1 to this bit will clear it.
In transmitting mode:
0: Transmitting in progress
1: Transmitting complete
In receiving mode:
0: Receiving in progress
1: Receiving complete
R/W
Reset
R
0
RW
0
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6
STOP Detect Bit.
The bit will be cleared when the I2C mode disables or when
the START condition is detected again. Writing 1 to the bit
STPD
will clear it.
1: Indicate that the STOP bit is detected
0: STOP bit is not detected
RW
0
5
START Detect Bit.
The bit is cleared when the I2C mode disables or when the
STAD STOP condition is detected. Writing 1 to the bit will clear it.
1: Indicate that the START bit is detected
0: START bit is not detected
RW
0
4
Read/Write Status Bit (only for Slave mode).
When in slave mode, this bit reflects the master device
read from or writes to the slave device if the last address is
matched.
RWST
This bit is valid before the next start bit, stop bit or NAK bit
occurred.
1: Read
0: Write
RW
0
3
Last Byte Status Bit.
LBST 1: Indicate the last byte received or transmitted is data
0: Indicate the last byte received or transmitted is address
RW
0
2
IRQ Pending Bit.
Writing 1 to this bit will clear it.
IRQP
1: IRQ
0: No IRQ
RW
0
1
Overflow Status Bit.
Writing 1 to this bit will clear it.
OVST 1: A new byte is received whereas the previous byte has
not been read
0: No overflow
RW
0
0
Writing Collision Bit.
Writing 1 to this bit will clear it.
1: The I2C data register is written when it is still
transmitting the previous byte.
0: No collision
RW
0
WCO
Note: Whenever writing collision or overflow is set, NAK will occur automatically.
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14.2.4 I2Cx_ADDR
I2Cx Address Register
Offset=0x000C
Bit Name
31:8
-
Description
R/W Reset
Reserved
R
0
Slave Device Address.
In master mode, these bits are I2C slave device address.
RW
7:1 SDAD
In slave mode, these bits are used to compare with the address that
the master device sends out.
Read/Write Control or Match.
In master mode, the bit is read/write control bit.
0: Write
0 RWCM 1: Read
In slave mode, the bit is slave address match bit.
0: Not match, do not send the IRQ
1: Match, l send IRQ to MCU
0
RW
0
14.2.5 I2Cx_DAT
I2Cx Data Register
Offset=0x0010
Bit
Name
31:8
-
7:0
Description
Reserved
TXRXDAT Transmit/Receive Data.
R/W
Reset
R
0
RW
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
15
SPI Interface
15.1
Description
The SPI can be configured as either a master or slave device. During an SPI transfer, data
is shifted out and shifted in (transmitted and received) simultaneously. The SPI_SCK line
synchronizes the shifting and sampling of the information. It is an output when the SPI is
configured as a master or an input when the SPI is configured as a slave.
The SPI uses a couple parameters called clock polarity (CPOL) and clock phase (CPHA) to
determine when data is valid with respect to the clock signal. These must be set on the
Master and all the Slaves in order for communication to work. CPOL determines whether the
leading edge is defined to be the rising or falling edge of the clock (and vice versa for the
trailing edge). CPHA determines whether the leading edge is used for setup or sample (and
vice versa for the trailing edge).
15.2
Register List
SPI Registers Block Base Address
Block Name
Physical Bass Address
KSEG1 Base Address
SPI
0x10080000
0xB0080000
The register block contains the registers.
SPI Registers Offset Address
Offset
Register Name
Description
0x0000
SPI_CTL
SPI Control Register
0x0004
SPI_CLKDIV
SPI Clock Divide Register
0x0008
SPI_STAT
SPI Status Register
0x000c
SPI_RXDAT
SPI Receive FIFO Data Register
0x0010
SPI_TXDAT
SPI Transmit FIFO Data Register
15.2.1 SPI_CTL
SPI Control Register
Offset=0x0000
Bits
Name
Description
R/W
Reset
ATJ2256/ATJ2257/ATJ2257B DATASHEET
31:24 -
Reserved
23:22 RDIC
RX DRQ/IRQ Control.
00: set when at least one byte received in IRQ mode.
01: set when 4 bytes received in IRQ/DRQ mode
10: set when 8 bytes received in IRQ/DRQ mode
RW
11: set when 12 bytes received in IRQ/DRQ mode
In DMA mode, DO not set 00, because at lease 2 bytes
necessary.
0
21:20 TDIC
TX DRQ/IRQ Control.
00: set when TX FIFO is 1 byte empty in IRQ mode.
01: set when TX FIFO is 4 bytes empty in IRQ/DRQ mode.
10: set when TX FIFO is 8 bytes empty in IRQ/DRQ mode. RW
11: set when TX FIFO is 12 bytes empty in IRQ/DRQ mode.
In DMA mode, DO not set 00, because at lease 2 bytes
necessary.
0
TWME
Two wire mode enable bit
0: normal 4 wire mode
1: two wire mode, use two pin, SPI_CLK and SPI_MOSI
RW
0
EN
Enable.
0: Disable
1: Enable
RW
0
R/W control
00: no effect
01: write only
10: read only
11: write and read
RW
00
19
18
17:16 RWC
R
0
15
DTS
DMA transfer start(available only in master read only
mode)
0: DMA transfer over.(this bit will be cleared to 0 when
RW
transfer over)
1: DMA transfer start(write 1 will start the DMA data
transfer)
0
14
SPI_SS active automatically enable when in mode 0 and
mode 2
SSATEN
RW
0:disable
1:enable
0
13
RXBL
SPI RX DMA block mode enable
0: demand mode
1: block mode
RW
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
SPI TX DMA block mode enable
12
TXBL
0:demand mode
1:block mode
RW
0
11
CEB
Convert Endian bit
0: not convert Endian
0x3210 ->0x3210
1: convert Endian
16bit mode:
0x3210->0x1032
MSB or LSB first shift in or out
RW
0
FMS
SPI fast mode select, only apply to SPI master mode.
0: synchronization design, SPICLK=HCLK/(CLKDIV*2), the
least value of CLKDIV is 3, so the least divide is 6.
RW
1: fast mode, SPICLK=HCLK/(CLKDIV*2), but when
CLKDIV is set to 0, the divide is 1. so the least divide is 1.
0
MS
Master/Slave Select.
0: Master
1: Slave
RW
0
DAWS
Data/Address Width. Select
0: 8 bit data and address
1: 16 bit data and address
RW
0
7:6
CPOS
Clock Polarity Select.
CPOL CPHA
00: Mode 0
01: Mode 1
10: Mode 2
11: Mode 3
RW
b11
5
LMFS
LSB/MSB First Select.
0:Transmit and receive MSB first
1:Transmit and receive LSB first
RW
0
SSCO
SPI_SS Control Output (only for master mode).
1: output high
0: output low.
RW
1
TIEN
TX IRQ Enable.
0: Disable
1: Enable
RW
0
RIEN
RX IRQ Enable.
0: Disable
1: Enable
RW
0
10
9
8
4
3
2
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
1
0
TDEN
TX DRQ Enable.
0: Disable
1: Enable
RW
0
RDEN
RX DRQ Enable.
0: Disable
1: Enable
RW
0
Note:
1. The bit 14 is valuable only operation in the mode 0、mode2.
2. When the TMS=1 & RWC=10, the controller will automatically send the clock.
3. When the TMS=1 & RWC=11, the controller will send the clock depend on the data of
register SPI_TXDATA.
4.When the data<4 bytes(8 bit mode)、data<8 bytes(16 bit mode), the DMA mode should
not used.
5. The select DMA mode or CPU mode depend on the [TDEN] and [RDEN].
15.2.2 SPI_CLKDIV
SPI Clock Divide Control Register
Offset=0x0004
Bits
Name
31:10 -
9:0
Description
Reserved
R/W
R
Reset
0
Depend on the SPI_CTL bit 10:
SPICLK=HCLK/(CLKDIV*2),
When not select fast mode, the least value of CLKDIV is 3,
so the least divide from HCLK is 6. Supporting SPI clock
CLKDIV
RW
rate up to 15MHz.
When SPI master selects fast mode, the least value of
CLKDIV is 0.when CLKDIV is set to 0, the divide is 1. So the
least divide is 1. Supporting SPI clock rate up to 60MHz.
0
15.2.3 SPI_STAT
SPI Status Register
Offset=0x0008
Bits
Name
31:10 -
Description
Reserved
R/W
R
Reset
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
TX FIFO Empty.
9
TFEM
1: Empty
R
1
R
0
R
0
R
1
0: Not Empty
RX FIFO Full.
8
RFFU
1: Full
0: Not Full
TX FIFO Full.
7
TFFU
1: Full
0: Not Full
RX FIFO Empty.
6
RFEM
1: Empty
0: Not Empty
TX FIFO Error.
5
TFER
When overflow, the bit is set to 1. Writing 1 to the bit will RW
clear the bit and reset the FIFO.
0
RX FIFO Error.
4
RFER
When overflow, the bit is set to 1. Writing 1 to the bit will RW
clear the bit and reset the FIFO.
0
3
-
Reserved
0
TCOM
Transfer Complete Bit.
DMA mode: bit will be set to 1 when all the data sent out
RW
CPU mode: will be set to 1 when very byte data sent out
Write 1 will clear to zero
0
TIP
TX IRQ Pending Bit.
0: No IRQ
1: IRQ
Write 1 to the bit will clear it.
RW
0
PIP
RX IRQ Pending Bit.
0: No IRQ
1: IRQ
Write 1 to this bit will clear it.
RW
0
2
1
0
R
Note
1. When the SPI_CTL[RWC]=11 and :
TX: DMA mode, RX: CPU mode
Or
TX: CPU mode, RX: DMA mode
Than SPI_STA[TCOM] will be set to 1 when every byte data sent out.
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
15.2.4 SPI_RXDAT
SPI RX Data Register
Offset=0x000c
Bits
Name
Description
R/W
Reset
31:16 -
Reserved
R
0
15:0
Receive Data.
The depth of RXFIFO is 16bit×16 levels.
R
x
RXDAT
15.2.5 SPI_TXDAT
SPI TXData Register
Offset=0x0010
Bits
Name
31:16 15:0
TXDAT
Description
R/W
Reset
Reserved
R
0
Transmit Data.
The depth of RXFIFO is 16bit×16 levels.
W
x
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
16
UART (2) Interface
16.1
Description
ATJ2256/ATJ2257/ATJ2257B Platform contains two UART interfaces. Each UART has the
following features:
¾
5-8 Data Bits and LSB first in Transmit and Received
¾
1-2 Stop Bits
¾
Even, Odd, or No Parity
¾
16 Byte Transmit and Receive FIFOs
¾
Interrupts for Receive FIFO Half Full and Not Empty
¾
Interrupts for Transmit FIFO Empty and Half Empty
¾
Support RTS/CTS Automatic Hardware Flow Control on UART1 to reduce
interrupts to host system
¾
Capable of speeds up to 1.5Mbs to enable connections with Bluetooth and
other peripherals
¾
UART2 has Infrared Data Association(IrDA) Inputs and Outputs (Optional)
16.2
Register List
Each UART is controlled by a register block.
UART Registers Block Base Address
Block Name
Physical Bass Address
KSEG1 Base Address
Uart1
0x10160000
0xB0160000
Uart2
0x10160020
0xB0160020
The register block contains the registers.
UART Registers Offset Address
Offset
Register Name
Description
0x0000
UARTx_CTL
UART Control Register
0x0004
UARTx_RXDAT
UART Receive FIFO Data Register
0x0008
UARTx_TXDAT
UART Transmit FIFO Data Register
0x000c
UARTx_STAT
UART Status Register
ATJ2256/ATJ2257/ATJ2257B DATASHEET
16.2.1 UART1_CTL
UART1 Control Register
Offset=0x0000
Bits
Name
31:2
1
20
19
18
17
16
15
14
13
Description
Reserved
R/W Reset
R
0
LBEN
Loop Back Enable.
Set this bit to enable a loop back mode that data coming
on the input will be presented on the output. Both in
RW
UART and IR.
0: Disable
1: Enable
0
TXIE
UART1 TX IRQ Enable.
0: Disable
1: Enable
RW
0
RXIE
UART1 RX IRQ Enable.
0: Disable
1: Enable
RW
0
TXDE
UART1 TX DRQ Enable.
0: Disable
1: Enable
RW
0
RXDE
UART1 RX DRQ Enable.
0: Disable
1: Enable
RW
0
EN
UART1 Enable.
When this bit is clear, the UART clock source is inhibited.
RW
This can be used to place the module in a low power
standby state.
0
TRFS
UART1 TX/RX FIFO Select
TX/RX FIFO Level is reflected in bit 15 to bit 12 of
UART1_STAT Register.
RW
0: RX FIFO
1: TX FIFO
0
RTSE
RTS Enable.
When this bit is set, request to send data.
Note: This bit has no effect if Autoflow enable bit is set.
0
RW
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Autoflow Enable
Setting this bit enables automatic hardware flow control.
RW
Enabling this mode overrides software control of the
signals.
0
11:1
RDIC
0
UART1 RX DRQ/IRQ Control
00: set when at least one byte received in IRQ mode.
01: set when 4 bytes received in IRQ/DRQ mode
10: set when 8 bytes received in IRQ/DRQ mode
RW
11: set when 12 bytes received in IRQ/DRQ mode
In DMA mode, DO not set 00, because at lease 2 bytes
necessary.
00
9:8
TDIC
UART1 TX DRQ/IRQ Control
00: set when TX FIFO is 1 byte leave in IRQ mode.
01: set when TX FIFO is 4 bytes empty in IRQ/DRQ mode.
10: set when TX FIFO is 8 bytes empty in IRQ/DRQ mode.
RW
11: set when TX FIFO is 12 bytes empty in IRQ/DRQ
mode.
In DMA mode, DO not set 00, because at lease 2 bytes
necessary.
00
7
BLOC
12
AFE
Uart1 DMA block mode Enable
0:demand
1:Block
RW
6:4
PRS
Parity Select.
Bit 4: EPS, Even parity
Bit 5: STKP, Stick parity
Bit 6: PEN, Parity enable
PEN EPS STKP Selected Parity
0
x
x
None
1
0
0
Odd
1
0
1
Even
1
1
0
logic 1
1
1
1
logic 0
3
-
Reserved
STPS
STOP Select.
If this bit is 0, 1 stop bit is generated in transmission. If RW
this bit is 1, 2 stop bits are generated.
2
0
RW
000
R
0
0
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1:0
Data Width Length Select.
00: 5 bits
01: 6 bits
10: 7 bits
11: 8 bits
DWLS
RW
00
Note: 1. The UART module should be reset for the next time usage.
16.2.2 UART1_RXDAT
UART1 Receive FIFO Data Register
Offset=0x0004
Bits
Name
31:10
8:0
Description
R/W
Reset
-
Reserved
R
0
RXDAT
Received Data.
The depth of FIFO is 9bit×16 levels.
Bit 8 is error status bit.
R
x
16.2.3 UART1_TXDAT
UART1 Transmit FIFO Data Register
Offset=0x0008
Bits
Name
Description
R/W
Reset
31:9
-
Reserved
R
0
7:0
TXDAT
Transmit Data.
The depth of FIFO is 8bit×16 levels.
R
x
16.2.4 UART1_STAT
UART1 Status Register
Offset=0x000c
Bits
Name
Description
R/W
Reset
31:16 -
Reserved
R
0
15:11 TRFL
TX/RX FIFO Level.
The field indicates the current RX and TX FIFO level.
R
0
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TFES
TX FIFO empty Status
0: empty
1: no empty
R
0
9
RFFS
RX FIFO full Status
0: no full
1: full
R
0
8
RTSS
RTS Status.
The bit reflects the status of the external RTS- pin.
R
x
7
CTSS
CTS Status.
The bit reflects the status of the external CTS- pin.
R
x
TFFU
TX FIFO Full.
1: Full
0: No Full
R
0
RFEM
RX FIFO Empty.
1: Empty
0: No Empty
R
1
RXST
Receive Status.
0: receive OK
1: receive error.
Writing 1 to the bit will clear the bit.
RW
0
TFER
TX FIFO Error.
0: No Error
1: Error
RW
Writing 1 to the bit will clear the bit and reset the TX
FIFO.
0
RXER
RX FIFO Error.
0: No Error
1: Error
RW
Writing 1 to the bit will clear the bit and reset the RX
FIFO.
0
TIP
TX IRQ Pending Bit.
0: No IRQ
1: IRQ
Writing 1 to the bit to clear the bit.
RW
0
RIP
RX IRQ Pending Bit.
0: No IRQ
1: IRQ
Writing 1 to the bit to clear it.
RW
0
10
6
5
4
3
2
1
0
Note:
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1. Software should reset the Uart module when some error information is detected.
16.2.5 UART2_CTL
UART2 Control Register
Offset=0x0000
Bit
31:24
23
Name Description
-
PWS
Reserved
R/W
Reset
R
0
SIR pulse width select
0: 3/16 bit width
RW
1: 1.6us width, (support baudrate from 9600 to 115200
bps)
0
22
IRTR
IR TX Reverse bit, 0: disable; 1: enable
RW
0
21
IRRR IR RX Reverse bit, 0: disable; 1:enable
RW
0
20
Loop Back Enable.
Set this bit to enable a loop back mode that data coming
on the input will be presented on the output. Both in UART
LBEN
and IR.
0: Disable
1: Enable
RW
0
TXIE
UART2/IR TX IRQ Enable.
0: Disable
1: Enable
RW
0
18
RXIE
UART2/IR RX IRQ Enable.
0: Disable
1: Enable
RW
0
17
UART2/IR TX DRQ Enable.
TXDE 0: Disable
1: Enable
RW
0
16
UART2/IR RX DRQ Enable.
RXDE 0: Disable
1: Enable
RW
0
RW
0
19
15
EN
UART2/IR Enable.
When this bit is cleared, the UART clock source is
inhibited. This can be used to place the module in a low
power standby state.
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14
13:12
11:10
9:8
7
6:4
TX/RX FIFO Select.
TX/RX FIFO Level is reflected in bit 15 to bit 12 of
TRFS UART2_STAT Register.
0: RX FIFO
1: TX FIFO
RW
0
Mode Select.
00: UART2
01: IRDA-SIR
10: IRDA-MIR
11: IRDA-FIR
RW
0
RDIC
UART2 RX DRQ/IRQ Control
00: set when at least one byte received in IRQ mode.
01: set when 4 bytes received in IRQ/DRQ mode
10: set when 8 bytes received in IRQ/DRQ mode
11: set when 12 bytes received in IRQ/DRQ mode
In DMA mode, DO not set 00, because at lease 2 bytes
necessary.
RW
0
TDIC
UART2 TX DRQ/IRQ Control
00: set when TX FIFO is 1 byte leave in IRQ mode.
01: set when TX FIFO is 4 bytes empty in IRQ/DRQ mode.
10: set when TX FIFO is 8 bytes empty in IRQ/DRQ mode.
11: set when TX FIFO is 12 bytes empty in IRQ/DRQ
mode.
In DMA mode, DO not set 00, because at lease 2 bytes
necessary.
RW
0
R
0
RW
0
MS
Uart2 DMA block mode Enable
BLOC - 0: demand
1: Block
PRS
Parity Select.
Bit 4: EPS, Even parity
Bit 5: STKP, Stick parity
Bit 6: PEN, Parity enable
PEN EPS STKP Selected Parity
0
x
x
None
1
0
0
Odd
1
0
1
Even
1
1
0
logic 1
1
1
1
logic 0
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3
VFIRE
RW
0
STOP Select.
If this bit is 0, 1 stop bit is generated in transmission. If
STPS
this bit is 1, 2 stop bits are generated. The receiver always
checks 1 stop bit only.
RW
0
Data Width Length Select.
00: 5bit
DWLS 01: 6bit
10: 7bit
11: 8bit
RW
00
2
1:0
VFIR Function enable
0: disable
1: enable
Notes
1. The Uart module should be reset when the next time usage.
16.2.6 UART2_RXDAT
UART2 Receive FIFO DATA Register
Offset=0x0004
Bit
Name Description
31:10
-
R/W Reset
Reserved
UART2/IR Received Data.
9:0 RXDAT The depth of FIFO is 10bit×8 levels. The 9th bit is the error bit, the
8th bit is the end of package bit and the 7:0 bits is the data.
R
0
R
x
16.2.7 UART2_TXDAT
UART2 Transmit FIFO DATA Register
Offset=0x0008
Bit Name Description
31:9
-
R/W Reset
Reserved
UART2/IR Transmit Data.
8:0 TXDAT The depth of FIFO is 9bit×8 levels. The 8th bit is the end of package
bit and the 7:0 bits is the data.
R
0
W
x
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16.2.8 UART2_STAT
UART2 Status Register
Offset=0x000c
Bits
Name
Description
R/W
Reset
31:16 -
Reserved
R
0
15:11 TRFL
UART2/IR TX/RX FIFO Level.
The field indicates the current RX and TX FIFO level.
R
0
TFES
TX FIFO empty Status
0: empty
1: no empty
R
0
RFFS
RX FIFO full Status
0: no full
1: full
R
0
8
IRES
IR EOP Status.
Writing the bit to high when next writing IR TX FIFO is
the last byte of the packet. Next writing TX FIFO after
this bit is set will clear this bit automatically. When read RW
from this bit, the EOP status bit of IR receiver is
returned. This bit can be polled by MCU to see if end of
package is reached.
0
7
IRCE
IR CRC Error Flag Bit (only in MIR or FIR mode). Write 1
RW
to this bit will clear it.
0
TFFU
UART2/IR TX FIFO Full.
1: Full
0: No Full
R
0
RFEM
UART2/IR RX FIFO Empty.
1: Empty
0: No Empty
R
1
RXST
UART2/IR Receive Status.
0: receive OK
1: receive error.
Writing 1 to the bit will clear the bit.
RW
0
TFER
UART2/IR TX FIFO Error.
0: No Error
1: Error
RW
Writing 1 to the bit will clear the bit and reset the TX
FIFO.
0
10
9
6
5
4
3
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2
1
0
RXER
UART2/IR RX FIFO Error.
0: No Error
1: Error
RW
Writing 1 to the bit will clear the bit and reset the RX
FIFO.
0
TIP
UART2/IR TX IRQ Pending Bit.
0: No IRQ
1: IRQ
Writing 1 to the bit to clear the bit.
RW
0
RIP
UART2/IR RX IRQ Pending Bit.
0: No IRQ
1: IRQ
Writing 1 to the bit to clear it.
RW
0
Note:
1. Software should reset the UART module when some error information is detected.
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17 IR Interface
17.1
Description
IrDA is a standard defined by IrDA consortium (Infrared Data Association). It specifies
the way to transfer data via infrared radiation wireless. The IrDA specifications include
standards for both the physical devices and the protocols used to communicate with each
other. IrDA devices conform to standards IrDA 1.0 and 1.1.
Speed for IrDA v1.0 ranges from 2400bps to 115200bps. Pulse modulation with 3/16
of the length of the original duration of a bit is used. Data format is the same as a serial port
asynchronously transmitted word, with a start bit at the beginning.
IrDA v1.1 defines the speed 0.576 and 1.152 Mbps for MIR mode and 4Mbps for FIR
mode with 1/4 mark-to-space ratio.
For MIR mode, the basic unit (packet) is transmitted synchronously, with a starting
sequence at the beginning. A packet consists of two start words followed by a target address
(IrDA devices are assigned numbers by the means of IrDA protocol, so they are able to
unambiguously identify themselves), data, CRC-16 and a stop word.
IR Interface Modes
Mode
Speed
SIR
2.4 to
115.2kbps
Depend on the UART2_CTL bit 23:
When select pulse width 3/16 bit :
BaudRate*16=CORE_CLK/UART2_CLK_DIV
When select pulse width 1.6u, (support
baudrate from 9600 to 115200 bps)
BaudRate*16*16=
CORE_CLK/UART2_CLK_DIV
IrDA 1.0
MIR
0.576 and
1.152 Mbps
BaudRate*8=CORE_CLK/UART2_CLK_DIV
IrDA 1.1 with error detection
FIR
4 Mbps
24M=CORE_CLK/UART2_CLK_DIV
IrDA 1.1 with error detection
17.2
CLK setting
Compliance
Register List
IR Registers Block Base Address
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Block Name
Physical Bass Address
KSEG1 Base Address
IR
0x10160000
0xB0160000
IR Registers Offset Address
Offset
Register Name
Description
0x0030
IR_PL
IrDA Packet Length Register
0x0034
IR_RBC
IrDA Receive Byte Count Register
17.2.1 IR_PL
IrDA Packet Length Register
Offset=0x0010
Bit
Name Description
31:13
-
R/W Reset
Reserved
12:0 MAXSPL Maximum Send Packet Length (only used in MIR or FIR mode).
R
0
RW
0
17.2.2 IR_RBC
IrDA Receive Byte Count Register
Offset=0x0014
Bit
Name Description
31:13
-
R/W Reset
Reserved
12:0 CRXBN
Current Received Bytes Number (only used in MIR or FIR mode).
Writing the field to reset it.
R
0
RW
0
18 SPDIF Interface
18.1
Register List
SPDIF Registers Block Base Address
Block Name
Physical Bass Address
KSEG1 Base Address
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SPDIF
0x10140000
0xB0140000
SPDIF Registers Offset Address
Offset
Register Name
Description
0x0000
SPDIF_CTL
SPDIF Control Register
0x0004
SPDIF_STAT
SPDIF Status Register
0x0008
SPDIF_TXDAT
SPDIF TX FIFO Data Register
0x000c
SPDIF_RXDAT
SPDIF RX FIFO Data Register
0x0010
SPDIF_TXCSTAT
SPDIF TX Channel Status Register
0x0014
SPDIF_RXCSTAT
SPDIF RX Channel Status Register
18.1.1 SPDIF_CTL
SPDIF Control Register
Offset=0x0000
Bits
Name
Description
31:16 -
Reserved
15
14
R/W
Reset
R
0
EN
SPDIF Enable.
0: Disable (will reset the RX and TX state machine)
1: Enable
RW
0
TRFS
SPDIF TX/RX FIFO Select.
TX/RX FIFO Level is reflected in bit 15 to bit 12 of
SPDIF_STAT Register.
0: RX FIFO
1: TX FIFO
RW
0
R
0
RW
0
RW
0
RW
0
13:12 -
Reserved
11:10 TDIC
SPDIF TX DRQ/IRQ Control.
X0:set when FIFO is empty
X1:set when FIFO is half empty
In DMA DRQ mode,this field must be set X1.
In DMA mode,TX fifo empty is at least 2 bytes remained.
9:8
RDIC
SPDIF RX DRQ/IRQ Control.
X0:set when FIFO is half full
X1:set when at least one byte is received
In DMA DRQ mode,this field must be set X0.
7
TXDE
SPDIF TX DRQ Enable.
0: Disable
1: Enable
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RXDE
SPDIF RX DRQ Enable.
0: Disable
1: Enable.
RW
0
TXIE
SPDIF TX IRQ Enable.
0: Disable
1: Enable.
RW
0
RXIE
SPDIF RX IRQ Enable.
0: Disable
1: Enable.
RW
0
BIE
SPDIF Block IRQ Enable.
0: Disable
1: Enable
RW
0
2
TXFR
SPDIF TX FIFO Reset. (also reset the TX state machine).
0: FIFO reset valid
1: FIFO reset invalid.
RW
0
1
RXFR
SPDIF RX FIFO Reset. (also reset the RX state machine).
0: FIFO reset valid
1: FIFO reset invalid
RW
0
LBEN
Loop Back Enable.
Set this bit to enable a loop back mode that data
coming on the input will be presented on the output.
0: Disable
1: Enable
RW
0
6
5
4
3
0
18.1.2 SPDIF_STAT
SPDIF Status Register
Offset=0x0004
Bits
Name
31:18 -
Description
Reserved
17
TFES
TX FIFO empty Status
0: empty
1: no empty
16
RFFS
RX FIFO full Status
0: no full
1: full
15:12 TRFL
TX/RX FIFO Level.
The field indicates the current RX and TX FIFO level.
R/W
R
Reset
0
R
0
R
0
R
0
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11:10 -
9:8
7
6
5
4
3
2
1
0
Reserved
R
0
R
0
TFFU
TX FIFO Full.
1: Full
0: No Full
R
0
RFEM
RX FIFO Empty.
1: Empty
0: No Empty
R
1
TIP
TX IRQ Pending Bit.
0: No IRQ
1: IRQ
Writing 1 to the bit to clear the bit.
RW
0
RIP
RX IRQ Pending Bit.
0: No IRQ
1: IRQ
Writing 1 to the bit to clear it.
RW
0
BIP
SPDIF Block IRQ Pending Bit. (receive the B preamble)
0: No IRQ
1: IRQ
Writing 1 to this bit will clear it.
RW
0
TFEP
TX FIFO Error Pending Bit.
0: No Error
1: Error
Writing 1 to this bit will clear it or reset FIFO clear it.
RW
0
RFEP
RX FIFO Error Pending Bit.
0: No Error
1: Error
Writing 1 to this bit will clear it or reset FIFO clear it.
RW
0
RERP
Receive Error Pending Bit.
0: No Error
1: Error
Writing 1 to this bit will clear it.
RW
0
Sample Rate Detected.
00:44.1 kHz
SAMRD 01:DC
10:48 kHz
11:32 kHz
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18.1.3 SPIDF_TXDAT
SPDIF TX FIFO DATA Register
Offset=0x0008
Bits
Name
31:26 25:0
Description
Reserved
SPDIF TX FIFO DATA.
TXDAT The depth of TX FIFO is 26bit x 8 levels.
Note: bit[23:0] is the really send data.
R/W
Reset
R
0
W
x
18.1.4 SPDIF_RXDAT
SPDIF RX FIFO DATA Register
Offset=0x000c
Bits
Name
31:26 -
25:0
Description
Reserved
SPDIF RX FIFO DATA.
The depth of TX FIFO is 26bit x 8 levels.
Note: bit[23:0] is the really received data.
Bit[25:24] is the data type
RXDAT
00: B
01: W
10: M
11:reserved
R/W
Reset
R
0
R
x
18.1.5 SPDIF_TXCSTAT
SPDIF TX Channel Status Register
Offset=0x0010
Bits
31:0
Name
Description
TXCSTAT SPDIF TX Channel Status.
R/W
RW
Reset
x
Note: For TX:
There is no channel status CRC to transfer. The SPDIF_TXSTAT just mapped to first 32 bit of
every 192 frames data and the remained bit will be set to zero by the hardware.
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18.1.6 SPDIF_RXCSTAT
SPDIF RX Channel Status Register
Offset=0x14
Bits
31:0
Name
Description
RXCSTAT SPDIF RX Channel Status.
R/W
RW
Reset
x
Note:
For RX:
There are 192 bits status data per 192 frames transfer. The SPDIF_RXSTAT register only
receive the bit 32 bit data ever 192 frames data of the left channel status.
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
19 Key Scan
19.1
Description
The Key Scan supports parallel mode and serial mode. The max scan matrix in serial
mode is 4x16. There are 4 key scan data registers. For each byte (there are 4 bytes for each
register), only the low 4 bits are valid.
In parallel mode, the max scan matrix is 3x4 and is shown as follows:
Max Key Scan Matrix in Parallel Mode
In the serial mode, one or more external shift register chips should be used. The
following is a 4x8 scan matrix example.
ATJ2256/ATJ2257/ATJ2257B DATASHEET
KEYO
0
KEYSO
KEYSCLK
D
Q
CL
K
KEYO
1
D
Q
CL
K
KEYI
0
KEYO
2
D
Q
CL
K
KEYI
1
KEYO
3
D
Q
CL
K
KEYI
2
KEYO
4
D
CL
K
Q
KEYO
5
D
Q
KEYO
6
D
CL
K
CL
K
Q
KEYO
7
D
Q
CL
K
KEYI
3
KEYO
0
b00
b01
b02
b03
KEYO
1
b10
b11
b12
b13
KEYO
2
b20
b21
b22
b23
KEYO
3
b30
b31
b32
b33
KEYO
4
b40
b41
b42
b43
KEYO
5
b50
b51
b52
b53
KEYO
6
b60
b61
b62
b63
KEYO
7
b70
b71
b72
b73
4*8 Key Scan Matrix in Serial Mode
Note: KEYSO is PIN KEYO1, KEYSCLK is PIN KEYO0.
The whole timing is as follows (parallel mode):
The Whole Key Scan Timing
In serial mode, two external 8bit shift registers can be used at least, that is to say, the
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maximum scan matrix is 4x16.
The state machine of KEY controller is described as below:
Idle
Debounce
Scan
Wait
Idle
Idle is active when no key is touched. Normally the time of Idle is equal to the time of
one line scan. When key touch is not occurred again, the idle state will be extended to the
time of scan period in order to save power in serial mode.
19.2
Register List
Key Scan Registers Block Base Address
Block Name
Physical Bass Address
KSEG1 Base Address
KEY
0x101A0000
0xB01A0000
Key Scan Registers Offset Address
Offset
Register Name
Description
0x0000
KEY_CTL
Key Scan Control Register
0x0004
KEY_DAT0
Key Scan Data Register0
0x0008
KEY_DAT1
Key Scan Data Register1
0x000c
KEY_DAT2
Key Scan Data Register2
0x0010
KEY_DAT3
Key Scan Data Register3
19.2.1 KEY_CTL
Key Scan Control Register
Offset=0x0000
Bits
Name
Description
R/W Reset
31:27 -
Reserved
R
26:24 WTS
Key Scan Wait Time Select.
KeyScan Wait Time=WTS*32ms
RW 0
23
Reserved
--
Key Scan output (KEYO[2:0])enable bit
0:Mask Key scan output
22:20 KOUTEN
1: Enable Key scan output
These bits are available for Parallel/Serial Mode
0
RW 0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
19
OTYP
KSOUT pin output type, Only for Parallel Key mode
0: Opendrain output.
1: push pull output
18
IRCL
Key Scan IRQ Cleared (only used when shutting down APB Clock). R
IRP
Key Scan IRQ Pending Bit.
0: No IRQ
1: IRQ
Writing 1 to the bit will clear the bit.
RW 0
IREN
Key Scan IRQ Enable.
0: Disable
1: Enable
RW 0
17
16
15:12 --
RW 0
0
Reserved
Key Scan Input (KEYI[3:0]) Mask Enable.
0: Mask Key Input
11:8 INMKEN 1: Enable Key Input
RW 0
When any pin of KEYI[3:0] is masked, it can used as GPIO, even if
key scan mode is active.
7:6
5:4
3:2
1
0
MATS
Key Scan Matrix Select (Only active in serial mode).
00: 8*4. Use Key_DAT0 register.
01: 8*8. Use Key_DAT0 and Key_DAT1 registers.
10: 8*16. Use registers from Key_DAT0 to Key_DAT3
11: Reserved
RW 0
PRS
Key Scan Period Select.
00: 40ms
01: 80ms
10: 160ms
11: 320ms
RW 0
DTS
Key Scan Debounce Time Select.
00: 10ms
01: 20ms
10: 40ms
11: No debounce time
The decounce time is 24MHz dividing frequency.
RW 0
MS
Key Scan Mode Select.
0: Parrel Mode
1: Serial Mode
RW 0
EN
Key Scan Enable.
0: Disable
1: Enable
RW 0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
19.2.2 KEY_DAT0
Key Scan Data Register0
Offset=0x0004
Bit
Name
Description
R/W
Reset
31:0
DAT
Key Scan Data
R
x
19.2.3 KEY_DAT1
Key Scan Data Register1
Offset=0x0008
Bit
Name
Description
R/W
Reset
31:0
DAT
Key Scan Data
R
x
19.2.4 KEY_DAT2
Key Scan Data Register2
Offset=0x000c
Bit
Name
Description
R/W
Reset
31:0
DAT
Key Scan Data
R
x
19.2.5 KEY_DAT3
Key Scan Data Register3
Offset=0x0010
Bit
Name
Description
R/W
Reset
31:0
DAT
Key Scan Data
R
x
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
20 GPIO and Multi-function Configuration
20.1
Description
There is 64 bit General purpose IO port in ATJ2256/ATJ2257/ATJ2257B. Each GPIO is
controlled by corresponding bit in GPIOx_Out_En reg and GPIOx_In_En reg.
20.1.1 Multi-function
There many multi function pin in ATJ2256/ATJ2257/ATJ2257B. The register Multi_con0 and
Multi_con1 can control the pad’s function. Some special pads with build-in pull up or pull
down resistance.
20.1.2 GPIO/Function pin
There are 64 GPIO in ATJ2256/ATJ2257/ATJ2257B. GPIO share pads with many functional
pads. The GPIO function has the highest priority. That is to say, if GPIO enables input or
output, the corresponding functional signal is masked.
20.1.3 Pad with Built-in Resistance
1. SD data bus:
SD_D0~D7, SD_CMD, pull up 50k
2. NF
NF_RB 2.2k pull up
3. I2C
SDA, SCL 4.7k pull up
4. Keyin
600K pull up
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
20.2
Register List
GPIO Registers Block Base Address
Module name
Physical Bass Address
KSEG1 Base Address
GPIO
0x101C0000
0xB01C0000
GPIO Registers Offset Address
Offset
Register Name
Description
0x0000
GPIO_AOUTEN
GPIOA Output Enable Register
0x0004
GPIO_AINEN
GPIOA Input Enable Register
0x0008
GPIO_ADAT
GPIOA Data Register
0x000c
GPIO_BOUTEN
0x0010
GPIO_BINEN
GPIOB Input Enable Register
0x0014
GPIO_BDAT
GPIOB Data Register
0x0018
GPIO_MFCTL0
Multi-function Control Register0
0x001c
GPIO_MFCTL1
Multi-function Control Register1
GPIOB Output Enable Register
20.2.1 GPIO_AOUTEN
GPIOA Output Enable Register
Offset=0x0000
Bit
31:0
Name
OUTEN
Description
GPIOA[31:0] Output Enable.
0: Disable
1: Enable
R/W
Reset
RW
0
R/W
Reset
RW
0
20.2.2 GPIO_AINEN
GPIOA Input Enable Register
Offset=0x0004
Bit
Name
31:0
INEN
Description
GPIOA [31:0] Input Enable.
0: Disable
1: Enable
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
20.2.3 GPIO_ADAT
GPIOA Data Register
Offset=0x0008
Bit
Name
31:0
IODAT
Description
GPIOA [31:0] Input/Output Data.
R/W
Reset
RW
0
20.2.4 GPIO_BOUTEN
GPIOB Output Enable Register
Offset=0x000c
Bit
31:0
Name
OUTEN
Description
GPIOB [31:0] Output Enable.
0: Disable
1: Enable
R/W
Reset
RW
0
R/W
Reset
RW
0
20.2.5 GPIO_BINEN
GPIOB Input Enable Register
Offset=0x0010
Bit
31:0
Name
INEN
Description
GPIOB [31:0] Input Enable.
0: Disable
1: Enable
20.2.6 GPIO_BDAT
GPIOB Data Register
Offset=0x0014
Bit
Name
31:0
IODAT
Description
GPIOB [31:0] Input/Output Data.
R/W
Reset
RW
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
20.2.7 GPIO_MFCTL0
Multi-function Control Register0
Offset=0x0018
Bit
Name
31
-
30:29 OTGDRV
Description
R/W Reset
Reserved
R
0
OTG DRVVBUS Multi Function.
00: Reserved
01: OTG_DRVVBUS
10: RGB_RDB
11: Reserved
RW 01
28:27
-
Reserved
RW
01
26:22
-
Reserved
RW
0
CEB6 Multi-function.
00: reserved
01: reserved
10: RGB_CE
11: SDCLK
RW
11
Reserved
RW
11
CEB4 Multi Function.
00: NOR_CEB4
01: RGBS_CE
10: RGB_CE
11: Reserved
RW
CEB3
CEB3 Multi-function.
00: reserved
01: NandFlash_CEB3
10: RGB_CE
11: reserved
RW
10
CEB2
CEB2 Multi-function.
00: reserved
01: NandFlash_CEB2
10: RGB_CE
11: reserved
RW
01
21:20
CEB6
19:18
-
17:16
15:14
13:12
CEB4
11
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
11:10
9:8
7:6
CEB1
CEB1 Multi-function.
00: reserved
01: NandFlash_CEB1
10: RGB_CE
11: reserved
RW
01
CEB0
CEB0 Multi-function.
00: reserved
01: NandFlash_CEB0
10: RGB_CE
11: reserved
RW
0
WRRD
Write and Read (WR and RD) Multi-function.
00: reserved
01: NandFlash_WR and NandFlash_RD
10: RGB_WRB and RGB_RDB
11: reserved
RW
0
NAND_D[7:0] Multi-function.
001: NandFlash_D[7:0]
010: RGB_WD[17:10]
Others: Reserved
RW
0
RW
0
5:3
NAND_D[7:0]
2:0
NAND_D[15:8] Multi-function.
001: NandFlash_D[15:8]
NAND_D[15:8] 010: RGB_WD[8:1]
100: SD_D[7:0]
Others: Reserved
20.2.8 GPIO_MFCTL1
Multi-function Control Register1
Offset=0x001c
Bit
31
Name
Description
MFEN
Multi Function Enable.
0: Disable
1: Enable
R/W Reset
RW
0
30:18 -
Reserved
R
0
17
Select SD Card Clock Output Enable.
0:Disable
1:Enable
RW
0
SD2E
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
16
--
Reserved
RW
0
15:14 --
Reserved
RW
00
13:12 --
Reserved
RW
1
11
SIRQ0 Multi Function.
0: SIRQ0
1: Reserved
Pad Enables by MFEN.
SIR0
10:9
8
7:6
-
RW
0
Reserved
0
U2TR
UART2 TX and RX Multi Function.
0: UART2_TX and UART2_RX
1: I2C2_SCL and I2C2_SDA
Pad Enables by MFEN.
RW
0
U1TR
UART1_TX and UART1_RX Multi Function.
00: UART1_TX and UART1_RX
01: SPI_SS and SPI_MISO
10: I2C2_SCL and I2C2_SDA
11: SPDIF_Pin1 and SPDIF_Pin2
Pad Enables by MFEN.
RW
0
5:4
I2C1SS
3:1
-
0
BT656
I2C1 SCL and SDA Multi Function.
00: I2C1_SCL and I2C1_SDA
01: UART2_TX and UART2_RX
10: Reserved
11: Reserved
Pad Enables by MFEN.
RW
0
Reserved
RW
0
BT656] Multi Function.
0: NOR_A[17:6]
1: BT656_CLKOUT, VSYNC, HSYNC, PCLK, D[7:0]
Pad Enables by MFEN or CE0S.
RW
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
21 DAC and Headphone Driver
21.1
Description
ATJ2256/ATJ2257/ATJ2257B’s internal DAC is an on-chip Sigma-Delta Modulator of
which an 18-bit high performance DAC is composed. DAC interface supports 8-level play
back FIFO (16 X 24bit PCM data for L/R channel and variable sample rates, such as
48K/44.1K/32K/24K/22.05K/16K/12K/11.025K/8KHz).
Vol Control
FIFO
Modulator
Low-pass filter
DAC Block Diagram
The following is ADDA Analog diagram:
AudioOutR
AudioOutL
ATJ2256/ATJ2257/ATJ2257B DATASHEET
ADDA Analog diagram
MIC_En
MICI
N
ADC_E
n
ADC_Mux_Sel
EN
MIC_Gai
n
ADC_Gai
n
EN
Sigmal
MU
X
delta
modulator
FM_E
n
FM_Mix_E
n
MIC_Mix_E
n
ENFM_Gai
n
FMINL/
R
DAC_E
n
EN
DAC_Mute
sigmal
delta
DAC
+
AoutL/R
EN
DAC_Volue
DAC_Analog_En
21.2
Register List
DAC Registers Block Base Address
Module Name
Physical Bass Address
KSEG1 Base Address
DAC
0x10100000
0xB0100000
DAC Registers Offset Address
Offset
Register Name
Description
0x0000
DAC_CTL
DAC Control Register
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
0x0004
DAC_FIFOCTL
DAC FIFO Control Register
0x0008
DAC_DAT
DAC Data Register
0x000c
DAC_Debug
DAC Debug Register
0x0010
DAC_Analog
DAC Analog Register
21.2.1 DAC_CTL
DAC Control Register
Offset=0x0000
Bit Name Description
R/W Reset
31:30
-
Reserved
29:24
-
Reserved
23:20
-
Reserved
RW
0
DAC Dither Amplitude.
00: ×1/8
19:18 DIAM 01: ×1/4
10: ×1/2
11: ×1
RW
00
17
DAC Dynamic Dither Enable.
DDEN 0: Disable
1: Enable
RW
0
16
DAC Dither Enable.
DIEN 0: Disable
1: Enable
RW
0
RW
1001
RW
1
RW
0
Internal DAC Quantization Levels.
15:12 QUL Levels=[3*(22+QUL[3:0])]/64,
Default levels=3*27/64=1.27
11
Internal DAC Quantization Bit Select.
QUBS 0: 3bit
1: 1bit
DAC Mono Enable.
0: Stereo, 8 levels FIFO
10 MOEN
1: mono, 16 levels FIFO
When enabled, L & R channel sends same data.
RW
0
R 000011
9:8
-
Reserved
R
00
7
-
Reserved
RW
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
6:4
-
Reserved
R
000
3
-
Reserved
RW
0
2
Internal DAC Sample Rate Select.
SRS 0: Sample Rate Internal Set
1: Reserved
RW
0
1
Internal DAC Output Select.
OUTS 0: On-chip Sigma-Delta
1: Reserved
RW
0
RW
0
0
Internal DAC Enable.
EN 0: Disable
1: Enable
21.2.2 DAC_FIFOCTL
DAC FIFO Control Register
Offset=0x0004
Bit
31:14
Name Description
-
R/W Reset
Reserved
13
DAC FIFO Debug Left/Right Channel Select.
LRCS 0: Left
1: Right
12
DAC FIFO Debug Data Ready Flag.
0: Not Ready
DDRF
1: Ready
After DAC_DAT_Debug is read, the bit is automatically cleared.
DAC PLAYBACK FIFO FULL Flag.
The above bits are also mapped into a 24-bit DSP memory
mapped EM port 0x3FEEh, low byte of this port.
DSP3FEEh.bit0: Reserved
DSP3FEEh.bit1: Reserved
DSP3FEEh.bit2: Internal DAC FIFO FULL
11
FUF
10
DAC FIFO Empty IRQ Pending Bit.
0: No IRQ
FEIP
1: IRQ
Writing 1 to the bit to clear it.
R
0
RW
0
R
0
R
0
RW
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
9
DAC FIFO Empty IRQ Enable.
FEIE 0: Disable
1: Enable
RW
0
8
DAC FIFO Empty DRQ Enable.
FEDE 0: Disable
1: Enable
RW
0
R
0
DAC Empty Condition.
00: 16/16 Empty (All empty)
EMCO 01: 15/16 Empty (Mono almost empty)
10: 14/16 Empty (Stereo almost empty)
11: 13/16 Empty
RW
01
DAC DSP Port Enable.
DSPE 0: Disable
1: Enable
RW
0
RW
0
DAC FIFO Input Select.
00: APB
FINS 01: Reserved
10: Reserved
11: ADC
RW
0
DAC FIFO Reset.
FIRT 0: Reset FIFO
1: Enable FIFO
RW
0
7
6:5
4
3
2:1
0
-
Reserved
-
Reserved
21.2.3 DAC_DAT
DAC FIFO Data Register
Offset=0x0008
Bit
Name
Description
R/W
Reset
31:8
DAT
DAC FIFO Data
W
x
7:0
-
Reserved
R
0
21.2.4 DAC_Debug
DAC Debug Register
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
Offset=0x000c
Bit
Name
Description
R/W
Reset
R
x
R
0
31:8
DATDE
DAC Data Debug.
Data is the same as the DAC reads from the FIFO.
Speed of refreshing the register is equal to FS*2,
whether stereo or mono. When
DAC_Fifo_Debug_Flag (DDRF) becomes 1, the data is
ready. DAC_Fifo_Debug_LR (LRCS) bit shows whether
the data comes from left or right channel.
7:0
-
Reserved
21.2.5 DAC_ANALOG
DAC Analog Register
Offset=0x0010
Bit
Name
Description
R/W Reset
31:30
-
Reserved
29:27
PAAPCTL
PA Anti-pop Control.
Note: 000 is the worst, 111 is the best.
RW
100
DACC
DAC Bias Current Control.
Note: 00 is minimum, 11 is maximum.
RW
0
25:24
OPGCTL
OPG Bias Current Control.
Note: 00 is minimum, 11 is maximum.
RW
01
23:22
PACCTL
PA Bias Current Control.
Note: 00 is minimum, 11 is maximum.
RW
01
21:20
OPFCCTL
OPF Bias Current Control.
Note: 00 is minimum, 11 is maximum.
RW
01
19:18
OP3CCTL
OPDA3P Bias Current Control.
Note: 00 is minimum, 11 is maximum.
RW
01
17:15
OP12CCTL
OPDA1 & 2 Bias Current Controls.
Note: 000 is minimum, 111 is maximum.
RW
011
14:13
OP0CTL
OP0 Output Stage Voltage Control.
Note: 00 is minimum, 11 is maximum.
RW
01
ZCDE
DAC Zero Cross Detect Enable.
0: Disable
1: Enable
RW
0
26
12
R
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
PBM
Internal DAC Playback Mute.
0: Mute DAC Playback
1: Enable DAC Playback
RW
0
10
FIMM
FM Input to Analog Mixer Mute.
0: Mute
1: Not Mute
RW
0
9
--
Reserved
RW
0
8
MIMM
MIC Input to Analog Mixer Mute.
0: Mute
1: Not mute
RW
0
7:3
HAVC
Master/Headphone Amp Volume Control.
Total 32 level, -1.8Db/step
RW
0
2
PAGC
PA Gain Control.
0: 1.2 Vpp
1: 1.6 Vpp
RW
0
AMPE
Internal Analog Mixer and PA Enable.
0: Disable
1: Enable
RW
0
EN
Internal DAC Analog Circuit Enable.
0: Disable
1: Enable
RW
0
11
1
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
22 ADC
22.1
Description
Internal microphone amplifier has gain for recording. VMIC pin is the power supply
(2.57V) for microphone.
Audio ADC is a 21-bit Sigma-delta Analog-to-digital converter. Its input source can be
selected from MIC amplifier or external FM, and it has two FIFO.
Fs supports 48K/44.1K/32K/24K/22.05K/16K/12K/11.025K/8KHz.
22.2
Register List
ADC Registers Block Base Address
Module name
Physical Bass Address
KSEG1 Base Address
ADC
0x10110000
0xB0110000
ADC Registers Offset Address
Offset
Register Name
Description
0x0000
ADC_CTL
ADC Control Register
0x0004
ADC_FIFOCTL
ADC FIFO Control Register
0x0008
ADC_DAT
ADC Data Register
0x000c
ADC_ANALOG
ADC Analog Register
0x0010
ADC_DEBUG
ADC Debug Register
22.2.1 ADC_CTL
ADC Control Register
Offset=0x0000
Bit
Name
31:29
-
Description
R/W Reset
Reserved
R
1000
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
28
27:26
25
24:23
VMIC_CTL
VMIC Enable.
0: Disable
1: Enable
AVCC_Voltage
AVCC Voltage
00: 0.15V
01: 0.20V
10: 0.25
11: 0.20V
-
ADCINGC
22:21
ADCINS
20:18
--
17
16
15:13
12
RW
RW
0
10
Reserved
1
ADC Input Gain Control.
00: -6dB
01: -3dB
10: 00dB
11: +3dB
RW
10
ADC Input Source Select.
00: MIC
01: FM
10: Reserved
11: Internal Analog Mixer Output(AOUT)
RW
01
Reserved
RW
101
LIRE
Linein Right Channel Enable.
0: Disable
1: Enable
RW
0
LILE
Linein Left Channel Enable.
0: Disable
1: Enable
RW
0
FMGC
FM Input Gain Control:
000: -7.5db
001: -6.0db
010: -4.5db
011: -3.0db
100: -1.5db
101: 0db
110: 1.5db
111: 3.0db
RW
101
FM Right Channel Enable.
0: Disable
1: Enable
RW
0
FMRE
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
11
FM Left Channel Enable.
0: Disable
1: Enable
FMLE
RW
0
10:8 MIGC
MIC Gain Control.
000: ×1
001: ×10
010: ×20
011: ×30
100: ×40
101: ×50
110: ×60
111: ×70
7
MIRE
MIC Right Channel Enable.
0: Disable
1: Enable
RW
0
6
MILE
MIC Left Channel Enable.
0: Disable
1: Enable
RW
0
5
ADRE
ADC Right Channel Enable.
0: Disable
1: Enable
RW
0
4
ADLE
ADC Left Channel Enable.
0: Disable
1: Enable
RW
0
3:1
-
Reserved
ADC Sample Rate Set. (For Debug)
RW
101
-
Reserved
0: ADC Clock from CMU
1: ADC Clock from OSC (For Debug)
0
RW
101
RW
0
22.2.2 ADC_FIFOCTL
ADC FIFO Control Register
Offset=0x0004
Bit
Name
Description
R/W
Reset
31:11
-
Reserved
R
0
10
-
Reserved
RW
0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
ADC PLAYBACK FIFO Empty Flag.
The above bits are also mapped into a 24-bit DSP memory
mapped EM port 0x3FEEh, low byte of this port.
DSP3FEEh. bit0: Reserved
DSP3FEEh. bit1: Internal ADC FIFO Empty
DSP3FEEh. bit2: Reserved
9
FEF
8
ADC FIFO Full IRQ Pending Bit.
0: No IRQ
FFIP
1: IRQ
Writing 1 to the bit is clear it.
ADC FIFO Full IRQ Enable.
0: Disable
1: Enable
R
0
RW
0
RW
0
7
FFIE
6
ADC FIFO Full DRQ Enable.
FFDE 0: Disable
1: Enable
RW
0
Internal ADC FIFO Full Condition:
00: 16/16 Full (all full)
FIFU 01: 15/16 Full (almost full)
10: 14/16 Full
11: 13/16 Full
RW
01
3
ADC DSP Port Enable.
DSPE 0: Disable
1: Enable
RW
0
2
ADC APB Port Enable.
APBE 0: Disable
1: Enable
RW
0
1
ADC FIFO Input Select.
FINS 0: ADC
1: Reserved
RW
0
0
ADC FIFO Reset.
FIRT 0: Reset FIFO
1: Enable FIFO
RW
0
5:4
22.2.3 ADC_DAT
ADC FIFO Data Register
Offset=0x0008
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
Bit Name Description
R/W Reset
31:8
ADC FIFO Data.
DAT Simultaneously mapped into a 24-bit DSP memory mapped EM port
0x3FECh.
R
x
7:0
-
R
0
Reserved
22.2.4 ADC_Analog
ADC Analog Register
Offset=0x000c
Bit
31:15
Name
-
Description
Reserved
R/W Default
R
14:12
OPAD3 in ADC Bias Current Select.
000: 0 level
001: 1 level
010: 2 level
OPAD3CS 011: 3 level
100: 4 level
101: 5 level
110: 6 level
111: 7 level
RW
11:9
OPAD2 in ADC Bias Current Select.
000: 0 level
001: 1 level
010: 2 level
OPAD2CS 011: 3 level
100: 4 level
101: 5 level
110: 6 level
111: 7 level
RW
0
101
101
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
8:6
OPAD1 in ADC Bias Current Select.
000: 0 level
001: 1 level
010: 2 level
OPAD1CS 011: 3 level
100: 4 level
101: 5 level
110: 6 level
111: 7 level
RW
011
5:3
LPFCS
Audio ADC LPF Bias Current Select.
000: 0 level
001: 1 level
010: 2 level
011: 3 level
100: 4 level
101: 5 level
110: 6 level
111: 7 level
RW
100
OPCS
OP in Audio ADC Pre-amplifies Bias Current Select:
000: 0 level
001: 1 level
010: 2 level
011: 3 level
100: 4 level
101: 5 level
110: 6 level
111: 7 level
RW
010
2:0
22.2.5 ADC_Debug
ADC Debug Register
Offset=0x0010
Bit
Name
31:23
-
22
DEDF
Description
R/W
Reset
Reserved
R
0
ADC Debug Data Channel Flag.
R
0
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21
DERF
ADC Debug Ready Flag.
0: Not Ready
1: Ready
Writing 1 to the bit will clear it.
20:0
DEDAT
ADC Debug Data.
RW
0
R
x
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23 Electrical Characteristics
23.1
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Symbol
Min
Max
Unit
VDD
-0.3
2.4
V
RTCVDD
-0.3
2.4
V
VCC
-0.3
3.8
V
DC5V
-0.3
6
V
BAT
-0.3
4.6
V
IOVCC
-0.3
4.6
V
IOVDD
-0.3
4.6
V
LXVCC
-0.3
4.6
V
LXVDD
-0.3
4.6
V
Junction Temperature
Tj
150
℃
Lead Temperature
(Soldering, 10 sec)
260
℃
Storage temperature
Tstg
150
℃
-65
Note:
1. TO = 25℃(Operating Temperature), VDD = 1.8 V, VCC = 3.1 V.
2. Do not short-circuit two or more output pins simultaneously.
3. Even if one of the above parameters exceeds the absolute maximum ratings momentarily,
the quality of the product may be degraded. The absolute maximum ratings, therefore,
specify the value exceeding, which the product may be physically damaged. Use the product
well within these ratings.
4. The specifications and conditions shown in the DC and AC characteristics are the ranges
for normal operation and the quality assurance of the product.
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23.2
Capacitance
Parameter
Symbol
Condition
Input capacitance
CI
I/O capacitance
CIO
MIN.
MAX.
Unit
fC = 1 MHz
20
pF
Unmeasured pins returned to 0 V
20
pF
Note: TO = 25℃, VCC = 0 V.
23.3
DC Characteristics
DC Characteristics
Parameter
Symbol
Condition
MIN.
High-level output voltage
VOH
IOH = -2 mA
2.4
Low-level output voltage
VOL
IOL = 2 mA
High-level input voltage
VIH
Low-level input voltage
VIL
Input leakage current
ILI
Output leakage current
ILO
TYP.
MAX.
Unit
V
0.4
V
0.9VCC
VCC+0.3
V
-0.3
0.1VCC
V
VCC = 3.6 V, VI = VCC, 0 V
+10
uA
VCC = 3.6 V, VI = VCC, 0 V
+5
uA
Notes:
1. TA = 0 to +70℃, VDD = 1.8 V, VCC = 3.1 V
2. IVDD is a total power supply current for the 2.5 V power supply. IVDD is applied to the
LOGIC and PLL and OSC block.
3. IVCC is a total power supply current for the 3.0 V power supply. IVCC is applied to the USB,
IO, TP, and AD block.
Recommended Operating Condition
PINS
MIN
TYPE
MAX
DC5V
2.9 V
4.5V
5.5V
BAT
2.9V
3.9V
4.2V
VCC,GPIO
2.6V
3.1V
3.6V
VDD, RTCVDD(Note 1)
1.3V(Note 2) 1.8V
2.2V
IOVCC , IOVDD
2.9V
---
4.2V
LXVCC, LXVDD
-0.3V
---
4.2V
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VMIC
2.4V
2.6V
2.8V
Note: 1: the recommended voltage differential between RTCVDD & VDD is <0.2V for
normal working.
Note 2:VDD shall be no less than 1.6V when USB functions normally.
23.4
Reset Characteristics
Reset Hysteresis
Note: Reset Pin input has the characteristics of hysteresis. The relationship between reset
level and reset pin is shown in Figure 17: upper threshold VT+=1.9V, lower threshold
VT-=1.2V.
23.5
PMU
DC/DC Operating Voltages: When Li-ion mode: DC/DC operates with battery as low as
2.8V.
System Standby Dissipation
Parameter
MIN (uA)
Typical (uA)
MAX (uA)
IVCC+IAVCC
100
112.6
IVDD
40
55
IAVDD
3.5
4.5
RTCVDD
1.01
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0.32
IUVCC
150
175
Note1: When ex osc is enabled.
Note2: When ex osc is disabled.
LRADC Precision
ERROR
MIN
TYPICAL
MAX
Unit
REMO_ADC
-
-
20
mV
BAT_ADC Li-ION
-
-
50
mV
Parameter
Efficiency Curve for Backlight Circuit
77
76
Efficiency (%)
75
74
73
72
71
70
69
68
67
66
0
10
20
30
40
Load Current(mA)
50
60
70
Efficiency Curve for Backlight Step Up Circuit
It is the ordinary TDK47uH inductor that has been applied in backlight circuit, and the diode
is RB491D Schottky.
When Vin=3.6V, Vout=12V
(Please refer to the corresponding schematic diagram of reference circuit for DC/DC circuit
components)
Li-ION mode: VBAT=3.6V
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Relation between VDD Load Current and the Efficiency
90
85
Efficiency(%)
80
75
70
65
60
55
50
0
10
20
30
40
50
60
70
80
90
100 110 120 130
140 150 160 170 180 190 200 210 220
230 240 250 260 270
Ivdd(mA)
DC/DC Efficiency Curve 1
Relation between VCC Load Current and the Efficiency
100
95
90
Efficiency(%)
85
80
75
70
65
60
55
50
0
10 20 30 40 50 60 70 80 90 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VCC Current(mA)
DC/DC Efficiency Curve 2
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Charging Curve—Voltage Characteristics Curve
Charging Curve—Current Characteristics Curve
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Note: the above results are measured when charging 270mAh Li-ion battery at the charging
current of 200mA.
LDO Load Capacity
LDO
Input
IVDD (vcc=1.6v)
IVCC(vcc=3.1v)
MIN
(mA)
Typical
(mA)
3.6V
320
350
4.5V
350
380
5.0V
420
480
MAX
(mA)
MIN
(mA)
Typical
(mA)
350
400
MAX
(mA)
Note: the parameter is tested when VOUT is 95%VIN.
23.6
AC Characteristics
(To = 0 to +70℃, VDD = 2 to 3 V, VCC = 2.7 to 3.6 V)
23.6.1
AC Test Input Waveform
23.6.2
Output Measuring Points
23.7
Reset Parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
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Reset input low-level width
23.8
230
us
Initialization Parameter
Parameter
Symbol
Data sampling time
(from RESET# )
Output delay time (from RESET# )
23.9
RESET# pin
tWRSL
Condition
MIN.
MAX.
Unit
tSS
120
us
tOD
120
us
GPIO Interface Parameter
Table 5: GPIO Interface Parameter
Parameter
Symbol
GPIO output rise time
tGPRISE
GPIO output fall time
tGPFALL
Condition
MIN.
TYPE
MAX.
Unit
3
40
ns
3
40
ns
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GPIO Interface -- Output time
Table 6: GPIO Drive
Rh (ohm)
Ioh (mA)
Rl (ohm)
Iol (mA)
Power on status
(CEOS=1)
GPIOA0(A0)
330.0
9.000
297.0
10.000
ale-0
GPIOA1(A1)
297.0
10.000
330.0
9.000
rb-1
GPIOA2 (A2)
330.0
9.000
297.0
10.000
cle-0
GPIOA6 (I2C1SCL)
330.0
9.000
330.0
9.000
z
GPIOA7 (I2C1SDA)
GPIOA8 (KSIN0)
330.0
9.000
330.0
9.000
z
990.0
3.000
742.5
4.000
1
GPIOA9 (KSIN1)
990.0
3.000
742.5
4.000
1
GPIOA10 (KSIN2)
1485.0
2.000
742.5
4.000
1
GPIOA11 (KSIN3)
990.0
3.000
742.5
4.000
z
GPIOA12 (KSOUT0)
1485.0
2.000
742.5
4.000
z
GPIOA13 (KSOUT1)
1485.0
2.000
742.5
4.000
0
GPIOA14 (WRB)
330.0
9.000
297.0
10.000
0
GPIOA15 (DRVVBUS)
GPIOA16 (CEB0)
330.0
9.000
330.0
9.000
0
330.0
9.000
297.0
10.000
1
GPIOA17 (CEB2)
330.0
9.000
297.0
10.000
1
GPIOA18 (SDRRASB)
198.0
15.000
135.0
22.000
0
GPIOA19 (SDRCASB)
371.3
8.000
297.0
10.000
uncertain
GPIOA20 (SDRWEB)
371.3
8.000
297.0
10.000
1
GPIOA21 (SDRA7)
371.3
8.000
297.0
10.000
1
GPIOA22 (SDRA8)
371.3
8.000
297.0
10.000
1
GPIOA23 (SDRA9)
371.3
8.000
297.0
10.000
1
GPIOA24 (SDRA10)
371.3
8.000
330.0
9.000
1
GPIOA25 (SDRA11)
371.3
8.000
330.0
9.000
0
GPIOA26 (SDRA12)
371.3
8.000
297.0
10.000
0
GPIOB28 (CEB5)
330.0
9.000
330.0
9.000
GPIOA31 (SIRQ0)
990.0
3.000
742.5
4.000
GPIOX (Name)
0
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GPIOB0 (GPIOB0)
330.0
9.000
297.0
10.000
z
GPIOB1 (GPIOB1)
330.0
9.000
330.0
9.000
z
GPIOB2 (GPIOB2)
330.0
9.000
297.0
10.000
z
GPIOB3 (GPIOB3)
330.0
9.000
330.0
9.000
z
GPIOB4 (A10)
330.0
9.000
330.0
9.000
z
GPIOB5 (GPIOB5)
330.0
9.000
330.0
9.000
z
GPIOB6 (GPIOB6)
330.0
9.000
297.0
10.000
z
GPIOB7 (GPIOB7)
330.0
9.000
330.0
9.000
z
GPIOB8 (GPIOB8)
371.3
8.000
330.0
9.000
z
GPIOB9 (GPIOB9)
330.0
9.000
330.0
9.000
z
GPIOB10 (GPIOB10)
330.0
9.000
330.0
9.000
z
GPIOB11 (GPIOB11)
330.0
9.000
297.0
10.000
z
GPIOB12 (UART2TX)
330.0
9.000
330.0
9.000
z
GPIOB13 (UART2RX)
330.0
9.000
330.0
9.000
z
GPIOB14 (UART1TX)
330.0
9.000
330.0
9.000
z
GPIOB15 (UART1RX)
330.0
9.000
330.0
9.000
z
GPIOB17 (CEB3)
330.0
9.000
297.0
10.000
z
GPIOB22 (KSOUT2)
990.0
3.000
990.0
3.000
1
GPIOB27 (CEB4)
330.0
9.000
297.0
10.000
1
GPIOB29 (CEB6)
212.1
14.000
165.0
18.000
1
GPIOB31 (SIRQ1)
1485.0
2.000
990.0
3.000
0
Notes:
1. Rh is internal pull up resistance, and IoH is drive ability of output H;
2. RL is internal pull down resistance, and IoL is drive ability of output L;
3. Power up status means the status start from BROM;
4. For those GPIO reused with SDRAM (A18-A26), there is HOLD circuit. Its pull up/down
resistance status is decided by the previous pad level status in Input Enable status. HOLD
circuit is meaningless in output status.
23.10
Ordinary ROM Parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Data access time (from address)
tACC
HOSC=24MHz
102
ns
Data access time (from CEx# )
tCE
HOSC=24MHz
82
ns
Data input setup time
tDS
HOSC=24MHz
0
ns
Data input hold time
tDH
HOSC=24MHz
0
ns
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23.11
External System Bus Parameter
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External System Bus Parameter
Parameter
Address setup time (to command signal)Note 1, 2
Symbol
Condition
MIN.
MAX.
Unit
tXAS
Memory Read
25
ns
tXAS
Memory Write
10
ns
Address hold time (from command signal)Note 1, 2
tXAH
5
ns
Data output setup time (to command signal)Note 1
tWXDS
20
ns
Data output hold time(from command signal)Note 1
tWXDH
10
ns
Data input setup time (to command signal)Note 1
tRXDS
20
ns
Data input hold time (from command signal)Note 1
tRXDH
10
ns
Notes: 1. MRD#, MWR# are called the command signals for the External System Bus Interface.
2. T (ns) = 1/ fMCUCLK
23.12
Bus Operation
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23.13
SPI Parameter
/CS
tWH
SCK
tdov:MOSI
tWL
tH:MOSI
MOSI
tSU:MISO
tH:MISO
MISO
SPI timing
coreCLK=180M, Sclk=90M, PCLK=45M, CLKDIV=3, SPICLK=7.5M, double the drive
ability at PAD_DRV.
SPI Parameter
Parameter
Symbol
SCK Clock
fclk
SCK High time
tWH
Min
Max
Unit
7.5
MHz
66
ns
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68
ns
SCK Low time
tWL
SCK rise time
tr
11.6
ns
SCK fall time
tf
12.8
ns
Data output valid
tDOV:MOSI
14
ns
Data output hold
tH:MOSI
100
ns
Data in setup time
tSU:MISO
14
ns
Data in hold time
tH:MISO
100
ns
23.14
SPDIF Interface Parameter
SPDIF Interface Parameter
Sampling Rate
Channel Bit
Theoretical Value
Channel Bit Tw+
Channel Bit Tw-
32K
244nS
242nS
246
44.1K
177nS
176nS
178
48K
163nS
161nS
163
23.15
I2C Interface Parameter
Parameter
Symbol
Typical
Unit
SCL period
fSCL
100
400
kHz
Clock low time
TLOW
5.0
1.26
us
Clock high time
THIGH
4.96
1.22
us
Clock rise time
tr
90
90
ns
Clock fall time
tf
7.5
8
ns
Data setup time
tSU:DAT
3.7
0.68
us
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Data hold time
tHD:DAT
1.24
0.74
us
Start hold time
tHD:STA
9.2
2.45
us
Start setup time
tSU:STA
5.3
1.3
us
Stop setup time
tSU:STO
5.3
1.3
us
23.16
A/D Converter Characteristics
(TA = -10 - +70℃, VDD = 1.8 V, VCC = 3.1V, Sample Rate=48KHz)
Characteristics
Min.
Typ.
Max.
Unit
Dynamic Range –40 dBFS Input
89
dB
Total Harmonic Distortion+Noise
-81
dB
Frequency Response 20-18KHz
0.5
dB
Reference Voltage
1.510
V
Full Scale Input Voltage
2.58
Vpp
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A/D Converter -- Frequency Response Characteristics
A/D Converter -- THD+N vs AMP
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A/D Converter --Small Signal Power Spectrum
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A/D Converter -- Linearity
23.17
DAC Characteristics
DAC Characteristics
Characteristics
MIN.
Typ.
MAX.
UNIT
Dynamic Range –48 dBFS Input
91.5
dB
Total Harmonic Distortion + Noise
-85.5
dB
Full Scale Output Voltage
Interchannel Isolation (1k)
0.48
0.58
0.72
-99/-81
Vrms
dB
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DAC --Small Signal Power Spectrum
23.18
Headphone Driver Characteristics
(TA =-10 - +70℃, VDD = 2.0 V, VCC = 3.0 V, Sample Rate=48KHz, Volume Level=0x1F)
Characteristics
MIN.
Typ.
MAX.
UNIT
Dynamic Range
94
dB
Total Harmonic Distortion+Noise
-90
dB
Output Common Mode Voltage
1.516
Vrms
Full Scale Output Voltage@-70dB thd+n
1.77
Vpp
Output Power @16ohm
24
mW
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Headphone Driver–Frequency Response
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Headphone Driver--THD + N Amplitude Diagram of Headphone Driver
Headphone Driver—Linearity
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Headphone Driver--Small Signal Power Spectrum
23.19
LCM Driver Parameter
LCM Timing
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LCM Driver Parameter
Item
Symbol
Unit
Min.
Typ.
Max.
Test Condition
Write
tCYCW
ns
34
200
-
AHB clk.=60MHz
Read
tCYCR
ns
34
134
-
AHB clk.=60MHz
Write low-level pulse width
PWLW
ns
17
100
-
AHB clk.=60MHz
Read low-level pulse width
PWLR
ns
17
67
-
AHB clk.=60MHz
Write high-level pulse width
PWHW
ns
17
100
-
AHB clk.=60MHz
Read high-level pulse width
PWHR
ns
17
67
-
AHB clk.=60MHz
Write / Read rise / fall time
tWRr ,
tWRf
ns
-
11
-
AHB clk.=60MHz
Write data set up time
tDSW
ns
27
110
-
AHB clk.=60MHz
Write data hold time
tH
ns
23
28
-
AHB clk.=60MHz
Read data delay time
tDDR
ns
-
45
-
AHB clk.=60MHz
Read data hold time
tDHR
ns
-
105
-
AHB clk.=60MHz
Bus cycle time
23.20
NAND Flash IF
Data Fetch at RD# Rising Edge
Conventional Serial Access Mode
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Data Fetch at RD# Falling Edge
EDO Type Serial Access Mode
IO[15:8] must be set to zero
Command Latch Cycle
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IO[15:8] must be set to zero
Address Latch Cycle
Nand Flash Timing Request
Item
Conventional
Serial Access
EDO Type Serial Access
tCEA
23nS (min)
23nS (min)
tREA
30nS (max)
18nS (max)
tREH
15nS (min)
12.5nS (min)
tRP
25nS (min)
12.5nS (min)
tRC
30nS (min)
25nS (min)
Data Fetch
At RD# Rising Edge
At next RD# Falling Edge
tFALLING
5nS
5nS
tRISINFG
5nS
5nS
tCLS
25nS (min)
12nS (min)
tCLH
10nS (min)
5nS (min)
tCS
35nS (min)
20nS (min)
tCH
10nS (min)
5nS (min)
tALS
25nS (min)
12nS (min)
Remark
Conventional: duty≠50%
EDO type: duty=50%
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tALH
10nS (min)
5nS (min)
tDS
20nS (min)
12nS (min)
tDH
10nS (min)
5nS (min)
tWC
30nS (min)
25nS (min)
DMA clk
30MHz
40MHz
23.21
SD Card
Timing Diagram Data Input/Output Referenced to Clock
Card Interface Timings
Parameter
Symbol
Min.
Max.
Unit
Remark
Clock CLK
Clock frequency data Transfer Mode
(Push Pull)
fpp
0
26/52
MHz
CL<=30pF(tolerance
+100KHz)
Clock frequency identification
Mode(Open Drain)
fOD
0
400
KHz
Tolerance:+20KHz
Clock low time
tWL
6.5
ns
CL<=30pF
Clock rise time
tTLH
ns
CL<=30pF
3
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Clock fall time
3
ns
CL<=30pF
Inputs CMD DAT (reference to CLK)
Input setup time
tISU
3
ns
CL<=30pF
Input hold time
tIH
3
ns
CL<=30pF
Output CMD DAT(reference to CLK)
Output setup time
tOSU
5
ns
CL<=30pF
Output hold time
tOH
5
ns
CL<=30pF
Signal rise time
trise
3
ns
CL<=30pF
Signal fall time
tfall
3
ns
CL<=30pF
Bus Signal Line Load
Parameter
Symbol
Min
Recommend
Max
Unit
Pull up resistance for
CMD
Rcmd
4.7
10
100
KOhm
To prevent bus
floating
Pull up resistance for
dat0-7
Rdat
50
50
100
KOhm
To prevent bus
floating
CL
30
pF
Ccard
7
pF
16
nH
Bus signal line
capacitance
Signal card capacitance
Maximum signal line
inductance
Remark
Single card
Fpp<=52MHz
CL=CHost+Cbus+Ccard
SD Spec. ver1.0 Timing
Parameter
Symbol
Min
Max
Unit
Remark
Clock Frequency Data transfer mode
fpp
0
25
MHz
CL<=100Pf
Clock Frequency identification mode
fOD
0~100
400
KHz
CL<=250pF
Clock Low Time
tWL
10
Ns
CL<=100pF
Clock High Time
TWH
10
Ns
CL<=100pF
Clock Rise Time
tTLH
10
Ns
CL<=100pF
Clock Fall Time
tTHL
10
Ns
CL<=100pF
Clock Low Time
tWL
50
Ns
CL<=100pF
Clock High Time
TWH
50
Ns
CL<=100pF
Clock Rise Time
tTLH
50
Ns
CL<=100pF
Clock Fall Time
tTHL
50
Ns
CL<=100pF
Input Set-up Time
tISU
5
Ns
CL<=25pF
Input Hold Time
tIH
5
Ns
CL<=25pF
Ns
CL<=25pF
Output Delay Time under Data Transfer
tODLY
14
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Mode
Output Delay time under identification
transfer mode
23.22
tODLY
50
Ns
CL<=25pF
SDRAM IF
Standard SDRAM Power Up
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Mobile SDRAM Power Up
NOTE:
1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock high time, all commands applied are NOP.
3. Outputs are guaranteed High-Z after command is issued.
4. A12 should be a LOW at tP + 1.
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SDRAM IF-- Power Down
NOTE:
1. Violating refresh requirements during power-down may result in a loss of data.
2. CAS latency indicated in parentheses
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SDRAM IF-- Clock Suspend
NOTE:
1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is
disabled.
2. CAS latency indicated in parentheses
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SDRAM IF-- Auto Refresh
NOTE:
1. CAS latency indicated in parentheses
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SDRAM IF -- Self Refresh
NOTE:
1. No maximum time limit for Self Refresh. tRAS(MIN) applies to non-Self Refresh mode.
2. tXSR requires minimum of two clocks regardless of frequency or timing.
3. CAS latency indicated in parentheses
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SDRAM IF-- Read
NOTE:
1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed
by a “manual” PRECHARGE.
2. CAS latency indicated in parentheses
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SDRAM IF -- Read DQM Operation
NOTE:
1. For this example, the burst length = 4, and the CAS latency = 2.
2. CAS latency indicated in parentheses.
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SDRAM IF-- Write
NOTE:
1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual”
PRECHARGE.
2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of
frequency.
3. CAS latency indicated in parentheses.
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SDRAM IF-- Write-DQM Operation
NOTE:
1. For this example, the burst length = 4.
2. CAS latency indicated in parentheses.
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SDRAM IF -- Parameter
AC Characteristics
Symbol
Parameter
Access time from CLK
(positive edge)
PC-100
Min
Max
Units
CL =
3
tAC (3)
7
ns
CL =
2
tAC (2)
8
ns
Address hold time
tAH
1
ns
Address setup time
tAS
2.5
ns
CLK high-level width
tCH
3
ns
CLK low-level width
tCL
3
ns
CL =
3
tCK (3)
10
ns
CL =
2
tCK (2)
12
ns
CKE hold time
tCKH
1
ns
CKE setup time
tCKS
2.5
ns
CS#, RAS#, CAS#, WE#, DQM
hold time
tCMH
1
ns
CS#, RAS#, CAS#, WE#, DQM
setup time
tCMS
2.5
ns
Data-in hold time
tDH
1
ns
Data-in setup time
tDS
2.5
ns
Clock cycle time
Data-out High-Z time
CL =
3
tHZ (3)
7
ns
CL =
2
tHZ (2)
8
ns
Data-out Low-Z time
tLZ
1
ns
Data-out hold time (load)
tOH
2.5
ns
Data-out hold time (no load)
tOHN
1.8
ns
ACTIVE-to-PRECHARGE command
tRAS
50
ACTIVE-to-ACTIVE command
period
tRC
100
ns
ACTIVE-to-READ or WRITE delay
tRCD
20
ns
Refresh period
tREF
AUTO REFRESH command period
tRFC
100
ns
PRECHARGE command period
tRP
20
ns
ACTIVE bank a to ACTIVE bank b
tRRD
2
tCK
120,000
64
ns
ms
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command
Transition time
tT
0.5
1.2
ns
WRITE recovery time Auto
precharge mode (a)
tWR
(a)
1 CLK +5ns
–
Manual precharge mode (m)
tWR
(m)
15
ns
Exit SELF REFRESH to ACTIVE
command
tXSR
100
ns
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24 Ordering Information
24.1
Recommended Soldering Conditions
Soldering Conditions for Surface-mount Devices
Soldering
Process
Soldering Conditions
Peak package’s surface temperature: 235℃ (Lead) or 260℃ (Lead Free)
Reflow time: 30 seconds or less (210℃or more)----(Lead) or 60 seconds or less
Infrared Ray Reflow
(217℃or more)---- (Lead Free)
Maximum allowable number of reflow processes: 2
Exposure limit: 1 days at Rh=60%, Tem=30℃ (12 hours of pre-baking is
required at 125℃ afterward).
Partial heating
method
Terminal temperature: 300℃ or less
Heat time: 3 seconds or less (for one side of a device)
Note:
The maximum number of days during which the product can be stored at a temperature of
25℃ and a relative humidity of 65% or less after dry-pack package is opened.
Caution:
Do not apply two or more different soldering methods to one chip (except for partial heating
method for terminal sections).
24.2
Precaution against ESD for Semiconductors
When the strong electric field is exposed to a MOS device, the destruction of the gate oxide
may occur and then it can ultimately degrade the device operation. Measures must be taken
to stop the generation of static electricity as many as possible, and it is a must to quickly
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dissipate the static electricity when it occurs. Environmental control must be adequate
enough. Humidifier should be used when it is dry. Recommend to avoid using insulators,
which may easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container or a static shielding bag or objects made from
conductive material. All test and measurement tools including work bench and floor should
be grounded. The operator shall be grounded by using wrist strap. Semiconductor devices
shall not be touched with bare hands. Similar precautions shall be taken for PW boards with
semiconductor devices on it.
24.3
Handling of Unused Input Pins for CMOS
The cause for no connection to CMOS device inputs can be the malfunction. If no connection
is provided for the input pins, the possible cause is that an internal input level may be
generated due to noise, etc., which results in malfunction. CMOS devices behave differently
from Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by
using a pull-up or pull-down circuitry. Each unused pin shall be connected to the
corresponding power SDRVP/VCC etc. or GND with a resistor, if it is considered to have the
possibility of being an output pin. All handling related to the unused pins must be judged
device by device and follows the related specifications governing the devices.
24.4
Status before Initialization of MOS Devices
Power-on does not necessarily define the initial status of MOS device. Production process of
MOS does not define the initial operation status of the device. Immediately after the power
source is turned on, the devices with reset function have not yet been initialized. Hence,
power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is
not initialized until the reset signal is received. Reset operation must be executed
immediately after the power-on.
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25 Pin Description
25.1
ATJ 2256
25.1.1 Pin Definition
Pin
No.
Pin Name
Function Name
I/O Type
Reset
Default
1
LOSCI
LOSCI
AI
Low Oscillator Input
2
LOSCO
LOSCO
AO
Low Oscillator Output
ATA_CS1B/
3
CEB5
NOR_CEB5/
NF_CEB2
4
CEB2
Ata Interface CS1
O
Nor Flash CE5
RGB_CE
GPIOB28
/RGB_CE
GPIOA17
NF_CEB1
Description
RGB Interface CE
BI
O
GPIOB Port 28
NAND FLASH Interface CE2
1
BI
RGB Interface CE
GPIOA Port 17
NAND FLASH Interface CE1
5
CEB1
6
SIRQ1
7
WRB
8
RDB
9
VDD
VDD
PWRI
VDD
10
VCC
VCC
PWRI
VCC
11
GND
GND
PWR
GND
/RGB_CE
O
SIRQ1
I
GPIOB31
BI
NF_WR
/RGB_WRB
NF_RD
/RGB_RDB
O
O
RGB Interface CE
z
External IRQ 1
GPIOB Port 31
NAND FLASH Interface WR
RGB Interface WR
NAND FLASH Interface RD
RGB Interface RD
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12
SDRBA0
SDRAM_BA0
O
SDRAM Interface Bank Address0
13
SDRDQ0
SDRAM_DQ0
BI
SDRAM Interface Data 0
14
SDRA0
SDRAM_A0
O
SDRAM Interface Address 0
15
SDRA1
SDRAM_A1
O
SDRAM Interface Address 1
16
SDRDQ1
SDRAM_DQ1
BI
SDRAM Interface Data 1
17
SDRA2
SDRAM_A2
O
SDRAM Interface Address2
18
SDRBA1
SDRAM_BA1
O
SDRAM Interface Bank Address 1
19
SDRA3
SDRAM_A3
O
SDRAM Interface Address 3
20
SDRDQ2
SDRAM_DQ2
BI
SDRAM Interface Data 2
21
SDRA4
SDRAM_A4
O
SDRAM Interface Address 4
22
SDRA5
SDRAM_A5
O
SDRAM Interface Address 5
23
SDRDQ3
SDRAM_DQ3
BI
SDRAM Interface Data 3
24
SDRA6
SDRAM_A6
O
SDRAM Interface Address 6
25
SDRVP
SDRAM_VP
PWRI
SDRAM Interface Power
26
SDRDQ4
SDRAM_DQ4
BI
SDRAM Interface Data 4
27
SDRA7
SDRAM_A7
O
SDRAM Interface Address 7
28
SDRA8
SDRAM_A8
O
SDRAM Interface Address 8
29
SDRDQ5
SDRAM_DQ5
BI
SDRAM Interface Data 5
30
SDRA9
SDRAM_A9
O
SDRAM Interface Address 9
31
SDRA10
SDRAM_A10
O
SDRAM Address 10
32
SDRDQ6
SDRAM_DQ6
BI
SDRAM Interface Data 6
SDRAM_A11
O
SDRAM Interface Address11
GPIOA25
BI
GPIOA Port 25
33
SDRA11
34
SDRDQ7
SDRAM_DQ7
BI
SDRAM Interface Data7
35
SDRWEB
SDRAM_WEB
O
SDRAM Interface Write Enable
36
SDRDQ8
SDRAM_DQ8
BI
SDRAM Interface Data 8
37
SDRA12
SDRAM_A12
O
SDRAM Interface Address12
GPIOA26
BI
GPIOA Port 26
38
SDRDQ9
SDRAM_DQ9
BI
SDRAM Interface Data 9
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39
SDRDQ10
SDRAM_DQ10
BI
SDRAM Interface Data10
40
SDRDQ11
SDRAM_DQ11
BI
SDRAM Interface Data11
41
SDRDQ12
SDRAM_DQ12
BI
SDRAM Interface Data 12
42
SDRRASB
SDRAM_RASB
O
SDRAM Interface RAS
43
SDRCASB
SDRAM_CASB
O
SDRAM Interface CAS
44
SDRDQ13
SDRAM_DQ13
BI
SDRAM Interface Data13
45
SDRCSB
SDRAM_CSB
O
SDRAM Interface CS
46
SDRGND
SDRAM_GND
PWR
SDRAM Interface GND
47
SDRVP
SDRAM_VP
PWRI
SDRAM Interface Power
48
SDRCK
SDRAM_CK
O
SDRAM Interface Clock
49
SDRCKE
SDRAM_CKE
O
SDRAM Interface Clock Enable
50
SDRDQM0
SDRAM_LDQM
O
51
SDRDQ14
SDRAM_DQ14
BI
SDRAM Interface LDQM (for 16bits
SDRAM)
SDRAM Data14
SDRAM Interface DQM
52
SDRDQM1
SDRAM_DQM/UD
QM
O
(for 8bits SDRAM)
SDRAM Interface UDQM
(for 16bits SDRAM)
53
SDRDQ15
SDRAM_DQ15
BI
SDRAM Interface Data15
54
NC
55
VBUS
VBUS
I
VBUS
56
ID
ID
BI
OTG Interface ID
57
UVCC
UVCC
PWR
UVCC
58
DP
DP
BI
Data Plus
59
DM
DM
BI
Data Minus
60
UGND
UGND
PWR
UGND
61
RREF
RREF
AO
Reference Resistance
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UART1_RX
/SPI_MISO
62
UART1RX
/I2C2_SDA
Uart1 Interface RX
BI
z
/SPDIF_RX
GPIOB15
63
UART1TX
/I2C2_SCL
I2C2 Interface SDA
SPDIF Interface RX
BI
GPIOB Port 15
UART1_TX
/SPI_SS
SPI Interface MISO
Uart1 Interface Tx
BI
1
/SPDIF_TX
SPI Interface Slave Selection
I2C2 Interface SCL
SPDIF Interface TX
GPIOB14
BI
GPIOB Port 14
64
MICIN
MICIN
AI
Microphone In Left Channel
65
VMIC
VMIC
AI
Microphone Power Supply
66
FMINR
FMINR
AI
FM In Right Channel
67
FMINL
FMINL
AI
FM in Left Channel
68
AGND
AGND
PWR
Audio Analog GND
69
AVCC
AVCC
PWRO
Audio Analog VCC
70
VRDA
VRDA
AO
Audio DAC Voltage Reference
71
VREFI
VREFI
AI
Voltage Reference Input
72
PAGND
PAGND
PWR
Audio PA GND
73
AOUTR
AOUTR
AO
Audio output Right Channel
74
PAVCC
PAVCC
PWRO
Audio PA VCC
75
AOUTL
AOUTL
AO
Audio output Left Channel
76
TVCVBS
TVCVBS
AO
Video CVBS signal Output
77
TVREF
TVREF
AO
TV reference Resistance
78
AVDD
AVDD
PWRO
Audio VDD
79
HOSCO
HOSCO
AO
High Oscillator Output
80
HOSCI
HOSCI
AI
High Oscillator Input
81
VCC
VCC
PWRI
VCC
82
KSIN2
KSIN[2]
BI
GPIOA10
BI
1
Key Scan Input2
GPIOA Port 10
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KS_OUT[2]
BI
GPIOB22
BI
KS_IN[1]
BI
GPIOA9
BI
KS_OUT[1]
BI
GPIOA13
BI
KS_IN[0]
BI
GPIOA8
BI
KS_OUT[0]
BI
GPIOA12
BI
CEB3
NF_CEB3
O
NAND FLASH Interface CE3
RESETB
RESETB
I
System RESET
TEST
I
83
KSOUT2
84
KSIN1
85
KSOUT1
86
KSIN0
87
KSOUT0
88
89
90
TEST
/CLKOUT
1
1
z
1
z
91
I2C1SDA
/UART1_CTSB
92
I2C1SCL
/UART1_RTSB
GPIOA Port 9
Key Scan Output 1
GPIOA Port 13
KEY Scan in 0
GPIOA Port 8
Key Scan Output 0
GPIOA Port12
I2C1 Interface SDA
BI
UART2 or IrDA Interface RX
z
Uart1 Interface CTS
SPI Interface Master Output Slave in
BI
GPIOA Port 7
I2C1_SCL
/UART2IR_TX
Key Scan Input 1
FM Module Clock out
/SPI_MOSI
GPIOA7
GPIOB Port 22
TEST
I2C1_SDA
/UART2IR_RX
Key Scan output 2
I2C1 Interface SCL
BI
/SPI_SCK
UART2 or IrDA Interface TX
z
Uart1 Interface RTS
SPI Interface Clock
GPIOA6
BI
GPIOA Port 6
93
BL_NDR
BL_NDR
AO
Back Light NDR
94
REM_CON
REM_CON
AI
Remote Control ADC input
95
IO_VDD
IO_VDD
PWR
POWER Pin IOVDD
96
LXVDD
LXVDD
PWR
POWER Pin LXVDD
97
PGND
PGND
PWR
POWER MOS GND
98
BAT
BAT
PWRI
Battery input
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99
DC5V
DC5V
PWRI
DC5V input
100
VCC
VCC
PWRIO
VCC
101
VDD
VDD
PWRIO
VDD
102
GND
GND
PWR
GND
103
SIRQ0
External IRQ 0
I
External IRQ 0
GPIOA Port 31
BI
GPIOA Port 31
SD_CLK
104
CEB6
/CE6
GPIOB29
NF_ALE
105
A0
/RGB_WD[0]
GPIOA0
NF_RB
106
A1
/RGB_WD[9]
GPIOA1
O
SD CARD Interface CLOCK
1
BI
O
GPIOB Port 29
NAND FLASH ALE
0
BI
O
107
/RGB_RS
NAND FLASH Interface Ready/Busy
0
BI
O
BI
NF_D[8]
108
109
110
D0
D1
D2
/RGB_WD[1]
RGB Interface Data 9
GPIOA Port 1
NAND FLASH Interface CLE
/SD_CMD
GPIOA2
RGB Interface Data0
GPIOA Port 0
NF_CLE
A2
LCD Interface CE6
0
RGB Interface RS
SD card Interface CMD
GPIOA Port 2
NAND FLASH Data 8
BI
RGB Interface Data 1
/SD_DAT[0]
SD Card Interface Data 0
NF_D[9]
NAND FLASH Interface Data 9
/RGB_WD[2]
BI
RGB Interface Data 2
/SD_DAT[1]
SD Card Interface Data 1
NF_D[10]
NAND FLASH Interface Data 10
/RGB_WD[3]
/SD_DAT[2]
BI
RGB Interface Data 3
SD Card Interface Data 2
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NF_D[11]
111
112
113
114
115
D3
/RGB_WD[4]
D4
NF_D[12]
NAND FLASH Interface Data 12
BI
SD Card Interface Data 4
NF_D[13]
NAND FLASH Interface Data 13
BI
SD card Interface Data 5
NF_D[14]
NAND FLASH Interface Data 14
BI
117
VDD
118
D8
119
D9
120
D10
121
D11
122
D12
123
D13
RGB Interface Data 7
/SD_DAT[6]
SD card Interface Data 6
NF_D[15]
NAND FLASH Interface Data 15
BI
/SD_DAT[7]
CEB0
RGB Interface Data 6
/SD_DAT[5]
/RGB_WD[8]
116
RGB Interface Data 5
/SD_DAT[4]
/RGB_WD[7]
D7
RGB Interface Data 4
SD Card Interface Data 3
/RGB_WD[6]
D6
BI
/SD_DAT[3]
/RGB_WD[5]
D5
NAND FLASH Interface Data 11
RGB Interface Data 8
SD card Interface Data 7
NF_CEB0
O
NAND FLASH Interface CE0
GPIOA16
BI
GPIOA Port 16
VDD
PWRI
VDD
NF_D[0]
/RGB_WD[10]
NF_D[1]
/RGB_WD[11]
NF_D[2]
/RGB_WD[12]
NF_D[3]
/RGB_WD[13]
NF_D[4]
/RGB_WD[14]
NF_D[5]
/RGB_WD[15]
BI
BI
BI
BI
BI
BI
NAND FLASH Data 0
RGB Interface Data 10
NAND FLASH Interface Data 1
RGB Interface Data 11
NAND FLASH Interface Data 2
RGB Interface Data 12
NAND FLASH Interface 3
RGB Interface Data 13
NAND FLASH Data 4
RGB Interface Data 14
NAND FLASH Interface Data 5
RGB Interface WD 15
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KS_IN[3]
KSIN3
125
D14
126
D15
127
GND
GND
PWR
GND
128
RTCVDD
RTCVDD
PWRI
RTC Power VDD
/ GPIOA11
NF_D[6]
/RGB_WD[16]
NF_D[7]
/RGB_WD[17]
BI
Key scan input 3
127
BI
BI
GPIOA port 11
NAND FLASH Data 6
RGB Interface Data 16
NAND FLASH Interface Data 7
RGB Interface Data 17
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
25.1.2 Pin Assignment
25.2
ATJ 2257
25.2.1 Pin Definition
Pin No.
Pin Name
Function Name
I/O Type
1
LOSCI
LOSCI
AI
Reset
Default
Short Description
Low Oscillator Input
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
2
LOSCO
LOSCO
CEB2
NF_CEB2
3
RGB_CE
GPIOA17
4
5
6
CEB1
NF_CEB1
RGB_CE
GPIOB6
SIRQ1
DRVVBUS
7
AO
NAND FLASH Interface CE2
O
GPIOB6
BI
SIRQ1
I
GPIOB31
BI
O
BI
NAND FLASH Interface CE1
RGB Interface CE
0
z
9
10
11
12
WRB
NF_WR
RGB_WRB
GPIOB7
RDB
0
GPIOB8
GPIOB11
External IRQ 1
GPIOB Port 31
RGB Interface RD
NAND FLASH Interface WR
O
BI
GPIOB7
BI
RGB_RDB
GPIOB Port 6
GPIOA Port 15
BT656_D[7]
NF_RD
BT656 Interface Data 6
OTG Interface VBUS
GPIOA15
8
RGB Interface CE
GPIOA Port 17
O
BI
RGB_RDB
1
BI
BT656_D[6]
DRV_VBUS
Low Oscillator Output
RGB Interface WR
0
BI
GPIOB8
BI
BT656_CLKOUT
BI
GPIOB11
BI
GPIOB Port 7
NAND FLASH Interface RD
O
BT656_PCLK
BT656 Interface Data 7
RGB Interface RD
0
0
BT656 Interface PCLK
GPIOB Port 8
BT656 Interface CLKOUT
GPIOB Port 11
13
VDD
VDD
PWRI
VDD
14
VCC
VCC
PWRI
VCC
15
GND
GND
PWR
GND
16
SDRBA0
SDRAM_BA0
O
SDRAM Interface Bank Address0
17
SDRDQ0
SDRAM_DQ0
BI
SDRAM Interface Data 0
18
SDRA0
SDRAM_A0
O
SDRAM Interface Address 0
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
19
SDRA1
SDRAM_A1
O
SDRAM Interface Address 1
20
SDRDQ1
SDRAM_DQ1
BI
SDRAM Interface Data 1
21
SDRA2
SDRAM_A2
O
SDRAM Interface Address2
22
SDRBA1
SDRAM_BA1
O
SDRAM Interface Bank Address 1
23
SDRA3
SDRAM_A3
O
SDRAM Interface Address 3
24
SDRDQ2
SDRAM_DQ2
BI
SDRAM Interface Data 2
25
SDRA4
SDRAM_A4
O
SDRAM Interface Address 4
26
SDRA5
SDRAM_A5
O
SDRAM Interface Address 5
27
SDRDQ3
SDRAM_DQ3
BI
SDRAM Interface Data 3
28
SDRA6
SDRAM_A6
O
SDRAM Interface Address 6
29
SDRVP
SDRAM_VP
PWRI
SDRAM Interface Power
30
SDRGND
SDRAM_GND
PWR
SDRAM Interface GND
31
SDRDQ4
SDRAM_DQ4
BI
SDRAM Interface Data 4
32
SDRA7
SDRAM_A7
O
SDRAM Interface Address 7
33
SDRA8
SDRAM_A8
O
SDRAM Interface Address 8
34
SDRDQ5
SDRAM_DQ5
BI
SDRAM Interface Data 5
35
SDRA9
SDRAM_A9
O
SDRAM Interface Address 9
36
SDRA10
SDRAM_A10
O
SDRAM Address 10
37
SDRDQ6
SDRAM_DQ6
BI
SDRAM Interface Data 6
SDRA11
SDRAM_A11
O
SDRAM Interface Address11
GPIOA25
BI
GPIOA Port 25
38
39
SDRDQ7
SDRAM_DQ7
BI
SDRAM Interface Data7
40
SDRWEB
SDRAM_WEB
O
SDRAM Interface Write Enable
41
SDRDQ8
SDRAM_DQ8
BI
SDRAM Interface Data 8
SDRA12
SDRAM_A12
O
SDRAM Interface Address12
GPIOA26
BI
GPIOA Port 26
42
43
SDRDQ9
SDRAM_DQ9
BI
SDRAM Interface Data 9
44
SDRDQ10
SDRAM_DQ10
BI
SDRAM Interface Data10
45
SDRDQ11
SDRAM_DQ11
BI
SDRAM Interface Data11
46
SDRDQ12
SDRAM_DQ12
BI
SDRAM Interface Data 12
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47
SDRRASB
SDRAM_RASB
O
SDRAM Interface RAS
48
SDRCASB
SDRAM_CASB
O
SDRAM Interface CAS
49
SDRDQ13
SDRAM_DQ13
BI
SDRAM Interface Data13
50
SDRCSB
SDRAM_CSB
O
SDRAM Interface CS
51
SDRGND
SDRAM_GND
PWR
SDRAM Interface GND
52
SDRVP
SDRAM_VP
PWRI
SDRAM Interface Power
53
SDRCK
SDRAM_CK
O
SDRAM Interface Clock
54
SDRCKE
SDRAM_CKE
O
SDRAM Interface Clock Enable
SDRAM_LDQM
O
SDRAM_DQ14
BI
55
56
SDRDQM0
SDRDQ14
SDRDQM1
SDRAM Interface LDQM(for 16bits
SDRAM)
SDRAM Data14
SDRAM Interface DQM
SDRAM_DQM
57
(for 8bits SDRAM)
O
SDRAM Interface UDQM
UDQM
(for 16bits SDRAM)
58
SDRDQ15
SDRAM_DQ15
BI
SDRAM Interface Data15
59
VBUS
VBUS
I
OTG Interface VBUS
60
ID
ID
BI
OTG Interface ID
61
UVCC
UVCC
PWR
OTG Interface UVCC
62
DP
DP
BI
OTG Interface Data Plus
63
DM
DM
BI
OTG Interface Data Minus
64
UGND
UGND
PWR
OTG Interface UGND
65
UREF
RREF
AO
OTG Interface Reference Resistance
66
UGNDS
UGNDS
PWR
OTG Interface UGND
67
UVCCS
UVCCS
PWR
OTG Interface UVCC
UART1RX
UART1_RX
SPI_MISO
68
I2C2_SDA
Uart1 Interface RX
BI
SPI Interface MISO
z
I2C2 Interface SDA
SPDIF_RX
SPDIF Interface RX
GPIOB15
GPIOB Port 15
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
UART1TX
UART1_TX
SPI_SS
69
I2C2_SCL
Uart1 Interface Tx
BI
SPI Interface Slave Selection
1
I2C2 Interface SCL
SPDIF_TX
SPDIF Interface TX
GPIOB14
GPIOB Port 14
70
MICIN
MICIN
AI
Microphone Input
71
VMIC
VMIC
AI
Microphone Power Supply
72
FMINR
FMINR
AI
FM Input Right Channel
73
FMINL
FMINL
AI
FM input Left Channel
74
AGND
AGND
PWR
Audio Analog GND
75
AVCC
AVCC
PWRO
Audio Analog VCC
76
VRDA
VRDA
AO
Audio DAC Voltage Reference
77
VREFI
VREFI
AI
Voltage Reference Input
78
PAGND
PAGND
PWR
Audio PA GND
79
AOUTR
AOUTR
AO
Audio output Right Channel
80
PAVCC
PAVCC
PWRO
Audio PA VCC
81
AOUTL
AOUTL
AO
Audio output Left Channel
82
TVOUT
TVCVBS
AO
Video CVBS signal Output
83
TVREF
TVREF
AO
TV reference Resistance
84
AVDD
AVDD
PWRO
Audio VDD
85
HOSCO
HOSCO
AO
High Oscillator Output
86
HOSCI
HOSCI
AI
High Oscillator Input
87
VCC
VCC
PWRI
VCC
KSIN2
KSIN[2]
BI
GPIOA10
BI
KS_OUT[2]
BI
GPIOB22
BI
KS_IN[1]
BI
GPIOA9
BI
KS_OUT[1]
BI
88
89
90
91
KSOUT2
KSIN1
KSOUT1
1
1
1
z
Key Scan Input2
GPIOA Port 10
Key Scan output 2
GPIOB Port 22
Key Scan Input 1
GPIOA Port 9
Key Scan Output 1
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
92
93
KSIN0
KSOUT0
GPIOA13
BI
KS_IN[0]
BI
GPIOA8
BI
KS_OUT[0]
BI
GPIOA12
BI
GPIOA Port 13
1
z
KEY Scan in 0
GPIOA Port 8
Key Scan Output 0
GPIOA Port12
94
CEB3
NF_CEB3
O
NAND FLASH Interface CE3
95
RESET
RESETB
I
System RESET
96
TEST
TEST
TEST
I
FM Module Clock out
CLKOUT
97
98
GPIOB5
GPIOB4
I2C1SDA
BT656_D[5]
BI
GPIOB5
BI
BT656_D[4]
BI
GPIOB4
BI
I2C1_SDA
BI
0
0
z
UART2IR_RX
99
UART1_CTSB
SPI_MOSI
I2C1SCL
102
103
GPIOB9
BL_NDR
GPIOB Port 4
I2C1 Interface SDA
Uart1 Interface CTS
BI
SPI Interface Master Output Slave in
GPIOA Port 7
I2C1_SCL
I2C1 Interface SCL
BI
UART1_RTSB
GPIOB10
BT656 Interface Data 4
Uart2 or IrDA Interface Rx
Uart2 or IrDA Interface Tx
z
SPI_SCK
101
GPIOB Port 5
GPIOA7
UART2IR_TX
100
BT656 Interface Data 5
SPI Interface Clock
GPIOA6
BI
BT656_VSYNC
BI
GPIOB10
BI
BT656_HSYNC
BI
GPIOB9
BI
BL_NDR
(PFM/PWM)
Uart1 Interface RTS
AO
GPIOA Port 6
0
0
BT656 Interface VSYNC
GPIOB Port 10
BT656 Interface HSYNC
GPIOB Port 9
Back Light NDR
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
104
REM_CON
REM_CON
AI
Remote Control ADC input
105
BL_FB
BL_FB
O
Back Light Feed Back
106
IO_VDD
IO_VDD
PWR
POWER Pin IOVDD
107
LXVDD
LXVDD
PWR
POWER Pin LXVDD
108
PGND
PGND
PWR
POWER MOS GND
109
PGND
PGND
PWR
POWER MOS GND
110
LXVCC
LXVCC
PWR
POWER Pin LXVCC
111
IO_VCC
IO_VCC
PWR
POWER Pin IOVCC
112
BAT
BAT
PWRI
Battery input
113
DC5V
DC5V
PWRI
DC5V input
114
VCC
VCC
PWRIO
VCC
115
VDD
VDD
PWRIO
VDD
116
VCCOUT
VCCOUT
PWRO
Programmed VCC output
117
GND
GND
PWR
GND
CEB6
SD_CLK
O
GPIOB29
BI
118
NF_ALE
A0
119
RGB_WD[0]
GPIOA0
NF_RB
A1
120
RGB_WD[9]
GPIOA1
RGB_RS
121
123
GPIOB0
RGB Interface Data0
NAND FLASH Interface Ready/Busy
0
RGB Interface Data 9
GPIOA Port 1
NAND FLASH Interface CLE
O
GPIOA2
BI
BT656_D[0]
BI
GPIOB0
BI
NF_D[8]
BI
RGB_WD[1]
GPIOB Port 29
GPIOA Port 0
BI
SD_CMD
D0
0
BI
O
SD CARD Interface CLOCK
NAND FLASH ALE
NF_CLE
A2
122
O
1
0
RGB Interface RS
SD card Interface CMD
GPIOA Port 2
0
BT656 Interface Data 0
GPIOB Port 0
NAND FLASH Data 8
RGB Interface Data 1
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SD_DAT[0]
124
GPIOB1
SD Card Interface Data 0
BT656_D[1]
BI
GPIOB1
BI
0
NF_D[9]
D1
RGB_WD[2]
125
GPIOB2
D2
RGB Interface Data 2
BI
SD Card Interface Data 1
BT656_D[2]
BI
GPIOB2
BI
0
NF_D[10]
RGB_WD[3]
127
GPIOB3
D3
SD Card Interface Data 2
BT656_D[3]
BI
GPIOB3
BI
RGB_WD[4]
D4
D5
D6
D7
NAND FLASH Interface Data 11
BI
BI
VDD
RGB Interface Data 5
SD_DAT[4]
SD Card Interface Data 4
NF_D[13]
NAND FLASH Interface Data 13
BI
RGB Interface Data 6
SD_DAT[5]
SD card Interface Data 5
NF_D[14]
NAND FLASH Interface Data 14
BI
RGB Interface Data 7
SD_DAT[6]
SD card Interface Data 6
NF_D[15]
NAND FLASH Interface Data 15
BI
SD_DAT[7]
134
RGB Interface Data 4
NAND FLASH Interface Data 12
RGB_WD[8]
133
GPIOB Port 3
NF_D[12]
RGB_WD[7]
132
BT656 Interface Data 3
SD Card Interface Data 3
RGB_WD[6]
131
0
SD_DAT[3]
RGB_WD[5]
130
GPIOB Port 2
RGB Interface Data 3
BI
NF_D[11]
129
BT656 Interface Data 2
NAND FLASH Interface Data 10
SD_DAT[2]
128
GPIOB Port 1
NAND FLASH Interface Data 9
SD_DAT[1]
126
Bt656 Interface Data 1
VDD
RGB Interface Data 8
SD card Interface Data 7
PWRI
VDD
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
135
136
137
NF_D[0]
D8
RGB_WD[10]
D9
NF_D[1]
RGB_WD[11]
D10
RGB_WD[12]
D11
138
139
140
141
142
NF_D[2]
NF_D[4]
RGB_WD[14]
D13
NF_D[5]
RGB_WD[15]
D14
NF_D[6]
RGB_WD[16]
D15
BI
BI
NF_D[3]
RGB_WD[13]
D12
BI
NF_D[7]
RGB_WD[17]
NAND FLASH Data 0
RGB Interface Data 10
NAND FLASH Interface Data 1
RGB Interface Data 11
NAND FLASH Interface Data 2
RGB Interface Data 12
NAND FLASH Interface 3
BI
BI
BI
BI
BI
RGB Interface Data 13
NAND FLASH Data 4
RGB Interface Data 14
NAND FLASH Interface Data 5
RGB Interface WD 15
NAND FLASH Data 6
RGB Interface Data 16
NAND FLASH Interface Data 7
RGB Interface Data 17
143
GND
GND
PWR
GND
144
RTCVDD
RTCVDD
PWRI
RTC Power VDD
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
25.2.2 Pin Assignment
25.3
ATJ2257B
25.3.1 Pin Definition
No.
Pin
No
Pin Name
Function Name
I/O
Type
Driver
Reset
Default
1
A1
LXVDD
LXVDD
PWR
/
POW Pin LXVDD
2
A2
IOVDD
IO_VDD
PWR
/
POW Pin IOVDD
Description
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
3
A3
HOSCI
HOSCI
AI
/
High Oscillator Input
4
A4
PGND
PGND
PWR
/
POWER MOS GND
5
A5
TVRREF
TVRREF
AO
/
6
A6
PAVCC
PAVCC
PWRO
/
Audio PA VCC
7
A7
AGND
AGND
PWR
/
Audio Analog GND
8
A8
AVCC
AVCC
PWRO
/
Audio Analog VCC
9
A9
VMIC
VMIC
AI
/
10
A10
DP
DP
BI
/
11
A11
VBUS
VBUS
I
/
OTG Interface VBUS
12
A12
PAGND
PAGND
PWR
/
Audio PA GND
13
B1
VDD
VDD
PWRI
/
VDD
14
B2
BAT
BAT
PWRI
/
Battery Input
15
B3
HOSCO
HOSCO
AO
/
High Oscillator Output
16
B4
AVDD
AVDD2
PWRO
/
Audio VDD
17
B5
TVCVBS
TVCVBS
AO
/
18
B6
VRDA
VRDA
AO
/
19
B7
VREFI
VREFI
AI
/
20
B8
MICIN
MICIN
AI
/
21
B9
UREF
RREF
AO
/
22
B10
ID
ID
BI
/
23
B11
DM
DM
BI
/
24
B12
UVCC
UVCC
PWR
/
TV reference
Resistance
Microphone Power
Supply
OTG Interface Data
Plus
Video CVBS signal
Output
Audio DAC Voltage
Reference
Voltage Reference
Input
Microphone Input
OTG Interface
Reference Resistance
OTG Interface ID
OTG Interface Data
Minus
OTG Interface UVCC
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
25
C1
VCC
VCC
PWRI
/
VCC
26
C2
DC5V
DC5V
PWRI
/
DC5V Input
I2C1 Interface SDA
I2C1_SDA
/UART2IR_RX
27
C3
I2C1SDA
/UART1_CTSB
Uart2 or IrDA Interface
BI
Rx
2mA
/SPI_MOSI
Uart1 Interface CTS
SPI Interface Master
Output Slave in
28
C4
RESETB
GPIOA7
BI
RESETB
I
/
BI
2mA
KS_OUT[1]
29
C5
KSOUT1
/EJ_DINT
GPIOA13
KS_IN[1]
30
C6
KSIN1
/EJ_TMS
GPIOA Port 7
BI
BI
GPIOA9
BI
2mA
AOUTL
AOUTL
AO
/
32
C8
FMINL
FMINL
AI
/
UART1TX
/I2C2_SCL
BI
2mA
/SPI_MISO
34
C10
/I2C2_SDA
BI
Channel
FM in Left Channel
Selection
I2C2 Interface SCL
GPIOB Port 14
Uart1 Interface RX
BI
/SPDIF_RX
GPIOB15
Audio Output Left
SPDIF Interface TX
UART1_RX
UART1RX
EJTAG Port TMS
SPI Interface Slave
/SPDIF_TX
GPIOB14
Key Scan Input 1
Uart1 Interface TX
UART1_TX
C9
EJTAG Port DINT
GPIOA Port 9
C7
33
Key Scan Output 1
GPIOA Port 13
31
/SPI_SS
System RESET
SPI Interface MISO
2mA
I2C2 Interface SDA
SPDIF Interface RX
BI
GPIOB Port 15
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
35
C11
SDRDQ0
SDRAM_DQ0
BI
8mA
36
C12
SDRDQ1
SDRAM_DQ1
BI
8mA
37
D1
GND
GND
PWR
/
38
D2
VCCOUT
VCCOUT
PWRO
/
39
D3
I2C1SCL
/UART1_RTSB
KS_OUT[0]
40
D4
KSOUT0
/EJ_TDO
GPIOA12
KS_OUT[2]
41
D5
KSOUT2
/EJ_TRSTGPIOB22
42
D6
KSIN2
43
D7
AOUTR
44
D8
45
KSIN[2]
BI
1
GND
Programmed VCC
Output
Tx
2mA
Uart1 Interface RTS
SPI Interface Clock
BI
BI
GPIOA Port 6
2mA
BI
BI
Key Scan Output 0
EJTAG Port TDO
GPIOA Port12
2mA
BI
Key Scan Output 2
EJTAG Port TRST
GPIOB Port 22
BI
2mA
AOUTR
AO
/
FMINR
FMINR
AI
/
D9
SDRDQ15
SDRAM_DQ15
BI
8mA
46
D10
SDRDQ14
SDRAM_DQ14
BI
8mA
47
D11
SDRDQ2
SDRAM_DQ2
BI
8mA
48
D12
SDRDQ3
SDRAM_DQ3
BI
8mA
/EJ_TDI
SDRAM Interface Data
Uart2 or IrDA Interface
/SPI_SCK
GPIOA6
0
I2C1 Interface SCL
I2C1_SCL
/UART2IR_TX
SDRAM Interface Data
Key Scan Input2
EJTAG Port TDI
Audio Output Right
Channel
FM In Right Channel
SDRAM Interface
Data15
SDRAM Data14
SDRAM Interface
Data2
SDRAM Interface
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
Data3
BT656_HSYNC
49
E1
A15
/NOR_A[15]
GPIOB9
BT656_VSYNC
50
E2
A16
/NOR_A[16]
GPIOB10
BT656 Interface
BI
2mA
HSYNC
Nor Flash Address 15
GPIOB Port 9
BI
BT656 Interface
BI
2mA
VSYNC
NOR Flash address16
BI
GPIOB Port 10
BT656 Interface Data
BT656_D[4]
51
E3
A10
/NOR_A[10]
BI
4
4mA
Nor Flash Interface
Address 10
GPIOB4
BT656_PCLK
52
E4
A14
/NOR_A[14]
GPIOB8
KS_IN[0]
53
E5
54
E6
55
E7
56
KSIN0
/EJ_TCK
57
E9
58
E10
BI
GPIOB Port 4
BT656 Interface PCLK
4mA
BI
KEY Scan in 0
2mA
EJTAG Port TCK
GPIOA Port 8
BI
REMCON
REM_CON
AI
/
TEST
TEST
I
/
Remote Control ADC
Input
TEST
FM Module Clock out
SDRAM Interface
SDRAM_A12
O
GPIOA26
BI
SDRDQ13
SDRAM_DQ13
BI
8mA
SDRDQ12
SDRAM_DQ12
BI
8mA
SDRA12
Nor Flash Address 14
GPIOB Port 8
BI
GPIOA8
/CLKOUT
E8
BI
8mA
Address12
GPIOA Port 26
SDRAM Interface
Data13
SDRAM Interface Data
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ATJ2256/ATJ2257/ATJ2257B DATASHEET
12
59
E11
60
E12
SDRDQ4
SDRAM_DQ4
BI
8mA
SDRDQ5
SDRAM_DQ5
BI
8mA
BT656_D[7]
61
F1
A13
/NOR_A[13]
GPIOB7
SDRAM Interface Data
4
SDRAM Interface Data
5
BT656 Interface Data
BI
4mA
BI
7
Nor Flash Address13
GPIOB Port 7
BT656 Interface
BT656_CLKOUT
62
F2
A17
/NOR_A[17]
BI
CLKOUT
8mA
Nor Flash Interface
Address 17
GPIOB11
BT656_D[0]
63
F3
A6
/NOR_A[6]
GPIOB0
BI
GPIOB Port 11
BT656 Interface Data
BI
4mA
BI
0
Nor Flash Address 6
GPIOB Port 0
BT656 Interface Data
BT656_D[3]
64
F4
A9
/NOR_A[9]
BI
3
4mA
Nor Flash Interface
Address 9
GPIOB3
BI
GPIOB Port 3
65
F5
BL_NDR
BL_NDR
AO
/
Back Light NDR
66
F6
VCC
VCC
PWRI
/
VCC
67
F7
VCC
VCC
PWRI
/
VCC
68
F8
SD_VP
SDRAM_VP
PWRI
/
SDRDQ11
SDRAM_DQ11
BI
8mA
69
F9
SDRAM Interface
Power
SDRAM Interface
Data11
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70
71
72
F10
F11
F12
SDRDQ10
SDRAM_DQ10
BI
8mA
SDRDQ6
SDRAM_DQ6
BI
8mA
SDRDQ7
SDRAM_DQ7
BI
8mA
SDRAM Interface
Data10
SDRAM Interface Data
6
SDRAM Interface
Data7
BT656 Interface Data
BT656_D[6]
73
G1
/NOR_A[12]
BI
4mA
A12
BT656_D[5]
G2
A11
Nor Flash Interface
Address 12
GPIOB6
74
6
/NOR_A[11]
GPIOB5
BI
GPIOB Port 6
BT656 Interface Data
BI
4mA
5
Nor Flash A 11
BI
GPIOB Port 5
Bt656 Interface Data
BT656_D[1]
75
G3
A7
/NOR_A[7]
BI
4mA
1
Nor Flash Interface
Address 7
GPIOB1
BI
GPIOB Port 1
BT656 Interface Data
BT656_D[2]
76
G4
A8
/NOR_A[8]
BI
4mA
2
Nor Flash Interface
Address 8
GPIOB2
SIRQ0
77
G5
SIRQ0
/ATA_IRQ
BI
I
GPIOA31
BI
GPIOB Port 2
External IRQ 0
2mA
ATA Interface IRQ
GPIOA Port 31
78
G6
GND
GND
PWR
/
GND
79
G7
GND
GND
PWR
/
GND
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80
G8
GND
GND
PWR
/
81
G9
SDRDQ8
SDRAM_DQ8
BI
8mA
SDRDQ9
SDRAM_DQ9
BI
8mA
SDRAM_WEB
O
GPIOA20
BI
82
83
G10
G11
SDRWEB
GND
SDRAM Interface Data
8
SDRAM Interface Data
9
SDRAM Interface
8mA
Write Enable
GPIOA Port 20
SDRAM Interface
84
G12
SDRDQM0
SDRAM_LDQM
/SDRAM_DQM[0]
LDQM(for 16bits
O
8mA
SDRAM)
SDRAM Interface
DQM0
NAND Flash Data 8
NF_D[8]
Nor Flash Data 0
/NOR_D[0]
85
H1
D0
/RGB_WD[1]
BI
4mA
/ATA_D[0]
RGB Interface Data 1
ATA Interface Data 0
SD Card Interface Data
/SD_DAT[0]
0
NAND Flash Interface
Data 9
NF_D[9]
Nor Flash Interface
/NOR_D[1]
86
H2
D1
/RGB_WD[2]
BI
4mA
/ATA_D[1]
Data 1
RGB Interface Data 2
ATA Interface Data 1
/SD_DAT[1]
SD Card Interface Data
1
NF_D[12]
87
H3
D4
/NOR_D[4]
/RGB_WD[5]
/ATA_D[4]
NAND Flash Interface
BI
4mA
Data 12
Nor Flash Interface
Data 4
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/SD_DAT[4]
RGB Interface Data 5
ATA Interface Data 4
SD Card Interface Data
4
NAND Flash Interface
Data 13
NF_D[13]
Nor Flash Interface
/NOR_D[5]
88
H4
D5
/RGB_WD[6]
BI
4mA
/ATA_D[5]
Data 5
RGB Interface Data 6
ATA Interface Data 5
/SD_DAT[5]
SD card Interface Data
5
89
H5
KSIN3
KS_IN[3]
BI
GPIOA11
BI
2mA
ATA_CS0B/
90
H6
CEB4
NOR_CEB4/
GPIOA Port 11
ATA Interface CS0
O
RGB_CE
GPIOB27
Key scan Input 3
4mA
BI
NOR Flash CE4
RGB Interface CE
GPIOB Port 27
Nor Flash Interface
91
H7
CEB0
NOR_CEB0
/NF_CEB0
O
4mA
CE0
NAND Flash Interface
CE0
DRV_VBUS
/NOR_RDB
92
H8
DRVVBUS
/RGB_RDB
OTG Interface VBUS
O
Nor Flash Interface RD
2mA
ATA Interface RD
/ATA_RDB
93
94
H9
H10
SDRCK
SDRDQM1
GPIOA15
BI
SDRAM_CK
O
16mA
O
8mA
SDRAM_DQM/UDQM
/SDRAM_DQM[1]
RGB Interface RD
GPIOA Port 15
SDRAM Interface
Clock
SDRAM Interface
DQM(for 8bits SDRAM)
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SDRAM Interface
UDQM(for 16bits
SDRAM)
SDRAM Interface
DQM1(for 32bits
SDRAM)
95
96
H11
H12
SDRRASB
SDRCASB
SDRAM_RASB
O
GPIOA18
BI
SDRAM_CASB
O
GPIOA19
BI
8mA
8mA
SDRAM Interface RAS
GPIOA Port 18
SDRAM Interface CAS
GPIOA Port 19
NAND Flash Interface
Data 10
NF_D[10]
Nor Flash Interface
/NOR_D[2]
97
J1
D2
/RGB_WD[3]
BI
4mA
/ATA_D[2]
Data 2
RGB Interface Data 3
ATA Interface Data 2
/SD_DAT[2]
SD Card Interface Data
2
NAND Flash Interface
Data 11
NF_D[11]
Nor Flash Interface
/NOR_D[3]
98
J2
D3
/RGB_WD[4]
BI
4mA
/ATA_D[3]
Data 3
RGB Interface Data 4
ATA Interface Data 3
/SD_DAT[3]
SD Card Interface Data
3
NF_D[14]
99
J3
D6
/NOR_D[6]
/RGB_WD[7]
/ATA_D[6]
NAND Flash Interface
BI
4mA
Data 14
Nor Flash Interface
Data 6
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/SD_DAT[6]
RGB Interface Data 7
ATA Interface Data 6
SD card Interface Data
6
NAND Flash Interface
Data 15
NF_D[15]
Nor Flash Interface
/NOR_D[7]
100
J4
D7
/RGB_WD[8]
BI
4mA
/ATA_D[7]
Data 7
RGB Interface Data 8
ATA Interface Data 7
/SD_DAT[7]
SD card Interface Data
7
SD CARD Interface
SD_CLK
101
J5
CEB6
/CE6
O
CLOCK
16mA
Nor Flash Interface
CE6
GPIOB29
BI
GPIOB Port 29
NAND Flash Interface
CE1
NF_CEB1
102
J6
CEB1
/NOR_CEB1/RGB_CE
O
4mA
/ATA_CS0B
Nor Flash Interface
CE1
RGB Interface CE
ATA Interface CS0
103
J7
SIRQ1
SIRQ1
I
GPIOB31
BI
UART2IR_TX
104
105
J8
J9
UART2TX
SDRA11
/ I2C2_SCL
BI
GPIOB12
BI
SDRAM_A11
O
GPIOA25
BI
2mA
External IRQ 1
GPIOB Port 31
Uart2 or IrDA Port Tx
2mA
I2C2 Interface SCL
GPIOB Port 12
SDRAM Interface
8mA
Address11
GPIOA Port 25
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106
107
108
109
J10
J11
SDRCKE
SDRBA0
J12
SDRCSB
K1
VDD
SDRAM_CKE
O
GPIOA16
BI
SDRAM_BA0
O
SDRAM_CSB
O
GPIOA17
BI
VDD
PWRI
SDRAM Interface
16mA
Clock Enable
GPIOA Port 16
8mA
8mA
SDRAM Interface bank
address0
SDRAM Interface CS
GPIOA Port 17
/
VDD
NAND Flash Interface
CLE
NF_CLE
ATA Interface Address
/ATA_A2
110
K2
A2
/NOR_A[2]
O
4mA
/RGB_RS
2
Nor Flash Interface
address 2
/SD_CMD
RGB Interface RS
SD card Interface CMD
GPIOA2
BI
GPIOA Port 2
NAND Flash Interface
Ready/Busy
NF_RB
/ATA_A1
111
K3
A1
/NOR_A[1]
ATA Interface Address
O
4mA
/RGB_WD[9]
1
Nor Flash Interface
Address 1
RGB Interface Data 9
GPIOA1
BI
GPIOA Port 1
NAND Flash ALE
NF_ALE
112
K4
A0
/ATA_A0
/NOR_A[0]
/RGB_WD[0]
ATA Interface Address
O
4mA
0
Nor Flash Interface
Address 0
RGB Interface Data0
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GPIOA0
BI
GPIOA Port 0
NOR Flash Interface
NOR_CEB3
113
K5
CEB3
/NF_CEB3
O
CE3
4mA
NAND Flash Interface
CE3
GPIOB17
BI
GPIOB Port 17
NAND Flash Interface
NF_CEB2
114
K6
CEB2
/NOR_CEB2
/RGB_CE
CE2
O
4mA
/ATA_CS1B
Nor Flash Interface
CE2
RGB Interface CE
ATA Interface CS1
DRV_VBUS
/NOR_RDB
115
K7
RDB
/RGB_RDB
OTG Interface VBUS
O
2mA
UART2IR_RX
116
117
118
K8
K9
K10
119
K11
120
K12
UART2RX
SDRA8
SDRA9
SDRA10
SDRBA1
/I2C2_SDA
RGB Interface RD
ATA Interface RD
/ATA_RDB
GPIOA15
Nor Flash Interface RD
BI
BI
GPIOB13
BI
SDRAM_A8
O
GPIOA22
BI
SDRAM_A9
O
GPIOA23
BI
SDRAM_A10
O
GPIOA24
BI
SDRAM_BA1
O
GPIOA Port 15
Uart2 or IrDA Port Rx
2mA
I2C2 Interface SDA
GPIOB PORT13
8mA
SDRAM Interface
Address 8
GPIOA Port A 22
8mA
SDRAM Interface
Address 9
GPIOA Port 23
8mA
SDRAM Address 10
GPIOA Port 24
SDRAM Interface
8mA
Bank Address 1
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121
L1
LOSCO
LOSCO
AO
122
L2
RTCVDD
RTCVDD
PWRI
/
/
NF_D[0]
123
L3
D8
/NOR_D[8]
/RGB_WD[10]
Low Oscillator Output
RTC Power VDD
NAND Flash Data 0
BI
4mA
Nor Flash Data 8
RGB Interface Data 10
ATA Interface Data 8
/ATA_D[8]
NAND Flash Interface
NF_D[2]
124
L4
D10
/NOR_D[10]
/RGB_WD[12]
Data 2
BI
4mA
/ATA_D[10]
Nor Flash Interface
Data 10
RGB Interface Data 12
ATA Interface Data 10
125
L5
D12
NF_D[4]
NAND Flash Data 4
/NOR_D[12]
Nor Flash Data 12
/RGB_WD[14]
BI
4mA
/ATA_D[12]
ATA Interface Data 12
/ICE_CK
ICE Port clock
NAND Flash Data 6
NF_D[6]
Nor Flash Interface
/NOR_D[14]
126
L6
D14
RGB Interface Data 14
/RGB_WD[16]
BI
4mA
/ATA_D[14]
Data 14
RGB Interface Data 16
ATA Interface Data 14
/ICE_DI
ICE Port DI
OTG charge pump
DISCHG
/NOR_WRB
127
L7
WRB
/RGB_WRB
Discharge
O
Nor Flash Interface
WR
2mA
/ATA_WRB
RGB Interface WR
ATA Interface WR
128
L8
SD_VP
GPIOA14
BI
SDRAM_VP
PWRI
GPIOA Port 14
/
SDRAM Interface
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Power
129
130
131
132
L9
L10
L11
L12
SDRA6
SDRAM_A6
O
8mA
SDRAM_A7
O
8mA
GPIOA21
BI
SDRA1
SDRAM_A1
O
8mA
SDRA0
SDRAM_A0
O
8mA
/
SDRA7
133
M1
LOSCI
LOSCI
AI
134
M2
GND
GND
PWR
SDRAM Interface
Address 6
SDRAM Interface
Address 7
GPIOA Port 21
SDRAM Interface
Address 1
SDRAM Interface
address 0
Low Oscillator Input
/
GND
NAND Flash Interface
NF_D[1]
135
M3
D9
/NOR_D[9]
/RGB_WD[11]
Data 1
BI
4mA
/ATA_D[9]
Nor Flash Interface
Data 9
RGB Interface Data 11
ATA Interface Data 9
NAND Flash Interface
136
M4
D11
NF_D[3]
3
/NOR_D[11]
Nor Flash Data 11
/RGB_WD[13]
BI
4mA
RGB Interface Data 13
/ATA_D[11]
ATA Interface Data
/ICE_EN
11
ICE Port EN
NAND Flash Interface
NF_D[5]
Data 5
/NOR_D[13]
137
M5
D13
/RGB_WD[15]
/ATA_D[13]
/ICE_RSTB
BI
4mA
Nor Flash Interface
Data 13
RGB Interface WD 15
ATA Interface Data 13
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ICE Port RST
NAND Flash Interface
NF_D[7]
Data 7
/NOR_D[15]
138
M6
D15
/RGB_WD[17]
BI
Nor Flash Port Data 15
4mA
RGB Interface Data 17
/ATA_D[15]
ATA Interface Data 15
/ICE_DO
ICE Port DO
139
M7
VDD
VDD
PWRI
/
VDD
140
M8
GND
GND
PWR
/
GND
141
M9
SDRA4
SDRAM_A4
O
8mA
SDRA5
SDRAM_A5
O
8mA
SDRA3
SDRAM_A3
O
8mA
SDRAM_A2
O
8mA
142
143
144
M10
M11
M12
SDRA2
SDRAM Interface
Address4
SDRAM Interface
Address 5
SDRAM Interface
Address3
SDRAM Interface
Address2
25.3.2 Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
A
LXVDD
IOVDD
HOSCI
PGND
TVRREF
PAVCC
AGND
AVCC
VMIC
DP
VBUS
PAGND
B
VDD
BAT
HOSCO
AVDD
TVCVBS
VRDA
VREFI
MICIN
UREF
IDPIN
DM
UVCC
C
VCC
DC5V
I2C1SDA
RESETB
KSOUT1
KSIN1
AOUTL
FMINL
UART1TX
UART1RX
SDRDQ0
SDRDQ1
D
GND
VCCOUT
I2C1SCL
KSOUT0
KSOUT2
KSIN2
AOUTR
FMINR
SDRDQ15
SDRDQ14
SDRDQ2
SDRDQ3
E
A15
A16
A10
A14
KSIN0
REMCON
TEST
SDRA12
SDRDQ13
SDRDQ12
SDRDQ4
SDRDQ5
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F
A13
A17
A6
A9
BL_NDR
VCC
VCC
SD_VP
SDRDQ11
SDRDQ10
SDRDQ6
SDRDQ7
G
A12
A11
A7
A8
SIRQ0
GND
GND
GND
SDRDQ8
SDRDQ9
SDRWEB
SDRDQM0
H
D0
D1
D4
D5
KSIN3
CEB4
CEB0
DRVVBUS
SDRCK
SDRDQM1
SDRRASB
SDRCASB
J
D2
D3
D6
D7
CEB6
CEB1
SIRQ1
UART2TX
SDRA11
SDRCKE
SDRBA0
SDRCSB
K
VDD
A2
A1
A0
CEB3
CEB2
RDB
UART2RX
SDRA8
SDRA9
SDRA10
SDRBA1
L
LOSCO
RTCVDD
D8
D10
D12
D14
WRB
SD_VP
SDRA6
SDRA7
SDRA1
SDRA0
M
LOSCI
GND
D9
D11
D13
D15
VDD
GND
SDRA4
SDRA5
SDRA3
SDRA2
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26
Package Drawing
26.1
ATJ2256
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26.2
ATJ2257
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26.3
ATJ2257B
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27 Appendix
27.1
Acronym and Abbreviations
ADC: Analog-to-Digital Converter
AHB: Advanced High-Performance Bus
ALE: Address-Locked Enable
APB: Advanced Peripheral Bus
BIST: Built-in Self-Test
CLE: Command-Locked Enable
CMU: Clock Management Unit
CP0: System Control Coprocessor
CRC: Cyclic redundancy Check
CVBS: Composite Video Broadcasting Signal
DAC: Digital-to-Analog Converter
dB: Decibel
DC: Direct Current
DSP: Digital Signal Processing
DVB: Digital Video Broadcasting
EAV: End of Active Video
ECC: Error Correct Code
FIR: Fast Infrared
GPIO: General-Purpose Input/Output
I2C: Inter-Integrated Circuit
IR: Infrared
IrDA: Infrared Data Association
IRQ: Interrupt Request
JPEG: Joint Photographic Experts Group
Li-Ion: Lithium Ion (battery type)
LRADC: Low Resolution ADC
MAC: Multiplier Accumulator Control
MCA: Motion Compensation Accelerator
MIPS: Million Instructions Per Second
MIR: Mid Infrared
MJPEG: Motion JPEG
MMC: Multimedia Card
MMU: Memory Management Unit
MLC: Multi-Level Cell
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MPEG: Motion Picture Expert Group
NTSC: National Television Standards Committee
OLED: Polymer Light-Emitting Diode
PA: Power Amplifier
PAL: Phase Alteration Line
PCM: Pulse Code Modulation
PFM: Pulse Frequency Modulation
PLL: Phase-Locked Loop
PMU: Power Management Unit
PWM: Pulse Width Modulation
RISC: Reduced Instruction Set Computing
RTC: Real-Time Clock
SAV: Start of Active Video
SD: Secure Digital memory card
SIR: Slow Infrared
SMC: State Machine Controller
SLC: Single-Level Cell
SOC: System on a Chip
SPEC: Specification
SPDIF: SONY-Philips Digital Interface Format
SPI: Serial Peripheral Interface
SPRAM: Scratch Pad RAM
SW: Software
THD: Total Harmonic Distortion
TLB: Translation Look-aside Buffer
TS: Transport Stream
UART: Universal Asynchronous Receiver Transmitter
WMA: Windows Media Audio
WMV: Windows Media Video
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Actions Semiconductor Co., Ltd.
Address: Bldg. 15-1, NO.1, HIT Rd., Tangjia, Zhuhai, Guangdong, China
Tel: +86-756-3392353
Fax: +86-756-3392251
Post code: 519085
http://www.actions-semi.com
Business Email: mp-sales@actions-semi.com
Technical Service Email: mp-cs@actions-semi.com
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