OPA1622 SoundPlus™ High-Fidelity, Bipolar-Input, Audio Operational Amplifier 1 Features 3 Description

OPA1622 SoundPlus™ High-Fidelity, Bipolar-Input, Audio Operational Amplifier 1 Features 3 Description
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OPA1622
Burr-Brown Audio
SBOS727A – NOVEMBER 2015 – REVISED NOVEMBER 2015
OPA1622 SoundPlus™ High-Fidelity, Bipolar-Input, Audio Operational Amplifier
1 Features
3 Description
•
•
•
The OPA1622, dual, bipolar-input, SoundPlus™
audio operational amplifier achieves a very low, 2.8nV/√Hz noise density with an ultralow THD+N of
–119.2 dB at 1 kHz, while driving a 32-Ω load at 100mW output power. The OPA1622 offers extremelyhigh ac PSRR and CMRR specifications that
eliminate noise from power supplies, making the
OPA1622 ideal for use in portable-audio applications.
This device also has a high output-drive capability of
+145 mA / –130 mA.
1
•
•
•
•
•
•
•
•
•
High-Fidelity Sound Quality
Ultralow Noise: 2.8 nV/√Hz at 1 kHz
Ultralow Total Harmonic Distortion + Noise:
–119 dB THD+N (142 mW/Ch into 32 Ω/Ch)
Wide Gain Bandwidth Product:
32 MHz (G = +1000)
High Slew Rate: 10 V/μs
High Capacitive-Load Drive Capability: > 600 pF
High Open-Loop Gain: 136 dB (600-Ω Load)
Low Quiescent Current: 2.6 mA per Channel
Low-Power Shutdown Mode With Reduced Pop
and Click Noise: 5 μA per Channel
Short-Circuit Protection
Wide Supply Range: ±2 V to ±18 V
Available in small VSON-10 µPackage
2 Applications
•
•
•
•
•
•
High-Fidelity (HiFi) Headphone Drivers
Professional Audio Equipment
Analog and Digital Mixing Consoles
Audio Test and Measurement
High-End Blu-ray™ Players
High-End Audio and Video (A/V) Receivers
The OPA1622 operates over a very wide supply
range of ±2 V to ±18 V, on only 2.6 mA of supply
current per channel. The OPA1622 op amp is unitygain stable and provides excellent dynamic behavior
over a wide range of load conditions. The OPA1622
includes a shutdown mode, allowing the amplifiers to
be switched from normal operation to a standby
current that is typically less than 5 µA. This shutdown
feature is specifically designed to eliminate click and
pop noise when transitioning into or out of shutdown
mode.
The OPA1622 features a unique internal layout for
lowest crosstalk, and freedom from interactions
between channels, even when overdriven or
overloaded. This device is specified from –40°C to
+125°C.
Device Information(1)
PART NUMBER
OPA1622
PACKAGE
VSON (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the datasheet.
OPA1622 in a High-Fidelity Headphone Driver
Application
FFT: 1 kHz, 32-Ω Load, 50 mW
0
C1 470 pF
R1
R2
499
768
±40
VAC
VDC
+
+
VAC
ROUT
OPA1622
±60
±80
±100
-133.6 dBc (Second Harmonic)
±120
R3
±140
499
Audio DAC
Headphone
Output
Amplitude (dBc)
ROUT
±20
R4
768
C2
470 pF
±160
±180
0
5k
10k
Frequency (Hz)
15k
20k
C005
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA1622
SBOS727A – NOVEMBER 2015 – REVISED NOVEMBER 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: ........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 17
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 22
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
28
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
Changes from Original (November 2015) to Revision A
•
2
Page
Changed from product preview to production data ............................................................................................................... 1
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SBOS727A – NOVEMBER 2015 – REVISED NOVEMBER 2015
5 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
V+
2
GND
3
V±
4
+INB
5
10 ±INA
+
1
+
+INA
±
±
9
OUTA
8
EN
7
OUTB
6
±INB
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
GND
3
—
EN
8
I
Shutdown (logic low), enable (logic high)
+IN A
1
I
Noninverting input, channel A
–IN A
10
I
Inverting input, channel A
+IN B
5
I
Noninverting input, channel B
–IN B
6
I
Inverting input, channel B
OUT A
9
O
Output, channel A
OUT B
7
O
Output, channel B
V+
8
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
Thermal pad
Connect to ground
Exposed thermal die pad on underside; connect thermal die pad to V–. Soldering the thermal
pad improves heat dissipation and provides specified performance.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Supply voltage, VS = (V+) – (V–)
Voltage
Input voltage (Signal Inputs, Enable, Ground)
Current
Input current (all pins except power-supply pins)
±10
(2)
(2)
V
mA
Continuous
–55
125
Junction, TJ
200
Storage, Tstg
(1)
(V+) + 0.5
±0.5
Operating, TA
Temperature
(V–) – 0.5
Input differential voltage
Output short-circuit
UNIT
40
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to VS / 2 (ground in symmetrical dual supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage (V+ – V–)
Specified temperature
NOM
MAX
UNIT
4 (±2)
36 (±18)
V
–40
125
°C
6.4 Thermal Information
OPA1622
THERMAL METRIC (1)
DRC (SON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
47.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
58.1
°C/W
RθJB
Junction-to-board thermal resistance
22.0
°C/W
ψJT
Junction-to-top characterization parameter
0.9
°C/W
ψJB
Junction-to-board characterization parameter
22.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.1
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5
SBOS727A – NOVEMBER 2015 – REVISED NOVEMBER 2015
Electrical Characteristics:
at TA = +25°C, VS = ±2 V to ±18 V, VCM = VOUT = midsupply, and RL = 1 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
THD+N
IMD
Total harmonic distortion +
noise
Intermodulation distortion
G = 1, f = 1 kHz, VOUT = 3.5 VRMS, RL = 2 kΩ,
80-kHz measurement bandwidth
0.000024%
G = 1, f = 1 kHz, VOUT = 3.5 VRMS, RL = 600 Ω,
80-kHz measurement bandwidth
0.000025%
G = 1, f = 1 kHz, POUT = 10 mW, RL = 128 Ω,
80-kHz measurement bandwidth
0.000071%
G = 1, f = 1 kHz, POUT = 10 mW, RL = 32 Ω,
80-kHz measurement bandwidth
0.000149%
G = 1, f = 1 kHz, POUT = 10 mW, RL = 16 Ω,
80-kHz measurement bandwidth
0.000214%
SMPTE/DIN two-tone, 4:1 (60 Hz and 7 kHz),
G = 1, VO = 3 VRMS, RL = 2 kΩ, 90-kHz measurement
bandwidth
0.000018%
–132
dB
–132
dB
–123
dB
–116
dB
–113
dB
–135
dB
0.00005%
CCIF twin-tone (19 kHz and 20 kHz), G = 1,
VO = 3 VRMS, RL = 2 kΩ, 90-kHz measurement bandwidth
–126
dB
FREQUENCY RESPONSE
G = 1000
32
GBW
Gain-bandwidth product
SR
Slew rate
G = –1
10
V/μs
Full-power bandwidth (1)
VO = 1 VP
1.6
MHz
Overload recovery time
G = –10
300
ns
Channel separation (dual)
f = 1 kHz
140
dB
Input voltage noise
f = 20 Hz to 20 kHz
2.1
μVPP
f = 10 Hz
10
G=1
MHz
8
NOISE
Input voltage noise density (2)
en
In
Input current noise density
f = 100 Hz
4
f = 1 kHz
2.8
f = 10 Hz
2.5
f = 1 kHz
0.8
nV/√Hz
pA/√Hz
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift (2)
PSRR
Power-supply rejection ratio
±100
TA = –40°C to +125°C
±500
±600
TA = –40°C to +125°C
μV
0.5
2.5
μV/°C
0.1
3
μV/V
1.2
2.0
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
TA = –40°C to +125°C (2)
2.2
±10
TA = –40°C to +125°C (2)
±50
±80
μA
nA
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
(1)
(2)
(V–) + 1.5
(V–) + 1.5 V ≤ VCM ≤ (V+) – 1 V, TA = –40°C to +125°C
110
(V+) – 1
127
V
dB
Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
Specified by design and characterization.
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Electrical Characteristics: (continued)
at TA = +25°C, VS = ±2 V to ±18 V, VCM = VOUT = midsupply, and RL = 1 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT IMPEDANCE
Differential
Common-mode
60k || 0.8
Ω || pF
500M || 0.9
Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 2 V ≤ VO ≤ (V+) – 2 V, RL = 32 Ω, VS = ± 5 V
114
120
(V–) + 1.5 V ≤ VO ≤ (V+) – 1.5 V, RL = 600 Ω, VS = ± 18 V
120
136
dB
OUTPUT
Positive rail
VO
Voltage output swing from rail
Negative rail
IOUT
Output current
ZO
Open-loop output impedance
ISC
Short-circuit current
CLOAD
Capacitive load drive
No load
800
RL = 600 Ω
900
No load
800
RL = 600 Ω
mV
900
See Figure 38 and Figure 39
VS = ±18 V
mA
See Figure 40
Ω
+145 / –130
mA
See Figure 24
pF
ENABLE PIN
VIH
Logic high threshold
VIL
Logic low threshold
IIH
Input current
0.82
TA = –40°C to +125°C
0.95
0.78
TA = –40°C to +125°C
V
0.65
VEN = 1.8 V
V
μA
1.5
POWER SUPPLY
IQ
Quiescent current
(per channel)
VEN = 2.0 V, IOUT = 0 A
2.6
TA = –40°C to +125°C (2)
VEN = 0 V, IOUT = 0 A
6
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3.3
4.2
5
10
mA
μA
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6.6 Typical Characteristics
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
20
20
18
15
14
Amplifiers (%)
Amplifiers (%)
16
12
10
8
6
10
5
4
2
0
-2
-1.8
-1.6
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
100
75
50
25
0
-25
-50
-75
-100
0
Offset Voltage Drift (µV/ƒC)
Offset Voltage (µV)
C013
C013
9250 channels
50 channels
Figure 1. Input Offset Voltage Histogram
Figure 2. Input Offset Voltage Drift Histogram
300
±60
±62
200
±66
VOS (µV)
100
VOS ( V)
VCM = -16.5 V
±64
0
±68
VCM = 17 V
±70
±72
±100
±74
±76
±200
±78
±80
±300
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
±20
150
0
±10
10
20
VCM (V)
C001
C001
4 typical units
Figure 4. Input Offset Voltage vs Common-Mode Voltage
Figure 3. Input Offset Voltage vs Temperature
10
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9ROWDJH 1RLVH 6SHFWUDO 'HQVLW\ Q9 ¥+]
100
10
+31
-31
1
1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
1
0.1
1
Figure 5. Input Voltage Noise Spectral Density vs Frequency
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
C307
100M
C306
Figure 6. Input Current Noise Spectral Density vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
50 nV/div
9ROWDJH 1RLVH 6SHFWUDO 'HQVLW\ Q9 ¥+]
1000
Time (2 s/div)
Source Resistor Noise Contribution
100
10
Total Noise
1
Voltage Noise Contribution
Current Noise Contribution
0.1
10
100
1k
Figure 7. 0.1-Hz to 10-Hz Noise
C302
225
120
180
100
12
10
8
6
VS = ±5V
80
40
90
20
4
VS = ±2V
2
135
60
0
0
±20
10k
Phase (º)
VS = ±15V
14
Gain (dB)
Output Amplitude (VP)
1M
140
16
100k
1M
10M
Frequency (Hz)
1
10
100
1k
10k
100k
1M
45
10M 100M
Frequency (Hz)
C303
Figure 9. Maximum Output Voltage vs Frequency
C005
Figure 10. Open-Loop Gain and Phase vs Frequency
5.0
5.0
4.0
4.0
VS = ±2 V
3.0
3.0
2.0
2.0
AOL (µV/V)
AOL (µV/V)
100k
Figure 8. Voltage Noise vs Source Resistance
18
1.0
0.0
VS = ±18 V
±1.0
VS = ±2 V
1.0
0.0
VS = ±18 V
±1.0
±2.0
±2.0
±3.0
±3.0
±4.0
±4.0
±5.0
±5.0
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
600-Ω load
150
C001
2-kΩ load
Figure 11. Open-Loop Gain vs Temperature
8
10k
Source Resistance ( )
C017
Figure 12. Open-Loop Gain vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
40
Total Harmonic Distortion + Noise (%)
Gain (dB)
20
0
-20
0.01
-80
G = -1, 600- Load
G = -1, 2k- Load
G = -1, 10k- Load
G = +1, 600- Load
G = +1, 2k- Load
G = +1, 10k- Load
0.001
-100
-120
0.0001
-140
20k
0.00001
100
1k
10k
100k
1M
10M
Frequency (Hz)
20
200
2k
Frequency (Hz)
C004
Total Harmonic Distortion + Noise (dB)
G = +10
G = -1
G = +1
C004
3.5 VRMS, 80-kHz measurement bandwidth
0.01
-80
0.001
-100
0.0001
-120
-140
20k
0.00001
20
200
2k
Frequency (Hz)
Total Harmonic Distortion + Noise (%)
-60
G = -1, 128- Load
G = -1, 32- Load
G = -1, 16- Load
G = +1, 128- Load
G = +1, 32- Load
G = +1, 16- Load
0.01
0.0001
-140
1
10
Output Amplitude (VRMS)
10
Output Amplitude (VRMS)
0.1
Intermodulation Distortion (%)
Total Harmonic Distortion + Noise (%)
-120
128- Load
32- Load
16- Load
1
C004
-80
0.01
SMPTE
-100
0.001
-120
0.0001
CCIF
0.00001
0.001
-140
0.01
0.1
1
10
Output Amplitude (VRMS)
C004
1 kHz, 80-kHz measurement bandwidth
Figure 17. THD+N Ratio vs Output Amplitude
-60
2k- Load
32- Load
Intermodulation Distortion (dB)
Noninverting
Total Harmonic Distortion + Noise (dB)
-100
0.0001
-140
0.1
Figure 16. THD+N Ratio vs Output Amplitude
-80
0.001
0.1
2k- Load
600- Load
1 kHz, 80-kHz measurement bandwidth
-60
Inverting
-120
Noninverting
0.00001
0.01
Figure 15. THD+N Ratio vs Frequency
0.00001
0.01
-100
C004
0.1
-80
Inverting
0.001
10 mW, 80-kHz measurement bandwidth
0.01
-60
0.1
Total Harmonic Distortion + Noise (dB)
0.1
Figure 14. THD+N Ratio vs Frequency
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
Figure 13. Closed-Loop Gain vs Frequency
C004
90-kHz measurement bandwidth
Figure 18. Intermodulation Distortion vs Output Amplitude
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
160
-80
Crosstalk (dB)
-100
Power Supply Rejection Ratio (dB)
No Load
32- Load
600- Load
-120
-140
120
80
60
40
20
0
100
1k
10k
100k
1M
10M
Frequency (Hz)
1
100
1k
10k
100k
1M
Frequency (Hz)
Figure 19. Channel Separation vs Frequency
10M
C115
Figure 20. PSRR vs Frequency (Referred to Input)
140
Common-mode Rejection Ratio (dB)
Power-Supply Rejection Ratio (µV/V)
10
C004
5
4
3
2
1
0
-1
-2
-3
-4
120
100
-5
80
60
40
20
0
±75
±50
0
±25
25
50
75
100
125
Temperature (ƒC)
150
1
10
100
1k
10k
100k
1M
Frequency (Hz)
C001
Figure 21. PSRR vs Temperature
10M
C004
Figure 22. CMRR vs Frequency (Referred to Input)
90
1
0.8
” 9CM ” 9
VS = ±2 V, (V±)
±1V
80
0.6
G = +1
70
0.4
Phase Margin (º)
Common-Mode Rejection Ratio (µV/V)
PSRR-
100
-160
0.2
0
” 9CM ” 9
VS = ±18 V, (V±)
-0.2
± 1V
-0.4
60
G = -1
50
40
30
20
-0.6
10
-0.8
0
-1
±75
±50
±25
0
25
50
75
100
Temperature (ƒC)
125
150
0
200
400
600
800
Capacitive Load (pF)
C001
Figure 23. CMRR vs Temperature
10
PSRR+
140
1000
C308
Figure 24. Phase Margin vs Capacitive Load
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Typical Characteristics (continued)
2 V/div
2 mV/div
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
Time (2.5 s/div)
Time (2.5 s/div)
C017
C017
G = 1, 10 mV
G = 1, 10 V
Figure 25. Small-Signal Step Response
Figure 26. Large-Signal Step Response
VOUT
5 V/div
5 V/div
VIN
VIN
VOUT
Time (200 ns/div)
Time (200 ns/div)
C017
C017
G = –10
G = –10
Figure 27. Negative Overload Recovery
Figure 28. Positive Overload Recovery
1.5
5 V/div
Input Bias Current ( A)
1.4
VOUT
VIN
1.3
1.2
1.1
1
IBIB+
0.9
Time (500 ms/div)
±50
C017
Figure 29. No Phase Reversal
±25
0
25
50
75
100
Temperature (ºC)
125
C304
Figure 30. IB vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
1.5
Input Bias Current ( A)
Input Offset Current (nA)
5
4
3
2
1.4
1.3
1.2
1.1
1
1
±50
0
±25
25
50
75
100
125
Temperature (ºC)
-20
-10
0
10
20
Common-Mode Voltage (V)
C305
C001
VS = ±18 V
Figure 31. IOS vs Temperature
Figure 32. IB vs Common-Mode Voltage
5
1.3
4
1.25
3.5
IQ (mA)
Input Bias Current ( A)
4.5
1.2
VS = ±18 V
3
VS = ±2 V
2.5
2
1.5
1.15
1
0.5
0
1.1
-1.5
-1
-0.5
0
0.5
1
±75
1.5
Common-Mode Voltage (V)
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C002
C001
VS = ±2 V
Figure 34. Quiescent Current vs Temperature
Figure 33. IB vs Common-Mode Voltage
3
5
2.5
4
125ºC
85ºC
IQ (mA)
IQ (mA)
2
1.5
3
2
-40ºC
1
1
0.5
0
0
0
2
4
6
8
10
12
14
16
18
Supply Voltage (V)
20
0.5
1
1.5
Enable Voltage (V)
C001
Figure 35. Quiescent Current vs Supply Voltage
12
25ºC
2
C002
Figure 36. Quiescent Current vs Enable Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
18
200
16
180
14
ISC, Source
160
12
VO (V)
ISC (mA)
140
120
8
6
ISC, Sink
100
10
125°C
25°C
4
80
±40°C
0
60
±75
±50
0
±25
25
50
75
100
125
0
150
Temperature (ƒC)
20
40
60
80
100 120 140 160 180 200
IO (mA)
C001
C001
Figure 38. Positive Output Voltage vs Output Current
Figure 37. Short-Circuit Current vs Temperature
0
100
-2
125°C
25°C
-4
85°C
-6
±40°C
-8
ZO ( )
VO (V)
85°C
2
-10
10
-12
-14
-16
-18
1
0
20
40
60
80
100 120 140 160 180 200
IO (mA)
1
Figure 39. Negative Output Voltage vs Output Current
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
C001
100M
C001
Figure 40. Open-Loop Output Impedance vs Frequency
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7 Detailed Description
7.1 Overview
The OPA1622, dual, bipolar-input, audio operational amplifier uses a unique internal topology to deliver high
output current with extremely low distortion while consuming minimal supply current. A single gain stage
architecture, combining a high-gain transconductance input stage and a unity gain output stage, allows the
OPA1622 to achieve an open-loop gain of 136 dB, even with 600-Ω loads.
The output stage of the OPA1622 is designed specifically to source and sink large amounts of current without
degrading amplifier linearity. High-order distortion harmonics, produced by output stage crossover distortion, are
greatly reduced with this design. The OPA1622 output stage also provides exceptionally low open-loop output
impedance that improves stability with capacitive loads and is protected against short-circuit events.
A separate enable circuit maintains control of the input and output stage when the amplifier is placed into its
shutdown mode and limits transients at the amplifier output when transitioning to and from this state. The enable
circuit features logic levels referenced to the amplifier ground pin. This configuration simplifies the interface
between the amplifier and the ground-referenced GPIO pins of microcontrollers. The addition of a ground pin to
the amplifier provides several additional benefits. For example, the compensation capacitor between the input
and output stages of the OPA1622 is referenced to the ground pin, greatly improving PSRR.
7.2 Functional Block Diagram
Short Circuit Current Limit
±
+
High-Gain Input Stage
+IN
+
±IN
±
OUT
High-Current Output
Stage
Compensation
Capacitor
GND
±
EN
+
Enable Circuitry
Figure 41. OPA1622 Simplified Schematic
7.3 Feature Description
7.3.1 Power Dissipation
The OPA1622 is capable of high output current with power-supply voltages up to ±18 V. Internal power
dissipation increases when operating at high supply voltages. The power dissipated in the op amp (POPA) is
calculated using Equation 1:
V
POPA
V VOUT u IOUT
V VOUT u OUT
RL
(1)
14
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Feature Description (continued)
In order to calculate the worst-case power dissipation in the op amp, the ac and dc cases must be considered
separately.
In the case of constant output current (dc) to a resistive load, the maximum power dissipation in the op amp
occurs when the output voltage is half the positive supply voltage. This calculation assumes that the op amp is
sourcing current from the positive supply to a grounded load. If the op amp sinks current from a grounded load,
modify Equation 2 to include the negative supply voltage instead of the positive.
POPA(MAX _ DC)
§V ·
POPA ¨
¸
© 2 ¹
V2
4RL
(2)
The maximum power dissipation in the op amp for a sinusoidal output current (ac) to a resistive load occurs
when the peak output voltage is 2/π times the supply voltage, given symmetrical supply voltages:
POPA(MAX _ AC)
§ 2V ·
POPA ¨
¸
© S ¹
2˜V
2
S2 ˜ RL
(3)
The dominant pathway for the OPA1622 to dissipate heat is through the package thermal pad and pins to the
PCB. Copper leadframe construction used in the OPA1622 improves heat dissipation compared to conventional
materials. PCB layout greatly affects thermal performance. Connect the OPA1622 package thermal pad to a
copper pour at the most negative supply potential. This copper pour can be connected to a larger copper plane
within the PCB using vias to improve power dissipation. Figure 42 shows an analogous thermal circuit that can
be used for approximating the junction temperature of the OPA1622. The power dissipated in the OPA1622 is
represented by current source PD; the ambient temperature is represented by voltage source 25ºC; and the
junction-to-board and board-to-ambient thermal resistances are represented by resistors θJB and θBA,
respectively. The board-to-ambient thermal resistance is unique to every application. The sum of θJB and θBA is
the junction-to-ambient thermal resistance of the system. The value for junction-to-ambient thermal resistance
reported in the Thermal Information table is determined using the JEDEC standard test PCB. The voltages in the
analogous thermal circuit at the points TJ and TPCB represent the OPA1622 junction and PCB temperatures,
respectively.
TJ
JB (22.0ºC/W)
TPCB
BA
PD
25ºC
Figure 42. Approximate Thermal System Model of the OPA1622 Soldered to a PCB.
7.3.2 Thermal Shutdown
If the junction temperature of the OPA1622 exceeds 175ºC, a thermal shutdown circuit disables the amplifier in
order to protect the device from damage. The amplifier is automatically re-enabled after the junction temperature
falls below approximately 160ºC. If the condition that caused excessive power dissipation has not been removed,
the amplifier oscillates between a shutdown and enabled state until the output fault is corrected.
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Feature Description (continued)
7.3.3 Enable Pin
The enable pin (EN) of the OPA1622 is used to toggle the amplifier enabled and disabled states. The logic levels
defining these two states are: VEN ≤ 0.78 V (shutdown mode), and VEN ≥ 0.82 V (enabled). These threshold
levels are referenced to the device ground pin. The enable pin can be driven by a GPIO pin from the system
controller, discrete logic gates, or can be connected directly to the V+ supply. Do not leave the enable pin
floating because the amplifier is prevented from being enabled. Likewise, do not place GPIO pins used to control
the enable pin in a high-impedance state because this placement also prevents the amplifier from being enabled.
A small current flows into the enable pin when a voltage is applied. Using the simplified internal schematic shown
in Figure 43, use Equation 4 to estimate the enable pin current:
VEN 0.7 V
IEN
700 k
(4)
As illustrated in Figure 43, the enable pin is protected by diodes to the amplifier power supplies. Do not connect
the enable pin to voltages outside the limits defined in the Specifications section.
To
Amplifier
VCC
500 k
EN
VEE
VCC
200 k
GND
VEE
Figure 43. Enable Pin Simplified Internal Schematic
7.3.4 Ground Pin
The inclusion of a ground pin in the OPA1622 architecture allows the internal enable circuitry to be referenced to
the system ground, eliminating the need for level shifting circuitry in many applications. The internal amplifier
compensation capacitors are also referenced to this pin, greatly increasing the ac PSRR. For highest
performance, connect the ground pin to a low-impedance reference point with minimal noise present. As shown
in Figure 43, the ground pin is protected by ESD diodes to the amplifier power supplies. Do not connect the
ground pin to voltages outside the limits defined in Specifications.
7.3.5 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 44 shows the ESD circuits contained in the OPA1622. The ESD protection circuitry involves
several current-steering diodes connected from the input and output pins and routed back to the internal powersupply lines, where they meet at an absorption device internal to the operational amplifier. This protection
circuitry is intended to remain inactive during normal circuit operation.
16
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Feature Description (continued)
V+
Power Supply
ESD Cell
EN
+IN
+
±
± IN
OUT
GND
V±
Figure 44. Equivalent Internal ESD Circuitry
7.3.6 Input Protection
The input pins of the OPA1622 are protected from excessive differential voltage with back-to-back diodes, as
Figure 45 shows. In most circuit applications, the input protection circuitry has no consequence. However, in lowgain or G = +1 circuits, fast-ramping input signals can forward bias these diodes because the output of the
amplifier cannot respond quickly enough to the input ramp. If the input signal is fast enough to create this
forward-bias condition, the input signal current must be limited to 10 mA or less. If the input signal current is not
inherently limited, use an input series resistor (RI) or a feedback resistor (RF) to limit the signal input current. This
input series resistor degrades the low-noise performance of the OPA1622 and is examined in the Noise
Performance section. Figure 45 shows an example configuration when both current-limiting input and feedback
resistors are used.
RF
–
Device
RI
Input
Output
+
Figure 45. Pulsed Operation
7.4 Device Functional Modes
The OPA1622 has two operating modes determined by the voltage between the enable and ground pins: a
shutdown mode (VEN ≤ 0.78V) and an enabled mode (VEN ≥ 0.82V). The measured datasheet performance
parameters specified in the Typical Characteristics and Specifications sections are given with the amplifier in the
enabled mode, unless otherwise noted.
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Device Functional Modes (continued)
7.4.1 Shutdown Mode
When the enable pin voltage is below the logic low threshold, the OPA1622 enters a shutdown mode with
minimal power consumption. In this state the output transistors of the amplifier are not powered on. However, do
not consider the amplifier output to be high-impedance. Applying signals to the output of the OPA1622 while the
device is in the shutdown mode may parasitically power the output stage, causing the OPA1622 output to draw
current.
The OPA1622 enable circuitry limits transients at the output when transitioning into or out of shutdown mode.
However, small output transients do still accompany this transition, as illustrated in Figure 46 and Figure 47. Note
that in both figures the time scale is 1 µs per division, indicating that the output transients are extremely brief in
nature, and therefore not likely to be audible in headphone applications.
Enable (2 V/div)
Voltage
Voltage
Enable (2 V/div)
Output (20 mV/div)
Output (20 mV/div)
Time (1 s/div)
Time (1 s/div)
C001
C002
Figure 46. OPA1622 Output Voltage When Enable Pin
Transitions High (32-Ω Load Connected)
Figure 47. OPA1622 Output Voltage When Enable Pin
Transitions Low (32-Ω Load Connected)
7.4.2 Output Transients During Power Up and Power Down
To minimize the possibility of output transients that might produce an audible click or pop, ramp the supply
voltages for the OPA1622 symmetrically to their nominal values. Asymmetrical supply ramping can cause output
transients during power up that may be audible in headphone applications. If possible, hold the enable pin low
while the power supplies are ramping up or down. If the enable pin is not being independently controlled (for
example, by a GPIO pin), use a voltage divider to hold the enable pin voltage below the logic-high threshold until
the power supplies reach the specified minimum voltage, as shown in Figure 48.
VCC
22.1 k
To enable
pin on IC
10.7 k
Figure 48. Voltage Divider Used to Hold Enable Low at Power Up or Power Down.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The low noise and distortion of the OPA1622 make it well suited for a variety of applications in professional and
consumer audio products. However, these same performance metrics also make the OPA1622 useful for
industrial, test-and-measurement, and data-acquisition applications. The example shown here is only one
possible application where the OPA1622 provides exceptional performance.
8.1.1 Noise Performance
Figure 49 shows the total circuit noise for varying source impedances with the op amp in a unity-gain
configuration (no feedback resistor network, and therefore no additional noise contributions).
The OPA1622 is shown with total circuit noise calculated. The op amp contributes both a voltage noise
component and a current noise component. The voltage noise is commonly modeled as a time-varying
component of the offset voltage. The current noise is modeled as the time-varying component of the input bias
current, and reacts with the source resistance to create a voltage component of noise. Therefore, the lowest
noise op amp for a given application depends on the source impedance. For low source impedance, current
noise is negligible, and voltage noise generally dominates. The low voltage and current noise of the OPA1622 op
amp make it a excellent choice for use in applications where the source impedance is less than 10 kΩ.
8.1.1.1 Noise Calculations
The equations in Figure 50 show the calculation of the total circuit noise using these parameters:
• en = voltage noise
• In = current noise
• RS = source impedance
• k = Boltzmann’s constant = 1.38 × 10–23 J/K
• T = temperature in kelvins (K)
8.1.1.2 Application Curve
9ROWDJH 1RLVH 6SHFWUDO 'HQVLW\ Q9 ¥+]
1000
Source Resistor Noise Contribution
100
10
Total Noise
1
Voltage Noise Contribution
Current Noise Contribution
0.1
10
100
1k
10k
Source Resistance ( )
100k
1M
C302
Figure 49. Noise Performance of the OPA1622 in a Unity-Gain Buffer Configuration
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Application Information (continued)
8.1.1.3 Basic Noise Calculations
Designing low-noise op amp circuits requires careful consideration of a variety of possible noise contributors,
such as noise from the signal source, noise generated in the op amp, and noise from the feedback network
resistors. The total noise of the circuit is the root sum squared combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. Figure 49 plots this function. The source impedance is usually fixed; consequently, select the op amp
and the feedback resistors to minimize the respective contributions to the total noise.
Figure 50 shows both inverting and noninverting op amp circuit configurations with gain. In circuit configurations
with gain, the feedback network resistors also contribute noise.
The current noise of the op amp reacts with the feedback resistors to create additional noise components.
Choose feedback resistor values that make these noise sources negligible. The equations for total noise are
shown for both configurations.
Noise in Noninverting Gain Configuration
Noise at the output:
R2
2
EO
2
R1
EO
é R ù
R ù
2
2é
= ê1 + 2 ú en2 + e12 + e22 + (in R2 ) + eS2 + (in RS ) ê1 + 2 ú
ë R1 û
ë R1 û
2
where
é R ù
· eS = 4kTRS ´ ê1 + 2 ú = thermal noise of RS
ë R1 û
RS
éR ù
· e1 = 4kTR1 ´ ê 2 ú = thermal noise of R1
ë R1 û
VS
· e2 = 4kTR2 = thermal noise of R2
Noise in Inverting Gain Configuration
Noise at the output:
R2
2
é
R2 ù
2
2
2
2
2
EO2 = ê1 +
ú en + e1 + e2 + (in R2 ) + eS
+
R
R
1
Sû
ë
R1
EO
RS
where
é R2 ù
· eS = 4kTRS ´ ê
ú = thermal noise of RS
ë R1 + RS û
VS
é R2 ù
· e1 = 4kTR1 ´ ê
ú = thermal noise of R1
ë R1 + RS û
· e2 = 4kTR2 = thermal noise of R2
For the OPA1622 at 1 kHz, en = 2.8 nV/√Hz and in = 800 fA/√Hz.
Figure 50. Noise Calculation in Gain Configurations
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Application Information (continued)
8.1.2 Total Harmonic Distortion Measurements
The distortion produced by OPA1622 is below the measurement limit of many commercially-available distortion
analyzers. However, a special test circuit, as shown in Figure 51, can be used to extend the measurement
capabilities.
R1
Gain(Signal)
1
R2
R1
R2
R3
±
Device
Under Test
+
Gain(Distortion)
R2
1
R1 || R3
Generator
Output
Analyzer
Input
Audio
Analyzer
Load
Figure 51. Distortion Test Circuit
Consider op amp distortion an internal error source that is referred to the input. Figure 51 shows a circuit that
causes the op amp distortion to be 101 times (approximately 40 dB) greater than that normally produced by the
op amp. The addition of R3 to the otherwise standard noninverting amplifier configuration alters the feedback
factor or noise gain of the circuit. The closed-loop gain is unchanged, but the feedback available for error
correction is reduced by a factor of 101, thus extending the resolution by 101. Note that the input signal and load
applied to the op amp are the same as with conventional feedback without R3. Keep the value of R3 small to
minimize its effect on the distortion measurements.
Verify the validity of this technique by duplicating measurements at high gain or high frequency where the
distortion is within the measurement capability of the test equipment.
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8.2 Typical Application
The low distortion and high output-current capabilities of the OPA1622 make this device an excellent choice for
headphone-amplifier applications in portable or studio applications. These applications typically employ an audio
digital-to-analog converter (DAC) and a separate headphone amplifier circuit connected to the DAC output. Highperformance audio DACs may have an output signal that is either a varying current or voltage. Voltage output
configurations require less external circuitry, and therefore have advantages in cost, power consumption, and
solution size. However, these configurations may offer slightly lower performance than current output
configurations. Differential outputs are standard on both types of DACs. Differential outputs double the output
signal levels that can be delivered on a single, low-voltage supply, and also allow for even-harmonics common to
both outputs to be cancelled by external circuitry. A simplified representation of a voltage-output audio DAC is
shown in Figure 52. Two ac voltage sources (VAC) deliver the output signal to the complementary outputs
through their associated output impedances (ROUT). Both output signals have a dc component as well,
represented by dc voltage source VDC. The headphone amplifier circuit connected to the output of an audio DAC
must convert the differential output into a single-ended signal and be capable of producing signals of sufficient
amplitude at the headphones to achieve reasonable listening levels.
C1 470 pF
ROUT
R1
R2
499
768
VAC
+
VDC
+
Headphone
Output
OPA1622
VAC
R3
ROUT
499
R4
768
Audio DAC
C2
470 pF
Figure 52. OPA1622 Used as a Headphone Amplifier for a Voltage-Output Audio DAC
8.2.1 Design Requirements
•
•
•
•
±5-V power supplies
150-mW output power (32-Ω load)
< –115-dB THD+N at maximum output (32-Ω load)
< 0.01-dB magnitude deviation (20 Hz to 20 kHz)
8.2.2 Detailed Design Procedure
Figure 52 shows a schematic of a headphone amplifier circuit for voltage output DACs. An op amp is configured
as a difference amplifier that converts the differential output voltage to single-ended. The values of the resistors
in the difference amplifier circuit are determined by the specifications of the DAC, such as output voltage and
output impedance, as well as the maximum output voltage desired at the headphone output. The op amp chosen
must be capable of delivering the necessary current to the headphones and remain stable into typical headphone
loads that may have capacitances as high as 400 pF. The following design process uses a hypothetical DAC
with common values of output voltage and impedance for the design process. The specifications of the DAC are
shown in Table 1:
Table 1. Audio DAC Specifications Used for the Design Process
22
PARAMETER
VALUE
Maximum differential output voltage
2 VRMS
Output impedance (ROUT)
200 Ω
Output dc offset
1.65 V
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The gain of the difference amplifier in Figure 52 is determined by the resistor values, and includes the output
impedance of the DAC. For R2 = R4 and R1 = R3, the output voltage of the headphone amplifier circuit is shown
in Equation 5:
R2
VOUT VDAC
R1 ROUT
(5)
The output voltage required for headphones depends on the headphone impedance, as well as the headphone
efficiency (η), a measure of the sound pressure level (SPL, measured in dB) for a certain input power level
(typically given at 1 mW). The headphone SPL at other power levels is calculated using Equation 6:
§ P
·
SPL(dB) K 10log ¨ IN ¸
© 1 mW ¹
where
•
•
η = efficiency
PIN = input power to the headphones
(6)
Figure 53 shows the input power required to produce certain SPLs for different headphone efficiencies. Typically,
over-the-ear style headphones have lower efficiencies than in-ear types with 95 dB/mW being a common value.
150
Sound Pressure Level (SPL, dB)
140
130
120
110
100
90-dB/mW
90
95-dB/mW
100-dB/mW
80
105-dB/mW
70
110-dB/mW
115-dB/mW
60
0.01
0.1
1
10
100
1000
Input Power (mW)
C001
Figure 53. Sound Pressure Level vs Input Power for Headphones of Various Efficiencies
In-ear headphones may have efficiencies of 115 dB/mW or greater, and therefore have much lower power
requirements. The output power goal for this design is 150 mW; sufficient power to produce extremely loud
sound pressure levels in a wide range of headphones. A 32-Ω headphone impedance is used for this
requirement because 32 Ω is a very common value in headphones for portable applications. Equation 7 shows
the voltage required for 32-Ω headphones:
VO
PuR
150 mW u 32
9RMS
(7)
A tradeoff exists when selecting resistor values for this design. First, high resistor values contribute additional
noise to the circuit, degrading the audio performance. However, extremely low resistor values draw excessive
current from the DAC, increasing distortion. A value of 499 Ω is used for resistors R1 and R3 as a reasonable
compromise between these two considerations. Resistor R2 and R4 can then be calculated as shown in
Equation 8:
R2
R2
VOUT VDAC
o 1.095
o R2 765.4 o
R1 ROUT
499
(8)
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In order to accommodate higher impedance headphones, increase the gain of the circuit to produce greater
output voltages. However, increasing the gain also increases the noise of the circuit and limits the dynamic range
of the circuit into lower impedance headphones. For this reason, some designers choose to select the
headphone amplifier gain by using a switch.
Capacitors C1 and C2 limit the bandwidth of the circuit to prevent the unnecessary amplification of interfering
signals. The maximum value of these capacitors is determined by the limitations on frequency response
magnitude deviation detailed in the Design Requirements section. C1 and C2 combine with resistors R2 and R4 to
form a pole, as shown in Equation 9:
1
fP
2S(R2 ,R 4 )(C1,C2 )
(9)
Calculate the minimum pole frequency allowable to meet the magnitude deviation requirements using
Equation 10:
f
20 kHz
t
t 416.6 kHz
fP t
2
2
§1·
§ 1 ·
¨G¸ 1
¨ 0.999 ¸ 1
© ¹
©
¹
where
•
G represents the gain in decimal for a –0.01-dB deviation at 20 kHz.
(10)
Use Equation 11 to calculate the upper limit for the value of C1 and C2 in order to meet the goal for minimal
magnitude deviation at 20 kHz.
1
1
C1,C2 d
d
d 497 pF o 470 pF
2S(R2 ,R4 )FP 2S(768
N+]
(11)
8.2.3 Application Curves
The circuit described in Figure 52 is constructed using 0.1% tolerance thin-film resistors (0603 package) and
surface-mount film capacitors. The performance of the circuit is measured using a high-performance audio
analyzer and is displayed in Figure 54 through Figure 59. The maximum output power for three common
headphone impedances is shown in Table 2
Table 2. Maximum Output Power and THD+N Before Clipping for Common Headphone Impedances
LOAD IMPEDANCE
(Ω)
MAXIMUM OUTPUT POWER BEFORE CLIPPING
(mW)
THD+N AT MAXIMUM OUTPUT POWER
(dB)
16
95
–114.2
32
150
–118.7
600
11.3
–119.4
The maximum output power delivered to low impedance headphone loads (16 Ω and 32 Ω) is limited by the
output current capabilities of the amplifier. For the 600-Ω case, the maximum power delivered is limited by the
output voltage capability of the amplifier and depends greatly on the power-supply voltages used. Figure 55
shows the maximum output voltage achievable for each load before the onset of clipping (±5-V supplies),
indicated by a sharp increase in distortion.
As more current is delivered by the output transistors of an amplifier, additional distortion is produced. At low
frequencies, this distortion is corrected by the feedback loop of the amplifier. However, as the loop gain of the
amplifier begins to decline at high frequencies, the overall distortion begins to climb. The unique output stage
design of the OPA1622 greatly reduces the additional distortion at high frequency when delivering large currents,
as shown in Figure 56. High-ordered harmonics (above the 2nd and 3rd) are also kept to a minimal level at high
output powers, as shown in Figure 57 through Figure 59.
24
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OPA1622
SBOS727A – NOVEMBER 2015 – REVISED NOVEMBER 2015
Total Harmonic Distortion + Noise (%)
3
Gain (dB)
2.5
2
1.5
100
1k
-60
0.01
-80
0.001
-100
0.0001
16-
Load
32-
Load
600-
10k
Frequency (Hz)
-120
Load
-140
0.00001
0.01
1
10
0.1
0.1
1
Output Voltage (VRMS)
C001
Total Harmonic Distortion +Noise (dB)
www.ti.com
C002
22.4-kHz measurement bandwidth
Figure 54. Headphone Amplifier Transfer Function
60032-
Load
Load
Load
-100
0.001
-120
0.0001
10
100
1k
±20
±40
Amplitude (dBc)
16-
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
0
-80
0.01
Figure 55. THD+N vs Output Voltage for Headphone Loads
±60
±80
±100
±140
±160
±180
10k
Frequency (Hz)
-134 dBc (Second Harmonic)
±120
0
15k
20k
C004
1 kHz, 32-Ω load, 10 mW
Figure 56. THD+N vs Frequency for Headphone Loads
Figure 57. Output Spectrum
0
0
±20
±20
±40
±40
Amplitude (dBc)
Amplitude (dBc)
10k
Frequency (Hz)
90-kHz measurement bandwidth, 1-VRMS output
±60
±80
±100
5k
C003
-133.6 dBc (Second Harmonic)
±120
±60
±80
±120
±140
±140
±160
±160
±180
-126 dBc (Third Harmonic)
±100
±180
0
5k
10k
15k
Frequency (Hz)
20k
0
C005
1 kHz, 32-Ω load, 50 mW
5k
10k
15k
Frequency (Hz)
20k
C006
1 kHz, 32-Ω load, 150 mW
Figure 58. Output Spectrum
Figure 59. Output Spectrum
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SBOS727A – NOVEMBER 2015 – REVISED NOVEMBER 2015
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9 Power Supply Recommendations
The OPA1622 op amp operates from ±2-V to ±18-V supplies, while maintaining excellent performance. However,
some applications do not require equal positive and negative output voltage swing. With the OPA1622, powersupply voltages do not need to be equal. For example, the positive supply could be set to +25 V with the
negative supply at –5 V.
In all cases, the common-mode voltage must be maintained within the specified range. Key parameters are
specified over the temperature range of TA = –40°C to +125°C. Parameters that vary with operating voltage or
temperature are shown in the Typical Characteristics.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply
applications. The bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry, because noise can propagate into analog circuitry through the power
pins of the circuit as a whole and the op amp specifically.
• Connect the IC ground pin to a low-impedance, low-noise, system reference point, such as an analog ground.
• Place the external components as close to the device as possible. As shown in Figure 60, keep feedback
resistors close to the inverting input to minimize parasitic capacitance and the feedback loop area.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• For proper amplifier function, connect the package thermal pad to the most negative supply voltage (VEE).
10.2 Layout Example
ININ+
Place feedback
resistors to minimize
feedback loop area
GND
VEE
Place bypass
capacitors as close to
IC as possible
-IN
V+
IC ground pin
connected to lowimpedance, low-noise
system ground
+
+IN
A
±
OUT
EN
GND
+
V±
B
±
OUT
OUT
ENABLE
OUT
-IN
+IN
VEE
GND
Copper pour for thermal
pad must be connected to
negative supply (VEE)
IN+
IN-
Figure 60. Operational Amplifier Board Layout for a Difference Amplifier Configuration
26
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OPA1622
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SBOS727A – NOVEMBER 2015 – REVISED NOVEMBER 2015
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision
Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of
operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured
performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Feedback Plots Define Op Amp AC Performance , SBOA015
• Circuit Board Layout Techniques, SLOA089
• Headphone Amplifier for Voltage-Output Audio DACs Reference Design,TIDUAW1
• Stabilizing Difference Amplifiers for Headphone Applications,SLYT630
• Reducing Distortion from CMOS Analog Switches,SLYT612
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
SoundPlus, E2E are trademarks of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Blu-ray is a trademark of Blu-ray Disc Association.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
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SBOS727A – NOVEMBER 2015 – REVISED NOVEMBER 2015
www.ti.com
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA1622IDRCR
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O1622
OPA1622IDRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O1622
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Dec-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA1622IDRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA1622IDRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Dec-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA1622IDRCR
VSON
DRC
10
3000
367.0
367.0
35.0
OPA1622IDRCT
VSON
DRC
10
250
210.0
185.0
35.0
Pack Materials-Page 2
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