datasheet for AD5170BRMZ10 by Analog Devices Inc.

datasheet for AD5170BRMZ10 by Analog Devices Inc.
256-Position, Two-Time Programmable,
I2C Digital Potentiometer
AD5170
256-position digital potentiometer
Two-time programmable (TTP) set-and-forget resistance
setting allows second-chance permanent programming
Unlimited adjustments prior to one-time programming
(OTP) activation
OTP overwrite allows dynamic adjustments with userdefined preset
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact 10-lead MSOP: 3 mm × 4.9 mm package
Fast settling time: tS = 5 µs typical in power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins: AD0 and AD1
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: IDD = 6 µA maximum
Wide operating temperature: −40°C to +125°C
Evaluation board and software are available
Software replaces MicroConverter® in factory programming
applications
FUNCTIONAL BLOCK DIAGRAM
A
VDD
1
AD1
SDA
SCL
FUSE
LINKS
2
RDAC
REGISTER
GND
AD0
B
W
ADDRESS
DECODE
8
SERIAL INPUT
REGISTER
04104-0-001
FEATURES
Figure 1.
APPLICATIONS
Systems calibration
Electronics level setting
Mechanical trimmers replacement in new designs
Permanent factory PCB settings
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustments
Gain control and offset adjustments
GENERAL DESCRIPTION
The AD5170 is a 256-position, two-time programmable, digital
potentiometer1 that employs fuse link technology, giving users
two opportunities to permanently program the resistance setting.
For users who do not need to program the digital potentiometer
setting in memory more than once, the OTP feature is a costeffective alternative to EEMEM. The AD5170 performs the same
electronic adjustment function as mechanical potentiometers or
variable resistors with enhanced resolution, solid-state reliability,
and superior low temperature coefficient performance.
The AD5170 is programmed using a 2-wire, I2C®-compatible
digital interface. Unlimited adjustments are allowed before
permanently setting the resistance value, and there are two
opportunities for permanent programming. During OTP
activation, a permanent blow fuse command freezes the wiper
position (analogous to placing epoxy on a mechanical trimmer).
Unlike traditional OTP digital potentiometers, the AD5170 has
a unique temporary OTP overwrite feature that allows for new
adjustments even after the fuse is blown. However, the OTP setting
is restored during subsequent power-up conditions. This feature
allows users to treat these digital potentiometers as volatile potentiometers with a programmable preset.
For applications that program the AD5170 at the factory, Analog
Devices, Inc., offers device programming software that runs on
Windows NT®, Windows® 2000, and Windows XP operating
systems. This software effectively replaces any external I2C controllers, thus enhancing the time-to-market of the user’s systems.
1
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.461.3113 ©2003–2011 Analog Devices, Inc. All rights reserved.
AD5170
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 4 Electrical Characteristics: 2.5 kΩ ............................................... 4 Electrical Characteristics: 10 kΩ, 50 kΩ, and 100 kΩ ............. 5 Timing Characteristics: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 10 Test Circuits..................................................................................... 14 Theory of Operation ...................................................................... 15 Programming the Potentiometer Divider—Voltage Output
Operation .................................................................................... 16 ESD Protection ........................................................................... 17 Terminal Voltage Operating Range ......................................... 17 Power-Up Sequence ................................................................... 17 Power Supply Considerations................................................... 17 Layout Considerations............................................................... 18 Controlling the AD5170................................................................ 19 Software Programming ............................................................. 19 Device Programming................................................................. 19 I2C Controller Programming.................................................... 21 I2C-Compatible, 2-Wire Serial Bus.......................................... 21 Level Shifting for Different Voltage Operation ...................... 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23 One-Time Programming (OTP) .............................................. 15 Programming the Variable Resistor and Voltage—Rheostat
Operation..................................................................................... 15 REVISION HISTORY
5/11—Rev. F to Rev. G
Changes to Equation 1 and Equation 2 ....................................... 16
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
Changes to I2C Notice .................................................................... 24
5/09—Rev. E to Rev. F
Changes to Resistor Integral Nonlinearity, Table 1...................... 3
Changes to Full-Scale Error, Table 1 .............................................. 3
Changes to Zero-Scale Error, Table 1............................................. 3
Changes to Table 10........................................................................ 19
Changes to Figure 46...................................................................... 20
12/08—Rev. D to Rev. E
Changes to Resistor Integral Nonlinearity, Table 1...................... 3
Changes to OTP Supply Voltage Parameter, Table 1.................... 3
Changes to OTP Voltage Parameter, Table 2 ................................ 5
Changes to Table 5............................................................................ 8
Changes to One-Time Programming (OTP) Section................ 14
Changes to Power Supply Considerations Section..................... 16
Change to Caption, Figure 49 ....................................................... 22
Changes to Ordering Guide .......................................................... 22
7/08—Rev. C to Rev. D
Changes to Power Supplies Parameter in Table 1 and Table 2 ... 3
Updated Fuse Blow Condition to 400 ms Throughout ............... 5
1/08—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Changes to Table 3.............................................................................6
Changes to Table 5.............................................................................8
Inserted Figure 25........................................................................... 12
Changes to One-Time Programming (OTP) Section................ 14
Changes to Power Supply Considerations Section .................... 16
Deleted Figure 38 and Figure 39 .................................................. 17
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 21
5/05—Rev. A to Rev. B
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................5
Changes to Pin Function Descriptions...........................................9
Changes to Figure 28...................................................................... 14
Changes to Power Supply Considerations Section .................... 17
Changes to I2C-Compatible 2-Wire Serial Bus Section............ 21
Added Level Shifting for Different Voltage Operation
Section.............................................................................................. 23
Added Figure 48 ............................................................................. 23
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 24
Rev. G | Page 2 of 24
AD5170
11/04—Rev. 0 to Rev. A
Changes to Electrical Characteristics Table 1................................3
Changes to Electrical Characteristics Table 2................................4
Changes to One-Time Programming ..........................................12
Changes to Figure 37, Figure 38, and Figure 39 .........................14
Changes to Power Supply Considerations ...................................14
Changes to Figure 40 ......................................................................15
Changes to Layout Considerations ...............................................15
11/03—Revision 0: Initial Version
Rev. G | Page 3 of 24
AD5170
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: 2.5 kΩ
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity 2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance 3
Resistance Temperature Coefficient
RWB (Wiper Resistance)
DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE (SPECIFICATIONS APPLY TO ALL VRs)
Differential Nonlinearity 4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range 5
Capacitance A, Capacitance B 6
Capacitance W6
Shutdown Supply Current 7
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High (SDA and SCL) 8
Input Logic Low (SDA and SCL)8
Input Logic High (AD0 and AD1)
Input Logic Low (AD0 and AD1)
Input Current
Input Capacitance6
POWER SUPPLIES
Power Supply Range
OTP Supply Voltage8, 9
Supply Current
OTP Supply Current8, 10, 11
Power Dissipation 12
Power Supply Sensitivity
Symbol
Conditions
Min
Typ 1
Max
Unit
R-DNL
R-INL
∆RAB
(∆RAB/RAB)/∆T
RWB
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
−2
−14
−20
±0.1
±2
+2
+14
+55
LSB
LSB
%
ppm/°C
Ω
DNL
INL
(∆VW/VW)/∆T
VWFSE
VWZSE
VA, VB, VW
CA, CB
CW
IA_SD
ICM
VIH
VIL
VIH
VIL
IIL
CIL
VDD RANGE
VDD_OTP
IDD
IDD_OTP
PDISS
PSS
35
160
Code = 0x00, VDD = 5 V
−1.5
−2
Code = 0x80
Code = 0xFF
Code = 0x00
−14
0
±0.1
±0.6
15
−5.5
4.5
GND
f = 1 MHz, measured to GND,
code = 0x80
f = 1 MHz, measured to GND,
code = 0x80
VDD = 5.5 V
VA = VB = VDD/2
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
200
+1.5
+2
0
12
VDD
45
V
pF
60
pF
0.01
1
0.7 VDD
−0.5
2.1
1
μA
nA
VDD + 0.5
+0.3 VDD
V
V
V
V
μA
pF
0.6
±1
5
TA = 25°C
VIH = 5 V or VIL = 0 V
VDD_OTP = 5 V, TA = 25°C
VIH = 5 V or VIL = 0 V, VDD = 5 V
VDD = 5 V ± 10%, code =
midscale
Rev. G | Page 4 of 24
2.7
5.6
LSB
LSB
ppm/°C
LSB
LSB
5.7
3.5
100
±0.02
5.5
5.8
6
33
±0.08
V
V
μA
mA
μW
%/%
AD5170
Parameter
DYNAMIC CHARACTERISTICS 13
–3 dB Bandwidth
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage Density
Symbol
Conditions
BW_2.5k
THDW
tS
Code = 0x80
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = 5 V, VB = 0 V, ±1 LSB error
band
RWB = 1.25 kΩ, f = 1 kHz
eN_WB
Min
Typ 1
Max
Unit
4.8
0.1
1
MHz
%
μs
3.2
nV/√Hz
1
Typical specifications represent average readings at 25°C and VDD = 5 V.
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
VAB = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled
up to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without
pull-up resistors.
9
Different from operating power supply; power supply for OTP is used one time only.
10
Different from operating current; supply current for OTP lasts approximately 400 ms for use one time only.
11
See Figure 26 for the energy plot during OTP program.
12
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
13
All dynamic characteristics use VDD = 5 V.
2
ELECTRICAL CHARACTERISTICS: 10 kΩ, 50 kΩ, AND 100 kΩ
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity 2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance 3
Resistance Temperature Coefficient
RWB (Wiper Resistance)
DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE (SPECIFICATIONS APPLY TO ALL VRs)
Differential Nonlinearity 4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range 5
Capacitance A, Capacitance B 6
Capacitance W6
Shutdown Supply Current 7
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High (SDA and SCL) 8
Input Logic Low (SDA and SCL)8
Input Logic High (AD0 and AD1)
Input Logic Low (AD0 and AD1)
Input Current
Input Capacitance6
Symbol
Conditions
Min
Typ 1
Max
Unit
R-DNL
R-INL
∆RAB
(∆RAB/RAB)/∆T
RWB
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
−1
−2.5
−20
±0.1
±0.25
+1
+2.5
+20
LSB
LSB
%
ppm/°C
Ω
DNL
INL
(∆VW/VW)/∆T
VWFSE
VWZSE
VA, VB, VW
CA, CB
CW
IA_SD
ICM
VIH
VIL
VIH
VIL
IIL
CIL
35
160
Code = 0x00, VDD = 5 V
−1
−1
Code = 0x80
Code = 0xFF
Code = 0x00
−2.5
0
±0.1
±0.3
15
−1
1
GND
f = 1 MHz, measured to GND,
code = 0x80
f = 1 MHz, measured to GND,
code = 0x80
VDD = 5.5 V
VA = VB = VDD/2
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
+1
+1
0
2.5
VDD
LSB
LSB
ppm/°C
LSB
LSB
45
V
pF
60
pF
0.01
1
0.7 VDD
−0.5
2.1
1
μA
nA
VDD + 0.5
+0.3 VDD
V
V
V
V
μA
pF
0.6
±1
5
Rev. G | Page 5 of 24
200
AD5170
Parameter
POWER SUPPLIES
Power Supply Range
OTP Supply Voltage8, 9
Supply Current
OTP Supply Current8, 10, 11
Power Dissipation 12
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS 13
–3 dB Bandwidth
Symbol
VDD RANGE
VDD_OTP
IDD
IDD_OTP
PDISS
PSS
BW
Total Harmonic Distortion
THDW
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
tS
Resistor Noise Voltage Density
eN_WB
Conditions
Min
2.7
5.6
VIH = 5 V or VIL = 0 V
VDD_OTP = 5 V, TA = 25°C
VIH = 5 V or VIL = 0 V, VDD = 5 V
VDD = 5 V ± 10%, code =
midscale
RAB = 10 kΩ, code = 0x80
RAB = 50 kΩ, code = 0x80
RAB = 100 kΩ, code = 0x80
VA =1 V rms, VB = 0 V, f = 1 kHz,
RAB = 10 kΩ
VA = 5 V, VB = 0 V, ±1 LSB error
band
RWB = 5 kΩ, f = 1 kHz
1
Typ 1
5.7
3.5
100
±0.02
Max
Unit
5.5
5.8
6
V
V
μA
mA
μW
%/%
33
±0.08
600
100
40
0.1
kHz
kHz
kHz
%
2
μs
9
nV/√Hz
Typical specifications represent average readings at 25°C and VDD = 5 V.
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
VAB = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up
to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pullup resistors.
9
Different from operating power supply, power supply OTP is used one time only.
10
Different from operating current, supply current for OTP lasts approximately 400 ms for use one time only.
11
See Figure 26 for the energy plot during OTP program.
12
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
13
All dynamic characteristics use VDD = 5 V.
2
Rev. G | Page 6 of 24
AD5170
TIMING CHARACTERISTICS: 2.5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD; VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter
I2C INTERFACE TIMING CHARACTERISTICS 1 (SPECIFICATIONS
APPLY TO ALL PARTS)
SCL Clock Frequency
tBUF Bus Free Time Between Stop and Start
tHD;STA Hold Time (Repeated Start)
Symbol
fSCL
t1
t2
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Repeated Start Condition
tHD;DAT Data Hold Time 2
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for Stop Condition
OTP Program Time
1
2
Conditions
Min
After this period, the first clock
pulse is generated
t3
t4
t5
t6
t7
t8
t9
t10
t11
Typ
Max
Unit
400
kHz
μs
μs
1.3
0.6
1.3
0.6
0.6
μs
μs
μs
μs
ns
ns
ns
μs
ms
0.9
100
300
300
0.6
400
See Figure 2 for locations of measured values.
The maximum tHD;DAT must be met only if the device does not stretch the low period (tLOW) of the SCL signal.
Timing Diagram
t8
t6
t2
t9
SCL
t2
t4
t3
t8
t7
t10
t5
t9
t1
P
S
S
Figure 2. I2C Interface Detailed Timing Diagram
Rev. G | Page 7 of 24
P
04104-044
SDA
AD5170
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to GND
VA, VB, VW to GND
Terminal Current, A to B, A to W, B to W 1
Pulsed
Continuous
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (TJMAX)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Thermal Resistance 2
θJA: 10-Lead MSOP
Rating
−0.3 V to +7 V
VDD
±20 mA
±5 mA
0 V to 7 V
−40°C to +125°C
150°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
230°C/W
1
Maximum terminal current is bound by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Package power dissipation = (TJMAX − TA)/θJA.
Rev. G | Page 8 of 24
AD5170
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A 2
AD0 3
GND 4
VDD 5
10 W
AD5170
9
NC
TOP VIEW
(Not to Scale)
8
AD1
7
SDA
6
SCL
04104-048
B 1
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
Mnemonic
B
A
AD0
GND
VDD
6
SCL
7
SDA
8
9
10
AD1
NC
W
Description
B Terminal. GND ≤ VB ≤ VDD.
A Terminal. GND ≤ VA ≤ VDD.
Programmable Address Bit 0 for Multiple Package Decoding.
Digital Ground.
Positive Power Supply. Specified for operation from 2.7 V to 5.5 V. For OTP programming, the VDD supply must be
within the 5.6 V to 5.8 V range and capable of driving 100 mA.
Serial Clock Input. Positive edge triggered. Requires a pull-up resistor. If it is driven directly from a logic controller
without the pull-up resistor, ensure that VIH minimum is 0.7 V × VDD.
Serial Data Input/Output. Requires a pull-up resistor. If it is driven directly from a logic controller without the
pull-up resistor, ensure that VIH minimum is 0.7 V × VDD.
Programmable Address Bit 1 for Multiple Package Decoding.
No Connect.
W Terminal. GND ≤ VW ≤ VDD.
Rev. G | Page 9 of 24
AD5170
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
2.0
TA = 25°C
RAB = 10kΩ
1.0
VDD = 2.7V
0.5
0
VDD = 5.5V
–0.5
RAB = 10kΩ
0.4
POTENTIOMETER MODE DNL (LSB)
–1.0
–1.5
0.3
0.2
0.1
VDD = 2.7V; TA = –40°C, +25°C, +85°C, +125°C
0
–0.1
–0.2
–0.3
–0.4
64
96
128
160
192
224
256
CODE (DECIMAL)
–0.5
0
96
128
160
192
224
256
256
256
Figure 7. DNL vs. Code vs. Temperature
0.5
1.0
TA = 25°C
RAB = 10kΩ
0.3
0.2
VDD = 2.7V
0.1
0
–0.1
–0.2
VDD = 5.5V
–0.3
TA = 25°C
RAB = 10kΩ
0.8
POTENTIOMETER MODE INL (LSB)
0.4
RHEOSTAT MODE DNL (LSB)
64
CODE (DECIMAL)
Figure 4. R-INL vs. Code vs. Supply Voltages
–0.4
0.6
0.4
VDD = 5.5V
0.2
0
VDD = 2.7V
–0.2
–0.4
–0.6
–0.8
0
32
64
96
128
160
192
224
256
CODE (DECIMAL)
–1.0
04104-003
–0.5
0
32
64
96
128
160
192
224
CODE (DECIMAL)
Figure 5. R-DNL vs. Code vs. Supply Voltages
Figure 8. INL vs. Code vs. Supply Voltages
0.5
0.5
RAB = 10kΩ
0.3
VDD = 5.5V
TA = –40°C, +25°C, +85°C, +125°C
0.2
0.1
0
–0.1
VDD = 2.7V
TA = –40°C, +25°C, +85°C, +125°C
–0.2
TA = 25°C
RAB = 10kΩ
0.4
POTENTIOMETER MODE DNL (LSB)
0.4
–0.3
–0.4
0.3
0.2
0.1
VDD = 2.7V
0
–0.1
VDD = 5.5V
–0.2
–0.3
–0.4
–0.5
0
32
64
96
128
160
192
CODE (DECIMAL)
224
256
04104-004
POTENTIOMETER MODE INL (LSB)
32
04104-005
32
04104-006
0
04104-002
–2.0
04104-007
RHEOSTAT MODE INL (LSB)
1.5
Figure 6. INL vs. Code vs. Temperature
–0.5
0
32
64
96
128
160
192
CODE (DECIMAL)
Figure 9. DNL vs. Code vs. Supply Voltages
Rev. G | Page 10 of 24
224
AD5170
2.0
4.50
RAB = 10kΩ
RAB = 10kΩ
1.0
0.5
0
VDD = 5.5V
TA = –40°C, +25°C, +85°C, +125°C
–0.5
–1.0
–1.5
0
32
64
96
128
160
192
224
256
CODE (DECIMAL)
3.00
2.25
VDD = 2.7V, VA = 2.7V
1.50
VDD = 5.5V, VA = 5.0V
0.75
0
–40
04104-008
–2.0
3.75
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
Figure 13. Zero-Scale Error vs. Temperature
Figure 10. R-INL vs. Code vs. Temperature
10
0.5
RAB = 10kΩ
0.4
0.3
0.2
IDD, SUPPLY CURRENT (µA)
RHEOSTAT MODE DNL (LSB)
–25
04104-011
VDD = 2.7V
TA = –40°C, +25°C, +85°C, +125°C
ZSE, ZERO-SCALE ERROR (LSB)
RHEOSTAT MODE INL (LSB)
1.5
VDD = 2.7V, 5.5V; TA = –40°C, +25°C, +85°C, +125°C
0.1
0
–0.1
–0.2
VDD = 5V
1
VDD = 3V
–0.3
32
64
96
128
160
192
224
256
CODE (DECIMAL)
0.1
–40
–7
26
59
92
Figure 14. IDD, Supply Current vs. Temperature
Figure 11. R-DNL vs. Code vs. Temperature
120
2.0
RAB = 10kΩ
RAB = 10kΩ
RHEOSTAT MODE TEMPCO (ppm/°C)
1.0
0.5
0
VDD = 5.5V, VA = 5.0V
–0.5
–1.0
VDD = 2.7V, VA = 2.7V
–1.5
100
80
60
VDD = 2.7V
TA = –40°C TO +85°C, –40°C TO +125°C
40
VDD = 5.5V
TA = –40°C TO +85°C, –40°C TO +125°C
20
0
–20
–25
–10
5
20
35
50
65
80
95
TEMPERATURE (°C)
110
125
04104-010
FSE, FULL-SCALE ERROR (LSB)
1.5
–2.0
–40
125
TEMPERATURE (°C)
0
32
64
96
128
160
192
224
CODE (DECIMAL)
Figure 15. Rheostat Mode Tempco ∆RWB/∆T vs. Code
Figure 12. Full-Scale Error vs. Temperature
Rev. G | Page 11 of 24
256
04104-013
0
04104-009
–0.5
04104-012
–0.4
AD5170
0
RAB = 10kΩ
0x80
–6
40
0x40
–12
30
GAIN (dB)
20
0x20
–18
VDD = 2.7V
TA = –40°C TO +85°C, –40°C TO +125°C
10
0
0x10
–24
0x08
–30
0x04
–36
0x02
–42
–10
0x01
VDD = 5.5V
TA = –40°C TO +85°C, –40°C TO +125°C
–48
–20
–54
64
96
128
160
192
224
256
CODE (DECIMAL)
–60
1k
10k
1M
10M
Figure 19. Gain vs. Frequency vs. Code, RAB = 50 kΩ
0
0
0x80
–6
0x80
–6
0x40
–12
0x40
–12
0x20
–18
0x20
–18
0x10
–24
–30
GAIN (dB)
0x08
0x04
–36
0x02 0x01
–42
0x10
–24
0x08
–30
0x04
–36
0x02
–42
0x01
–48
–48
–54
–54
–60
10k
100k
1M
10M
FREQUENCY (Hz)
–60
04104-015
GAIN (dB)
1M
FREQUENCY (Hz)
Figure 16. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
1k
10k
100k
FREQUENCY (Hz)
Figure 17. Gain vs. Frequency vs. Code, RAB = 2.5 kΩ
Figure 20. Gain vs. Frequency vs. Code, RAB = 100 kΩ
0
0
0x80
–6
–12
0x40
–18
0x20
–6
–12
GAIN (dB)
–24
0x08
–30
0x04
–36
0x02
0x01
–42
–24
10kΩ
570kHz
2.5kΩ
2.2MHz
–36
–42
–48
–54
–54
–60
10k
50kΩ
120kHz
–30
–48
1k
100kΩ
60kHz
–18
0x10
100k
FREQUENCY (Hz)
1M
04104-016
GAIN (dB)
100k
04104-017
32
04104-018
0
04104-019
–30
04104-014
POTENTIOMETER MODE TEMPCO (ppm/°C)
50
Figure 18. Gain vs. Frequency vs. Code, RAB = 10 kΩ
–60
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 21. −3 dB Bandwidth at Code = 0x80
Rev. G | Page 12 of 24
AD5170
10
1
VDD = 5.5V
VW
0.1
VDD = 2.7V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
DIGITAL INPUT VOLTAGE (V)
04104-020
0.01
04104-023
SCL
Figure 22. IDD, Supply Current vs. Digital Input Voltage
Figure 25. Large Signal Settling Time
CH1 MAX
103mA
VW
CH1 MIN
–1.98mA
04104-021
CH1 20.0mAΩ
Figure 23. Digital Feedthrough
M 200ns
A CH1
T
588.000ns
32.4mA
Figure 26. OTP Program Energy Plot for Single Fuse
VW
Figure 24. Midscale Glitch, Code 0x80 to Code 0x7F
Rev. G | Page 13 of 24
04104-033
1
SCL
04104-025
IDD, SUPPLY CURRENT (mA)
TA = 25°C
AD5170
TEST CIRCUITS
Figure 27 to Figure 32 illustrate the test circuits that define the test conditions used in the product specification tables.
VA
V+
VDD A
W
V+
B
VMS
PSRR (dB) = 20 LOG
VMS%
PSS (%/%) =
VDD%
W
B
Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
DUT
A
IW
A W
)
+5V
W
VIN
AD8610
B
VOUT
OFFSET
GND
04104-027
B
VMS
VMS
VDD
Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSRR)
NO CONNECT
DUT
(
VMS
04104-026
A
V+ = VDD ± 10%
DUT
04104-030
DUT
04104-029
V+ = VDD
1LSB = V+/2N
–5V
2.5V
Figure 31. Test Circuit for Gain vs. Frequency
Figure 28. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
NC
W
IW = VDD/RNOMINAL
VW
A
VDD
B
VMS1
GND
RW = [VMS1 – VMS2]/IW
04104-028
A
VMS2
DUT
W
ICM
B
NC
VCM
NC = NO CONNECT
04104-032
DUT
Figure 32. Test Circuit for Common-Mode Leakage Current
Figure 29. Test Circuit for Wiper Resistance
Rev. G | Page 14 of 24
AD5170
THEORY OF OPERATION
A
SCL
SDA
I2C
INTERFACE
DECODER
MUX
DAC
REG.
W
B
COMPARATOR
FUSES
EN
FUSE
REG.
04104-022
ONE-TIME
PROGRAM/TEST
CONTROL BLOCK
Figure 33. Detailed Functional Block Diagram
The AD5170 is a 256-position, digitally controlled, variable
resistor (VR) that employs fuse link technology to achieve
memory retention of the resistance setting.
Table 6. Validation Status
ONE-TIME PROGRAMMING (OTP)
Prior to OTP activation, the AD5170 presets to midscale during
initial power-on. After the wiper is set at the desired position,
the resistance can be permanently set by programming the T bit
high along with the proper coding (see Table 9 and Table 10) and
one-time VDD_OTP. Note that fuse link technology of the AD517x
family of digital potentiometers requires that VDD_OTP between 5.6 V
and 5.8 V blow the fuses to achieve a given nonvolatile setting. On
the other hand, VDD can be 2.7 V to 5.5 V during operation. For
system supplies that are lower than 5.6 V, an external supply for
one-time programming is required. Note that the user is allowed
only one attempt in blowing the fuses. If the user fails to blow the
fuses at the first attempt, the structures of the fuses may have
changed such that they can never be blown, regardless of the
energy applied at subsequent events. For details, see the Power
Supply Considerations section.
The device control circuit has two validation bits, E1 and E0,
that can be read back to check the programming status (see
Table 6). Users should always read back the validation bits to
ensure that the fuses are properly blown. After the fuses are
blown, all fuse latches are enabled upon subsequent power-on;
therefore, the output corresponds to the stored setting. Figure 33
shows a detailed functional block diagram.
E0
0
0
1
1
Status
Ready for programming.
Fatal error. Some fuses are not blown. Do not retry.
Discard this unit.
Successful. No further programming is possible.
PROGRAMMING THE VARIABLE RESISTOR AND
VOLTAGE—RHEOSTAT OPERATION
The nominal resistance (RAB) between Terminal A and Terminal B
is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal
resistance of the VR has 256 contact points that are accessed by
the wiper terminal, plus the B terminal contact. The 8-bit data
in the RDAC latch is decoded to select one of the 256 possible
settings.
A
A
W
B
A
W
B
W
B
04104-024
An internal power-on preset places the wiper at midscale during
power-on. If the OTP function is activated, the device powers
up at the user-defined permanent setting.
E1
0
1
Figure 34. Rheostat Mode Configuration
Assuming that a 10 kΩ part is used, the first connection of the
wiper starts at Terminal B for Data 0x00. Because there is a 50 Ω
wiper contact resistance, such a connection yields a minimum of
100 Ω (2 × 50 Ω) resistance between Terminal W and Terminal B.
The second connection is the first tap point, which corresponds
to 139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 × 50 Ω) for Data
0x01. The third connection is the next tap point, representing
178 Ω (2 × 39 Ω + 2 × 50 Ω) for Data 0x02, and so on. Each LSB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 10,100 Ω (RAB + 2 × RW).
Rev. G | Page 15 of 24
AD5170
For RAB = 10 kΩ and Terminal B open circuited, Table 8 shows
some examples of the output resistance (RWA) vs. the RDAC
latch codes.
A
SD BIT
RS
Table 8. Codes and Corresponding RWA Resistance
RS
D (Dec)
255
128
1
0
RS
W
04104-034
RS
B
PROGRAMMING THE POTENTIOMETER DIVIDER—
VOLTAGE OUTPUT OPERATION
Figure 35. Equivalent RDAC Circuit
The general equation that determines the digitally programmed
output resistance between Terminal W and Terminal B is
RWB (D) =
D
× R AB + 2 × RW
256
(1)
The digital potentiometer easily generates a voltage divider at
wiper to B and wiper to A proportional to the input voltage at
A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
VI
A
W
Table 7. Codes and Corresponding RWB Resistance
RWB (Ω)
9961
5060
139
100
VO
B
In summary, if RAB = 10 kΩ and Terminal A is open-circuited,
the output resistance, RWB, is set for the RDAC latch codes, as
shown in Table 7.
D (Dec)
255
128
1
0
Output State
Full scale
Midscale
1 LSB
Zero scale
Typical device-to-device matching is process-lot dependent
and can vary by up to ±30%. Because the resistance element is
processed using thin film technology, the change in RAB with
temperature has a very low 35 ppm/°C temperature coefficient.
RDAC
LATCH
AND
DECODER
RWA (Ω)
139
5060
9961
10,060
Output State
Full scale (RAB − 1 LSB + RW)
Midscale
1 LSB
Zero scale (wiper contact resistance)
04104-035
D7
D6
D5
D4
D3
D2
D1
D0
Figure 36. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting Terminal A to 5 V and Terminal B to ground produces an output voltage at the wiper to B starting at 0 V up to
1 LSB less than 5 V. Each LSB of voltage is equal to the voltage
applied across Terminal A and Terminal B divided by the 256
positions of the potentiometer divider. The general equation
defining the output voltage at VW with respect to ground for any
valid input voltage applied to Terminal A and Terminal B is
VW (D) =
D
256 − D
VA +
VB
256
256
(3)
Note that in the zero-scale condition, a finite wiper resistance of
100 Ω is present. Care should be taken to limit the current flow
between Terminal W and Terminal B in this state to a maximum
pulse current of no more than 20 mA. Otherwise, degradation
or possible destruction of the internal switch contact can occur.
For a more accurate calculation, which includes the effect of
wiper resistance, VW, the following equation can be used:
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper (Terminal W) and Terminal A also
produces a digitally controlled, complementary resistance, RWA.
When these terminals are used, Terminal B can be opened.
Setting the resistance value for RWA starts at a maximum value
of resistance and decreases as the data loaded in the latch
increases in value. The general equation for this operation is
Operation of the digital potentiometer in divider mode results
in a more accurate operation over temperature. Unlike rheostat
mode, the output voltage is dependent mainly on the ratio of
the internal resistors, RWA and RWB, and not the absolute values.
Therefore, the temperature drift reduces to 15 ppm/°C.
RWA (D) =
256 – D
× R AB + 2 × RW
256
VW (D) =
(2)
Rev. G | Page 16 of 24
R (D )
RWB (D)
VB
VA + WA
R AB
R AB
(4)
AD5170
ESD PROTECTION
All digital inputs, SDA, SCL, AD0, and AD1, are protected with
a series input resistor and parallel Zener ESD structures, as shown
in Figure 37 and Figure 38.
When the fuse programming is complete, the VDD_OTP supply
must be removed to allow normal operation at 2.7 V to 5.5 V,
and the device consumes current in the μA range.
R1
340Ω
LOGIC
10kΩ
04104-037
GND
APPLY FOR OTP ONLY
5.7V
2.7V
P1
Figure 37. ESD Protection of Digital Pins
P2
C1
10µF
C2
0.1µF
VDD
AD5170
A, B, W
04104-038
GND
04104-0-51
P1 = P2 = FDV302P, NDS0610
Figure 40. Isolate 5.7 V OTP Supply from 2.7 V Normal Operating Supply
Figure 38. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5170 VDD-to-GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer operation. Supply signals present on Terminal A, Terminal B, and
Terminal W that exceed VDD or GND are clamped by the internal
forward-biased diodes (see Figure 39).
VDD
A
W
GND
04104-039
B
Figure 39. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W, it is important to
power VDD/GND before applying any voltage to Terminal A,
Terminal B, and Terminal W (see Figure 39). Otherwise, the
diode is forward-biased such that VDD is powered unintentionally
and may affect the rest of the user’s circuit. The ideal power-up
sequence is GND, VDD, the digital inputs, and then VA/VB/VW.
The relative order of powering VA, VB, VW, and the digital inputs
is not important as long as they are powered up after GND/VDD.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time programming and normal operating voltage supplies share the
same VDD terminal of the AD5170. The AD5170 employs fuse
link technology that requires 5.6 V to 5.8 V for blowing the
internal fuses to achieve a given setting, but normal VDD can be
anywhere between 2.7 V and 5.5 V after the fuse programming
process. As a result, dual voltage supplies and isolation are needed if
system VDD is lower than the required VDD_OTP. The fuse programming supply (either an on-board regulator or rack-mount power
supply) must be rated at 5.6 V to 5.8 V and be able to provide a
100 mA current for 400 ms for successful OTP.
For example, for those who operate their systems at 2.7 V, use of
the bidirectional, low threshold, P-Channel MOSFETs is recommended for the isolation of the supply. As shown in Figure 40,
this assumes that the 2.7 V system voltage is applied first, and
the P1 and P2 gates are pulled to ground, thus turning on P1 and,
subsequently, P2. As a result, VDD of the AD5170 approaches 2.7 V.
When the AD5170 setting is found, the factory tester applies the
VDD_OTP to both the VDD and the MOSFETs gates, turning off P1
and P2. The OTP command is executed at this time to program the
AD5170 while the 2.7 V source is protected. When the fuse programming is complete, the tester withdraws the VDD_OTP and the
setting for the AD5170 is permanently fixed.
The AD5170 achieves the OTP function by blowing internal
fuses. Users should always apply the 5.6 V to 5.8 V one-timeprogram voltage requirement at the first fuse programming
attempt. Failure to comply with this requirement can lead to a
change in the fuse structures, rendering programming inoperable.
Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high
level is between 0.7 V × VDD and VDD + 0.5 V. Refer to the Level
Shifting for Different Voltage Operation section.
Poor PCB layout introduces parasitics that can affect the fuse
programming. Therefore, it is recommended to add a 10 μF
tantalum capacitor in parallel with a 1 nF ceramic capacitor as
close as possible to the VDD pin. The type and value chosen for
both capacitors are important. This combination of capacitor
values provides both a fast response and larger supply current
handling with minimum supply droop during transients. As a
result, these capacitors increase the OTP programming success
by not inhibiting the proper energy needed to blow the internal
fuses. Additionally, C1 minimizes transient disturbance and low
frequency ripple, and C2 reduces high frequency noise during
normal operation.
Rev. G | Page 17 of 24
AD5170
LAYOUT CONSIDERATIONS
Note that the digital ground should also be joined remotely to
the analog ground at one point to minimize the ground bounce.
VDD
C1
10µF
+
C2
1nF
VDD
AD5170
GND
04104-040
It is good practice to employ compact, minimum lead length,
layout design. The leads to the inputs should be as direct as
possible, with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Figure 41. Power Supply Bypassing
Rev. G | Page 18 of 24
AD5170
CONTROLLING THE AD5170
04104-041
There are two ways of controlling the AD5170. Users can program the device with either computer software or external I2C controllers.
Figure 42. AD5170 Computer Software Interface
SOFTWARE PROGRAMMING
Write
The AD5170 starts at midscale after power-up prior to OTP
programming. To increment or decrement the resistance, move
the scroll bars on the left. To write any specific value, use the bit
pattern in the upper screen and click Run. The format of writing
data to the device is shown in Table 9. Once the desired setting
is found, click Program Permanent: First Fuse Link to blow
the internal fuse links.
Read
R3
SCL
100Ω
R2 READ
100Ω
SDA
R1 WRITE
100Ω
04104-042
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
Due to the advantages of the one-time programmable feature,
consider programming the device in the factory before shipping
the final product to the end users. Analog Devices offers device
programming software that can be implemented in the factory
on PCs running Windows 95 or later. As a result, external controllers are not required, significantly reducing development time.
The program is an executable file that does not require knowledge
of programming languages or programming skills, and it is easy to
set up and to use. Figure 42 shows the software interface. The
software can be downloaded from the AD5170 product page.
Figure 43. Parallel Port Connection
(Pin 2 = SDA_write, Pin 3 = SCL, Pin 15 = SDA_read, and Pin 25 = DGND)
To read the validation bits and data from the device, click Read.
The format of the read bits is shown in Table 10.
To apply the device programming software in the factory, modify
a parallel port cable and configure Pin 2, Pin 3, Pin 15, and Pin 25
for SDA_write, SCL, SDA_read, and DGND, respectively, for
the control signals (see Figure 43). Also, lay out the PCB of the
AD5170 with SCL and SDA pads, as shown in Figure 44, such
that pogo pins can be inserted for factory programming.
Rev. G | Page 19 of 24
W
NC
AD1
SDA
SCL
04104-043
DEVICE PROGRAMMING
AD5170
B
A
AD0
GND
VDD
Figure 44. Recommended AD5170 PCB Layout
AD5170
Table 9. Write Mode
S
0
1
0
1 1 AD1 AD0
Slave Address Byte
W
A
2T
A
D7
SD
T 0 OW X
Instruction Byte
X
X
A
D7
D6
D5
D4 D3
Data Byte
D2
D1
D0
A
P
X
A
P
Table 10. Read Mode
S
0
1
0
1 1 AD1 AD0
Slave Address Byte
R
D6
D5
D4 D3
Data Byte
D2
D1
D0
A
E1
E0
X X X X
Validation Byte
X
Table 11. SDA Bit Definitions and Descriptions
Bit
S
P
A
AD0, AD1
X
W
R
2T
SD
T
OW
D7, D6, D5, D4, D3,
D2, D1, and D0
E1, E0
Description
Start condition.
Stop condition.
Acknowledge.
Package pin-programmable address bits.
Don’t care.
Write.
Read.
Second fuse link array for two-time programming. Logic 0 corresponds to first trim. Logic 1 corresponds to
second trim. Note that blowing Trim 2 before Trim 1 effectively disables Trim 1 and, in turn, allows only one-time
programming.
Shutdown connects wiper to Terminal B and open circuits Terminal A. It does not change the contents of the wiper register.
OTP programming bit. Logic 1 permanently programs the wiper.
Overwrite the fuse setting and program the digital potentiometer to a different setting. Note that upon power-up,
the digital potentiometer presets to either midscale or fuse setting, depending on whether the fuse link is blown.
Data bits.
OTP validation bits:
0, 0 = ready to program.
1, 0 = fatal error. Some fuses are not blown. Do not retry. Discard this unit.
1, 1 = programmed successfully. No further adjustments are possible.
Rev. G | Page 20 of 24
AD5170
I2C CONTROLLER PROGRAMMING
Write Bit Patterns
9
1
1
9
9
1
SCL
0
1
0
1
1
AD1 AD0 R/W
A0
SD
T
0
OW
X
X
ACK BY
AD5170
START BY
MASTER
D7
X
D6
D5
D4
D3
D2
D1
D0
ACK BY
AD5170
ACK BY
AD5170
FRAME 2
INSTRUCTION BYTE
FRAME 1
SLAVE ADDRESS BYTE
STOP BY
MASTER
FRAME 3
DATA BYTE
04104-045
SDA
Figure 45. Writing Data to the RDAC Register
Read Bit Pattern
9
1
1
9
9
1
SCL
0
1
0
1
1
AD1 AD0 R/W
D7
D6
D5
D4
D3
D2
ACK BY
AD5170
START BY
MASTER
D1
D0
E1
E0
X
X
X
X
X
FRAME 2
DATA BYTE
FRAME 1
SLAVE ADDRESS BYTE
X
NO ACK
BY MASTER
ACK BY
MASTER
FRAME 3
VALIDATION BYTE
STOP BY
MASTER
04104-046
SDA
Figure 46. Reading Data from the RDAC Register
I2C-COMPATIBLE, 2-WIRE SERIAL BUS
2
The following section describes how the 2-wire, I C serial bus
protocol operates (see Figure 45 and Figure 46).
The master initiates a data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line
occurs while SCL is high (see Figure 45). The following byte is
the slave address byte, which consists of the slave address followed
by an R/W bit (this bit determines whether data is read from or
written to the slave device). AD0 and AD1 are configurable address
bits that allow up to four devices on one bus (see Table 9).
The slave address corresponding to the transmitted address bits
responds by pulling the SDA line low during the ninth clock
pulse (this is called the acknowledge bit). At this stage, all other
devices on the bus remain idle while the selected device waits
for data to be written to, or read from, its serial register. If the
R/W bit is high, the master reads from the slave device. If the
R/W bit is low, the master writes to the slave device.
In write mode, the second byte is the instruction byte. The first
MSB of the instruction byte, 2T, is the second trim enable bit.
A logic low selects the first array of the fuses, and a logic high
selects the second array of the fuses. This means that after blowing
the fuses with Trim 1, the user still has another chance to blow
them again with Trim 2. Note that using Trim 2 before Trim 1
effectively disables Trim 1 and, in turn, allows only one-time
programming.
The second MSB, SD, is a shutdown bit. A logic high causes an
open circuit at Terminal A and shorts the wiper to Terminal B.
This operation yields almost 0 Ω in rheostat mode or 0 V in
potentiometer mode. Note that the shutdown operation does
not disturb the contents of the register. When brought out of
shutdown, the previous setting is applied to the RDAC. In
addition, new settings can be programmed during shutdown.
When the part is returned from shutdown, the corresponding
VR setting is applied to the RDAC.
The third MSB, T, is the OTP programming bit. A logic high
blows the polyfuses and programs the resistor setting permanently. For example, if the user wants to blow the first array
of fuses, the instruction byte is 00100XXX. To blow the second
array of fuses, the instruction byte is 10100XXX. A logic low of
the T bit simply allows the device to act as a typical volatile digital
potentiometer.
The fourth MSB must always be Logic 0.
The fifth MSB, OW, is an overwrite bit. When raised to a logic
high, OW allows the RDAC setting to be changed even after the
internal fuses are blown. However, when OW is returned to
Logic 0, the position of the RDAC returns to the setting prior to
the overwrite. Because OW is not static, if the device is powered
off and on, the RDAC presets to midscale or to the setting at
which the fuses were blown, depending on whether the fuses
are permanently set.
The remainder of the bits in the instruction byte are don’t care
bits (see Figure 45).
After acknowledging the instruction byte, the last byte in write
mode is the data byte. Data is transmitted over the serial bus in
sequences of nine clock pulses (eight data bits followed by an
acknowledge bit). The transitions on the SDA line must occur
during the low period of SCL and remain stable during the high
period of SCL (see Figure 2).
In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is transmitted
over the serial bus in sequences of nine clock pulses (a slight
difference from write mode, with eight data bits followed by an
acknowledge bit). Similarly, transitions on the SDA line must
occur during the low period of SCL and remain stable during
the high period of SCL (see Figure 46).
Following the data byte, the validation byte contains two validation bits, E0 and E1. These bits signify the status of the one-time
programming (see Figure 46).
Rev. G | Page 21 of 24
AD5170
5V
RP
SDA
MASTER
SCL
5V
In read mode, the master issues a no acknowledge for the 9th
clock pulse (that is, the SDA line remains high). The master brings
the SDA line low before the 10th clock pulse and then brings the
SDA line high to establish a stop condition (see Figure 46).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. For example, after the RDAC has acknowledged
its slave address and instruction bytes in write mode, the RDAC
output updates on each successive byte. If different instructions
are needed, the write/read mode has to start again with a new
slave address, instruction, and data byte. Similarly, a repeated
read function of the RDAC is also allowed.
Multiple Devices on One Bus
Figure 47 shows four AD5170s on the same serial bus. Each has
a different slave address because the states of their AD0 and
AD1 pins are different, which allows each device on the bus to
be written to or read from independently. The master device
output bus line drivers are open-drain pull-downs in a fully
I2C-compatible interface.
RP
SDA
SCL
5V
SDA
5V
SDA
SCL
SCL
SDA
SCL
AD1
AD1
AD1
AD1
AD0
AD0
AD0
AD0
AD5170
AD5170
AD5170
AD5170
04104-047
After all the data bits are read or written, a stop condition is
established by the master. A stop condition is defined as a lowto-high transition on the SDA line while SCL is high. In write
mode, the master pulls the SDA line high during the 10th clock
pulse to establish a stop condition (see Figure 45).
Figure 47. Multiple AD5170s on One I2C Bus
LEVEL SHIFTING FOR DIFFERENT VOLTAGE
OPERATION
If the SCL and SDA signals come from a low voltage logic controller and are below the minimum VIH level (0.7 V × VDD), level
shift the signals for read/write communications between the
AD5170 and the controller. Figure 48 shows one of the implementations. For example, when SDA1 is at 2.5 V, M1 turns off and
SDA2 becomes 5 V. When the SDA1 is at 0 V, M1 turns on and
the SDA2 approaches 0 V. As a result, proper level shifting is
established. M1 and M2 should be low threshold, N-channel
power MOSFETs, such as the FDV301N.
VDD2 = 5V
VDD1 = 2.5V
Rp
Rp
Rp
Rp
G
D
S
SDA1
M1
SCL1
G
SDA2
D
S
SCL2
2.5V
CONTROLLER
2.7V TO 5.5V
AD5170
Figure 48. Level Shifting for Different Voltage Operation
Rev. G | Page 22 of 24
04104-052
M2
AD5170
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
0.23
0.13
6°
0°
0.70
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
0.15
0.05
COPLANARITY
0.10
Figure 49. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5170BRM2.5
AD5170BRM2.5-RL7
AD5170BRMZ2.5
AD5170BRM10
AD5170BRM10-RL7
AD5170BRMZ10
AD5170BRMZ10-RL7
AD5170BRM50
AD5170BRM50-RL7
AD5170BRMZ50
AD5170BRM100
AD5170BRM100-RL7
AD5170BRMZ100
1
RAB (kΩ)
2.5
2.5
2.5
10
10
10
10
50
50
50
100
100
100
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Z = RoHS Compliant Part.
Rev. G | Page 23 of 24
Package Option
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
Branding
DD2
DD2
DD7
DD3
DD3
DD4
DD4
DD0
DD0
DD6
DD1
DD1
DD5
AD5170
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2003–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04104-0-5/11(G)
Rev. G | Page 24 of 24
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