datasheet for FQV2113 by AMIC Technology

datasheet for FQV2113 by AMIC Technology
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
3.3 Volt Synchronous x9/x18 First-In/First-Out Queue
Memory Organization
Device
Memory Organization
Device
262,144 x 18 / 524,288 x 9
131,072 x 18 / 262,144 x 9
65,536 x 18 / 131,072 x 9
32,768 x 18 / 65,536 x 9
FQV2113
FQV2103
FQV293
FQV283
16,384 x 18 / 32,768 x 9
8,192 x 18 / 16,384 x 9
4,096 x 18 / 8,192 x 9
2,048 x 18 / 4,096 x 9
FQV273
FQV263
FQV253
FQV243
Key Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Industry leading First-In/First-Out Queues (up to 166MHz)
Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns)
Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns)
User selectable input and output port bus-sizing
Big Endian/Little Endian user selectable byte representation
3.3V power supply
5V input tolerant on all control and data input pins
5V output tolerant on all flags and data output pins
Master Reset clears all previously programmed configurations including Write and Read pointers
Partial Reset clears Write and Read pointers but maintains all previously programmed configurations
First Word Fall Through (FWFT) and Standard Timing modes
Presets for eight different Almost Full and Almost Empty offset values
Parallel/Serial programming of PRAF and PRAE offset values
Programmable 8-bit or 9-bit parallel programming modes for offset values
Full, Empty, Almost Full, Almost Empty, and Half Full indicators
PRAF and PRAE operates in either synchronous or asynchronous modes
Asynchronous output enable tri-state data output drivers
Data retransmission with programmable zero or normal latency modes
Available package: 80 - pin Plastic Thin Quad Flat Pack (TQFP)
(0°C to 70°C) Commercial operating temperature available for cycle time of 6.0ns and above
(-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above
Product Description
HBA’s FlexQ™ III offers industry leading FIFO queuing bandwidth (up to 3.0 Gbps), with a wide range of memory
configurations (from 2,048 x 18 to 262,144 x 18 or 4,096 x 9 to 524,286 x 9). System designer has full flexibility of
implementing deeper and wider queues using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators
allow easy handshaking between transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial)
indicators allow implementation of virtual queue depths.
5V tolerant on all input and output pins allows easy interfacing with devices operating at higher voltage levels. Asynchronous
Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching
capability.
Master Reset clears all previously programmed configurations by providing a low pulse on MRST pin. In addition, Write and
Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will
initialize Write and Read pointers to zero.
In FWFT mode, the first data written into the queue appears on output data bus after the specified latency period at the low to
high transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when
implementing depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and
EMPTY respectively.
3F30918C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JANUARY 2003
Page 1 of 43
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FlexQTMIII
Product Description (Continued)
In Standard mode, always assert REN whenever a read operation. FULL and EMPTY are used instead of DRDY and
QRDY respectively.
Bus matching feature is available with the following configurations:
Input Bus Width
x9
x9
x18
x18
Output Bus Width
x9
x18
x9
x18
In addition, Endian Select is available for implementing byte re-ordering on data outputs.
Eight different default offset values are available for Almost Full ( PRAF ) and Almost Empty ( PRAE ) flags. Parallel and Serial
programming of these offset values provide total flexibility other than the pre-defined default values. Both 8-bit and 9-bit
parallel programming modes for offset values can be selected for convenience.
PRAF , PRAE , and HALF are available in either FWFT or Standard mode. PRAF and PRAE can operate in either
synchronous or asynchronous modes.
At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of
RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the
physical 0th (Read pointer = zero) location of the queue. Both zero and normal latency timing modes are available for retransmit
operation.
These FlexQ™ III devices have low power consumption, hence minimizing system power requirements. In addition, industry
standard 80 - pin Plastic TQFP is offered to save system board space.
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test
equipment, network switching, etc.
.
3F30918C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JANUARY 2003
Page 2 of 43
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
Block Diagram of Single Synchronous Queue
262,144 x 18 / 131,072 x 18 / 65,536 x 18 / 32,768 x 18 / 16,384 x 18 / 8,192 x 18 / 4,096 x 18 / 2,048 x 18 /
524,288 x 9 / 262,144 x 9 / 131,072 X 9 / 65,536 X 9 / 32,768 X 9 / 16,384 X 9 / 8,192 x 9 / 4,096 x 9
PARTIAL RESET ( PRST )
MASTER RESET ( MRST)
READ CLOCK (RCLK)
WRTIE CLOCK (WCLK)
READ ENABLE ( REN )
WRITE ENABLE ( WEN)
OUTPUT ENABLE ( OE )
LOAD ( LOAD)
x18 or x9 DATA IN (D 17 - 0)
SERIAL DATA ENABLE
( SDEN )
FIRST WORD FALL THROUGH/
SERIAL DATA INPUT (FWFT/SDI)
FULL FLAG / INPUT READY
( FULL / DRDY )
PROGRAMMABLE
ALMOST-FULL (PRAF)
FQV2113
FQV2103
FQV293
FQV283
FQV273
FQV263
FQV253
FQV243
x18 or x9 DATA OUT (Q 17 - 0)
RETRANSMIT ( RET)
EMPTY FLAG / OUTPUT READY
(EMPTY / QRDY )
PROGRAMMABLE ALMOSTEMPTY ( PRAE )
HALF-FULL FLAG ( HALF )
BIG-ENDIAN / LITTLE-ENDIAN ( ES )
INTERSPERSED /
NON-INTERSPERSED PARITY (IPAR)
BUS MATCHING 1
(BM1)
BUS MATCHING 0
(BM0)
Figure 1. Single Device Configuration Signal Flow Diagram
3F30918C
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JANUARY 2003
Page 3 of 43
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FlexQTMIII
WCLK
IPAR
WEN
LOAD SDEN FWFT/SDI
FULL / DRDY
Write Control
Logic
PRAF
EMPTY/ QRDY
PRAE
Offset Register
Flag Logic
HALF
FWFT/SDI
SFM
Write Pointer
PFS1
PFS0
D 17-0 x18, x9
Input Register
SRAM
Output Register
Output
Buffer
Q 17-0 x18, x9
OE
Read Pointer
Read Control
Logic
RETZL RET RCLK REN
Reset
MRST PRST
Bus
Configuration
ES
BM1 BM0
Figure 2. Device Architecture
3F30918C
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JANUARY 2003
Page 4 of 43
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RETZL
RCLK
REN
63
62
61
IPAR
68
SFM
ES
69
EMPTY/QRDY
PFS1
70
64
HALF
71
PRAE
PFS0
72
65
BM0
73
66
PRAF
74
Vcc
FWFT/SDI
FULL/DRDY
75
LOAD
77
76
PRST
MRST
78
WCLK
79
80
FlexQTMIII
67
Index
WEN
01
60
RET
SDEN
02
59
OE
1
03
58
Vcc
DNC
Vcc
04
57
Q17
DNC1
05
56
Q16
BM1
06
55
GND
GND
07
54
GND
D17
08
53
Q15
Vcc
09
52
Q14
D16
10
51
Vcc
D15
11
50
Q13
D14
12
49
Q12
D13
13
48
GND
GND
14
47
Q11
D12
15
46
GND
D11
16
45
Q10
D10
17
44
Vcc
38
39
40
Q5
GND
Q6
34
Q2
37
33
GND
Q4
32
Q1
36
31
Q0
35
30
GND
Q3
29
D0
Vcc
28
27
D2
D1
26
25
D3
D4
Q7
24
41
D5
20
23
Vcc
GND
Q8
22
42
21
43
19
D6
18
D8
D7
D9
Q9
TQFP - 80 (Drw No: PF-01A; Order code: PF)
Top View
NOTES:
1.
DNC = Do Not Connect.
Figure 3. Device Pin Out
3F30918C
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JANUARY 2003
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FlexQTMIII
Pin #
78
Pin Name
Master Reset
Pin Symbol
MRST
Input/Output
Description
Input
Master Reset is required to initialize Write and Read
pointers to the first position of the queue by setting
MRST low. In Standard mode, FULL and PRAF will
go high; EMPTY and PRAE will go low. In FWFT
mode, DRDY will go low and QRDY will go high.
PRAF and PRAE will go to the same state as Standard
mode. In both modes, all data outputs will go low.
Previous programmed configurations will not be
maintained.
79
Partial Reset
PRST
Input
Partial Reset is required to initialize Write and Read
pointers to the first position of the queue by setting
PRST low. In Standard mode, FULL and PRAF will
go high; EMPTY and PRAE will go low. In FWFT
mode, DRDY will go low and QRDY will go high.
PRAF and PRAE will go to the same state as Standard
mode. In both modes, all data outputs will go low.
Previous programmed configurations will be
maintained.
80
Write Clock
WCLK
Input
Writes data into queue during low to high transitions of
WCLK if WEN is set to low.
01
Write Enable
WEN
Input
Controls write operation into queue or offset registers
during low to high transition of WCLK.
77
Load Enable
LOAD
Input
During Master Reset, set LOAD low to select parallel
programming and one of eight default-offset values.
Set LOAD high to select serial programming and one
of eight default offset values. After Master Reset,
LOAD controls write/read, to/from offset registers
during low to high transition of WCLK/RCLK
respectively. Use in conjunction with WEN / REN .
70
Default
Programming 1
PFS1
Input
During Master Reset, select one of eight default-offset
values. Use in conjunction with LOAD and PFS0.
72
Default
Programming 0
PFS0
Input
During Master Reset, select one of eight default-offset
values. Use in conjunction with LOAD and PFS1.
08,10,11,
12,13,15,
16,17,18
19,21,22,
24,25,26,
27,28,29
Data Inputs
D17-0
Input
18 - bit wide input data bus.
62
Read Clock
RCLK
Input
Reads data from queue during low to high transitions of
RCLK if REN is set to low.
61
Read Enable
REN
Input
Controls read operation from queue or offset registers
during low to high transition of RCLK.
59
Output Enable
OE
Input
Setting OE low activates the data output drivers.
Setting OE high deactivates the data output drivers
(High-Z).
Table 1. Pin Descriptions
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
Pin #
Pin Name
Pin Symbol
Input/Output
57,56,53,
52,50,49,
47,45,43,
42,41,40,
38,37,35,
34,32,31
Data Outputs
Q17-0
Output
Description
18 - bit wide output data bus.
Input
Selects FWFT timing or Standard timing mode during
Master Reset. After Master Reset, if serial
programming is selected ( LOAD = high), FWFT/SDI
is used as the serial data input for the offset registers.
Serial data is written during the low to high transition
of WCLK. Use in conjunction with SDEN .
SDEN
Input
If serial programming is selected, setting SDEN low
and LOAD low enables serial data input to be written
into offset registers during the low to high transition of
WCLK.
Bus Matching
1
BM1
Input
During Master Reset, set BM1 low to select x18 input
bus width or BM1 high to select x9 input bus width.
73
Bus Matching
0
BM0
Input
During Master Reset, set BM0 low to select x18
output bus width or BM0 high to select x9 output bus
width.
69
Endian Select
ES
Input
During Master Reset, set ES high to select byte reordering on data outputs or ES low to select no byte
re-ordering on data outputs.
76
First Word Fall
Through/Serial
Data Input
02
Serial Data
Input Enable
06
FWFT/SDI
60
Retransmit
RET
Input
Data previously read from the queue can be
retransmitted by asserting RET pin at the low to high
transition of RCLK for a retransmit operation.
Retransmit initializes the Read pointer to zero. Hence,
all re-reads will always start from the physical 0th
(Read pointer = zero) location of the queue.
63
Zero Latency
Retransmit
RETZL
Input
During Master Reset, set RETZL low to select zero
latency retransmit or RETZL high to select normal
latency retransmit.
75
Full/Data Input
Ready Flag
FULL / DRDY
Output
Queue is full when FULL goes low during the low to
high transition of WCLK. This prohibits further
writes into the queue. In FWFT mode, queue is full
when DRDY goes high during low to high transition
of WCLK. This prohibits further writes into the
queue.
64
Empty/Data
Output Ready
Flag
EMPTY / QRDY
Output
Queue is empty when EMPTY goes low during the
low to high transition of RCLK. This prohibits further
reads from the queue. In FWFT mode, queue is empty
when QRDY goes high during the low to high
transition of RCLK. This prohibits further reads from
the queue.
68
Interspersed
Parity
IPAR
Input
During Master Reset, set IPAR low to select 9-bit
parallel programming mode or IPAR high to select 8bit parallel programming mode.
Table 1. Pin Descriptions (Continued)
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
Description
Pin #
Pin Name
Pin Symbol
Input/Output
65
Synchronous
Partial Flag Mode
SFM
Input
During Master Reset, set SFM high to select
Synchronous Partial Flag mode or SFM low to select
Asynchronous Partial Flag mode.
Output
Queue is almost full when PRAF goes low during the
low to high transition of WCLK. Default (Full-offset)
or programmed offset values determine the status of
PRAF .
74
Almost Full
PRAF
66
Almost Empty
PRAE
Output
Queue is almost empty when PRAE goes low during
the low to high transition of RCLK. Default (Empty
+offset) or programmed offset values determine the
status of PRAE .
71
Half Full
HALF
Output
Queue is more than half full when HALF goes low.
Triggered by both WCLK and RCLK.
03, 05
Do Not Connect
DNC
N/A
Do not connect.
04,09,20
36,44,51,
58,67
Power
VCC
N/A
3.3V power supply.
07,14,23,
30,33,39,
46,48,54,55,
Ground
GND
N/A
0V Ground.
Table 1. Pin Descriptions (Continued)
3F30918C
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JANUARY 2003
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FlexQTMIII
Symbol
Com’l & Ind’l
Unit
Terminal Voltage with
respect to GND
-0.5 to + 4.5
V
TSTG
Storage Temperature
-55 to +125
IOUT
DC Output Current
-50 to +50
VTERM
Rating
NOTES:
Absolute Max Ratings are for reference only. Permanent damage to the device may
occur if extended period of operation is outside this range. Standard operation should
fall within the Recommended Operating Conditions.
°
C
mA
Table 2. Absolute Maximum Ratings
FQV2113, FQV2103FQV293, FQV283
FQV273, FQV263, FQV253, FQV243
Commercial
Clock = 6ns, 7.5ns, 10ns,
15ns
Industrial
Clock = 7.5ns, 10ns, 15ns
Symbol
Parameter
Recommended Operating Conditions
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Vcc
Supply Voltage Com’l / Ind’l
3.15
3.3
3.45
3.15
3.3
3.45
V
GND
Supply Voltage
0
0
0
0
0
0
V
VIH
Input High Voltage Com’l /
Ind’l
2.0
-
5.5
2.0
-
5.5
V
VIL
Input Low Voltage Com’l /
Ind’l
-
-
0.8
-
-
0.8
V
TA
Operating Temperature
Commercial
0
-
70
0
-
70
°
TA
Operating Temperature
Industrial
-40
-
85
-40
-
85
°
C
C
DC Electrical Characteristics
ILI(1)
Input Leakage Current (any
input)
-1
-
1
-1
-
1
µA
ILO
Output Leakage Current
-10
-
10
-10
-
10
µA
VOH
Output Logic “1” Voltage,
IOH=-2mA
2.4
-
-
2.4
-
-
V
VOL
Output Logic “0” Voltage, IOL
= 8mA
-
-
0.4
-
-
0.4
V
ICC1(2,3)
Active Power Supply Current
(x9 Input to x9 Output)
-
-
30
-
-
30
mA
ICC1(2,3)
Active Power Supply Current
(x18 Input to x18 Output)
-
-
35
-
-
35
mA
ICC2(4)
Standby Current
-
-
15
-
-
15
mA
Power Consumption
Table 3. DC Specifications
3F30918C
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JANUARY 2003
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FlexQTMIII
Capacitance at 1.0MHz Ambient Temperature (25°C)
Symbol
Parameter
CIN(2)
Input Capacitance
COUT(2,4)
Output Capacitance
Conditions
Max.
Unit
VIN= 0V
10
pF
VOUT= 0V
10
pF
NOTES:
1.
2.
3.
4.
Measurement with 0.4<=VIN<=Vcc.
With output tri-stated ( OE = High).
Icc(1,2) is measured with WCLK and RCLK at 20 MHz.
Design simulated, not tested.
Table 3. DC Specifications (Continued)
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
Commercial
FQV2113-6
FQV2103-6
FQV293-6
FQV283-6
FQV273-6
FQV263-6
FQV253-6
FQV243-6
Symbol
Parameter
Commercial & Industrial
FQV2113-7.5
FQV2103-7.5
FQV293-7.5
FQV283-7.5
FQV273-7.5
FQV263-7.5
FQV253-7.5
FQV243-7.5
FQV2113-10
FQV2103-10
FQV293-10
FQV283-10
FQV273-10
FQV263-10
FQV253-10
FQV243-10
FQV2113-15
FQV2103-15
FQV293-15
FQV283-15
FQV273-15
FQV263-15
FQV253-15
FQV243-15
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
-
166
-
133
-
100
-
66
MHz
tA
Data Access Time
1
4
2
5
2
6.5
2
10
ns
tWCLK
Write Clock Cycle Time
6
-
7.5
-
10
-
15
-
ns
tWCLKH
Write Clock High Time
2.5
-
3.5
-
4.5
-
6
-
ns
tWCLKL
Write Clock Low Time
2.5
-
3.5
-
4.5
-
6
-
ns
tRCLK
Read Clock Cycle Time
6
-
7.5
-
10
-
15
-
ns
tRCLKH
Read Clock High Time
2.5
-
3.5
-
4.5
-
6
-
ns
tRCLKL
Read Clock Low Time
2.5
-
3.5
-
4.5
-
6
-
ns
tDS
Data Set-up Time
2.0
-
2.5
-
3.5
-
4
-
ns
tDH
Data Hold Time
0.5
-
0.5
-
0.5
-
1
-
ns
tENS
Enable Set-up Time
2.0
-
2.5
-
3.5
-
4
-
ns
tENH
Enable Hold Time
0.5
-
0.5
-
0.5
-
1
-
ns
tRST
Reset Pulse Width(1)
8
-
10
-
10
-
15
-
ns
tRSTS
Reset Set-up Time
10
-
15
15
-
15
-
ns
tRSTR
Reset Recovery Time
10
-
10
-
10
-
15
-
ns
tRSTF
Reset to Flag and Output Time
-
10
-
15
-
15
-
15
ns
tOLZ
Output Enable to Output in Low-Z(1)
0
-
0
-
0
-
0
-
ns
tOE
Output Enable to Output Valid
2
4
2
6
2
6
2
8
ns
(1)
tOHZ
Output Enable to Output in High-Z
2
4
2
6
2
6
2
8
ns
tFULL
Write Clock to Full Flag
-
4
-
5
-
6.5
-
10
ns
tEMPTY
Read Clock to Empty Flag
-
4
-
5
-
6.5
-
10
ns
tPRAFS
Write Clock to Synchronous Almost-Full Flag
-
4
-
5
-
6.5
-
10
ns
tPRAES
Read Clock to Synchronous Almost-Empty
Flag
-
4
-
5
-
6.5
-
10
ns
tSKEW1
Skew time between Read Clock & Write Clock
for Full Flag / Empty Flag
4
-
5
-
7
-
9
-
ns
tSKEW2
Skew time between Read Clock & Write Clock
for PRAE & PRAF
6
-
7
-
10
-
14
-
ns
tLOADS
Load Setup Time
2
-
2.5
-
3.5
-
4
-
ns
tLOADH
Load Hold Time
0.5
-
0.5
-
0.5
-
1
-
ns
Table 4. AC Electrical Characteristics
3F30918C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
Commercial
FQV2113-6
FQV2103-6
FQV293-6
FQV283-6
FQV273-6
FQV263-6
FQV253-6
FQV243-6
Symbol
Parameter
Commercial & Industrial
FQV2113-7.5
FQV2103-7.5
FQV293-7.5
FQV283-7.5
FQV273-7.5
FQV263-7.5
FQV253-7.5
FQV243-7.5
FQV2113-10
FQV2103-10
FQV293-10
FQV283-10
FQV273-10
FQV263-10
FQV253-10
FQV243-10
FQV2113-15
FQV2103-15
FQV293-15
FQV283-15
FQV273-15
FQV263-15
FQV253-15
FQV243-15
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tRETS
Retransmit Setup Time
3
-
3.5
-
3.5
-
4
-
ns
tHALF
Clock to HALF
-
12
-
12.5
-
16
-
20
ns
tPRAFA
Write Clock to Asynchronous
Programmable Almost-Full Flag
-
12
-
12.5
-
16
-
20
ns
tPRAEA
Read Clock to Asynchronous
Programmable Almost-Empty Flag
-
12
-
12.5
-
16
-
20
ns
NOTES:
1.
Design simulated, not tested.
Table 4. AC Electrical Characteristics (Continued)
3F30918C
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JANUARY 2003
Page 12 of 43
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load, clock = 6ns, 7.5ns
Refer to Figure 4 & 6
*
Output Load , clock = 10ns, 15 ns
Refer to Figure 5
* Include jig and scope capacitances
Table 5. AC Test Condition
3.3V
Vcc/2
330 Ω
50 Ω
D.U.T.
30pF*
I/O
510 Ω
Z0 = 50 Ω
Figure 5. Output Load
for clock = 10ns, 15ns
*Includes jig and scope capacitances.
Figure 4. AC Test Load
for clock = 6ns, 7.5ns
tCD (Typical, ns)
4
3
2
1
20 30
50
80
100
200
Capacitance (pF)
Figure 6. Lumped Capacitive Load
3F30918C
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JANUARY 2003
Page 13 of 43
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
Pin Functions
MRST
Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting
MRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In
FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state
as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will
not be maintained.
PRST
Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting
PRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In
FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state
as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will
be maintained.
WCLK
Writes data into queue during low to high transitions of WCLK if WEN is activated. Synchronizes
FULL / DRDY and PRAF flags. WCLK and RCLK are independent of each other.
WEN
Controls write operation into queue or offset registers during low to high transition of WCLK.
LOAD
During Master Reset, set LOAD low to select parallel programming and one of eight default offset
values. Set LOAD high to select serial programming and one of eight default offset values. After Master
Reset, LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK
respectively for parallel programming. Use in conjunction with WEN / REN . During programming of
offset registers, PRAF and PRAE flag status are invalid. For Serial programming, LOAD is used to
enable serial loading of offset registers together with SDEN . Refer to Figure 7 & Table 11 for details.
PFS1
During Master Reset, select one of eight default-offset values. Use in conjunction with LOAD
and PFS0. Refer to Table 11 for details.
PFS0
During Master Reset, select one of eight default-offset values. Use in conjunction with LOAD and
PFS1. Refer to Table 11 for details.
D17-0
18 - bit wide input data bus.
RCLK
Reads data from queue during low to high transitions of RCLK if REN is set low. Synchronizes the
EMPTY / QRDY and PRAE flags. RCLK and WCLK are independent of each other.
REN
Reads data from queue or offset registers during low to high transitions of RCLK if REN is set low. This
also advances the Read pointer of the queue.
OE
Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers
(High-Z). OE does not control advancement of Read pointer.
Q17-0
18 - bit wide output data bus.
FWFT/SDI
Selects FWFT timing or Standard timing mode during Master Reset. After Master Reset, if serial
programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for the offset
registers. Serial data is written during the low to high transition of WCLK. Use in conjunction with
SDEN . In FWFT mode, DRDY and QRDY is used instead of FULL and EMPTY . Refer to Table 9
for all flags status. In Standard mode, FULL and EMPTY are used instead of DRDY and QRDY .
Refer to Table 8 for all flags status.
SDEN
If serial programming is selected, setting SDEN low and LOAD low enables serial data to be written into
offset registers during the low to high transition of WCLK. During serial programming, PRAF and
PRAE flags status are invalid. Refer to Figure 7 for details.
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
Pin Functions (Continued)
BM1
During Master Reset, setting BM1 low selects x18 input bus width. Set BM1 high selects x9 input bus
width. Refer to Table 10 for details.
BM0
During Master Reset, set BM0 low to select x18 output bus width. Set BM0 high to select x9 output
bus width. Refer to Table 10 for details.
ES
During Master Reset, Set ES high to select byte re-ordering on data outputs or set ES low to select no
byte re-ordering on data outputs. ES must be static throughout device operation. Refer to Table 10 for
details.
RET
Data previously read from the queue can be retransmitted by asserting RET pin at the low to high
transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence,
all re-reads will always start from the physical 0th (Read pointer = zero), location of the queue. Refer to
Diagram 7 & 8 for details.
RETZL
During Master Reset, set RETZL low to select zero latency retransmit or set RETZL high to select
normal latency retransmit.
FULL / DRDY
In Standard mode, queue is full when FULL goes low during the low to high transition of WCLK. This
prohibits further writes into the queue and prevents advancement of Write pointer. In FWFT mode,
queue is full when DRDY goes high during the low to high transition of WCLK. This prohibits further
writes into the queue and prevents advancement of Write pointer. Refer to Table 8 & 9 for behavior of
FULL / DRDY .
EMPTY / QRDY
In Standard mode, queue is empty when EMPTY goes low during the low to high transition of RCLK.
This prohibits further reads from the queue and prevents advancement of Read pointer. In FWFT mode,
queue is empty when QRDY goes high during the low to high transition of RCLK. This prohibits
further reads from the queue and prevents advancement of Read pointer. Refer to Table 8 & 9 for
behavior of EMPTY / QRDY .
IPAR
During Master Reset, set IPAR low to select 9-bit parallel programming mode or set IPAR high to
select 8-bit parallel programming mode. In 9-bit mode, 9-bit wide data input/output bus width is used
for storing/fetching offset values. In 8-bit mode, 8-bit wide data input/output bus is used for
storing/fetching offset values.
SFM
During Master Reset, set SFM high to select Synchronous Partial Flag mode or set SFM low to select
Asynchronous Partial Flag mode. In Synchronous mode, PRAF and PRAE are synchronous to WCLK
and RCLK respectively. In Asynchronous mode, WCLK synchronizes the assertion of PRAF and deassertion of PRAE . RCLK synchronizes the assertion of PRAE and de-assertion of PRAF .
PRAF
In Synchronous mode, queue is almost full when PRAF goes low during the low to high transition of
WCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . In
Asynchronous mode, PRAF is triggered by both WCLK and RCLK. Refer to Table 8 & 9 for behavior
of PRAF .
PRAE
In Synchronous mode, queue is almost empty when PRAE goes low during the low to high transition of
RCLK. Default (Empty+offset) or programmed offset values determine the status of PRAE . In
Asynchronous timing mode, PRAE is triggered by both WCLK and RCLK. Refer to Table 8 & 9 for
behavior of PRAE .
HALF
Queue is more than half full when HALF goes low during the low to high transition of WCLK.
HALF goes high during low to high transition of RCLK when queue is less than half full. Refer to
Table 8 & 9 for details.
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
LOAD
0
0
WEN
0
1
REN
1
0
SDEN
WCLK
1
1
RCLK
X
X
0
1
1
0
X
1
1
1
1
0
X
X
1
X
0
X
X
1
1
1
X
X
X
FQV283
FQV273
FQV263
FQV253
FQV243
Selection / Sequence
Parallel write to offset
registers:
Empty Offset (Low Byte)
Empty Offset (High Byte)
Full Offset (Low Byte)
Full Offset (High Byte)
Parallel write to
registers:
1. PRAE Low Byte
2. PRAE High Byte
3. PRAF Low Byte
4. PRAF High Byte
Parallel read from offset
registers:
Empty Offset (Low Byte)
Empty Offset (High Byte)
Full Offset (Low Byte)
Full Offset (High Byte)
Parallel read from
registers:
1. PRAE Low Byte
2. PRAE High Byte
3. PRAF Low Byte
4. PRAF High Byte
X
x9 to x9 Mode
Serial shift into registers:
32 bits for the FQV283
30 bits for the FQV273
28 bits for the FQV263
26 bits for the FQV253
24 bits for the FQV243
1 bit for each rising WCLK
edge
Starting with Empty Offset
(Low Byte)
Ending with Full Offset
(High Byte)
X
No Operation
X
Write Memory
All Other Modes
Serial shift into registers:
30 bits for the FQV283
28 bits for the FQV273
26 bits for the FQV263
24 bits for the FQV253
22 bits for the FQV243
1 bit for each rising WCLK
edge
Starting with Empty Offset
(Low Byte)
Ending with Full Offset
(High Byte)
Read Memory
X
No Operation
Figure 7. Programmable Flag Offset Programming Sequence (FQV283, FQV273, FQV263, FQV253 and FQV243)
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
LOAD
0
0
WEN
0
1
REN
1
0
SDEN
WCLK
1
1
RCLK
X
X
0
1
1
0
X
1
1
1
1
0
X
X
1
X
0
X
X
1
1
1
X
X
X
FQV2113
FQV2103
FQV293
Selection / Sequence
Parallel write to offset
registers:
Empty Offset (Low Byte)
Empty Offset (Mid Byte)
Empty Offset (High Byte)
Full Offset (Low Byte)
Full Offset (Mid Byte)
Full Offset (High Byte)
Parallel write to
registers:
1. PRAE Low Byte
2. PRAE Mid Byte
3. PRAE High Byte
4. PRAF Low Byte
5. PRAF Mid Byte
6. PRAF High Byte
Parallel read from offset
registers:
Empty Offset (Low Byte)
Empty Offset (Mid Byte)
Empty Offset (High Byte)
Full Offset (Low Byte)
Full Offset (Mid Byte)
Full Offset (High Byte)
Parallel read from
registers:
1. PRAE Low Byte
2. PRAE Mid Byte
3. PRAE High Byte
4. PRAF Low Byte
5. PRAF Mid Byte
6. PRAF High Byte
X
x9 to x9 Mode
Serial shift into registers:
38 bits for the FQV2113
36 bits for the FQV2103
34 bits for the FQV293
1 bit for each rising WCLK
edge
Starting with Empty Offset
(Low Byte)
Ending with Full Offset
(High Byte)
X
No Operation
X
Write Memory
All Other Modes
Serial shift into registers:
36 bits for the FQV2113
34 bits for the FQV2103
32 bits for the FQV293
1 bit for each rising WCLK
edge
Starting with Empty Offset
(Low Byte)
Ending with Full Offset
(High Byte)
Read Memory
X
No Operation
Figure 8. Programmable Flag Offset Programming Sequence (FQV2113, FQV2103, FQV293)
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
Device
FQV2113
FQV2103
FQV293
FQV283
FQV273
FQV263
FQV253
FQV243
PRAF Programming (bits)
PRAE Programming (bits)
D/Q15 - 0
Non-IPAR
D/Q15 - 0
Non-IPAR
D/Q16 – 9 & D/Q7 – 0
IPAR
D/Q16 – 9 & D/Q7 – 0
IPAR
D/Q15 - 0
Non-IPAR
D/Q15 - 0
Non-IPAR
D/Q16 – 9 & D/Q7 – 0
IPAR
D/Q16 – 9 & D/Q7 – 0
IPAR
D/Q15 - 0
Non-IPAR
D/Q15 - 0
Non-IPAR
D/Q16 – 9 & D/Q7 – 0
IPAR
D/Q16 – 9 & D/Q7 – 0
IPAR
D/Q14 - 0
Non-IPAR
D/Q14 - 0
Non-IPAR
D/Q15 – 9 & D/Q7 – 0
IPAR
D/Q15 – 9 & D/Q7 – 0
IPAR
D/Q13 - 0
Non-IPAR
D/Q13 - 0
Non-IPAR
D/Q14 – 9 & D/Q7 – 0
IPAR
D/Q14 – 9 & D/Q7 – 0
IPAR
D/Q12 - 0
Non-IPAR
D/Q12 - 0
Non-IPAR
D/Q13 – 9 & D/Q7 – 0
IPAR
D/Q13 – 9 & D/Q7 – 0
IPAR
D/Q11 - 0
Non-IPAR
D/Q11 - 0
Non-IPAR
D/Q12 – 9 & D/Q7 – 0
IPAR
D/Q12 – 9 & D/Q7 – 0
IPAR
D/Q10 - 0
Non-IPAR
D/Q10 - 0
Non-IPAR
IPAR
D/Q11 – 9 & D/Q7 – 0
IPAR
D/Q11 – 9 & D/Q7 – 0
Condition Applies to: Write Cycle with x18 input Bus Width and/or
Read Cycle with x18 output Bus Width
Device
PRAF Programming (bits)
D/Q7 - 0
FQV2113
FQV2103
FQV293
FQV283
FQV273
FQV263
FQV253
FQV243
PRAE Programming (bits)
Low Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Mid Byte
D/Q7 - 0
Mid Byte
D/Q1 - 0
High Byte
D/Q1 - 0
High Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Mid Byte
D/Q7 - 0
Mid Byte
D/Q0
High Byte
D/Q 0
High Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
High Byte
D/Q7 - 0
High Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Low Byte
D/Q6 - 0
High Byte
D/Q6 - 0
High Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Low Byte
D/Q5 - 0
High Byte
D/Q5 - 0
High Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Low Byte
D/Q4 - 0
High Byte
D/Q4 - 0
High Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Low Byte
D/Q3 - 0
High Byte
D/Q3 - 0
High Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Low Byte
D/Q2 - 0
High Byte
D/Q2 - 0
High Byte
Condition Applies to: Write Cycle with x9 input Bus Width or
Read Cycle with x9 output Bus Width (except x9 to x9 mode)
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
Device
PRAF Programming (bits)
D/Q7 - 0
FQV2113
FQV2103
FQV293
FQV283
FQV273
FQV263
FQV253
FQV243
PRAE Programming (bits)
Low Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Mid Byte
D/Q7 - 0
Mid Byte
D/Q2 - 0
High Byte
D/Q2 - 0
High Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Mid Byte
D/Q7 - 0
Mid Byte
D/Q1 - 0
High Byte
D/Q1 - 0
High Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Mid Byte
D/Q7 - 0
Mid Byte
D/Q0
High Byte
D/Q0
High Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
High Byte
D/Q7 - 0
High Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Low Byte
D/Q6 - 0
High Byte
D/Q6 - 0
High Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Low Byte
D/Q5 - 0
High Byte
D/Q5 - 0
High Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Low Byte
D/Q4 - 0
High Byte
D/Q4 - 0
High Byte
D/Q7 - 0
Low Byte
D/Q7 - 0
Low Byte
D/Q3 - 0
High Byte
D/Q3 - 0
High Byte
Condition Applies to: Write Cycle with x9 input Bus Width and
Read Cycle with x9 output Bus Width (only x9 to x9 mode)
Table 6. Parallel Offset Write/Read Cycle Register Location
Device
Standard Mode
FQV2113
262,144 x 18 / 524,288 x9
262,145 x 18 / 524,289 x9
FWFT Mode
FQV2103
131,072 x 18 / 262,144 x9
131,073 x 18 / 262,145 x 9
FQV293
65,536 x 18 / 131,072 x 9
65,537,x 18 / 131,073 x 9
FQV283
32,768 x 18 / 65,536 x 9
32,769 x 18 / 65,537 x 9
FQV273
16,384 x 18 / 32,768 x 9
16,385 x 18 / 32,769 x 9
FQV263
8,192 x 18 / 16,384 x 9
8,193 x 18 / 16,385 x 9
FQV253
4,096 x 18 / 8,192 x 9
4,097 x 18 / 8,193 x 9
FQV243
2,048 x 18 / 4,096 x 9
2,049 x 18 / 4,097 x 9
Table 7. Maximum Depth of Queue for Standard and FWFT Mode
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
Data Width
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
1st Cycle PRAE Low Byte
7
66
55
4
37
2
17
0
2nd Cycle PRAE High Byte
15
14
13
12
11
10
9
8
3rd Cycle PRAF Low Byte
7
66
55
4
37
2
17
0
4th Cycle PRAF High Byte
15
14
13
12
11
10
9
8
FQV293, FQV283, FQV273, FQV263, FQV253, FQV243
Parallel Offset Write/Read Cycles for x9 Bus Width
Condtion Applies to: Write Cycle with x9 input Bus Width
and/or Read Cycle output with x9 Bus Width
(except FQV293 x9 to x9 mode)
Data Width
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
1st Cycle PRAE Low Byte
77
66
55
4
37
2
17
0
2nd Cycle PRAE Mid Byte
15
14
13
12
11
10
9
8
18
17
16
3rd Cycle PRAE High Byte
4th Cycle PRAF Low Byte
77
66
55
4
37
2
17
0
5th Cycle PRAF Mid Byte
15
14
13
12
11
10
9
8
18
17
16
6th Cycle PRAF High Byte
FQV2113, FQV2103, FQV293
Parallel Offset Write/Read Cycles for x9 Bus Width
Condtion Applies to: FQV293 x9 to x9 mode or
FQV2113, FQV2103 for all modes
x9 to x9 Mode
All Other Modes
# of Bits for Offset Registers
# of Bits for Offset Registers
19 bits for FQV2113
18 bits for FQV2103
17 bits for FQV293
16 bits for FQV283
15 bits for FQV273
14 bits for FQV263
13 bits for FQV253
12 bits for FQV243
18 bits for FQV2113
17 bits for FQV2103
16 bits for FQV293
15 bits for FQV283
14 bits for FQV273
13 bits for FQV263
12 bits for FQV253
11 bits for FQV243
Note: Don’t Care applies to all unused bits
Note: Don’t Care applies to all unused bits
Figure 9. Parallel Offset Write/Read Cycle Diagram
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
Data Width
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10
D/Q9
D/Q8
D/Q7
D/Q6
D/Q5
D/Q4
D/Q3
D/Q2
D/Q1
D/Q0
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1st Cycle PRAE
Non-Interspersed Parity
Interspersed Parity
Data Width
15
15
14
13
12
11
10
9
14
13
12
11
10
9
8
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10
D/Q9
D/Q8
D/Q7
D/Q6
D/Q5
D/Q4
D/Q3
D/Q2
D/Q1
D/Q0
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
2nd Cycle PRAF
Non-Interspersed Parity
Interspersed Parity
15
15
14
13
12
11
10
9
14
13
12
11
10
9
8
FQV293, FQV283, FQV273, FQV263, FQV253, FQV243
Parallel Offset Write/Read Cycles for x18 Bus Width
Condtion Applies to: Write Cycle with x18 input Bus Width
and/or Read Cycle for x18 output Bus Width
Data Width
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10
D/Q9
D/Q8
D/Q7
D/Q6
D/Q5
D/Q4
D/Q3
D/Q2
D/Q1
D/Q0
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Non-Interspersed Parity
17
16
Interspersed Parity
17
16
1st Cycle PRAE
Non-Interspersed Parity
Interspersed Parity
15
15
14
13
12
11
10
9
14
13
12
11
10
9
8
2nd Cycle PRAE
3rd Cycle PRAF
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Non-Interspersed Parity
17
16
Interspersed Parity
17
16
Non-Interspersed Parity
Interspersed Parity
15
15
14
13
12
11
10
9
14
13
12
11
10
9
8
8
4th Cycle PRAF
FQV2113, FQV2103
Parallel Offset Write/Read Cycles for x18 Bus Width
Condtion Applies to: Write Cycle with x18 input Bus Width
and/or Read Cycle for x18 output Bus Width
Figure 9. Parallel Offset Write/Read Cycles Diagram (Continued)
3F30918C
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JANUARY 2003
Page 21 of 43
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
FQV2113
BM1 = BM0 = x9
0
1 to y(1)
(y+1) to 262,144
262,145 to [524,288-(x+1)]
(524,288 -x(1)) to 524,287
524,288
FQV2103
FULL
PRAF
HALF
PRAE
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
FULL
PRAF
HALF
PRAE
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
FULL
PRAF
HALF
PRAE
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
FULL
PRAF
HALF
PRAE
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
FULL
PRAF
HALF
PRAE
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
EMPTY
L
H
H
H
H
H
FQV2113
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y
(y+1) to 131,072
131,073 to [262,144-(x+1)]
(262,144 -x) to 262,143
262,144
BM1 = BM0 = x9
FQV293
EMPTY
L
H
H
H
H
H
FQV2103
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y
(y+1) to 65,536
65,537 to [131,072-(x+1)]
(131,072 -x) to 131,071
131,072
BM1 = BM0 = x9
FQV283
EMPTY
L
H
H
H
H
H
FQV293
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y
(y+1) to 32,768
32,769 to [65,536-(x+1)]
(65,536 -x) to 65,535
65,536
BM1 = BM0 = x9
FQV273
EMPTY
L
H
H
H
H
H
FQV283
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y
(y+1) to 16,384
16,385 to [32,768-(x+1)]
(32,768 -x) to 32,767
32,768
BM1 = BM0 = x9
EMPTY
L
H
H
H
H
H
NOTES:
1.
See Table 11 for values x, y.
Table 8. Status Flags (Standard Mode)
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
FQV263
BM1 = BM0 = x9
FQV273
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y
(y+1) to 8,192
8,193 to [16,384-(x+1)]
(16,384 –x) to 16,383
16,384
FQV253
BM1 = BM0 = x9
PRAF
HALF
PRAE
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
FULL
PRAF
HALF
PRAE
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
FULL
PRAF
HALF
PRAE
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
FULL
PRAF
HALF
PRAE
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
EMPTY
L
H
H
H
H
H
FQV263
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y
(y+1) to 4,096
4,097 to [8,192-(x+1)]
(8,192 –x) to 8,191
8,192
FQV243
BM1 = BM0 = x9
FULL
EMPTY
L
H
H
H
H
H
FQV253
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y
(y+1) to 2,048
2,049 to [4,096-(x+1)]
(4,096 –x) to 4,095
4,096
EMPTY
L
H
H
H
H
H
FQV243
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y
(y+1) to 1,024
1,025 to [2,048-(x+1)]
(2,048–x) to 2,047
2,048
EMPTY
L
H
H
H
H
H
NOTES:
1.
See Table 11 for values x, y.
Table 8. Status Flags (Standard Mode) (Continued)
3F30918C
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JANUARY 2003
Page 23 of 43
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
FQV2113
BM1 = BM0 = x9
0
1 to y+1(1)
(y+2) to 262,145
262,146 to [524,289-(x+1)]
(524,289-x(1)) to 524,288
524,289
FQV2103
DRDY
PRAF
HALF
PRAE
QRDY
L
L
L
L
L
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
DRDY
PRAF
HALF
PRAE
QRDY
L
L
L
L
L
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
DRDY
PRAF
HALF
PRAE
QRDY
L
L
L
L
L
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
DRDY
PRAF
HALF
PRAE
QRDY
L
L
L
L
L
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
DRDY
PRAF
HALF
PRAE
QRDY
L
L
L
L
L
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
FQV2113
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y+1
(y+2) to 131,073
131,074 to [262,145-(x+1)]
(262,145-x) to 262,144
262,145
BM1 = BM0 = x9
FQV293
FQV2103
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y+1
(y+2) to 65,537
65,538 to [131,073-(x+1)]
(131,073-x) to 131,072
131,073
BM1 = BM0 = x9
FQV283
FQV293
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y+1
(y+2) to 32,769
32,770 to [65,537-(x+1)]
(65,537 -x) to 65,536
65,537
BM1 = BM0 = x9
FQV273
FQV283
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y+1
(y+2) to 16,385
16,386 to [32,769-(x+1)]
(32,769-x) to 32,768
32,769
BM1 = BM0 = x9
NOTES:
1.
See Table 11 for values x, y.
Table 9. Status Flags (FWFT Mode)
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
FQV263
BM1 = BM0 = x9
FQV273
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y+1
(y+2) to 8,193
8,194 to [16,385-(x+1)]
(16,385 -x) to 16,384
16,385
FQV253
BM1 = BM0 = x9
PRAF
HALF
PRAE
QRDY
L
L
L
L
L
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
DRDY
PRAF
HALF
PRAE
QRDY
L
L
L
L
L
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
DRDY
PRAF
HALF
PRAE
QRDY
L
L
L
L
L
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
DRDY
PRAF
HALF
PRAE
QRDY
L
L
L
L
L
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
FQV263
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y+1
(y+2) to 4,097
4,098 to [8,193-(x+1)]
(8,193 -x) to 8,192
8,193
FQV243
BM1 = BM0 = x9
DRDY
FQV253
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y+1
(y+2) to 2,049
2,050 to [4,097-(x+1)]
(4,097-x) to 4,096
4,097
FQV243
BM1 ≠ BM0 or BM1 = BM0 = x18
0
1 to y+1
(y+2) to 1,025
1,026 to [2,049 -(x+1)]
(2,049 -x) to 2,048
2,049
NOTES:
1.
See Table 11 for values x, y.
Table 9. Status Flags (FWFT Mode) (Continued)
3F30918C
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JANUARY 2003
Page 25 of 43
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
ES
BM1
BM0
I/O
Width
D/Q17 - 9
D/Q8 – 0
Sequence
0
0
0
I
18
Byte 2
Byte 1
1st Write
O
18
Byte 2
Byte 1
1st Read
I
18
Byte 2
Byte 1
1st Write
O
9
X
Byte 2
1st Read
X
Byte 1
2nd Read
X
Byte 2
1st Write
X
Byte 1
2nd Write
0
0
X
0
1
1
1
0
1
I
O
18
Byte 2
Byte 1
1st Read
I
9
X
Byte 2
1st Write
X
Byte 1
2nd Write
X
Byte 2
1st Read
X
Byte 1
2nd Read
O
1
1
1
0
0
1
0
1
0
9
9
I
18
Byte 2
Byte 1
1st Write
O
18
Byte 1
Byte 2
1st Read
I
18
Byte 2
Byte 1
1st Write
O
9
X
Byte 1
1st Read
X
Byte 2
2nd Read
X
Byte 2
1st Write
X
Byte 1
2nd Read
Byte 1
Byte 2
1st Read
I
O
9
18
Table 10. Bus-Matching Table
3F30918C
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JANUARY 2003
Page 26 of 43
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
LOAD
PFS0
FQV273
FQV263
FQV253
FQV243
Offsets x, y
PFS1
All Other
Modes
x9 to x9 Mode
Offsets x, y
0
0
0
127
127
127
0
0
1
511
511
511
0
1
0
255
255
255
0
1
1
63
63
63
1
0
0
31
1,023
1,023
1
0
1
15
31
31
1
1
0
7
15
15
1
1
1
3
7
7
1
X
X
Serial
0
X
X
Parallel
LOAD
PFS0
FQV2113
FQV2103
FQV293
FQV283
Offsets x, y
PFS1
All Other
Modes
x9 to x9 Mode
Offsets x, y
0
0
0
127
127
127
0
0
1
511
16,383
16,383
0
1
0
255
8,191
8,191
0
1
1
63
4,095
4,095
1
0
0
1,023
1,023
1,023
1
0
1
31
2,047
2,047
1
1
0
15
511
511
1
1
1
7
255
255
1
X
X
Serial
0
X
X
Parallel
NOTES:
1.
x = PRAF offset, y = PRAE offset.
Table 11. Default Programmable Flag Offsets
3F30918C
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JANUARY 2003
Page 27 of 43
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
Timing Diagrams
tRST
MRST
tRSTS
tRSTR
tRSTS
tRSTR
tRSTS
tRSTR
tRSTS
tRSTR
REN
WEN
FWFT/SDI
LOAD
tRSTS
PFS1/PFS0
tRSTS
BM1/BM0
tRSTS
ES
tRSTS
RETZL
tRSTS
SFM
tRSTS
IPAR
tRSTS
RET
tRSTS
SDEN
tRSTF
If FWFT = 1,QRDY = 1
EMPTY / QRDY
If FWFT = 0, EMPTY = 0
tRSTF
If FWFT = 0, FULL = 1
FULL / DRDY
If FWFT = 1, DRDY = 0
tRSTF
PRAE
tRSTF
PRAF , HALF
tRSTF
OE = 1
Q17- 0
OE = 0
Diagram 1. Master Reset Timing
3F30918C
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JANUARY 2003
Page 28 of 43
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
tRST
PRST
tRSTS
tRSTR
tRSTS
tRSTR
REN
WEN
tRSTS
RET
tRSTS
SDEN
tRSTF
If FWFT = 1,QRDY = 1
EMPTY / QRDY
If FWFT = 0, EMPTY = 0
tRSTF
If FWFT = 0, FULL = 1
FULL / DRDY
If FWFT = 1, DRDY = 0
tRSTF
PRAE
tRSTF
PRAF , HALF
tRSTF
OE = 1
Q17 - 0
OE = 0
Diagram 2. Partial Reset Timing
3F30918C
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JANUARY 2003
Page 29 of 43
3F30918C
tWCLK
No
Write
WCLK
tWCLKH
1
No
Write
tWCLKL
2
1
tDS
tSKEW1
2
tSKEW1
tDH
tDS
DWi
D 17 - 0
tFULL
tDH
DWi + 1
tFULL
tFULL
tFULL
FULL
WEN
RCLK
tENH
tENS
tENS
tENH
REN
tA
Q 17 - 0
Output Register Data
tA
Data Read
Next Data Read
NOTES:
___________
1.
___________
2.
__________
If the time between a rising edge of RCLK to the rising edge of WCLK is greater or equal than tSKEW1, FULL will go high (after one WCLK cycle plus tFULL). If tSKEW1 is not met, then FULL will assert 1 or more
WCLK cycles.
______
LOAD = High, OE = Low.
Diagram 3. Write Cycle and Full Flag Timing (Standard Mode)
FlexQTMIII
JANUARY 2003
Page 30 of 43
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
No
Write
3F30918C
RCLK
tRCLKL
1
tENS
2
tENH
tENS
No Operation
tENH
tENS
tENH
No Operation
REN
tEMPTY
tEMPTY
tEMPTY
EMPTY
tA
tA
Q17 - 0
Last Word
tOLZ
Last Word
tA
DW1
DW2
tOLZ
tOHZ
tOE
OE
tSKEW1
WCLK
tENH
tENS
tENS
tENH
WEN
tDS
tDH
DW1
D17 - 0
tDS
tDH
DW2
NOTES:
______________
1.
______________
If the time between a rising edge of WCLK to the rising edge of RCLK is greater or equal than tSKEW1, EMPTY will go high (after one RCLK cycle plus tEMPTY). If tSKEW1 is not met, then EMPTY will assert 1 or
more RCLK cycles.
___________
2.
3.
LOAD = High.
First word latency: tSKEW1 + tEMPTY + 1 * tRCLK.
FlexQTMIII
Page 31 of 43
JANUARY 2003
Diagram 4. Read Cycle, Empty Flag and First Data Word Latency Timing (Standard Mode)
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
tRCLK
tRCLKH
3F30918C
1
2
tENS
WEN
tDS
tDH
D 17 - 0
DW1
tDS
DW2
DW3
DW4
tDS
DW[y+2]
tSKEW1
RCLK
1
DW[y+3]
DW[y+4]
DW[(D-1)/2+1]
tDS
DW[(D-1)/2+2]
DW[(D-1)/2+3]
DW[D-x-1]
tENH
DW[D-x]
DW[D-x+1]
DW[D-x+2]
DW[D-x+3]
DW[D-1]
DWD
tSKEW2
2
3
1
2
REN
tA
Q 17 - 0
Output Register Data
DW1
tEMPTY
QRDY
tPRAES
PRAE
tHALF
HALF
tPRAFS
PRAF
tFULL
DRDY
NOTES:
____________
____________
1.
If the time between a rising edge of WCLK to the rising edge of RCLK is greater or equal than tSKEW1, QRDY will go low (after two RCLK cycle plus tEMPTY). If tSKEW1 is not met, then QRDY will assert 1 or more
RCLK cycles.
2.
If the time between a rising edge of WCLK to the rising edge of RCLK is greater or equal than tSKEW2, PRAE will go high (after one RCLK cycle plus tPRAES). If tSKEW2 is not met, then PRAE will assert 1 or more
RCLK cycles.
___________
___________
3.
______
LOAD = High, OE = Low.
___________
4.
5.
6.
___________
___________
y = PRAE offset, x = PRAF offset.
D = maximum queue depth. Please refer to Table 7 for Depth.
First word latency: tSKEW1 + tEMPTY + 2 * tRCLK
Diagram 5. Write Timing (FWFT Mode)
FlexQTMIII
JANUARY 2003
Page 32 of 43
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
WCLK
3F30918C
2
1
tENH
tENS
2
1
tSKEW1
tSKEW2
WEN
tDS
tDH
DWD
D17 - 0
RCLK
2
1
tENS
tENS
REN
OE
tOHZ
tOE
DW1
Q 17 - 0
tA
DW1
tA
DW2
tA
DW3
DWx+1
tA
DWx+2
DWx+3
DW[(D-1)/2+1]
tA
DW[(D-1)/2+2]
DW[D-y-1]
tA
DW[D-y]
DW[D-y+1]
DW[D-y+2]
DW[D-1]
DWD
tEMPTY
QRDY
tPRAES
PRAE
tHALF
HALF
tPRAFS
PRAF
tFULL
tFULL
DRDY
NOTES:
____________
____________
1.
If the time between a rising edge of RCLK to the rising edge of WCLK is greater or equal than tSKEW1, DRDY will go low (after one WCLK cycle plus tFULL) . If tSKEW1 is not met, then DRDY will assert 1 or more
WCLK cycles.
2.
If the time between a rising edge of RCLK to the rising edge of WCLK is greater or equal than tSKEW2, PRAF will go high (after one WCLK cycle plus tPRAFS) If tSKEW2 is not met, then PRAF will assert 1 or more
WCLK cycles.
___________
___________
___________
3.
LOAD = High
4.
5.
y = PRAE Offset, x = PRAF offset.
D = maximum queue depth. Please refer to Table 7 for Depth.
___________
___________
FlexQTMIII
JANUARY 2003
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Diagram 6. Read Timing (FWFT Mode)
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
WCLK
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
RCLK
2
1
tENS
tENH
tRETS
tENH
tENS
REN
tA
Q 17 - 0
tA
DWi
DWi+1
tA
DW1
DW2
tSKEW2
WCLK
1
2
tRETS
WEN
tENS
tENH
RET
tEMPTY
tEMPTY
EMPTY
tPRAES
PRAE
tHALF
HALF
tPRAFS
PRAF
NOTES:
1.
2.
3.
4.
Upon completion of retransmit setup, a read operation can begin only after EMPTY returns high.
OE = Low.
DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.
Upon reset completion, there must be more than two words written to the queue for a retransmit setup to be valid.
Diagram 7. Retransmit Timing (Standard Mode)
3F30918C
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FlexQTMIII
RCLK
1
tENS
tENH
2
tRETS
3
4
tENS
tENH
REN
tA
Q 17 - 0
DWi
DWi+1
tA
DW1
tA
DW2
tA
DW3
DW4
tSKEW2
WCLK
1
2
tRETS
WEN
tENS
tENH
RET
tEMPTY
tEMPTY
QRDY
tPRAES
PRAE
tHALF
HALF
tPRAFS
PRAF
NOTES:
1.
2.
3.
4.
5.
Upon completion of retransmit setup, a read operation can begin only after QRDY returns low.
OE = Low.
DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.
Upon reset completion, there must be more than two words written to the queue for a retransmit setup to be valid.
Please refer to Table 7 for Depth.
Diagram 8. Retransmit Timing (FWFT Mode)
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
RCLK
1
2
3
tENS
tENH
REN
tA
Q 17 - 0
tA
tA
DWi+1
DWi
tA
DW1
DW2
tA
DW3
DW4
tSKEW2
WCLK
1
2
tRETS
WEN
tENS
tENH
RET
EMPTY
tPRAES
PRAE
tHALF
HALF
tPRAFS
PRAF
NOTES:
1.
2.
3.
4.
5.
6.
If the part is empty at the point of retransmit, the Empty Flag ( EMPTY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will
appear on the output.
OE = Low; enables data to be read on outputs Q17 – 0.
DW1= first word written to the queue after Master Reset; DW2= second word written to the queue after Master Reset.
No more than D-2 may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, FULL will be high throughout the
retransmit setup procedure. Please refer to Table 7 for Depth.
There must be at least two words written to zero latency retransmit from the queue before a retransmit operation can be invoked.
RETZL is set Low during MRST .
Diagram 9. Zero Latency Retransmit Timing (Standard Mode)
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
RCLK
1
2
3
4
5
tENH
tENS
REN
tA
tA
DWi
Q 17 - 0
tA
DW i+1
DW1
tA
DW2
tA
tA
DW3
DW4
DW5
tSKEW2
WCLK
1
2
tRETS
WEN
tENS
tENH
RET
QRDY
tPRAES
PRAE
tHALF
HALF
tPRAFS
PRAF
NOTES:
1.
2.
3.
4.
5.
6.
If the part is empty at the point of retransmit, the output ready flag ( QRDY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will
appear on the output.
No more than D-2 words may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, DRDY will be low throughout
the retransmit setup procedure. Please refer to Table 7 for Depth.
OE = Low.
DW1, DW2, DW3 = first, second and third words written to the queue after Master Reset.
There must be at least two words written to the queue before a retransmit operation can be invoked.
RETZL is set low during MRST .
Diagram 10. Zero Latency Retransmit Timing (FWFT Mode)
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
WCLK
tENS
tENH
tENH
tLOADH
tLOADH
SDEN
tLOADS
LOAD
tDS
SDI
tDH
BIT 0
BIT MSB
BIT 0
PRAE Offset
BIT MSB
PRAF Offset
*Refer to Table 12
Diagram 11. Serial Loading of Programmable Flag Registers (Standard and FWFT Mode)
FQV21113
FQV2103
FQV293
FQV283
FQV273
FQV263
FQV253
FQV243
MSB for x9 to x9
18
17
16
15
14
13
12
11
MSB for All
Other Modes
17
16
15
14
13
12
11
10
Table 12. Reference Table for Diagram 11
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
tWCLK
tWCLKH
tWCLKL
WCLK
tLOADS
tLOADH
tLOADH
LOAD
tENS
tENH
tENH
WEN
tDS
tDH tDS
tDH tDS
tDH tDS
tDH
D 17 - 0
PRAE offset
(Low Byte)
PRAE offset
(High Byte)
PRAF offset
(Low Byte)
PRAF offset
(High Byte)
NOTES:
___________
1.
___________
Based on programming the x18 bus width. For the x9 bus width, add one extra cycle to both PRAE and PRAF offsets.
Diagram 12. Parallel Loading of Programmable Flag Registers (Standard and FWFT Mode)
tRCLK
tRCLKH
tRCLKL
RCLK
tLOADS
tLOADH
tLOADH
tENH
tENH
LOAD
tENS
REN
tA
Q 17 - 0
tA
tA
tA
Data Output Register
PRAE offset
(Low Byte)
PRAE offset
(High Byte)
PRAF offset
(Low Byte)
PRAF offset
(High Byte)
NOTES:
___________
1.
___________
Based on programming the x18 bus width. For the x9 bus width, add one extra cycle to both PRAE and PRAF offsets.
Diagram 13. Parallel Read of Programmable Flag Registers (Standard and FWFT Mode)
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
tWCLKH
tWCLKL
WCLK
1
tENS
2
1
2
tENH
WEN
tPRAFS
PRAF
tPRAFS
D - ( x + 1 ) words
in Queue
D - x words in Queue
D - ( x + 1 ) words in Queue
tSKEW2
RCLK
tENS
tENH
REN
NOTES:___________
1.
2.
3.
4.
x = PRAF offset.
D = maximum queue depth. Please refer to Table 7 for Depth.
___________
If the time between a rising edge of
RCLK to the rising edge of WCLK is greater or equal than tSKEW2, PRAF will go high (after one WCLK cycle plus
___________
t___________
PRAFS). If tSKEW2 is not met, then PRAF will assert 1 or more WCLK cycles.
PRAF synchronizes to the rising edge of WCLK only.
Diagram 14. Synchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)
tWCLKH
tWCLKL
WCLK
tENS
tENH
WEN
PRAE
y words in Queue(2) ; y+1 words in Queue(3)
tSKEW2
RCLK
tPRAES
1
y words in Queue(2) ;
y+1 words in Queue(3)
y+1 words in Queue(2) ; y+2 words in Queue(3)
tPRAES
2
1
tENS
2
tENH
REN
NOTES:___________
1.
2.
3.
4.
5.
y = PRAE offset.
For Standard Mode.
For FWFT Mode.
___________
If the time between a rising edge of
WCLK to the rising edge of RCLK is greater or equal than tSKEW2, PRAE will go high (after one RCLK cycle plus
___________
tPRAES). If tSKEW2 is not met, then PRAE will assert 1 or more RCLK cycles.
___________
PRAE synchronizes to the rising edge of RCLK only.
Diagram 15. Synchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)
3F30918C
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JANUARY 2003
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
tWCLKH
tWCLKL
WCLK
tENS
tENH
WEN
tPRAFA
D - x words in
Queue
D - ( x + 1) words in Queue
PRAF
D - ( x + 1) words in Queue
tPRAFA
RCLK
tENH
tENS
REN
NOTES:___________
1.
2.
3.
4.
x = PRAF offset.
D
= maximum queue depth. Please refer to Table 7 for Depth.
___________
PRAF is asserted to low on WCLK transition and reset to high on RCLK transition.
Select this mode by setting SFM low during Master Reset.
Diagram 16. Asynchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)
tWCLKH
tWCLKL
WCLK
tENS
tENH
WEN
tPRAEA
y+1 words in
Queue(2); y+2
words in Queue (3)
y words in Queue(2); y+1 words in Queue(3)
PRAE
y words in Queue(2); y+1 words in Queue(3)
tPRAEA
RCLK
tENS
tENH
REN
NOTES:___________
1.
2.
3.
4.
5.
y = PRAE offset.
For Standard Mode.
For
FWFT Mode.
___________
PRAE is asserted to low on RCLK transition and reset to high on WCLK transition.
Select this mode by setting SFM low during Master Reset.
Diagram 17. Asynchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)
3F30918C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JANUARY 2003
Page 41 of 43
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
tWCLKL
tWCLKH
WCLK
tENS
tENH
WEN
D/2 + 1 words in
Queue(1);
[(D+1)/2 + 1] words
in Queue(2)
tHALF
HALF
D/2 words in Queue(1); [(D+1)/2] words in Queue(2)
tHALF
D/2 words in Queue(1);
[(D+1)/2] words in Queue(2)
RCLK
tENS
tENH
REN
NOTES:
1.
2.
3.
For Standard Mode.
For FWFT Mode.
Please refer to Table 7 for Depth.
Diagram 18. Half-Full Flag Timing (Standard and FWFT Mode)
3F30918C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JANUARY 2003
Page 42 of 43
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQTMIII
Order Information:
HBA
Device Family
Device Type
Power
Speed (ns) *
Package**
Temperature Range
XX
FQ
XXXXX
V2113 (524,288 x 9)
X
Low
XX
6 – 166 MHz
XX
PF
X
Blank – Commercial (0°C to 70°C)
(262,144 x 18)
V2103 (262,144 x 9)
(131,072 x 18)
V293
7-5 – 133 MHz
I – Industrial (-40° to 85°C)
10 – 100 MHz
15 – 66 MHz
(131,072 x 9)
(65,536 x 18)
V283
(65,536 x 9)
V273
(32,768 x 9)
V263
(16,384 x 9)
(32,768 x 18)
(16,384 x 18)
(8,192 x 18)
V253
(8,192 x 9)
(4,096 x 18)
V243
(4,096 x 9)
(2,048 x 18)
*Speed – 6ns available only in Commercial temp (0°C to 70°C). Slower speeds available upon request.
**Package – 80 pin Plastic Thin Quad Flat Pack (TQFP)
Example:
FQV283L6PF
FQV273L10PFI
(64k x 9, 6ns, Commercial temp)
(32k x 9, 10ns, Industrial temp)
Document Revision History:
02/26/03 pg. 1, 2, 3, 5, 6, 7, 8, 9, 10, 13, 14, 15, 20, 21, 24, 25, 27, 28, 29, 30, 31, 32, 34, 38, 39, 40, 41, 42
USA
2107 North First Street, Suite 415
San Jose, CA 95131, USA
www.hba.com
Tel: 408.453.8885
Fax: 408.453.8886
3F30918C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
Taiwan
No. 81, Suite 8F-9, Shui-Lee Rd.
Hsinchu, Taiwan, R.O.C.
www.hba.com
Tel: 886.3.516.9118
Fax: 886.3.516.9181
JANUARY 2003
Page 43 of 43
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