Manual 8470400

Manual 8470400
Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
Reference
Design
TPD3E001
SLLS683F – JULY 2006 – REVISED OCTOBER 2015
TPD3E001 Low-Capacitance 3-Channel ESD-Protection for High-Speed Data Interfaces
1 Features
3 Description
•
The TPD3E001 is a three-channel Transient Voltage
Suppressor (TVS) based Electrostatic Discharge
(ESD) protection diode array. The TPD3E001 is rated
to dissipate ESD strikes at the maximum level
specified in the IEC 61000-4-2 international standard
(Level 4). This device has a 1.5-pF IO capacitance
per channel, making it ideal for use in high-speed
data IO interfaces. The ultra low leakage current
(<1 nA max) is suitable for precision analog
measurements in applications like glucose meters
and heart rate monitors.
1
•
•
•
•
•
•
•
IEC61000-4-2 Level-4 ESD Protection
– ±8-kV IEC 61000-4-2 Contact Discharge
– ±15-kV IEC 61000-4-2 Air-Gap Discharge
5.5-A Peak Pulse Current (8/20-µs Pulse)
I/O Capacitance: 1.5 pF (Typical)
Low Leakage Current: 1-nA (Maximum)
Low Supply Current: 1-nA (Typical)
0.9-V to 5.5-V Supply-Voltage Range
Space-Saving DRY, DRL, and DRS Package
Options
Alternate 2-, 4-, and 6-Channel Options Available:
TPD2E2U06, TPD4E1U06, and TPD6E001
2 Applications
•
•
End Equipments
– Blood Glucose Meters
– Video Surveillance Equipment
– Portable Data Terminal
– Industrial Monitor
Interfaces
– USB2.0
– SDIO
– Precision Analog Interface
– SVGA Video Connections
The TPD3E001 is available in space saving DRY
(USON), DRL (SOT), and DRS (WSON) packages
and is specified for –40°C to 85°C operation. Also
see TPD2E2U06, TPD4E1U06, and TPD6E001
which are 2, 4, and 6 channel ESD protection
options, respectively, for ESD protection diode arrays
with a different number of channels. The TPD2E2U06
provides a higher level of IEC ESD protection, when
compared to the TPDxE001 family, and removes the
need for an input capacitor. The TPD4E1U06
removes the need for an input capacitor, provides
higher IEC ESD protection, and provides lower
capacitance, when compared to the TPDxE001
family.
Device Information(1)
PART NUMBER
TPD3E001
PACKAGE
BODY SIZE (NOM)
SOT (5)
1.60 mm × 1.20 mm
WSON (6)
3.00 mm × 3.00 mm
USON (6)
1.45 mm × 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Application Schematic
0.1µF
VCC
VBUS
DD+
ID
IO1
USB
Controller
IO2
IO3
GND
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD3E001
SLLS683F – JULY 2006 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
5
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 6
7.1 Overview ................................................................... 6
7.2 Functional Block Diagram ......................................... 6
7.3 Feature Description................................................... 6
7.4 Device Functional Modes.......................................... 6
8
Application and Implementation .......................... 7
8.1 Application Information.............................................. 7
8.2 Typical Application ................................................... 7
9 Power Supply Recommendations........................ 9
10 Layout..................................................................... 9
10.1 Layout Guidelines ................................................... 9
10.2 Layout Example ...................................................... 9
11 Device and Documentation Support ................. 10
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
10
10
10
10
10
12 Mechanical, Packaging, and Orderable
Information ........................................................... 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (April 2013) to Revision F
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: TPD3E001
TPD3E001
www.ti.com
SLLS683F – JULY 2006 – REVISED OCTOBER 2015
5 Pin Configuration and Functions
DRY Package
6-Pin USON
Top View
DRL Package
5-Pin SOT
Top View
IO1
1
6
VCC
IO2
2
5
N.C.
GND
3
4
IO3
IO1
1
IO2
2
GND
3
5
VCC
4
IO3
DRS Package
6-Pin WSON
Top View
IO1 1
6
VCC
IO2 2
5
N.C.
4
IO3
GND
GND 3
Pin Functions
PIN
NAME
IOx
DRY NO.
DRL NO.
DRS NO.
TYPE
DESCRIPTION
1, 2, 4
1, 2, 4
1, 2, 4
I/O
GND
3
3
3
GND
Ground
VCC
6
5
6
Power
Power-supply input. Bypass VCC to GND with a 0.1-μF
ceramic capacitor.
N.C.
5
–
5
–
–
Exposed
Thermal
Pad
GND
EP
–
ESD-protected channel
No connection. Not internally connected.
Exposed thermal pad. Connect to GND or leave floating.
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: TPD3E001
3
TPD3E001
SLLS683F – JULY 2006 – REVISED OCTOBER 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
UNIT
–0.3
7
V
–0.3
VI/O
IO voltage tolerance
VCC + 0.3
V
TJ
Junction temperature
150
°C
Lead temperature (soldering, 10 s)
300
°C
Peak pulse power (tp = 8/20 µs)
90
W
Peak pulse power (tp = 8/20 µs)
5.5
A
150
°C
Tstg
(1)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±15000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
IEC 61000-4-2 Contact Discharge
±8000
IEC 61000-4-2 Air-gap Discharge
±15000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Operating Voltage
NOM
MAX
VCC Pin
0.9
5.5
IOx Pin
0
VCC
-40
85
Operating free-air temperature, TA
UNIT
V
°C
6.4 Thermal Information
TPD3E001
THERMAL METRIC
(1)
DRL (SOT)
DRS (WSON)
DRY (USON)
5 PINS
6 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
266.3
91.9
374.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
111.5
106.9
223.4
°C/W
RθJB
Junction-to-board thermal resistance
84.5
64.8
227.8
°C/W
ψJT
Junction-to-top characterization parameter
16.0
10.2
52.9
°C/W
ψJB
Junction-to-board characterization parameter
84.0
64.9
224.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
29.9
87.5
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: TPD3E001
TPD3E001
www.ti.com
SLLS683F – JULY 2006 – REVISED OCTOBER 2015
6.5 Electrical Characteristics
VCC = 5 V ± 10%, TA = -40°c to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCC
Supply voltage
ICC
Supply current
VF
Diode forward voltage
IF = 10 mA
0.65
VBR
Breakdown Voltage
IBR = 10mA
11
MAX
5.5
V
1
100
nA
0.95
V
0.9
Channel clamp voltage (2)
VC
TYP (1)
TA = 25°C, ±15-kV HBM,
IF = 10 A
Positive transients
TA = 25°C,
±8-kV Contact Discharge
(IEC 61000-4-2), IF = 24 A
Positive transients
TA = 25°C,
±15-kV Air-Gap Discharge
(IEC 61000-4-2), IF = 45 A
Positive transients
UNIT
V
VCC + 25
Negative transients
–25
VCC + 60
Negative transients
–60
V
VCC + 100
Negative transients
–100
Ii/o
Channel leakage current
Vi/o = GND or VCC
Cio
Channel input capacitance
VCC = 5 V, bias of VCC/2
1.5
pF
Rdyn
Dynamic resistance
Ii/o = 1 A, between IO pin and
ground
1.2
Ω
(1)
(2)
±1
nA
Typical values are at VCC = 5 V and TA = 25°C.
Channel clamp voltage is not production tested.
6.6 Typical Characteristics
1000
2.20
IO Leakage Current (pA)
IO Capacitance (pF)
2.00
1.80
1.60
1.40
1.20
1.00
0.00
1.00
2.00
2.50
3.00
4.00
5.00
100
10
1
–40
25
IO Voltage (V)
45
65
85
Temperature (°C)
VCC = 5.0 V
VCC = 5.5 V
Figure 1. IO Capacitance vs IO Voltage
Figure 2. IO Leakage Current vs Temperature
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: TPD3E001
5
TPD3E001
SLLS683F – JULY 2006 – REVISED OCTOBER 2015
www.ti.com
7 Detailed Description
7.1 Overview
The TPD3E001 is a three-channel Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD)
protection diode array. The TPD3E001 is rated to dissipate ESD strikes at the maximum level specified in the
IEC 61000-4-2 international standard (Level 4). This device has a 1.5-pF IO capacitance per channel, making it
ideal for use in high-speed data IO interfaces. The ultra low leakage current (< 1 nA maximum) is suitable for
precision analog measurements in applications like glucose meters and heart rate monitors. The wide voltage
range on VCC (up to 5.5V) gives this device the flexibility to be used in a wide variety applications. Having 3channels of ESD protection makes this device particularly well suited to protect a micro-AB USB connector,
which has three signal lines to be protected (D+, D-, ID). The VBUS pin can also be protected by connecting it to
VCC on TPD3E001. Therefore, TPD3E001 is a one-chip solution to provide Level 4 IEC 61000-4-2 ESD
protection on every pin of the micro-AB USB connector.
7.2 Functional Block Diagram
VCC
IO1
IO3
IO2
GND
7.3 Feature Description
TPD3E001 is a uni-directional ESD protection device with low capacitance. The device is constructed with a
central ESD clamp that features two hiding diodes per line to reduce the capacitive loading. This central ESD
clamp is also connected to VCC to provide protection for the VCC line. Each IO line is rated to dissipate ESD
strikes at the maximum level specified in the IEC 61000-4-2 level 4 international standard. The TPD3E001's low
loading capacitance makes it ideal for protection high-speed signal terminals.
7.4 Device Functional Modes
TPD3E001 is a passive-integrated circuit that activates whenever voltages above VBR or below the lower diodes
Vforward (–0.6V) are present upon the circuit being protected. During ESD events, voltages as high as ±15 kV can
be directed to ground and VCC via the internal diode network. Once the voltages on the protected lines fall below
the trigger voltage of the TPD3E001 (usually within 10's of nano-seconds) the device reverts back to a highimpedance state.
6
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: TPD3E001
TPD3E001
www.ti.com
SLLS683F – JULY 2006 – REVISED OCTOBER 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
TPD3E001 is a diode array type Transient Voltage Suppressor (TVS) which is typically used to provide a path to
ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a system.
As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is
the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a
tolerable level to the protected IC.
8.2 Typical Application
0.1µF
VCC
VBUS
D-
IO1
USB
Controller
IO2
D+
IO3
ID
GND
GND
Figure 3. Typical Application Schematic
8.2.1 Design Requirements
For this design example, a single TPD3E001 is used to protect all the pins of a USB2.0 micro-AB connector. The
micro-AB connector has an extra pin, the ID pin, which is used by the device to determine whether it is to
perform the "A" role or the "B' role. This functionality the ID offers is part of the USB On-the-Go (OTG) Standard.
The TPD3E001 offers 3-channels of IEC Level ESD protection to provide complete protection for the USB microAB style connector, plus VCC (VBUS, D+, D-, ID).
Given the USB application, the following parameters are known.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Signal range on IO1, IO2
0 V to 3.6 V
State of IO3 (ID)
GND or Floating
Signal voltage range on VCC
0 V to 5.25 V
Operating Frequency
240 MHz
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: TPD3E001
7
TPD3E001
SLLS683F – JULY 2006 – REVISED OCTOBER 2015
www.ti.com
8.2.2 Detailed Design Procedure
When placed near the USB connectors, the TPD3E001 ESD solution offers little or no signal distortion during
normal operation due to low IO capacitance and ultra-low leakage current specifications. The TPD3E001 ensures
that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For
proper operation, the following layout/ design guidelines should be followed:
1. Place the TPD3E001 solution close to the connectors. This allows the TPD3E001 to take away the energy
associated with ESD strike before it reaches the internal circuitry of the system board.
2. Place a 0.1-μF capacitor very close to the VCC pin. This limits any momentary voltage surge at the IO pin
during the ESD strike event.
3. Ensure that there is enough metallization for the VCC and GND loop. During normal operation, the TPD3E001
consumes approximately 1 nA (typ.) supply current through the VCC and GND loop. But during the ESD
event, VCC and GND may see 15 A to 30 A of current, depending on the ESD level. Sufficient current path
enables safe discharge of all the energy associated with the ESD strike.
4. Leave the unused IO pins floating. In this example of protecting a micro-AB type USB port, none of the IO
pins will be left unused.
5. The VCC pin can be connected in two different ways:
(a) If the VCC pin is connected to the system power supply, the TPD3E001 works as a transient suppressor
for any signal swing above VCC + VF. A 0.1-μF capacitor on the device VCC pin is recommended for ESD
bypass.
(b) If the VCC pin is not connected to the system power supply, the TPD3E001 can tolerate higher signal
swing in the range up to 10 V. Please note that a 0.1-μF capacitor is still recommended at the VCC pin for
ESD bypass.
8.2.3 Application Curve
Voltage (V)
Figure 4 is a capture of the voltage clamping waveform of TPD3E001 on IO1 during a +8kV Contact IEC61000-42 ESD strike.
100
90
80
70
60
50
40
30
20
10
0
±10
±20
±30
±40
±15
0
15
30
45
60
75
90
105 120 135 150
Time (nS)
C001
Figure 4. TPD3E001 +8kV Contact IEC61000-4-2 Voltage Clamping Waveform
8
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: TPD3E001
TPD3E001
www.ti.com
SLLS683F – JULY 2006 – REVISED OCTOBER 2015
9 Power Supply Recommendations
TPD3E001 is a passive TVS diode, so there is no requirement to power this device. However, for best IEC
61000-4-2 ESD performance and lowest capacitance performance, it is recommended that the VCC pin is biased
with a 5V supply and that a 0.1µF capacitor is placed near the VCC pin. Take care to make sure that the
maximum voltage specification for the VCC pin is not violated.
10 Layout
10.1 Layout Guidelines
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
Figure 5 is an example of how to layout three data lines with the TPD3E001. One example could be protecting a
USB micro-AB connector from IEC ESD, as discussed in the Application and Implementation section.
GND
0.1µF
IO1
VCC
IO1
IO2
IO2
IO3
GND
IO3
= VIA to GND
Figure 5. Routing with the DRL Package
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: TPD3E001
9
TPD3E001
SLLS683F – JULY 2006 – REVISED OCTOBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
1. TPD2E2U06 Data Sheet, SLLSEG9
2. TPD4E1U06 Data Sheet, SLVSBQ9
3. TPD6E001 Data Sheet, SLLS685
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: TPD3E001
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPD3E001DRLR
ACTIVE
SOT
DRL
5
4000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
2BR
2BH
TPD3E001DRLRG4
ACTIVE
SOT
DRL
5
4000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
2BR
2BH
TPD3E001DRSR
ACTIVE
SON
DRS
6
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ZWL
TPD3E001DRYR
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
2B
TPD3E001DRYRG4
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
2B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Feb-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.78
0.69
4.0
8.0
Q3
TPD3E001DRLR
SOT
DRL
5
4000
180.0
8.4
1.98
TPD3E001DRSR
SON
DRS
6
1000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPD3E001DRYR
SON
DRY
6
5000
179.0
8.4
1.2
1.65
0.7
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Feb-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD3E001DRLR
SOT
DRL
5
4000
202.0
201.0
28.0
TPD3E001DRSR
SON
DRS
6
1000
367.0
367.0
35.0
TPD3E001DRYR
SON
DRY
6
5000
203.0
203.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising