L2_slides
Transmission techniques and
multiplexing hierarchies
Switching Technology S38.3165
http://www.netlab.hut.fi/opetus/s383165
© P. Raatikainen
Switching Technology / 2007
L2 - 1
Transmission techniques
• PDH (Plesiochronous Digital Hierarchy)
• ATM (Asynchronous Transfer Mode)
• IP/Ethernet
• SDH (Synchronous Digital Hierarchy)
• OTN (Optical Transport network)
• GFP (Generic Framing Procedure)
© P. Raatikainen
Switching Technology / 2007
L2 - 2
Plesiochronous Digital Hierarchy (PDH)
• Transmission technology of the
digitized telecom network
• Basic channel capacity 64 kbit/s
• Voice information PCM coded
• 8 bits per sample
• A or µ law
• sample rate 8 kHz (125 µs)
• Channel associated signaling
(SS7)
• Higher order frames obtained by
multiplexing four lower order
frames bit by bit and adding some
synchr. and management info
• The most common switching and
transmission format in the
telecommunication network is
PCM 30 (E1)
© P. Raatikainen
139.264 Mbit/s
E4
1920 channels
x 4
34.368 Mbit/s
E3
480 channels
x 4
8.448 Mbit/s
E2
120 channels
x 4
2.048 Mbit/s
E1
...
64 kbit/s
E0
30 channels
x 32
1 channel
Switching Technology / 2007
L2 - 3
PDH E1-frame structure (even frames)
Multi- frame
F0
F1
...
F14
Voice channels 1 - 15
T0
T1
T2
...
T0
C
0
0
1
1
0
1
1
Frame alignment signal (FAS)
Error indicator
bit (CRC-4)
© P. Raatikainen
Voice channels 16 - 30
...
T15 T16 T17
T28 T29 T30 T31
Signaling time-slot
Frame alignment time-slot
F15
0
0
0
0
Multi-frame
alignment bit
sequence in F0
1
Voice channel 28
A
1
1
B1 B2 B3 B4 B5 B6 B7 B8
Voice sample
amplitude
Multi-frame
alarm
Switching Technology / 2007
Polarity
L2 - 4
PDH E1-frame structure (odd frames)
Multi- frame
F0
F1
...
F14
Voice channels 1 - 15
T0
T1
T2
T0
...
1
A
D
D
D
D
D
Data bits for
management
Error indicator
bit (CRC-4)
© P. Raatikainen
Voice channels 16 - 30
T15 T16 T17
T28 T29 T30 T31
...
Signaling time-slot
Frame alignment time-slot
C
F15
a
b
c
Channel 1
signaling
bits
d
a
b
c
c
Channel 16
signaling
bits
Far end
alarm indication
Switching Technology / 2007
Nowadays, time slot 1
used for signaling and
time slot 16 for voice
L2 - 5
PDH-multiplexing
• Tributaries have the same nominal bit rate, but with a
specified, permitted deviation (100 bit/s for 2.048 Mbit/s)
• Plesiochronous = tributaries have almost the same bit
rate
• Justification and control bits are used in multiplexed
flows
• First order (E1) is octet-interleaved, but higher orders
(E2, … ) are bit-interleaved
© P. Raatikainen
Switching Technology / 2007
L2 - 6
PDH network elements
• concentrator
– n channels are multiplexed to a higher capacity link that carries
m channels (n > m)
• multiplexer
– n channels are multiplexed to a higher capacity link that carries n
channels
• cross-connect
– static multiplexing/switching of user channels
• switch
– switches incoming TDM/SDM channels to outgoing ones
© P. Raatikainen
Switching Technology / 2007
L2 - 7
Example PDH network elements
...
n input
channels
Concentrator
n>m
Cross-connect
DXC
m output
channels
Switch
...
n input
channels
Multiplexer
n=m
© P. Raatikainen
m output
channels
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
Switching Technology / 2007
L2 - 8
Synchronous digital hierarchy
40 Gbit/s
STM-256
x 4
Major ITU-T SDH standards:
- G.707
- G.783
STM-64
10 Gbit/s
x 4
2.48 Gbit/s
STM-16
x 4
Notice that each frame
transmitted in 125 µs !
622 Mbit/s
STM-4
x 4
155 Mbit/s
STM-1
© P. Raatikainen
Switching Technology / 2007
L2 - 9
SDH reference model
DXC
STM-n
MPX
R
STM-n
STM-n
R
STM-n
Tributaries
Tributaries
MPX
Regeneration Regeneration Regeneration
section
section
section
Multiplexing
section
Multiplexing section
Path layer connection
- DXC
- MPX
-R
© P. Raatikainen
Digital cross-connect
Multiplexer
Repeater
Switching Technology / 2007
L2 - 10
SDH-multiplexing
• Multiplexing hierarchy for plesiochronous and synchronous
tributaries (e.g. E1 and E3)
• Octet-interleaving, no justification bits - tributaries visible and
available in the multiplexed SDH flow
• SDH hierarchy divided into two groups:
– multiplexing level (virtual containers, VCs)
– line signal level (synchronous transport level, STM)
• Tributaries from E1 (2.048 Mbit/s) to E4 (139.264 Mbit/s) are
synchronized (using justification bits if needed) and packed in
containers of standardized size
• Control and supervisory information (POH, path overhead) added to
containers => virtual container (VC)
© P. Raatikainen
Switching Technology / 2007
L2 - 11
SDH-multiplexing (cont.)
• Different sized VCs for different tributaries (e.g. VC-12/E1, VC3/E3, VC-4/E4)
• Smaller VCs can be packed into a larger VC (+ new POH)
• Section overhead (SOH) added to larger VC
=> transport module
• Transport module corresponds to line signal (bit flow transferred
on the medium)
– bit rate is 155.52 Mbit/s or its multiples
– transport modules called STM-N (N = 1, 4, 16, 64, ...)
– bit rate of STM-N is Nx155.52 Mbit/s
– duration of a module is 125 µs (= duration of a PDH frame)
© P. Raatikainen
Switching Technology / 2007
L2 - 12
SDH network elements
• regenerator (intermediate repeater, IR)
– regenerates line signal and may send or receive data via
communication channels in RSOH header fields
• multiplexer
– terminal multiplexer multiplexes/demultiplexes PDH and SDH
tributaries to/from a common STM-n
– add-drop multiplexer adds or drops tributaries to/from a common
STM-n
• digital cross-connect
– used for rearrangement of connections to meet variations of
capacity or for protection switching
– connections set up and released by operator
© P. Raatikainen
Switching Technology / 2007
L2 - 13
Example SDH network elements
Cross-connect
STM-n
STM-n
STM-n
DXC
STM-n
STM-n
Add-drop multiplexer
STM-n
ADM
Terminal multiplexer
STM-n
2 - 140 Mbit/s
© P. Raatikainen
STM-n
ADM
STM-n
2 - 140 Mbit/s
Switching Technology / 2007
L2 - 14
Generation of STM-1 frame
Justification
PDH/E1
VC-12
MUX
+ POH
+ POH
© P. Raatikainen
STM-1
VC-4
+ SOH
Switching Technology / 2007
L2 - 15
STM-n frame
Three main fields:
– Regeneration and multiplexer section overhead (RSOH and MSOH)
– Payload and path overhead (POH)
– AU (administrative) pointer specifies where payload (VC-4 or VC-3)
starts
nx9 octets
nx261 octets
© P. Raatikainen
3
RSOH
1
AU-4 PTR
5
MSOH
P
O
H
Switching Technology / 2007
L2 - 16
Synchronization of payload
• Position of each octet in a STM frame (or VC frame) has a number
• AU pointer contains position number of the octet in which VC starts
• Lower order VC included as part of a higher order VC (e.g. VC-12
as part of VC-4)
VC-4 no. 0
RSOH
STM-1
no. k
AU-4 PTR
MSOH
VC-4 no. 1
RSOH
STM-1
no. k+1
AU-4 PTR
MSOH
© P. Raatikainen
VC-4 no. 2
Switching Technology / 2007
L2 - 17
Asynchronous Transfer Mode (ATM)
• cell
– 53 octets
• routing/switching
– based on VPI and VCI
• adaptation
– processing of user data into ATM cells
• error control
– cell header checking and discarding
• flow control
– no flow control
– input rate control
• congestion control
– cell discarded (two priorities)
© P. Raatikainen
Switching Technology / 2007
L2 - 18
ATM reference interfaces
NNI
UNI
EX
ATM
network
TE
NNI
UNI
EX
TE
© P. Raatikainen
-
Network-to-Network Interface
User Network Interface
Exchange Equipment
Terminal Equipment
Switching Technology / 2007
L2 - 19
ATM cell structure
5 octets
48 octets
ATM
ATM
header
header
Cell
Cellpayload
payload
ATM header for UNI
GFC
GFC
VPI
VPI
VPI
VPI
VCI
VCI
VCI
VCI
VCI
VCI
PTI
PTI
CPL
CPL
HEC
HEC
ATM header for NNI
UNI
NNI
VPI
VCI
GFC
PTI
CPL
HEC
- User Network Interface
- Network-to-Network Interface
- Virtual Path Identifier
- Virtual Channel Identifier
- Generic Flow Control
- Payload Type Identifier
- Cell Loss Priority
- Header Error Control
VPI
VPI
VPI
VPI
VCI
VCI
VCI
VCI
VCI
VCI
PTI
PTI
HEC
HEC
© P. Raatikainen
CPL
CPL
HEC = 8 x (header octets 1 to 4) / (x8 + x2 + x + 1)
Switching Technology / 2007
L2 - 20
ATM connection types
VCI 1
VCI 1
VPI 1
VPI 1
VCI 2
VCI 2
Physical channel
VCI 1
VCI 1
VPI 2
VPI 2
VCI 2
VCI 2
VCI k
VPI k
© P. Raatikainen
- Virtual Channel Identifier k
- Virtual Path Identifier k
Switching Technology / 2007
L2 - 21
Physical layers for ATM
• SDH (Synchronous Digital Hierarchy)
– STM-1 155 Mbit/s
– STM-4 622 Mbit/s
– STM-16 2.4 Gbit/s
• PDH (Plesiochronous Digital Hierarchy)
– E1
– E3
– E4
2 Mbit/s
34 Mbit/s
140 Mbit/s
• TAXI 100 Mbit/s and IBM 25 Mbit/s
• Cell based interface
– uses standard bit rates and physical level interfaces
(e.g. E1, STM-1 or STM-4)
– HEC used for framing
© P. Raatikainen
Switching Technology / 2007
L2 - 22
Transport of data in ATM cells
Network layer
Pad 0 - 47 octets
IP packet
(1+1+ 2) octets
≤ 65 535
ATM
adaptation
layer (AAL)
4 octets
AAL 5 payload
5
P
UU/
CPI/
LEN
CRC
48
ATM layer
H
Physical layer
P
UU
CPI
LEN
© P. Raatikainen
H
Cell payload
-
H
Cell payload
Cell payload
H
Cell payload
Padding octets
AAL layer user-to-user indicator
Common part indicator
Length indicator
Switching Technology / 2007
L2 - 23
ATM cell encapsulation / SDH
9 octets
3
1
STM-1
frame
261 octets
VC-4
frame
SOH
AU-4 PTR
J1
...
B3
5
...
C2
SOH
G1
F2
H4
...
...
...
Z3
Z4
Z5
...
ATM cell
VC-4 POH
© P. Raatikainen
Switching Technology / 2007
L2 - 24
ATM cell encapsulation / PDH (E1)
32 octets
Header
TS0
TS16
TS0
TS16
TS0
TS16
Header
TS0
Header
TS16
TS0
Head.
TS16
...
TS0
•frame alignment
•F3 OAM functions
•loss of frame alignment
•performance monitoring
•transmission of FERF and LOC
•performance reporting
© P. Raatikainen
TS16
•reserved for signaling
Switching Technology / 2007
L2 - 25
Cell based interface
Frame structure for cell base interfaces:
27
P
L
IDLE or
PL-OAM
1
2
H ATM layer H ATM layer
26
...
H ATM layer
27
P
L
IDLE or
PL-OAM
• PL cells processed on physical layer (not on ATM layer)
• IDLE cell for cell rate adaptation
• PL-OAM cells carry physical level OAM information
(regenerator (F1) and transmission path (F3) level messages)
• PL cell identified by a pre-defined header
• 00000000 00000000 0000000 00000001 (IDLE cell)
• 00000000 00000000 0000000 00001001 (phys. layer OAM)
• xxxx0000 00000000 0000000 0000xxxx (reserved for phys. layer)
H = ATM cell Header, PL = Physical Layer, OAM = Operation Administration and Maintenance
© P. Raatikainen
Switching Technology / 2007
L2 - 26
ATM network elements
• Cross-connect
– switching of virtual paths (VPs)
– VP paths are statically connected
• Switch
– switching of virtual channel (VCs)
– VC paths are dynamically or statically connected
• DSLAM (Digital Subscriber Line Access Multiplexer)
– concentrates a larger number of sub-scriber lines to a common
higher capacity link
– aggregated capacity of subscriber lines surpasses that of the
common link
© P. Raatikainen
Switching Technology / 2007
L2 - 27
Ethernet
• Originally a link layer protocol for LANs (10 and 100 MbE)
• Upgrade of link speeds
=> optical versions 1GbE and 10 GbE
=> suggested for long haul transmission
• No connections - each data terminal (DTE) sends data
when ready - MAC is based on CSMA/CD
• Synchronization
– line coding, preamble pattern and start-of-frame delimiter
– Manchester code for 10 MbE, 8B6T for 100 MbE,
8B10B for GbE
© P. Raatikainen
Switching Technology / 2007
L2 - 28
Ethernet frame
64 - 1518 octets
S
Preamble F
DA
SA
6
6
T/L
CRC
Payload
D
7
1
2
46 - 1500
4
Preamble - AA AA AA AA AA AA AA (Hex)
SFD - Start of Frame Delimiter AB (Hex)
DA - Destination Address
SA - Source Address
T/L - Type (RFC894, Ethernet) or Length (RFC1042, IEEE 802.3) indicator
CRC - Cyclic Redundance Check
Inter-frame gap 12 octets (9,6 µs /10 MbE)
© P. Raatikainen
Switching Technology / 2007
L2 - 29
1GbE frame
512 - 1518 octets
S
Preamble F
D
7
1
DA
SA
6
6
L
2
Payload
46 - 1500
CRC Extension
4
Preamble - AA AA AA AA AA AA AA (Hex)
SFD - Start of Frame Delimiter AB (Hex)
DA - Destination Address
SA - Source Address
T/L - Type (RFC894, Ethernet) or Length (RFC1042, IEEE 802.3) indicator
CRC - Cyclic Redundancy Check
Inter-frame gap 12 octets (96 ns /1 GbE)
Extension - for padding short frames to be 512 octets long
© P. Raatikainen
Switching Technology / 2007
L2 - 30
Ethernet network elements
• Repeater
– interconnects LAN segments on physical layer
– regenerates all signals received from one segment and forwards them
onto the next
• Bridge
– interconnects LAN segments on link layer (MAC)
– all received frames are buffered and error free ones are forwarded to
another segment (if they are addressed to it)
• Hub and switch
– hub connects DTEs with two twisted pair links in a star topology and
repeats received signal from any input to all output links
– switch is an intelligent hub, which learns MAC addresses of DTEs and
is capable of directing received frames only to addressed ports
© P. Raatikainen
Switching Technology / 2007
L2 - 31
Optical transport network
• Optical Transport Network (OTN), being developed by
ITU-T (G.709), specifies interfaces for optical networks
• Goal to gather for the transmission needs of today’
s wide
range of digital services and to assist network evolution
to higher bandwidths and improved network performance
• OTN builds on SDH and introduces some refinements:
– management of optical channels in optical domain
– FEC to improve error performance and allow longer link spans
– provides means to manage optical channels end-to-end in
optical domain (i.e. no O/E/O conversions)
– interconnections scale from a single wavelength to multiple ones
© P. Raatikainen
Switching Technology / 2007
L2 - 32
OTN reference model
OMPX
OA
OTS
Optical
channels
Optical
channels
OMPX
OA
OTS
OTS
OMS
OCh
- OCh
- OA
- OMS
- OMPX
- OTS
Optical Channel
Optical Amplifier
Optical Multiplexing Section
Optical Multiplexer
Optical Transport Section
© P. Raatikainen
Switching Technology / 2007
L2 - 33
OTN layers and OCh sub-layers
SONET/
SDH
ATM
Ethernet
IP
OPU
Optical channel payload unit
ODU
Optical channel data unit
Optical channel
Optical multiplexing section
(OMSn)
OTU
Optical channel transport unit
Optical transport section
(OTSn)
© P. Raatikainen
Switching Technology / 2007
L2 - 34
OTN frame structure
•Three main fields
– Optical channel overhead
– Payload
– Forward error indication field
GbE
IP
FR
SONET/SDH
ATM
GbE
IP
ATM/FR
SONET/SDH
Och
DWDM
Payload
FEC
Client
Digital wrapper
© P. Raatikainen
Switching Technology / 2007
L2 - 35
OTN frame structure (cont.)
4080 bytes
4 rows
1
16
17
...................................
Och
overhead
1
1
.....
.....
Payload
7
8
.....
14
2
ODU
overhead
OPU
overh.
4
OTU - Optical transport unit
ODU - Optical data unit
OPU - Optical payload unit
FEC - Forward error correction
© P. Raatikainen
3825
...
4080
FEC
15 ... 16
Frame alignmt. OTU overhead
3
3824
• Frame size remains the same (4x4080)
regardless of line rate
=> frame rate increases as line rate increases
• Three line rates defined:
• OTU1 2.666 Gbit/s
• OTU2 10.709 Gbit/s
• OTU3 43.014 Gbit/s
Switching Technology / 2007
L2 - 36
Generation of OTN frame and signal
OTN frame generation
Client signal
OPU
ODU
+ OPU-OH
OTU
+ OTU-OH
+ FEC
OTN signal generation
Client signal
OCh
OMUX
…
Client signal
OMS
OTS
OCh
© P. Raatikainen
Switching Technology / 2007
L2 - 37
OTN network elements
• optical amplifier
– amplifies optical line signal
• optical multiplexer
– multiplexes optical wavelengths to OMS signal
– add-drop multiplexer adds or drops wavelengths to/from a common
OMS
• optical cross-connect
– used to direct optical wavelengths (channels) from an OMS to another
– connections set up and released by operator
• optical switches ?
– when technology becomes available optical switches will be used for
switching of data packets in the optical domain
© P. Raatikainen
Switching Technology / 2007
L2 - 38
Generic Framing Procedure (GFP)
• Recently standardized traffic adaptation mechanism especially for
transporting block-coded and packet-oriented data
• Standardized by ITU-T (G.7041) and ANSI (T1.105.02) (the only
standard supported by both organizations)
• Developed to overcome data transport inefficiencies of existing
ATM, POS, etc. technologies
• Operates over byte-synchronous communications channels (e.g.
SDH/SONET and OTN)
• Supports both fixed and variable length data frames
• Generalizes error-control-based frame delineation scheme
(successfully employed in ATM)
– relies on payload length and error control check for frame boundary
delineation
© P. Raatikainen
Switching Technology / 2007
L2 - 39
GFP (cont.)
• Two frame types: client and control frames
– client frames include client data frames and client management
frames
– control frames used for OAM purposes
• Multiple transport modes (coexistent in the same channel)
possible
– Frame-mapped GFP for packet data, e.g. PPP, IP, MPLS and
Ethernet)
– Transparent-mapped GFP for delay sensitive traffic (storage area
networks), e.g. Fiber Channel, FICON and ESCON
© P. Raatikainen
Switching Technology / 2007
L2 - 40
GFP client data frame
• Composed of a frame header and payload
• Core header intended for data link management
– payload length indicator (PLI, 2 octets), HEC (CRC-16, 2 octets)
• Payload field divided into payload header, payload and optional
FCS (CRC-32) sub-fields
• Payload header includes:
– payload type (2 octets) and type HEC (2 octets) sub-fields
– optional 0 - 60 octets of extension header
• Payload:
– variable length (0 - 65 535 octets, including payload header and FCS)
for frame mapping mode (GFP-F) - frame multiplexing
– fixed size Nx[536, 520] for transparent mapping mode (GFP-T) - no
frame multiplexing
© P. Raatikainen
Switching Technology / 2007
L2 - 41
GFP frame structure
PTI
Payload length indicator
Payload type
Core
header
Core HEC
EXI
UPI
Type HEC
CID
Payload header
Payload
area
PFI
0 –60 bytes
extension header
(optional)
Spare
Extension HEC MSB
Extension HEC LSB
Payload
[N x 536, 520 bytes
or variable length
packet]
Payload FCS
CID - Channel identifier
FCS - Frame Check Sequence
EXI - Extension Header Identifier
HEC - Header Error Check
PFI - Payload FCS Indicator
PTI - Payload Type Indicator
UPI - User payload Identifier
Source: IEEE Communications Magazine, May 2002
© P. Raatikainen
Switching Technology / 2007
L2 - 42
Frame
mapped
GFP
client-dependent
Other
client
signals
ESCON
FICON
Fiber
Channel
RPR
MAPOS
IP/PPP
Ethernet
GFP relationship to client signals and
transport paths
Transparent
mapped
GFP
client-independent
SDH/SONET path
ESCON
FICON
IP/PPP
MAPOS
RPR
-
OTN ODUk path
Enterprise System CONnection
Fiber CONnection
IP over Point-to-Point Protocol
Multiple Access Protocol over SONET/SDH
Resilient Packet Ring
Source: IEEE Communications Magazine, May 2002
© P. Raatikainen
Switching Technology / 2007
L2 - 43
Adapting traffic via GFP-F and GFP-T
GFP-F frame
PLI
Payload
header
cHEC
2 bytes 2 bytes
Client PDU
(PPP, IP, Ethernet, RPR, etc.)
4 bytes
FCS
(optional)
4 bytes
GFP-T frame
PLI
cHEC
2 bytes 2 bytes
FCS
cHEC
PDU
PLI
Payload
header
FCS
8x64B/65B superblock #1
4 bytes
#2
... #N-1 #N (optional)
4 bytes
- Frame Check Sequence
- Core Header Error Control
- Packet Data Unit
- Payload Length Indicator
© P. Raatikainen
Switching Technology / 2007
L2 - 44
GFP-T frame mapping
64B/65B code block
8B
8B
8B
8B
8B
8B
8B
8B
8 x 64B/65B code blocks
Superblock (8 x 64B/65B code blocks + CRC-16)
CRC-16
GFP-T frame with five superblocks
Core header and payload header
© P. Raatikainen
FCS (optional)
Switching Technology / 2007
L2 - 45
Switch Fabrics
Switching Technology S38.3165
http://www.netlab.hut.fi/opetus/s383165
© P. Raatikainen
Switching Technology / 2007
L2 - 46
Switch fabrics
•Basic concepts
•Time and space switching
•Two stage switches
•Three stage switches
•Cost criteria
•Multi-stage switches and path search
© P. Raatikainen
Switching Technology / 2007
L2 - 47
Switch fabrics (cont.)
•Multi-point switching
•Self-routing networks
•Sorting networks
•Fabric implementation technologies
•Fault tolerance and reliability
© P. Raatikainen
Switching Technology / 2007
L2 - 48
Basic concepts
•Accessibility
•Blocking
•Complexity
•Scalability
•Reliability
•Throughput
© P. Raatikainen
Switching Technology / 2007
L2 - 49
Accessibility
• A network has full accessibility (= connectivity)
when each inlet can be connected to each outlet (in
case there are no other I/O connections in the
network)
• A network has a limited accessibility when the
above given property does not exist
• Interconnection networks applied in today’
s switch
fabrics usually have full accessibility
© P. Raatikainen
Switching Technology / 2007
L2 - 50
Accessibility (cont.)
Example of full accessibility
© P. Raatikainen
Example of limited accessibility
Switching Technology / 2007
L2 - 51
Blocking
• Blocking is defined as failure to satisfy a connection request and
it depends strongly on the combinatorial properties of the
switching networks
Network class
Non-blocking
Network type
Network state
Strict-sense
non-blocking
Without blocking
states
Wide-sense
non-blocking
Rearrangeably
non-blocking
Blocking
© P. Raatikainen
With
blocking
state
Others
Switching Technology / 2007
L2 - 52
Blocking (cont.)
• Non-blocking - a path between an arbitrary idle inlet and arbitrary idle
outlet can always be established independent of network state at set-up
time
• Blocking - a path between an arbitrary idle inlet and arbitrary idle outlet
cannot be established owing to internal congestion due to the already
established connections
• Strict-sense non-blocking - a path can always be set up between any
idle inlet and any idle outlet without disturbing paths already set up
• Wide-sense non-blocking - a path can be set up between any idle
inlet and any idle outlet without disturbing existing connections,
provided that certain rules are followed. These rules prevent network
from entering a state for which new connections cannot be made
• Rearrangeably non-blocking - when establishing a path between an
idle inlet and an idle outlet, paths of existing connections may have to
be changed (rearranged) to set up that connection
© P. Raatikainen
Switching Technology / 2007
L2 - 53
Examples of different sorts of blocking
networks
Rearrangeably non-blocking
Blocking
Strict-sense non-blocking
© P. Raatikainen
Strict-sense non-blocking
Switching Technology / 2007
L2 - 54
Complexity
• Complexity of an interconnection network is expressed by
cost index
• Traditional definition of cost index gives the number of crosspoints in a network
– used to be a reasonable measure of space division switching
systems
• Nowadays cost index alone does not characterize cost of an
interconnection network for broadband applications
– VLSIs and their integration degree has changed the way how
cost of a switch fabric is formed (number of ICs, power
consumption)
– management and control of a switching system has a significant
contribution to cost
© P. Raatikainen
Switching Technology / 2007
L2 - 55
Complexity (cont.)
Cost index of an 8x8 crossbar
is 64 (cross-points)
© P. Raatikainen
Cost index of an 8x8 banyan
is 12x4= 48 (cross-points)
Switching Technology / 2007
L2 - 56
Scalability
• Due to constant increase of transport links and data rates on
links, scalability of a switching system has become a key
parameter in choosing a switch fabric architecture
• Scalability describes ability of a system to evolve with
increasing requirements
• Issues that are usually matter of scalability
–
–
–
–
–
–
number of switching nodes
number of interconnection links between nodes
bandwidth of interconnection links and inlets/outlets
throughput of switch fabric
buffering requirements
number of inlets/outlets supported by switch fabric
© P. Raatikainen
Switching Technology / 2007
L2 - 57
Scalability (cont.)
Example of scalability
• a switching equipment has room for 20 line-cards and the original design
supports 10 Mbit/s interfaces (one per line card)
• throughput of switch fabric is scalable from 500 Mbit/s to 2 Gbit/s
• when new line cards that each implement two 10 Mbit/s interfaces are
introduced, the interface logic may have to be upgraded
• when new line cards that implement a 100 Mbit/s interface (one per linecard) are introduced, the switch fabric has to be upgraded (scaled up) to 2
Gbit/s speed and the interface logic has to be upgraded to 100 Mbit/s speed
• buffering memories need to be replaced by faster (and possible larger) ones
• larger number (>20) of line cards implies at least new physical design
• increase of line rates beyond 100 Mbit/s means redesign of switch fabric
© P. Raatikainen
Switching Technology / 2007
L2 - 58
Reliability
• Reliability and fault tolerance are system measures that have an
impact on all functions of a switching system
• Reliability defines probability that a system does not fail within a
given time interval provided that it functions correctly at the start
of the interval
• Availability defines probability that a system will function at a
given time instant
• Fault tolerance is the capability of a system to continue its
intended function in spite of having a fault(s)
• Reliability measures:
– MTTF (Mean Time To Failure)
– MTTR (Mean Time To Repair)
– MTBF (Mean Time Between Failures)
© P. Raatikainen
Switching Technology / 2007
L2 - 59
Throughput
• Throughput gives forwarding/switching speed/efficiency of a
switch fabric
• It is measured in bits/s, octets/s, cells/s, packet/s, etc.
• Quite often throughput is given in the range (0 ... 1.0], i.e. the
obtained forwarding speed is normalized to the theoretical
maximum throughput
© P. Raatikainen
Switching Technology / 2007
L2 - 60
Switch fabrics
•Basic concepts
•Time and space switching
•Two stage switches
•Three stage switches
•Cost criteria
•Multi-stage switches and path search
© P. Raatikainen
Switching Technology / 2007
L2 - 61
Switching mechanisms
• A switched connection requires a mechanism that
attaches the right information streams to each other
• Switching takes place in the switch fabric, the
structure of which depends on network’
s mode of
operation, available technology and required capacity
• Communicating terminals may use different physical
links and different time-slots, so there is an obvious
need to switch both in time and in space domain
• Time and space switching are basic functions of a
switch fabric
© P. Raatikainen
Switching Technology / 2007
L2 - 62
Space division switching
•A space switch directs traffic from input links to output links
•An input may set up one connection (1, 3, 6 and 7), multiple
connections (4) or no connection (2, 5 and 8)
INPUTS
OUTPUTS
1
2
3
1
2
4
5
3
4
6
7
5
6
8
m INPUT LINKS
© P. Raatikainen
INTERCONNECTION
NETWORK
n OUTPUT LINKS
Switching Technology / 2007
L2 - 63
Crossbar switch matrix
m INPUT LINKS
•Crossbar matrix introduces the basic structure of a space switch
•Information flows are controlled (switched) by opening and closing
cross-points
•m inputs and n outputs => mn cross-points (connection points)
•Only one input can be connected to an output at a time, but an input
can be connected to multiple outputs (multi-cast) at a time
1
2
3
4
5
6
7
8
MULTI-CAST
A CLOSED CROSS-POINT
1
2
3
4 5
6
n OUTPUT LINKS
© P. Raatikainen
Switching Technology / 2007
L2 - 64
An example space switch
•m x1 -multiplexer used to implement a space switch
•Every input is fed to every output mux and mux control signals
are used to select which input signal is connected through
each mux
mux/connection control
1
2
m
mx1
mx1
1
mx1
2
© P. Raatikainen
m
Switching Technology / 2007
L2 - 65
Time division multiplexing
•Time-slot interchanger is a device, which buffers m incoming timeslots, e.g. 30 time-slots of an E1 frame, arranges new transmit
order and transmits n time-slots
•Time-slots are stored in buffer memory usually in the order they
arrive or in the order they leave the switch - additional control logic
is needed to decide respective output order or the memory slot
where an input slot is stored
TIME-SLOT INTERCHANGER
Time-slot 1
INPUT CHANNELS
OUTPUT CHANNELS
Time-slot 2
6
5
4
3
2
1
Time-slot 3
5
6
1
5
3
4
2
3
6
2
4
1
Time-slot 4
Time-slot 5
Time-slot 6
© P. Raatikainen
BUFFER SPACE FOR TIME-SLOTS
Switching Technology / 2007
L2 - 66
Time-slot interchange
BUFFER FOR m
INPUT/OUTPUT SLOTS
DESTINATION OUTPUT #
8
(2)
7
6
5
(4) (1,6) (5)
4
3
2
n OUTPUT LINKS
m INPUT LINKS
1
(3)
2
3
1
6
5
4
3
2
1
4
5
6
7
8
© P. Raatikainen
Switching Technology / 2007
L2 - 67
Time switch implementation example 1
•Incoming time-slots are written cyclically into switch memory
•Output logic reads cyclically control memory, which contains a pointer for
each output time-slot
•Pointer indicates which input time-slot to insert into each output time-slot
Incoming frame buffer
…
3
2
write
address (3)
Cyclic read
1
Outgoing frame buffer
Switch
memory
1
Control
memory
1
2
3
2
3
..
.
m
j
…
2
1
Cyclic write
..
.
k
..
.
n …
read
address (k)
j (k)
..
.
n
read/write
address (j)
m
Time-slot counter & R/W control
© P. Raatikainen
Switching Technology / 2007
L2 - 68
Time switch implementation example 2
•Incoming time-slots are written into switch memory by using write-addresses
read from control memory
•A write address points to an output slot to which the input slot is addressed
•Output time-slots are read cyclically from switch memory
Incoming frame buffer
3
…
2
read
address (3)
Cyclic read
1
Outgoing frame buffer
Control
memory
1
Switch
memory
1
2
3 (k)
2
3
write
address (k)
..
.
..
.
k
m
n
..
.
n …
j
…
2
1
Cyclic write
read/write
address (2)
m
Time-slot counter & R/W control
© P. Raatikainen
Switching Technology / 2007
L2 - 69
Properties of time switches
•Input and output frame buffers are read and written at wire-speed,
i.e. m R/Ws for input and n R/Ws for output
•Interchange buffer (switch memory) serves all inputs and outputs
and thus it is read and written at the aggregate speed of all inputs
and outputs
=> speed of an interchange buffer is a critical parameter in time
switches and limits performance of a switch
•Memory speed requirement can be cut by utilizing parallel to serial
conversion
•Speed requirement of control memory is half of that of switch
memory (in fact a little moor than that to allow new control data to
be updated)
© P. Raatikainen
Switching Technology / 2007
L2 - 70
Time-Space analogy
•A time switch can be logically converted into a space switch by
setting time-slot buffers into vertical position => time-slots can be
considered to correspond to input/output links of a space switch
•But is this logical conversion fair ?
m
…
3
2
1
n
© P. Raatikainen
…
3
2
1
1
1
2
2
3
3
…
Time switch
…
Space switch
m
m
Switching Technology / 2007
L2 - 71
Space-Space analogy
•A space switch carrying time multiplexed input and output signals can be
logically converted into a pure space switch (without cyclic control) by
distributing each time-slot into its own space switch
n
…
1
2
n
1
1
2
2
m
2
…
m
1
m
…
…
1
2
…
1
2
2
…
1
Inputs and outputs are
time multiplexed signals
(K time-slots)
n
…
© P. Raatikainen
…
To switch a time-slot, it suffices
to control one of the K boxes
2
m
Switching Technology / 2007
1
K
2
…
1
n
L2 - 72
1
1
2
1
2
…
…
m
…
2
…
K multiplexed
input signals
on each link
An example conversion
m
n
1
2
mxn
KxK
nxm
1
1
1
m
m
1
2
2
2
2
1
2
m
m
…
…
…
1
2
1
2
K
n
K
m
m
© P. Raatikainen
1
2
Switching Technology / 2007
L2 - 73
Properties of space and time switches
Space switches
Time switches
•number of cross-points (e.g. ANDgates)
- m input x n output = mn
- when m=n => n2
•size of switch memory (SM) and
control memory (CM) grows
linearly as long as memory speed
is sufficient, i.e. SM + CM + input
buffering + output buffering
= 2 x 2 x number of time-slots
•output bit rate determines the
speed requirement for the switch
components
•both input and output lines deploy
“bus”structure
=> fault location difficult
© P. Raatikainen
•a simple and cost effective
structure when memory speed is
sufficient
•speed of available memory
determines the maximum switching
capacity
Switching Technology / 2007
L2 - 74
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