PCM1792
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
FEATURES
D 24-Bit Resolution
D Analog Performance:
− Dynamic Range:
− 132 dB (9 V rms, Mono)
− 129 dB (4.5 V rms, Stereo)
− 127 dB (2 V rms, Stereo)
− THD+N: 0.0004%
D Differential Current Output: 7.8 mA p-p
D 8× Oversampling Digital Filter:
− Stop-Band Attenuation: –130 dB
− Pass-Band Ripple: ±0.00001 dB
D Sampling Frequency: 10 kHz to 200 kHz
D System Clock: 128, 192, 256, 384, 512, or
768 fS With Autodetect
D Accepts 16-, 20-, and 24-Bit Audio Data
D PCM Data Formats: Standard, I2S, and
Left-Justified
D DSD Format Interface Available
D Optional Interface to External Digital Filter or
DSP Available
D TDMCA or Serial Port (SPI/I2C)
D User-Programmable Mode Controls:
− Digital Attenuation: 0 dB to –120 dB,
0.5 dB/Step
− Digital De-Emphasis
− Digital Filter Rolloff: Sharp or Slow
− Soft Mute
− Zero Flag for Each Output
D Dual Supply Operation:
− 5-V Analog, 3.3-V Digital
D 5-V Tolerant Digital Inputs
D Small 28-Lead SSOP Package
APPLICATIONS
D A/V Receivers
D SACD Player
D DVD Players
D HDTV Receivers
D Car Audio Systems
D Digital Multitrack Recorders
D Other Applications Requiring 24-Bit Audio
DESCRIPTION
The PCM1792 is a monolithic CMOS integrated circuit that
includes stereo digital-to-analog converters and support
circuitry in a small 28-lead SSOP package. The data
converters use TI’s advanced segment DAC architecture
to achieve excellent dynamic performance and improved
tolerance to clock jitter. The PCM1792 provides balanced
current outputs, allowing the user to optimize analog
performance externally. The PCM1792 accepts PCM and
DSD audio data formats, providing easy interfacing to
audio DSP and decoder chips. The PCM1792 also
accepts to interface external digital filter devices (DF1704,
DF1706, PMD200). Sampling rates up to 200 kHz are
supported. A full set of user-programmable functions is
accessible through an SPI or I2C serial control port, which
supports register write and readback functions. The
PCM1792 also supports the time division multiplexed
command and audio (TDMCA) data format.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright  2006, Texas Instruments Incorporated
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE CODE
OPERATION
TEMPERATURE
RANGE
PACKAGE
MARKING
PCM1792DB
28-lead SSOP
28DB
−25°C to 85°C
PCM1792
ORDERING
NUMBER
TRANSPORT
MEDIA
PCM1792DB
Tube
PCM1792DBR
Tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
PCM1792
VCC1, VCC2L, VCC2R
VDD
Supply voltage
−0.3 V to 6.5 V
−0.3 V to 4 V
±0.1 V
Supply voltage differences: VCC1, VCC2L and VCC2R
±0.1 V
Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R, and DGND
LRCK, DATA, BCK, SCK, MSEL, RST, MS(2), MDI, MC, MDO(2), ZEROL(2), ZEROR(2)
Digital input
–0.3 V to 6.5 V
ZEROL(3), ZEROR(3), MDO(3), MS(3)
voltage
–0.3 V to (VDD + 0.3 V) < 4 V
–0.3 V to (VCC + 0.3 V) < 6.5 V
Analog input voltage
±10 mA
Input current (any pins except supplies)
Ambient temperature under bias
–40°C to 125°C
Storage temperature
–55°C to 150°C
Junction temperature
150°C
Lead temperature (soldering)
260°C, 5 s
Package temperature (IR reflow, peak)
250°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input mode or I2C mode.
(3) Output mode except for I2C mode.
ELECTRICAL CHARACTERISTICS
all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted
PCM1792DB
PARAMETER
TEST CONDITIONS
MIN
TYP
RESOLUTION
MAX
24
UNIT
Bits
DATA FORMAT (PCM Mode)
Standard, I2S, left justified
Audio data interface format
fS
Audio data bit length
16-, 20-, 24-bit selectable
Audio data format
MSB first, 2s complement
Sampling frequency
10
System clock frequency
200
kHz
128, 192, 256, 384, 512, 768 fS
DATA FORMAT (DSD Mode)
Audio data interface format
fS
DSD (direct stream digital)
Audio data bit length
1 Bit
Sampling frequency
2.8224
System clock frequency
2.8224
MHz
11.2896
MHz
DIGITAL INPUT/OUTPUT
Logic family
TTL compatible
VIH
VIL
Input logic level
IIH
IIL
Input logic current
VIN = VDD
VIN = 0 V
VOH
VOL
Output logic level
IOH = −2 mA
IOL = 2 mA
2
2
0.8
10
–10
VDC
µA
2.4
0.4
VDC
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted
PCM1792DB
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
fS = 44.1 kHz
fS = 96 kHz
0.0004%
0.0008%
fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
0.0015%
UNIT
DYNAMIC PERFORMANCE (PCM MODE, 2-V RMS OUTPUT) (1)(2)
THD+N at VOUT = 0 dB
Dynamic range
Channel separation
Dynamic range
Signal-to-noise ratio
Channel separation
127
127
EIAJ, A-weighted, fS = 192 kHz
127
123
127
EIAJ, A-weighted, fS = 192 kHz
127
fS = 44.1 kHz
fS = 96 kHz
120
dB
127
EIAJ, A-weighted, fS = 96 kHz
fS = 192 kHz
Level Linearity Error
VOUT = −120 dB
DYNAMIC PERFORMANCE (PCM Mode, 4.5-V RMS Output) (1)(3)
THD+N at VOUT = 0 dB
123
EIAJ, A-weighted, fS = 96 kHz
EIAJ, A-weighted, fS = 44.1 kHz
Signal-to-noise ratio
0.0008%
dB
123
122
dB
120
±1
fS = 44.1 kHz
fS = 96 kHz
0.0004%
fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
0.0015%
EIAJ, A-weighted, fS = 96 kHz
EIAJ, A-weighted, fS = 192 kHz
129
EIAJ, A-weighted, fS = 44.1 kHz
129
EIAJ, A-weighted, fS = 96 kHz
129
EIAJ, A-weighted, fS = 192 kHz
129
fS = 44.1 kHz
fS = 96 kHz
124
fS = 192 kHz
121
fS = 44.1 kHz
fS = 96 kHz
0.0004%
fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
0.0015%
dB
0.0008%
129
dB
129
123
dB
dB
DYNAMIC PERFORMANCE (MONO MODE) (1)(3)
THD+N at VOUT = 0 dB
Dynamic range
Signal-to-noise ratio
0.0008%
132
EIAJ, A-weighted, fS = 96 kHz
132
EIAJ, A-weighted, fS = 192 kHz
132
EIAJ, A-weighted, fS = 44.1 kHz
132
EIAJ, A-weighted, fS = 96 kHz
EIAJ, A-weighted, fS = 192 kHz
132
dB
dB
132
(1) Filter condition:
THD+N: 20-Hz HPF, 20-kHz apogee LPF
Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Channel separation: 20-Hz HPF, 20-kHz AES17 LPF
Analog performance specifications are measured using the System Twot Cascade audio measurement system by Audio Precision in the
averaging mode.
(2) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 36.
(3) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 37.
Audio Precision and System Two are trademarks of Audio Precision, Inc.
Other trademarks are the property of their respective owners.
3
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted
PCM1792DB
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
MAX
DSD MODE DYNAMIC PERFORMANCE (1) (2) (44.1 kHz, 64 fS)
THD+N at fS
4.5 V rms
Dynamic range
–60 dB, EIAJ, A-weighted
0.0005%
128
dB
Signal-to-noise ratio
EIAJ, A-weighted
128
dB
ANALOG OUTPUT
Gain error
–6
±2
6
% of FSR
Gain mismatch, channel-to-channel
–3
±0.5
3
% of FSR
–2
±0.5
2
% of FSR
Bipolar zero error
At BPZ
Output current
Full scale (0 dB)
Center current
At BPZ
7.8
mA p-p
–6.2
mA
DIGITAL FILTER PERFORMANCE
±0.004
De-emphasis error
dB
FILTER CHARACTERISTICS–1: SHARP ROLL OFF
Pass band
±0.00001 dB
0.454 fS
–3 dB
Stop band
0.49 fS
0.546 fS
±0.00001
Pass-band ripple
Stop-band attenuation
Stop band = 0.546 fS
–130
Delay time
dB
dB
55/fS
s
FILTER CHARACTERISTICS–2: SLOW ROLL OFF
Pass band
±0.04 dB
0.254 fS
–3 dB
Stop band
0.46 fS
0.732 fS
±0.001
Pass-band ripple
Stop-band attenuation
Stop band = 0.732 fS
–100
dB
dB
Delay time
18/fS
s
(1) Filter condition:
THD+N: 20-Hz HPF, 20-kHz apogee LPF
Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Channel separation: 20-Hz HPF, 20-kHz AES17 LPF
Analog performance specifications are measured using the System Two Cascade audio measurement system by Audio Precision in the averaging
mode.
(2) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 38.
4
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted
PCM1792DB
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY REQUIREMENTS
VDD
VCC1
VCC2L
3
3.3
3.6
VDC
4.75
5
5.25
VDC
fS = 44.1 kHz
fS = 96 kHz
12
15
fS = 192 kHz
fS = 44.1 kHz
45
fS = 96 kHz
fS = 192 kHz
35
fS = 44.1 kHz
fS = 96 kHz
205
fS = 192 kHz
335
Voltage range
VCC2R
IDD
ICC
Supply current (1)
Supply current (1)
Power dissipation (1)
23
33
mA
40
mA
37
250
250
mW
TEMPERATURE RANGE
Operation temperature
–25
θJA
Thermal resistance
(1) Input is BPZ data.
28-pin SSOP
85
100
°C
°C/W
PIN ASSIGNMENTS
PCM1792
(TOP VIEW)
ZEROL
ZEROR
MSEL
LRCK
DATA
BCK
SCK
DGND
VDD
MS
MDI
MC
MDO
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC2L
AGND3L
IOUTL−
IOUTL+
AGND2
VCC1
VCOML
VCOMR
IREF
AGND1
IOUTR−
IOUTR+
AGND3R
VCC2R
5
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
Terminal Functions
TERMINAL
NAME
PIN
I/O
DESCRIPTIONS
AGND1
19
−
Analog ground (internal bias)
AGND2
24
−
Analog ground (internal bias)
AGND3L
27
−
Analog ground (L-channel DACFF)
AGND3R
16
−
BCK
6
I
Analog ground (R-channel DACFF)
Bit clock input(1)
DATA
5
I
Serial audio data input for normal operation(1)
DGND
8
−
Digital ground
IOUTL+
IOUTL–
25
O
L-channel analog current output+
26
O
L-channel analog current output–
IOUTR+
IOUTR–
17
O
R-channel analog current output+
18
O
R-channel analog current output–
IREF
LRCK
20
−
Output current reference bias pin
4
I
MC
12
I
Left and right clock (fS) input for normal operation(1)
Mode control clock input(1)
MDI
11
I
Mode control data input(1)
MDO
13
I/O
MS
10
I/O
MSEL
3
I
RST
14
I
I2C/SPI select(1)
Reset(1)
SCK
7
I
System clock input(1)
VCC1
VCC2L
23
−
Analog power supply, 5 V
28
−
Analog power supply (L-channel DACFF), 5 V
VCC2R
VCOML
15
−
Analog power supply (R-channel DACFF), 5 V
22
−
L-channel internal bias decoupling pin
VCOMR
VDD
21
−
R-channel internal bias decoupling pin
9
−
ZEROL
1
I/O
Digital power supply, 3.3 V
Zero flag for L-channel(2)
Mode control readback data output(3)
Mode control chip-select input(2)
ZEROR
2
I/O
Zero flag for R-channel(2)
(1) Schmitt-trigger input, 5-V tolerant
(2) Schmitt-trigger input and output. 5-V tolerant input and CMOS output
(3) Schmitt-trigger input and output. 5-V tolerant input. In I2C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a CMOS
output.
6
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
FUNCTIONAL BLOCK DIAGRAM
IOUTL−
LRCK
BCK
Current
Segment
DAC
Audio
Data Input
I/F
RST
IOUTL+
8
Oversampling
Digital
Filter
and
Function
Control
MDO
MDI
VCOML
Advanced
Segment
DAC
Modulator
Bias
and
Vref
MC
IREF
VCOMR
Current
Segment
DAC
MSEL
VOUTR
IOUTR+
I/V and Filter
System
Clock
Manager
VCC2R
VCC1
AGND3L
AGND2
AGND1
VDD
Power Supply
DGND
Zero
Detect
SCK
ZEROL
ZEROR
I/V and Filter
IOUTR−
Function
Control
I/F
AGND3R
MS
VOUTL
VCC2L
DATA
7
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
TYPICAL PERFORMANCE CURVES
DIGITAL FILTER
Digital Filter Response
AMPLITUDE
vs
FREQUENCY
0
2
0.00002
−50
1
0.00001
−100
Amplitude − dB
Amplitude − dB
AMPLITUDE
vs
FREQUENCY
−150
−1
−0.00001
−200
0
1
2
3
4
0
−2
−0.00002
0.0
0.1
Frequency [× fS]
0.2
0.3
0.4
0.5
Frequency [× fS]
Figure 1. Frequency Response, Sharp Rolloff
Figure 2. Pass-Band Ripple, Sharp Rolloff
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
0
−2
−4
−50
Amplitude − dB
Amplitude − dB
−6
−100
−8
−10
−12
−14
−150
−16
−18
−200
0
1
2
3
4
Frequency [× fS]
Figure 3. Frequency Response, Slow Rolloff
8
−20
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency [× fS]
Figure 4. Transition Characteristics, Slow Rolloff
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De-Emphasis Filter
DE-EMPHASIS LEVEL
vs
FREQUENCY
DE-EMPHASIS ERROR
vs
FREQUENCY
0
20
0.020
fS = 32 kHz
fS = 32 kHz
15
0.015
De-Emphasis Error − dB
De-Emphasis Level − dB
−2
−4
−6
10
0.010
5
0.005
0
−5
−0.005
−10
−0.010
−8
−15
−0.015
−10
−20
−0.020
0
2
4
6
8
10
12
14
0
2
4
6
f − Frequency − kHz
8
10
12
14
f − Frequency − kHz
Figure 5
Figure 6
DE-EMPHASIS LEVEL
vs
FREQUENCY
DE-EMPHASIS ERROR
vs
FREQUENCY
0
20
0.020
fS = 44.1 kHz
fS = 44.1 kHz
15
0.015
De-Emphasis Error − dB
De-Emphasis Level − dB
−2
−4
−6
10
0.010
5
0.005
0
−5
−0.005
−10
−0.010
−8
−15
−0.015
−10
−20
−0.020
0
2
4
6
8
10
12
14
f − Frequency − kHz
Figure 7
16
18
20
0
2
4
6
8
10
12
14
16
18
20
f − Frequency − kHz
Figure 8
9
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
De-Emphasis Filter (Continued)
DE-EMPHASIS LEVEL
vs
FREQUENCY
DE-EMPHASIS ERROR
vs
FREQUENCY
0
20
0.020
fS = 48 kHz
fS = 48 kHz
15
0.015
De-Emphasis Error − dB
De-Emphasis Level − dB
−2
−4
−6
10
0.010
5
0.005
0
−5
−0.005
−10
−0.010
−8
−15
−0.015
−10
−20
−0.020
0
2
4
6
8
10
12
14
f − Frequency − kHz
Figure 9
10
16
18
20
22
0
2
4
6
8
10
12
14
f − Frequency − kHz
Figure 10
16
18
20
22
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
ANALOG DYNAMIC PERFORMANCE
Supply Voltage Characteristics
TOTAL HARMONIC DISTORTION + NOISE
vs
SUPPLY VOLTAGE
DYNAMIC RANGE
vs
SUPPLY VOLTAGE
132
130
fS = 96 kHz
Dynamic Range − dB
THD+N − Total Harmonic Distortion + Noise − %
0.01
fS = 192 kHz
0.001
fS = 96 kHz
fS = 48 kHz
128
fS = 192 kHz
126
124
fS = 48 kHz
0.0001
4.50
4.75
5.00
5.25
122
4.50
5.50
VCC − Supply Voltage − V
4.75
5.50
CHANNEL SEPARATION
vs
SUPPLY VOLTAGE
132
130
130
128
Channel Separation − dB
SNR − Signal-to-Noise Ratio − dB
SIGNAL-to-NOISE RATIO
vs
SUPPLY VOLTAGE
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz
126
124
122
4.50
5.25
Figure 12
Figure 11
128
5.00
VCC − Supply Voltage − V
126
124
fS = 96 kHz
fS = 48 kHz
fS = 192 kHz
122
4.75
5.00
5.25
VCC − Supply Voltage − V
5.50
120
4.50
4.75
5.00
5.25
5.50
VCC − Supply Voltage − V
Figure 13
Figure 14
NOTE: PCM mode, TA = 25°C, VDD = 3.3 V, measurement circuit is Figure 37 (VOUT = 4.5 V rms).
11
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Temperature Characteristics
TOTAL HARMONIC DISTORTION + NOISE
vs
FREE-AIR TEMPERATURE
DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
132
130
Dynamic Range − dB
THD+N − Total Harmonic Distortion + Noise − %
0.01
fS = 192 kHz
0.001
fS = 96 kHz
128
fS = 96 kHz
fS = 48 kHz
126
124
fS = 48 kHz
0.0001
−50
−25
0
25
50
75
122
−50
100
TA − Free-Air Temperature − °C
−25
0
75
100
CHANNEL SEPARATION
vs
FREE-AIR TEMPERATURE
132
130
130
128
fS = 96 kHz
Channel Separation − dB
SNR − Signal-to-Noise Ratio − dB
50
Figure 16
SIGNAL-to-NOISE RATIO
vs
FREE-AIR TEMPERATURE
128
fS = 192 kHz
fS = 48 kHz
126
124
122
−50
25
TA − Free-Air Temperature − °C
Figure 15
126
fS = 48 kHz
124
fS = 192 kHz
fS = 96 kHz
122
−25
0
25
50
TA − Free-Air Temperature − °C
75
100
120
−50
−25
0
25
50
TA − Free-Air Temperature − °C
Figure 17
NOTE: PCM mode, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 37 (VOUT = 4.5 V rms).
12
fS = 192 kHz
Figure 18
75
100
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AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
0
−20
−20
−40
−60
Amplitude − dB
Amplitude − dB
−40
−80
−100
−120
−60
−80
−100
−120
−140
−140
−160
−180
−160
0
2
4
6
8
10
12
14
16
18
0
20
10
20
30
f − Frequency − kHz
40
50
60
70
80
90 100
f − Frequency − kHz
Figure 19. −60-dB Output Spectrum, BW = 20 kHz
Figure 20. −60-dB Output Spectrum, BW = 100 kHz
NOTE: PCM mode, fS = 48 kHz, 32,768 point 8 average, TA = 25°C, VDD = 3.5 V VCC = 5 V, measurement circuit is Figure 37.
TOTAL HARMONIC DISTORTION + NOISE
vs
INPUT LEVEL
THD+N − Total Harmonic Distortion + Noise − %
10
1
0.1
0.01
0.001
0.0001
−100
−80
−60
−40
−20
0
Input Level − dBFS
Figure 21. THD+N vs Input Level, PCM Mode
NOTE: PCM mode, fS = 48 kHz, TA = 25°C, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 37.
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
AMPLITUDE
vs
FREQUENCY
0
−20
Amplitude − dB
−40
−60
−80
−100
−120
−140
−160
0
2
4
6
8
10
12
14
16
18
20
f − Frequency − kHz
Figure 22. −60-dB Output Spectrum, DSD Mode
NOTE: DSD mode (FIR-4), 32,768 point 8 average, TA = 25°C, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 38.
AMPLITUDE
vs
FREQUENCY
−130
−133
−136
Amplitude − dB
−139
−142
−145
−148
−151
−154
−157
−160
0
2
4
6
8
10
12
14
16
18
20
f − Frequency − kHz
Figure 23. −150-dB Output Spectrum, DSD Mono Mode
NOTE: DSD mode (FIR-4), 32,768 point 8 average, TA = 25°C, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 38.
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The PCM1792 requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 7). The PCM1792 has a system clock detection circuit
that automatically senses if the system clock is operating between 128 fS and 768 fS. Table 1 shows examples of
system clock frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma modulator
is selected as 128 fS, the system clock frequency is over 256 fS.
Figure 24 shows the timing requirements for the system clock input. For optimal performance, it is important to use
a clock source with low phase jitter and noise. One of the Texas Instruments’ PLL1700 family of multiclock generators
is an excellent choice for providing the PCM1792 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
SYSTEM CLOCK FREQUENCY (fSCK) (MHz)
128 fS
4.096(1)
192 fS
6.144(1)
256 fS
8.192
384 fS
12.288
512 fS
16.384
768 fS
24.576
5.6488(1)
6.144(1)
8.4672
11.2896
16.9344
22.5792
33.8688
48 kHz
9.216
12.288
18.432
96 kHz
12.288
18.432
24.576
36.864
36.864
73.728(1)
36.864
73.728(1)
192 kHz
24.576
49.152(1)
24.576
49.152(1)
(2)
(2)
32 kHz
44.1 kHz
(1) This system clock rate is not supported in I2C fast mode.
(2) This system clock rate is not supported for the given sampling frequency.
t(SCKH)
H
2V
System Clock (SCK)
0.8 V
L
t(SCKL)
PARAMETERS
t(SCY)
MIN
MAX
UNITS
t(SCY) System clock pulse cycle time
t(SCKH) System clock pulse duration, HIGH
13
ns
0.4t(SCY)
ns
t(SCKL) System clock pulse duration, LOW
0.4t(SCY)
ns
Figure 24. System Clock Input Timing
Power-On and External Reset Functions
The PCM1792 includes a power-on reset function. Figure 25 shows the operation of this function. With VDD > 2 V,
the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time
VDD > 2 V. After the initialization period, the PCM1792 is set to its default reset state, as described in the MODE
CONTROL REGISTERS section of this data sheet.
The PCM1792 also includes an external reset capability using the RST input (pin 14). This allows an external
controller or master reset circuit to force the PCM1792 to initialize to its default reset state.
Figure 26 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The
RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock
periods. The external reset is especially useful in applications where there is a delay between the PCM1792 power
up and system clock activation.
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
VDD
2.4 V (Max)
2 V (Typ)
1.6 V (Min)
Reset
Reset Removal
Internal Reset
1024 System Clocks
System Clock
Figure 25. Power-On Reset Timing
RST (Pin 14)
50 % of VDD
t(RST)
Reset
Reset Removal
Internal Reset
1024 System Clocks
System Clock
t(RST)
PARAMETERS
MIN
Reset pulse duration, LOW
20
Figure 26. External Reset Timing
16
MAX
UNITS
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
AUDIO DATA INTERFACE
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the
serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio
interface. Serial data is clocked into the PCM1792 on the rising edge of BCK. LRCK is the serial audio left/right word
clock.
The PCM1792 requires the synchronization of LRCK and system clock, but does not need a specific phase relation
between LRCK and system clock.
If the relationship between LRCK and system clock changes more than ±6 BCK, internal operation is initialized within
1/fS and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock
is completed.
PCM Audio Data Formats and Timing
The PCM1792 supports industry-standard audio data formats, including standard right-justified, I2S, and
left-justified. The data formats are shown in Figure 28. Data formats are selected using the format bits, FMT[2:0],
in control register 18. The default data format is 24-bit I2S. All formats require binary 2s complement, MSB-first audio
data. Figure 27 shows a detailed timing diagram for the serial audio interface.
50% of VDD
LRCK
t(BCH)
t(BCL)
t(LB)
50% of VDD
BCK
t(BCY)
t(BL)
50% of VDD
DATA
t(DS)
t(DH)
PARAMETERS
MIN
MAX
UNITS
t(BCY)
t(BCL)
BCK pulse cycle time
70
ns
BCK pulse duration, LOW
30
ns
t(BCH)
t(BL)
BCK pulse duration, HIGH
30
ns
BCK rising edge to LRCK edge
10
ns
t(LB)
t(DS)
LRCK edge to BCK rising edge
10
ns
DATA setup time
10
ns
t(DH)
—
DATA hold time
10
ns
LRCK clock duty
50% ± 2 bit clocks
Figure 27. Timing of Audio Interface
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(1) Standard Data Format (Right Justified) ; L-Channel = HIGH, R-Channel = LOW
1/fS
LRCK
R-Channel
L-Channel
BCK
Audio Data Word = 16-Bit
DATA
14 15 16
1
2
MSB
15 16
1
2
15 16
LSB
Audio Data Word = 20-Bit
DATA
18 19 20
1
2
19 20
1
2
19 20
LSB
MSB
Audio Data Word = 24-Bit
DATA
22 23 24
1
2
23 24
1
2
23 24
LSB
MSB
(2) Left Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS
LRCK
R-Channel
L-Channel
BCK
Audio Data Word = 24-Bit
DATA
1
2
23 24
1
2
23 24
1
2
LSB
MSB
(3) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
1/fS
LRCK
L-Channel
R-Channel
BCK
Audio Data Word = 16-Bit
DATA
1
2
15 16
MSB
1
2
1
2
15 16
1
2
1
2
LSB
Audio Data Word = 24-Bit
DATA
1
2
23 24
MSB
LSB
Figure 28. Audio Data Input Formats
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
External Digital Filter Interface and Timing
The PCM1792 supports an external digital filter interface comprising a 3- or 4-wire synchronous serial port, which
allows the use of an external digital filter. External filters include the Texas Instruments’ DF1704 and DF1706, the
Pacific Microsonics PMD200, or a programmable digital signal processor.
In the external DF mode, LRCK (pin 4), BCK (pin 6) and DATA (pin 5) are defined as WDCK, the word clock; BCK,
the bit clock; and DATA, the monaural data. The external digital filter interface is selected by using the DFTH bit of
control register 20, which functions to bypass the internal digital filter of the PCM1792.
When the DFMS bit of control register 19 is set, the PCM1792 can process stereo data. In this case, ZEROL (pin 1)
and ZEROR (pin 2) are defined as L-channel data and R-channel data, respectively.
Detailed information for the external digital filter interface mode is provided in the APPLICATION FOR EXTERNAL
DIGITAL FILTER INTERFACE section of this data sheet.
Direct Stream Digital (DSD) Format Interface and Timing
The PCM1792 supports the DSD-format interface operation, which includes out-of-band noise filtering using an
internal analog FIR filter. For DSD operation, SCK (pin 7) is redefined as BCK, DATA (pin 5) as DATAL (left channel
audio data), and LRCK (pin 4) as DATAR (right channel audio data). BCK (pin 6) must be forced low in the DSD mode.
The DSD-format interface is activated by setting the DSD bit of control register 20.
Detailed information for the DSD mode is provided in the APPLICATION FOR DSD-FORMAT (DSD MODE)
INTERFACE section of this data sheet.
TDMCA Interface
The PCM1792 supports the time-division-multiplexed command and audio (TDMCA) data format to enable control
of and communication with a number of external devices over a single serial interface.
Detailed information for the TDMCA format is provided in the TDMCA Format section of this data sheet.
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FUNCTION DESCRIPTIONS
Zero Detect
The PCM1792 has a zero-detect function. When the PCM1792 detects the zero conditions as shown in Table 2, the
PCM1792 sets ZEROL (pin 1) and ZEROR (pin 2) to HIGH.
Table 2. Zero Conditions
MODE
DETECTING CONDITION AND TIME
PCM
DATA is continuously LOW for 1024 LRCKs.
External DF Mode
DATA is continuously LOW for 1024 WDCKs.
DZ0
There are and equal number of 1s and 0s in every 8 bits of DSD
input data for 200 ms.
DZ1
The input data is 1001 0110 continuously for 200 ms.
DSD
Serial Control Interface
The PCM1792 supports SPI and I2C that sets mode control registers as shown in Table 4. This serial control interface
is selected by MSEL (pin 3); SPI is activated when MSEL is set to LOW, and I2C is activated when MSEL is set to
HIGH.
SPI Interface
The SPI interface is a 4-wire synchronous serial port which operates asynchronously to the serial audio interface and
the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers. The
control interface includes MDO (pin 13), MDI (pin 11), MC (pin 12), and MS (pin 10). MDO is the serial data output,
used to read back the values of the mode registers; MDI is the serial data input, used to program the mode registers;
MC is the serial bit clock, used to shift data in and out of the control port, and MS is the mode control enable, used
to enable the internal mode register access.
Register Read/Write Operation
All read/write operations for the serial control port use 16-bit data words. Figure 29 shows the control data word
format. The most significant bit is the read/write (R/W) bit. For write operations, the R/W bit must be set to 0. For
read operations, the R/W bit must be set to 1. There are seven bits, labeled IDX[6:0], that hold the register index (or
address) for the read and write operations. The least significant eight bits, D[7:0], contain the data to be written to,
or the data that was read from, the register specified by IDX[6:0].
Figure 30 shows the functional timing diagram for writing or reading the serial control port. MS is held at a logic 1
state until a register needs to be written or read. To start the register write or read cycle, MS is set to logic 0. Sixteen
clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI and readback data
on MDO. After the eighth clock cycle has completed, the data from the indexed-mode control register appears on
MDO during the read operation. After the sixteenth clock cycle has completed, the data is latched into the
indexed-mode control register during the write operation. To write or read subsequent data, MS must be set to 1 once.
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LSB
MSB
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
D7
D6
D5
Register Index (or Address)
D4
D3
D2
D1
D0
Register Data
Figure 29. Control Data Word Format for MDI
MS
MC
MDI
R/W
A6
A5
A4
A3
A2
A1
A0
High Impedance
MDO
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
When Read Mode is Instructed
NOTE: Bit 15 is used for selection of write or read. Setting R/W = 0 indicates a write, while R/W = 1 indicates a read. Bits 14−8 are used for the register
address. Bits 7–0 are used for register data.
Figure 30. Serial Control Format
t(MHH)
MS
50% of VDD
t(MSS)
t(MCL)
t(MCH)
t(MSH)
MC
50% of VDD
t(MCY)
LSB
MDI
t(MDS)
50% of VDD
t(MOS)
t(MDH)
MDO
50% of VDD
PARAMETER
t(MCY)
t(MCL)
MC pulse cycle time
t(MCH)
t(MHH)
MIN
MAX
UNITS
100
ns
MC low-level time
40
ns
MC high-level time
40
ns
MS high-level time
80
ns
t(MSS)
t(MSH)
MS falling edge to MC rising edge
MS hold time(1)
15
ns
15
ns
t(MDH)
t(MDS)
MDI hold time
15
ns
MDI setup time
15
t(MOS) MC falling edge to MDO stable
(1) MC rising edge for LSB to MS rising edge
ns
30
ns
Figure 31. Control Interface Timing
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
I2C Interface
The PCM1792 supports the I2C serial bus and the data transmission protocol for standard and fast mode as a slave
device. This protocol is explained in I2C specification 2.0.
In I2C mode, the control terminals are changed as follows.
TERMINAL NAME
TDMCA NAME
PROPERTY
MS
ADR0
Input
MDI
ADR1
Input
DESCRIPTION
I2C address 0
MC
SCL
Input
I2C address 1
I2C clock
MDO
SDA
Input/output
I2C data
Slave Address
MSB
LSB
1
0
0
1
1
ADR1
ADR0
R/W
The PCM1792 has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory preset
to 10011. The next two bits of the address byte are the device select bits which can be user-defined by the ADR1
and ADR0 terminals. A maximum of four PCM1792s can be connected on the same bus at one time. Each PCM1792
responds when it receives its own slave address.
Packet Protocol
A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data
if write or acknowledge if read, and stop condition. The PCM1792 supports only slave receivers and slave
transmitters.
SDA
SCL
St
1−7
8
9
1−8
9
1−8
9
9
Slave Address
R/W
ACK
DATA
ACK
DATA
ACK
ACK
R/W: Read Operation if 1; Otherwise, Write Operation
DATA: 8 Bits (Byte)
ACK: Acknowledgement of a Byte if 0
NACK:Not Acknowledgement if 1
Start
Condition
Write Operation
Sp
Stop
Condition
Transmitter
M
M
M
S
M
S
M
S
S
M
Data Type
St
Slave Address
W
ACK
DATA
ACK
DATA
ACK
ACK
Sp
Read Operation
Transmitter
M
M
M
S
S
M
S
M
M
M
Data Type
St
Slave Address
R
ACK
DATA
ACK
DATA
ACK
NACK
Sp
M: Master Device
S: Slave Device
St: Start Condition
Sp: Stop Condition
W: Write
R: Read
Figure 32. Basic I2C Framework
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Write Register
A master can write to any PCM1792 registers using single or multiple accesses. The master sends a PCM1792 slave
address with a write bit, a register address, and the data. If multiple access is required, the address is that of the
starting register, followed by the data to be transferred. When the data are received properly, the index register is
incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. When undefined
registers are accessed, the PCM1792 does not send an acknowledgement. The Figure 33 is a diagram of the write
operation.
Transmitter
M
M
M
S
M
S
M
S
M
S
S
M
Data Type
St
Slave Address
W
ACK
Reg Address
ACK
Write Data 1
ACK
Write Data 2
ACK
ACK
Sp
M: Master Device
S: Slave Device
St: Start Condition
ACK: Acknowledge
Sp: Stop Condition
W: Write
Figure 33. Write Operation
Read Register
A master can read the PCM1792 register. The value of the register address is stored in an indirect index register in
advance. The master sends a PCM1792 slave address with a read bit after storing the register address. Then the
PCM1792 transfers the data which the index register points to. When the data are transferred during a multiple
access, the index register is incremented by 1 automatically. (When first going into read mode immediately following
a write, the index register is not incremented. The master can read the register that was previously written.) When
the index register reaches 0x7F, the next value is 0x0. The PCM1792 outputs some data when the index register
is 0x10 to 0x1F, even if it is not defined in Table 4. Figure 34 is a diagram of the read operation.
Transmitter
M
M
M
Data Type
St
Slave Address
W
S
M
S
ACK Reg Address ACK
M
M
M
S
Slave
M
S
M
Sr
Slave Address
R
ACK
Data
ACK
NACK
Sp
M: Master Device
S: Slave Device
St: Start Condition
Sr: Repeated Start Condition ACK: Acknowledge
W: Write
R: Read
Sp: Stop Condition
NACK: Not Acknowledge
Figure 34. Read Operation
Noise Suppression
The PCM1792 incorporates noise suppression using the system clock (SCK). However, there must be no more than
two noise spikes in 600 ns. The noise suppression works for SCK frequencies between 8 MHz and 40 MHz in fast
mode. However, it works incorrectly in the following conditions.
Case 1:
1. t(SCK) > 120 ns (t(SCK): period of SCK)
2. t(HI) + t(D−HD) < t(SCK) × 5
3. Spike noise exists on the first half of the SCL HIGH pulse.
4. Spike noise exists on the SDA HIGH pulse just before SDA goes LOW.
SCL
Noise
SDA
When these conditions occur at the same time, the data is recognized as LOW.
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
Case 2:
1. t(SCK) > 120 ns
2. t(S−HD) or t(RS−HD) < t(SCK) × 5
3. Spike noise exists on both SCL and SDA during the hold time.
SCL
Noise
SDA
When these conditions occur at the same time, the PCM1792 fails to detect a start condition.
Case 3:
1. t(SCK) < 50 ns
2. t(SP) > t(SCK)
3. Spike noise exists on SCL just after SCL goes LOW.
4. Spike noise exists on SDA just before SCL goes LOW.
SCL
SDA
Noise
When these conditions occur at the same time, the PCM1792 erroneously detects a start or stop condition.
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
TIMING DIAGRAM
Start
Repeated Start
Stop
t(D-HD)
t(BUF)
t(D-SU)
t(SDA-F)
t(P-SU)
t(SDA-R)
SDA
t(SCL-R)
t(RS-HD)
t(SP)
t(LOW)
SCL
t(S-HD)
t(HI)
t(RS-SU)
t(SCL-F)
TIMING CHARACTERISTICS
PARAMETER
f(SCL)
SCL clock frequency
t(BUF)
Bus free time between stop and start conditions
t(LOW)
Low period of the SCL clock
t(HI)
High period of the SCL clock
t(RS-SU)
t(S-HD)
t(RS-HD)
Setup time for (repeated) start condition
Hold time for (repeated) start condition
t(D-SU)
Data setup time
t(D-HD)
Data hold time
t(SCL-R)
Rise time of SCL signal
Rise time of SCL signal after a repeated start condition and after an
t(SCL-R1)
acknowledge bit
t(SCL-F)
Fall time of SCL signal
t(SDA-R)
Rise time of SDA signal
t(SDA-F)
Fall time of SDA signal
t(P-SU)
Setup time for stop condition
C(B)
t(SP)
Capacitive load for SDA and SCL line
VNH
Noise margin at high level for each connected device (including hysteresis)
Pulse duration of suppressed spike
CONDITIONS
MIN
MAX
Standard
100
Fast
400
Standard
4.7
Fast
1.3
Standard
4.7
Fast
1.3
Standard
UNIT
kHz
µs
µs
µs
4
Fast
600
ns
Standard
4.7
µs
Fast
600
ns
4
µs
Fast
600
ns
Standard
250
Fast
100
Standard
ns
Standard
0
900
Fast
0
900
Standard
20 + 0.1 CB
1000
Fast
20 + 0.1 CB
300
Standard
20 + 0.1 CB
1000
Fast
20 + 0.1 CB
300
Standard
20 + 0.1 CB
1000
Fast
20 + 0.1 CB
300
Standard
20 + 0.1 CB
1000
Fast
20 + 0.1 CB
300
Standard
20 + 0.1 CB
1000
Fast
20 + 0.1 CB
300
Standard
Fast
ns
ns
ns
ns
ns
µs
4
600
Fast
ns
ns
400
pF
50
ns
Standard
Fast
0.2 VDD
V
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
MODE CONTROL REGISTERS
User-Programmable Mode Controls
The PCM1792 includes a number of user-programmable functions which are accessed via mode control registers.
The registers are programmed using the serial control interface, which was previously discussed in this data sheet.
Table 3 lists the available mode-control functions, along with their default reset conditions and associated register
index.
Table 3. User-Programmable Function Controls
FUNCTION
DEFAULT
REGISTER
BIT
PCM
DSD
DF
BYPASS
Digital attenuation control
0 dB to –120 dB and mute, 0.5 dB step
0 dB
Register 16
Register 17
ATL[7:0] (for L-ch)
ATR[7:0] (for R-ch)
yes
Attenuation load control
Disabled, enabled
Attenuation disabled
Register 18
ATLD
yes
Input audio data format selection
16-, 20-, 24-bit standard (right-justified) format
24-bit MSB-first left-justified format
16-/24-bit I2S format
24-bit I2S format
Register 18
FMT[2:0]
yes
Sampling rate selection for de-emphasis
Disabled,44.1 kHz, 48 kHz, 32 kHz
De-emphasis disabled
Register 18
DMF[1:0]
yes
De-emphasis control
Disabled, enabled
De-emphasis disabled
Register 18
DME
yes
Soft mute control
Mute disabled, enabled
Mute disabled
Register 18
MUTE
yes
Output phase reversal
Normal, reverse
Normal
Register 19
REV
yes
Attenuation speed selection
×1fS, ×(1/2)fS, ×(1/4)fS, ×(1/8)fS
DAC operation control
Enabled, disabled
×1 fS
Register 19
ATS[1:0]
yes
DAC operation enabled
Register 19
OPE
yes
Stereo DF bypass mode select
Monaural, stereo
Monaural
Register 19
DFMS
Digital filter rolloff selection
Sharp rolloff, slow rolloff
Sharp rolloff
Register 19
FLT
yes
Infinite zero mute control
Disabled, enabled
Disabled
Register 19
INZD
yes
System reset control
Reset operation , normal operation
Normal operation
Register 20
SRST
yes
yes
DSD interface mode control
DSD enabled, disabled
Disabled
Register 20
DSD
yes
yes
Digital-filter bypass control
DF enabled, DF bypass
DF enabled
Register 20
DFTH
yes
Monaural mode selection
Stereo, monaural
Stereo
Register 20
MONO
yes
yes
yes
Channel selection for monaural mode data
L-channel, R-channel
L-channel
Register 20
CHSL
yes
yes
yes
Delta-sigma oversampling rate selection
×64 fS, ×128 fS, ×32 fS
×64 fS
Register 20
OS[1:0]
yes
yes(2)
yes
PCM zero output enable
Enabled
Register 21
PCMZ
yes
DSD zero output enable
Disabled
Register 21
DZ[1:0]
Not zero = 0
Zero detected = 1
Register 22
ZFGL (for L-ch)
ZFGR (for R-ch)
yes
yes(1)
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Function available only for read
Zero detection flag
Not zero, zero detected
Device ID (at TDMCA)
−
Register 23 ID[4:0]
(1) When in DSD mode, DMF[1:0] is defined as DSD filter (analog FIR) performance selection.
(2) When in DSD mode, OS[1:0] is defined as DSD filter (analog FIR) operation rate selection.
26
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yes
yes
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
Register Map
The mode control register map is shown in Table 4. Registers 16–21 include an R/W bit, which determines whether
a register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only.
Table 4. Mode Control Register Map
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
0
1
0
0
0
0
ATL7
ATL6
ATL5
ATL4
ATL3
ATL2
ATL1
ATL0
Register 17
R/W
0
0
1
0
0
0
1
ATR7
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
Register 18
R/W
0
0
1
0
0
1
0
ATLD
FMT2
FMT1
FMT0
DMF1
DMF0
DME
MUTE
Register 19
R/W
0
0
1
0
0
1
1
REV
ATS1
ATS0
OPE
RSV
DFMS
FLT
INZD
Register 20
R/W
0
0
1
0
1
0
0
RSV
SRST
DSD
DFTH
MONO
CHSL
OS1
OS0
Register 21
R/W
0
0
1
0
1
0
1
RSV
RSV
RSV
RSV
RSV
DZ1
DZ0
PCMZ
Register 22
R
0
0
1
0
1
1
0
RSV
RSV
RSV
RSV
RSV
RSV
ZFGR
ZFGL
Register 23
R
0
0
1
0
1
1
1
RSV
RSV
RSV
ID4
ID3
ID2
ID1
ID0
Register Definitions
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
0
1
0
0
0
0
ATL7
ATL6
ATL5
ATL4
ATL3
ATL2
ATL1
ATL0
Register 17
R/W
0
0
1
0
0
0
1
ATR7 ATR6
ATR5 ATR4
ATR3
ATR2
ATR1
ATR0
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
ATx[7:0]: Digital Attenuation Level Setting
These bits are available for read and write.
Default value: 1111 1111b
Each DAC output has a digital attenuator associated with it. The attenuator can be set from 0 dB to –120 dB, in 0.5-dB
steps. Alternatively, the attenuator can be set to infinite attenuation (or mute).
The attenuation data for each channel can be set individually. However, the data load control (the ATLD bit of control
register 18) is common to both attenuators. ATLD must be set to 1 in order to change an attenuator setting. The
attenuation level can be set using the following formula:
Attenuation level (dB) = 0.5 dB • (ATx[7:0] DEC – 255)
where: ATx[7:0] DEC = 0 through 255
For ATx[7:0] DEC = 0 through 14, the attenuator is set to infinite attenuation. The following table shows attenuation
levels for various settings:
ATx[7:0]
Decimal Value
Attenuation Level Setting
1111 1111b
255
0 dB, no attenuation (default)
1111 1110b
254
–0.5 dB
1111 1101b
253
–1.0 dB
L
L
0001 0000b
16
–119.5 dB
0000 1111b
15
–120.0 dB
0000 1110b
14
Mute
L
L
L
0000 0000b
0
Mute
L
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
Register 18
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
R/W
0
0
1
0
0
1
0
ATLD
FMT2
FMT1
FMT0
B3
B2
DMF1 DMF0
B1
B0
DME
MUTE
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
ATLD: Attenuation Load Control
This bit is available for read and write.
Default value: 0
ATLD = 0
Attenuation control disabled (default)
ATLD = 1
Attenuation control enabled
The ATLD bit is used to enable loading of the attenuation data contained in registers 16 and 17. When ATLD = 0,
the attenuation settings remain at the previously programmed levels, ignoring new data loaded from registers 16 and
17. When ATLD = 1, attenuation data written to registers 16 and 17 is loaded normally.
FMT[2:0]: Audio Interface Data Format
These bits are available for read and write.
Default value: 101
For the external digital filter interface mode (DFTH mode), this register is operated as shown in the Application for
Interfacing With an External Digital Filter section of this data sheet.
FMT[2:0]
Audio Data Format Selection
000
16-bit standard format, right-justified data
001
20-bit standard format, right-justified data
010
24-bit standard format, right-justified data
011
24-bit MSB-first, left-justified format data
100
16-bit I2S format data
101
24-bit I2S format data (default)
110
Reserved
111
Reserved
The FMT[2:0] bits are used to select the data format for the serial audio interface.
DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
These bits are available for read and write.
Default value: 00
DMF[1:0]
De-Emphasis Sampling Frequency Selection
00
Disabled (default)
01
48 kHz
10
44.1 kHz
11
32 kHz
The DMF[1:0] bits are used to select the sampling frequency used by the digital de-emphasis function when it is
enabled by setting the DME bit. The de-emphasis curves are shown in the TYPICAL PERFORMANCE CURVES
section of this data sheet.
For the DSD mode, analog FIR filter performance can be selected using this register. Filter response plots are shown
in the TYPICAL PERFORMANCE CURVES section of this data sheet. A register map is shown in the Configuration
for the DSD Interface Mode section of this data sheet.
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DME: Digital De-Emphasis Control
This bit is available for read and write.
Default value: 0
DME = 0
De-emphasis disabled (default)
DME = 1
De-emphasis enabled
The DME bit is used to enable or disable the de-emphasis function for both channels.
MUTE: Soft Mute Control
This bit is available for read and write.
Default value: 0
MUTE = 0
MUTE disabled (default)
MUTE = 1
MUTE enabled
The MUTE bit is used to enable or disable the soft mute function for both channels.
Soft mute is operated as a 256-step attenuator. The speed for each step to –∞ dB (mute) is determined by the
attenuation rate selected in the ATS register.
Register 19
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R/W
0
0
1
0
0
1
1
REV
ATS1
ATS0
OPE
RSV
DFMS
FLT
INZD
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
REV: Output Phase Reversal
This bit is available for read and write.
Default value: 0
REV = 0
Normal output (default)
REV = 1
Inverted output
The REV bit is used to invert the output phase for both channels.
ATS[1:0]: Attenuation Rate Select
These bits are available for read and write.
Default value: 00
ATS[1:0]
Attenuation Rate Selection
00
LRCK/1 (default)
01
LRCK/2
10
LRCK/4
11
LRCK/8
The ATS[1:0] bits are used to select the rate at which the attenuator is decremented/incremented during level
transitions.
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OPE: DAC Operation Control
This bit is available for read and write.
Default value: 0
OPE = 0
DAC operation enabled (default)
OPE = 1
DAC operation disabled
The OPE bit is used to enable or disable the analog output for both channels. Disabling the analog outputs forces
them to the bipolar zero level (BPZ) even if digital audio data is present on the input.
DFMS: Stereo DF Bypass Mode Select
This bit is available for read and write.
Default value: 0
DFMS = 0
Monaural (default)
DFMS = 1
Stereo input enabled
The DFMS bit is used to enable stereo operation in DF bypass mode. In the DF bypass mode, when DFMS is set
to 0, the pin for the input data is DATA (pin 5) only, therefore the PCM1792 operates as a monaural DAC. When DFMS
is set to 1, the PCM1792 can operate as a stereo DAC with inputs of L-channel and R-channel data on ZEROL
(pin 1) and ZEROR (pin 2), respectively.
FLT: Digital Filter Rolloff Control
This bit is available for read and write.
Default value: 0
FLT = 0
Sharp rolloff (default)
FLT = 1
Slow rolloff
The FLT bit is used to select the digital filter rolloff characteristic. The filter responses for these selections are shown
in the TYPICAL PERFORMANCE CURVES section of this data sheet.
INZD: Infinite Zero Detect Mute Control
This bit is available for read and write.
Default value: 0
INZD = 0
Infinite zero detect mute disabled (default)
INZD = 1
Infinite zero detect mute enabled
The INZD bit is used to enable or disable the zero detect mute function. Setting INZD to 1 forces muted analog outputs
to hold a bipolar zero level when the PCM1792 detects a zero condition in both channels. The infinite zero detect
mute function is disabled in the DSD mode.
Register 20
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R/W
0
0
1
0
1
0
0
RSV
SRST
DSD
DFTH
MONO
CHSL
OS1
OS0
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
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SRST: System Reset Control
This bit is available for write only.
Default value: 0
SRST = 0
Normal operation (default)
SRST = 1
System reset operation (generate one reset pulse)
The SRST bit is used to reset the PCM1792 to the initial system condition.
DSD: DSD Interface Mode Control
This bit is available for read and write.
Default value: 0
DSD = 0
DSD interface mode disabled (default)
DSD = 1
DSD interface mode enabled
The DSD bit is used to enable or disable the DSD interface mode.
DFTH: Digital Filter Bypass (or Through Mode) Control
This bit is available for read and write.
Default value: 0
DFTH = 0
Digital filter enabled (default)
DFTH = 1
Digital filter bypassed for external digital filter
The DFTH bit is used to enable or disable the external digital filter interface mode.
MONO: Monaural Mode Selection
This bit is available for read and write.
Default value: 0
MONO = 0
Stereo mode (default)
MONO = 1
Monaural mode
The MONO function is used to change operation mode from the normal stereo mode to the monaural mode. When
the monaural mode is selected, both DACs operate in a balanced mode for one channel of audio input data. Channel
selection is available for L-channel or R-channel data, determined by the CHSL bit as described immediately
following.
CHSL: Channel Selection for Monaural Mode
This bit is available for read and write.
Default value: 0
This bit is available when MONO = 1.
CHSL = 0
L-channel selected (default)
CHSL = 1
R-channel selected
The CHSL bit selects L-channel or R-channel data to be used in monaural mode.
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OS[1:0]: Delta-Sigma Oversampling Rate Selection
These bits are available for read and write.
Default value: 00
Operation Speed Select
OS[1:0]
00
64 times fS (default)
01
32 times fS
10
128 times fS
11
Reserved
The OS bits are used to change the oversampling rate of delta-sigma modulation. Use of this function enables the
designer to stabilize the conditions at the post low-pass filter for different sampling rates. As an application example,
programming to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, and 32 times in 192-kHz operation
allows the use of only a single type (cutoff frequency) of post low-pass filter. The 128 fS oversampling rate is not
available at sampling rates above 100 kHz. If the 128-fS oversampling rate is selected, a system clock of more than
256 fS is required.
In DSD mode, these bits are used to select the speed of the bit clock for DSD data coming into the analog FIR filter.
Register 21
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R/W
0
0
1
0
1
0
1
RSV
RSV
RSV
RSV
RSV
DZ1
DZ0
PCMZ
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
DZ[1:0]: DSD Zero Output Enable
These bits are available for read and write.
Default value: 00
Zero Output Enable
DZ[1:0]
00
Disabled (default)
01
Even pattern detect
1x
96H pattern detect
The DZ bits are used to enable or disable the output zero flags, and to select the zero pattern in the DSD mode.
PCMZ: PCM Zero Output Enable
These bits are available for read and write.
Default value: 1
PCMZ = 0
PCM zero output disabled
PCMZ = 1
PCM zero output enabled (default)
The PCMZ bit is used to enable or disable the output zero flags in the PCM mode and the external DF mode.
Register 22
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R
0
0
1
0
1
1
0
RSV
RSV
RSV
RSV
RSV
RSV
ZFGR
ZFGL
R: Read Mode Select
Value is always 1, specifying the readback mode.
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ZFGx: Zero-Detection Flag
Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback.
Default value: 00
ZFGx = 0
Not zero
ZFGx = 1
Zero detected
These bits show zero conditions. Their status is the same as that of the zero flags at ZEROL (pin 1) and ZEROR
(pin 2). See Zero Detect in the FUNCTION DESCRIPTIONS section.
Register 23
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R
0
0
1
0
1
1
1
RSV
RSV
RSV
ID4
ID3
ID2
ID1
ID0
R: Read Mode Select
Value is always 1, specifying the readback mode.
ID[4:0]: Device ID
The ID[4:0] bits hold a device ID in the TDMCA mode.
TYPICAL CONNECTION DIAGRAM IN PCM MODE
Cf
5V
Rf
1
ZEROL
VCC2L
28
2
ZEROR
AGND3L
27
3
MSEL
IOUTL− 26
4
LRCK
IOUTL+
25
5
DATA
AGND2
24
6
BCK
VCC1
23
7
SCK
VCOML
22
+
0.1 µF
10 µF
−
0.1 µF
Controller
8
DGND
9
VDD
PCM1792
VCOMR
21
IREF
20
10 MS
AGND1
19
11 MDI
IOUTR−
18
12 MC
IOUTR+
17
AGND3R
16
VCC2R
15
13 MDO
Rf
5V
−
47 µF 10 µF
+
Differential
to
Single
Converter
With
Low-Pass
Filter
VOUT
R-Channel
Rf
10 kΩ
−
+
Cf
Rf
5V
−
10 µF
VOUT
L-Channel
Cf
47 µF
0.1 µF
Differential
to
Single
Converter
With
Low-Pass
Filter
+
+
+
14 RST
Cf
+
PCM
Audio
Data
Source
+
+
3.3 V
+
10 µF
Figure 35. Typical Application Circuit for Standard PCM Audio Operation
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
APPLICATION INFORMATION
APPLICATION CIRCUIT
The design of the application circuit is very important in order to actually realize the high S/N ratio of which the
PCM1792 is capable. This is because noise and distortion that are generated in an application circuit are not
negligible.
In the circuit of Figure 36, the output level is 2 V rms and 127 dB S/N is achieved.
The circuit of Figure 37 can realize the highest performance. In this case the output level is set to 4.5 V rms and 129 dB
S/N is achieved (stereo mode). In monaural mode, if the output of the L-channel and R-channel is used as a balanced
output, 132 dB S/N is achieved (see Figure 39).
Figure 38 shows a circuit for the DSD mode, which is a 4th-order LPF in order to reduce the out-of-band noise.
I/V Section
The current of the PCM1792 on each of the output pins (IOUTL+, IOUTL–, IOUTR+, IOUTR–) is 7.8 mA p-p at 0 dB (full
scale). The voltage output level of the I/V converter (Vi) is given by following equation:
Vi = 7.8 mA p−p × Rf (Rf : feedback resistance of I/V converter)
An NE5534 operational amplifier is recommended for the I/V circuit to obtain the specified performance. Dynamic
performance such as the gain bandwidth, settling time, and slew rate of the operational amplifier affects the audio
dynamic performance of the I/V section.
Differential Section
The PCM1792 voltage outputs are followed by differential amplifier stages, which sum the differential signals for each
channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a low-pass filter
function.
The operational amplifier recommended for the IV circuit is the NE5534, and the operational amplifier recommended
for the differential circuit is the Linear Technology LT1028, because its input noise is low.
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
C1
2200 pF
R1
750 Ω
VCC
VCC
C11
0.1 µF
C17
22 pF
7
IOUT−
5
2
8
−
3
R5
270 Ω
6
+
C3
2700 pF
R3
560 Ω
C19
33 pF
7
2
U1
NE5534
4
C15
0.1 µF
3
5
−
6
+
4
C12
0.1 µF
VEE
R4
560 Ω
R6
270 Ω
R7
100 Ω
U3
LT1028
C16
0.1 µF
C4
2700 pF
VEE
C2
2200 pF
R2
750 Ω
VCC
C13
0.1 µF
C18
22 pF
7
IOUT+
2
3
5
−
8
6
+
4
U2
NE5534
C14
0.1 µF
VCC = 15 V
VEE = −15 V
fc = 217 kHz
VEE
Figure 36. Measurement Circuit for PCM, VOUT = 2 V rms
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
C1
2200 pF
R1
820 Ω
VCC
VCC
C11
0.1 µF
C17
22 pF
7
IOUT−
5
2
8
−
3
R5
360 Ω
6
+
C3
2700 pF
R3
360 Ω
C19
33 pF
7
2
U1
NE5534
4
C15
0.1 µF
3
5
−
6
+
4
C12
0.1 µF
VEE
R4
360 Ω
R6
360 Ω
R7
100 Ω
U3
LT1028
C16
0.1 µF
C4
2700 pF
VEE
C2
2200 pF
R2
820 Ω
VCC
C13
0.1 µF
C18
22 pF
7
IOUT+
2
3
5
−
8
6
+
4
U2
NE5534
C14
0.1 µF
VEE
Figure 37. Measurement Circuit for PCM, VOUT = 4.5 V rms
36
VCC = 15 V
VEE = −15 V
fc = 162 kHz
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
C1
2200 pF
R1
820 Ω
VCC
VCC
C11
0.1 µF
C17
22 pF
7
IOUT−
5
2
8
−
3
R5
330 Ω
6
+
R3
110 Ω
R10
68 Ω
C3
18000 pF
U1
NE5534
4
R8
220 Ω
C5
10000 pF
C4
47000 pF
C15
0.1 µF
C19
33 pF
7
2
3
5
−
6
+
4
C12
0.1 µF
VEE
R4
110 Ω
R9
220 Ω
R6
330 Ω
R11
68 Ω
R7
100 Ω
U3
LT1028
C14
0.1 µF
C6
10000 pF
VEE
C2
2200 pF
R2
820 Ω
VCC
C13
0.1 µF
C18
22 pF
7
IOUT+
2
3
5
−
8
6
+
4
U2
NE5534
VCC = 15 V
VEE = −15 V
fc = 38 kHz
C14
0.1 µF
VEE
Figure 38. Measurement Circuit for DSD
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IOUTL− (Pin 26)
IOUT−
IOUTL+ (Pin 25)
IOUT+
OUT+
Figure 37
Circuit
3
1
2
IOUTR− (Pin 18)
IOUT−
OUT−
Figure 37
Circuit
IOUTR+ (Pin 17)
Balanced Out
IOUT+
Figure 39. Measurement Circuit for Monaural Mode
APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE
DFMS = 0
External Filter Device
PCM1792
1
ZEROL
2
ZEROR
3
MSEL
WDCK (Word Clock)
4
LRCK
DATA
5
DATA
BCK
6
BCK
SCK
7
SCK
DFMS = 1
External Filter Device
PCM1792
DATA_L
1
ZEROL
DATA_R
2
ZEROR
3
MSEL
4
LRCK
5
DATA
BCK
6
BCK
SCK
7
SCK
WDCK (Word Clock)
Figure 40. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application
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Application for Interfacing With an External Digital Filter
For some applications, it may be desirable to use an external digital filter to perform the interpolation function, as it
can provide improved stop-band attenuation when compared to the internal digital filter of the PCM1792.
The PCM1792 supports several external digital filters, including:
D Texas Instruments DF1704 and DF1706
D Pacific Microsonics PMD200 HDCD filter/decoder IC
D Programmable digital signal processors
The external digital filter application mode is accessed by programming the following bits in the corresponding control
register:
D DFTH = 1 (register 20)
The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of
Figure 40. The word (WDCK) signal must be operated at 8× or 4× the desired sampling frequency, fS.
System Clock (SCK) and Interface Timing
The PCM1792 in an application using an external digital filter requires the synchronization of WDCK and the system
clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, DATAL, and
DATAR is shown in Figure 42.
Audio Format
The PCM1792 in the external digital filter interface mode supports right-justified audio formats including 16-bit, 20-bit,
and 24-bit audio data, as shown in Figure 41. The audio format is selected by the FMT[2:0] bits of control register
18.
1/4 fS or 1/8 fS
WDCK
BCK
Audio Data Word = 16-Bit
DATA
15 16
1
2
3
4
MSB
5
6
7
8
9 10 11 12 13 14 15 16
LSB
Audio Data Word = 20-Bit
DATA
19 20
1
2
3
4
MSB
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
LSB
Audio Data Word = 24-Bit
DATA
23 24
1
2
3
MSB
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
LSB
Figure 41. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
WDCK
(LRCK)
50% of VDD
t(BCH)
t(BCL)
t(LB)
50% of VDD
BCK
t(BCY)
t(BL)
50% of VDD
DATA
t(DS)
t(DH)
PARAMETER
MIN
t(BCY) BCK pulse cycle time
t(BCL) BCK pulse duration, LOW
MAX
UNITS
20
ns
7
ns
t(BCH) BCK pulse duration, HIGH
t(BL)
BCK rising edge to WDCK falling edge
7
ns
5
ns
t(LB)
t(DS)
WDCK falling edge to BCK rising edge
5
ns
DATA setup time
5
ns
t(DH)
DATA hold time
5
ns
Figure 42. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application
Functions Available in the External Digital Filter Mode
The external digital filter mode allows access to the majority of the PCM1792 mode control functions.
The following table shows the register mapping available when the external digital filter mode is selected, along with
descriptions of functions which are modified when using this mode selection.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
0
1
0
0
0
0
−
−
−
−
−
−
−
−
Register 17
R/W
0
0
1
0
0
0
1
−
−
−
−
−
−
−
−
Register 18
R/W
0
0
1
0
0
1
0
−
FMT2
FMT1
FMT0
−
−
−
−
Register 19
R/W
0
0
1
0
0
1
1
REV
−
−
OPE
−
DFMS
−
INZD
Register 20
R/W
0
0
1
0
1
0
0
−
SRST
0
1
MONO
CHSL
OS1
OS0
Register 21
R/W
0
0
1
0
1
0
1
−
−
−
−
−
−
−
PCMZ
Register 22
R
0
0
1
0
1
1
0
−
−
−
−
−
−
ZFGR
ZFGL
NOTE: 1: Bit is required for selection of external digital filter mode.
−:Function is disabled. No operation even if data bit is set
FMT[2:0]: Audio Data Format Selection
Default value: 000
FMT[2:0]
000
16-bit right-justified format (default)
001
20-bit right-justified format
010
24-bit right-justified format
Other
40
Audio Data Format Select
N/A
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
OS[1:0]: Delta-Sigma Modulator Oversampling Rate Selection
Default value: 00
OS[1:0]
Operation Speed Select
00
8 times WDCK (default)
01
4 times WDCK
10
16 times WDCK
11
Reserved
The effective oversampling rate is determined by the oversampling performed by both the external digital filter and
the delta-sigma modulator. For example, if the external digital filter is 8× oversampling, and the user selects
OS[1:0] = 00, then the delta-sigma modulator oversamples by 8×, resulting in an effective oversampling rate of 64×.
The 16× WDCK oversampling rate is not available above a 100-kHz sampling rate. If the oversampling rate selected
is 16× WDCK, the system clock frequency must be over 256 fS.
APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE
DSD Decoder
PCM1792
1
ZEROL
2
ZEROR
3
MSEL
DATA_R
4
LRCK
DATA_L
5
DATA
6
BCK
7
SCK
Bit Clock
Figure 43. Connection Diagram in DSD Mode
Feature
This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CDt (SACD) applications.
The DSD mode is accessed by programming the following bit in the corresponding control register.
DSD = 1 (register 20)
The DSD mode provides a low-pass filtering function. The filtering is provided using an analog FIR filter structure.
Four FIR responses are available, and are selected by the DMF[1:0] bits of control register 18.
The DSD bit must be set before inputting DSD data; otherwise, the PCM1792 erroneously detects the TDMCA mode,
and commands are not accepted through the serial control interface.
Super Audio CD is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan.
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
Pin Assignment When Using DSD Format Interface
Several pins are redefined for DSD mode operation. These include:
D
D
D
D
DATA (pin 5): DSDL as L-channel DSD data input
LRCK (pin 4): DSDR as R-channel DSD data input
SCK (pin 7): DBCK as a bit-clock input
BCK (pin 6): Set LOW (N/A)
t = 1/(64 × 44.1 kHz)
DBCK
DSDL
DSDR
D0
D1
D2
D3
D4
Figure 44. Normal Data Output Form From DSD Decoder
t(BCH)
t(BCL)
50% of VDD
DBCK
t(BCY)
DSDL
DSDR
50% of VDD
t(DS)
t(DH)
PARAMETER
t(BCY) DBCK pulse cycle time
t(BCH) DBCK high-level time
t(BCL) DBCK low-level time
t(DS) DSDL, DSDR setup time
MIN
85(1)
MAX
UNITS
ns
30
ns
30
ns
10
ns
t(DH) DSDL, DSDR hold time
10
ns
(1) 2.8224 MHz × 4. (2.8224 MHz = 64 × 44.1 kHz. This value is
specified as a sampling rate of DSD.)
Figure 45. Timing for DSD Audio Interface
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
ANALOG FIR FILTER PERFORMANCE IN DSD MODE
GAIN
vs
FREQUENCY
GAIN
vs
FREQUENCY
0
0
−1
−10
−2
−20
Gain − dB
Gain − dB
fc = 185 kHz
Gain(1) = −6.6 dB
−3
−30
−4
−40
−5
−50
−6
−60
0
50
100
150
200
0
500
f − Frequency − kHz
1000
1500
f − Frequency − kHz
Figure 46. DSD Filter-1, Low BW
Figure 47. DSD Filter-1, High BW
GAIN
vs
FREQUENCY
GAIN
vs
FREQUENCY
0
0
−1
−10
−2
−20
Gain − dB
Gain − dB
fc = 77 kHz
Gain(1) = −6 dB
−3
−30
−4
−40
−5
−50
−6
−60
0
50
100
150
200
0
500
f − Frequency − kHz
Figure 48. DSD Filter-2, Low BW
1000
1500
f − Frequency − kHz
Figure 49. DSD Filter-2, High BW
(1) This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%.
All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 fS), and 50% modulation DSD data input, unless otherwise noted.
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
GAIN
vs
FREQUENCY
GAIN
vs
FREQUENCY
0
0
−1
−10
−2
−20
Gain − dB
Gain − dB
fc = 85 kHz
Gain(1) = −1.5 dB
−3
−30
−4
−40
−5
−50
−6
−60
0
50
100
150
200
0
f − Frequency − kHz
500
1000
1500
f − Frequency − kHz
Figure 50. DSD Filter-3, Low BW
Figure 51. DSD Filter-3, High BW
GAIN
vs
FREQUENCY
GAIN
vs
FREQUENCY
0
0
−1
−10
−2
−20
Gain − dB
Gain − dB
fc = 94 kHz
Gain(1) = −3.3 dB
−3
−30
−4
−40
−5
−50
−6
−60
0
50
100
150
200
0
f − Frequency − kHz
Figure 52. DSD Filter-4, Low BW
500
1000
f − Frequency − kHz
Figure 53. DSD Filter-4, High BW
(1) This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%.
All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 fS), and 50% modulation DSD data input, unless otherwise noted.
44
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
DSD MODE CONFIGURATION AND FUNCTION CONTROLS
Configuration for the DSD Interface Mode
DSD = 1 (Register 20, B5)
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
0
1
0
0
0
0
−
−
−
−
−
−
−
−
Register 17
R/W
0
0
1
0
0
0
1
−
−
−
−
−
−
−
−
Register 18
R/W
0
0
1
0
0
1
0
−
−
−
−
DMF1
DMF0
−
−
Register 19
R/W
0
0
1
0
0
1
1
REV
−
−
OPE
−
−
−
−
Register 20
R/W
0
0
1
0
1
0
0
−
SRST
1
−
MONO
CHSL
OS1
OS0
Register 21
R
0
0
1
0
1
0
1
−
−
−
−
−
DZ1
DZ0
−
Register 22
R
0
0
1
0
1
1
0
−
−
−
−
−
−
ZFGR
ZFGL
NOTE: −: Function is disabled. No operation even if data bit is set
DMF[1:0]: Analog FIR Performance Selection
Default value: 00
DMF[1:0]
Analog-FIR Performance Select
00
FIR-1 (default)
01
FIR-2
10
FIR-3
11
FIR-4
Plots for the four analog FIR filter responses are shown in the TYPICAL PERFORMANCE CURVES section of this
data sheet.
OS[1:0]: Analog-FIR Operation-Speed Selection
Default value: 00
OS[1:0]
Operation Speed Select
00
fDBCK (default)
01
fDBCK /2
10
Reserved
11
fDBCK/4
The OS bit in the DSD mode is used to select the operating rate of the analog FIR. The OS bits must be set before
setting the DSD bit to1.
TDMCA Format
The PCM1792 supports the time-division-multiplexed command and audio (TDMCA) data format to simplify the host
control serial interface. The TDMCA format is designed not only for the McBSP of TI DSPs but also for any
programmable devices. The TDMCA format can transfer not only audio data but also command data, so that it can
be used together with any kind of device that supports the TDMCA format. The TDMCA frame consists of command
field, extended command field, and some audio data fields. Those audio data are transported to IN devices (such
as a DAC) and/or from OUT devices (such as an ADC). The PCM1792 is an IN device. LRCK and BCK are used
with both IN and OUT devices so that the sample frequency of all devices in a system must be the same. The TDMCA
mode supports a maximum of 30 device IDs. The maximum number of audio channels depends on the BCK
frequency.
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
TDMCA Mode Determination
The PCM1792 recognizes the TDMCA mode automatically when it receives an LRCK signal with a pulse duration
of two BCK clocks. If the TDMCA mode operation is not needed, the duty cycle of LRCK must be 50%. Figure 54
shows the LRCK and BCK timing that determines the TDMCA mode. The PCM1792 enters the TDMCA mode after
two continuous TDMCA frames. Any TDMCA commands can be issued during the next TDMCA frame after the
TDMCA mode is entered.
Pre-TDMCA Frame
TDMCA Frame
Command
Accept
LRCK
2 BCK
BCK
Figure 54. LRCK and BCK Timing of Determination TDMCA Mode
TDMCA Terminals
TDMCA requires six signals, of which four signals are for command and audio data interface, and two pairs of signals
which are for daisy chaining. Those signals can be shared as in the following table. The DO signal has a 3-state output
so that it can be connected directly to other devices.
TERMINAL
NAME
TDMCA
NAME
PROPERTY
LRCK
LRCK
input
TDMCA frame start signal. It must be the same as the sampling frequency.
BCK
BCK
input
TDMCA clock. Its frequency must be high enough to communicate a TDMCA frame within an LRCK
cycle.
TDMCA command and audio data input signal
DATA
DI
input
MDO
DO
output
DESCRIPTION
TDMCA command data 3-state output signal
MC
DCI
input
TDMCA daisy-chain input signal
MS
DCO
output
TDMCA daisy-chain output signal
Device ID Determination
The TDMCA mode also supports a multichip implementation in one system. This means a host controller (DSP) can
simultaneously support several TDMCA devices, which can be of the same type or different types, including PCM
devices. The PCM devices are categorized as IN device, OUT device, IN/OUT device, and NO device. The IN device
has an input port to get audio data, the OUT device has an output port to supply audio data, the IN/OUT device has
both input and output ports for audio data, and the NO device has no port for audio data but needs command data
from the host. A DAC is an IN device, an ADC is an OUT device, a CODEC is an IN/OUT device, and a PLL is a NO
device. The PCM1792 is an IN device. For the host controller to distinguish the devices, each device is assigned its
own device ID by the daisy chain. The devices obtain their own device IDs automatically by connecting their DCI to
the DCO of the preceding device and their DCO to the DCI of the following device in the daisy chain. The daisy chains
are categorized as the IN chain and the OUT chain, which are completely independent and equivalent. Figure 55
shows an example daisy chain connection. If a system needs to chain the PCM1792 and a NO device in the same
IN or OUT chain, the NO device should be chained at the back end of the chain because it does not require any audio
data. Figure 56 shows an example of TDMCA system including an IN chain and an OUT chain with a TI DSP. For
a device to get its own device ID, the DID signal must be set to 1 (see the Command Field section for details), and
LRCK and BCK must be driven in the TDMCA mode for all PCM devices which are chained. The device at the top
of the chain knows its device ID is 1 because its DCI is fixed HIGH. Other devices count the BCK pulses and observe
their own DCI signal to determine their position and ID. Figure 57 shows the initialization of each device ID.
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
DCO
DCI
NO Device
•••
DCO
DCOo
DCIo
DCO
NO Device
OUT
DCOo
DCIo
OUT
NO Device
DCI
•••
DCO
IN/OUT
Device
•••
NO Device
DCI
IN/OUT
Device
DCI
DCOi
DCIi
DCOi
DCIi
IN
OUT Device
•••
DCO
DCO
IN
IN Device
OUT Device
DCI
DCO
DCI
•••
IN Device
DCI
DCO
DCI
IN Chain
OUT Chain
Figure 55. Daisy Chain Connection
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
DCII
LRCK
BCK
IN/OUT DCOI
Device
(DIX1700)
DI
DCIO
DO
DCOO
Device ID = 1
LRCK
BCK
IN Device
(PCM1792)
DI
DO
LRCK
DCI
DCO
Device ID = 2
NO Device
DCI
BCK
DI
DO
DCO
Device ID = 3
•
•
•
FSX
FSR
CLKX
CLKR
DX
DR
LRCK
OUT Device
DCI
BCK
DI
DO
DCO
Device ID = 2
TI DSP
LRCK
OUT Device
DCI
BCK
DI
DO
DCO
Device ID = 3
•
•
•
Figure 56. IN Daisy Chain and OUT Daisy Chain Connection for a Multichip System
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
LRCK
BCK
DID
DI
Device ID = 1
DCO1
Device ID = 2
DCO1
DCI2
Command Field
Device ID = 3
DCO2
DCI3
•
•
•
•
•
•
Device ID = 30 DCO29
DCI30
58 BCK
Figure 57. Device ID Determination Sequence
TDMCA Frame
In general, the TDMCA frame consists of the command field, extended command (EMD) field, and audio data fields.
All of them are 32 bits in length, but the lowest byte has no meaning. The MSB is transferred first for each field. The
command field is always transferred as the first packet of the frame. The EMD field is transferred if the EMD flag of
the command field is HIGH. If any EMD packets are transferred, no audio data follows the EMD packets. This frame
is for quick system initialization. All devices of a daisy chain should respond to the command field and extended
command field. The PCM1792 has two audio channels that can be selected by OPE (register 19). If this OPE bit is
not set to HIGH, those audio channels are transferred. Figure 58 shows the general TDMCA frame. If some DACs
are enabled, but corresponding audio data packets are not transferred, the analog outputs are unpredictable.
1/fS
LRCK
BCK
[For Initialization]
DI
CMD
EMD
EMD
EMD
EMD
EMD
CMD
CMD
CMD
CMD
CMD
Don’t
Care
CMD
Don’t
Care
CMD
32 Bits
DO
CMD
[For Operation]
DI
CMD
DO
CMD
Ch1
Ch1
Ch2
Ch3
Ch4
Ch(n)
Ch2
Ch3
Ch4
Ch(m)
Figure 58. General TDMCA Frame
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
1/fS (256 PBCK Clocks)
7 Packets × 32 Bits
LRCK
BCK
DI
Ch1
CMD
Ch2
Ch3
Ch4
Ch5
Ch6
Don’t
Care
CMD
IN and OUT Channel Orders are Completely Independent
DO
Ch1
CMD
Ch2
Figure 59. TDMCA Frame Example of 6-Ch DAC and 2-Ch ADC With Command Read
Command Field
The normal command field is defined as follows. When the DID bit (MSB) is 1, this frame is used only for device ID
determination, and all remaining bits in the field are ignored.
command
31
30
29
DID
EMD
DCS
28
24
device ID
23
22
R/W
16
15
register ID
8
7
data
0
not used
Bit 31: Device ID enable flag
The PCM1792 operates to get its own device ID for TDMCA initialization if this bit is HIGH.
Bit 30: Extended command enable flag
The EMD packet will be transferred if this bit is HIGH, otherwise skipped. Once this bit is HIGH, this frame does not
contain any audio data. This is for system initialization.
Bit 29: Daisy chain selection flag
HIGH designates OUT-chain devices, LOW designates IN-chain devices. The PCM1792 is an IN device, so the DCS
bit must be set to LOW.
Bits[28:24]: Device ID. It is 5 bits length, and it can be defined.
These bits identify the order of a device in the IN or OUT daisy chain. The top of the daisy chain defines device ID
1 and successive devices are numbered 2, 3, 4, etc. All devices for which the DCI is fixed HIGH are also defined as
ID 1. The maximum device ID is 30 each in the IN and OUT chains. If a device ID of 0x1F is used, all devices are
selected as broadcast when in the write mode. If a device ID of 0x00 is used, no device is selected.
Bit 23: Command Read/Write flag
If this bit is HIGH, the command is a read operation.
Bits[22:16]: Register ID
It is 7 bits in length.
Bits[15:8]: Command data
It is 8 bits in length. Any valid data can be chosen for each register.
Bits[7:0]: Not used
These bits are never transported when a read operation is performed.
Extended command field
The extended command field is the same as the command field, except that it does not have a DID flag.
extended command
50
31
30
29
rsvd
EMD
DCS
28
24
device ID
23
R/W
22
16
register ID
15
8
data
7
0
not used
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
Audio Fields
The audio field is 32 bits in length and the audio data is transferred MSB first, so the other fields must be stuffed with
0s as shown in the following example.
audio data
31
16
MSB
24 bits
12
8
7
LSB
4 3
0
All 0s
TDMCA Register Requirements
TDMCA mode requires device ID and audio channel information, previously described. The OPE bit in register 19
indicates audio channel availability and register 23 indicates the device ID. Register 23 is used only in the TDMCA
mode. See the mode control register map (Table 4).
Register Write/Read Operation
The command supports register write and read operations. If the command requests to read one register, the read
data is transferred on DO during the data phase of the timing cycle. The DI signal can be retrieved at the positive
edge of BCK, and the DO signal is driven at the negative edge of BCK. DO is activated one BCK cycle early to
compensate for the output delay caused by high impedance. Figure 60 shows the TDMCA write and read timing.
Register ID Phase
Data Phase
BCK
DI
Read Mode and Proper Register ID
DO
Write Data Retrieved, if Write Mode
Read Data Driven, if Read Mode
1 BCK Early
DOEN
(Internal)
Figure 60. TDMCA Write and Read Operation Timing
TDMCA-Mode Operation
DCO specifies the owner of the next audio channel in TDMCA-mode operation. When a device retrieves its own audio
channel data, DCO goes HIGH during the last audio channel period. Figure 61 shows the DCO output timing in
TDMCA-mode operation. The host controller ignores the behavior of DCI and DCO. DCO indicates the last audio
channel of each device. Therefore, DCI means the next audio channel is allocated.
If some devices are skipped due to no active audio channel, the skipped devices must notify the next device that the
DCO will be passed through the next DCI. Figure 62 and Figure 63 show DCO timing with skip operation. Figure 64
shows the ac timing of the daisy chain signals.
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1/fS (384 PBCK Clocks)
9 Packets y 32 Bits
LRCK
BCK
IN Daisy Chain
CMD
DI
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Ch8
Don’t Care
DCI1
DID = 1
DID = 2
DID = 3
DID = 4
DCO1
DCI2
DCO2
DCI3
DCO3
DCI4
DCO4
Figure 61. DCO Output Timing of TDMCA Mode Operation
1/fS (256 PBCK Clocks)
5 Packets × 32 Bits
LRCK
BCK
DI
CMD
Ch1
Ch2
Ch15
Ch16
Don’t Care
DCI
DID = 1
DCO
DCI
DID = 2
•
•
•
•
•
•
2 PBCK Delay
DCO
•
•
•
14 PBCK Delay
DCI
DID = 8
DCO
Figure 62. DCO Output Timing With Skip Operation
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CMD
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
Command Packet
LRCK
BCK
DI
DID EMD
DCO1
DCO2
•
•
•
Figure 63. DCO Output Timing With Skip Operation (for Command Packet 1)
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LRCK
t(LB)
t(BL)
BCK
t(BCY)
t(DS)
t(DH)
DI
t(DOE)
DO
t(DS)
t(DH)
DCI
t(COE)
DCO
PARAMETER
t(BCY) BCK pulse cycle time
t(LB)
LRCK setup time
MIN
MAX
UNITS
20
ns
0
ns
t(BL)
t(DS)
LRCK hold time
3
ns
DI setup time
0
ns
t(DH)
t(DS)
DI hold time
3
ns
DCI setup time
0
ns
3
ns
t(DH) DCI hold time
t(DOE) DO output delay(1)
t(COE) DCO output delay(1)
(1) Load capacitance is 10 pF.
Figure 64. AC Timing of Daisy Chain Signals
54
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ns
6
ns
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SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
THEORY OF OPERATION
Upper
6 Bits
ICOB
Decoder
0−62
Level
0−66
Advanced
DWA
Digital Input
24 Bits
8 fS
MSB
and
Lower 18 Bits
3rd-Order
5-Level
Sigma-Delta
Current
Segment
DAC
Analog Output
0−4
Level
Figure 65. Advanced Segments DAC
The PCM1792 uses TI’s advanced segment DAC architecture to achieve excellent dynamic performance and
improved tolerance to clock jitter. The PCM1792 provides balanced current outputs.
Digital input data via the digital filter is separated into six upper bits and 18 lower bits. The six upper bits are converted
to inverted complementary offset binary (ICOB) code. The lower 18 bits, associated with the MSB, are processed
by a five-level third-order delta-sigma modulator operated at 64 fS by default. The 1 level of the modulator is equivalent
to the 1 LSB of the ICOB code converter. The data groups processed in the ICOB converter and third-order
delta-sigma modulator are summed together to an up to 66-level digital code, and then processed by data-weighted
averaging (DWA) to reduce the noise produced by element mismatch. The data of up to 66 levels from the DWA is
converted to an analog output in the differential-current segment section.
This architecture has overcome the various drawbacks of conventional multibit processing and also achieves
excellent dynamic performance.
55
www.ti.com
SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
Analog output
The following table and Figure 66 show the relationship between the digital input code and analog output.
IOUTN [mA]
IOUTP [mA]
VOUTN [V]
VOUTP [V]
800000 (–FS)
000000 (BPZ)
7FFFFF (+FS)
–2.3
–6.2
–10.1
–10.1
–6.2
–2.3
–1.725
–4.650
–7.575
–7.575
–4.650
–1.725
VOUT [V]
–2.821
0
2.821
NOTE: VOUTN is the output of U1, VOUTP is the output of U2, and VOUT is the output of U3 in the
measurement circuit of Figure 36.
OUTPUT CURRENT
vs
INPUT CODE
0
IO − Output Current − mA
−2
IOUTN
−4
−6
−8
−10
IOUTP
−12
800000(−FS)
000000(BPZ)
7FFFFF(+FS)
Input Code − Hex
Figure 66. The Relationship Between Digital Input and Analog Output
56
PACKAGE OPTION ADDENDUM
www.ti.com
27-Oct-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
PCM1792DB
ACTIVE
SSOP
DB
28
47
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCM1792DBG4
ACTIVE
SSOP
DB
28
47
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCM1792DBR
ACTIVE
SSOP
DB
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCM1792DBRG4
ACTIVE
SSOP
DB
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jun-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
PCM1792DBR
Package Package Pins
Type Drawing
SSOP
DB
28
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2000
330.0
17.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.5
10.8
2.4
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jun-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCM1792DBR
SSOP
DB
28
2000
336.6
336.6
28.6
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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