Institutionen för systemteknik Department of Electrical Engineering Examensarbete Mahir Al-Taie

Institutionen för systemteknik Department of Electrical Engineering Examensarbete Mahir Al-Taie
Institutionen för systemteknik
Department of Electrical Engineering
Examensarbete
A Comparison of EDMOS and Cascode Structures
for PA Design in 65 nm CMOS Technology
Master thesis performed in Electronic Devices
by
Mahir Al-Taie
LiTH-ISY-EX--13/4715--SE
Linköping September 2013
TEKNISKA HÖGSKOLAN
LINKÖPINGS UNIVERSITET
Department of Electrical Engineering
Linköping University
S-581 83 Linköping, Sweden
Linköpings tekniska högskola
Institutionen för systemteknik
581 83 Linköping
ii
A Comparison of EDMOS and Cascode Structures
for PA Design in 65 nm CMOS Technology
Master thesis
Performed in Electronic Devices
Department of Electrical Engineering
Linköping Institute of Technology
by
Mahir Al-Taie
LiTH-ISY-EX--13/4715--SE
Supervisor: Professor Atila Alvandpour
Examiner: Adjunct Professor Ted Johansson
Linköping, 2013
iii
iv
Department and Division
Presentation Date
11-09-2013
Department of Electrical Engineering
_______________________
Publishing Date (Electronic version)
23-09-2013
Language
Type of Publication
X English
Other (specify below)
Number of Pages
78
X
ISBN (Licentiate thesis)
Licentiate thesis
Degree thesis
Thesis C-level
Thesis D-level
Report
Other (specify below)
ISRN: LiTH-ISY-EX--13/4715--SE
Title of series (Licentiate thesis)
Series number/ISSN (Licentiate thesis)
URL, Electronic Version
http://www.ep.liu.se
Publication Title
A Comparison of EDMOS and Cascode Structures for PA Design in 65 nm CMOS Technology
Author
Mahir Jabbar Rashid Al-Taie
Abstract
This thesis addresses the potential of implementing watt-level class-AB Power Amplifier (PA) for WLAN in 65 nm
CMOS technology, at 2.4 GHz frequency. In total, five PAs have been compared, where the examined parameters
were output power (Pout), linearity, power added efficiency (PAE), and area consumption. Four PAs were
implemented using conventional cascode topology with different combination of transistors sizes in 65nm CMOS,
and one PA using a high-voltage Extended Drain MOS (EDMOS) device, implemented in the same 65 nm CMOS
with no process or mask changes. All schematics were created using Cadence Virtuoso CAD tools. The test benches
were created using the Agilent's Advance Design System ( ADS) and simulated with the ADS-Cadence dynamic
link.
The simulation results show that the EDMOS PA (L=350 nm) has the smallest area, but has harder to reach the
required Pout. Cascode no. 3 (L= 500,260 nm) has the best P out (29.1 dBm) and PAE (49.5 %). Cascode no. 2 (L=
500,350 nm) has the best linearity (low EVM). Cascode no. 1 (L=500,500 nm) has low Pout (27.7 dBm). Cascode
no.4 (L=500,60 nm) has very bad linearity.
The thesis also gives an overview for CMOS technology, discusses the most important aspects in RF PAs design,
such as Pout, PAE, gain, and matching networks. Different PA classes are also discussed in this thesis.
Keywords
RF, Power amplifier, Linearity, PAE, Reliabilty issues, EVM, Cascode, HV-MOS, EDMOS, Matching networks.
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To my country Iraq!
To my Lovely Parents!
To my Lovely Wife!
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Abstract
This thesis addresses the potential of implementing watt-level class-AB Power Amplifier (PA) for WLAN in
65 nm CMOS technology, at 2.4 GHz frequency. In total, five PAs have been compared, where the examined
parameters were output power (Pout), linearity, power added efficiency (PAE), and area consumption. Four
PAs were implemented using conventional cascode topology with different combination of transistors sizes
in 65nm CMOS, and one PA using a high-voltage Extended Drain MOS (EDMOS) device, implemented in
the same 65 nm CMOS with no process or mask changes. All schematics were created using Cadence
Virtuoso CAD tools. The test benches were created using the Agilent's Advance Design System (ADS) and
simulated with the ADS-Cadence dynamic link.
The simulation results show that the EDMOS PA (L=350 nm) has the smallest area, but has harder to reach
the required Pout. Cascode no. 3 (L= 500,260 nm) has the best Pout (29.1 dBm) and PAE (49.5 %). Cascode no.
2 (L= 500,350 nm) has the best linearity (low EVM). Cascode no. 1 (L=500,500 nm) has low Pout (27.7
dBm). Cascode no.4 (L=500,60 nm) has very bad linearity.
The thesis also gives an overview for CMOS technology, discusses the most important aspects in RF PAs
design, such as Pout, PAE, gain, and matching networks. Different PA classes are also discussed in this thesis.
ix
Abbreviations
ACPR
Adjacent Channel Power Ratio
ADS
Advanced Design System
ASK
Amplitude Shift Keying
BV
Breakdown Voltage
CF
Crest Factor
CMOS
Complementary Metal-Oxide-Semiconductor
DC
Direct Current
EDMOS
Extended Drain Metal-Oxide-Semiconductor
ednfet
Extended Drain N-channel Metal-Oxide-Semiconductor
EVM
Error Vector Magnitude
FET
Field-Effect Transistor
FSK
Frequency Shift Keying
GC
Gain Compression
HB
Harmonic Balance
HV-MOS
High Voltage Metal-Oxide-Semiconductor
IEEE
The Institute of Electrical and Electronics Engineers
LDMOS
Laterally Diffused Metal-Oxide-Semiconductor
MOSFET
Metal-Oxide-Semiconductor Field Effect Transistor
NMOS
N-channel Metal-Oxide-Semiconductor
PA
Power Amplifier
PAPR
Peak-to-Average Power Ratio
PDK
process design kit
PEP
Peak Envelope output Power
PMOS
P-channel Metal-Oxide-Semiconductor Field-Effect Transistor
PSK
Phase Shift Keying
x
QAM
Quadrature amplitude modulation
QPSK
Quadrature Phase Shift Keying
RF
Radio Frequency
SoC
System-on-Chip
TDDB
Time Dependent Dielectric Breakdown
TX
Transmitter
UWB
Ultra-Wide Band
VLSI
Very-large-scale integration
W-LAN
Wireless Local Area Network
WCDMA
Wide-band Code Division Multiple Access
xi
Acknowledgement
I would like to express my deepest appreciation to all the people who have helped me during the
conduction of this thesis work.
I would like to thank my examiner Adjunct Professor Ted Johansson for giving me the chance to
work in this field, and for his valuable ideas, guidance and help during this project. Thank you so
much for the experience.
I also would like to express my gratitude to my supervisor Professor Atila Alvandpour, for all his
insightful discussions and guidance which was given with the most passion and generosity in time
and knowledge.
I am also grateful for all the valuable help that I have received from Ph.D students, Fahad Qazi,
Amin Ojani, Ameya Bhide, Ali Fazli, Muhammad Irfan Kazim, and Daniel Svärd. I am also
thankful from all other researchers who have helped me during this project.
A big thank you goes to my parents and my Lovely wife Maya, for their unconditional love and
support. I am also thankful to all my friends, who have enriched my life with love and joy.
My acknowledgements to Linköping University, for providing all the resources that I needed to
learn and grow.
Mahir Jabbar Rashid Al-Taie
Linköping, 2013
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Contents
xiv
Abstract
ix
Abbreviations
x
Acknowledgement
xii
List of Figures
xvii
List of Tables
xix
Chapter 1 Basic MOS Device Physics
1.1
1.2
1.3
1
Brief History
MOSFET Structure
MOS I/V Characteristic
1.3.1
Threshold Voltage
1.3.2
Operating Regions
1.3.2.1
The Deep Triode Region
1.3.2.2
The Saturation Region
1.4
Reliability issues in Power Amplifier Design
1.4.1
Drain-Bulk Breakdown
1.4.2
Hot Carrier Effect
1.4.3
Time Dependent dielectric Breakdown TDDB
1.4.4
Punch-through
1
1
4
4
6
8
9
10
10
10
10
10
Chapter 2 Important Aspects in Power Amplifier Design
11
2.1
2.2
2.2.1
2.2.2
2.2.3
2.3
2.3.1
2.3.2
2.3.3
Introduction
Digital Modulation
Bandwidth Efficiency
Signal Constellation
Error Vector Magnitude (EVM)
Power Amplifier Properties
Output Power
Power Gain
Peak Output Power, Peak to Average Power Ratio and Crest
xiv
11
12
13
14
15
17
17
18
Factor
2.3.4
Efficiency
2.3.5
Linearity
2.3.5.1
Adjacent Channel Power Ratio
2.4
Matching Network
2.4.1
Load line theory
2.4.2
Load-pull
2.4.3
Passive Impedance Transformation
2.4.4
Quality factor
2.4.5
L-Match Network
2.4.5.1
High to Low Transformation
2.4.5.2
Inductor Loss and Efficiency
2.5
HV-MOS Devices
2.5.1
Extended Drain MOS Devices
Chapter 3 Power Amplifier Classification
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.2.1
3.2.2
3.2.3
Linear Power Amplifiers
Class-A Power Amplifier
Class-B Power Amplifier
Class-C Power Amplifier
Class-AB Power Amplifier
Switching Power Amplifiers
Class-D Power Amplifier
Class-E Power Amplifier
Class-F Power Amplifier
Chapter 4 Test Bench and Simulation Results
4.1
4.2
4.3
4.3.1
4.3.2
4.4
4.5
4.6
4.6.1
4.6.2
4.7
4.7.1
4.7.2
4.7.3
4.7.4
Introduction
Tools and Programs
Structure of Class-AB Power Amplifier
Cascode Power Amplifier
EDMOS Power Amplifier
Test Bench
Devices Parameters
Simulation and results
Simulation Results of Test Bench No.1
Simulation Results of Test Bench No.2
Discussion / Interpretation
Power Density (Pout / M)
Error Vector Magnitude (EVM) and Ppeak
Pout – Pin
Area
xv
18
19
19
20
22
23
24
25
25
26
27
28
30
30
32
32
33
34
36
37
38
38
40
42
44
44
45
45
45
47
48
50
50
50
51
51
51
52
52
52
4.7.5
4.7.6
Power Added Efficiency
Transformation Ratio ((Zsource / Zin) and (ZL / Zout))
Chapter 5 Conclusion and Future Work
5.1
5.2
Summary and Concentration
Future Works
References
53
53
54
54
55
56
xvi
List of Figures
Figure 1.1: (a) NMOS symbol, (b) structure of NMOS device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 1.2: (a) PMOS symbol, (b) structure of PMOS device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 1.3: PMOS device in an n-well . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 1.4: (a) A MOSFET driven by gate voltage, (b) formation of depletion region, (c) onset of
inversion, (d) formation of inversion layer . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . 4
Figure 1.5: Formation of inversion layer in a PFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 1.6: Channel charge with equal source and drain voltages. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 1.7: Channel charge with unequal source and drain voltages. . . . . . . . . . . . . . . . . . . . . . .
6
Figure 1.8: Linear operation region in deep triode region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 1.9: MOSFET as a controlled resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 1.10: Saturation of drain current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2.1: Direct-conversion transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2.2: Amplitude shift keying. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2.3: Phase-shift keying. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2.4: Frequancy shift keying. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 13
Figure 2.5: Signal constellation for: (a) ideal PSK signal, (b) Noisy received PSK signal. . . .. . . 14
Figure 2.6: Constellation of 16 QAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2.7: Constellation of 16 QAM (noisy received signal). . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 2.8: Illustration of EVM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 2.9: (a) Power amplifier connected to an antenna, (b) Antenna modeled by pure
resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 2.10: Illustration of P1dB compression point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 2.11: An example of ACPR measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 2.12: Load line imposed on IV-curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 2.13: (a) Load-pull test, (b) contours used in load-pull test, (c) input and output
matching networks . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
Figure 2.14: Inductor with loss. (a) Series model and (b) parallel model. . . . . . . . . . . . . . . . . . . . 25
xvii
Figure 2.15: Matching network (a) High to low transformation, (b) Low to high
transformation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 2.16: L-match impedance transformation network. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 27
Figure 2.17: L-match impedance transformation network with series inductor loss. . . . . . . .. . . . 28
Figure 2.18: Relationship between the power enhancement and the efficiency of an L-match
network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 2.19: A structures of (a) N-EDMOS, (b) P-EDMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 3.1: Common source linear power amplifier . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 32
Figure 3.2: Drain voltage and current for ideal class-A amplifier. . . . . . . . . . . . . . .. . . . . . . . . . . 33
Figure 3.3: Drain voltage and current for ideal class-B amplifier. . . . . . . . . . . . . . . .. . . . . . . . . . 35
Figure 3.4: Drain voltage and current for ideal class-C amplifier. . . . . . . . . . . .. . . . . . . . . . . . . . 36
Figure 3.5: Class-D amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 38
Figure 3.6: T2 drain voltage and current for ideal class-D amplifier. . . . . . . . . . . . . . . . .. . . . . . . 38
Figure 3.7: M1 drain voltage and current for ideal class-D amplifier. . . . . . . . . . . . . . . . . . . . . . . 39
Figure 3.8: Inverter-based class-D amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 3.9: Class-E amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3.10: Waveform for class-E amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 3.11: Class-F amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 3.12: Drain voltage and current for ideal class-F amplifier. . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 4.1: Structure of cascode power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 4.2: Power amplifier, core and matching networks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 4.3: Schematic of class AB, cascode power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 4.4: Cross-section of EDMOS device. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 47
Figure 4.5: Schematic of class AB, EDMOS power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 4.6: Test bench no.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 4.7: Test bench no.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 4.8: Ppeak VS EVM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
xviii
List of Tables
Table 2.1 Bandwidth efficiency for different modulation schemes. . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 2.2 Constellation error and EVM equivalent for IEEE 802.11a . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4.1 Devices size and parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 4.2 performances and results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . … . . . . . . . . . 50
Table 4.3 Peak output power measurements (estimation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 4.4 Area measurements (estimation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
xix
Chapter 1
Basic MOS Device Physics
________________________________________________________________________________________________________________________________________________________________
Chapter 1
1.1
Basic MOS Device Physics
Brief History
The theory of a metal-oxide-silicon field-effect transistors(MOSFETs) was known 20 years before the
invention of the bipolar transistors. In 1930, the idea of creating a FET-like transistor was patented by J.E.
Lilienfeld, but he could never construct a working device [1].
Due to fabrication limitations and lack of appropriate semiconductors, the development was very slow. In the
early 1960s, MOS technologies became practical with several generations which contained only n-type
transistors. It was in 1963 when the CMOS circuits was invented by Frank Wanlass [2]. Thus, circuits with
both n-type and p-type transistors were introduced. These circuits are known as Complementary MOS, or
CMOS circuits.
The availability of complementary enhancement NMOS and PMOS transistors had many benefits such as
low power dissipation and low fabrication cost, which made the CMOS IC an attractive technology for the
realization of digital circuits. Furthermore, the ease to scale down the dimensions of the MOS device lead to
the integration of more and more dense and complex digital circuits. Device scaling also improved the speed
of MOSFETs. That was the principal force of making CMOS technology the dominating technology also in
the analog and RF market [3].
1.2
MOSFET Structure
There are many symbol can be used to represent NMOS transistor, one of these symbols is shown in Figure
1.1 (a). The MOSFET is a four terminal device: gate (G), source (S), drain (D), and substrate (B) which is
also called bulk.
Figure 1.1 (b) shows the structure of NMOS device. The NMOS device consists of two heavily-doped n +
regions forming the source and drain terminals. These two regions are built on a p-type substrate. The gate is
made of heavily doped poly-silicon isolated from the substrate by a layer of silicon oxide (SiO 2). Note that
the drain and source are interchangeable because the MOS device is symmetric with respect to drain and
source. The substrate is usually connected to the most negative supply in the system to insure a reverse bias
for the drain-body and source-body junctions [3].
1
Chapter 1
Basic MOS Device Physics
________________________________________________________________________________________________________________________________________________________________
(a)
(b)
Figure 1.1: (a) NMOS symbol, (b) structure of NMOS device [3].
In CMOS technology, both NMOS and PMOS are available. The PMOS transistor consists of two heavily
doped p+ fabricated on a n-type substrate. The gate and the oxide layer are the same as those for the NMOS
transistor. To make sure the inverse bias of the drain-body and source-body junctions, the substrate is
connected to the most positive supply in the system. Figure 1.2 (a) shows the symbol of the PMOS transistor,
and Figure 1.2 (b) shows the structure of this device.
2
Chapter 1
Basic MOS Device Physics
________________________________________________________________________________________________________________________________________________________________
(a)
(b)
Figure 1.2: (a) PMOS symbol, (b) structure of PMOS device [3].
In practice, both NMOS and PMOS devices are fabricated on a single substrate. Thus, one device type has to
be fabricated on a local substrate (also called well). Figure 1.3 shows a PMOS device placed in an n-well.
Figure 1.3: PMOS device in an n-well [3].
3
Chapter 1
Basic MOS Device Physics
________________________________________________________________________________________________________________________________________________________________
1.3
MOS I/V Characteristics
1.3.1 Threshold Voltage
Consider an NMOS transistor shown in Figure 1.4.
Figure 1.4: (a) A MOSFET driven by gate voltage, (b) formation of depletion region, (c) onset of
inversion, (d) formation of inversion layer [3].
When the VG is 0, the drain and source are connected by back-to-back PN junctions. Thus, the transistor is
off and there is no current flowing between the source and drain. As the gate and substrate form a capacitor,
if a positive voltage is applied at the gate, positive and negative charges will accumulate at the gate and
substrate, respectively. Thus, the holes in the substrate are repelled and a depletion region is formed below
the gate. The width of this depletion region can be defined as
Wd =
√
2 εsi ϕ
q NA
(1.1)
where φ is the potential across the depletion region, N A is the substrate doping and Ɛsi is the dielectric
constant of silicon.
The potential across the depletion region is directly proportional to V G. When the potential reaches a
critical value, a channel between the drain and the source is formed under the gate and the transistor
is turned on. This phenomenon is also called strong inversion. The value of VG at which the strong
inversion occurs is called threshold voltage VTH.
The threshold voltage is a function of several parameters, such as the oxide thickness, the dosage of ions
4
Chapter 1
Basic MOS Device Physics
________________________________________________________________________________________________________________________________________________________________
implemented for threshold adjustment and the source-bulk voltage V SB. It can be defined as
V TH = V TH0+ γ( √ ∣2 ϕ F +V SB∣− √ ∣2 ϕ F∣)
(1.2)
where VTH0 is threshold voltage at VSB = 0, ɤ is the body-effect coefficient and φF is the Fermi potential.
For PMOS devices, same arguments can be applied for the turn on phenomenon but with all of the polarities
are reversed. Figure 1.5 shows the formation of inversion layer in PMOS. When the V G becomes sufficiently
negative, the strong inversion occurs and a channel between the drain and the source is formed.
Figure 1.5: Formation of inversion layer in a PFET [3].
5
Chapter 1
Basic MOS Device Physics
________________________________________________________________________________________________________________________________________________________________
1.3.2 Operation Regions
To understand the operation regions, the relationship between the drain current and terminals voltages are
discussed.
Figure 1.6: Channel charge with equal source and drain voltages [3].
Figure 1.6 shows an NFET whose drain and source are connected to ground and gate is connected to V G. The
charge of the gate oxide capacitance is proportional to the effective voltage (V GS-VTH). For (VGS-VTH ≥ 0), the
induced channel charge per unit area can be written as
Q̄d = C ox (V GS −V TH )
(1.3)
and the charge per unit length is
Q d = W C ox (V GS −V TH )
(1.4)
where W is the gate width.
Now suppose the drain voltage is positive, as shown in Figure 1.7.
Figure 1.7: Channel charge with unequal source and drain voltages [3].
The channel potential increases from zero at the source to V D at the drain. Thus, the local voltage difference
between the gate and the channel decreases from V G at the source to (VG-VD) at the drain. If the potential at
6
Chapter 1
Basic MOS Device Physics
________________________________________________________________________________________________________________________________________________________________
the point x is V(x), then the charge density at that point can be written as
Qd (x) = W C ox [V GS −V ( x)−V th ]
(1.5)
The ID can be defined as
I D = −Qd (x)⋅v
(1.6)
Where v is the velocity of the electron in the channel, which is defined as
v = μ E = −μ
d V (x)
dx
(1.8)
Thus, the drain current can be written as
I D = μn W C ox [V GS −V (x)−V TH ]
d V (x)
dx
I D dx = μ n W C ox [V GS −V (x)−V TH ] d V ( x)
(1.9)
(1.10)
By setting the boundary of integration as At x =0 => V ( x)=0 and at x= L => V ( x)=V DS , the
above equation can be written as
V ( x)=V DS
x= L
∫
I D dx =
x=0
∫
μ n W C ox [V GS −V ( x)−V TH ] d V (x) (1.11)
V ( x)=0
Finally, by assuming that µ and VTH are independent of x, VGS, and VDS, the drain current is defined as
I D = μn C ox
W
1
[(V GS −V TH )V DS − V 2DS ]
L
2
7
(1.12)
Chapter 1
Basic MOS Device Physics
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1.3.2.1 The Deep Triode Region
For VDS ˂˂ 2(VGS-VTH), the drain current can be written as
I D = μn C ox
W
[(V GS −V TH )V DS ]
L
(1.13)
Thus, if the VGS is constant, the drain current is a linear function of V DS. This is also shown in Figure 1.8. For
small VDS, each parabola can be approximated by a straight line.
Figure 1.8: Linear operation region in deep triode region [3].
At this region, the transistor can be modeled as a resistor (R on), this is also shown in Figure 1.9. The value of
this resistor is controlled by VDS, and can be written as
R on =
1
(1.14)
W
μn C ox (V GS −V TH )
L
Figure 1.9: MOSFET as a controlled resistor [3].
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1.3.2.2 The Saturation Region
Recall from equation (1.5), that the charge density at point x is proportional to (VGS-VTH) - V(x). Thus, the
channel exists as long as (VGS-VTH ≥ V(x)).
As it has been mentioned previously, the potential voltage V(x) at the drain voltage reaches V DS.
At the drain side, the channel disappears if (VGS-VTH ≤ VDS). This is known as pinch-off phenomenon. When
this phenomenon occurs, the drain current becomes relatively constant and the NMOS transistor is said to be
in saturation region. This is illustrated in Figure 1.10.
Figure 1.10: Saturation of drain current [3].
The drain current of an NMOS in saturation region is defined as
ID=
1
W
μ n C ox (V GS −V TH )2 .
2
L
(1.15)
The equation above approves that the drain current of an NMOS in saturation region does not depend on the
VDS. Note that this transistor can be modeled as a current source whose current magnitude is in response to
the gate-source overdrive voltage.
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1.4
Reliability issues in Power Amplifiers Design
In PA, amplification of electrical signal requires high voltage and current. So, both the voltage and current of
the transistor are pushed to their limits. In CMOS technology, the limits of the voltage and current are
determined by the following mechanisms [4].
1.4.1 Drain-Bulk Breakdown
The drain-bulk diode experiences a reverse bias. Usually, in standard CMOS process, the bulk is connected
to a fix electrical potential. So the diode reverse bias is directly proportional to the drain voltage. This diode
has a reverse breakdown voltage which in today's processes is relatively low. To avoid diode breakdown, the
drain-bulk voltage is not allowed to reach this breakdown voltage.
1.4.2 Hot Carrier Effect
As complementary metal–oxide–semiconductor (CMOS) technologies are scaled down into the nanometer
range, transistors may experience high lateral electric field if the voltage between the drain and source is
large. High electrical field causes continual increase in the velocity and hence the kinetic energy of the
carrier. Such a carrier is called Hot Carrier [ 3].
Hot carriers can leave the silicon and tunnel through the gate oxide but some of them get trapped in the
oxide, thus changing the threshold voltage and the I-V characteristics of the MOS device [5]. As a
consequence, hot carrier phenomenon can lead to a long-term degradation and the performance of the circuit
might be out of the specification after long time [7].
1.4.3 Time Dependent Dielectric Breakdown TDDB
High voltage between the gate and the channel causes large stress on the gate oxide. Such stress can cause
breakdown in gate oxide if it is applied for a long time. This type of gate oxide breakdown is called Time
Dependent Dielectric Breakdown [1]. This phenomenon causes a permanent damage in the device. But
before it occurs, there is no degradation in the device performances.
1.4.4 Punch-through
At high drain-source voltage, the drain space charge region expands over the channel. For high enough value
of drain-source voltage, the drain can come in contact with the source depletion region. This effect, which is
called punch-through, causes a large increase in the drain current which can lead to a permanent damage in
the device [7].
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Chapter 2
2.1
Important Aspects in PA Design
Introduction
In designing a PA for a wireless communication, it is very important to have good knowledge of the
communication system itself and the signal that needs to be amplified. Therefore, this section will review
some aspects that are important for PA [4].
Initially, the PA is considered in the context of a radio transmitter. There are many transmitter architectures,
but the considered one in this section is “direct-conversion” transmitter. This topology, as shown in Figure
2.1, consists of Mixers, two local oscillator signals (phase-shifted by 90°), PA, and matching network. The
mixer converts a base-band spectrum, which is a digital modulated signal, to the RF spectrum. The PA is the
last active component in the transmitter. The sole purpose of PA is amplifying modulated signal and
providing maximum power delivery to the antenna through the matching network. It is also known that the
PA is the most power hungry component in the transmitter.
Thus, the most important properties of a PA designed for wireless system are output power, efficiency, gain,
and linearity.
Figure 2.1: Direct-conversion transmitter [10].
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2.2
Digital Modulation
Modern communication systems utilize different digital modulation schemes such as Amplitude Shift Keying
ASK, Phase shift Keying PSK, and Frequency Shift Keying FSK. In all types of digital modulation, the
carrier signal is modulated by a digital base-band signal.
Figure 2.2: Amplitude shift keying.
In Binary ASK, the modulated signal toggles between zero and full amplitude. Such a modulation is called
non-constant envelope modulation. In Binary PSK the phase of the modulated signal toggles between 0 0 and
1800. In Binary FSK, the frequency of the modulated signal toggles between two different frequencies.
Figure 2.2, 2.3, and 2.4 illustrate examples of these waveforms for binary base-band signal.
Figure 2.3: Phase-shift keying.
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Figure 2.4: Frequency shift keying.
2.2.1 Bandwidth Efficiency
If B is the bandwidth occupied by a digital modulated signal, one can define spectral efficiency as
η=
Rb
bit / S / Hz
B
(2.1)
where Rb is the bit rate of the transmission and is defined as
Rb =
log 2 M
Number of bit per symbol
=
symbol duration
TS
(2.2)
Thus, the bandwidth efficiency can be increased by increasing the number of bits per each transmitted
symbol. Other modulation schemes, such as Quadrature PSK (QPSK) and Quadrature Amplitude Modulation
QAM, have been introduced to save the bandwidth of the modulated signal. Bandwidth efficiency for
different modulation schemes is shown in Table 2.1.
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Modulation format
Bandwidth efficiency (C/B)
16 PSK
4
16QAM
4
8PSK
3
4PSK
2
4QAM
2
BFSK
1
BPSK
1
Table 2.1 Bandwidth efficiency for different modulation schemes [23].
2.2.2 Signal Constellation
Signal constellation is a way to represent digital modulated signals and visualize the effect of nonidealities
on them.
Figure 2.5 (a) shows a signal constellation for an ideal PSK signal and Figure 1.5 (b) shows a nosy received
PSK signal. The receiver has to distinguish and decide whether the received bit is a ONE or ZERO. If the
received signal is noisier, the two points come closer to each other making the detection more difficult and
prone to error [10].
Figure 2.5: Signal constellation for: (a) ideal PSK signal, (b) noisy received PSK signal.
Figure 2.6 shows a constellation of 16 QAM. The points in this constellation are closer to one another than
those in the PSK constellation, making the detection more sensitive to noise.
Figure 2.6: Constellation of 16 QAM.
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16 QAM modulation scheme, exhibits large envelope variations. Such a modulation scheme requires a
highly – linear PA.
Figure 2.7: Constellation of 16 QAM (noisy received signal).
2.2.3 Error Vector Magnitude (EVM)
Error Vector Magnitude (EVM) is a powerful tool for analysing the effect of various nonidealities, such as
Non-linearity in the PA, in the transceiver, and in the channel. EVM represents deviation of the constellation
points from their ideal position. EVM can be obtained by constructing a constellation based on a large
number of detected samples, as shown in Figure 2.8, a vector is drawn between each measured point and its
ideal constellation position [10].
EVM is defined as
1 1
EVM =
P avg N
N
∑ e 2j
(2.3)
j =1
The maximum acceptable EVM is determined by the standard being employed. Table 2.2 shows the
constellation error and EVM equivalent for IEEE 802.11a [11].
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Figure 2.8: Illustration of EVM.
Data Rate (Mbps)
Relative Constellation Error(dB)
EVM(%RMS)
6
-5
56.2
9
-8
39.8
12
-10
31.6
18
-13
22.3
24
-16
15.8
36
-19
11.2
48
-22
7.9
54
-25
5.6
Table 2.2 Constellation error and EVM equivalent for IEEE 802.11a.
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2.3
Power Amplifier Properties
The most important properties of a PA designed for wireless system are output power, efficiency, gain, and
linearity. These properties are explained in this section.
2.3.1 Output Power
Consider the circuit of Figure 2.9 (a), which shows a PA connected to an antenna. Usually, the antenna
impedance can be considered as pure resistance in the frequencies of interest . So the antenna can be
modeled by a resistor RL, usually 50 Ohm, as shown in Figure 2.9 (b).
The output power is defined as the active power delivered by the PA into the antenna.
(a)
(b)
Figure 2.9: (a) Power amplifier connected to an antenna, (b) Antenna modeled by pure resistance.
The instantaneous output power is defined as
P 0 (t)=v0ut (t ).i out (t)
(2.4)
and the total power is defined as
T
2
1
P o,tot= lim ( ) ∫ P0 (t ) dt
T → ∞ T −T
(2.5)
2
Assuming that the output signal is a sine wave with frequency f C, the total power is defined as
P o,tot=
1
Tc
Tc
2
∫ P 0 (t )dt
(2.6)
−T c
2
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Finally, assuming a pure resistive load, the output power is defined as
2
V
P o,tot= 0,rms
RL
(2.7)
and
2
V
P o,tot= 0
2 RL
(2.8)
where V0 is the supply voltage.
2.3.2 Power Gain
The power gain, usually expressed in dB, is defined as the ratio between the output power to the input power
G P,dB=10 log 10 (
P0
).
P in
(2.9)
2.3.3 Peak Output Power, Peak to Average Power Ratio and Crest Factor
As it has been mentioned above, different communication systems utilize different modulation schemes. For
a constant envelope modulation schemes (with constant output power), one could define a fixed envelope
output power (P0(A)) as the average output power dissipated in the load as
2
A
P 0 ( A)=
2 RL
(2.10)
where A, the amplitude of output signal, is constant.
On the other hand, for a non-constant envelope modulation schemes, the PA will operate at a relatively low
output power but also deliver large power peaks for small fraction of time. Assuming that the PA operates at
the maximum output power all the time, one can define a Peak Envelope output Power (PEP) as
2
A
(max {A(t)})2
PEP = Max { P 0 ( A(t))} =
= max
2RL
2RL
(2.11)
The Peak Envelope output Power can be much higher than the average output power (P0). In this regard, one
can define a Peak to Average Power Ratio (PAPR) as
PAPR =
PEP
P0
(2.12)
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where P0 is define as
2
V
P o= 0,rms
2R L
(2.13)
This can also be calculated based on voltages, which gives what is known as Crest Factor (CF)
CF =
V 0, max
V 0, rms
(2.14)
2.3.4 Efficiency
As it has been mentioned above, the PA is the most hungry component of a transmitter so an important
property is the efficiency. One of efficiency measurement is the drain efficiency ƞd which is defined as the
ratio between the average output power (P 0) and the DC power consumption of the PA (PDC,PA)
ηd =
P0
(2.15)
P DC , PA
In some cases, when the PA has a relatively low power gain, the input power P in becomes a considerable
value in efficiency measurement. This measurement is known as Power Added Efficiency (PAE). It is also
useful when the PA is a multi-stage amplifier. The PAE is defined as
PAE=
P 0 −Pin
P DC ,tot
(2.16)
where the (PDC,tot) is the total DC power consumption by the PA and all other amplifier stages.
2.3.5 Linearity
As it has been mentioned previously, several communication systems utilize modulation schemes with nonconstant envelope where information is contained in the amplitude of the modulated signal. Such a
modulated signal needs to be amplified by a linear amplifier, which means that the gain of the PA is equal
over a range of different input amplitude. Otherwise, the output waveform will have different shape from the
input waveform and information will be corrupted.
All PAs experience a reduction of gain at high input amplitude. So, the output power will be lower than the
expected, as illustrated in Figure 2.10. This effect can be quantified by the P1dB compression point. The P1dB
compression point is defined as the point where the output power is 1 dB lower than the anticipated from the
gain in the linear region [3].
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Figure 2.10: Illustration of P1dB compression point.
There are two important metrics to express the nonlinearity of a PA, the Error Vector Magnitude (EVM),
which already has been discussed, and the Adjacent Channel Power Ratio (ACPR).
2.3.5.1 Adjacent Channel Power Ratio
The nonlinearity of a PA causes a power leakage in the adjacent channels. If the leakage power reaches a
predefined level, the adjacent channels may be disturbed. Therefore, the transmission should occur in a
limited bandwidth. The traditional way for testing adjacent channel is called two tone test, where two inchannel tones is used to measure the out-of-channel distortion. However, this testing method is not good
enough for the real applications of wide-bandwidth wireless systems. A better measurement is what called
ACPR measurement which is defined as the ratio of the integrated signal power in an adjacent channel to the
integrated signal power in the main channel [25].
It is also important to mention that reducing the power leakage leads to decrease the power consumption thus
increasing the battery life for the mobile device. Figure 2.11 shows an example for ACPR measurements.
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Figure 2.11: An example of ACPR measurement [37].
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2.4
Matching Network
In RF and microwave, components such as antenna and antenna-filters have single ended input and output
impedances of 50 ohm. Consider the circuit shown in Figure 2.9 (a), the PA is directly connected to the antenna.
The antenna can be modeled as resistance (R L). This is shown in Figure 2.9 (b) and the output power delivered to
RL can be defined as
V 2DD
P out =
2 RL
(2.17)
As an example, if the supply voltage is 1.2 V, then the output power will be only 14.4 mW So, to achieve a
sufficient out power, matching network is needed to transform R L to some lower resistance. Generally, in PA
design, the maximum power transfer theory is useless for two reasons. The first reason is that it is fuzzy and
difficult to define impedance in large-signal, nonlinear system. The other reason is, in maximum power transfer
theory, the efficiency would be only 50 % because equal amount of power will be dissipated on the source and
load. For these reasons, the PA is designed to deliver a specified amount power with highest possible efficiency
and with an acceptable gain [12]. Instead of matching to maximum power transfer, the input and output
impedance of the PA are matched to achieve maximum gain and maximum output power respectively.
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2.4.1 Load Line Theory
In PA design, the load line theory can help the designer to know if the transistor is working with the full
power capability or not. This is done by studying the current and voltage waveforms. The load line theory
can also help the designer to predict the optimum output resistance, R OL, that the transistor should see for
delivering the maximum linear output power.
I2
I1
V1
V2
Figure 2.12: Load line imposed on IV-curve.
Figure 2.12 shows three load lines for three different loads seen by the transistor, imposed on I-V curves. All
lines are centred on the bias point of the transistor. The slope of each load line is equal to the susceptance of
the corresponding load [29]. The minimum and maximum drain current is zero and I D,max, respectively. The
minimum and maximum drain to source voltage is V knee and 2VDD-Vknee, respectively. The optimum load can
be defined as [30]
R LO =
V DS , max
I D , max
(2.18)
For RL = RLO, the current swings fully between zero and I D,max and the voltage swings fully between V knee and
2VDD-Vknee. Thus, the transistor is working with full power capability. For R L < RLO, the voltage swings
between V1 and and V2,thus the voltage is limiting the output power. For RL > RLO, the current swings
between I1 and I2, thus the current is limiting the output power.
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2.4.2 Load-pull
In deep-submicron CMOS technologies, the voltage knee as high as 50 % of the supply voltage [30]. Thus,
the load line concept may not be a good approach to determine the optimum load resistor for the MOS device
as the transistor would not work with full power capability. A better approach to determine the optimum
resistor is to use load-pull technique [3].
Consider the circuit shown in Figure 13 (a), where a passive matching network is used to present a complex
load impedance, Z1, to the transistor M1. The real and the imaginary part of Z 1 is varied in a way such that
the power delivered to the R L is constant and equal to P1. This yields the contour shown in Figure 13 (b).
Next step is to seek those values of Z 1 that gives higher power, P2, yielding another contour. A high P2
corresponds to narrower rang of Re{Z1}and Im{Z1}, hence tighter contour. These “load-pull” measurements
can be iterated to increase the power level, until reaching an optimum impedance, Z opt, for the maximum
power level.
Figure 2.13: (a) Load-pull test, (b) contours used in load-pull test, (c) input and output matching networks.
Due to gate-drain capacitance of M1, varying Z 1 may have some effect on the input impedance of the
transistor, Zin. Thus, the power delivered to the transistor varies with Z 1, which could yield a variable power
gain. This effect can be eliminated by tuning the input matching network, shown in Figure 2.13 (c), to obtain
the required power gain.
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2.4.3 Passive Impedance Transformation
For operating frequency between 1 and 10 GHz, passive matching networks (consist of lumped inductors and
capacitors) are used to transform impedance from high to low and vice versa. The drawback with passive
matching network is that they suffer from losses especially if they are built on silicon chips because of the
low substrate resistivity. Therefore, passive matching networks are not easy to integrate [13].
2.4.4 Quality Factor Q
To understand the limitation of passive matching network design, the quality factor of passive components
are discussed here. Many different definitions can be found in literature for quality factor (Q). Generally, a Q
for a device indicates how close to ideal this device stores energy. For example, a capacitor said to be ideal if
it dissipates no energy. Such a capacitor exhibits an infinite Q. But in reality, passive elements are not ideal
and they always dissipate energy. Loss due energy dissipation can be modeled by adding a resistance in
series or in parallel.
Figure 2.14: Inductor with loss. (a) Series model and (b) parallel model [4].
Figure 2.14 (a) shows a circuit of an inductor with series resistance. The Q of this circuit can be defined as
QS =
X S w LS
=
RS
RS
(2.18)
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This series circuit can be converted to parallel network as shown in Figure 2.14 (b). The Q of this circuit can
be defined as
Qp =
Rp
Rp
=
X p w Lp
(2.19)
Similar concepts can be applied to capacitors. The Q can be defined as
QS =
1
RS w C S
(2.20)
Qp =
Rp
= Rp w C p
Xp
(2.21)
and
2.4.5 L-Match Network
There are many types of matching networks topologies like L-match, T-match, pi-match, and Tapped
Capacitor Resonator match.
An excellent candidate topology for CMOS integration is L-match topology, which is discussed in this
section. An elaborate discussion on other topologies can be found in [12], [31]-[32] and will not be reported
here.
A common situation in RF transmitter design is that an impedance must be transformed from high to low
value (like the load resistance of a PA) using matching network circuit shown in Figure 2.15 (a) or from low
to high (like the source impedance of a PA) using the circuit shown in Figure 2.15 (b).
Figure 2.15: Matching network. (a) High to low transformation and (b) low to high transformation.
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2.4.5.1 High to Low Transformation
High to low transformation can be accomplished by the circuit shown in Figure 2.16 (a), where the load
impedance is transformed from RL to a lower value Rin. The parallel circuit of CP and RL can be converted to a
series equivalent circuit of CS and R1 as shown in Figure 2.16 (b).
Figure 2.16: L-match impedance transformation network.
The value of CS and R1 can be calculated as
R1 =
RL
(2.22)
1+Q 2C
C S = C P⋅(1+
1
)
2
QC
(2.23)
where QC is
QC =
RL
1/(w C P )
(2.24)
The L1is designed to be in resonance with CS at the operating frequency ɷ0, which can be defined as
ω0 =
1
1/ √ L1 C S
(2.25)
Thus, at resonance frequency ɷ0 , L1and CS provide a short circuit and the input impedance of the matching
network Rin is equal to R1. This is shown in Figure 2.16 (c).
The impedance transformation ratio (r) is defined as
r=
RL
Rin
(2.26)
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An important parameter in designing a matching network for PA is the power enhancement ratio, E, which is
the ratio between the output power with the matching network (P out) and the output power without the
matching network Pout,1 [4].
E=
P out
P out ,1
(2.27)
If the above circuit is assumed to be loss-less, the power enhancement ratio is the same as the impedance
transformation ratio r.
2.4.5.2 Inductor Loss and Efficiency
The overall loss of an L-match network is dominated by the inductor loss which can be modeled as a series
resistance (Rlm) as shown in Figure 2.17 (a). At the resonance frequency, the equivalent circuit of the
matching network and RL is shown in Figure 2.17 (b).
Figure 2.17: L-match impedance transformation network with series inductor loss.
Thus, the input impedance of the matching network can be written as
Rin = R1+ RLm
(2.28)
And the impedance transformation ratio is
r=
RL
R 1+R Lm
(2.29)
The power delivered to the load is
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R1
2
P out =V DD
(2.30)
2( R1 +R Lm )2
and the total input power to the matching network is
2
V DD
P in,L =
2( R1 +R Lm )
(2.31)
Thus, the efficiency of the matching network can be calculated as
ηL =
P out
R1
=
P in,L
R1 +R Lm
(2.32)
So, the efficiency of the matching network is inversely proportional to the parasitic resistance of the inductor.
Figure 2.18 shows the relationship between the power enhancement and the efficiency of an L-match
network for different values of inductor quality factor. At higher values of E, the efficiency will decrease.
Figure 2.18: Relationship between the power enhancement
and the efficiency of an L-match network [4].
Recall the example which has been discussed above. For supply voltage of 1.2 V, the output power without
using matching network was 14.4 mw. Now, assume that a matching network is used to convert the load
impedance. Also assume the the quality factor of the used inductor is 15. From Figure 1.18, if the minimum
acceptable efficiency of the matching network is 80 %, then the allowable power enhancement ratio is 10.
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Thus the delivered power to the load is 144 mW. To achieve higher output power for a given power
enhancement ratio, the supply voltage of the PA has to be increased and a reliable operation has to be
maintain [4].
2.5
HV-MOS Devices
The rapid technology evolution of CMOS has largely improved the radio frequency performance of MOS
devices, such as large RF gain, higher cut-off frequency (F T), and maximum oscillation frequency (F max).
This has made CMOS device technology the prime choice for RF system-on-chip (SoC) applications, such as
WCDMA, W-LAN, and ultra-wide band (UWB) wireless communication. Nowadays, CMOS technologies
represent an alternative to III-V technologies in RF PAs design. However, low drain break down voltage and
other reliability issues of nanometer CMOS transistors reduce the maximum output power and efficiency for
RF PAs. When the SoC design includes the PA, it is therefore challenging using a baseline CMOS logic
process [14]-[16].
To overcome the reliability issues in PA design, one can use circuit solution that can handle higher voltage
such as cascode configuration, where standard thick-oxide transistors are stacked in a cascode configuration
to eliminate the effect of oxide breakdown voltage and to make use of a larger supply voltage. The other
solution is to use high-voltage MOS, H-V MOS devices. Due to their ability to integrate with the low
modules in MOS, HV-MOS devices have became an accessible solution for power integrated circuits. Today,
HV-MOS devices are used in many applications, like switch-mode power supplies, motor drivers, and PAs
[17]-[19].
Generally, HV-MOS devices are classified into two types, Extended Drain MOSFET devices (EDMOS) and
Lateral double-Diffused MOSFET (LDMOS) devices. The LDMOS devices require extra process and that
increases the process complexity and cost. Thus, LDMOS devices will not be reported here and eager readers
can refer to [21], [33]-[36].
2.5.1 Extended Drain MOS Devices
The nominal voltages of modern digital VLSI circuits are at 1.8 V level and below. However, such circuits
are often needs to be integrated with other circuits operating at 3.3/5.0 V or even higher. Example circuits are
power management switches that regulate power from battery or system supplies, output analog drive
functions for speakers, and RF PAs [19].
In analog system, reliability issues represent great challenge for the system designers. To handle 3.3 V, thick
-oxide transistors are added into all processes. One solution to handle greater supply voltage is to use devices
like Extended Drain MOS (EDMOS) transistors [26], [27]. They can cope with higher drain voltages without
significant loss of performance and without added process complexity. Figure 2.19 shows the structures of
N-EDMOS and P-EDMOS.
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(a)
(b)
Figure 2.19: Structures of (a) N-EDMOS, (b) P-EDMOS [17].
This structure requires one extra mask and one implantation step to build the drain extension [17]. By
extending the drain region, the electric field under the gate at the drain end of the transistor is reduced, thus,
the breakdown voltage is increased.
31
Chapter 3
Power Amplifier Classification
________________________________________________________________________________________________________________________________________________________________
Chapter 3
Power Amplifier Classification
As the previous chapter covered some important concepts in PA design, this chapter describes the PA
classification and the trade-off between linearity and efficiency.
Generally, PAs can be divided into two groups, linear amplifiers and switching amplifiers.
3.1
Linear Power Amplifiers
In linear amplifiers, the active device is used as current source. They are classified to class-A, B, C, and AB
PA. All these classes may be understood by studying one single model shown in Figure 3.1. The only
difference between these classes is the way of gate biasing of the transistor.
Figure 3.1: Common source linear power amplifier. [12]
32
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Power Amplifier Classification
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3.1.1 Class-A Power Amplifier
In class-A PA, the transistor is biased in a way so that it is always on and never turns off, which means that
the conduction angle of the PA is 360°. To satisfy this condition, the transistor has to be kept in saturation
region all the time.
Figure 3.2: Drain voltage and current for ideal class-A amplifier [12].
Figure 3.2 shows the drain voltage and the drain current waveforms. Since the input voltage is sinusoidal, the
figure shows a linear relationship between the input voltage and the output current.
Even when there is no input signal, the transistor is always on and dissipates energy because of the bias
current. So, class-A PA provides a linear signal but at the expense of efficiency.
The efficiency can be computed by, first, calculating the signal power delivered to R L as:
i 2rf R L
P rf =
2
(3.1)
where (irf)2 is the amplitude of the the RF signal component of the drain current.
The second step is to calculate the DC power supplied to the amplifier as
P DC = I DC V DD
(3.2)
To guarantee that the transistor never turns off, I DC should at least equal to irf, so
P DC = i rf V DD
(3.3)
Finally, the drain efficiency is defined as
P rf
I 2rf ( R/2)
i R
η=
=
= rf L
P DC
i rf V DD
2V DD
33
(3.4)
Chapter 3
Power Amplifier Classification
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Now, the maximum value of the product (irfRL = VDD), so the maximum efficiency can be defined as
η Max =
V DD
= 50 %
2V DD
(3.5)
The above calculations show that maximum efficiency in class-A PA is 50 %. Different parameters, like
variation in bias condition, non ideal drive amplitude and losses in the filter, cause the efficiency to drop
below the 50 %. In practice, drain efficiencies of 30-35 % are not unusual.
An other important issue to be discussed is the stress on the transistor M1. In class A amplifiers, the
transistor M1 experiences maximum drain-to-source voltage, V DS,max= 2VDD, while the peak drain current,
iD,max=2VDD/RL. The device has to be able to handle the stress resulted from these peaks of voltage and current
even though they do not occur simultaneously.
One common way to quantify this stress is to define what is called normalized power output capability P N
which is defined as
PN =
actual output power
v DS , max .i D , max
(3.6)
So, for class-A amplifiers, the normalized power output capability is
V 2DD /(2 R L )
1
PN =
=
(2V DD )(V DD / R L ) 8
(3.7)
3.1.2 Class-B Power Amplifier
The efficiency of a linear amplifier can be increased by decreasing power dissipation by forcing the
waveform of either drain current or drain voltage to be non-sinusoidal, so that the product of drain current
and drain voltage decreases. This can be done by lowering the input bias point, so the transistor is in nonconducting state for a part of time [28].
With this condition of conduction, one can expect large distortion at the output voltage. To get a fairly
sinusoidal output signal, a high-Q tank is needed at the output of the PA [1].
In class-B PA, the transistor is bias in a way so that it is off half of every cycle, which means that the
conduction angle of the PA is 180°.
34
Chapter 3
Power Amplifier Classification
________________________________________________________________________________________________________________________________________________________________
Figure 3.3: Drain voltage and current for ideal class-B amplifier [12].
The drain current and drain voltage waveform are shown in Figure 2.3. To compute the efficiency, the
fundamental component of the drain current should be calculated, which is defined as
i fund
2
=
T
T /2
∫ i rf (sin w0 t )(sin w0 t)dt =
0
i rf
2
(3.8)
The output voltage is defined as
v out =
i rf
R sin w 0 t
2 L
(3.9)
Since the maximum possible value of vout is VDD, then the maximum value of irf is
i rf,max =
2V DD
RL
2
(3.10)
The output power is calculated as
v 20
P0 =
2R L
(3.11)
where V0 is the amplitude of the signal across RL.
Given that the maximum value of v0 is VDD, the maximum output power is
V 2DD
P 0,max =
2 RL
(3.12)
To compute the DC input power, the average drain current is needed to be calculated, which is defined as
35
Chapter 3
Power Amplifier Classification
________________________________________________________________________________________________________________________________________________________________
1
i D , avg =
T
T /2
∫2
0
V DD
2V DD
sin w 0 t dt =
R
πR
(3.13)
The DC power is
P DC
2V 2DD
= V DD i D , avg =
π RL
(3.14)
Finally, the maximum drain efficiency is
η=
P 0, max π
=  0.785
P DC
4
(3.15)
Thus, the drain efficiency of class-B PA is higher than for class-Amplifier, but at the expense of more
distortion.
The output power, id,max, and vDS,max are the same for class-A amplifier, so the normalized power output
capability for this class is the same as for class-A amplifier as well.
3.1.3 Class-C Power Amplifier
In class-C PA, the the bias voltage is arranged in a way that the transistor is turned off more than on. Thus,
the efficiency is increased. Figure 3.4 shows the waveforms of the drain current and drain voltage. The drain
consists of periodic pulses.
Figure 3.4: Drain voltage and current for ideal class-C amplifier [12].
Full derivation of efficiency is given in [12], [13]. The drain efficiency is defined as
ηmax =
2 ϕ−sin 2 ϕ
4(sin ϕ−ϕ cos ϕ)
(3.16)
where ɸ is the conduction angle.
36
Chapter 3
Power Amplifier Classification
________________________________________________________________________________________________________________________________________________________________
As the conduction angle approaches zero, the efficiency approaches 100 %. But, at the same time, the powerhandling capability of the amplifier approaches zero. In practice, the PA has to deliver a reasonable amount
of power with high efficiency. Thus, a trade-off between efficiency output power is required.
Compared to class-B, one can expect more distortion at the output voltage. Thus, class-C PA has lower
linearly than class-A and class-B.
3.1.4 Class-AB Power Amplifier
Depending on the bias level, class-AB PA conducts somewhere between 50% and 100% of the cycle. So the
conduction angle of class-AB PA is somewhere in between class-A and class-B conduction angles. As a
result, class-AB PA achieves better linearity than class-B, but at reduced efficiency. Class-AB PA is more
popular than other classes because of the possibility of getting an acceptable trade-off between linearity and
efficiency.
37
Chapter 3
Power Amplifier Classification
________________________________________________________________________________________________________________________________________________________________
3.2
Switching Power Amplifiers
The second group of PA is switching amplifiers which use the device as a switch. An ideal switch
experiences either zero voltage across it or zero current through it. Therefore, the V-I product is always zero.
In other words, an ideal switch dissipates no power.
3.2.1 Class-D Power Amplifier
One type of switching amplifiers is class-D amplifier. Figure 3.5 shows a model of class-D amplifier. The
connection at the input side guarantees that, at a given time, only one transistor is driven on. One has to make
sure that the transistors are driven hard enough so they act like switch.
Figure 3.5: Class-D amplifier.
As the transistor M1 and M2 switches on and off alternately, each terminal of the primary winding of T2 is
driven to ground alternately as well. This action yields a square-wave voltage across the primary winding of
T2. As a consequence, a square-wave voltage appears at the secondary winding of T2. Because of the series
LC tank only the fundamental component of the square-wave is allowed to flow to R L. So, the secondary
current, as well as the primary current, is a sine-wave. See Figure 3.6.
Figure 3.6: T2 secondary voltage and current for ideal class-D amplifier.
38
Chapter 3
Power Amplifier Classification
________________________________________________________________________________________________________________________________________________________________
Figure 3.7: M1 drain voltage and current for ideal class-D amplifier.
Figure 3.7 shows the drain voltage and drain current of transistor M1 for ideal class-D amplifier. Because of
the switching action, transistor M1 sees a sine-wave current for the half-cycle that it is on and because of the
transformer T2 the drain voltage is forced to 2V DD.
The normalized power output capability of class-D amplifier can be defined as [12]
PN =
P0
1
= π  0.32
V DS , on i D , pk
(3.17)
So, the stress on the devices in class-D amplifier is much less than the stress on the devices in class-A and
class-B amplifiers.
Figure 3.8: Inverter-based class-D amplifier [9].
An other architecture of class-D is the inverter-based switched amplifier, which is shown in Figure 3.7. There
are many advantages for this architecture, such as that the peak drain voltage dose not exceed the supply
voltage. So the stress on the devices is low compared with the stress on the device in the first architecture.
39
Chapter 3
Power Amplifier Classification
________________________________________________________________________________________________________________________________________________________________
Other advantages are high bandwidth and the insensitivity of load impedance. However, this architecture
requires fast p-devices, which have not been available until about the 130 nm CMOS node. The drawback
with this architecture is that it suffers from short-circuit power dissipation, power consumption due to drain
capacitance, and power losses due to strong harmonics [9].
3.2.2 Class-E Amplifier
To get an efficiency of 100 % in class-D amplifiers, the assumption was that the transistors act like ideal
switches. In reality, transistors suffer from the parasitic output capacitance. During the switching action, the
transistor may carry some voltage across it when it conducts current. Thus, the power dissipated by the
transistor is no longer zero.
In class-E amplifier shown in Figure 3.8, the drain-to-source voltage is forced to have a zero value and zero
slope at switch turn on. This shaping of the drain voltage is done with help of the high-order reactive
network. Thus, during turn-on transition, the transistor dissipates no power.
Figure 3.9: Class-E amplifier.
One drawback with class-E PA is that the drain current, shown in Figure 3.8, is nearly a maximum during the
off transition which can lead to a significant power dissipation during that transition.
Shown in Figure 3.9, the peak drain voltage is roughly 3.6 V DD and the peak drain current is approximately
1.7VDD / RL.
40
Chapter 3
Power Amplifier Classification
________________________________________________________________________________________________________________________________________________________________
Figure 3.10: Waveform for class-E amplifier.
The maximum output power I delivered to RL can be defined as
V 2DD
V 2DD
2
P0 =
⋅
 0.577
RL
(1+π 2 /4) R L
(3.18)
and the normalized power output capability is
PN =
P0
 0.098.
V DS , on i D , pk
(3.19)
Thus, the class-E amplifier has a very poor output capability and the transistor M1 has to cope with a very
high stress. Therefore, class-E have been quite popular in large discrete PAs but not found wide application
in SoC CMOS technologies.
41
Chapter 3
Power Amplifier Classification
________________________________________________________________________________________________________________________________________________________________
3.2.3 Class-F Power Amplifier
A major drawback with class-E amplifier was that this amplifier does nothing for the power dissipation
during the off transition. However, class-F amplifier has the ability to shape the drain voltage in a way so
there is no power dissipation caused by switching activity. Thus, the efficiency of class-F amplifier is 100 %.
A class-F amplifier is shown in Figure 2.10. A tank is connected in parallel with R L. One should make sure
that the Q of the tank is high enough so it acts as a short circuit at all frequencies out of the desired
bandwidth. The drain of the M1 is connected to a transmission line. At the fundamental frequency, the
length(l) of the transmission line is λ/4.
Figure 3.11: Class-F amplifier.
The impedance seen by the drain of M1 can be defined as
Z load = Z 0
R L + j Z 0 tan(2 πl / λ)
Z 0 + j R L tan(2 πl / λ)
(3.20)
where Z0 is characteristic impedance of the transmission line.
At the fundamental frequency,the length l = λ/4, so the impedance seen by the drain is Z02 / RL.
At all even harmonics, the tank acts as a short circuit. Thus, the impedance seen by the drain is (Z load=zero).
At all odd harmonics, the tank acts as an open circuit. Thus, the impedance seen by the drain is Z load=∞.
Figure 3.11 shows the drain voltage and drain current waveforms of M1. If the applied voltage at the gate is a
square wave with 50 % duty cycle, the drain voltage well also be a square-wave. Since the transmission line
acts as an open circuit at all odd harmonics above the fundamental, the drain current is purely sinusoidal. The
even harmonics are not taken in account, since the 50 % duty cycle square-wave contains no such harmonics.
42
Chapter 3
Power Amplifier Classification
________________________________________________________________________________________________________________________________________________________________
Figure 3.12: Drain voltage and current for ideal class-F amplifier.
The output power delivered to the load is defined as
[(4/π)V DD ] 2
P0 =
2 RL
(3.21)
From Figure 2.10, Vds,on = 2VDD and iD,pk = 8VDD /πRL. Thus, the normalized power output capability is
calculated as
PN =
P0
1
= π  0.16.
V DS , on i D , pk
(3.22)
One drawback in class-F amplifier implementation is that several resonant with high Q is needed to achieve a
high efficiency, which requires additional area. One other drawback is that λ/4 transmission line can not be
directly integrated at typical wireless communications frequencies (1-6 GHz) [9].
43
Chapter 4
Test Bench and Simulation Results
________________________________________________________________________________________________________________________________________________________________
Chapter 4
4.1
Test Bench and Simulation Results
Introduction
In this chapter, performances for different integrated CMOS class-AB PAs have been analysed and studied.
The PAs are designed for watt level output power and 2.4 GHz operating frequency for WLAN. The used
supply voltage is 3.3 V.
As it has been mentioned previously, the output power delivered to the load (antenna) can be defined as:
2
P out =V DD /2 RL
To reach high output power, high voltage (special devices, process features, design features) or high current
(matching network or power combination using passives) could be used.
The low drain breakdown voltage of modern CMOS transistors reduces the maximum output power and
efficiency for RF PAs (PAs). When the SoC design includes the PA, it is therefore challenging using a
baseline CMOS logic process. The conventional design approach to allow PAs being operated at high supply
voltage is to use a cascode structure, as shown in Figure 4.1.
Figure 4.1: Cascode structure PA.
44
Chapter 4
Test Bench and Simulation Results
________________________________________________________________________________________________________________________________________________________________
The other approach is to use single HV-MOS devise. In the past, LDMOS transistors were introduced to
overcome the low drain breakdown voltage issue at the expense of complex process and lower operation
speed. Lately, high-voltage MOS devices with no added process steps or masks have been realized by using
the CMOS well implants for the formation of the extended drain regions. Such EDMOS devices are now
available in some foundry processes.
The aims of this project are to analyse (simulation study) and compare the performances of conventional
CMOS circuit solution (cascode with different types of transistors) and the HV-MOS device solution
(EDMOS device) for class-AB PA design. The examined performances are output power, gain, efficiency,
linearity, design complexity of matching network, and area consumption. The comparison is between
different types of cascode PA with an EDMOS PA.
4.2
Tools and Programs
The technical part of this project includes a simulation study of RF PA performances of different structures in
65nm CMOS using foundry PDKs. All the schematics have been created using the Cadence Virtuoso CAD
tools. The test benches have been created using the Agilent's Advance Design System, ADS, and simulated
with the ADS-Cadence dynamic link.
4.3
Structure of Class-AB Power Amplifier
As shown in Figure 4.2, class-AB PA can be considered as three main blocks The first block is the matching
network at the input side (the input impedance is matched for high gain), the second block is the core of the
PA, and the third block is the matching network at the output side (the output impedance is matched for high
P-1dB compression point).
Figure 4.2: Power amplifier, core and matching networks.
4.3.1 Cascode Power Amplifier
The cascode PA is shown in Figure 4.3. The first and third blocks consist of passive components (L and C).
The second block consists of two stacked transistors (M1 and M2). Four different cascode PAs have been
45
Chapter 4
Test Bench and Simulation Results
________________________________________________________________________________________________________________________________________________________________
tested. All the different cascode PAs use the same device (dgnfettw_rf, L=500 nm) for the upper transistor
M2, but different devices (L= 500, 350, 260, 60 nm) are used for the lower transistor (M1).
Figure 4.3: Schematic of class AB cascode power amplifier.
46
Chapter 4
Test Bench and Simulation Results
________________________________________________________________________________________________________________________________________________________________
4.3.2 EDMOS power amplifier
For the EDMOS PA, shown in Figure 4.4, the first and third blocks have the same topology as the cascode
PAs. In the second block, the used transistor is EDMOS (ednfet_rf, L=350 nm). Figure 4.5 shows a cross
section of EDMOS. DC, RF, and power characterization of this device are presented in [20].
Figure 4.4: Cross-section of EDMOS device [20].
Figure 4.5: Schematic of class-AB, EDMOS power amplifier.
47
Chapter 4
Test Bench and Simulation Results
________________________________________________________________________________________________________________________________________________________________
4.4
Test Bench
Two test benches, shown in Figure 4.6 and Figure 4.7, have been created using ADS. For each type of PAs,
several metrics have been measured and studied using different simulation. The used simulations in the test
bench no.1 are
•
Gain Compression (GC)
The Gain Compression simulation has been used to measure output power, gain, and power added
efficiency. It is also used to measure the impedance seen at the input side Z in and the output side Zout
of the PA.
•
Optimizer
The Optimizer has been used together with the Gain Comparison simulation to tune the matching
network of the input impedance for acceptably high gain (11 to 14 dB) and tune the matching
network of the output impedance for maximum output power (30 dBm level).
•
Harmonic Balance (HB)
The Harmonic Balance simulation has been used to measure the P out-Pin characteristics,
which shows the deviation of the gain (in dB) from a small signal gain before it starts
dropping at high output power levels. It appears from practical experiences that the less
variation in gain, especially close to P1dB, the more linear the device will be.
The used simulations in the second test bench are
•
Envelope Box and the WLAN_802_11a_TX
The Envelope simulation has been used to measure the EVM of the PA. The WLAN_802_11_a_TX
simulation has been used to generate a digital modulated signal which is necessary for EVM
measurements. The data rate of the modulated signal is 54 Mbps. From Table 2.2, the maximum
acceptable EVM is 5.6 %.
48
Chapter 4
Test Bench and Simulation Results
________________________________________________________________________________________________________________________________________________________________
Figure 4.6: Test bench no.1.
Figure 4.7: Test bench no.2.
49
Chapter 4
Test Bench and Simulation Results
________________________________________________________________________________________________________________________________________________________________
4.5
Devices Parameters
The parameters of the devices used in all different types of PAs are shown in Table 4.1.
Device Type of device Length (nm)
Finger
name
width (um)
No. of
fingers
Multiplicity Total width (um)
M1
dgnfet_rf
500
20
10
14
2800
M2
dgnfettw_rf
500
20
10
14
2800
M1
dgnfet_rf
350
20
10
14
2800
M2
dgnfettw_rf
500
20
10
14
2800
M1
dgnfet_rf
260
20
10
14
2800
M2
dgnfettw_rf
500
20
10
14
2800
Cascode
no. 4
M1
dgnfet_rf
60
20
10
14
2800
M2
dgnfettw_rf
500
20
10
14
2800
EDMOS
M1
ednfet_rf
350
20
5x2
14
2800
Cascode
no. 1
Cascode
no. 2
Cascode
no. 3
Table 4.1 Devices size and parameters.
4.6
Simulation Results
4.6.1 Simulation Results of Test Bench No.1
As it has been mention above, two test benches has been created using ADS. Table 4.2 shows the simulation
results using test bench no.1.
PAE
(%)
Z in
(Ohm)
Z out
(Ohm)
Z source
Z in
ZL
Z out
P out – P in
[dB]
11.5
44.8
7.5
8.7
6.6
5.7
0.81
54
12.9
44.1
11.1
6.3
4.4
7.8
0.01
830
59
10.4
49.5
16.3
7.0
3.0
7.0
0.07
30.0
1016
73
8.0
52.2
21.4
9.1
2.3
5.4
12.60
28.7
748
53
13.0
38.3
4.6
4.8
10.7
10.2
0.60
P out
[dBm]
P out
(mW )
P out
M
Cascode
no. 1
27.7
601
43
Cascode
no. 2
28.7
757
Cascode
no. 3
29.1
Cascode
no. 4
EDMOS
PA
type
Gain
[dB]
Table 4.2 performances and results.
All metrics shown in Table 4.2 will be discussed in section 4.7.
50
Chapter 4
Test Bench and Simulation Results
________________________________________________________________________________________________________________________________________________________________
4.6.2
Simulation Results of Test Bench No.2
To see the relation between output power and EVM, several simulations, with different values of input
power, have been done for each PA. By increasing the input power, the output power, P peak [dBm], increases
as well as the EVM. Figure 4.8 Shows the EVM vs P peak of all PAs according to the simulation results. It was
simulated using an 801.11a signal with 54 Mbps, which means an EVM limit of 5.6 % (according to Table
2.2).
Figure 4.8: Ppeak VS EVM.
4.7
Discussion / Interpretation
In this section, results from both test benches are discussed in details.
4.7.1 Power Density (Pout / M)
The metric (Pout / M) represents the output power density per device, where P out is the output power in mW
and M is the number of devices. Different numbers of devices have been tested (not shown). The simulations
show that the output power of a PA is directly proportional to the number of the devices. Thus, the power
density per device is constant for each type of PAs.
It is obvious from Table 4.2 that the cascode no. 4 has the maximum power density (73 mW / device). From
the output power point of view, cascode no. 4, is the best choice. On the other hand, this PA has very poor
linearity. This is also shown in Figure 4.8. Thus, from linearity point of view, cascode no. 4 is the worse
choice. This issue also shows the trade-off between the output power and linearity.
51
Chapter 4
Test Bench and Simulation Results
________________________________________________________________________________________________________________________________________________________________
4.7.2 Error Vector Magnitude (EVM) and PPeak
Figure 4.8 shows the PPeak[dBm] verses the EVM curves for all PAs. For EVM ≤ 5.6 %, the allowable output
power can be extracted from the PA is shown in Table 4.3. Thus, from linearity point of view, cascode no. 2
is more linear than the other types.
PA type
P Peak [dBm]
Cascode no.1
29.1
Cascode no.2
30.7
Cascode no.3
24.1
Cascode no.4
7.3
EDMOS
25.1
Table 4.3 Peak output power measurements (estimation).
4.7.3 Pout – Pin
As it has been mentioned above, it appears from practical experiences that the less variation in gain,
especially close to P-1dB, the more linear device will be. Thus, cascode no. 2 is the most linear PA.
4.7.4 Area
To have a good estimation for area consumption, layouts for all types of PA have been implemented by Ted
Johansson using Cadence. The required area for one cell are determined as shown in Table 4.4.
PA type
Width (um)
Length (um)
Total area for one
cell (um2)
Cascode no.1
33.5
28
938
Cascode no.2
33.5
28
938
Cascode no.3
33.5
28
938
Cascode no.4
63.5
28
1778
EDMOS
17
23
391
Table 4.4 Area measurements (estimation).
According to table 4.4, the first, second and third cascode PAs occupy almost the same area, which is about
two and half times larger than the area occupied by the EDMOS PA. The area occupied by cascode no. 4 is
about four and half times the area occupied by the EDMOS PA. Thus, from area consumption point of view,
the EDMOS PA is the best choice.
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4.7.5 Power Added Efficiency
From the PAE point of view, cascode no. 4 is the best choice. But, cascode no. 4 has very bad linearity and
from linearity point of view is useless. This issue also shows the trade-off between linearity and efficiency.
4.7.6 Transformation Ratio (Zsource / Zin) and (ZL / Zout))
In Table 4.2, the metrics (Z source / Zin) and (ZL / Zout), where Zsource = ZL = 50 Ohm, represent the input
impedance transformation ratio and output impedance transformation ratio, respectively. As it has been
mentioned in chapter 2, the efficiency of the matching network is reversely proportional to the
transformation ratio. From the implementation complexity point of view, decreasing the transformation ratio
relaxes the requirement on the quality factor of the used inductor. Thus, cascode no. 4 has the less
implementation complexity.
53
Chapter 5
Conclusion and Future Work
________________________________________________________________________________________________________________________________________________________________
Chapter 5
5.1
Conclusion and Future Work
Summary and conclusion
The PA can be considered as a key building block in RF transmitter. Now days, full integration of a complete
radio System-on-Chip (SoC) is desired to lower cost and area consumption. The rapid technology evolution
of CMOS has largely improved the radio frequency performance of MOS devices which made CMOS
technology the prime choice for digital circuits. But with each new generation, it becomes harder to meet the
requirements on output power, linearity, and efficiency at lower supply voltages that follow from technology
scaling in traditional RF PA architectures, such as the class-AB PA.
The low drain breakdown voltage and other reliability issues of nanometer CMOS transistors reduce the
maximum output power and efficiency for RF PAs. When the SoC design includes the PA, it is therefore
challenging using a baseline CMOS logic process [14]-[17].
To overcome the reliability issues while delivering high output power in PA design, one can use circuit
solution that can handle higher voltage such as the cascode configuration, where standard thick-oxide
transistors are stacked in a cascode configuration to eliminate the effects of oxide breakdown voltage and to
make use of a larger supply voltage. One other solution is to use high-voltage MOS, H-V MOS devices, such
as EDMOS devices, which have high break down voltage.
This thesis has addressed the potential of implementing class-AB PAs in nanometer CMOS technologies at
2.4 GHz frequency. In total, five amplifiers have been implemented, four cascode class-AB PAs and one
EDMOS class-AB PA. A comparison between the five PA has been done. The examined parameters were
output signal performances, design complexity, and area consumption.
While the EDMOS class-AB PA has the benefit of low area consumption compared to conventional cascode
class-AB PAs, it is more challenging to reach the required output power (watt level) for WLAN using
EDMOS PA. Still, if the area consumption is the most important parameter for the designer, then the
EDMOS PA is the recommended type. Cascode no.3 has less design complexity than other PA types. If the
output power is the most important parameter, then the cascode no. 3, (L= 500,260 nm), is the best choice,
which is also the best choice if the power added efficiency is the most important parameter. If the linearity is
the most important parameter, then cascode no. 2, (L= 500,350 nm), is the best choice. Note that cascode no.
54
Chapter 5
Conclusion and Future Work
________________________________________________________________________________________________________________________________________________________________
4, (L= 500,60 nm), has very poor linearity which makes it a useless choice. Cascode no. 1, (L= 500,500 nm),
has low output power, thus it is not a recommended choice.
5.2
Future Work
As it has been mentioned previously, the output power is directly proportional to the square of the supply
voltage. The used supply voltage in this work is 3.3 V. In future, higher supply voltage can be used to have
higher output power, but a reliable operation has to be maintain. Different biasing techniques [38] for the
different cascode architectures can be implemented and tested. Comparison of cascode structures in 65 nm,
45 nm and 28 nm processes is also suggested as future work.
55
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58
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