74ABT125 1. General description Quad buffer; 3-state

74ABT125 1. General description Quad buffer; 3-state
74ABT125
Quad buffer; 3-state
Rev. 7 — 25 November 2015
Product data sheet
1. General description
The 74ABT125 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT125 device is a quad buffer that is ideal for driving bus lines. The device
features four output enable inputs (1OE, 2OE, 3OE, 4OE), each controlling one of the
3-state outputs.
2. Features and benefits








Quad bus interface
3-state buffers
Live insertion and extraction permitted
Output capability: HIGH 32 mA; LOW +64 mA
Power-up 3-state
Inputs are disabled during 3-state mode
Latch-up protection exceeds 500 mA per JESD78 class II level A
ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V
 Multiple package options
 Specified from 40 C to +85 C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74ABT125D
40 C to +85 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74ABT125DB
40 C to +85 C
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74ABT125PW
40 C to +85 C
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74ABT125BQ
40 C to +85 C
DHVQFN14
plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5  3  0.85 mm
SOT762-1
74ABT125
NXP Semiconductors
Quad buffer; 3-state
4. Functional diagram
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Fig 1.
PQD
Logic symbol
Fig 2.
PQD
IEC logic symbol
Fig 3.
Logic diagram (one buffer)
5. Pinning information
5.1 Pinning
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7UDQVSDUHQWWRSYLHZ
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(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration SO14 and (T)SSOP14
74ABT125
Product data sheet
Fig 5.
Pin configuration DHVQFN14
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 15
74ABT125
NXP Semiconductors
Quad buffer; 3-state
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1OE to 4OE
1, 4, 10, 13
output enable input (active LOW)
1A to 4A
2, 5, 9, 12
data input
1Y to 4Y
3, 6, 8, 11
data output
GND
7
ground (0 V)
VCC
14
supply voltage
6. Functional description
Table 3.
Function selection[1]
Inputs
Output
nOE
nA
L
L
L
L
H
H
H
X
Z
[1]
nY
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
0.5
+7.0
V
VI
input voltage
1.2
+7.0
V
VO
output voltage
output in OFF-state or HIGH-state
0.5
+5.5
V
IIK
input clamping current
VI < 0 V
18
-
IOK
output clamping current
VO < 0 V
50
-
mA
IO
output current
output in LOW-state
-
128
mA
Tj
junction temperature
-
150
C
Tstg
storage temperature
65
+150
C
-
500
mW
total power dissipation
Ptot
[2]
Tamb = 40 C to +85 C
[3]
mA
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[3]
SO14 packages: above 70 C Ptot derate linearly with 8 mW/K
SSOP14 and TSSOP14 packages: above 60 C Ptot derate linearly with 5.5 mW/K
DHVQFN14 packages: above 60 C Ptot derate linearly with 4.5 mW/K
74ABT125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 15
74ABT125
NXP Semiconductors
Quad buffer; 3-state
8. Recommended operating conditions
Table 5.
Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
VCC
supply voltage
VI
input voltage
VIH
HIGH-level input voltage
VIL
LOW-level Input voltage
IOH
HIGH-level output current
Min
Max
Unit
4.5
5.5
V
0
VCC
V
2.0
-
V
-
0.8
V
32
-
mA
IOL
LOW-level output current
-
64
mA
t/V
input transition rise and fall rate
-
10
ns/V
Tamb
ambient temperature
40
+85
C
in free air
9. Static characteristics
Table 6.
Static characteristics
Symbol
Parameter
25 C
Conditions
40 C to +85 C Unit
Min
Typ
Max
Min
Max
-
0.9
1.2
-
1.2
V
VCC = 4.5 V; IOH = 3 mA
2.5
2.9
-
2.5
-
V
VCC = 5.0 V; IOH = 3 mA
3.0
3.4
-
3.0
-
V
VCC = 4.5 V; IOH = 32 mA
VIK
input clamping voltage VCC = 4.5 V; IIK = 18 mA
VOH
HIGH-level output
voltage
VI = VIL or VIH
2.0
2.4
-
2.0
-
V
VOL
LOW-level output
voltage
VCC = 4.5 V; IOL = 64 mA;
VI = VIL or VIH
-
0.35
0.55
-
0.55
V
II
input leakage current
VCC = 5.5 V; VI = GND or 5.5 V
-
0.01
1.0
-
1.0
A
IOFF
power-off leakage
current
VCC = 0.0 V; VI or VO  4.5 V
-
5.0
100
-
100
A
IO(pu/pd)
power-up/power-down VCC = 2.1 V; VO = 0.5 V;
output current
VI = GND or VCC; OE = don’t care
-
5.0
50
-
50
A
IOZ
OFF-state output
current
VO = 2.7 V
-
1.0
50
-
50
A
VO = 0.5 V
-
1.0
50
-
50
A
-
5.0
50
-
50
A
50
100
180
50
180
mA
-
65
250
-
250
A
[1]
VCC = 5.5 V; VI = VIL or VIH
ICEX
output high leakage
current
HIGH-state; VO = 5.5 V;
VCC = 5.5 V; VI = GND or VCC
IO
output current
VCC = 5.5 V; VO = 2.5 V
ICC
supply current
VCC = 5.5 V; VI = GND or VCC
[2]
outputs HIGH-state
74ABT125
Product data sheet
outputs LOW-state
-
12
15
-
30
mA
outputs disabled
-
65
250
-
50
A
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74ABT125
NXP Semiconductors
Quad buffer; 3-state
Table 6.
Static characteristics …continued
Symbol
Parameter
ICC
additional supply
current
25 C
Conditions
40 C to +85 C Unit
Min
Typ
Max
Min
Max
outputs enabled
-
0.5
1.5
-
1.5
mA
outputs disabled
-
50
250
-
250
mA
one enable input at 3.4 V and other
inputs at VCC or GND; outputs
disabled
-
0.5
1.5
-
1.5
mA
per control pin; VCC = 5.5 V;
one control input at 3.4 V, other
inputs at VCC or GND
[3]
CI
input capacitance
VI = 0 V or VCC
-
4
-
-
-
pF
CO
output capacitance
outputs disabled; VO = 0 V or VCC
-
7
-
-
-
pF
[1]
This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V  10 %,
a transition time of up to 100 s is permitted.
[2]
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[3]
This is the increase in supply current for each input at 3.4 V.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V. Test circuit is shown in Figure 8.
Symbol Parameter
25 C; VCC = 5.0 V
Conditions
40 C to +85 C; Unit
VCC = 5.0 V  0.5 V
Min
Typ
Max
Min
Max
tPLH
LOW to HIGH
propagation delay
nA to nY, see Figure 6
1.0
2.8
4.1
1.0
4.6
ns
tPHL
HIGH to LOW
propagation delay
nA to nY; see Figure 6
1.0
3.1
4.6
1.0
4.9
ns
tPZH
OFF-state to HIGH
propagation delay
nOE to nY; see Figure 7
1.0
3.2
5.0
1.0
5.9
ns
tPZL
OFF-state to LOW
propagation delay
nOE to nY; see Figure 7
1.0
4.2
6.2
1.0
6.8
ns
tPHZ
HIGH to OFF-state
propagation delay
nOE to nY; see Figure 7
1.0
4.1
5.4
1.0
6.2
ns
tPLZ
LOW to OFF-state
propagation delay
nOE to nY; see Figure 7
1.5
2.8
5.0
1.5
5.5
ns
74ABT125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 15
74ABT125
NXP Semiconductors
Quad buffer; 3-state
11. Waveforms
9,
90
Q$LQSXW
*1'
W3+/
W3/+
92+
90
Q<RXWSXW
92/
PQD
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6.
Propagation delay input (nA) to output (nY)
9,
Q2(LQSXW
90
90
*1'
W3=/
W3/=
9
RXWSXW
/2:WR2))
2))WR/2:
90
92/9
92/
W3+=
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W3=+
92+ 9
RXWSXW
+,*+WR2))
2))WR+,*+
90
*1'
RXWSXWV
HQDEOHG
RXWSXWV
GLVDEOHG
RXWSXWV
HQDEOHG
DDO
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7.
Enable and disable times
74ABT125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 15
74ABT125
NXP Semiconductors
Quad buffer; 3-state
9,
W:
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SXOVH
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9
9(;7
WI
WU
WU
WI
9,
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SXOVH
9
90
9&&
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9,
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90
90
57
W:
5/
92
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DDL
a. Input pulse definition
5/
b. Test circuit
Test data is given in Table 8.
Test circuit definitions:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 8.
Table 8.
Test circuit for measuring switching times
Test data
Input
Load
VEXT
VI
fI
tW
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
3.0 V
1 MHz
500 ns
 2.5 ns
50 pF
500 
open
open
7.0 V
74ABT125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
7 of 15
74ABT125
NXP Semiconductors
Quad buffer; 3-state
12. Package outline
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74ABT125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
8 of 15
74ABT125
NXP Semiconductors
Quad buffer; 3-state
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74ABT125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
9 of 15
74ABT125
NXP Semiconductors
Quad buffer; 3-state
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74ABT125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
10 of 15
74ABT125
NXP Semiconductors
Quad buffer; 3-state
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74ABT125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 15
74ABT125
NXP Semiconductors
Quad buffer; 3-state
13. Abbreviations
Table 9.
Abbreviations
Acronym
Description
BiCMOS
BipolarCMOS
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
14. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74ABT125 v.7
20151125
Product data sheet
-
74ABT125 v.6
Modifications:
74ABT125 v.6
Modifications:
•
Type number 74ABT125N (SOT27-1) removed.
20111103
•
Product data sheet
-
74ABT125 v.5
Legal pages updated
74ABT125 v.5
20101124
Product data sheet
-
74ABT125 v.4
74ABT125 v.4
20100427
Product data sheet
-
74ABT125 v.3
74ABT125 v.3
20080429
Product data sheet
-
74ABT125 v.2
74ABT125 v.2
19980116
Product specification
-
74ABT125 v.1
74ABT125 v.1
19960305
-
-
-
74ABT125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
12 of 15
74ABT125
NXP Semiconductors
Quad buffer; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74ABT125
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
13 of 15
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Quad buffer; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74ABT125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
14 of 15
74ABT125
NXP Semiconductors
Quad buffer; 3-state
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 November 2015
Document identifier: 74ABT125
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