datasheet for LTC3856 by Linear Technology

datasheet for LTC3856 by Linear Technology
LTC3856
2-Phase Synchronous
Step-Down DC/DC
Controller with Diffamp
DESCRIPTION
FEATURES
PolyPhase® Controller Reduces Input and Output
Capacitance and Power Supply Induced Noise
Wide VIN Range: 4.5V to 38V Operation
±0.75%, 0.6V Reference Voltage Accuracy
High Eficiency: Up to 95%
Programmable Burst Mode® Operation or
Stage Shedding™ for Highest Light Load Eficiency
Active Voltage Positioning (AVP)
RSENSE or DCR Current Sensing
Programmable DCR Temperature Compensation
Phase-Lockable Fixed Frequency: 250kHz to 770kHz
True Remote Sense Differential Ampliier
Dual N-Channel MOSFET Synchronous Drive
VOUT Range: 0.6V to 5V without Differential Ampliier
VOUT Range: 0.6V to 3.3V with Differential Ampliier
Adjustable Soft-Start or VOUT Tracking
Stackable for Up to 12-Phase Operation
32-Pin (5mm × 5mm) QFN and 38-Pin TSSOP Packages
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The LTC®3856 is a single output, dual channel PolyPhase
synchronous step-down DC/DC controller that drives all
N-channel power MOSFET stages. This device includes a
high speed differential ampliier for remote output voltage sense. Power loss and supply noise are minimized by
operating the two controller output stages out-of-phase
and up to 12-phase operation can be achieved.
The LTC3856 monitors the output current by sensing
the voltage drop across the output inductor (DCR) or by
using a sense resistor. DCR temperature compensation
maintains an accurate current sense threshold over a
broad temperature range. A constant-frequency, current
mode architecture allows a phase-lockable frequency of
up to 770kHz.
A wide 4.5V to 38V input supply range encompasses
most intermediate bus voltages and battery chemistries.
Burst Mode operation, continuous or Stage Shedding
modes are supported. A TK/SS pin shared by both channels ramps the output voltage during start-up.
APPLICATIONS
Telecom and Datacom Systems
Industrial and Medical Instruments
DC Power Distribution Systems
Computer Systems
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L, LT, LTC, LTM, Linear Technology, the Linear logo, PolyPhase, Burst Mode and OPTI-LOOP
are registered trademarks and Stage Shedding is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6498466,
6580258, 6611131, 6674274.
TYPICAL APPLICATION
Eficiency and Power Loss
vs Output Current
High Eficiency 1.5V/50A Step-Down Converter
10µF
฀4
30.1k
TG1
VIN
VFB
20k
S
0.33µH
BOOST1
ILIM
LTC3856
PGOOD
CLKOUT
PHASMD
S
BG1
PLLIN
S
TG2
ITEMP
BOOST2
SW2
S
EXTVCC
INTVCC
DIFFN
SENSE2+
DIFFP
SENSE2–
ITH TK/SS GND AVP ISET
2200pF
1.5k 0.1µF
0.33µH
VOUT
1.5V
50A
0.1µF
S
S
BG2
122k
S
SENSE1+
SENSE1–
MODE
FREQ
80
0.1µF
SW1
100
VIN = 12V
VOUT = 1.5V
Burst Mode
OPERATION
70
60
50
1
40
30
0
20
S
S
4.7µF
S
100µF
฀8
10
POWER LOSS (W)
RUN
90
EFFICIENCY (%)
DIFFOUT
S
100
VIN
4.5V TO
20V
10
0
0.1
1
10
LOAD CURRENT (A)
–1
100
3856 TA01b
S
3856 TA01a
3856f
1
LTC3856
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage (VIN) ......................... 40V to –0.3V
Topside Driver Voltages (BOOSTn) ............ 46V to –0.3V
Switch Voltage (SWn) ................................... 40V to –5V
INTVCC, RUN, PGOOD, EXTVCC,
(BOOSTn – SWn) ......................................... 6V to –0.3V
SENSEn Voltages ...................................... 5.5V to –0.3V
MODE, PLLIN, ILIM, TK/SS, AVP,
FREQ, ISET Voltages ............................. INTVCC to –0.3V
DIFFP, DIFFN, DIFFOUT, PHASMD,
ITEMP Voltages..................................... INTVCC to –0.3V
ITH, VFB Voltages ................................... INTVCC to –0.3V
INTVCC Peak Output Current ................................100mA
Operating Junction Temperature Range
(Notes 2, 3) ............................................ –40°C to 125°C
Storage Temperature Range................... –65°C to 125°C
Relow Peak Body Temperature (UH Package) ...... 260°C
Lead Temperature (Soldering, 10 sec.)
FE Package............................................................ 300°C
PIN CONFIGURATION
TOP VIEW
35 TG1
TG1
4
SW1
SENSE1–
TOP VIEW
CLKOUT
36 SW1
PLLIN
3
FREQ
37 CLKOUT
SENSE1+
RUN
38 PLLIN
2
SENSE1+
1
RUN
SENSE1–
FREQ
NC
5
34 NC
TK/SS
6
33 BOOST1
VFB
7
32 PGND1
ITH
8
31 BG1
VFB 2
23 BG1
30 VIN
ITH 3
22 VIN
SENSE2+ 13
26 PGND2
SENSE2– 14
25 NC
DIFFP 15
24 BOOST2
DIFFN 16
23 TG2
DIFFOUT 17
22 SW2
ISET 18
21 PGOOD
ILIM 19
20 MODE
FE PACKAGE
38-LEAD PLASTIC TSSOP
19 BG2
SENSE2+ 7
18 BOOST2
SENSE2– 8
17 TG2
9 10 11 12 13 14 15 16
SW2
27 BG2
PGOOD
PHASMD 12
20 EXTVCC
PHASMD 6
MODE
28 EXTVCC
21 INTVCC
33
ITEMP 5
ILIM
29 INTVCC
ISET
ITEMP 11
39
DIFFOUT
AVP 10
AVP 4
DIFFN
9
24 BOOST1
DIFFP
SGND
32 31 30 29 28 27 26 25
TK/SS 1
UH PACKAGE
32-LEAD (5mm 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 33) IS SGND/PGND, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 25°C/W
EXPOSED PAD (PIN 39) IS SGND/PGND, MUST BE SOLDERED TO PCB
3856f
2
LTC3856
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3856EFE#PBF
LTC3856EFE#TRPBF
LTC3856FE
38-Lead Plastic TSSOP
–40°C to 125°C
LTC3856IFE#PBF
LTC3856IFE#TRPBF
LTC3856FE
38-Lead Plastic TSSOP
–40°C to 125°C
LTC3856EUH#PBF
LTC3856EUH#TRPBF
3856
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
LTC3856IUH#PBF
LTC3856IUH#TRPBF
3856
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts speciied with wider operating temperature ranges. *The temperature grade is identiied by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based inish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel speciications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the speciications which apply over the full operating
junction temperature range, otherwise speciications are at TA = 25°C (Note 2). VIN = 15V, VRUN = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
VIN
Input Voltage
4.5
38
V
VOUT
Output Voltage
0.6
5.0
V
VFB
Regulated Feedback Voltage
ITH Voltage = 1.2V, E-Grade (Note 4)
ITH Voltage = 1.2V, I-Grade (Note 4)
IFB
Feedback Current
(Note 4)
VREFLNREG
Reference Voltage Line Regulation
VIN = 4.5V to 38V (Note 4)
VLOADREG
Output Voltage Load Regulation
(Note 4)
Measured in Servo Loop, ∆ITH Voltage = 1.2V to 0.7V
Measured in Servo Loop, ∆ITH Voltage = 1.2V to 1.6V
l
l
0.5955
0.593
l
l
0.600 0.6045
0.600 0.607
–15
–50
nA
0.002
0.02
%/V
0.01
–0.01
0.1
–0.1
%
%
gm
Transconductance Ampliier gm
ITH = 1.2V, Sink/Source 5µA (Note 4)
2.0
IQ
Input DC Supply Current
Normal Mode
Shutdown
(Note 5)
VIN = 15V
VRUN = 0V
4.0
40
Maximum Duty Factor
In Dropout; fOSC = 500kHz
VINTVCC Ramping Down
DFMAX
93
V
V
mmho
70
94
mA
µA
%
UVLO
Undervoltage Lockout
UVLO Hyst
UVLO Hysteresis
VOVL
Feedback Overvoltage Lockout
Measured at VFB
l
ISENSE+
SENSE+ Pins Bias Current
Each Channel, VSENSE1,2 = 3.3V
l
ITEMP
DCR Tempco Compensation Current
VITEMP = 0.3V
l
9
ITK/SS
Soft-Start Charge Current
VTK/SS = 0V
l
1.0
VRUN
RUN Pin On Threshold
VRUN Rising
l
1.1
VRUNHYS
RUN Pin On Hysteresis
VSENSE(MAX)
Maximum Current Sense Threshold
(E-Grade)
VFB = 0.5V, VSENSE1,2 = 3.3V
ILIM = 0V
ILIM = Float
ILIM = INTVCC
l
l
l
25
45
68
30
50
75
35
55
82
mV
mV
mV
Maximum Current Sense Threshold
(I-Grade)
VFB = 0.5V, VSENSE1,2 = 3.3V
ILIM = 0V
ILIM = Float
ILIM = INTVCC
l
l
l
23
43
66
30
50
75
37
57
84
mV
mV
mV
VSENSE(MAX)
l
3.0
3.2
3.4
0.6
0.64
V
V
0.66
0.68
V
±1
±2
µA
10
11
µA
1.25
1.5
µA
1.22
1.35
V
80
mV
3856f
3
LTC3856
ELECTRICAL CHARACTERISTICS
The l denotes the speciications which apply over the full operating
junction temperature range, otherwise speciications are at TA = 25°C (Note 2). VIN = 15V, VRUN = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
TG1,2 tr
TG1,2 tf
TG Transition Time
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
MIN
TYP
MAX
UNITS
25
25
ns
ns
BG1,2 tr
BG1,2 tf
BG Transition Time
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
25
ns
ns
TG/BG t1D
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver
30
ns
BG/TG t2D
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver
30
ns
tON(MIN)
Minimum On-Time
(Note 7)
90
ns
INTVCC Linear Regulator
VINTVCC
Internal VCC Voltage
6V < VIN ≤ 38V
VLDO INT
INTVCC Load Regulation
ICC = 0mA to 20mA
VEXTVCC
EXTVCC Switchover Voltage
EXTVCC Ramping Positive
VLDO EXT
EXTVCC Voltage Drop
ICC = 20mA, VEXTVCC = 5V
VLDOHYS
EXTVCC Hysteresis
l
4.8
5.0
5.2
V
0.5
2.0
%
4.5
4.7
50
V
100
200
mV
mV
Oscillator and Phase-Locked Loop
fNOM
Nominal Frequency
VFREQ = 1.2V
450
500
550
kHz
fLOW
Lowest Frequency
VFREQ = 0V
210
250
290
kHz
fHIGH
Highest Frequency
VFREQ ≥ 2.4V
700
770
850
kHz
RMODE
MODE Input Resistance
IFREQ
Frequency Setting Output Current
CLKOUT
Phase (Relative to Controller 1)
CLKHIGH
Clock High Output Voltage
CLKLOW
Clock Low Output Voltage
250
9
PHASMD = GND; Non Stage Shedding Mode
PHASMD = FLOAT; Non Stage Shedding Mode
PHASMD = INTVCC; Non Stage Shedding Mode
Stage Shedding Mode
10
kΩ
11
60
90
120
180
4
µA
Deg
Deg
Deg
Deg
5
V
0
0.2
V
0.1
0.2
V
±2
µA
PGOOD Output
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
VPG
PGOOD Trip Level, Either Controller
VFB with Respect to Set Output Voltage
VFB Ramping Negative
VFB Ramping Positive
–10
10
%
%
3856f
4
LTC3856
ELECTRICAL CHARACTERISTICS
The l denotes the speciications which apply over the full operating
junction temperature range, otherwise speciications are at TA = 25°C (Note 2). VIN = 15V, VRUN = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.998
0.997
1
1
1.002
1.003
V/V
V/V
Differential Ampliier
ADA
Gain
E-Grade
I-Grade
RIN
Input Resistance
Measured at DIFFP Input
l
l
VOS
Input Offset Voltage
VDIFFP = VDIFFOUT = 1.5V, IDIFFOUT = 100µA
PSRR
Power Supply Rejection Ratio
4.5V < VIN < 38V
ICL
Maximum Output Current
VOUT(MAX)
Maximum Output Voltage
80
2
2
IDIFFOUT = 300µA
kΩ
mV
100
dB
3
mA
VINTVCC VINTVCC
–1.4
–1.1
V
On-Chip Driver
TG RUP
TG Pull-Up RDS(ON)
TG High
2.6
Ω
TG RDOWN
TG Pull-Down RDS(ON)
TG Low
1.5
Ω
BG RUP
BG Pull-Up RDS(ON)
BG High
2.4
Ω
BG RDOWN
BG Pull-Down RDS(ON)
BG Low
1.1
Ω
GBW
Gain-Bandwidth Product
(Note 8)
3
MHz
SR
Slew Rate
(Note 8)
2
V/µs
Stage Shedding Mode
IISET
Programmable Stage Shedding
Mode Current
6.5
7.5
8.5
µA
AVP (Active Voltage Positioning)
VAVP
ISINK
ISOURCE
Maximum VOUT with AVP
2.5
V
250
µA
Sink Current of AVP Pin
SENSE+ = 1.2V
Source Current of AVP Pin
SENSE+ = 1.2V
2
mA
SENSE+ = 1.2V
120
mV
VAVP-VO(MAX) Maximum Voltage Drop VAVP to VO
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3856 is tested under pulse load conditions such that
TJ ≈ TA. The LTC3856E is guaranteed to meet performance speciications
from 0°C to 85°C operating junction temperature. Speciications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3856I is guaranteed to meet performance speciications over the
full –40°C to 125°C operating junction temperature range.
Note 3: TJ is calculated from the ambient temperature, TA, and power
dissipation, PD, according to the following formula:
LTC3856UH: TJ = TA + (PD • 34°C/W)
LTC3856FE: TJ = TA + (PD • 25°C/W)
Note 4: The LTC3856 is tested in a feedback loop that servos VITH to a
speciied voltage and measures the resultant VFB.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See the Applications Information
section.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition corresponds to the on inductor
peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time
Considerations in the Applications Information section).
Note 8: Guaranteed by design.
3856f
5
LTC3856
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step:
Burst Mode Operation
Load Step:
Forced Continuous Mode
VBAT = 3.6V
ILOAD ICPO = 200µA
40A/DIV CCPO = 2.2ΩF
VBAT = 3.6V
ILOAD ICPO = 200µA
40A/DIV CCPO = 2.2ΩF
IL1
20A/DIV
IL1
20A/DIV
IL2
20A/DIV
IL2
20A/DIV
VOUT
200mV/DIV
VOUT
200mV/DIV
3856 G01
100µs/DIV
VIN = 12V
VOUT = 1.5V
ILOAD = 1A TO 40A
VIN = 12V
VOUT = 1.5V
ILOAD = 1A TO 40A
Eficiency vs Output Current
and Mode
Inductor Current at Light Load
100
3856 G02
VBAT = 3.6V
FORCED ICPO = 200µA
CONTINUOUS CCPO = 2.2ΩF
MODE, 5A/DIV
Burst Mode
OPERATION
90
80
EFFICIENCY (%)
100µs/DIV
70
60
Stage
Shedding
MODE
50
40
FORCED
CONTINUOUS
MODE
Burst Mode
OPERATION, 5A/DIV
DCM OPERATION,
5A/DIV
30
20
1µs/DIV
VIN = 12V
VOUT = 1.5V
10
0
0.1
1
10
LOAD CURRENT (A)
VIN = 12V
VOUT = 1.5V
ILOAD = 400mA
100
3856 G03
Stage Shedding Transition,
1-Phase to 2-Phase
VOUT
100mV/DIV
Stage Shedding Transition,
2-Phase to 1-Phase
UNDERSHOOT
35mV
VOUT
100mV/DIV
VSW1
10V/DIV
VSW1
10V/DIV
VSW2
10V/DIV
VSW2
10V/DIV
VIN = 12V
VOUT = 1.5V
10µs/DIV
3856 G04
OVERSHOOT
36mV
3856 G05
VIN = 12V
VOUT = 1.5V
10µs/DIV
3856 G06
3856f
6
LTC3856
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step without AVP
Quiescent Current vs Input
Voltage without EXTVCC
Load Step with AVP
4.5
4.3
VOUT
50mV/DIV
54mV
50A
IL
20A/DIV
50A
IL
20A/DIV
25A
3856 G07
100µs/DIV
VIN = 12V
VOUT = 1.5V
25A
VIN = 12V
VOUT = 1.5V
QUIESCENT CURRENT (mA)
108mV
VOUT
50mV/DIV
3856 G07a
100µs/DIV
4.1
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
5
Current Sense Threshold
vs ITH Voltage
INTVCC Line Regulation
CURRENT SENSE THRESHOLD (mV)
60
VSENSE (mV)
INTVCC VOLTAGE (V)
4.75
4.50
4.25
4.00
ILIM = FLOAT
40
20
ILIM = GND
0
3.75
3.50
–20
3.25
–40
0
5
10
15
20
25
INPUT VOLTAGE (V)
30
35
40
3856 G09
90
ILIM = INTVCC
70
60
ILIM = FLOAT
50
40
ILIM = GND
30
20
10
0
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3856 G12
40
3856 G08
1.5
60
ILIM = FLOAT
50
40
ILIM = GND
30
20
10
0
2
ILIM = INTVCC
70
0
3856 G10
Maximum Current Sense Voltage
vs Feedback Voltage
(Current Foldback)
MAXIMUM CURRENT SENSE VOLTAGE (mV)
MAXIMUM CURRENT SENSE VOLTAGE (mV)
100
1
VITH (V)
Maximum Current Sense Voltage
vs Duty Cycle
80
0.5
0
2
3
4
1
VSENSE COMMON MODE VOLTAGE (V)
5
3856 G11
TK/SS Pull-Up Current
vs Temperature
100
1.5
90
80
1.4
ILIM = INTVCC
TK/SS CURRENT (µA)
3.00
35
80
ILIM = INTVCC
5.00
25
20
30
15
INPUT VOLTAGE (V)
Maximum Current Sense Threshold
vs Common Mode Voltage
80
5.25
10
70
60
ILIM = FLOAT
50
40
ILIM = GND
30
20
1.3
1.2
1.1
10
0
0
0.1
0.4
0.3
0.2
0.5
FEEDBACK VOLTAGE (V)
0.6
3856 G13
1.0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
3856 G14
3856f
7
LTC3856
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown (RUN) Threshold
vs Temperature
1.25
1.15
OFF
1.10
–50 –25
0
25
50
75
TEMPERATURE (°C)
700
0.603
0.602
0.601
0.600
VFREQ = 1.2V
500
400
VFREQ = GND
300
100
–25
0
25
50
75
100
TEMPERATURE (°C)
3856 G15
Undervoltage Lockout Threshold
(INTVCC) vs Temperature
0
–50
125
–25
0
25
50
75
100
TEMPERATURE (°C)
3856 G16
Oscillator Frequency
vs Input Voltage
125
3856 G17
Shutdown Current
vs Input Voltage
60
520
4.0
ON
50
3.8
FREQUENCY (kHz)
510
3.6
3.4
500
40
30
20
490
OFF
10
3.2
3.0
–50
600
200
0.599
0.598
–50
100 125 150
VFREQ = INTVCC
800
0.604
INPUT CURRENT (µA)
RUN PIN VOLTAGE (V)
1.20
900
FREQUENCY (kHz)
REGULATED FEEDBACK VOLTAGE (mV)
0.605
ON
UNDERVOLTAGE LOCKOUT THRESHOLD (INTVCC) (V)
Oscillator Frequency
vs Temperature
Regulated Feedback Voltage
vs Temperature
480
–25
0
25
50
75
100
TEMPERATURE (°C)
125
0
5
10
25
15
20
30
INPUT VOLTAGE (V)
0
5
10
15
3856 G19
70
6
60
5
50
40
30
20
20
25
30
35
40
3856 G20
Quiescent Current vs Temperature
without EXTVCC
QUIESCENT CURRENT (mA)
SHUTDOWN CURRENT (µA)
40
INPUT VOLTAGE (V)
3856 G18
Shutdown Current vs Temperature
4
3
2
1
10
0
–50
35
–25
0
25
50
75
TEMPERATURE (°C)
100
125
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
3856 G21
100
125
3856 G22
3856f
8
LTC3856
PIN FUNCTIONS
(TSSOP/QFN)
FREQ (Pin 1/Pin 29): Frequency Setting Pin. A resistor
to ground sets the operating frequency of the controller.
This pin can also be driven with a DC voltage to vary the
frequency of the internal oscillator.
RUN (Pin 2/Pin 30): Run Control Input. A voltage above
1.22V on this pin turns on the IC. There is a 1µA pull-up
current for this pin. Once the RUN pin rises above 1.22V,
an additional 4.5µA pull-up current is added to the pin.
SENSE1+, SENSE2+ (Pins 3, 13/Pins 31, 7): Current
Sense Comparator Inputs. The (+) inputs to the current
comparators are normally connected to DCR sensing
networks or current sensing resistors.
temperature coeficient) resistor placed near the heat
source on the PCB board (e.g., inductors) changes the
controller’s current limit with temperature.
PHASMD (Pin 12/Pin 6): Connect this pin to SGND, INTVCC,
or loat this pin to select the phase of CLKOUT to be 60°,
120° and 90°, respectively.
DIFFP (Pin 15/Pin 9): Positive Input of Remote Sensing
Differential Ampliier. Connect this directly to the remote
load voltage.
DIFFN (Pin 16/Pin 10): Negative Input of Remote Sensing Differential Ampliier. Connect this pin to the negative
terminal of output load capacitors.
SENSE1–, SENSE2– (Pins 4, 14/Pins 32, 8): Current
Sense Comparator Inputs. The (–) inputs to the current
comparators are connected to the outputs.
DIFFOUT (Pin 17/Pin 11): Output of Remote Sensing
Differential Ampliier. Connect this pin to VFB through a
resistive divider.
NC (Pins 5, 25, 34) TSSOP Package: No Connections.
ISET (Pin 18/Pin 12): Stage Shedding Mode Comparator
and Burst Mode Comparator Programming Pin. A resistor
to ground programs the threshold of the Stage Shedding
mode comparator or Burst Mode comparator threshold
and current limit.
TK/SS (Pin 6/Pin 1): Output Voltage Tracking and SoftStart Input. When one particular IC is conigured to be the
master of two ICs, a capacitor to ground at this pin sets
the ramp rate for the master IC’s output voltage. When the
IC is conigured to be the slave of two ICs, the VFB voltage
of the master IC is reproduced by a resistor divider and
applied to this pin. An internal soft-start current of 1.25µA
is charging this pin.
VFB (Pin 7/Pin 2): Error Ampliier Feedback Input. This
pin receives the remotely sensed feedback voltage from
an external resistive divider.
ITH (Pin 8/Pin 3): Current Control Threshold and Error
Ampliier Compensation Point. Each associated channels’
current comparator tripping threshold increases with ITH
control voltage.
SGND (Pin 9/Pin 33): Signal Ground and Power Ground. All
small-signal components and compensation components
should connect to this ground, which in turn connects to
PGND at one point.
AVP (Pin 10/Pin 4): Active Voltage Positioning Load Slope
Programming Pin. A resistor between this pin and the
DIFFP pin sets the load slope.
ITEMP (Pin 11/Pin 5): Input to the Temperature Sensing
Circuit. Connect this pin to an external NTC (negative
ILIM (Pin 19/Pin 13): Current Comparator Sense Voltage Range Input. This pin is to be programmed to
SGND, FLOAT or INTVCC to set the maximum current
sense threshold to one of three different levels for both
comparators.
MODE (Pin 20/Pin 14): Forced Continuous Mode,
Burst Mode Operation or Stage Shedding Mode Selection Pin. Connect this pin to SGND to force IC in
continuous mode of operation. Connect to INTVCC to
enable Stage Shedding mode operation. Leaving the pin
loating enables Burst Mode operation.
PGOOD (Pin 21/Pin 15): Power Good Indicator Output.
Open-drain logic out that is pulled to ground when the
output exceeds the ±10% regulation window, after the
internal 20µs power-bad mask timer expires.
EXTVCC (Pin 28/Pin 20): External Power Input to an
Internal Switch Connected to INTVCC. This switch closes
and supplies the IC power, bypassing the internal low
dropout regulator, whenever EXTVCC is higher than 4.7V.
Do not exceed 6V on this pin and ensure VIN > VEXTVCC
at all times.
3856f
9
LTC3856
PIN FUNCTIONS
(TSSOP/QFN)
INTVCC (Pin 29/Pin 21): Internal 5V Regulator Output. The
control circuits are powered from this voltage. Decouple
this pin to PGND with a minimum of 4.7µF low ESR tantalum or ceramic capacitor.
the sources of the bottom N-channel MOSFETs, the (–)
terminal of CVCC and the (–) terminal of CIN. All small-signal
components and compensation components should also
connect to this ground.
VIN (Pin 30/Pin 22): Main Input Supply. Decouple this pin
to PGND with a capacitor (0.1µF to 1µF).
TG1, TG2 (Pins 35, 23/Pins 25, 17): Top Gate Driver
Outputs. These are the outputs of loating drivers with
a voltage swing equal to INTVCC superimposed on the
switch nodes voltages.
BG1, BG2 (Pins 31, 27/Pins 23, 19): Bottom Gate Driver
Outputs. These pins drive the gates of the bottom N-channel MOSFETs between INTVCC and PGND.
PGND1, PGND2 (Pins 32, 26) TSSOP Package: Power
Ground Pin. Connect this pin closely to the sources of the
bottom N-channel MOSFETs, the (–) terminal of CVCC and
the (–) terminal of CIN.
BOOST1, BOOST2 (Pins 33, 24/Pins 24, 18): Boosted
Floating Driver Supplies. The (+) terminal of the bootstrap capacitors connect to these pins. These pins swing
from a diode voltage drop below INTVCC up to VIN +
INTVCC.
SGND/PGND (Exposed Pad Pin 33) QFN Package: Signal
Ground and Power Ground. Connect this pin closely to
SW1, SW2 (Pins 36, 22/Pins 26, 16): Switch Node
Connections to Inductors. Voltage swing at these pins
is from a Schottky diode (external) voltage drop below
ground to VIN.
CLKOUT (Pin 37/Pin 27): Clock output with phase changeable by PHASMD to enable usage of multiple LTC3856 ICs
in multiphase systems.
PLLIN (Pin 38/Pin 28): External Synchronization Pin. A
clock on the pin synchronizes the internal oscillator with
the clock on this pin.
SGND (Exposed Pad Pin 39) TSSOP Package: The exposed
pad must be soldered to the PCB.
3856f
10
LTC3856
FUNCTIONAL DIAGRAM
EXTVCC
ITEMP
MODE PLLIN PHASMD
4.7V
FREQ
+
–
TEMPSNS
VIN
F
0.6V
MODE/SYNC
DETECT
CIN
5V
REG
+
–
INTVCC
F
PLL-SYNC
INTVCC
BURSTEN
CLKOUT
S
+
ICMP
TG
CB
M1
SENSE+
SWITCH
LOGIC
AND
ANTISHOOTTHROUGH
–
+
–
DB
SW
ON
R Q
3k
BOOST
FCNT
OSC
IREV
ISET
VOUT
+
BG
COUT
M2
OV
ISET
L1
SENSE–
RUN
ISET
VIN
+
CVCC
PGND
ILIM
RAVP
PGOOD
SLOPE
COMPENSATION
+
INTVCC
UVLO
UV
+
0.54V
VFB
R2
DIFFAMP
–
1
51k
ITHB
SLEEP
40k
40k
–
SLOPE RECOVERY
ACTIVE CLAMP
+
40k
R1
40k
DIFFN
OV
–
ISET
+
–
0.5V
–
EA
SS
RUN
+
VIN
– + +
+
–
0.6V
REF
DIFFP
DIFFOUT
1.25µA
0.66V
SGND
RPRE-AVP
AVP
1.22V
0.55V
+
–
SENSE1+
SENSE1–
+
–
SENSE2+
SENSE2–
1µA
ITH
RC
CC1
RUN
TK/SS CSS
3856 FD
3856f
11
LTC3856
OPERATION (Refer to Functional Diagram)
Main Control Loop
The LTC3856 uses a constant-frequency, current mode
step-down architecture. During normal operation, each
top MOSFET is turned on each cycle when the oscillator
sets the RS latch, and turned off when the main current
comparator, ICMP , resets each RS latch. The peak inductor
current at which ICMP resets the RS latch is controlled
by the voltage on the ITH pin, which is the output of the
error ampliier, EA. The VFB pin receives a portion of
output voltage feedback signal via the DIFFOUT pin (if
DIFFAMP is used) through the external resistive divider
and is compared to the internal reference voltage. When
the load current increases, it causes a slight decrease in
the VFB pin voltage relative to the 0.6V reference, which
in turn causes the ITH voltage to increase until each
inductor’s average current matches half of the new load
current (assuming the two current sensing resistors are
equal). In Burst Mode operation, after each top MOSFET
has turned off, the bottom MOSFET is turned on until
either the inductor current starts to reverse, as indicated
by the reverse current comparator, IREV , or the beginning
of the next cycle.
The main control loop is shut down by pulling the RUN pin
low. Releasing RUN allows an internal 1µA current source
to pull up the RUN pin. When the RUN pin reaches 1.22V,
the main control loop is enabled and the IC is powered
up. When the RUN pin is low, all functions are kept in a
controlled state.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is left open or tied to a voltage less
than 4.7V, an internal 5V linear regulator supplies INTVCC
power from VIN. If EXTVCC is taken above 4.7V, the 5V
regulator is turned off and an internal switch is turned on
connecting EXTVCC. Using the EXTVCC pin allows the INTVCC
power to be derived from a high eficiency external source
such as a switching regulator output. Each top MOSFET
driver is biased from the loating bootstrap capacitor, CB,
which normally recharges during each off cycle through
an external diode when the top MOSFET turns off. If the
input voltage, VIN, decreases to a voltage close to VOUT ,
the loop may enter dropout and attempt to turn on the
top MOSFET continuously. The dropout detector detects
this and forces the top MOSFET off for about one-twelfth
of the clock period plus 100ns every third cycle to allow
CB to recharge. However, it is recommended that a load
be present or the IC operates at low frequency during the
dropout transition to ensure CB is recharged.
Shutdown and Start-Up (RUN and TK/SS Pins)
The LTC3856 can be shut down using the RUN pin. Pulling
the RUN pin below 1.22V shuts down the main control loop
for the controller and most internal circuits, including the
INTVCC regulator. Releasing the RUN pin allows an internal
1µA current to pull up the pin and enable the controller.
Alternatively, the RUN pin may be externally pulled up or
driven directly by logic. Be careful not to exceed the absolute maximum rating of 6V on this pin. The start-up of
the controller’s output voltage, VOUT , is controlled by the
voltage on the TK/SS pin. When the voltage on the TK/SS
pin is less than the 0.6V internal reference, the LTC3856
regulates the VFB voltage to the TK/SS pin voltage instead
of the 0.6V reference. This allows the TK/SS pin to be
used to program a soft-start by connecting an external
capacitor from the TK/SS pin to SGND. An internal 1.25µA
pull-up current charges this capacitor, creating a voltage
ramp on the TK/SS pin. As the TK/SS voltage rises linearly
from 0V to 0.6V (and beyond), the output voltage, VOUT ,
rises smoothly from zero to its inal value. Alternatively,
the TK/SS pin can be used to cause the start-up of VOUT
to track that of another supply. Typically, this requires
connecting to the TK/SS pin an external resistor divider
from the other supply to ground (see the Applications
Information section). When the RUN pin is pulled low to
disable the controller, or when INTVCC drops below its
undervoltage lockout threshold of 3.2V, the TK/SS pin is
pulled low by an internal MOSFET. When in undervoltage
lockout, all phases of the controller are disabled and the
external MOSFETs are held off.
3856f
12
LTC3856
OPERATION (Refer to Functional Diagram)
Light Load Current Operation (Burst Mode Operation,
Stage Shedding or Continuous Conduction)
The LTC3856 can be enabled to enter high eficiency
Burst Mode operation, Stage Shedding mode or forced
continuous conduction mode. To select forced continuous
operation, tie the MODE pin to a DC voltage below 0.6V
(e.g., SGND). To select Stage Shedding mode of operation, tie the MODE pin to INTVCC. To select Burst Mode
operation, loat the MODE pin.
When the controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-sixth of the maximum sense voltage even though
the voltage on the ITH pin indicates a lower value. The
peak current can be programmed by the ISET pin. If the
average inductor current is higher than the load current,
the error ampliier, EA, will decrease the voltage on the
ITH pin. When the ITH voltage drops, the internal sleep
signal goes high (enabling sleep mode) and the external
MOSFETs are turned off. In sleep mode, the load current
is supplied by the output capacitor. As the output voltage
decreases, the EA’s output begins to rise. When the output
voltage drops enough, the sleep signal goes low, and the
controller resumes normal operation by turning on the
top external MOSFET on the next cycle of the internal
oscillator. When a controller is enabled for Burst Mode
operation, the inductor current is not allowed to reverse.
The reverse current comparator, IREV , turns off the bottom
external MOSFET just before the inductor current reaches
zero, preventing it from reversing and going negative.
Thus, the controller operates in discontinuous operation.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation. In
this mode, the eficiency at light loads is lower than in
Burst Mode operation. However, continuous mode has the
advantages of lower output ripple and less interference
with audio circuitry.
When the MODE pin is connected to INTVCC, the LTC3856
operates in Stage Shedding mode at light loads. The
controller will turn off channel 2 and increase the current
gain of the irst channel to ensure a smooth transition. The
threshold where the controller goes into Stage Shedding
mode is where the ITH voltage drops below 0.5V, but it can
be programmed by the ISET pin. The inductor current is
not allowed to reverse in this mode (discontinuous operation). At very light loads, the current comparator may
remain tripped for several cycles and force the external top
MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). This mode exhibits low output ripple as
well as low audio noise and reduced RF interference as
compared to Burst Mode operation. It provides a higher
low current eficiency than forced continuous mode, but
not nearly as high as Burst Mode operation.
Multichip Operations (PHASMD and CLKOUT Pins)
The LTC3856’s two channels are 180° out-of-phase, providing multiphase operation. This coniguration can provide
enough power for most of the high current applications.
However, for even higher power applications, the LTC3856
can be conigured for PolyPhase and multichip operation.
The LTC3856 features PHASMD and CLKOUT pins which
enable multiple LTC3856s to operate out-of-phase, as
shown in Table 1. The CLKOUT signal is out-of-phase
with respect to phase 1 of the controller depending on the
PHASMD pin setting. In Stage Shedding mode, however,
the CLKOUT signal is 180° out-of-phase with respect to
phase 1 of the controller.
Table 1.
PHASMD
GND
FLOAT
INTVCC
Phase 1
0°
0°
0°
Phase 2
180°
180°
240°
CLKOUT
60°
90°
120°
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN Pins)
The selection of switching frequency is a trade-off between
eficiency and component size. Low frequency operation increases eficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
If the PLLIN pin is not being driven by an external clock
source, the FREQ pin can be used to program the controller’s
3856f
13
LTC3856
OPERATION (Refer to Functional Diagram)
operating frequency from 250kHz to 770kHz. There is a
precision 10µA current lowing out of the FREQ pin enabling
the user to program the controller’s switching frequency
with a single resistor to SGND. A curve is provided later in
the Applications Information section showing the relationship between the voltage on the FREQ pin and switching
frequency.
A phase-locked loop (PLL) is available on the LTC3856
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN pin. The PLL loop
ilter network is integrated inside the LTC3856. The
phase-locked loop is capable of locking any frequency
within the range of 250kHz to 770kHz. The frequency
setting resistor should always be present to set the
controller’s initial switching frequency before locking to
the external clock.
Sensing the Output Voltage with a Differential Ampliier
The LTC3856 includes a low offset, unity-gain, high bandwidth differential ampliier for applications that require true
remote sensing. Sensing the load across the load capacitors directly greatly beneits regulation in high current, low
voltage applications, where board interconnection losses
can be a signiicant portion of the total error budget.
The LTC3856 differential ampliier has a typical output slew
rate of 2V/µs. The ampliier is conigured for unity gain,
meaning that the difference between DIFFP and DIFFN is
translated to DIFFOUT, relative to SGND.
Care should be taken to route the DIFFP and DIFFN PCB
traces parallel to each other all the way to the terminals
of the output capacitor or remote sensing points on the
board. In addition, avoid routing these sensitive traces
near any high speed switching nodes in the circuit. Ideally,
the DIFFP and DIFFN traces should be shielded by a low
impedance ground plane to maintain signal integrity.
The maximum output voltage when using the differential
ampliier is INTVCC – 1.4V (typically 3.6V). The differential
ampliier should not be used above this voltage.
Power Good (PGOOD Pin)
The PGOOD pin is connected to an open drain of an internal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when either VFB pin voltage is not within
±10% of the 0.6V reference voltage. The PGOOD pin is
also pulled low when the RUN pin is below 1.22V or when
the LTC3856 is in the soft-start or tracking phase. When
the VFB pin voltage is within the ±10% regulation window,
the MOSFET is turned off and the pin is allowed to be
pulled up by an external resistor to a source of up to 6V.
The PGOOD pin will lag power good immediately when
VFB is within the regulation window. However, there is an
internal 20µs power-bad mask when VFB goes out of the
regulation window.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious conditions that may overvoltage the output. In such cases, the
top MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Undervoltage Lockout
The LTC3856 has two functions that help protect the
controller in case of undervoltage conditions. A precision
UVLO comparator constantly monitors the INTVCC voltage
to ensure that an adequate gate-drive voltage is present. It
locks out the switching action when INTVCC is below 3.2V.
To prevent oscillation when there is a disturbance on the
INTVCC, the UVLO comparator has 600mV of precision
hysteresis.
Another way to detect an undervoltage condition is
to monitor the VIN supply. Because the RUN pin has
a precision turn-on reference of 1.22V, one can use a
resistor divider to VIN to turn on the IC when VIN is high
enough. An extra 4.5µA of current lows out of the RUN
pin once the RUN pin voltage passes 1.22V. The RUN
comparator itself has about 80mV of hysteresis. One
can program additional hysteresis for the RUN comparator by adjusting the values of the resistive divider.
For accurate VIN undervoltage detection, VIN needs to
be higher than 4.5V.
3856f
14
LTC3856
APPLICATIONS INFORMATION
The Typical Application on the irst page of this data sheet
is a basic LTC3856 application circuit. LTC3856 can be
conigured to use either DCR (inductor resistance) sensing or low value resistor sensing. The choice between the
two current sensing schemes is largely a design trade-off
between cost, power consumption and accuracy. DCR
sensing is becoming popular because it saves expensive
current sensing resistors and is more power eficient,
especially in high current applications. However, current
sensing resistors provide the most accurate current limits
for the controller. Other external component selection is
driven by the load requirement, and begins with the selection of RSENSE (if RSENSE is used) and inductor value.
Next, the power MOSFETs are selected. Finally, input and
output capacitors are selected.
Current Limit Programming
The ILIM pin is a tri-level logic input which sets the maximum current limit of the controller. When ILIM is either
grounded, loated or tied to INTVCC, the typical value for
the maximum current sense threshold will be 30mV, 50mV
or 75mV, respectively.
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the current
comparators. The common mode input voltage range of
the current comparators is 0V to 5V. All SENSE+ pins are
high impedance inputs with small currents of less than
1µA. The positive high impedance input to the current
comparators allows accurate DCR sensing. All SENSE– pins
and DIFFP should be connected directly to VOUT when DCR
sensing is used. Care must be taken not to loat these pins
during normal operation. Filter components mutual to the
sense lines should be placed close to the LTC3856, and
the sense lines should run close together to a Kelvin connection underneath the current sense element (shown in
Figure 1). Sensing current elsewhere can effectively add
parasitic inductance and capacitance to the current sense
element, degrading the information at the sense terminals
and making the programmed current limit unpredictable.
If DCR sensing is used (Figure 2b), sense resistor R1
should be placed close to the switching node, to prevent
noise from coupling into sensitive small-signal nodes. The
capacitor C1 should be placed close to the IC pins.
TO SENSE FILTER,
NEXT TO THE CONTROLLER
Which setting should be used? For the best current limit
accuracy, use the 75mV setting. The 30mV setting will allow
for the use of very low DCR inductors or sense resistors,
but at the expense of current limit accuracy. The 50mV
setting is a good balance between the two.
VIN
INTVCC
VIN
INTVCC
RS
ESL
VOUT
PGND
RF
SENSE+
SENSE–
SGND
CF • 2RF ≤ ESL/RS
POLE-ZERO
CANCELLATION
L
SW
RS
DCR
VOUT
BG
PGND
R1
SENSE+
RNTC
CF
INDUCTOR
TG
OPTIONAL
TEMP COMP
NETWORK
ITEMP
BG
VIN
LTC3856
BOOST
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
SW
3856 F01
Figure 1. Sense Lines Placement with Sense Resistor
VIN
BOOST
TG
LTC3856
COUT
RSENSE
RP
C1*
R2
SENSE–
SGND
RF
3856 F02a
FILTER COMPONENTS
PLACED NEAR SENSE PINS
3856 F02b
(2a) Using a Resistor to Sense Current
*PLACE C1 NEAR SENSE+,
SENSE– PINS
R1||R2 × C1 =
L
DCR
RSENSE(EQ) = DCR
R2
R1 + R2
(2b) Using the Inductor DCR to Sense Current
Figure 2. Two Different Methods of Sensing Current
3856f
15
LTC3856
APPLICATIONS INFORMATION
Low Value Resistors Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. RSENSE is chosen based on the required
output current. The current comparator has a maximum
threshold, VSENSE(MAX), determined by the ILIM setting.
The input common mode range of the current comparator is 0V to 5V. The current comparator threshold sets the
peak of the inductor current, yielding a maximum average
output current, IMAX, equal to the peak value less half the
peak-to-peak ripple current, ∆IL. To calculate the sense
resistor value, use the equation:
RSENSE =
VSENSE(MAX )
I(MAX ) +
∆IL
2
Because of possible PCB noise in the current sensing loop,
the AC current sensing ripple of ∆VSENSE = ∆IL • RSENSE
also needs to be checked in the design to get a good
signal-to-noise ratio. In general, for a reasonably good
PCB layout, a 10mV ∆VSENSE voltage is recommended as
a conservative number to start with, either for RSENSE or
DCR sensing applications. For previous generation current
mode controllers, the maximum sense voltage was high
enough (e.g., 75mV for the LTC1628/LTC3728 family)
that the voltage drop across the parasitic inductance of
the sense resistor represented a relatively small error. For
today’s highest current density solutions, however, the
value of the sense resistor can be less than 1mΩ and the
peak sense voltage can be as low as 20mV. In addition,
inductor ripple currents greater than 50% with operation
up to 1MHz are becoming more common. Under these
conditions the voltage drop across the sense resistor’s
parasitic inductance is no longer negligible. A typical sensing circuit using a discrete resistor is shown in Figure 2a.
In previous generations of controllers, a small RC ilter
placed near the IC was commonly used to reduce the effects of capacitive and inductive noise coupled in the sense
traces on the PCB. A typical ilter consists of two series
10Ω resistors connected to a parallel 1000pF capacitor,
resulting in a time constant of 20ns. This same RC ilter,
with minor modiications, can be used to extract the resistive component of the current sense signal in the presence
of parasitic inductance. For example, Figure 3 illustrates
the voltage waveform across a 2mΩ sense resistor with
a 2010 footprint for the 1.2V/15A converter operating at
100% load. The waveform is the superposition of a purely
resistive component and a purely inductive component.
It was measured using two scope probes and waveform
math to obtain a differential measurement. Based on
additional measurements of the inductor ripple current
and the on-time and off-time of the top switch, the value
of the parasitic inductance was determined to be 0.5nH
using the equation:
ESL =
VESL(STEP) tON • tOFF
∆IL
tON + tOFF
(1)
If the RC time constant is chosen to be close to the
parasitic inductance divided by the sense resistor (L/R),
the resulting waveform looks resistive again, as shown
in Figure 4. For applications using low maximum sense
voltages, check the sense resistor manufacturer’s data
VESL(STEP)
VSENSE
20mV/DIV
VSENSE
20mV/DIV
500ns/DIV
3856 F03
Figure 3. Voltage Waveform Measured
Directly Across the Sense Resistor
500ns/DIV
3856 F04
Figure 4. Voltage Waveform Measured After
the Sense Resistor Filter. CF = 1000pF, RF = 100Ω
3856f
16
LTC3856
APPLICATIONS INFORMATION
sheet for information about parasitic inductance. In the
absence of data, measure the voltage drop directly across
the sense resistor to extract the magnitude of the ESL step
and use Equation 1 to determine the ESL. However, do not
overilter. Keep the RC time constant, less than or equal
to the inductor time constant to maintain a high enough
ripple voltage of ∆VSENSE. The equation generally applies
to high density/high current applications where IMAX >
10A and low values of inductors are used. For applications
where IMAX < 10A, set RF to 10Ω and CF to 1000pF. This
will provide a good starting point. The ilter components
need to be placed close to the IC. The positive and negative sense traces need to be routed as a differential pair
and Kelvin connected to the sense resistor.
Inductor DCR Sensing
For applications requiring the highest possible eficiency
at high load currents, the LTC3856 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such an
inductor, conduction loss through a sense resistor would
cost several points of eficiency compared to DCR sensing.
If the external R1|| R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external ilter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult the
manufacturers’ data sheets for detailed information.
Using the inductor ripple current value from the Inductor
Value Calculation and Output Ripple Current section, the
target sense resistor value is:
RSENSE(EQUIV ) =
VSENSE(MAX )
I(MAX ) +
∆IL
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the maximum current sense threshold
(VSENSE(MAX)) in the Electrical Characteristics table (25mV,
45mV or 68mV, depending on the state of the ILIM pin).
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coeficient of resistance, which is approximately 0.4%/°C.
A conservative value for TL(MAX) is 100°C. To scale the
maximum inductor DCR to the desired sense resistor
value, use the divider ratio:
RD =
RSENSE(EQUIV )
DCRMAX at TL(MAX )
C1 is usually selected to be in the range of 0.047µF to
0.47µF. This forces R1|| R2 to around 2k, reducing error
that might have been caused by the SENSE+ pins’ ±1µA
current. TL(MAX) is the maximum inductor temperature.
The equivalent resistance R1|| R2 is scaled to the room
temperature inductance and maximum DCR:
R1|| R2 =
L
(DCR at 20°C ) • C1
The sense resistor values are:
R1 =
R1 • RD
R1|| R2
; R2 =
RD
1 − RD
3856f
17
LTC3856
APPLICATIONS INFORMATION
The LTC3856 also features a DCR temperature compensation circuit by using a NTC temperature sensor. See the
Inductor DCR Sensing Temperature Compensation and
the ITEMP Pin section for details.
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
PLOSS R1=
(V
IN(MAX ) − VOUT
)•V
OUT
R1
Ensure that R1 has a power rating higher than this value.
If high eficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
to the extra switching losses incurred through R1. However,
DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher eficiency at heavy loads.
Peak eficiency is about the same with either method. To
maintain a good signal-to-noise ratio for the current sense
signal, use a minimum ∆VSENSE of 10mV for duty cycles
less than 40%. For a DCR sensing application, the actual
ripple voltage will be determined by the equation:
∆VSENSE =
VIN − VOUT VOUT
R1• C1 VIN • fOSC
Inductor DCR Sensing Temperature Compensation
and the ITEMP Pin
Inductor DCR current sensing provides a lossless method
of sensing the instantaneous current. Therefore, it can
provide higher eficiency for applications of high output
currents. However, the DCR of the inductor, which is the
small amount of DC winding resistance of the copper,
typically has a positive temperature coeficient. As the
temperature of the inductor rises, its DCR value increases.
The current limit of the controller is therefore reduced.
The LTC3856 offers a method to counter this inaccuracy
by allowing the user to place an NTC temperature sensing
resistor near the inductor to actively correct this error.
The ITEMP pin, when left loating, is at a voltage around
5V and DCR temperature compensation is disabled. The
ITEMP pin has a constant 10µA precision current lowing out of the pin. By connecting an NTC resistor from
the ITEMP pin to SGND, the maximum current sense
threshold can be varied over temperature according the
following equation:
VSENSEMAX( ADJ) = VSENSE(MAX ) •
1.8 – VITEMP
1.3
where:
VSENSEMAX(ADJ) is the maximum adjusted current sense
threshold at temperature.
VSENSE(MAX) is the maximum current sense threshold
speciied in the Electrical Characteristics table. It is
typically 75mV, 50mV or 30mV, depending on the setting ILIM pins.
VITEMP is the voltage of the ITEMP pin.
The valid voltage range for DCR temperature compensation on the ITEMP pin is between 0.5V to 0.2V, with 0.5V
or above being no DCR temperature correction and 0.2V
the maximum correction. However, if the duty cycle of the
controller is less than 25%, the ITEMP range is extended
from 0.5V to 0V.
The NTC resistor has a negative temperature coeficient,
meaning its value decreases as temperature rises. The
VITEMP voltage, therefore, decreases as temperature increases and in turn, the VSENSEMAX(ADJ) will increase to
compensate the DCR temperature coeficient. The NTC
resistor, however, is nonlinear and the user can linearize its value by building a resistor network with regular
resistors. Consult the NTC manufacture data sheets for
detailed information.
Another use for the ITEMP pins, in addition to NTC compensated DCR sensing, is adjusting VSENSE(MAX) to values
between the nominal values of 30mV, 50mV and 75mV
for a more precise current limit. This is done by applying
a voltage less than 0.5V to the ITEMP pin. VSENSE(MAX)
will be varied per the previous equation and the same
duty cycle limitations will apply. The current limit can be
adjusted using this method either with a sense resistor
or DCR sensing.
3856f
18
LTC3856
APPLICATIONS INFORMATION
NTC Compensated DCR Sensing
For DCR sensing applications where a more accurate
current limit is required, a network consisting of an NTC
thermistor placed from the ITEMP pin to ground will
provide correction of the current limit over temperature.
Figure 2b shows this network. Resistors RS and RP will
linearize the impedance the ITEMP pin sees. To implement
NTC compensated DCR sensing, design the DCR sense
ilter network per the same procedure mentioned in the
previous selection, except calculate the divider components using the room temperature value of the DCR. For
a typical application:
The resistance of the NTC thermistor can be obtained
from the vendor’s data sheet either in the form of graphs,
tabulated data or formulas. The approximate value for the
NTC thermistor for a given temperature can be calculated
from the following equation:
 

1 −
1
R = RO • exp B • 

  T + 273 TO + 273  
Where
R = resistance at temperature T, in degrees C
RO = resistance at temperature TO , typically 25°C
B = B-constant of the thermistor.
1. Set the ITEMP pin resistance to 50k at 25°C. With
10µA lowing out of the ITEMP pin, the voltage on the
ITEMP pin will be 0.5V at room temperature. Current
limit correction will occur for inductor temperatures
greater than 25°C.
Figure 5 shows a typical resistance curve for a 100k thermistor and the ITEMP pin network over temperature.
2. Calculate the ITEMP pin resistance and the maximum
inductor temperature, which is typically 100°C. Use the
following equations:
• RS = 20k
VITEMP100C
R2
0.4
IMAX • DCRMAX •
• (100 °C − 25 °C) •
R1 + R2
100
VSENSE(MAX )
Calculate the values for RP and RS. A simple method is to
graph the following RS versus RP equations with RS on
the y-axis and RP on the x-axis.
• NTC RO = 100k
• RP = 50k
But, the inal values should be calculated using the previous equations and checked at 25°C and 100°C.
10000
THERMISTOR RESISTANCE:
RO = 100k
TO = 25°C
B = 4334 for 25°C/100°C
1000
RESISTANCE (k)
VITEMP100C
10µA
= 0 . 5V − 1 .33 •
RITEMP100C =
Starting values for the NTC compensation network are:
100
10
RITMP:
RS = 20k
RP = 43.2k
100k NTC
RS = RITEMP25C – RNTC25C ||RP
RS = RITEMP100C – RNTC100C ||RP
Next, ind the value of RP that satisies both equations,
which will be the point where the curves intersect. Once
RP is known, solve for RS.
0
–40 –20
0
20 40 60 80 100 120
INDUCTOR TEMPERATURE (°C)
3856 F05
Figure 5. Resistance vs Temperature for the
ITEMP Pin Network and the 100k NTC
3856f
19
LTC3856
APPLICATIONS INFORMATION
After determining the components for the temperature
compensation network, check the results by plotting
IMAX versus inductor temperature using the following
equations:
IMAX =
Typical values for the NTC compensation network are:
• NTC RO = 100k, B-constant = 3000 to 4000
• RS ≈ 20k
• RP ≈ 50k
VSENSEMAX( ADJ) −
∆ VSENSE
2

0.4 
DCRMAX AT 25 ° C • 1 + (TL(MAX ) − 25 °C) •
100 

where
VSENSEMAX( ADJ) = VSENSE(MAX ) •
1. 8 V − VITMP
−A
1.3
VITMP = 10µA • (RS + RP ||RNTC)
Use typical values for VSENSE(MAX). Subtracting constant A
will provide a minimum value for VSENSE(MAX). These values
are summarized in Table 2.
Another approach for generating the IMAX versus inductor
temperature curve plot is to irst use the aforementioned
values as a starting point and then adjusting the RS and
RP values as necessary. Figure 6 shows a typical curve
of IMAX versus inductor temperature.
The same thermistor network can be used to correct for
temperatures less than 25°C. But, ensure that VITEMP is
greater than 0.2V for duty cycles of 25% or more, otherwise temperature correction may not occur at elevated
ambients. For the most accurate temperature detection,
place the thermistor next to the inductors, as shown in
Figure 7. Take care to keep the ITEMP pins away from the
switch nodes.
RNTC
Table 2. Values for VSENSE(MAX)
ILIM
GND
FLOAT
INTVCC
VSENSE(MAX) Typ
30mV
50mV
75mV
A
5mV
5mV
7mV
The resulting current limit should be greater than or
equal to IMAX for inductor temperatures between 25°C
and 100°C.
25
20
IMAX (A)
CORRECTED
IMAX
15
10
VOUT
L1
L2
SW1
SW2
3856 F07
Figure 7. Thermistor Location. Place Thermistor Next to
Inductor(s) for Accurate Sensing of the Inductor Temperature,
But Keep the ITEMP Pin Away from the Switch Nodes and
Gate Drive Traces.
Slope Compensation and Inductor Peak Current
NOMINAL
IMAX
UNCORRECTED
IMAX
RS = 20k
RP = 43.2k
5 NTC THERMISTOR:
RO = 100k
TO = 25°C
B = 4334
0
–40 –20 0
20 40 60 80 100 120
INDUCTOR TEMPERATURE (°C)
3856 F06
Figure 6. Worst Case IMAX vs Inductor Temperature Curve
with and without NTC Temperature Compensation
Slope compensation provides stability in constant-frequency, current mode architectures by preventing subharmonic
oscillation at high duty cycles. It is accomplished internally
by adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. Normally, this
results in a reduction of maximum inductor peak current
for duty cycles greater than 40%. However, the LTC3856
uses a scheme that counteracts this compensating ramp,
which allows the maximum inductor peak current to remain
unaffected throughout all duty cycles.
3856f
20
LTC3856
APPLICATIONS INFORMATION
Inductor Value Calculation and Output Ripple Current
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of
smaller inductor and capacitor values. A higher frequency
generally results in lower eficiency because of MOSFET
gate charge and transition losses. In addition to this basic
trade-off, the effect of inductor value on ripple current
and low current operation must also be considered. The
PolyPhase approach reduces both input and output ripple
currents while optimizing individual output stages to run
at a lower fundamental frequency, enhancing eficiency.
The inductor value has a direct effect on ripple current.
The inductor ripple current, ∆IL, per individual section
N, decreases with higher inductance or frequency and
increases with higher VIN or VOUT :
∆IL =
VOUT
fOSC • L
 VOUT 
 1– V 

IN 
where fOSC is the individual output stage operating frequency.
In a PolyPhase converter, the net ripple current seen by
the output capacitor is much smaller than the individual
inductor ripple currents due to the ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.
Figure 8 shows the net ripple current seen by the output
capacitors for the different phase conigurations. The
1.0
VOUT k
= where k = 1, 2,...,N – 1
VIN N
Power MOSFET and Schottky Diode
(Optional) Selection
At least two external power MOSFETs must be selected
for each power stage: One N-channel MOSFET for the top
(main) switch and one or more N-channel MOSFET(s) for
the bottom (synchronous) switch. The number, type and
on-resistance of all MOSFETs selected take into account
the voltage step-down ratio as well as the actual position
(main or synchronous) in which the MOSFET will be used.
A much smaller and much lower input capacitance MOSFET
should be used for the top MOSFET in applications that
have an output voltage that is less than one-third of the input
voltage. In applications where VIN >> VOUT, the top MOSFETs’
on-resistance is normally less important for overall eficiency
than its input capacitance at operating frequencies above
300kHz. MOSFET manufacturers have designed special
purpose devices that provide reasonably low on-resistance
with signiicantly reduced input capacitance for the main
switch application in switching regulators.
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
12-PHASE
0.9
0.8
0.7
IO(P-P)
VO/fL
output ripple current is plotted for a ixed output voltage
as the duty factor is varied between 10% and 90% on the
x-axis. The output ripple current is normalized against the
inductor ripple current at zero duty factor. The graph can
be used in place of tedious calculations. The zero output
ripple current is obtained when:
0.6
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3 0.4 0.5 0.6 0.7
DUTY FACTOR (VOUT/VIN)
0.8
0.9
3856 F08
Figure 8. Normalized Peak Output Current
vs Duty Factor [IRMS = 0.3(IOP-P)]
3856f
21
LTC3856
APPLICATIONS INFORMATION
The peak-to-peak MOSFET gate drive levels are set by the
voltage, VCC, requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BVDSS speciication for the MOSFETs as well; many of the
logic-level MOSFETs are limited to 30V or less. Selection
criteria for the power MOSFETs include the on-resistance,
RDS(ON), input capacitance, input voltage and maximum
output current. MOSFET input capacitance is a combination
of several components but can be taken from the typical
gate charge curve included on most data sheets (Figure 9).
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage, then plotting the gate voltage versus time.
mode, the duty cycles for the top and bottom MOSFETs
are given by:
Main Switch Duty Cycle =
 V –V 
Synchronous Switch Duty Cycle =  IN OUT 
VIN


The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
I

V
PMAIN = OUT  MAX 
VIN  N 
I
VIN
VGS
MILLER EFFECT
a
V
b
QIN
CMILLER = (QB – QA)/VDS
+
VGS
–
+V
DS
–
3856 F09
Figure 9. Gate Charge Characteristic
The initial slope is the effect of the gate-to-source and
the gate-to-drain capacitance. The lat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is lat) is speciied for a given VDS drain
voltage, but can be adjusted for different VDS voltages by
multiplying the ratio of the application VDS to the curve
speciied VDS values. A way to estimate the CMILLER
term is to take the change in gate charge from points
a and b on a manufacturer’s data sheet and divide by
the stated VDS voltage speciied. CMILLER is the most
important selection criteria for determining the transition
loss term in the top MOSFET but is not directly speciied
on MOSFET data sheets. CRSS and COS are speciied
sometimes but deinitions of these parameters are not
included. When the controller is operating in continuous
VOUT
VIN
2
(1+ δ )RDS(ON) +

( VIN )2  MAX
(R )(C
)•
2N  DR MILLER

1
1 
+

•f
 VCC – VTH(IL) VTH(IL) 
I

V –V
PSYNC = IN OUT  MAX 
VIN
 N 
2
(1+ δ )RDS(ON)
where N is the number of output stages, δ is the temperature dependency of RDS(ON), RDR is the effective top
driver resistance (approximately 2Ω at VGS = VMILLER),
VIN is the drain potential and the change in drain potential in the particular application. VTH(IL) is the data sheet
speciied typical gate threshold voltage speciied in the
power MOSFET data sheet at the speciied drain current.
CMILLER is the calculated capacitance using the gate charge
curve from the MOSFET data sheet and the technique just
described.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For VIN < 20V,
the high current eficiency generally improves with larger
MOSFETs, while for VIN > 20V, the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher eficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low, or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
3856f
22
LTC3856
APPLICATIONS INFORMATION
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diodes conduct during the dead
time between the conduction of the two large power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the
dead time and requiring a reverse-recovery period which
could cost as much as several percent in eficiency. A 2A
to 8A Schottky is generally a good compromise for both
regions of operation due to the relatively small average
current. Larger diodes result in additional transition loss
due to their larger junction capacitance. A Schottky diode
in parallel with the bottom FET may also provide a modest
improvement in Burst Mode eficiency.
CIN and COUT Selection
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle VOUT/
VIN. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a close form
equation can be found in Application Note 77. Figure 10
shows the input capacitor ripple current for different phase
conigurations with the output voltage ixed and input voltage varied. The input ripple current is normalized against
the DC output current. The graph can be used in place of
tedious calculations. The minimum input ripple current
can be achieved when the product of phase number and
output voltage, N(VOUT), is approximately equal to the
input voltage, VIN, or:
VOUT k
= where k = 1, 2,...,N – 1
VIN N
So, the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages. In
the graph of Figure 10, the local maximum input RMS
capacitor currents are reached when:
VOUT 2k – 1
where k = 1, 2,...,N
=
VIN
N
These worst-case conditions are commonly used for design
because even signiicant deviations do not offer much relief.
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. Always consult the
capacitor manufacturer if there is any question.
The Figure 10 graph shows that the peak RMS input
current is reduced linearly, inversely proportional to the
number N of stages used. It is important to note that the
eficiency loss is proportional to the input RMS current
squared and therefore a 3-stage implementation results
in 90% less power loss when compared to a single-phase
design. Battery/input protection fuse resistance (if used),
PC board trace and connector resistance losses are also
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.6
0.5
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
12-PHASE
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3 0.4 0.5 0.6 0.7
DUTY FACTOR (VOUT/VIN)
0.8
0.9
3856 F10
Figure 10. Normalized Input RMS Ripple Current
vs Duty Factor for One to Six Output Stages
3856f
23
LTC3856
APPLICATIONS INFORMATION
reduced by the reduction of the input ripple current in a
PolyPhase system. The required amount of input capacitance is further reduced by the factor N, due to the effective
increase in the frequency of the current pulses. Ceramic
capacitors are becoming very popular for small designs
but several cautions should be observed. X7R, X5R and
Y5V are examples of a few of the ceramic materials used
as the dielectric layer, and these different dielectrics have
very different effect on the capacitance value due to the
voltage and temperature conditions applied. Physically,
if the capacitance value changes due to applied voltage
change, there is a concomitant piezo effect which results
in radiating sound! A load that draws varying current at an
audible rate may cause an attendant varying input voltage
on a ceramic capacitor, resulting in an audible signal. A
secondary issue relates to the energy lowing back into
a ceramic capacitor whose capacitance value is being
reduced by the increasing charge. The voltage can increase
at a considerably higher rate than the constant current being
supplied because the capacitance value is decreasing as
the voltage is increasing! Nevertheless, ceramic capacitors,
when properly selected and used, can provide the lowest
overall loss due to their extremely low ESR.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically once the ESR requirement
is satisied the capacitance is adequate for iltering. The
steady-state output ripple (∆VOUT) is determined by:

1 
∆VOUT ≈ ∆IRIPPLE  ESR +
8NfCOUT 

where f = operating frequency of each stage, N = the
number of output stages, COUT = output capacitance and
∆IL = ripple current in each inductor. The output ripple is
highest at maximum input voltage since ∆IL increases with
input voltage. The output ripple will be less than 50mV at
maximum VIN with ∆IL = 0.4IOUT(MAX) assuming:
COUT required ESR < N • RSENSE
and
COUT >
1
(8Nf) (RSENSE )
The emergence of very low ESR capacitors in small, surface
mount packages makes very small physical implementa-
tions possible. The ability to externally compensate the
switching regulator loop using the ITH pin allows a much
wider selection of output capacitor types. The impedance
characteristic of each capacitor type is signiicantly different than an ideal capacitor and therefore requires accurate
modeling or bench evaluation during design. Manufacturers
such as Nichicon, Nippon Chemi-Con and Sanyo should be
considered for high performance through-hole capacitors.
The OS-CON semiconductor dielectric capacitors available
from Sanyo and the Panasonic SP surface mount types
have a good (ESR)(size) product.
Once the ESR requirement for COUT has been met, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement. Ceramic capacitors from AVX, Taiyo Yuden
and Murata offer high capacitance value and very low ESR,
especially applicable for low output voltage applications.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum
electrolytic and dry tantalum capacitors are both available
in surface mount conigurations. New special polymer
surface mount capacitors offer very low ESR also but
have much lower capacitive density per unit volume. In
the case of tantalum, it is critical that the capacitors are
surge tested for use in switching power supplies. Several
excellent choices are the AVX TPS, AVX TPSV, the KEMET
T510 series of surface mount tantalums or the Panasonic
SP series of surface mount special polymer capacitors
available in case heights ranging from 2mm to 4mm. Other
capacitor types include Sanyo POSCAP, Sanyo OS-CON,
Nichicon PL series and Sprague 595D series. Consult the
manufacturers for other speciic recommendations.
Differential Ampliier
The LTC3856 has a true remote voltage sense capability.
The sensing connections should be returned from the
load, back to the differential ampliier’s inputs through a
common, tightly coupled pair of PC traces. The differential
ampliier rejects common mode signals capacitively or
inductively radiated into the feedback PC traces as well as
ground loop disturbances. The differential ampliier output
signal is divided by a pair of resistors and is compared
with the internal, precision 0.6V voltage reference by the
3856f
24
LTC3856
APPLICATIONS INFORMATION
error ampliier. The ampliier has an output swing range
of 0V to 3.6V. The output uses an NPN emitter follower
with 80k feedback resistance.
Active Voltage Positioning (AVP)
In an application, the AVP scheme modiies the regulated
output voltage depending on its current loading. AVP
can improve overall transient response and save power
consumption.
The LTC3856 senses inductor current information by monitoring voltage drops across the sense resistors RSENSE or
the DCR sensing network of the two channels. The voltage
drops are added together and applied as VPRE-AVP between
the AVP and DIFFP pins, which are connected through
resistor RPRE-AVP . Then VPRE-AVP is scaled through RAVP
and added to output voltage as the compensation for the
load voltage drop.
Let:
฀ ∆V = VSENSE1+ – VSENSE1–
฀ ∆V = VSENSE2+ – VSENSE2–
then:
 R AVP 
∆VDIFFP,VOUT = 2 • ∆V 

 RPRE-AVP 
The inal load slope is deined by the inductor current
sense resistors and the two external resistors previously
mentioned.
In summary, the load slope is:

R AVP 
R
•
V/ A
SENSE

RPRE-AVP 
Programmable Stage Shedding Mode
When the MODE pin is tied to INTVCC, the LTC3856 enters Stage Shedding mode. This means that the second
channel will stop switching when ITH is below a certain
programmed threshold. This threshold voltage on ITH is
programmed according to the following formula:
 5
VSHED = 0 . 5 +   • ( 0 . 5 − VISET )
 3
The valid range of VISET is between 0V to 0.5V, where VISET
is the voltage on the ISET pin. There is a precision 7.5µA
lowing out of the ISET pin. Connecting a resistor to SGND
sets the VISET voltage. When left loating, VISET voltage will
be at INTVCC. The Stage Shedding mode threshold voltage
in this case will be 0.5V. There is a 50mV hysteresis for
the Stage Shedding mode threshold comparator.
Programmable Burst Mode Operation
When the MODE pin is loating, the LTC3856 enters Burst
Mode operation. This means that both channels will stop
switching when ITH is below a certain threshold.
The Burst Mode clamp, which sets the current limit when
bursting, can be programmed through VISET according to
the following formula:
VCLAMP = 0.7 + 0.62 (0.5 – VISET)
The valid range of VISET is between 0.3V to 0.5V and
VISET is the voltage on the ISET pin. There is a precision
7.5µA lowing out of ISET. Connecting a resistor to SGND
sets the VISET voltage. When left loating, VISET will be at
INTVCC. The Burst Mode clamp voltage in this case will
be 0.7V. There is a 50mV hysteresis for the Burst Mode
comparator.
The recommended value for RAVP is 90Ω to 100Ω. The
maximum output voltage at AVP is 2.5V. Therefore, for
outputs higher than 2.5V, the AVP function is not supported.
The DIFFP pin, however, should always be connected to the
output even when AVP or diffamp functions are not used.
3856f
25
LTC3856
APPLICATIONS INFORMATION
Soft-Start and Tracking
The LTC3856 has the ability to either soft-start by itself
with a capacitor or track the output of another external
supply. When the controller is conigured to soft-start by
itself, a capacitor should be connected to its TK/SS pin.
The controller is in the shutdown state if its RUN pin voltage is below 1.22V and its TK/SS pin is actively pulled to
ground in this shutdown state.
Once the RUN pin voltage is above 1.22V, the controller
powers up. A soft-start current of 1.25µA then starts to
charge the TK/SS soft-start capacitor. Note that soft-start
or tracking is achieved not by limiting the maximum
output current of the controller but by controlling the
output ramp voltage according to the ramp rate on the
TK/SS pin. Current foldback is disabled during this phase
to ensure smooth soft-start or tracking. The soft-start or
tracking range is deined to be the voltage range from 0V
to 0.6V on the TK/SS pin. The total soft-start time can be
calculated as:
t SOFTSTART = 0.6 •
CSS
1.25µA
Regardless of the mode selected by the MODE pin, the
controller always starts in discontinuous mode up to TK/SS
= 0.5V. Between TK/SS = 0.5V and 0.54V, it will operate in
forced continuous mode and revert to the selected mode
once TK/SS > 0.54V. The output ripple is minimized during the 40mV forced continuous mode window ensuring
a clean PGOOD signal.
When the channel is conigured to track another supply,
the feedback voltage of the other supply is duplicated by a
resistor divider and applied to the TK/SS pin. Therefore, the
voltage ramp rate on this pin is determined by the ramp rate
of the other supply’s voltage. Note that the small soft-start
capacitor charging current is always lowing, producing a
small offset error. To minimize this error, select the tracking resistive divider value to be small enough to make this
error negligible. In order to track down another channel or
supply after the soft-start phase expires, the LTC3856 is
forced into continuous mode of operation as soon as VFB
is below the undervoltage threshold of 0.54V regardless of
the setting on the MODE pin. However, the LTC3856 should
always be set in forced continuous mode tracking down
when there is no load. After TK/SS drops below 0.1V, the
controller operates in discontinuous mode.
The LTC3856 allows the user to program how its output
ramps up and down by means of the TK/SS pins. Through
these pins, the output can be set up to either coincidentally
or ratiometrically track another supply’s output, as shown
in Figure 11. In the following discussions, VOUT1 refers
to the LTC3856’s output as a master and VOUT2 refers to
another supply output as a slave. To implement the coincident tracking in Figure 11a, connect an additional resistive
divider to VOUT1 and connect its mid-point to the TK/SS pin
of the slave controller. The ratio of this divider should be
the same as that of the slave controller’s feedback divider
shown in Figure 12a. In this tracking mode, VOUT1 must
be set higher than VOUT2. To implement the ratiometric
tracking in Figure 11b, the ratio of the VOUT2 divider should
be exactly the same as the master controller’s feedback
divider shown in Figure 12b . By selecting different resistors, the LTC3856 can achieve different modes of tracking
including the two in Figure 11.
So, which mode should be programmed? While either
mode in Figure 11 satisies most practical applications,
some trade-offs exist. The ratiometric mode saves a pair
of resistors, but the coincident mode offers better output
regulation. Under ratiometric tracking, when the master
controller’s output experiences dynamic excursion (under
load transient, for example), the slave controller output
will be affected as well. For better output regulation, use
the coincident tracking mode instead of ratiometric.
INTVCC (LDO) and EXTVCC
The LTC3856 features a true PMOS LDO that supplies
power to INTVCC from the VIN supply. INTVCC powers
the gate drivers and much of the LTC3856’s internal circuitry. The LDO regulates the voltage at the INTVCC pin
to 5V when VIN is greater than 5.5V. EXTVCC connects
to INTVCC through a P-channel MOSFET and can supply
the needed power when its voltage is higher than 4.7V.
Each of these can supply a peak current of 100mA and
must be bypassed to ground with a minimum of 4.7µF
ceramic capacitor or other low ESR capacitor. No matter
what type of bulk capacitor is used, an additional 0.1µF
ceramic capacitor placed directly adjacent to the INTVCC
and PGND pins is highly recommended. Good bypassing
3856f
26
LTC3856
APPLICATIONS INFORMATION
VOUT1
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VOUT1
VOUT2
TIME
VOUT2
TIME
3856 F11a
3856 F11b
(11b) Ratiometric Tracking
(11a) Coincident Tracking
Figure 11. Two Different Modes of Output Voltage Tracking
VOUT1
VOUT2
R3
R1
TO
TK/SS2
PIN
R3
TO
VFB1
PIN
R4
R2
TO
VFB2
PIN
R4
VOUT1
TO
TK/SS2
PIN
VOUT2
R1
R2
R3
TO
VFB1
PIN
TO
VFB2
PIN
R4
3856 F12
(12a) Coincident Tracking Set-Up
(12b) Ratiometric Tracking Set-Up
Figure 12. Set-Up and Coincident and Ratiometric Tracking
is needed to supply the high transient currents required
by the MOSFET gate drivers and to prevent interaction
between the channels.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3856 to be
exceeded. The INTVCC current, which is dominated by the
gate charge current, may be supplied by either the 5V LDO
or EXTVCC. When the voltage on the EXTVCC pin is less
than 4.7V, the LDO is enabled. Power dissipation for the
IC in this case is highest and is equal to VIN • IINTVCC. The
gate charge current is dependent on operating frequency
as discussed in the Eficiency Considerations section.
The junction temperature can be estimated by using the
equations given in Note 3 of the Electrical Characteristics
table. For example, the LTC3856 INTVCC current is limited
to less than 42mA from a 38V supply in the UH package
and not using the EXTVCC supply:
TJ = 70°C + (42mA)(38V)(34°C/W) = 125°C
To prevent the maximum junction temperature from being exceeded, the input supply current must be checked
while operating in continuous conduction mode (MODE
= SGND) at maximum VIN. When the voltage applied to
EXTVCC rises above 4.7V, the INTVCC LDO is turned off
and the EXTVCC is connected to the INTVCC. The EXTVCC
remains on as long as the voltage applied to EXTVCC remains
above 4.5V. Using the EXTVCC allows the MOSFET driver
and control power to be derived from one of switching
regulator outputs during normal operation and from the
INTVCC when the output is out of regulation (e.g., start-up,
3856f
27
LTC3856
APPLICATIONS INFORMATION
short circuit). If more current is required through the
EXTVCC than is speciied, an external Schottky diode can
be added between the EXTVCC and INTVCC pins. Do not
apply more than 6V to the EXTVCC pin and make sure that
EXTVCC < VIN.
Signiicant eficiency and thermal gains can be realized
by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be
scaled by a factor of (duty cycle)/(switcher eficiency).
Tying the EXTVCC pin to a 5V supply reduces the junction
temperature in the previous example from 125°C to:
TJ = 70°C + (42mA)(5V)(34°C/W) = 77°C
However, for low voltage outputs, additional circuitry is
required to derive INTVCC power from the output.
The following list summarizes the four possible connections for EXTVCC:
1. EXTVCC left open (or grounded). This will cause INTVCC
to be powered from the internal 5V LDO resulting
in an eficiency penalty of up to 10% at high input
voltages.
2. EXTVCC connected directly to VOUT . This is the normal
connection for a 5V regulator and provides the highest
eficiency.
3. EXTVCC connected to an external supply. If a 5V external
supply is available, it may be used to power EXTVCC
providing it is compatible with the MOSFET gate drive
requirements.
4. EXTVCC connected to an output-derived boost network.
For 3.3V and other low voltage regulators, eficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V.
LTC3856
For applications where the main input power is 5V, tie the
VIN and INTVCC pins together and tie the combined pins
to the 5V input with a 1Ω or 2.2Ω resistor (as shown in
Figure 13) to minimize the voltage drop caused by the
gate charge current. This will override the INTVCC linear
regulator and will prevent INTVCC from dropping too low
due to the dropout voltage. Make sure the INTVCC voltage
is at or exceeds the RDS(ON) test voltage for the MOSFET,
which is typically 4.5V for logic-level devices.
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors, CB, connected to the
BOOST pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram
is charged though external diode DB from INTVCC when
the SW pin is low. When one of the topside MOSFETs is
to be turned on, the driver places the CB voltage across
the gate source of the desired MOSFET. This enhances
the MOSFET and turns on the topside switch. The switch
node voltage, SW, rises to VIN and the BOOST pin follows.
With the topside MOSFET on, the boost voltage is above
the input supply:
VBOOST = VIN + VINTVCC
The value of the boost capacitor, CB, needs to be 100 times
that of the total input capacitance of the topside MOSFET(s).
The reverse breakdown of the external Schottky diode
must be greater than VIN(MAX). When adjusting the gate
drive level, the inal arbiter is the total input current for
the regulator. If a change is made and the input current
decreases, then the eficiency has improved. If there is
no change in input current, then there is no change in
eficiency.
VIN
RVIN
1Ω
INTVCC
5V
CINTVCC
4.7µF
+
CIN
3856 F13
Figure 13. Set-Up for a 5V Input
3856f
28
LTC3856
APPLICATIONS INFORMATION
Setting Output Voltage
Fault Conditions: Current Limit and Current Foldback
If the DIFFAMP is not used, the LTC3856 output voltage
is set by an external feedback resistive divider carefully
placed across the output, as shown in Figure 14. The
regulated output voltage is determined by:
The LTC3856 includes current foldback to help limit load
current when the output is shorted to ground. If the output falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from its
maximum programmed value to one-third of the maximum
value. Foldback current limiting is disabled during the
soft-start or tracking up. Under short-circuit conditions
with very low duty cycles, the LTC3856 will begin cycle
skipping in order to limit the short-circuit current. In this
situation the bottom MOSFET will be dissipating most of
the power but less than in normal operation. The short
circuit ripple current is determined by the minimum ontime tON(MIN) of the LTC3856 (≈ 90ns), the input voltage
and inductor value:
 R 
VOUT = 0.6 V •  1+ B 
 RA 
To improve the frequency response, a feedforward capacitor, CFF , may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
If the diffamp is used, then VFB should be connected to the
output of the diffamp, DIFFOUT, as shown in the Typical
Application on the irst page.
VOUT /DIFFOUT
∆IL(SC) = tON(MIN) •
VIN
L
The resulting short-circuit current is:
LTC3856
RB
CFF
VFB
RA
 1/ 3 VSENSE(MAX ) 1

– ∆IL(SC)  • 2
ISC = 
2
RSENSE


3856 F14
Figure 14. Setting Output Voltage without the DIFFAMP
3856f
29
LTC3856
APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
The LTC3856 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the PLLIN pin. The turn-on of the
second phase’s top MOSFETs is thus 180° out-of-phase
with the external clock, and so on. The phase detector is
an edge-sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit a false lock
to harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the internal ilter
network. There is a precision 10µA of current lowing out
of FREQ pin. This allows the user to use a single resistor to
SGND to set the switching frequency when no external clock
is applied to the PLLIN pin. The internal switch between
the FREQ pin and the integrated PLL ilter network is on,
allowing the ilter network to be pre-charged at the same
voltage as of the FREQ pin. The relationship between the
voltage on the FREQ pin and operating frequency is shown
in Figure 15 and speciied in the Electrical Characteristics
table. If an external clock is detected on the PLLIN pin, the
internal switch mentioned above turns off and isolates the
inluence of the FREQ pin. Note that the LTC3856 can only
be synchronized to an external clock whose frequency is
within range of the LTC3856’s internal VCO. This is guaranteed to be between 250kHz and 770kHz. A simpliied
block diagram is shown in Figure 16.
If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the ilter network. When the external clock frequency is
900
2.4V
5V
RSET
800
FREQUENCY (kHz)
700
FREQ
600
PLLIN
500
EXTERNAL
OSCILLATOR
400
DIGITAL
SYNC
PHASE/
FREQUENCY
DETECTOR
VCO
300
200
100
0
0
0.5
1
1.5
2
FREQ/PLLFLTR PIN VOLTAGE (V)
2.5
3856 F16
3856 F15
Figure 15. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
Figure 16. Phase-Locked Loop Block Diagram
3856f
30
LTC3856
APPLICATIONS INFORMATION
less than fOSC, current is sunk continuously, pulling down
the ilter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the ilter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the ilter capacitor CLP holds the voltage.
Eficiency Considerations
Typically, the external clock (on the PLLIN pin) input high
threshold is 1.6V, while the input low threshold is 1V.
where L1, L2, etc. are the individual losses as a percentage of input power.
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3856 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <
VOUT
VIN ( f )
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase. The
minimum on-time for the LTC3856 is approximately 90ns,
with reasonably good PCB layout, minimum 30% inductor current ripple and at least 10mV ripple on the current
sense signal. The minimum on-time can be affected by
PCB switching noise in the voltage and current loop. As
the peak sense voltage decreases the minimum on-time
gradually increases to 130ns. This is of particular concern
in forced continuous applications with low ripple current
at light loads. If the duty cycle drops below the minimum
on-time limit in this situation, a signiicant amount of cycle
skipping can occur with correspondingly larger current
and voltage ripple.
The percent eficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the eficiency and which change would
produce the most improvement. Percent eficiency can
be expressed as:
%Eficiency = 100% – (L1 + L2 + L3 + ...)
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3856 circuits: 1) IC VIN current, 2) INTVCC
regulator current, 3) I2R losses, 4) topside MOSFET
transition losses.
1. The VIN current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver and control currents. VIN current typically results
in a small (<0.1%) loss.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG =
f(QT + QB), where QT and QB are the gate charges of the
topside and bottom side MOSFETs. Supplying INTVCC
power through EXTVCC from an output-derived source
will scale the VIN current required for the driver and
control circuits by a factor of (duty cycle)/(eficiency).
For example, in a 20V to 5V application, 10mA of
INTVCC current results in approximately 2.5mA of VIN
current. This reduces the mid-current loss from 10%
or more (if the driver was powered directly from VIN)
to only a few percent.
3. I2R losses are predicted from the DC resistances of
the fuse (if used), MOSFET, inductor and current sense
resistor. In continuous mode, the average output current
lows through L and RSENSE, but is chopped between
3856f
31
LTC3856
APPLICATIONS INFORMATION
the topside MOSFET and the synchronous MOSFET. If
the two MOSFETs have approximately the same RDS(ON),
then the resistance of one MOSFET can simply be
summed with the resistances of L and RSENSE to obtain I2R losses. For example, if each RDS(ON) = 10mΩ,
RL = 10mΩ, RSENSE = 5mΩ, then the total resistance is
25mΩ. This results in losses ranging from 2% to 8%
as the output current increases from 3A to 15A for a 5V
output, or a 3% to 12% loss for a 3.3V output.
Eficiency varies as the inverse square of VOUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become signiicant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) VIN2 • IO(MAX) • CRSS • f
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5%
to 10% eficiency degradation in portable systems. It
is very important to include these system level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by ensuring that
CIN has adequate charge storage and very low ESR at
the switching frequency. A 25W supply will typically
require a minimum of 20µF to 40µF of capacitance
having a maximum of 20mΩ to 50mΩ of ESR. Other
losses including Schottky conduction losses during
dead time and inductor core losses generally account
for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD (ESR), where ESR is the effective
series resistance of COUT . ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the ITH pin not only allows optimization of
control loop behavior but also provides a DC-coupled and
AC-iltered closed-loop response test point. The DC step,
rise time and settling at this test point truly relects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin.
The ITH external components shown in the Typical Application circuit will provide an adequate starting point for most
applications. The ITH series RC-CC ilter sets the dominant
pole-zero loop compensation. The values can be modiied
slightly (from 0.5 to 2 times their suggested values) to
optimize transient response once the inal PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1µs to
10µs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. Placing a power MOSFET
directly across the output capacitor and driving the gate
with an appropriate signal generator is a practical way to
produce a realistic load step condition. The initial output
voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop,
so this signal cannot be used to determine phase margin.
This is why it is better to look at the ITH pin signal which
is in the feedback loop and is the iltered and compensated control loop response. The gain of the loop will be
increased by increasing RC and the bandwidth of the loop
will be increased by decreasing CC. If RC is increased by
the same factor that CC is decreased, the zero frequency
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
3856f
32
LTC3856
APPLICATIONS INFORMATION
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT , causing a rapid drop in VOUT . No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
Design Example (Using Two Phases)
As a design example, assume:
VIN = 5V (nominal)
VIN = 5.5V (max),
VOUT = 1.8V,
IMAX = 20A
TA = 70°C
f = 300kHz
The inductance value is chosen irst based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Use a 71.5k resistor
from FREQ to ground to set the switching frequency at
about 300kHz. The minimum inductance for 30% ripple
current is:
L≥
VOUT  VOUT 
1−
f ( ∆I) 
VIN 
1.8 V
 1.8 V 
≥
1−
(300kHz )(30%)(10A )  5.5V 
≥ 1.35µH
A 2µH inductor will produce 20% ripple current. The peak
inductor current will be the maximum DC value plus one
half the ripple current, or 11A. The minimum on-time occurs at maximum VIN:
V
1.8 V
tON(MIN) = OUT =
= 1.1µs
VINf
5.5V 300kHz
(
)(
)
With the ILIM pin tied to ground, the RSENSE resistors
value can be calculated by using the minimum current
sense voltage speciication with some accommodation
for tolerances:
R SENSE =
25mV
≈ 0 . 002Ω
11A
Choosing 1% resistors: R1 = 10k and R2 = 20k yields an
output voltage of 1.80V.
The power dissipation on the topside MOSFET can be
easily estimated. Using a Siliconix Si4420DY for example;
RDS(ON) = 0.013Ω, CRSS = 300pF. At maximum input
voltage with TJ (estimated) = 110°C at an elevated ambient
temperature:
1 . 8V
2
10 ) 1 + ( 0 . 005) (110 °C − 25 °C) 
(
5 . 5V
2  10 A 
• 0 . 013Ω + ( 5 . 5V ) 
(2Ω)(300pF )
 2 
PMAIN =

1
1 
+
 5V − 2 . 6 V 2 . 6 V  • ( 300kHz )
= 0 . 606 + 0 . 022 = 0 . 628 W
The worst-case power dissipated by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction
temperature rise is:
5 . 5V − 1 . 8 V
2
10 A ) (1 . 25) ( 0 . 013Ω )
(
5 . 5V
= 1 . 0 9W
PSYNC =
3856f
33
LTC3856
APPLICATIONS INFORMATION
A short-circuit to ground will result in a folded back
current of:
I SC
25mV
1  90ns 5.5V
3
=
− 
0.002Ω
2 
2µH
(
)

 = 4.04A

The worst-case power dissipated by the synchronous
MOSFET under short-circuit conditions at elevated ambient temperature and estimated 50°C junction temperature
rise is:
5 . 5V − 1 . 8 V
2
4 . 04A ) (1 . 25) ( 0 . 013Ω )
(
5 . 5V
= 0 . 18W
PSYNC =
which is much less than normal, full-load conditions.
Incidentally, since the load no longer dissipates power in
the shorted condition, total system power dissipation is
decreased by over 99%.
The duty cycles when the peak RMS input current occurs is
at D = 0.25 and D = 0.75 according to Figure 10. Calculate
the worst-case required RMS input current rating at the
input voltage, which is 5.5V, that provides a duty cycle
nearest to the peak.
From Figure 10, CIN will require an RMS current rating of:
( )( )
CIN required IRMS = 20A 0.23
= 4.6ARMS
The output capacitor ripple current is calculated by using
the inductor ripple already calculated for each inductor and
multiplying by the factor obtained from Figure 8 along with
the calculated duty factor. The output ripple in continuous
mode will be highest at the maximum input voltage. From
Figure 8, the maximum output current ripple is:
VOUT
(0.34)
fL
1.8 ( 0.34)
∆ICOUTMAX =
= 1A
(300kHz )(2µH)
∆ICOUT =
Note that the PolyPhase technique will have its maximum
beneit for input and output ripple currents when the number
of phases times the output voltage is approximately equal
to or greater than the input voltage.
3856f
34
LTC3856
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 17. Check the following in the
PC layout:
1. Are the signal and power ground paths Kelvin connected?
Keep the SGND at one end of a printed circuit path thus
preventing MOSFET currents from traveling under the
IC. The INTVCC decoupling capacitor should be placed
immediately adjacent to the IC between the INTVCC pin
and PGND plane. A 1µF ceramic capacitor of the X7R or
X5R type is small enough to it very close to the IC to
minimize the ill effects of the large current pulses drawn
to drive the bottom MOSFETs. An additional 5µF to 10µF
of ceramic, tantalum or other very low ESR capacitance
is recommended in order to keep the internal IC supply
quiet. The power ground returns to the sources of the
bottom N-channel MOSFETs, anodes of the Schottky
diodes and (–) plates of CIN, which should have as short
lead lengths as possible.
2. Does the IC DIFFP pin connect to the (+) plates of
COUT? A 30pF to 300pF feedforward capacitor between
the DIFFP and VFB pins should be placed as close as
possible to the IC.
3. Are the SENSE– and SENSE+ printed circuit traces for
each channel routed together with minimum PC trace
spacing? The ilter capacitors between SENSE+ and
SENSE– for each channel should be as close as possible
to the pins of the IC. Connect the SENSE– and SENSE+
pins to the pads of the sense resistor as illustrated in
Figure 1.
4. Do the (+) plates of CPWR connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the pulsed current to the MOSFETs.
5. Keep the switching nodes, SWn, BOOSTn and TGn away
from sensitive small-signal nodes (SENSE+, SENSE–,
DIFFP, DIFFN, VFB, ITEMP). Ideally the SWn, BOOSTn
and TGn printed circuit traces should be routed away
and separated from the IC and especially the “quiet”
side of the IC. Separate the high dv/dt traces from sensitive small-signal nodes with ground traces or ground
planes.
6. Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.
7. The 47pF to 330pF ceramic capacitor between the ITH
pin and signal ground should be placed as close as possible to the IC. Figure 17 illustrates all branch currents
in a 2-phase switching regulator. It becomes very clear
after studying the current waveforms why it is critical to
keep the high switching current paths to a small physical
size. High electric and magnetic ields will radiate from
these loops just as radio stations transmit signals. The
output capacitor ground should return to the negative
terminal of the input capacitor and not share a common
ground path with any switched current paths. The left
half of the circuit gives rise to the noise generated by
a switching regulator. The ground terminations of the
synchronous MOSFETs and Schottky diodes should
return to the bottom plate(s) of the input capacitor(s)
with a short isolated PC trace since very high switched
currents are present. External OPTI-LOOP® compensation allows overcompensation for PC layouts which are
not optimized, but this is not the recommended design
procedure.
3856f
35
LTC3856
APPLICATIONS INFORMATION
SW1
L1
RSENSE1
D1
VOUT
VIN
RIN
CIN
+
+
SW2
L2
COUT
RL
RSENSE2
D2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.
3856 F17
Figure 17. Instantaneous Current Path Flow in a Multiple Phase Switching Regulation
3856f
36
LTC3856
TYPICAL APPLICATION
VIN
+
VIN
1nF
S
0.1µF
2.2Ω
5.6k
100pF
100Ω
VIN
100Ω
Q1
RJK0305DPB
S
S
CLKOUT
100k, 1%
0.1µF
VIN
FREQ
TG1
RUN
SW1
AVP
PHASMD
DIFFP
0.1µF
LTC3856
BOOST1
BG1
INTVCC
D1, CMDSH-3
INTVCC
4.7µF
TG2
D2, CMDSH-3
BOOST2
ISET
SW2
EXTVCC
BG2
ILIM
PGOOD
330µF
2.5V
฀4
4.7µF
6.3V
22µF
Q7
RJK0305DPB
L2
0.22µH
Q4
RJK0330DPB
0.001Ω
Q8
RJK0330DPB
SENSE2+
1nF
MODE
S
100µF
6.3V
+
฀4
22µF
INTVCC
0.1µF
VOUT
1.5V/
50A
0.001Ω
VIN
Q3
RJK0305DPB
DIFFN
100k
GND
Q6
RJK0330DPB
Q2
RJK0330DPB
DIFFOUT
INTVCC
L1
0.22µH
INTVCC
ITEMP
30.1k
Q5
RJK0305DPB
1nF
TK/SS
VFB
S
22µF
22µF
SENSE1+
PLLIN
ITH
20k
SENSE1–
180µF
16V
฀2
VIN
4.5V
TO 14V
PGOOD PGND SGND SENSE2–
100Ω
100Ω
S
10Ω
10Ω
3856 F18
Figure 18. 1.5V/50A Converter Using Sense Resistors
3856f
37
LTC3856
PACKAGE DESCRIPTION
FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev A)
Exposed Pad Variation AA
4.75 REF
38
9.60 – 9.80*
(.378 – .386)
4.75 REF
(.187)
20
6.60 ±0.10
2.74 REF
4.50 REF
SEE NOTE 4
6.40
2.74
REF (.252)
(.108)
BSC
0.315 ±0.05
1.05 ±0.10
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
1
0.25
REF
19
1.20
(.047)
MAX
0 –8
0.50
(.0196)
BSC
0.17 – 0.27
(.0067 – .0106)
TYP
0.05 – 0.15
(.002 – .006)
FE38 (AA) TSSOP 0608 REV A
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3856f
38
LTC3856
PACKAGE DESCRIPTION
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.57 ฀0.05
5.35
0.05
4.20 ฀0.05
3.45 ฀0.05
(4 SIDES)
PACKAGE OUTLINE
0.23
0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
5.00 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.75
R = 0.115
TYP
0.05
0.00 – 0.05
0.40
0.10
31 32
PIN 1
TOP MARK
1
2
3.45 0.10
(4-SIDES)
(UH) QFN 0102
0.200 REF
NOTE:
1. DRAWING PROPOSED TO INCLUDE JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
0.23
0.05
0.50 BSC
3856f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
39
LTC3856
TYPICAL APPLICATION
VIN
+
VIN
330pF
S
0.1µF
2.2Ω
2.68k
47pF
200Ω
VIN
200Ω
Q1
RJK0305DPB
S
S
CLKOUT
0.1µF
20k
S
FREQ
TG1
RUN
SW1
TK/SS
ITH
VFB
AVP
S
100pF
30.1k
LTC3856
INTVCC
ITEMP
DIFFP
0.1µF
CMDSH-3
INTVCC
100k
PGOOD
CMDSH-3
ISET
SW2
EXTVCC
BG2
ILIM
L2
0.22µH
INTVCC
0.1µF
4.7µF
6.3V
22µF
Q7
RJK0305DPB
TG2
BOOST2
330µF
2.5V
฀4
22µF
4.7µF
0.001Ω
Q8
RJK0330DPB
Q4
RJK0330DPB
SENSE2+
1nF
MODE
S
100µF
6.3V
+
฀2
VIN
Q3
RJK0305DPB
DIFFOUT
100Ω
GND
VOUT
1.5V/
50A
0.001Ω
Q6
RJK0330DPB
Q2
RJK0330DPB
DIFFN
INTVCC
L1
0.22µH
INTVCC
BOOST1
BG1
PHASMD
S
Q5
RJK0305DPB
1nF
SENSE1–
22µF
22µF
SENSE1+
PLLIN
100k
49.9Ω
VIN
180µF
16V
฀2
VIN
4.5V
TO 14V
PGOOD PGND SGND SENSE2–
200Ω
200Ω
S
10Ω
10Ω
S
S
VO_SNS–
VO_SNS+
3856 F19
Figure 19. 1.5V/50A Converter with AVP
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3829
3-Phase, Single Output, Synchronous Step-Down Controller
with Diffamp and DCR Temperature Compensation
Phase-Lockable Fixed 250kHz to 770kHz Frequency,
4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5V
LTC3860
Dual, Multiphase, Synchronous Step-Down DC/DC Controller
with Diffamp and Three-State Output Drive
Operates with Power Blocks, DRMOS Devices or External
MOSFETs, 3V ≤ VIN ≤ 24V, tON(MIN) = 20ns
LTC3855
Dual, Multiphase, Synchronous Step-Down DC/DC Controller
with Diffamp and DCR Temperature Compensation
Phase-Lockable Fixed Frequency 250kHz to 770kHz,
4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 12V
LTC3853
Triple Output, Multiphase, Synchronous Step-Down DC/DC
Controller, RSENSE or DCR Current Sensing and Tracking
Phase-Lockable Fixed 250kHz to 750kHz Frequency,
4V ≤ VIN ≤ 24V, VOUT3 Up to 13.5V
LTC3850/LTC3850-1/
LTC3850-2
Dual 2-Phase, High Eficiency, Synchronous Step-Down
Phase-Lockable Fixed 250kHz to 780kHz Frequency,
DC/DC Controller, RSENSE or DCR Current Sensing and Tracking 4V ≤ VIN ≤ 30V, 0.8V ≤ VOUT ≤ 5.25V
3856f
40 Linear Technology Corporation
LT 0510 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
฀LINEAR TECHNOLOGY CORPORATION 2010
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