SEL/SEU

SEL/SEU
SINGLE EVENT EFFECTS
TEST REPORT
Test Type:
Heavy Ions
Test facility:
RADEF/JYFL, FINLAND
Test Date:
August 2011
Part Types:
SN55LVDS31 & SN55LVDS32
Part Description:
High-Speed Differential Line Driver
High-Speed Differential Line Receiver
Part Manufacturer:
Texas Instruments
Issue
03
Date
September 15 2011
th
Texas Instruments PO No 4512186232 dated 24/05/2011
Hirex reference :
HRX/SEE/0369
Issue : 03
Written by :
M. Mazurek
Design Engineer
Authorized by:
F.X. Guerre
Study Manager
Date :
HIREX Engineering SAS au capital de 180 000 € - RCS Toulouse B 389 715 525
Siège social: 2 rue des Satellites - 31520 Toulouse
September 15th 2011
Hirex Engineering
Ref. :
Issue :
SEE Test Report
HRX/SEE/0369
03
RESULTS SUMMARY
Facility
RADEF, JYFL, Finland
Test date
August 2011
Device description
Part type:
Description:
Package:
Part dimensions:
SN55LVDS31
High-Speed Differential Line Driver
FP16
13,6 mm x 13,9 mm
Part type:
Description:
Receiver
Package:
Part dimensions:
SN55LVDS32
High-Speed Differential Line
FP16
12,32 mm x 12,4 mm
SEE Results
Two LVDS chains composed of SN55LVDS31 and SN55LVDS32 parts have been exposed over a LET range
from 10.08 to 54.95 MeV/(mg/cm²) at ambient temperature for SEU characterization.
In addition, tests with Xenon at 60 degrees and two different temperatures (80°C, 125°C) have been
performed for SEL evaluation.
SEL Results
No SEL was observed up to LET of 110 MeV/(mg/cm2) at 80°C and 125°C temperatures, a bias voltage
equal to 3.6V and a fluence of 1.0E+07 ions/cm² for both parts.
SEU Results
SN55LVDS31 Driver
No SEU event was observed up to LET of 55 MeV/(mg/cm2) at room temperature at receiver output, with a
bias voltage equal to 3.0V and a fluence of 1.0E+07 ions/cm².
SN55LVDS32 Receiver
Single event upsets were observed for SN55LVDS32 receiver. They can last up to 3 clock edges, but mainly
they stay during one clock edge. SEUs started to appear with Iron (LET of 18.84 MeV/(mg/cm2)).
SEU Cross-Section for SN55LVDS32 Receiver
The SEU cross-section reaches its highest value at 1.8E-05 cm2/device while the LET threshold is below 17
MeV/(mg/cm²).
SEU X-section/Device (cm²)
LVDS Receiver SN55LVDS32, SEU X-Section/Device
1.0E-04
LVDS Receiver SN55LVDS32
1.0E-05
1.0E-06
1.0E-07
1.0E-08
0
20
40
60
80
100
120
Eff LET (MeV/mg/cm²)
SN55LVDS32 Board 1, Room Temp.
SN55LVDS32 Board 2, Room Temp.
HRX/SEE/0369 Issue 03
SN55LVDS32 Board 1, 125°C
SN55LVDS32 Board 2, 125°C
SN55LVDS32 Board 1, 85°C
Weibull Fit
Page 2 / 21
S
W
x0
A
SEU Cross-Section/Device
1.94
31
17
1.8E-05
Hirex Engineering
SEE Test Report
Ref. :
Issue :
DOCUMENTATION CHANGE NOTICE
Issue
Date
Page
01
15/09/2011
All
02
26/09/2011
03
05/10/2011
Change Item
Original issue
6, 7, 8, 10, TI Comments
12, 17, 20, 21
2,15
TI Comments
Contributors to this work:
Maria Mazurek
Bertrand Forgerit
HRX/SEE/0369 Issue 03
Hirex Engineering
Hirex Engineering
Page 3 / 21
HRX/SEE/0369
03
Hirex Engineering
SEE Test Report
Ref. :
Issue :
HRX/SEE/0369
03
SEE TEST REPORT
TABLE OF CONTENTS
1
INTRODUCTION.....................................................................................................................................................5
2
APPLICABLE AND REFERENCE DOCUMENTS .............................................................................................5
2.1
2.2
3
DEVICE INFORMATION.......................................................................................................................................6
3.1
3.2
3.3
3.4
4
APPLICABLE DOCUMENTS ....................................................................................................................................5
REFERENCE DOCUMENTS .....................................................................................................................................5
DEVICE DESCRIPTION ...........................................................................................................................................6
SAMPLE IDENTIFICATION ......................................................................................................................................6
DIE MICROSECTION ..............................................................................................................................................8
EFFECTIVE LET CALCULATION ..........................................................................................................................10
TEST SET-UP .........................................................................................................................................................11
4.1
4.2
4.3
4.4
TEST SYSTEM .....................................................................................................................................................11
LVDS TEST PRINCIPLE .......................................................................................................................................11
TEST CONDITIONS ..............................................................................................................................................12
TEST CONFIGURATION ........................................................................................................................................12
5
RADEF TEST FACILITY .....................................................................................................................................13
6
SEE TEST RESULTS .............................................................................................................................................15
6.1
SEL....................................................................................................................................................................15
6.2
SEU ...................................................................................................................................................................15
6.2.1
Driver SN55LVDS31 ................................................................................................................................15
6.2.2
Receiver SN55LVDS32 ............................................................................................................................15
6.3
SUPPLY CURRENT MONITORING EXAMPLE ..........................................................................................................17
6.4
THE TOTAL ACCUMULATED IONIZING DOSE ......................................................................................................17
7
GLOSSARY.............................................................................................................................................................18
8
DETAILED RESULTS PER RUN ........................................................................................................................19
8.1
DETAILED RUN TABLE ........................................................................................................................................20
LIST OF FIGURES
Figure 1: Device identification for SN55LVDS31 & SN55LVDS32 parts ..................................................... 7
Figure 2: Die microsection for SN55LVDS31 part......................................................................................... 8
Figure 3: Die microsection for SN55LVDS32 part......................................................................................... 9
Figure 4: Effective LET definition for min and max cases......................................................................... 10
Figure 5: LVDS chain test set-up.................................................................................................................. 11
Figure 6: Test conditions for the LVDS Driver-Receiver chain ................................................................. 12
Figure 7: Unity gain configuration ............................................................................................................... 12
Figure 8: LVDS Driver-Receiver chain test configuration.......................................................................... 12
Figure 9: Hardware setup .............................................................................................................................. 12
Figure 10: RADEF, SEU Cross-section/device for SN55LVDS32 part, JYFL August 2011...................... 15
Figure 11: RADEF, Weibull parameters for the SN55LVDS32 part, JYFL August 2011........................... 15
Figure 12: RADEF, SEU statistics, JYFL August 2011 ............................................................................... 16
Figure 13: RADEF, Example of UI plot for SEL test, JYFL August 2011................................................... 17
LIST OF TABLES
Table 1: Effective LET values at active DUT area computed with SRIM2006 .......................................... 10
Table 2: RADEF, Used ion and features thereof, JYFL November 2011................................................... 14
Table 3: RADEF, Run Table for SN55LVDS31 and SN55LVDS32 parts, JYFL August 2011 ................... 20
Table 4: RADEF, SEU Statistics Table for SN55LVDS32 part, JYFL August 2011 ................................... 21
HRX/SEE/0369 Issue 03
Page 4 / 21
Hirex Engineering
1
SEE Test Report
Ref. :
Issue :
HRX/SEE/0369
03
Introduction
This report presents the results of Heavy Ion test program carried out on Texas Instruments HighSpeed Differential Line Driver and High-Speed Differential Line Receiver referenced SN55LVDS31
and SN55LVDS32.
Two devices of each type were heavy ion tested at RADEF, University of Jyväskylä, Department of
Physics, Jyväskylä, Finland in August 2011.
This work was performed for Texas Instruments PO No 4512186232 dated 24/05/2011
2
2.1
2.2
Applicable and Reference Documents
Applicable Documents
AD-1. Datasheet sn55lvds31-sp ; SLLS261L-JULY 1997; REVIDED JULY 2007
AD-2. Datasheet sn55lvds32-sp ; SLLS262Q-JULY 1997; REVISED JULY2007
Reference Documents
RD-1. Single Event Effects Test method and Guidelines ESA/SCC basic specification No 25100
HRX/SEE/0369 Issue 03
Page 5 / 21
Hirex Engineering
Ref. :
Issue :
SEE Test Report
HRX/SEE/0369
03
3
DEVICE INFORMATION
3.1
Device description
The SN55LVDS31 is differential line driver that implements the electrical characteristics of lowvoltage differential signaling (LVDS).
The SN55LVDS32 is a differential line receiver that implements the electrical characteristics of lowvoltage differential signaling (LVDS).
Part Type:
Manufacturer:
Package:
Top Marking:
Die dimensions:
3.2
SN55LVDS31
Texas Instruments
FP16
2D-R 1110A
5962-97621 01VFA
SNV55LVDS31W
THA
13,6 mm x 13,9 mm
Part Type:
Manufacturer:
Package:
Top Marking:
Die dimensions:
SN55LVDS32
Texas Instruments
FP16
3B-R 1112A
5962-97622 01VFA
SNV55LVDS32W
THA
12,32 mm x 12,4 mm
Sample identification
Texas Instruments delivered five SN55LVDS31 and five SN55LVDS32 devices with the lot datecodes
respectively “1110A” and “1112A”. Four parts of each type were prepared to be tested to heavy ions.
A die size is small comparing to the device cavity, so package shadowing is not an obstacle.
The test was performed on two samples of each type.
Photo 1 - Top Marking (SN55LVDS31)
Photo 2 – Top Marking (SN55LVDS32)
Photo 3 –Die full view (SN55LVDS31)
Photo 4 –Die full view (SN55LVDS32)
HRX/SEE/0369 Issue 03
Page 6 / 21
Hirex Engineering
SEE Test Report
Ref. :
Issue :
HRX/SEE/0369
03
Photo 5 – Die Marking (SN55LVDS31)
Photo 6 – Die Marking (SN55LVDS32)
Photo 7 – Die Marking (SN55LVDS31)
Photo 8 – Die Marking (SN55LVDS32)
Photo 9 – Device Opening (SN55LVDS31)
Photo 10 – Device Opening (SN55LVDS32)
Figure 1: Device identification for SN55LVDS31 & SN55LVDS32 parts
HRX/SEE/0369 Issue 03
Page 7 / 21
Hirex Engineering
3.3
Ref. :
Issue :
SEE Test Report
HRX/SEE/0369
03
Die microsection
Die microsections were performed for SN55LVDS31 part and SN55LVDS32 part in order to check
ion penetration.
Dead layer in each die was measured and will be taken into account for computing the effective LET
value.
SN55LVDS31
Layer ID
Material
Thickness
Passivation
Si3N4
0.98µm
Metal 2
Al (Cu/Ti traces?)
TiW liner
0.63µm
0.23µm
Inter Layer
Dielectric 2
Deposited SiO2
SOG - SiO2
0.35µm
0.04µm to 1µm
Metal 1
TiW ARC layer
Al (Cu/Ti Traces?)
TiW liner
0.08µm
0.5µm
0.29µm
Inter Layer
Dielectric 1
Deposited SiO2
SOG - SiO2
Deposited SiO2
SOG - SiO2
Deposited SiO2
0.37µm
0.1µm to 0.3µm
0.1µm
0.1µm to 0.25µm
0.3µm
Poly gate 1
Poly 2
Silicide TiSi
Polysilicon
Polysilicon
0.11µm
0.23µm
0.3µm
Gate oxide
Under LD
Under LD
Field oxide
Thermal SiO2
0.55µm
Passivation
Metal 2
ILD 2
SOG
Metal1
ILD 1
Poly
D/S
Metal 1
D/S
Metal 1
Minimum CD’s
transistor
Figure 2: Die microsection for SN55LVDS31 part
HRX/SEE/0369 Issue 03
Page 8 / 21
Hirex Engineering
Ref. :
Issue :
SEE Test Report
HRX/SEE/0369
03
SN55LVDS32
Passivation
Metal 2
ILD 2
SOG
Metal1
ILD 1
Layer ID
Material
Thickness
Passivation
Si3N4
1µm
Metal 2
Al (Cu/Ti traces?)
TiW liner
0.6µm
0.28µm
Inter Layer
Dielectric 2
Deposited SiO2
SOG - SiO2
0.45µm
0.1µm to 2.2µm
Metal 1
TiW ARC layer
Al (Cu/Ti
Traces?)
TiW liner
0.08µm
0.45µm
0.38µm
Inter Layer
Dielectric 1
Deposited SiO2
SOG - SiO2
Deposited SiO2
SOG - SiO2
Deposited SiO2
0.32µm
0.1µm to 0.2µm
0.07µm
0.1µm to 0.25µm
0.3µm
Poly gate
Silicide TiSi
Polysilicon
0.07µm
0.20µm
Gate oxide
Under LD
Under LD
Field oxide
Thermal SiO2
0.56µm
Poly
Field oxide
D/S
Contact
Minimum CD’s
transistor
Figure 3: Die microsection for SN55LVDS32 part
HRX/SEE/0369 Issue 03
Page 9 / 21
D/S
Contact
Hirex Engineering
3.4
HRX/SEE/0369
Ref. :
Issue :
SEE Test Report
03
Effective LET calculation
Taking into account passivation, metals, and dielectric layers, effective LET values at active DUT
1
surface are computed with the use of SRIM2006 .
Min Case
Max Case
LET at DUT surface
LET at DUT surface
Passivation Layer
Passivation Layer
Metal 2 Layer
Dielectric Layer
Dielectric Layer
Metal 1 Layer
Effective LET
Effective LET
Effective LET
Active Area
Dielectric Layer
Active Area
Figure 4: Effective LET definition for min and max cases
Min Case
Max Case
Bragg Peak
Used ions
Ion energy
LET @ DUT surface (MeV)
Eff. LET (MeV)
Eff. LET (MeV)
Eff. LET(MeV)
Argon
(362MeV)
10.2
10.5
10.6
18.7
Iron
(504 MeV)
18.5
19.3
19.7
29
Krypton
(736MeV)
32.2
33.6
34
40
Xenon
(1157MeV)
60
62.4
62.9
69
Table 1: Effective LET values at active DUT area computed with SRIM2006
1
http://www.srim.org/SRIM/SRIMLEGL.htm
HRX/SEE/0369 Issue 03
Page 10 / 21
Xenon @60
(1157MeV)
120
124.8
125.8
138
Hirex Engineering
Ref. :
Issue :
SEE Test Report
4
Test Set-up
4.1
Test system
Figure 5 shows the principle of the Heavy Ion test system.
HRX/SEE/0369
03
The test system is based on a Virtex5 FPGA (Xilinx). It runs at 50MHz. The test board has 168 I/Os
which can be configured using several I/O standards.
The test board includes the voltage/current monitoring and the latch-up management of the DUT
power supplies up to 24 independent channels.
A temperature control system is used to heat the DUT. Tests are executed at three different
temperatures.
The communication between the test chamber and the controlling computer is effectively done by a
100 Mbit/s Ethernet link which safely enables high speed data transfer.
External to Chamber
Chamber Wall
Internal to Chamber
Temperature
Control system
Voltage/Current
Monitoring
External Power
Supplies
COMPUTER
Graphical
User
Interface
LAN
DRIVER
VIRTEX 5
FPGA
I/O
Interface
DUTs
Daughter board
4- Chanel
400MHz Digitizer
BEAM COUNTER
Figure 5: LVDS chain test set-up
4.2
LVDS Test principle
In order to test the LVDS chain (driver + receiver) a daughter board is designed. One chain is placed
on one daughter board. Heavy ion beam is focused at first on driver part and then on receiver part.
Checkerboard and inverted checkerboard patterns are applied to DUT inputs with the frequency of
25MHz.
SEL
SEL detection is performed by monitoring the DUT supply current. When a SEL occurs, then the
transceiver is switched off during 1 second, and the SEL event is registered in the log file.
The SEL threshold can be adjusted during the test, but in general it is adjusted before starting the
test. During all irradiation time, the supply currents of each DUT are measured.
SEU
SEU detection is performed by comparing the outputs of the receiver SN55LVDS32 with data applied
on SN55LVDS31 inputs with a frequency of 50MHz. If a difference occurs then SEU event is
registered in the Summary.xls file.
HRX/SEE/0369 Issue 03
Page 11 / 21
Hirex Engineering
4.3
HRX/SEE/0369
Ref. :
Issue :
SEE Test Report
03
Test conditions
Runs are performed with selected ions: 40Ar+12, 56Fe+15, 82Kr+22, 131Xe35 and tilt angles set at
45 and 60 deg.
The tests are done at three different temperatures: ambient chamber temperature, 80°C and 125°C.
All values of the supply voltage are presented in Figure 6.
Device
Test
Type
Vcc (V)
Input
Temp.
Condition number
SN55LVDS31
SN55LVDS32
SEU
+3.0V
25MHz
Checkerboard Patter
AT
1
SN55LVDS31
SN55LVDS32
SEL
3.6V
25MHz
Checkerboard Patter
85C°
2
SN55LVDS31
SN55LVDS32
SEL
3.6V
25MHz
Checkerboard Patter
125C°
3
Figure 6: Test conditions for the LVDS Driver-Receiver chain
4.4
Test configuration
SN55LVDS31 and SN55LVDS32 are connected together forming LVDS driver-receiver chain. During
each run only one device of LVDS chain is irradiated. The beam source is collimated to be
compatible with the size of DUT. First ion beam is focused on driver, than on receiver.
SN55LVDS31
DUT1
Input 1
Input 2
Direction of transmission for LVDS Chain
1Y
1A
1Z
2Z
Input 3
1Y
100Ω
2Y
2A
SN55LVDS32
DUT2
2Y
100Ω
3Z
100Ω
4Y
Input 4
4A
4Z
Output 1
2Y
Output 2
3Y
Output 3
4Y
Output 4
2Z
3Y
3A
1Y
1Z
3Z
4Y
100Ω
Figure 7: Unity gain configuration
4Z
Figure 8: LVDS Driver-Receiver chain test configuration
Figure 9: Hardware setup
HRX/SEE/0369 Issue 03
Page 12 / 21
Hirex Engineering
5
SEE Test Report
Ref. :
Issue :
HRX/SEE/0369
03
RADEF Test Facility
Test at the cyclotron accelerator was performed at University of Jyvaskyla (JYFL) (Finland) under
HIREX Engineering responsibility.
The facility includes a special beam line dedicated to irradiation studies of semiconductor
components and devices. It consists of a vacuum chamber including component movement
apparatus and the necessary diagnostic equipment required for the beam quality and intensity
analysis.
The cyclotron is a versatile, sector-focused accelerator of beams from hydrogen to xenon equipped
with three external ion sources: two electron cyclotron resonance (ECR) ion sources designed for
high-charge-state heavy ions, and a multicusp ion source for intense beams of protons. The ECR's
are especially valuable in the study of single event effects (SEE) in semiconductor devices. For heavy
ions, the maximum energy attainable can be determined using the formula
130 Q2/M,
where Q is the ion charge state and M is the mass in Atomic Mass Units.
Test chamber
Irradiation of components is performed in a vacuum chamber with an inside diameter of 75 cm and a
height of 81 cm.
The vacuum in the chamber is achieved after 15 minutes of pumping, and the inflation takes only a
few minutes. The position of the components installed in the linear movement apparatus inside the
chamber can be adjusted in the X, Y and Z directions. The possibility of rotation around the Y-axis is
provided by a round table. The free movement area reserved for the components is 25 cm x 25 cm,
which allows one to perform several consecutive irradiations for several different components without
breaking the vacuum.
The assembly is equipped with a standard mounting fixture. The adapters required accommodating
the special board configurations and the vacuum feed-throughs can also be made in the laboratory’s
workshops. The chamber has an entrance door, which allows rapid changing of the circuit board or
individual components.
A CCD camera with a magnifying telescope is located at the other end of the beam line to determine
accurate positioning of the components. The coordinates are stored in the computer’s memory
allowing fast positioning of various targets during the test.
Beam quality control
For measuring beam uniformity at low intensity, a CsI(Tl) scintillator with a PIN-type photodiode
readout is fixed in the mounting fixture. The uniformity is measured automatically before component
irradiation and the results can be plotted immediately for more detailed analysis.
A set of four collimated PIN-CsI(Tl) detectors is located in front of the beam entrance. The detectors
are operated with step motors and are located at 90 degrees with respect to each other. During the
irradiation and uniformity scan they are set to the outer edge of the beam in order to monitor the
stability of the homogeneity and flux.
Two beam wobblers and/or a 0.5 microns diffusion Gold foil can be used to achieve good beam
homogeneity. The foil is placed 3 m in front of the chamber. The wobbler-coils vibrate the beam
horizontally and vertically, the proper sweeping area being attained with the adjustable coil-currents.
Dosimetry
The flux and intensity dosimeter system contains a Faraday cup, several collimators, a scintillation
counter and four PIN-CsI(Tl) detectors. Three collimators of different size and shape are placed 25
cm in front of the device under test. They can be used to limit the beam to the active area to be
studied.
At low fluxes a plastic scintillator with a photomultiplier tube is used as an absolute particle counter. It
is located behind the vacuum chamber and is used before the irradiation to normalize the count rates
of the four PIN-CsI(Tl) detectors.
JYFL facility is an ESA qualified heavy ion facility. Compliance for beam uniformity and fluence
dosimetry to ESA/SCC 25100 requirements are under JYFL responsibility.
For the present test, beam rectangular collimator was set to 20mm by 40 mm.
HRX/SEE/0369 Issue 03
Page 13 / 21
Hirex Engineering
SEE Test Report
Ref. :
Issue :
HRX/SEE/0369
03
Used ions
The RADEF ion used is listed in the table below.
Ion
Energy (MeV)
LET (MeV.cm²/mg)
Range (Si) (µm)
40Ar+12
372
10,1
118
56Fe+15
523
18,5
97
82Kr+22
768
30,2
94
131Xe+35
1217
55,3
89
Table 2: RADEF, Used ion and features thereof, JYFL November 2011
HRX/SEE/0369 Issue 03
Page 14 / 21
Hirex Engineering
6
Ref. :
Issue :
SEE Test Report
HRX/SEE/0369
03
SEE Test Results
Two LVDS chains composed of SN55LVDS31 and SN55LVDS32 parts have been exposed over a
LET range from 10.08 to 54.95 MeV/(mg/cm²) at ambient temperature for SEU characterization.
In addition, tests with Xenon at 60 degrees and two different temperatures (80°C, 125°C) have been
performed for SEL evaluation.
Detailed results per run are presented in Table 3 and Table 4.
6.1
SEL
No SEL was observed up to LET of 110 MeV/(mg/cm2) at 80°C and 125°C temperatures, a bias
voltage equal to 3.6V and a fluence of 1.0E+07 ions/cm² for both parts.
6.2
SEU
Single event upsets were observed for SN55LVDS32 receiver. They can last up to 3 clock edges, but
mainly they stay during one clock edge.
6.2.1
Driver SN55LVDS31
No SEU event was observed up to LET of 55 MeV/(mg/cm2) at room temperature, a bias voltage
equal to 3.0V and a fluence of 1.0E+07 ions/cm².
6.2.2
Receiver SN55LVDS32
The single event transients started to appear with Iron (LET of 18.84 MeV/(mg/cm2)).
SEU Cross-Section for SN55LVDS32 device
The SEU cross-section reaches its highest value at 1.8E-05 cm2/device while the LET threshold is
below 17 MeV/(mg/cm²).
SEU X-section/Device (cm²)
LVDS Receiver SN55LVDS32, SEU X-Section/Device
1.0E-04
1.0E-05
1.0E-06
1.0E-07
1.0E-08
0
20
40
60
80
100
120
Eff LET (MeV/mg/cm²)
SN55LVDS32 Board 1, Room Temp.
SN55LVDS32 Board 2, Room Temp.
SN55LVDS32 Board 1, 125°C
SN55LVDS32 Board 2, 125°C
SN55LVDS32 Board 1, 85°C
Weibull Fit
Figure 10: RADEF, SEU Cross-section/device for SN55LVDS32 part, JYFL August 2011
LVDS Receiver SN55LVDS32
S
W
x0
A
SEU Cross-Section/Device
1.94
31
17
1.8E-05
Figure 11: RADEF, Weibull parameters for the SN55LVDS32 part, JYFL August 2011
HRX/SEE/0369 Issue 03
Page 15 / 21
Hirex Engineering
Ref. :
Issue :
SEE Test Report
SEU Statistics for SN55LVDS32 device
All runs and all devices are taken together to calculate SEU statistics.
Total Number of Errors
SN55LVDS32 Receiver
Bit flipping Statistics
500
400
300
200
100
0
1->0
0->1
Total Number of Errors
SN55LVDS32 Receiver
Error Duration Statistics
1000
100
10
1
1 clk edge
2 clk edges
3 clk edges
Total Number of Errors
SN55LVDS32 Receiver
Error Output Statistics
250
200
150
100
50
0
Output 4
Output 3
Output 2
Output1
Figure 12: RADEF, SEU statistics, JYFL August 2011
HRX/SEE/0369 Issue 03
Page 16 / 21
HRX/SEE/0369
03
Hirex Engineering
6.3
Ref. :
Issue :
SEE Test Report
HRX/SEE/0369
03
Supply current monitoring example
Supply current and supply voltage were monitored all along test sequence. UI plot for run number 36
is presented as an example.
One can see that current did not exceed the SEL threshold of 50mA at any time. A constant offset
could be present in the current I2 value due to our internal A/D converter, but what is important is the
variation.
Figure 13: RADEF, Example of UI plot for SEL test, JYFL August 2011
6.4
The Total Accumulated Ionizing Dose
Here below a total accumulated ionizing dose for each tested sample.
Board
Part
Total Ionizing Dose
Board #1
Board #1
Board #2
Board #2
SN55LVDS31
SN55LVDS32
SN55LVDS31
SN55LVDS32
72 krads
72 krads
72 krads
72 krads
HRX/SEE/0369 Issue 03
Page 17 / 21
Hirex Engineering
7
SEE Test Report
Ref. :
Issue :
HRX/SEE/0369
03
Glossary
Most of the definitions here below are from JEDEC standard JESD89A
DUT: Device under test.
Fluence (of particle radiation incident on a surface): The total amount of particle radiant energy
incident on a surface in a given period of time, divided by the area of the surface.
In this document, Fluence is expressed in ions per cm2.
Flux: The time rate of flow of particle radiant energy incident on a surface, divided by the area of that
surface.
In this document, Flux is expressed in ions per cm2*s.
Single-Event Effect (SEE): Any measurable or observable change in state or performance of a
microelectronic device, component, subsystem, or system (digital or analog) resulting from a single
energetic particle strike.
Single-event effects include single-event upset (SEU), multiple-bit upset (MBU), multiple-cell upset
(MCU), single-event functional interrupt (SEFI), single-event latch-up (SEL.
Single-Event Upset (SEU): A soft error caused by the transient signal induced by a single energetic
particle strike.
Single-Event Latch-up (SEL): An abnormal high-current state in a device caused by the passage of
a single energetic particle through sensitive regions of the device structure and resulting in the loss of
device functionality.
SEL may cause permanent damage to the device. If the device is not permanently damaged, power
cycling of the device (off and back on) is necessary to restore normal operation.
An example of SEL in a CMOS device is when the passage of a single particle induces the creation
of parasitic bipolar (p-n-p-n) shorting of power to ground.
Single-Event Latch-up (SEL) cross-section: the number of events per unit fluence. For chip SEL
cross-section, the dimensions are cm2 per chip.
Error cross-section: the number of errors per unit fluence. For device error cross-section, the
dimensions are cm2 per device. For bit error cross-section, the dimensions are cm2 per bit.
Tilt angle: tilt angle, rotation axis of the DUT board is perpendicular to the beam axis; roll angle,
board rotation axis is parallel to the beam axis
Weibull Function:
F(x) = A (1- exp{-[(x-x0)/W]s})
x = effective LET in MeV-cm2 /milligram;
F(x) = SEE cross-section in square-cm2/bit;
A = limiting or plateau cross-section;
x0 = onset parameter, such that F(x) = 0 for x < x0;
W = width parameter;
s = a dimensionless exponent.
HRX/SEE/0369 Issue 03
Page 18 / 21
Hirex Engineering
8
SEE Test Report
Ref. :
Issue :
HRX/SEE/0369
03
Detailed results per run
Hirex RUN
JYFL RUN
Test SEL/SEU
Board #
DUT Number
Pattern
VCC
Temperature
Ion
Energy
Tilt Angle
Range
Base LET
Eff LET
Fluence
Flux
Beam Time
Dose
SEL Events
SEU Events
SEU on Output 4
SEU on Output 3
SEU on Output 2
SEU on Output 1
SEL X-Section
SEU X-Section
HRX/SEE/0369 Issue 03
Hirex test run number
RADEF test run number
Test Type
Number of used board
DUT irradiated during the run
Pattern applied during the runl
DUT logic supply voltage (V)
DUT temperature (°C)
Ion specie
Ion energy (MeV)
DUT tilt angle with beam direction (deg)
Ion range (micron)
Linear Energy Transfer (MeV/(mg/cm²))
LET / (cos(tilt angle) (MeV/(mg/cm²))
-2
Cumulated number of ions over the test run (cm )
-2
-1
Effective Fluence (cm x s )
Time of DUT exposure to the beam (s)
1.6E-19 *1.0E+14 * EffLET*Fluence
Number of observed SELs
Number of observed SEUs
Number of SEUs observed on Output 4 of each DUT
Number of SEUs observed on Output 3 of each DUT
Number of SEUs observed on Output 2 of each DUT
Number of SEUs observed on Output 1 of each DUT
SEL Crosse Section for total number of SELs (cm2)
SEU Crosse Section for total number of SEUs (cm2)
Page 19 / 21
HRX/SEE/0369 Issue 03
0
0
RT
RT
RT
RT
RT
RT
RT
RT
RT 131Xe+35 1217
RT 131Xe+35 1217
RT 131Xe+35 1217
RT 131Xe+35 1217
6 SEU 2 SN55LVDS31 CB 3.0V
7 SEU 1 SN55LVDS32 CB 3.0V
8 SEU 1 SN55LVDS31 CB 3.0V
9 SEU 1 SN55LVDS32 CB 3.0V
10
11
13
14 10 SEU 1 SN55LVDS31 CB 3.0V
16 11 SEU 2 SN55LVDS31 CB 3.0V
17 12 SEU 2 SN55LVDS32 CB 3.0V
18 13 SEU 2 SN55LVDS32 CB 3.0V
19 14 SEU 2 SN55LVDS31 CB 3.0V
21 15 SEU 1 SN55LVDS31 CB 3.0V
22 16 SEU 1 SN55LVDS32 CB 3.0V
23 17 SEU 1 SN55LVDS32 CB 3.0V
24 18 SEU 1 SN55LVDS31 CB 3.0V
26 19 SEU 2 SN55LVDS31 CB 3.0V
27 20 SEU 2 SN55LVDS32 CB 3.0V
29 21 SEL 2 SN55LVDS32 CB 3.6V +85 131Xe+35 1217
Beam Time
Flux
Fluence
Eff LET
Base LET[MeV/(mg*cm2)]
Range [µm]
0
0
0
40 31 SEL 1 SN55LVDS31 CB 3.6V +85 131Xe+35 1217
55.0 110.0 1.0E+07 1.05E+04 956 1.76E+04 0
55.0 55.0 1.0E+07 1.96E+04 509 8.80E+03 0
42 33 SEL 1 SN55LVDS31 CB 3.6V +125 131Xe+35 1217 60 89
0
0
43 34 SEL 1 SN55LVDS31 CB 3.6V +125 131Xe+35 1217
44 35 SEL 1 SN55LVDS32 CB 3.6V +125 131Xe+35 1217
24
0
0
28
0
0
0
0
0
0
0
0
0
0
0
0
0
0
50
0
0
65
4
6
0
0
0
1
0
0
0
0
0
0
0
0
SEU on Output 2
0
0
48
0
0
27
4
4
2
0
0
0
0
0
0
0
0
0
0
0
5
0
0
0
0
55.0 110.0 1.0E+07 1.04E+04 965 1.76E+04 0 112 28
20
0
0
0
0
4
0
30
7
0
0
0
0
4
25
36
2
0
30
5
0
0
0
0
9
23
30
6
0
24
3
0
0
0
0
6
20
45
8
Page 20 / 21
Table 3: RADEF, Run Table for SN55LVDS31 and SN55LVDS32 parts, JYFL August 2011
45 36 SEL 1 SN55LVDS32 CB 3.6V +125 131Xe+35 1217 60 89
89
55.0 55.0 1.0E+07 1.98E+04 504 8.80E+03 0
55.0 110.0 1.0E+07 1.56E+04 641 1.76E+04 0
41 32 SEL 1 SN55LVDS31 CB 3.6V +85 131Xe+35 1217 60 89
89
55.0 55.0 1.0E+07 2.63E+04 380 8.80E+03 0
89
23
18
55.0 55.0 1.0E+07 2.13E+04 469 8.80E+03 0
89
86
0
3
39 30 SEL 1 SN55LVDS32 CB 3.6V +85 131Xe+35 1217
19
55.0 110.0 1.0E+07 1.49E+04 670 1.76E+04 0
55.0 55.0 1.0E+07 2.38E+04 420 8.80E+03 0
55.0 55.0 1.0E+07 2.59E+04 386 8.80E+03 0
55.0 110.0 1.0E+07 1.28E+04 779 1.76E+04 0 143 32
89
89
38 29 SEL 1 SN55LVDS32 CB 3.6V +85 131Xe+35 1217 60 89
0
0
0
36 28 SEL 2 SN55LVDS32 CB 3.6V +125 131Xe+35 1217 60 89
0
35 27 SEL 2 SN55LVDS32 CB 3.6V +125 131Xe+35 1217
0
0
3
4
0
SEU on Output 3
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.50E-05
-
-
1.40E-05
1.10E-06
-
-
1.70E-06
2.00E-07
-
-
1.00E-07
HRX/SEE/0369
03
SEU on Output 1
-
-
-
-
-
-
-
-
-
-
-
1.1E-05
2.0E-06
-
-
-
-
2.3E-06
8.6E-06
1.4E-05
1.90E-06
-
Due to the temperature increase acquisition
time tuning for SEU events was needed;
These runs are not used for SEU statistics
and SEU cross-section
55.0 110.0 1.0E+07 1.45E+04 690 1.76E+04 0
55.0 55.0 1.0E+07 2.72E+04 367 8.80E+03 0
55.0 110.0 1.0E+07 1.34E+04 748 1.76E+04 0
34 26 SEL 2 SN55LVDS31 CB 3.6V +125 131Xe+35 1217
0
0
55.0 55.0 1.0E+07 2.24E+04 447 8.80E+03 0 150 28
55.0 55.0 1.0E+07 2.72E+04 368 8.80E+03 0
55.0 55.0 1.0E+07 2.62E+04 381 8.80E+03 0
89
33 25 SEL 2 SN55LVDS31 CB 3.6V +125 131Xe+35 1217 60 89
0
3
55.0 55.0 1.0E+07 1.40E+04 716 8.80E+03 0 140 20
32 24 SEL 2 SN55LVDS31 CB 3.6V +85 131Xe+35 1217 60 89
0
0
0
30.4 30.4 1.0E+07 3.21E+04 312 4.86E+03 0 11
30.4 30.4 1.0E+07 3.03E+04 330 4.86E+03 0
30.4 30.4 1.0E+07 3.24E+04 309 4.86E+03 0
0
0
0
0
0
0
0
0
0
0
0
SEU on Output 4
2 0
0
0
1
0
0
0
0
0
0
0
0
SEU Events
30.4 30.4 1.0E+07 2.85E+04 351 4.86E+03 0 17
18.8 18.8 1.0E+07 2.40E+04 416 3.01E+03 0
18.8 18.8 1.0E+07 2.78E+04 360 3.01E+03 0
18.8 18.8 1.0E+07 2.33E+04 430 3.01E+03 0
18.8 18.8 1.0E+07 1.32E+04 760 3.01E+03 0
31 23 SEL 2 SN55LVDS31 CB 3.6V +85 131Xe+35 1217
89
89
89
89
94
94
94
94
97
97
97
97
55.0 55.0 1.0E+07 2.42E+04 414 8.80E+03 0
0
0
0
0
0
0
0
0
0
0
0
55.0 110.0 1.0E+07 1.41E+04 709 1.76E+04 0
768
768
768
768
523
523
523
523
372 45 118 10.1 14.3 1.0E+07 2.00E+04 501 2.29E+03 0
372 45 118 10.1 14.3 1.0E+07 2.33E+04 429 2.29E+03 0
372 45 118 10.1 14.3 1.0E+07 2.09E+04 479 2.29E+03 0
372 45 118 10.1 14.3 1.0E+07 1.57E+04 636 2.29E+03 0
0 118 10.1 10.1 1.0E+06 4.29E+03 233 1.62E+02 0
0 118 10.1 10.1 1.0E+06 4.48E+03 223 1.62E+02 0
0 118 10.1 10.1 1.0E+06 6.41E+03 156 1.62E+02 0
89
82Kr+22
82Kr+22
82Kr+22
82Kr+22
56Fe+15
56Fe+15
56Fe+15
56Fe+15
40Ar+12
40Ar+12
40Ar+12
Dose
30 22 SEL 2 SN55LVDS32 CB 3.6V +85 131Xe+35 1217 60 89
RT
RT
RT
40Ar+12
Ref. :
Issue :
SEL Events
0 118 10.1 10.1 1.0E+06 4.15E+03 241 1.62E+02 0
8
RT
372
372
372
372
5 SEU 2 SN55LVDS32 CB 3.0V
40Ar+12
40Ar+12
40Ar+12
40Ar+12
7
RT
RT
RT
RT
4 SEU 2 SN55LVDS32 CB 3.0V
Test SEL/SEU
5
Board
3 SEU 2 SN55LVDS31 CB 3.0V
DUT Number
4
Pattern
2 SEU 1 SN55LVDS31 CB 3.0V
Vcc
1 SEU 1 SN55LVDS32 CB 3.0V
Temperature
2
Ion
1
Energy [MeV]
HIREX RUN
Detailed run table
Tilt
JYFL RUN
8.1
SEE Test Report
SEL X-Section
Hirex Engineering
SEU X-Section/Device
HRX/SEE/0369 Issue 03
Hirex Engineering
1
0
0
2
17
0
0
11
3 SEU 2 SN55LVDS31 40Ar+12
4 SEU 2 SN55LVDS32 40Ar+12
5 SEU 2 SN55LVDS32 40Ar+12
6 SEU 2 SN55LVDS31 40Ar+12
7 SEU 1 SN55LVDS32 40Ar+12
8 SEU 1 SN55LVDS31 40Ar+12
9 SEU 1 SN55LVDS32 56Fe+15
HIREX RUN
7
8
10
11
13
14 10 SEU 1 SN55LVDS31 56Fe+15
16 11 SEU 2 SN55LVDS31 56Fe+15
17 12 SEU 2 SN55LVDS32 56Fe+15
18 13 SEU 2 SN55LVDS32 82Kr+22
19 14 SEU 2 SN55LVDS31 82Kr+22
21 15 SEU 1 SN55LVDS31 82Kr+22
22 16 SEU 1 SN55LVDS32 82Kr+22
SEU on Output 4
SEU on Output 3
0
26 19 SEU 2 SN55LVDS31 131Xe+35
0
0
0
0
0
0
0
0
0
0
2
0
0
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
10
2
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
17
2
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
0
42 33 SEL 1 SN55LVDS31 131Xe+35
43 34 SEL 1 SN55LVDS31 131Xe+35
44 35 SEL 1 SN55LVDS32 131Xe+35 20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
20
0
0
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
0
0
3
Page 21 / 21
Table 4: RADEF, SEU Statistics Table for SN55LVDS32 part, JYFL August 2011
112
0
0
0
0
45 36 SEL 1 SN55LVDS32 131Xe+35 112 28 30 30 24 63 49
5
0
0
0
0
20
7
0
0
0
0
3 10 10
0
0
0
23
0
14
0
9
41 32 SEL 1 SN55LVDS31 131Xe+35
6
40 31 SEL 1 SN55LVDS31 131Xe+35
9
4
39 30 SEL 1 SN55LVDS32 131Xe+35 23
4
86
19
0
9
143
8 10
18 25 23 20 35 51
6
38 29 SEL 1 SN55LVDS32 131Xe+35 86
2
0
These runs are not applicable
for SEU statistics
127
0
0
36 28 SEL 2 SN55LVDS32 131Xe+35 143 32 36 30 45 70 73
0
3
0
35 27 SEL 2 SN55LVDS32 131Xe+35 19
34 26 SEL 2 SN55LVDS31 131Xe+35
33 25 SEL 2 SN55LVDS31 131Xe+35
32 24 SEL 2 SN55LVDS31 131Xe+35
31 23 SEL 2 SN55LVDS31 131Xe+35
30 22 SEL 2 SN55LVDS32 131Xe+35
29 21 SEL 2 SN55LVDS32 131Xe+35
27 20 SEU 2 SN55LVDS32 131Xe+35 150 28 24 50 48 76 100
0
24 18 SEU 1 SN55LVDS31 131Xe+35
4
0
0
4
2
0
0
0
0
0
0
0
0
0
0
0
115
4
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
SEU on Output 2
23 17 SEU 1 SN55LVDS32 131Xe+35 140 20 28 65 27 99 82
3
0
0
4
0
0
0
1
0
0
0
0
0
0
0
0
SEU on Output 1
11
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
0
Bit Flipping 0 -> 1
9
0
0
0
0
0
0
0
0
JYFL RUN
5
Test SEL/SEU
4
Board
2 SEU 1 SN55LVDS31 40Ar+12
DUT Number
1 SEU 1 SN55LVDS32 40Ar+12
Ion
2
SEU Events
1
Bit Flipping 1 -> 0
HRX/SEE/0369
03
1 clk edge error
Ref. :
Issue :
2 clk edges error
SEE Test Report
3 clk edges error
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising