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SP605 Hardware

User Guide

UG526 (v1.8) September 24, 2012

© Copyright 2009–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

DISCLAIMER

The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx hereby DISCLAIMS ALL

WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF

MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm

; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps .

Revision History

The following table shows the revision history for this document.

Date

10/07/09

11/09/09

02/01/10

05/18/10

06/16/10

09/24/10

02/16/11

07/18/11

06/19/12

Version

1.0

1.1

1.1.1

1.2

1.3

1.4

1.5

1.6

1.7

Revision

Initial Xilinx release.

• Updated Figure 1-17

and Figure 1-23 .

• Changed speed grade from -2 to -3.

• Miscellaneous typographical edits.

Minor typographical edits to

Table 1-24 and

Table 1-25 .

Updated Figure 1-2 . Added Note 6 to

Table 1-11

. Updated board connections for

SFP_TX_DISABLE in Table 1-12

. Added note about FMC LPC J63 connector in 18. VITA

57.1 FMC LPC Connector

. Updated U1 FPGA Pin column for FMC_LA00_CC_P/N in

Table 1-28

. Updated description of PMBus Pod and TI Fusion Digital Power Software

GUI in Onboard Power Regulation . Updated

Appendix C, VITA 57.1 FMC LPC

Connector Pinout

, and Appendix D, SP605 Master UCF .

Updated 2. 128 MB DDR3 Component Memory

. Added note 1 to Table 1-30

.

Updated description of Fusion Digital Power Software in

Onboard Power Regulation .

Revised oscillator manufacturer information from Epson to SiTime in

Table 1-1 . Revised

oscillator manufacturer information from Epson to SiTime on page

page 26 . Deleted note

on page 44 referring to J55: “Note: This header is not installed on the SP605 as built.”

Revised values for R50 and R216 in Figure 1-12 . Revised oscillator manufacturer

information from Epson to SiTime on page

page 61

.

Corrected “jitter” to “stability” in section

Oscillator (Differential), page 26

. Revised the

feature and notes descriptions for reference numbers 6

and

12 in

Table 1-1, page 12 .

Revised FPGA pin numbers for ZIO and RZQ

in

Table 1-4, page 17

. Added

Table 1-29, page 55

,

Table 1-31, page 58 , and table notes in Table 1-30 .

Removed reference to FPGA speed grade in 2. 128 MB DDR3 Component Memory, page 16

. Added IIC External Access Header, page 39 . Updated SFP Module connector

reference designator in

8. Multi-Gigabit Transceivers (GTP MGTs), page 28

.

SP605 Hardware User Guide

www.xilinx.com

UG526 (v1.8) September 24, 2012

Date

09/24/12

Version

1.8

Revision

Updated Figure 1-2, page 12 . Added

Regulatory and Compliance Information, page 73

.

UG526 (v1.8) September 24, 2012 www.xilinx.com

SP605 Hardware User Guide

SP605 Hardware User Guide

www.xilinx.com

UG526 (v1.8) September 24, 2012

Table of Contents

Revision History

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Preface: About This Guide

Guide Contents

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Additional Documentation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Additional Support Resources

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 1: SP605 Evaluation Board

Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Related Xilinx Documents

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Detailed Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1. Spartan-6 XC6SLX45T-3FGG484 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Configuration

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

I/O Voltage Rails

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2. 128 MB DDR3 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3. SPI x4 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4. Linear BPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

FPGA Design Considerations for the Configuration Flash

. . . . . . . . . . . . . . . . . . . . . . . 23

5. System ACE CF and CompactFlash Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6. USB JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Oscillator (Differential)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Oscillator Socket (Single-Ended, 2.5V or 3.3V)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SMA Connectors (Differential)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8. Multi-Gigabit Transceivers (GTP MGTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9. PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

10. SFP Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

12. USB-to-UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

13. DVI CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

14. IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

IIC External Access Header

8-Kb NV Memory

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

15. Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Ethernet PHY Status LEDs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

FPGA INIT and DONE LEDs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

16. User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

User LEDs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

User Pushbutton Switches

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

User DIP Switch

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

User SIP Header

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

User SMA GPIO

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

17. Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012 www.xilinx.com

5

Power On/Off Slide Switch SW2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

FPGA_PROG_B Pushbutton SW3 (Active-Low)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

SYSACE_RESET_B Pushbutton SW9 (Active-Low)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

System ACE CF CompactFlash Image Select DIP Switch S1 (Active-High)

. . . . . . . . . . 51

Mode DIP Switch SW1 (Active-High)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

18. VITA 57.1 FMC LPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

19. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

AC Adapter and 12V Input Power Jack/Switch

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Onboard Power Regulation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Configuration Options

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Appendix A: References

Appendix B: Default Jumper and Switch Settings

Appendix C: VITA 57.1 FMC LPC Connector Pinout

Appendix D: SP605 Master UCF

Appendix E: Regulatory and Compliance Information

Directives

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Standards

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Markings

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6

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SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012

Preface

About This Guide

This manual accompanies the Spartan®-6 FPGA SP605 Evaluation Board and contains information about the SP605 hardware and software tools.

Guide Contents

This manual contains the following chapters:

Chapter 1, SP605 Evaluation Board

, provides an overview of and details about the components and features of the SP605 board.

Appendix B, Default Jumper and Switch Settings

.

Appendix C, VITA 57.1 FMC LPC Connector Pinout .

Appendix D, SP605 Master UCF

.

Appendix A, References .

Additional Documentation

The following documents are available for download at http://www.xilinx.com/products/spartan6/ .

• Spartan-6 Family Overview

This overview outlines the features and product selection of the Spartan-6 family.

• Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

This data sheet contains the DC and switching characteristic specifications for the

Spartan-6 family.

• Spartan-6 FPGA Packaging and Pinout Specifications

This specification includes the tables for device/package combinations and maximum

I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

• Spartan-6 FPGA Configuration User Guide

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.

• Spartan-6 FPGA SelectIO Resources User Guide

This guide describes the SelectIO™ resources available in all Spartan-6 devices.

• Spartan-6 FPGA Clocking Resources User Guide

SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012 www.xilinx.com

7

Preface: About This Guide

This guide describes the clocking resources available in all Spartan-6 devices, including the DCMs and PLLs.

• Spartan-6 FPGA Block RAM Resources User Guide

This guide describes the Spartan-6 device block RAM capabilities.

• Spartan-6 FPGA GTP Transceivers User Guide

This guide describes the GTP transceivers available in the Spartan-6 LXT FPGAs.

• Spartan-6 FPGA DSP48A1 Slice User Guide

This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and provides configuration examples.

• Spartan-6 FPGA Memory Controller User Guide

This guide describes the Spartan-6 FPGA memory controller block, a dedicated embedded multi-port memory controller that greatly simplifies interfacing

Spartan-6 FPGAs to the most popular memory standards.

• Spartan-6 FPGA PCB Designer’s Guide

This guide provides information on PCB design for Spartan-6 devices, with a focus on strategies for making design decisions at the PCB and interface level.

Additional Support Resources

To search the database of silicon and software questions and answers or to create a technical support case in WebCase, see the Xilinx website at: http://www.xilinx.com/support .

8

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SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012

Chapter 1

SP605 Evaluation Board

Overview

The SP605 board enables hardware and software developers to create or evaluate designs targeting the Spartan®-6 XC6SLX45T-3FGG484 FPGA.

The SP605 provides board features common to many embedded processing systems. Some commonly used features include: a DDR3 component memory, a 1-lane PCI Express® interface, a tri-mode Ethernet PHY, general purpose I/O and a UART. Additional user desired features can be added through mezzanine cards attached to the onboard high speed VITA-57 FPGA Mezzanine Connector (FMC) low pin count (LPC) connector.

Features, page 10

provides a general listing of the board features with details provided in

Detailed Description, page 12

.

Additional Information

Additional information and support material is located at:

• http://www.xilinx.com/sp605

This information includes:

• Current version of this user guide in PDF format

• Example design files for demonstration of Spartan-6 FPGA features and technology

• Demonstration hardware and software configuration files for the System ACE™ CF controller, Platform Flash configuration storage device, and linear flash chip

• Reference Design Files

• Schematics in PDF format and DxDesigner schematic format

• Bill of materials (BOM)

• Printed-circuit board (PCB) layout in Allegro PCB format

• Gerber files for the PCB (Many free or shareware Gerber file viewers are available on the Internet for viewing and printing these files.)

• Additional documentation, errata, frequently asked questions, and the latest news

For information about the Spartan-6 family of FPGA devices, including product highlights, data sheets, user guides, and application notes, see the Spartan-6 FPGA website at http://www.xilinx.com/support/documentation/spartan-6.htm

.

9 SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012 www.xilinx.com

Chapter 1: SP605 Evaluation Board

Features

The SP605 board provides the following features (see Figure 1-2 and Table 1-1 ):

1. Spartan-6 XC6SLX45T-3FGG484 FPGA

2. 128 MB DDR3 Component Memory

3. SPI x4 Flash

4. Linear BPI Flash

5. System ACE CF and CompactFlash Connector

6. USB JTAG

7. Clock Generation

• Fixed 200 MHz oscillator (differential)

• Socket with a 2.5V 27MHz oscillator (single-ended)

• SMA connectors (differential)

• SMA connectors for MGT clocking (differential)

8. Multi-Gigabit Transceivers (GTP MGTs)

• FMC LPC connector

• SMA

• PCIe

• SFP module connector

9. PCI Express Endpoint Connectivity

• Gen1 x1

10. SFP Module Connector

11. 10/100/1000 Tri-Speed Ethernet PHY

12. USB-to-UART Bridge

13. DVI CODEC

14. IIC Bus

• IIC EEPROM - 1KB

• DVI CODEC

• DVI connector

• FMC LPC connector

• SFP Module connector

15. Status LEDs

• Ethernet Status

• FPGA INIT

• FPGA DONE

16. User I/O

• USER LED GPIO

• User pushbuttons

• CPU Reset pushbutton

• User DIP switch - GPIO

• User SMA GPIO connectors

10

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SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012

Overview

17. Switches

• Power On/Off slide switch

• System ACE CF Reset pushbutton

• System ACE CF bitstream image select DIP switch

• Mode DIP switch

18. VITA 57.1 FMC LPC Connector

19. Power Management

AC Adapter and 12V Input Power Jack/Switch

Onboard Power Regulation

Configuration Options

3. SPI x4 Flash (both onboard and off-board)

4. Linear BPI Flash

5. System ACE CF and CompactFlash Connector

6. USB JTAG

Block Diagram

Figure 1-1 shows a high-level block diagram of the SP605 and its peripherals.

X-Ref Target - Figure 1-1

LED

DIP Switch

User SMA x2

1-Lane I/Fs:

PCIe Edge Conn.

SMA x4 SFP

FMC-LPC

PCIe 125 MHz Clk

SMA REFCLK

SFPCLK

FMC GBTCLK

Part of

FMC-LPC

Expansion

Connector

SFP IIC Bus

JTAG JTAG

System ACE

MPU I/F

JTAG

USB JTAG Logic and USB Mini-B

Connector

DDR3

Component

Memory

Pushbuttons

DIP Switch

GPIO Header

L/S

L/S

DED

MGTs

Bank 0

2.5V

Bank 3

1.5V

Spartan-6

XC6SLX45T-3FGG484

U1

Bank 1

2.5V

Bank 2

2.5V

L/S

= Level Shifter

LED,

DIP Switch

SPI x4,

SPI Header

Part of FMC-LPC

Expansion Conn.

DVI IIC Bus

Figure 1-1:

SP605 Features and Banking

Main IIC Bus

USB UART and

USB Mini-B

Connector

DVI Codec and

DVI Connector

10/100/1000

Ethernet PHY,

Status LEDs, and Connector

Parallel Flash

UG526_01_110409

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11

Chapter 1: SP605 Evaluation Board

Related Xilinx Documents

Prior to using the SP605 Evaluation Board, users should be familiar with Xilinx resources.

See the following locations for additional documentation on Xilinx tools and solutions:

• ISE: www.xilinx.com/ise

• Answer Browser: www.xilinx.com/support

• Intellectual Property: www.xilinx.com/ipcenter

Detailed Description

Figure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and

the section headings in this document.

X-Ref Target - Figure 1-2

15e

15b 15a

15h

16d

18

17b

10

5

6

7a 17a

8

16c

2

7c

17c

17d

12

15d

19b

15c

1

11

15g

13

3

4

8

16b

19

7b

16a 15f

9

3, 14 (on back side)

UG526_02 _092412

Figure 1-2:

SP605 Board

The numbered features in Figure 1-2 correlate to the features and notes listed in Table 1-1

.

Table 1-1:

SP605 Features

Number

1

2

Feature

Spartan-6 FPGA

DDR3 Component Memory

Notes

XC6SLX45T-3FGG484 FPGA

Micron MT41J64M16LA-187E

Schematic

Page

2–7

9

12

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SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012

Detailed Description

9

10

11

12

13

14

Table 1-1:

SP605 Features (Cont’d)

Number

3

4

5

6

7

8

15

Feature Notes

Schematic

Page

SPI Header Ext. x4

SPI Flash x4 (on backside)

Linear BPI Flash x16

System ACE CompactFlash

Socket

USB UART (USB-to-UART

Bridge)

Winbond W25Q64VSFIG

Numonyx JS28F256P30T95

XCCACE-TQ144I Controller

Silicon Labs CP2103GM

Clock Generation

200 MHz OSC, oscillator socket,

SMA connectors

SiTime 200 MHz 2.5V LVDS a. 200 MHz oscillator b. Oscillator socket, singleended, LVCMOS

MMD Components 2.5V 27 MHz c. SMA connectors

GTP port SMA x4 and

MGT Clocking SMA (REFCLK)

PCIe 1-lane edge conn.(Gen 1)

SMA pair P(J41) / N(J38)

MGT RX,TX Pairs x4 SMA MGT

REFCLK x2 SMA

Card Edge Connector, 1-lane

SFP Module Cage/Connector

Ethernet 10/100/1000

AMP 136073-1

Marvell M88E1111 EPHY

USB JTAG Conn. (USB Mini-B) USB JTAG Download Circuit

DVI Codec and Video Connector Chrontel CH7301C-TF

IIC EEPROM (on backside) ST Micro M24C08-WDW6TP

Status LEDs a. FMC Power Good b. System ACE CF Status c. FPGA INIT and DONE d. Ethernet PHY Status e. JTAG USB Status f. FPGA Awake g. TI Power Good h. MGT AVCC, DDR3 Term

Pwr Good

18

19

20

32

13, 14

14

14

13

13

20

27

31

10

11

14

18

12

12

11

15

16,17

15

10, 11, 14,

18, 20, 25,

27, 31, 33

33

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Chapter 1: SP605 Evaluation Board

Table 1-1:

SP605 Features (Cont’d)

Number Feature

16

17

18

19

Notes

a. User LEDs (4) b. User Pushbuttons (4) c. User DIP Switch (4-pole) d. User SMA (2)

Switches

Red LEDs (active-High)

Active-High

4-pole (active-High)

GPIO x2 SMA

Power, Configuration,

Pushbutton Switches a. SP605 Power On-Off Slide

Switch b. FPGA Mode DIP Switch c. System ACE CF

Configuration DIP Switch d. FPGA PROG, CPU Reset, and System ACE CF Reset

Pushbutton Switches

FMC LPC Connector a. Power Management

Controller b. Mini-Fit Type 6-Pin, ATX

Type 4-pin

Samtec ASP-134603-01

2x TI UCD9240PFC

12V input power connectors

Schematic

Page

14

14

14

13

14, 18, 20,

25

25

18

20

14, 20

10

21, 26

25

1. Spartan-6 XC6SLX45T-3FGG484 FPGA

A Xilinx Spartan-6 XC6SLX45T-3FGG484 FPGA is installed on the SP605 Evaluation Board.

References

See the Spartan-6 FPGA Data Sheet.

[Ref 1]

Configuration

The SP605 supports configuration in the following modes:

• JTAG (using the included USB-A to Mini-B cable)

• JTAG (using System ACE CF and CompactFlash card)

• Master SPI x4

• Master SPI x4 with off-board device

• Linear BPI Flash

For details on configuring the FPGA, see

Configuration Options .

Mode switch SW1 (see Table 1-32, page 60 ) is set to 10 = Slave SelectMAP to choose the

System ACE CF default configuration.

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Detailed Description

References

See the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]

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Chapter 1: SP605 Evaluation Board

I/O Voltage Rails

There are four available banks on the XC6SLX45T-3FGG484 device. Banks 0, 1, and 2 are connected for 2.5V I/O. Bank 3 is used for the 1.5V DDR3 component memory interface of

Spartan-6 FPGA’s hard memory controller. The voltage applied to the FPGA I/O banks used by the SP605 board is summarized in

Table 1-2 .

Table 1-2:

I/O Voltage Rail of FPGA Banks

FPGA Bank

0

I/O Voltage Rail

2.5V

1

2

3

2.5V

2.5V

1.5V

References

See the Xilinx Spartan-6 FPGA documentation for more information at http://www.xilinx.com/support/documentation/spartan-6.htm

.

2. 128 MB DDR3 Component Memory

There are 128 MB of DDR3 memory available on the SP605 board. A 1-Gb Micron

MT41J64M16LA-187E (96-ball) DDR3 memory component is accessible through Bank 3 of the LX45T device. The Spartan-6 FPGA hard memory controller is used for data transfer across the DDR3 memory interface’s 16-bit data path using SSTL15 signaling. The SP605 board supports the “standard” VCCINT setting of 1.20V ± 5%. This setting provides memory controller block (MCB) performance of 667 MT/s for DDR3 memory. Signal integrity is maintained through DDR3 resistor terminations and memory on-die terminations (ODT), as shown in

Table 1-3 and

Table 1-4

.

Table 1-3:

Termination Resistor Requirements

Signal Name On-Die Termination

MEM1_A[14:0]

MEM1_BA[2:0]

MEM1_RAS_N

MEM1_CAS_N

MEM1_WE_N

MEM1_CS_N

MEM1_CKE

MEM1_ODT

MEM1_DQ[15:0]

Board Termination

49.9

Ω to V

TT

49.9

Ω to V

TT

49.9

Ω to V

TT

49.9

Ω to V

TT

49.9

Ω to V

TT

100

Ω to GND

4.7 K

Ω to GND

4.7 K

Ω to GND

ODT

MEM1_UDQS[P,N], MEM1_LDQS[P,N]

MEM1_UDM, MEM1_LDM

ODT

ODT

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SP605 Hardware User Guide

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Detailed Description

Table 1-3:

Termination Resistor Requirements (Cont’d)

MEM1_CK[P,N]

Signal Name Board Termination

100

Ω differential at memory component

On-Die Termination

Notes:

1. Nominal value of V

TT

for DDR3 interface is 0.75V.

Table 1-4:

FPGA On-Chip (OCT) Termination External Resistor Requirements

U1 FPGA Pin FPGA Pin Number Board Connection for OCT

ZIO

RZQ

M7

K7

No Connect

100

Ω to GROUND

Table 1-5 shows the connections and pin numbers for the DDR3 Component Memory.

Table 1-5:

DDR3 Component Memory Connections

U1 FPGA

Pin

Schematic Net Name

Pin Number

Memory U42

Pin Name

F1

J6

H5

J3

G3

G1

J4

E1

J1

H1

H3

M3

L4

K6

K2

K1

K5

M6

MEM1_A0

MEM1_A1

MEM1_A2

MEM1_A3

MEM1_A4

MEM1_A5

MEM1_A6

MEM1_A7

MEM1_A8

MEM1_A9

MEM1_A10

MEM1_A11

MEM1_A12

MEM1_A13

MEM1_A14

MEM1_BA0

MEM1_BA1

MEM1_BA2

N7

T3

T7

M2

T8

R3

L7

R7

N8

M3

P8

P2

R8

R2

N3

P7

P3

N2

A8

A9

A10/AP

A11

A12/BCN

NC/A13

NC/A14

BA0

BA1

BA2

A4

A5

A6

A7

A0

A1

A2

A3

R3

R1

P2

MEM1_DQ0

MEM1_DQ1

MEM1_DQ2

G2

H3

E3

DQ6

DQ4

DQ0

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Chapter 1: SP605 Evaluation Board

V1

N4

P3

E3

F2

N3

N1

V2

H2

M5

M4

L6

K4

K3

Table 1-5:

DDR3 Component Memory Connections (Cont’d)

Memory U42

U1 FPGA

Pin

Schematic Net Name

Pin Number Pin Name

U1

W3

W1

Y2

Y1

M1

T2

T1

U3

P1

L3

L1

M2

MEM1_DQ3

MEM1_DQ4

MEM1_DQ5

MEM1_DQ6

MEM1_DQ7

MEM1_DQ8

MEM1_DQ9

MEM1_DQ10

MEM1_DQ11

MEM1_DQ12

MEM1_DQ13

MEM1_DQ14

MEM1_DQ15

D7

A3

C8

B8

A7

F8

C2

C3

A2

F2

H7

H8

F7

DQ8

DQ15

DQ10

DQ14

DQ12

DQ2

DQ7

DQ5

DQ1

DQ3

DQ11

DQ9

DQ13

MEM1_WE_B

MEM1_RAS_B

MEM1_CAS_B

MEM1_ODT

MEM1_CLK_P

MEM1_CLK_N

MEM1_CKE

MEM1_LDQS_P

MEM1_LDQS_N

MEM1_UDQS_P

MEM1_UDQS_N

MEM1_LDM

MEM1_UDM

MEM1_RESET_B

B7

E7

D3

T2

K9

F3

G3

C7

L3

J3

K3

K1

J7

K7

WE_B

RAS_B

CAS_B

ODT

CLK_P

CLK_N

CKE

LDQS_P

LDQS_N

UDQS_P

UDQS_N

LDM

UDM

RESET_B

References

See the Micron Technology, Inc. DDR3 SDRAM Specification for more information. [Ref 12]

Also, see the Spartan-6 FPGA Memory Controller User Guide.

[Ref 3]

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Detailed Description

3. SPI x4 Flash

The Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are

3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flash through a 2.5V bank. The XC6SLX45T-3FGG484 is a master device when accessing an external SPI flash memory device.

The SP605 SPI interface has two parallel connected configuration options (

Figure 1-3

): an

SPI X4 (Winbond W25Q64VSFIG) 64-Mb flash memory device (U32) and a flash programming header (J17). J17 supports a user-defined SPI mezzanine board. The SPI configuration source is selected via SPI select jumper J46. For details on configuring the

FPGA, see Configuration Options

.

X-Ref Target - Figure 1-3

SPI Prog

J17

1

2

3

TMS

TDI

Silkscreen

TDO

TCK

GND

3V3

4

5

6

7

8

9

FPGA_PROG_B

FPGA_D2_MISO3

FPGA_D1_MISO2

SPI_CS_B

FPGA_MOSI_CSI_B_MISO0

FPGA_D0_DIN_MISO_MISO1

FPGA_CCLK

GND

VCC3V3

HDR_1X9

UG526_03_092409

Figure 1-3:

J17 SPI Flash Programming Header

X-Ref Target - Figure 1-4

U1

FPGA SPI Interface

U32

J17

DIN, DOUT, CCLK

SPI x4

Flash

Memory

Winbond

W25Q64VSFIG

SPIX4_CS_B SPI_CS_B

2 1

ON = SPI X4 U32

OFF = SPI EXT. J17

J46

SPI Select

Jumper

SPI Program

Header

UG526_04_092409

Figure 1-4:

SPI Flash Interface Topology

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Chapter 1: SP605 Evaluation Board

Table 1-6:

SPI x4 Memory Connections

U1 FPGA

Pin

Schematic Net Name

AB2

T14

R13

AA3

AB20

AA20

Y20

J46.2

(1)

FPGA_PROG_B

FPGA_D2_MISO3

FPGA_D1_MISO2_R

FPGA_MOSI_CSI_B_MISO0

FPGA_D0_DIN_MISO_MISO1

Notes:

1. Not a U1 FPGA pin

SPI_CS_B

FPGA_CCLK

SPIX4_CS_B

SPI MEM U32

Pin # Pin Name

16

7

15

8

– –

1 IO3_HOLD_B

9

IO2_WP_B

DIN

IO1_DOUT

CLK

CS_B

SPI HDR J17

Pin # Pin Name

7

8

9

3

4

1

2

5

6

TMS

TDI

TDO

TCK

GND

VCC3V3

References

See the Winbond Serial Flash Memory Data Sheet for more information.

[Ref 13]

See the XPS Serial Peripheral Interface Data Sheet for more information. [Ref 4]

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SP605 Hardware User Guide

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Detailed Description

4. Linear BPI Flash

A Numonyx JS28F256P30 Linear Flash memory (U25) on the SP605 (

Figure 1-5

) provides

32 MB of non-volatile storage that can be used for configuration as well as software storage. The Linear Flash is operated in asynchronous mode.

For details on configuring the FPGA, see

Configuration Options .

X-Ref Target - Figure 1-5

U1 U25

FPGA

BPI Flash

Interface

ADDR, DATA, CTRL

Numonyx Type P30

JS28F256P30

Figure 1-5:

Linear BPI Flash Interface

UG526_05_092409

Table 1-7:

Linear Flash Connections

U1 FPGA Pin

N22

N20

U25 BPI FLASH

Schematic Net Name

FLASH_A0

Pin Number

29

FLASH_A1 25

Pin Name

A1

A2

M22

M21

L19

FLASH_A2 24

FLASH_A3 23

FLASH_A4 22

A3

A4

A5

K20

H22

H21

L17

FLASH_A5 21

FLASH_A6 20

FLASH_A7 19

FLASH_A8 8

A6

A7

A8

A9

K17

G22

G20

K18

K19

H20

J19

FLASH_A9 7

FLASH_A10 6

FLASH_A11

FLASH_A12

FLASH_A13

FLASH_A14

FLASH_A15

2

1

5

4

3

A10

A11

A12

A13

A14

A15

A16

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Chapter 1: SP605 Evaluation Board

Table 1-7:

Linear Flash Connections (Cont’d)

U1 FPGA Pin Schematic Net Name

E22

E20

F22

F21

H19

H18

F20

G19

FLASH_A16

FLASH_A17

FLASH_A18

FLASH_A19

FLASH_A20

FLASH_A21

FLASH_A22

FLASH_A23

V13

R20

P22

P21

T19

T18

AA20

R13

T14

AA6

AB6

FPGA_D0_DIN_MISO_MISO1

FPGA_D1_MISO2

34

36

FPGA_D2_MISO3 39

FLASH_D3 41

FLASH_D4 47

Y5

AB5

W9

T7

FLASH_D5 49

FLASH_D6 51

FLASH_D7 53

FLASH_D8 35

U6 FLASH_D9 37

AB19 FLASH_D10 40

AA18

AB18

FLASH_D11

FLASH_D12

42

48

Y13

AA12

AB12

FLASH_D13

FLASH_D14

FLASH_D15

50

52

54

FMC_PWR_GOOD_FLASH_RST_B 44

FLASH_WE_B 14

FLASH_OE_B

FLASH_CE_B

32

30

FLASH_ADV_B

FLASH_WAIT

46

56

U25 BPI FLASH

Pin Number Pin Name

55

18

17

16

11

10

9

26

A17

A18

A19

A20

A21

A22

A23

A24

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ0

DQ1

DQ2

DQ3

DQ4

DQ13

DQ14

DQ15

RST_B

WE_B

OE_B

CE_B

ADV_B

WAIT

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Detailed Description

FPGA Design Considerations for the Configuration Flash

The SP605 has the P30 BPI flash connected to the FPGA dual use configuration pins and is not shared. It can be used to configure the FPGA, and then controlled post-configuration via the FPGA fabric. After FPGA configuration, the FPGA design can disable the configuration flash or access the configuration flash to read/write code or data.

When the FPGA design does not use the configuration flash, the FPGA design must drive the FLASH_OE_B pin High in order to disable the configuration flash and put the flash into a quiescent, low-power state. Otherwise, the flash memory can continue to drive its array data onto the data bus causing unnecessary switching noise and power consumption.

For FPGA designs that access the flash for reading/writing stored code or data, connect the FPGA design or EDK embedded memory controller (EMC) peripheral to the flash

through the pins defined in Figure 1-5, page 17

.

References

See the Numonyx StrataFlash Embedded Memory Data Sheet for more information. [Ref 14]

In addition, see the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]

5. System ACE CF and CompactFlash Connector

The Xilinx System ACE CompactFlash (CF) configuration controller allows a Type I or

Type II CompactFlash card to program the FPGA through the JTAG port. Both hardware and software data can be downloaded through the JTAG port. The System ACE CF controller supports up to eight configuration images on a single CompactFlash card. The configuration address switches allow the user to choose which of the eight configuration images to use.

The CompactFlash (CF) card shipped with the board is correctly formatted to enable the

System ACE CF controller to access the data stored in the card. The System ACE CF controller requires a FAT16 file system, with only one reserved sector permitted, and a sector-per-cluster size of more than one (UnitSize greater than 512). The FAT16 file system supports partitions of up to 2 GB. If multiple partitions are used, the System ACE CF directory structure must reside in the first partition on the CompactFlash, with the xilinx.sys

file located in the root directory. The xilinx.sys file is used by the System

ACE CF controller to define the project directory structure, which consists of one main folder containing eight sub-folders used to store the eight ACE files containing the configuration images. Only one ACE file should exist within each sub-folder. All folder names must be compliant to the DOS 8.3 short file name format. This means that the folder names can be up to eight characters long, and cannot contain the following reserved characters: < > " / \ |. This DOS 8.3 file name restriction does not apply to the actual ACE file names.

Other folders and files may also coexist with the System ACE CF project within the FAT16 partition. However, the root directory must not contain more than a total of 16 folder and/or file entries, including deleted entries. When ejecting or unplugging the

CompactFlash device, it is important to safely stop any read or write access to the

CompactFlash device to avoid data corruption.

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Chapter 1: SP605 Evaluation Board

T3

R4

V5

V3

N6

N7

U4

T4

P6

P7

P5

P4

H4

G4

D2

System ACE CF error and status LEDs indicate the operational state of the System ACE CF controller:

• A blinking red error LED indicates that no CompactFlash card is present

• A solid red error LED indicates an error condition during configuration

• A blinking green status LED indicates a configuration operation is ongoing

• A solid green status LED indicates a successful download

The mode SW1 setting is important because the System ACE CF can fail to configure the

FPGA when the mode pins are set to the master modes (

Table 1-32, page 60

). A configuration failure from the master mode can drive INIT_B low, which blocks the System

ACE CF from downloading a configuration ACE file. The FPGA mode pins must be set as specified in

Table 1-32

for the System ACE CF configuration solution.

With the mode switch SW1 set to 10 (Slave SelectMAP, Table 1-32 ), if a Compact Flash (CF)

card is installed in the CF socket U37, the System ACE CF will attempt to load a bitstream from the CF card image address pointed to by the image select switch S1.

Every time a CompactFlash card is inserted into the System ACE CF socket, a configuration operation is initiated. Pressing the System ACE CF reset button reprograms the FPGA.

Note:

System ACE CF configuration is enabled by way of DIP switch S1. See 17. Switches, page 49

for more details.

The System ACE CF MPU port (

Table 1-8 ) is connected to the FPGA. This connection

allows the FPGA to use the System ACE CF controller to reconfigure the system or access the CompactFlash card as a generic FAT file system.

Table 1-8:

System ACE CF Connections

U1 FPGA Pin Schematic Net Name

(1)

U17 XCCACETQ144I

Pin Number Pin Name

SYSACE_D0

SYSACE_D1

SYSACE_D2

SYSACE_D3

SYSACE_D4

SYSACE_D5

SYSACE_D6

SYSACE_D7

SYSACE_MPA00

SYSACE_MPA01

SYSACE_MPA02

SYSACE_MPA03

SYSACE_MPA04

SYSACE_MPA05

SYSACE_MPA06

59

58

70

69

66

65

63

62

61

60

68

67

45

44

43

MPD00

MPD01

MPD02

MPD03

MPD04

MPD05

MPD06

MPD07

MPA00

MPA01

MPA02

MPA03

MPA04

MPA05

MPA06

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Detailed Description

Table 1-8:

System ACE CF Connections (Cont’d)

U1 FPGA Pin

A21

E18

D20

N19

AA1

W4

AA2

T6

T5

G17

Schematic Net Name

SYSACE_MPBRDY

SYSACE_MPCE

SYSACE_MPIRQ

SYSACE_MPOE

SYSACE_MPWE

SYSACE_CFGTDI

FPGA_TCK

FPGA_TDI

FPGA_TMS

(1)

CLK_33MHZ_SYSACE(2)

U17 XCCACETQ144I

Pin Number Pin Name

39

42

41

77

76

81

80

82

85

93

MPBRDY

MPCE

MPIRQ

MPOE

MPWE

CFGTDI

CFGTCK

CFGTDO

CFGTMS

CLK

Notes:

1. U17 System ACE CF controller 3.3V signals as named are wired to a set of TXB0108 3.3V-to-1.5V level shifters. The nets between the 1.5V side of the level shifters and the U1 FPGA have the same names with _LS appended.

2. The System ACE CF clock is sourced from U29 32.000MHz oscillator.

References

See the System ACE CF product page for more information at http://www.xilinx.com/support/documentation/system_ace_solutions.htm

.

In addition, see the System ACE CompactFlash Solution Data Sheet.

[Ref 5]

6. USB JTAG

JTAG configuration is provided through onboard USB-to-JTAG configuration logic where a computer host accesses the SP605 JTAG chain through a Type-A (computer host side) to

Type-Mini-B (SP605 side) USB cable. The JTAG chain of the board is illustrated in

Figure 1-6 . JTAG configuration is allowable at any time under any mode pin setting. JTAG

initiated configuration takes priority over the mode pin settings.

X-Ref Target - Figure 1-6

J19

3.3V

2.5V

J4

Buffer

FMC LPC

TDI TDO

System ACE CF

TSTTDI

CFGTDO

TDI

FPGA

J2

TSTTDO

CFGTDI

U17

Figure 1-6:

JTAG Chain Diagram

TDO

U1

UG526_06_092409

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Chapter 1: SP605 Evaluation Board

FMC bypass jumper J19 must be connected between pins 1-2 (bypass) to enable JTAG access to the FPGA on the basic SP605 board (without FMC expansion modules installed), as shown in

Figure 1-7

. When the VITA 57.1 FMC LPC expansion connector is populated with an expansion module that has a JTAG chain, jumper J19 must be set to connect pins

2-3 in order to include the FMC expansion module's JTAG chain in the main SP605 JTAG chain.

X-Ref Target - Figure 1-7

J19

1

FMC_TDI_BUF

Bypass FMC LPC J2 = Jumper 1-2

2

SYSACE_TDI

Include FMC LPC J2 = Jumper 2-3

3

FMC_TD0

H - 1x3

UG526_07_092409

Figure 1-7:

VITA 57.1 FMC LPC (J2) JTAG Bypass Jumper J19

The JTAG chain can be used to program the FPGA and access the FPGA for hardware and software debug.

The JTAG connector (USB Mini-B J4) allows a host computer to download bitstreams to the

FPGA using the Xilinx iMPACT software tool. In addition, the JTAG connector allows debug tools such as the ChipScope® Pro Analyzer tool or a software debugger to access the

FPGA. The iMPACT software tool can also program the BPI flash via the USB J4 connection. iMPACT can download a temporary design to the FPGA through the JTAG.

This provides a connection within the FPGA from the FPGAs JTAG port to the FPGAs BPI interface. Through the connection made by the temporary design in the FPGA, iMPACT can indirectly program the BPI flash from the JTAG USB J4 connector. For an overview on

configuring the FPGA, see Configuration Options, page 60 .

7. Clock Generation

There are three clock sources available on the SP605.

Oscillator (Differential)

The SP605 has one 2.5V LVDS differential 200 MHz oscillator (U6) soldered onto the board and wired to an FPGA global clock input.

• Crystal oscillator: SiTime SiT9102AI-243N25E200.00000

• Frequency stability: 50 ppm

References

See the SiTime SiT9102 Data Sheet for more information. Search SiT9102 at SiTime.com

[Ref 15] .

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SP605 Hardware User Guide

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Detailed Description

Oscillator Socket (Single-Ended, 2.5V or 3.3V)

One populated single-ended clock socket (X2) is provided for user applications. The option of 2.5V or 3.3V power may be selected via a 0

Ω resistor selection. The SP605 board is shipped with a 27 MHz 2.5V oscillator installed.

Figure 1-8 shows the unpopulated user oscillator socket. This figure indicates the socket pin 1 location. Figure 1-9

shows the oscillator installed, with its pin 1 location identifiers.

X-Ref Target - Figure 1-8

Silkscreened outline has beveled corner

Socket has notch in crossbar

X-Ref Target - Figure 1-9

UG526_08_100509

Figure 1-8:

SP605 X2 Oscillator Socket Pin 1 Location Identifiers

Oscillator body has one square corner

Oscillator top has corner dot marking

SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012

UG526_09_100509

Figure 1-9:

SP605 X2 Oscillator Pin 1 Location Identifiers

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27

Chapter 1: SP605 Evaluation Board

SMA Connectors (Differential)

A high-precision clock signal can be provided to the FPGA using differential clock signals through the onboard 50

Ω SMA connectors J38 (N) and J41 (P).

Table 1-9:

SP605 Clock Source Connections

Source U1 FPGA Pin Schematic Net Name

Pin

Number

Pin Name

U6 200MHZ OSC

K22

K21

SYSCLK_N

SYSCLK_P

5

4

OUT_B

OUT

X2 27MHZ OSC

USER_SMA_CLOCK

SMA Connectors

AB13

M19

M20

USER_CLOCK

USER_SMA_CLOCK_N

USER_SMA_CLOCK_P

5

J38.1

J41.1

OUT

8. Multi-Gigabit Transceivers (GTP MGTs)

The SP605 provides access to 4 MGTs.

• One (1) MGT is wired to the PCIe x1 Endpoint (P4) edge connector fingers

• One (1) MGT is wired to the FMC LPC connector (J2)

• One (1) MGT is wired to MGT SMA connectors (J36, J37)

• One (1) MGT is wired to the SFP Module connector (P2)

The SP605 includes a set of six SMA connectors for the GTP (MGT) RX/TX Port and GTP

(MGT) Clock as described in

Figure 1-10

and Table 1-10 .

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Detailed Description

X-Ref Target - Figure 1-10

SMA_RX_N

SMA_RX_P

SMA MGT Connectors

SMA_TX_N

SMA_TX_P

MGT REFCLK

SMA_REFCLK_N

SMA_REFCLK_P

SMA_RX_C_N

SMA_RX_C_P

1

J35 32K10K-400E3

GND1

2

GND2

3

GND3

4

SIG GND4

5

GND5

6

GND6

7

GND7

8

1

J34 32K10K-400E3

GND1

2

GND2

3

GND3

4

SIG GND4

5

GND5

6

GND6

7

GND7

8

1

J33 32K10K-400E3

GND1

2

GND2

3

GND3

4

SIG GND4

5

GND5

6

GND6

7

GND7

8

1

J32 32K10K-400E3

SIG

GND1

GND2

GND3

GND4

GND5

GND6

GND7

5

6

7

8

2

3

4

SMA_REFCLK_C_N 1

J36 32K10K-400E3

SIG

GND1

GND2

GND3

GND4

GND5

GND6

GND7

4

5

6

7

8

2

3

SMA_REFCLK_C_P 1

J37 32K10K-400E3

GND1

2

GND2

3

GND3

4

SIG GND4

5

GND5

6

GND6

7

GND7

8

UG526_10 _092409

Figure 1-10:

GTP SMA Clock

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Chapter 1: SP605 Evaluation Board

Table 1-10:

GTP SMA Clock Connections

U1 FPGA Pin Schematic Net Name

C9

D9

A8

B8

D11

C11

SMA_RX_N

SMA_RX_P

SMA_TX_N

SMA_TX_P

SMA_REFCLK_N

SMA_REFCLK_P

SMA Pin

J35.1

J34.1

J33.1

J32.1

J36.1

J37.1

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Detailed Description

9. PCI Express Endpoint Connectivity

The 1-lane PCIe edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1 application. The Spartan-6 FPGA GTP MGT is used for the multi-gigabit per second serial interface.

The SP605 board trace impedance on the PCIe lane supports Gen1 applications. The SP605 supports Gen1 x1.

Table 1-11:

PCIe Edge Connector Connections

P4 PCIe Edge Connector

U1 FPGA Pin Schematic Net Name

Pin Number Pin Name

B10

A10

J7

C7

D7

A6

B6

PCIE_RX0_N

PCIE_RX0_P

PCIE_TX0_N

(1)

PCIE_TX0_P

(1)

PCIE_CLK_QO_N

(2)

PCIE_CLK_QO_P

(2)

PCIE_250M_N

(3)(6)

PCIE_250M_P

(3)(6)

PCIE_PERST_B_LS

B15

B14

A17

A16

A14

A13

U48.17

(4)

U48.18

(4)

A11

PETn0

PETp0

PERn0

PERp0

REFCLK-

REFCLK+

NQ

Q

PERST

(5)

Notes:

1. Each of the TX0_N/P signals has a 0.1 µF series capacitor.

2. PCIE_CLK_QO_N/P is the PC motherboard 100MHZ REFCLK.

3. Each of the PCIE_250M_N/P signals has a 0.1 µF series capacitor.

4. U48 is an ICS874001 clock multiplier device (U48.17/18 are not P4 pins).

5. The PERST signal from pin P4.A11 is isolated by a series resistor and then level-shifted by U52 before making the FPGA pin U1.J7 connection.

6. PCIE_250M_N/P signals can be a frequency other than 250 MHz, depending on the settings selected by resistor population for U48 ICS874001. The default setting is 125 MHz.

The PCIe interface obtains its power from the DC power supply provided with the SP605 or through the 12V ATX power supply connector. The PCIe edge connector is not used for any power connections.

The board can be powered by one of two 12V sources; J18, a 6-pin (2x3) Mini-Fit-type connector and J27, a 4-pin (inline) ATX disk drive type connector.

The 6-pin Mini-Fit-type connector provides 60W (12V @ 5A) from the AC power adapter provided with the board while the 4-pin ATX disk drive type connector is provided for users who want to power their board while it is installed inside a PC chassis.

For applications requiring additional power, such as the use of expansion cards drawing significant power, a larger AC adapter might be required. If a different AC adapter is used, its load regulation should be better than ±10%.

SP605 power slide switch SW2 turns the board on and off by controlling the 12V supply to the board.

Caution!

Caution! Never apply power to the power brick 6-pin Mini-Fit type connector (J18) and the 4-pin ATX disk drive type connector (J27) at the same time as this will result in damage to the board. Never connect an auxiliary PCIe 6-pin power connector to J18 6-pin Mini-Fit type connector on the SP605 board as this could result in damage to the PCIe motherboard and/or

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Chapter 1: SP605 Evaluation Board

SP605 board. The 6-pin Mini-Fit type connector is marked with a no PCIe power label to warn users of the potential hazard.

References

See the Spartan-6 FPGA GTP Transceivers User Guide for more information.

[Ref 6]

Also, see the following websites for more information about the Spartan-6 FPGA Integrated

Endpoint Block for PCI Express:

• Product information, http://www.xilinx.com/products/ipcenter/S6_PCI_Express_Block.htm

• IP data sheets, http://www.xilinx.com/support/documentation/ipbusinterfaceio_pci-express.htm#131486

In addition, see the PCI Express specifications for more information.

[Ref 16]

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Detailed Description

10. SFP Module Connector

The board contains a small form-factor pluggable (SFP) connector and cage assembly that accepts SFP modules. The SFP interface is connected to MGT Bank 123 on the FPGA. The

SFP module serial ID interface is connected to the “SFP” IIC bus (see 14. IIC Bus, page 38

for more information). The control and status signals for the SFP module are connected to jumpers and test points as described in

Table 1-12

. The SFP module connections are shown in

Table 1-13

.

Table 1-12:

SFP Module Control and Status

SFP Control/Status Signal Board Connection

SFP_TX_FAULT

SFP_TX_DISABLE

SFP_MOD_DETECT

SFP_RT_SEL

SFP_LOS

Test Point J15

High = Fault

Low = Normal Operation

Jumper J44

On = SFP Enabled

Off = SFP Disabled

Test Point J16

High = Module Not Present

Low = Module Present

Jumper J22

Jumper Pins 1-2 = Full Bandwidth

Jumper Pins 2-3 = Reduced Bandwidth

Test Point J14

High = Loss of Receiver Signal

Low = Normal Operation

Table 1-13:

SFP Module Connections

U1 FPGA Pin Schematic Net Name

D13

C13

B14

A14

T17

Y8

A12

B12

SFP_RX_P

SFP_RX_N

SFP_TX_P

SFP_TX_N

SFP_LOS

SFP_TX_DISABLE_FPGA

SFPCLK_QO_N

(1)

SFPCLK_QO_P

(1)

Notes:

1. The 125MHz SFP clock is sourced by clock driver U47.

2. Not P2 SFP module pins.

P2 SFP Module Connector

Pin Number

13

12

18

19

8

3

U47.6

(2)

U47.7

(2)

Pin Name

RDP

RDN

TDP

TDN

LOS

TX_DISABLE

-

-

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Chapter 1: SP605 Evaluation Board

11. 10/100/1000 Tri-Speed Ethernet PHY

The SP605 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernet communications at 10, 100, or 1000 Mb/s. The board supports a GMII interface from the

FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through a Halo

HFJ11-1G01E RJ-45 connector with built-in magnetics.

On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY address 0b00111 using the settings shown in

Table 1-14

. These settings can be overwritten via software commands passed over the MDIO interface.

Table 1-14:

PHY Configuration Pins

Pin

Connection on

Board

Bit[2]

Definition and Value

Bit[1]

Definition and Value

Bit[0]

Definition and Value

CFG2

CFG3

V

CC

2.5V

V

CC

2.5V

CFG4

CFG5

V

CC

2.5V

V

CC

2.5V

CFG6 PHY_LED_RX

ANEG[3] = 1

ANEG[0] = 1

ANEG[2] = 1

ENA_XC = 1

ANEG[1] = 1

DIS_125 = 1

HWCFG_MD[2] = 1 HWCFG_MD[1] = 1 HWCFG_MD[0] = 1

DIS_FC = 1

SEL_BDT = 0

DIS_SLEEP = 1

INT_POL = 1

HWCFG_MD[3] = 1

75/50

Ω = 0

Table 1-15 shows the connections and pin numbers for the PHY.

Table 1-15:

Ethernet PHY Connections

U1 FPGA Pin Schematic Net Name

U46 M88E111

Pin Number Pin Name

Y21

W22

W20

V22

V21

U20

T22

P19

Y22

V20

R19

J20

J22

N15

M16

P20

PHY_MDIO

PHY_MDC

PHY_INT

PHY_RESET

PHY_CRS

PHY_COL

PHY_RXCLK

PHY_RXER

PHY_RXCTL_RXDV

PHY_RXD0

PHY_RXD1

PHY_RXD2

PHY_RXD3

PHY_RXD4

PHY_RXD5

PHY_RXD6

126

125

124

123

121

8

4

3

128

36

115

114

7

33

35

32

RXER

RXDV

RXD0

RXD1

RXD2

RXD3

RXD4

RXD5

RXD6

MDIO

MDC

INT_B

RESET_B

CRS

COL

RXCLK

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Detailed Description

Table 1-15:

Ethernet PHY Connections (Cont’d)

U1 FPGA Pin Schematic Net Name

U46 M88E111

Pin Number Pin Name

T10

AB8

AA8

AB9

U22

AB7

L20

U8

T8

U10

Y9

Y12

W12

PHY_RXD7

PHY_TXC_GTPCLK

PHY_TXCLK

PHY_TXER

PHY_TXCTL_TXEN

PHY_TXD0

PHY_TXD1

PHY_TXD2

PHY_TXD3

PHY_TXD4

PHY_TXD5

PHY_TXD6

PHY_TXD7

19

20

24

25

120

14

10

13

16

18

26

28

29

RXD7

GTXCLK

TXCLK

TXER

TXEN

TXD0

TXD1

TXD2

TXD3

TXD4

TXD5

TXD6

TXD7

References

See the Marvell Alaska Gigabit Ethernet Transceivers product page for more information.

[Ref 17]

Also, see the LogiCORE™ IP Tri-Mode Ethernet MAC User Guide.

[Ref 7]

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Chapter 1: SP605 Evaluation Board

12. USB-to-UART Bridge

The SP605 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) which allows connection to a host computer with a USB cable. The USB cable is supplied in this evaluation kit (Type A end to host computer, Type Mini-B end to SP605 connector J23).

Table 1-16 details the SP605 J23 pinout.

Xilinx UART IP is expected to be implemented in the FPGA fabric (for instance, Xilinx XPS

UART Lite). The FPGA supports the USB-to-UART bridge using four signal pins: Transmit

(TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).

Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the

CP2103GM USB-to-UART bridge to appear as a COM port to host computer communications application software (for example, HyperTerm or TeraTerm). The VCP device driver must be installed on the host PC prior to establishing communications with the SP605. Refer to the evaluation kit Getting Started Guide for driver installation instructions.

Table 1-16:

USB Type B Pin Assignments and Signal Definitions

USB Connector

Pin

Signal Name Description

1

2

3

4

VBUS

USB_DATA_N

USB_DATA_P

GROUND

+5V from host system (not used)

Bidirectional differential serial data (N-side)

Bidirectional differential serial data (P-side)

Signal ground

Table 1-17:

USB-to-UART Connections

U1 FPGA Pin

UART Function in FPGA

Schematic Net

Name

U30 CP2103GM

Pin

UART Function in CP2103GM

F18

F19

B21

H17

RTS, output

CTS, input

TX, data out

RX, data in

USB_1_CTS

USB_1_RTS

USB_1_RX

USB_1_TX

22

23

24

25

CTS, input

RTS, output

RXD, data in

TXD, data out

Notes:

1. The schematic net names correspond with the CP2103GM pin names and functions, and the UART IP in the FPGA must be connected accordingly.

References

Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers.

In addition, see some of the Xilinx UART IP specifications at:

• http://www.xilinx.com/support/documentation/ip_documentation/xps_uartlite.pdf

• http://www.xilinx.com/support/documentation/ip_documentation/xps_uart16550.pdf

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Detailed Description

13. DVI CODEC

A DVI connector (P3) is present on the board to support an external video monitor. The

DVI circuitry utilizes a Chrontel CH7301C (U31) capable of 1600 X 1200 resolution with 24bit color. The video interface chip drives both the digital and analog signals to the DVI connector. A DVI monitor can be connected to the board directly. A VGA monitor can also be connected to the board using the supplied DVI-to-VGA adaptor. The Chrontel CH7301C is controlled by way of the video IIC bus.

The DVI connector (

Table 1-18

) supports the IIC protocol to allow the board to read the monitor's configuration parameters. These parameters can be read by the FPGA using the

DVI IIC bus (see

14. IIC Bus, page 38

).

Table 1-18:

DVI Controller Connections

U31 Chrontel CH7301C

U1 FPGA Pin

Schematic Net

Name

Pin Number Pin Name

L15

B22

C22

C20

P18

R17

J17

J16

No Connect

D22

M18

R15

R16

P17

K16

U19

T20

N16

P16

M17

DVI_D0 63

DVI_D1 62

DVI_D2 61

DVI_D3 60

DVI_D4 59

DVI_D5 58

DVI_D6 55

DVI_D7 54

DVI_D8 53

DVI_D9 52

DVI_D10 51

DVI_D11 50

DVI_DE 2

DVI_H 4

DVI_RESET_B 13

DVI_V 5

DVI_XCLK_N 56

DVI_XCLK_P 57

DVI_GPIO0

DVI_GPIO1

8

7

D10

D11

DE

H

RESET_B

V

XCLK_N

XCLK_P

GPIO0

GPIO1

D6

D7

D8

D9

D0

D1

D2

D3

D4

D5

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Chapter 1: SP605 Evaluation Board

X-Ref Target - Figure 1-11

14. IIC Bus

The SP605 implements three IIC bus interfaces at the FPGA.

The MAIN IIC bus hosts four items:

• FPGA U1 Bank 1 “MAIN” IIC interface

• 8-Kb NV Memory U4

• FMC LPC connector J2

• 2-Pin External Access Header J45

The DVI IIC bus hosts two items:

• FPGA U1 Bank 2 DVI IIC interface

• DVI Codec U31 and DVI connector P3

The SFP IIC bus hosts two items:

• FPGA U1 Bank 0 SFP IIC interface

• SFP module connector P2

The SP605 IIC bus topology is shown in

Figure 1-11

.

U1

BANK 1

BANK 0

BANK 2

IIC_SDA_MAIN

IIC_SCL_MAIN

IIC_SDA_SFP

IIC_SCL_SFP

IIC_SDA_DVI

IIC_SCL_DVI

LEVEL

SHIFTER

P3

DVI Connector

Addr: 0b1010000

U31

DVI CODEC

CHRONTEL

CH730C-TF

Addr: 0b1110110

IIC_CLK_DVI_F

IIC_SDA_DVI_F

Figure 1-11:

IIC Bus Topology

U4

ST MICRO

M24C08-WDW6TP

Addr: 0b1010100 through

0b1010111

J2

FMC LPC

Column C

2 Kb EEPROM on any FMC LPC

Mezzanine Card

Addr: 0b1010010

J45

2-Pin External

Access Header

P2

SFP Module

Connector

Addr: 0b1010000

UG526_11_092609

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Detailed Description

X-Ref Target - Figure 1-12

Table 1-19:

IIC Bus Connections

U1 FPGA Pin

Schematic

Netname

R22

T21

Connected To

IIC_SDA_MAIN J2.C31, U4.5

(1)

IIC_SCL_MAIN J2.C30, U4.6

(1)

AA4

W13

IIC_SDA_DVI

IIC_SCL_DVI

Q8.2, U31.14

Q7.2, U31.15

E6

E5

IIC_SDA_SFP

IIC_SCL_SFP

P2.4

P2.5

Notes:

1. U4 IIC bus signals are resistively coupled with 0

Ω resistors

2. Legend

J2, FMC LPC Connector

P2, SFP Module Connector

P3, DVI Connector

Qn.n, Level-Shifting Transistor

U31, Chrontel CH7301C

Level-Shifted

Connection

Q8.3, P3.7

Q7.3, P3.6

Level-Shifted

Net Name

IIC_SDA_DVI_F

IIC_CLK_DVI_F

IIC External Access Header

J45 (see Figure 1-12

) is a two-pin header that allows external IIC devices to be connected to the SP605 IIC bus. When connected, the external device can be accessed via IIC commands using IIC_SDA_MAIN and IIC_SCL_MAIN.

8-Kb NV Memory

The SP605 hosts a 8-Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage memory device (U4). The IIC address of U4 is 0b1010100, and U4 is not write protected

(WP pin 7 is tied to GND).

The IIC memory is shown in

Figure 1-12

.

VCC3V3

IIC_SCL_MAIN

IIC_SDA_MAIN

2

J45

1

H-1X2

External Access

Header

1

2

R6

1.0K

5%

1/10W

1

2

R5

1.0K

5%

1/10W

1

2

R50

50

1%

1/16W

IIC Address 0b1010100

6

5

SCL

SDA

U4

WP

1

2

3

A0

A1

A2

7

VCC

GND

8

4

M24C08-WDW6TP

VCC3V3

1

C40

0.1UF

2

X5R

10V

1

R216

DNP

2

UG526_12 _012611

Figure 1-12:

IIC Memory U4

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Chapter 1: SP605 Evaluation Board

Table 1-20:

IIC Memory Connections

U1 FPGA Pin Schematic Netname

Not Applicable

Not Applicable

Not Applicable

R22

T21

Not Applicable

Tied to GND

Tied to GND

Pulled up (0

Ω) to VCC3V3

IIC_SDA_MAIN

IIC_SCL_MAIN

Tied to GND

References

See the ST Micro M24C08 Data Sheet for more information. [Ref 18]

In addition, see the Xilinx XPS IIC Bus Interface Data Sheet.

[Ref 8]

IIC Memory U4

Pin Number Pin Name

3

5

1

2

6

7

A0

A1

A2

SDA

SCL

WP

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Detailed Description

DS9

DS10

DS14

DS15

DS17

DS18

DS19

15. Status LEDs

Table 1-21

defines the status LEDs.

Table 1-21:

Status LEDs

Reference

Designator

Signal Name

DS1

DS2

DS3

DS4

DS5

DS6

DS7

FMC_PWR_GOOD_FLASH_RST_B

FPGA_DONE

GPIO_LED_0

GPIO_LED_1

GPIO_LED_2

GPIO_LED_3

FPGA_AWAKE

Color

Green

Green

Green

Green

Green

Green

Green

DS8 Green SYSACE_STAT_LED

TI_PWRGOOD (AND)

MGT_TI_PWRGOOD

LED_RED / LED_GRN

VCC12_P

(U11.9 PGOOD PIN)

FPGA_INIT_B

SYSACE_ERR_LED

MGT_POWERGOOD

Green

Red/Green

Green

Green

Red

Red

Green

Label Description

FMC PWR GD

DONE

FMC Power Good

FPGA DONE

GPIO_LED_0

GPIO_LED_1

GPIO_LED_2

GPIO_LED_3

System ACE CF

Status LED

POWER GOOD

STATUS

12V

DDR3 PWR GD

INIT

System ACE CF

Error LED

MGT_AVCC GD

System ACE CF Status

TI_CORE_PWR+TI_MGT_PWR

GOOD

USB JTAG Controller Status

12V Power On

DDR3 1.5V Power On

FPGA INIT

System ACE CF Error

MGT_AVCC Power On

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Chapter 1: SP605 Evaluation Board

Ethernet PHY Status LEDs

The Ethernet PHY status LEDs (DS11-DS13) are mounted in right-angle plastic housings to make them visible on the connector end of the board when the SP605 board is installed into a PC motherboard. This cluster of six LEDs is installed adjacent to the RJ45 Ethernet jack

P1.

X-Ref Target - Figure 1-13

Direction

Indicator

Link Rate

(Mbps)

DUP

TX

RX

10

100

1000

P1

End view of SP605 Ethernet jack and status LEDs when installed vertically in a PC chassis

UG526_13 _092409

Figure 1-13:

Ethernet PHY Status LEDs

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Detailed Description

FPGA INIT and DONE LEDs

The typical Xilinx FPGA power up and configuration status LEDs are present on the SP605.

The red INIT LED DS17 comes on momentarily after the FPGA powers up and during its internal power-on process. The DONE LED DS2 comes on after the FPGA programming bitstream has been downloaded and the FPGA successfully configured.

X-Ref Target - Figure 1-14

VCC2V5

VCC2V5

1

2

R169

332

1%

1/16W

FPGA_DONE

VCC2V5

1

2

R19

4.7K

5%

1/16W

2

1

FPGA_INIT_B

INIT_B = 0, LED: ON

INIT_B = 1, LED: OFF

Figure 1-14:

FPGA INIT and DONE LEDs

Table 1-22:

FPGA INIT and DONE LED Connections

U1 FPGA Pin

Schematic Net

Name

Controlled LED

Y4

AB21

FPGA_INIT_B

FPGA_DONE

DS17 INIT, Red

DS2 DONE, Green

1

2

R70

27.4

1%

1/16W

UG526_14 _092409

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Chapter 1: SP605 Evaluation Board

16. User I/O

The SP605 provides the following user and general purpose I/O capabilities:

User LEDs

User Pushbutton Switches

User DIP Switch

User SIP Header

User SMA GPIO

User LEDs

The SP605 provides four active-High green LEDs as described in

Figure 1-15

and

Table 1-23

.

X-Ref Target - Figure 1-15

GPIO LED 3

GPIO LED 2

GPIO LED 1

GPIO LED 0

44

1

2

R74

27.4

1%

1/16W

1

2

R73

27.4

1%

1/16W

1

2

R72

27.4

1%

1/16W

1

2

R71

27.4

1%

1/16W

Figure 1-15:

User LEDs

Table 1-23:

User LED Connections

U1 FPGA Pin Schematic Net Name

D17

AB4

D21

W15

GPIO_LED_0

GPIO_LED_1

GPIO_LED_2

GPIO_LED_3

Controlled LED

DS3

DS4

DS5

DS6

UG526_15_092409 www.xilinx.com

SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012

Detailed Description

User Pushbutton Switches

The SP605 provides five active-High pushbutton switches: SW4, SW5, SW6, SW7 and SW8.

The five pushbuttons all have the same topology as the sample shown in

Figure 1-16

. Four pushbuttons are assigned as GPIO, and the fifth is assigned as a CPU_RESET.

Figure 1-16 and Table 1-24

describe the pushbutton switches.

X-Ref Target - Figure 1-16

VCC1V5

CPU_RESET

1

P1

Pushbutton

P4

4

2

P2

SW6

P3

3

Figure 1-16:

User Pushbutton Switch (Typical)

Table 1-24:

Pushbutton Switch Connections

U1 FPGA Pin Schematic Netname

F3

G6

F5

C1

H8

GPIO_BUTTON_0

GPIO_BUTTON_1

GPIO_BUTTON_2

GPIO_BUTTON_3

CPU_RESET

Switch Pin

SW4.2

SW7.2

SW5.2

SW8.2

SW6.2

1

2

R230

1.00K

1%

1/16W

UG526_16_092409

SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012 www.xilinx.com

45

Chapter 1: SP605 Evaluation Board

User DIP Switch

The SP605 includes an active-High four-pole DIP switch, as described in

Figure 1-17 and

Table 1-25

. Three poles (switches 1-3) are pulled up to 2.5V, and one pole (switch 4) is pulled up to 1.5V, when closed.

X-Ref Target - Figure 1-17

VCC2V5 VCC1V5_FPGA

S2

5

6

7

8

4

3

2

1

GPIO_SWITCH_3

GPIO_SWITCH_2

GPIO_SWITCH_1

GPIO_SWITCH_0

SDMX-4-X

2 2 2 2

1 1 1 1

Figure 1-17:

User DIP Switch S2

Table 1-25:

User DIP Switch Connections

U1 FPGA Pin Schematic Net Name

C18

Y6

W6

E4

GPIO_SWITCH_0

GPIO_SWITCH_1

GPIO_SWITCH_2

GPIO_SWITCH_3

DIP Switch Pin

S2.1

S2.2

S2.3

S2.4

UG526_17 _102609

46

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SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012

X-Ref Target - Figure 1-18

Detailed Description

User SIP Header

The SP605 includes a 6-pin single-inline (SIP) male pin header (J55) for FPGA GPIO access.

Four pins of J55 are wired to the FPGA through 200

Ω series resistors and a level shifter, and the remaining two J55 pins are wired to 3.3V and GND. The J55 header is described in

Figure 1-18 and Table 1-26 .

VCC1V5_FPGA VCC3V3

U1 FPGA Pin

G7

H6

D1

R7

GPIO_HEADER_0_LS

GPIO_HEADER_1_LS

GPIO_HEADER_2_LS

GPIO_HEADER_3_LS

NC

NC

NC

NC

U52

3

4

5

2

1

8

9

10

6

7

VCCA

A1

A2

A3

A4

A5

A6

A7

A8

OE

VCCB

B1

B2

B3

B4

B5

B6

B7

B8

GND

19

20

18

17

16

15

14

13

12

11

TXB0108

NC

NC

NC

NC

GPIO_HEADER_0

GPIO_HEADER_1

GPIO_HEADER_2

GPIO_HEADER_3

1

C384

X5R

2 10V

0.1UF

GPIO_HEADER_0

GPIO_HEADER_1

GPIO_HEADER_2

GPIO_HEADER_3

3

4

5

6

HDR_1x6

J55

1

2

DNP

VCC3V3

UG526_18 _092409

Figure 1-18:

User SIP Header J55

Table 1-26:

User SIP Header Connections

U1 FPGA Pin Schematic Net Name GPIO Header Pin

G7

H6

D1

R7

GPIO_HEADER_0

GPIO_HEADER_1

GPIO_HEADER_2

GPIO_HEADER_3

J55.1

J55.2

J55.3

J55.4

GND

VCC3V3

J55.5

J55.6

Notes:

1. Each GPIO_HEADER_n signal is sourced from the FPGA as

<netname>_LS to a level shifter, then to the J55 header.

2. Each GPIO_HEADER_n net has a 200

Ω series resistor between the level shifter and its respective header pin.

SP605 Hardware User Guide

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47

Chapter 1: SP605 Evaluation Board

User SMA GPIO

The SP605 includes an pair of SMA connectors for GPIO as described in Figure 1-19

and

Table 1-27

.

X-Ref Target - Figure 1-19

USER_SMA_GPIO_N

USER_SMA_GPIO_P

1

J39

32K10K-400E3

GND1

SIG

GND2

GND3

GND4

GND5

GND6

GND7

2

3

4

5

6

7

8

1

32K10K-400E3

SIG

GND1

GND2

GND3

GND4

J40

GND5

GND6

GND7

5

6

7

8

2

3

4

Figure 1-19:

User SMA GPIO

UG526_19 _092409

Table 1-27:

User SMA Connections

U1 FPGA Pin Schematic Net Name

A3

B3

USER_SMA_GPIO_N

USER_SMA_GPIO_P

GPIO SMA Pin

J39.1

J40.1

48

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SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012

Detailed Description

17. Switches

The SP605 Evaluation board includes the following switches:

Power On/Off Slide Switch SW2

FPGA_PROG_B Pushbutton SW3 (Active-Low)

SYSACE_RESET_B Pushbutton SW9 (Active-Low)

System ACE CF CompactFlash Image Select DIP Switch S1 (Active-High)

Mode DIP Switch SW1 (Active-High)

Power On/Off Slide Switch SW2

SW2 is the SP605 board main power on/off switch. Sliding the switch actuator from the off to on position applies 12V power from either J18 (6-pin Mini-Fit) or J27 (4-pin ATX) power connector to the VCC12_P power plane. Green LED DS14 will illuminate when the SPL605

board power is on. See 19. Power Management, page 55

for details on the on-board power system.

X-Ref Target - Figure 1-20

VCC12_P

J18

12v

12v

N/C

N/C

COM

COM

39-30-1060

1

5

3

4

2

6

NC

NC

VCC12_P_IN

1 +

C280

330UF

2

16V

ELEC

2

5

DPDT

1

3

4

6

NC

NC

SW2

1201M2S3ABE2

1

2

R322

1.00K

1%

1/16W

PCIe

Power

ATX Peripheral Cable Connector can plug into J27 when SP605 is in PC and the desk top AC adapter

(brick) is not used.

J27

12V

COM

COM

5V

3

4

1

2

NC

350211-1

CAUTION!

DO NOT plug a PC ATX power supply 6-pin connector into the J18 connector on the SP605 board. The ATX 6-pin connector has a different pinout than J18 and will damage the SP605 board and void the board warranty.

DO NOT plug an auxilliary PCIe 6-pin molex power connector into the J18 connector as this could damage the

PCIe motherboard and/or the SP605 board. J18 is marked with a NO PCIE POWER label to warn users of the potential hazard.

DO NOT apply power to J18 and the 4-pin ATX disk drive connector J27 at the same time as this will damage the

SP605 board.

UG526_20 _100609

Figure 1-20:

Power On/Off Slide Switch SW2

SP605 Hardware User Guide

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49

Chapter 1: SP605 Evaluation Board

FPGA_PROG_B Pushbutton SW3 (Active-Low)

The SW3 switch ( Figure 1-21

) grounds the FPGA PROG_B pin when pressed. This action clears the FPGA. See the Spartan-6 FPGA data sheet for more information on clearing the contents of the FPGA.

X-Ref Target - Figure 1-21

VCC2V5

1

2

R17

4.7K

5%

1/16W

FPGA_PROG_B

Pushbutton

1

P1

2

P2

SW3

P4

4

P3

3

UG526_21 _092409

Figure 1-21:

FPGA PROG_B Pushbutton SW3

SYSACE_RESET_B Pushbutton SW9 (Active-Low)

When the System ACE CF configuration mode pin is high (enabled by closing DIP switch

S1 switch 4), the System ACE CF controller configures the FPGA from the CompactFlash card when a card is inserted or the SYSACE RESET button is pressed. See

5. System ACE

CF and CompactFlash Connector, page 23

for more details.

X-Ref Target - Figure 1-22

SYSACE_RESET_B

20

Silkscreen:

"SYSACE RESET"

Pushbutton

1

P1 P4

4

2

P2

SW9

P3

3

UG526_22 _092409

Figure 1-22:

System ACE CF RESET_B Pushbutton SW9

50

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SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012

Detailed Description

System ACE CF CompactFlash Image Select DIP Switch S1 (Active-High)

System ACE CF CompactFlash (CF) image select DIP switch S1, switches 1–3 (

Figure 1-23 )

select which CF resident bitstream image is downloaded to the FPGA. S1 switches 1–3 offer eight binary addresses. When ON (high), the S1 switch 4 enables the System ACE CF controller to configure the FPGA from the CompactFlash card when a card is inserted or

the SYSACE RESET button is pressed. See 5. System ACE CF and CompactFlash

Connector, page 23

for more details.

X-Ref Target - Figure 1-23

VCC2V5

1 1 1 1

2 2 2 2

5

6

7

8

S1

SDMX-4-X

4

3

2

1

2 2 2 2

SYSACE_CFGMODEPIN

SYSACE_CFGADDR2

SYSACE_CFGADDR1

SYSACE_CFGADDR0

1 1 1 1

UG526_23 _102709

Figure 1-23:

System ACE CF CompactFlash Image Select DIP Switch S1

SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012 www.xilinx.com

51

Chapter 1: SP605 Evaluation Board

Mode DIP Switch SW1 (Active-High)

DIP switch SW1 sets the FPGA mode as shown in Figure 1-24

and Table 1-32, page 60 .

X-Ref Target - Figure 1-24

VCC2V5

FPGA_M0_CMP_MISO

FPGA_M1

1

2

1/16W

5%

200

R138

4

3

1

2

R8

1.0K

5%

1/10W

1

2

SW1

R9

1.0K

5%

SDMX-2-X

1/10W

2

1

1/16W

5%

200

R139

2

1

UG526_24 _092409

Figure 1-24:

FPGA Mode DIP Switch SW1

References

For more information, refer to the Spartan-6 FPGA Configuration User Guide [Ref 2] . See

Table 1-32, page 60 for the configuration modes.

52

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SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012

Detailed Description

18. VITA 57.1 FMC LPC Connector

The SP605 implements the Low Pin Count (LPC, J2) connector option of the VITA 57.1.1

FMC specification.

Note:

The FMC LPC J2 connector is a keyed connector oriented so that a plug-on card faces away from the SP605 board.

The FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low

Pin Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector form factor is used for both versions. The HPC version is fully populated with 400 pins present, and the LPC version is partially populated with 160 pins.

The 10 x 40 rows of a FMC LPC connector provides connectivity for:

• 68 single-ended or 34 differential user defined signals

• 1 MGT

• 1 MGT clock

• 2 differential clocks

• 61 ground, 10 power connections

Of the above signal and clock connectivity capability, the SP605 implements the full set:

• 34 differential user-defined pairs

• 34 LA pairs

• 1 MGT

• 1 MGT clock

• 2 differential clocks

Note:

The SP605 board VADJ voltage for the FMC LPC connector J2 is fixed at 2.5V (nonadjustable). The 2.5V rail cannot be turned off. The SP605 VITA 57.1 FMC interfaces are compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.

SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012 www.xilinx.com

53

Chapter 1: SP605 Evaluation Board

Table 1-28

shows the VITA 57.1 FMC LPC connections. The connector pinout is in

Appendix C, VITA 57.1 FMC LPC Connector Pinout .

G12

G13

G15

G16

G2

G3

G6

G7

G9

G10

G18

G19

C23

C26

C27

C30

C31

C15

C18

C19

C22

Table 1-28:

VITA 57.1 FMC LPC Connections

J63 FMC

LPC Pin

Schematic Net Name

U1 FPGA

Pin

J63 FMC

LPC Pin

C2

C3

C6

FMC_DP0_C2M_P

FMC_DP0_C2M_N

FMC_DP0_M2C_P

B16

A16

D15

D1

D4

D5

D8

C7

C10

C11

C14

FMC_DP0_M2C_N

FMC_LA06_P

FMC_LA06_N

FMC_LA10_P

C15

D4

D5

H10

D9

D11

D12

D14

FMC_LA10_N

FMC_LA14_P

FMC_LA14_N

FMC_LA18_CC_P

FMC_LA18_CC_N

FMC_LA27_P

FMC_LA27_N

IIC_SCL_MAIN

IIC_SDA_MAIN

H11

C17

A17

T12

U12

AA10

T21

R22

D15

D17

D18

D20

D21

D23

AB10 D24

D26

D27

FMC_CLK1_M2C_P

FMC_CLK1_M2C_N

FMC_LA00_CC_P

FMC_LA00_CC_N

FMC_LA03_P

FMC_LA03_N

FMC_LA08_P

FMC_LA08_N

FMC_LA12_P

FMC_LA12_N

FMC_LA16_P

FMC_LA16_N

B20

A20

H13

G13

E16

F16

G9

F10

B18

A18

C5

A5

H2

H4

H5

H7

H8

H10

H11

H13

H14

H16

H17

H19

Schematic Net Name

FMC_PWR_GOOD_FLASH_RST_B

FMC_GBTCLK0_M2C_P

FMC_GBTCLK0_M2C_N

FMC_LA01_CC_P

FMC_LA01_CC_N

FMC_LA05_P

FMC_LA05_N

FMC_LA09_P

FMC_LA09_N

FMC_LA13_P

FMC_LA13_N

FMC_LA17_CC_P

FMC_LA17_CC_N

FMC_LA23_P

FMC_LA23_N

FMC_LA26_P

FMC_LA26_N

FMC_PRSNT_M2C_L

FMC_CLK0_M2C_P

FMC_CLK0_M2C_N

FMC_LA02_P

FMC_LA02_N

FMC_LA04_P

FMC_LA04_N

FMC_LA07_P

FMC_LA07_N

FMC_LA11_P

FMC_LA11_N

FMC_LA15_P

AB11

U9

V9

U14

U13

F8

G16

F17

Y11

U1 FPGA

Pin

V13

E12

F12

F14

F15

C4

A4

F7

A19

B2

A2

H14

Y16

H12

G11

G8

F9

C19

G15

D18

54

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SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012

Detailed Description

Table 1-28:

VITA 57.1 FMC LPC Connections (Cont’d)

J63 FMC

LPC Pin

Schematic Net Name

U1 FPGA

Pin

J63 FMC

LPC Pin

G21

G22

G24

G25

FMC_LA20_P

FMC_LA20_N

FMC_LA22_P

FMC_LA22_N

R9

R8

V7

W8

H20

H22

H23

H25

G27

G28

G30

G31

FMC_LA25_P

FMC_LA25_N

FMC_LA29_P

FMC_LA29_N

W14

Y14

T15

U15

H26

H28

H29

H31

G33

G34

G36

G37

FMC_LA31_P

FMC_LA31_N

FMC_LA33_P

FMC_LA33_N

U16

V15

H32

H34

Y17 H35

AB17 H37

H38

Schematic Net Name

FMC_LA15_N

FMC_LA19_P

FMC_LA19_N

FMC_LA21_P

FMC_LA21_N

FMC_LA24_P

FMC_LA24_N

FMC_LA28_P

FMC_LA28_N

FMC_LA30_P

FMC_LA30_N

FMC_LA32_P

FMC_LA32_N

Table 1-29:

Power Supply Voltages for LPC Connector

Voltage Supply Voltage

Number of Pins

Maximum

Current

VADJ

VIO_B_M2C

Fixed 2.5V

NC

2

0

2A

0A

VREF_A_M2C

VREF_B_M2C

3P3VAUX

3P3V

12P0V

0-VADJ

NC

3.3V

3.3V

12V

1

0

1

4

2

0.001A

0A

0.020A

3A

1A

Tolerance

±5%

N/A

±2%

N/A

± 5%

±5%

±5%

19. Power Management

AC Adapter and 12V Input Power Jack/Switch

The SP605 is powered from a 12V source that is connected through a 6-pin (2X3) right angle

Mini-Fit type connector J18. The AC-to-DC power supply included in the kit has a mating

6-pin plug.

When the SP605 is installed into a table top or tower PC's PCIe slot, the SP605 is typically powered from the PC ATX power supply. One of the PC’s ATX hard disk type 4-pin power connectors is plugged into SP605 connector J27. The SP605 can be powered with the AC power adapter (plugged into J18) even when plugged into a PC PCIe motherboard slot;

U1 FPGA

Pin

D19

R11

T11

V11

W11

AA14

AB14

AA16

AB16

Y15

AB15

W17

Y18

SP605 Hardware User Guide

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55

Chapter 1: SP605 Evaluation Board however, users are cautioned not to also connect a PC ATX type 4-pin power connector to

J27. See the caution notes below and in Figure 1-20, page 49 .

Caution!

Caution! DO NOT plug a PC ATX power supply 6-pin connector into SP605 connector J18.The ATX 6-pin connector has a different pinout than SP605 J18, and connecting the ATX 6-pin connector will damage the SP605 and void the board warranty.

Caution!

DO NOT apply power to 6-pin Mini-Fit type connector J18 and 4-pin ATX disk drive type connector J27 at the same time as this will damage the SP605 board. Refer to

Figure 1-20, page 49 for details. The SP605 Power can be turned on or off through the board mounted slide

switch SW2. When the switch is in the on position, a green LED (DS14) is illuminated.

56

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SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012

Detailed Description

Onboard Power Regulation

Figure 1-25

shows the SP605 onboard power supply architecture. The SP605 uses Texas

Instruments power controllers for primary core power control and monitoring.

X-Ref Target - Figure 1-25

Power Supply

12V

PWR

Jack

J18 or J27

Linear Regulator U5

[email protected] max

TL1963AKTTR

Op Amps

Linear Regulator U49

3.0V@500mA max

LT1763CS8

Power Controller 1 U26

UCD9240PFC

Switching Module U18

VCCINT 1.2V@10A max

PTD08A010W

Switching Module U20

VCCAUX 2.5V@10A max

PTD08A010W

Switching Module U19

VCC 2.5V@10A max

PTD08A010W

SPI x4 Memory

FPGA

FPGA

FPGA

Linear Regulator U44

1.8V@500mA max

TL1963A-18DCQR

Power Controller 2 U27

UCD9240PFC

Switching Module U22

3.3V@10A max

PTD08A010W

Switching Module U21

1.5V@10A max

PTD08A010W

Linear FLash Memory

System Power

DDR3 Memory

1.5V

10K

10K

0.75Vref

3.3V

Linear Regulator U51

MGT AVCC 1.2V@3A max

TPS74401

MGTs

Sink/Source Regulator U11

0.75 VTT/VREF@3A max

TPS51200DRCT

DDR3 Memory Terminations

UG526_25_100509

Figure 1-25:

Onboard Power Regulators

SP605 Hardware User Guide

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57

Chapter 1: SP605 Evaluation Board

Table 1-30:

Onboard Power System Devices

Device Type

Reference

Designator

Description

UCD9240PFC

(1)

PTD08A010W

U26

U18

PMBus Controller - Core (Addr = 52)

Power Rail Net

Name

10A 0.6V - 3.6V Adj. Switching Regulator VCCINT_FPGA

Power Rail

Voltage (V)

Schematic

Page

1.20

(3)

21

22

PTD08A010W

PTD08A010W

U19

U20

10A 0.6V - 3.6V Adj. Switching Regulator VCC2V5_FPGA

10A 0.6V - 3.6V Adj. Switching Regulator VCCAUX

2.50

2.50

23

24

UCD9240PFC

(2)

PTD08A010W

PTD08A010W

U27

U21

U22

PMBus Controller - Core (Addr = 53)

10A 0.6V - 3.6V Adj. Switching Regulator VCC1V5_FPGA

10A 0.6V - 3.6V Adj. Switching Regulator VCC3V3

1.50

3.30

26

29

30

TL1963AKTTR

TPS74401

TPS51200DRCT

TPS51200DRCT

TL1963-18DCQR

LT1763CS8

TPS73633DBVT

U5

U51

U11

U11

U44

U49

U10

1.5A 12V IN, 5.0V OUT Linear Regulator

3A 1.5V IN, 1.2V OUT Linear Regulator

3A DDR3 VTERM Tracking Linear

Regulator

10 mA Tracking Reference output

1.5A 2.5V IN, 1.8V OUT Linear Regulator

500 mA 5V IN, 3.0V OUT Linear

Regulator

400 mA 5V IN, 3.30V OUT Linear

Regulator

VCC5

MGT_AVCC

VTTDDR

VTTVREF

VCC1V8

VCC3V0

DVI_VCCA

5.00

1.20

0.75

0.75

1.80

3.00

3.30

Notes:

1. See Table 1-31 ., part 1 (addr 52)

2. See Table 1-31 ., part 2 (addr 53)

3. V

CCINT

tolerance meets or exceeds the V

CCINT

±5% specification in the Recommended Operating Conditions table in the

Spartan-6 FPGA Data Sheet. [Ref 1]

21

27

31

31

31

31

17

Table 1-31:

Power Rail Specifications (UCD9240 PMBus Controllers at Addresses 52 and 53)

Device Rail #

Rail

Name

Schematic

Rail Name

Vout

(V)

PG On

(V)

PG Off

(V)

On

Delay

(ms)

Rise

(ms)

Off

Delay

Fall

(ms)

Vout

Over

Fault

(V)

Iout

Over

Fault

(A)

Temp

Over

Fault

(°C)

UCD9240

(Addr 52)

UCD9240

(Addr 53)

1

2

3

1

2

Rail

#1

Rail

#2

Rail

#3

Rail

#1

Rail

#2

VCCINT

_FPGA

VCC2V5

_FPGA

VCC1V5

_FPGA

VCC3V3

1.2

1.14

1.104

2.5

2.375

VCCAUX 2.5

2.375

2.3

2.3

1.5

1.425

1.38

3.3

3.135

3.036

0

0

10

10

0

0

10

10

1.344

2.8

1.68

3.696

Shut down

Shut down

14

13.203

Shut down

Shut down

80

80

Shut down

Shut down

58

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SP605 Hardware User Guide

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Detailed Description

Voltage and current monitoring and control are available for selected power rails through

Texas Instruments' Fusion Digital Power™ graphical user interface (GUI). Both onboard TI power controllers are wired to the same PMBus. The PMBus connector, J1, is provided for use with the TI USB Interface Adapter PMBus pod (TI part number EVM USB-TO-GPIO; refer to http://focus.ti.com/docs/toolsw/folders/print/usb-to-gpio.html

). The SP605 board is shipped with a TI flyer containing information that allows the user to purchase this EVM at a discount.

TI provides the Fusion Digital Power Designer software package

( http://focus.ti.com/docs/toolsw/folders/print/fusion_digital_power_designer.html

) which includes several tools capable of communicating with the UCD92xx series of controllers from a Windows-based host computer via the PMBus pod. The SP605 onboard connector J1 is wired for the TI EVM interface and provides access to the PMBUS and

UCD9240s for monitoring purposes. This is the simplest and most convenient way to

monitor the power rails. See Table 1-30 and Table 1-31 .

For details concerning the use of the Fusion software tool, refer to the documentation offered in the Fusion Digital Power Designer GUI help system (select Help

Documentation and Help Center

).

References

For more detailed information about this technology and the various power management controllers and regulator modules offered by Texas Instruments, visit http://www.ti.com/ww/en/analog/digital-power/index.html

.

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59

Chapter 1: SP605 Evaluation Board

Configuration Options

The FPGA on the SP605 Evaluation Board can be configured by the following methods:

3. SPI x4 Flash, page 19

4. Linear BPI Flash, page 21

5. System ACE CF and CompactFlash Connector, page 23

6. USB JTAG, page 25

For more information, refer to the Spartan-6 FPGA Configuration User Guide.

[Ref 2]

Table 1-32:

SP605 FPGA Configuration Modes

Configuration

Mode

M[1:0] Bus Width

CCLK

Direction

Configuration Solution User Guide Section

Master Serial/SPI

01

1, 2, 4

(1)

Output

SPI X4 Memory U32 (J46 on), or

External SPI Header J17 (J46 off)

3. SPI x4 Flash

Master

SelectMAP/BPI

(2)

00

8, 16 Output Linear Flash Memory U25 (BPI)

4. Linear BPI Flash

JTAG

(3)

Slave SelectMAP

(2)

Slave Serial

(4) xx

10

11

1

8, 16

1

Input

(TCK)

Input

Input

Xilinx Platform Cable USB plugged into J4

System ACE CF Controller and

CompactFlash Card

Not Supported

6. USB JTAG

5. System ACE CF and

CompactFlash Connector

Notes:

1. Utilizing dual and quad SPI modes.

2. Parallel configuration mode bus is auto-detected by the configuration logic.

3. Spartan-6 devices also have a dedicated four-wire JTAG (IEEE Std 1149.1) port that is always available to the FPGA regardless of the mode pin settings.

4. Default setting due to internal pull-up termination on Mode pins.

With the mode switch SW1 set to 01, the SP605 will attempt to boot or load a bitstream from either the SPI X4 Flash device U32 or a user supplied SPI Flash memory mezzanine card installed on the SPI programming header J17, depending on the SPI select jumper J46 configuration, as shown in

Table 1-32

. With the mode set to 00, the SP605 will attempt to boot or load a bitstream from Linear Flash device U25 (BPI).

With the mode switch SW1 set to 10, if a CompactFlash (CF) card is installed in the CF socket U37, System ACE CF will attempt to load a bitstream from the CF card image address pointed to by the image select switch S1. With no CF card present, the SP605 can be

configured via the onboard JTAG controller and USB download cable as described in 6.

USB JTAG, page 25 .

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Appendix A

References

This appendix provides references to documentation supporting Spartan-6 FPGAs, tools, and IP.

For additional information, see www.xilinx.com/support/documentation/index.htm

.

Xilinx documents supporting the SP605 Evaluation Board:

1.

DS162 , Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

2.

UG380

, Spartan-6 FPGA Configuration User Guide

3.

UG388 , Spartan-6 FPGA Memory Controller User Guide

4.

DS570 , XPS Serial Peripheral Interface (SPI) Data Sheet

5.

DS080 , System ACE CompactFlash Solution Data Sheet

6.

UG386 , Spartan-6 FPGA GTP Transceivers User Guide

7.

UG138 , LogiCORE™ IP Tri-Mode Ethernet MAC v4.2 User Guide

8.

DS606

,

XPS IIC Bus Interface Data Sheet

9.

UG381 , Spartan-6 FPGA SelectIO Resources User Guide

10.

DS614 , Clock Generator (v3.01a) Data Sheet

11.

DS643 , Multi-Port Memory Controller (MPMC) (v5.02a) Data Sheet

Additional documentation:

12.

Micron Technology, Inc.

, DDR3 SDRAM Specification (MT41J64M16LA-187E)

13.

Winbond , Serial Flash Memory Data Sheet ( W25Q64VSFIG)

14.

Numonyx , StrataFlash Embedded Memory Data Sheet (JS28F256P30)

15.

SiTime , Oscillator Data Sheet (SiT9102AI-243N25E200.00000)

16.

PCI SIG , PCI Express Specifications

17.

Marvell , Alaska Gigabit Ethernet Transceivers Product Page

18.

ST Micro , M24C08 Data Sheet

61 SP605 Hardware User Guide

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Appendix A: References

62

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Appendix B

Default Jumper and Switch Settings

Table B-33

shows the default switch settings and Table B-34, page 64 shows the default

jumper settings for the SP605.

Table B-33:

Default Switch Settings

REFDES Function/Type

SW2

SW1

S1

S2

Board power slide-switch

FPGA mode 2-pole DIP switch, Slave SelectMAP default selects System ACE CF configuration

2

1

M1 = 1

M0 = 0

System ACE CF configuration and image select

4-pole DIP switch

4

3

2

1

SysAce Mode = 1

SysAce CFGAddr2 = 0

SysAce CFGAddr1 = 0

SysAce CFGAddr0 = 0

User GPIO 4-pole DIP switch

4

3

2

1

Default

off on off on off off off off off off off

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Appendix B: Default Jumper and Switch Settings

Table B-34:

Default Jumper Settings

Jumper

REFDES

Function

FMC JTAG

Bypass

J19

SFP Module

J22

J44

SPI Memory

Select

J46

System ACE

CF Error LED

J60 exclude FMC LPC connector J2

SFP Full BW

SFP Enabled

SPI Select SPI X4 Memory U32

System ACE CF Error LED DS18 Enabled

Default

Jump 1-2

Jump 1-2

Jump 1-2

Jump 1-2

Jump 1-2

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Appendix C

VITA 57.1 FMC LPC Connector Pinout

X-Ref Target - Figure C-26

29

30

31

32

25

26

27

28

21

22

23

24

17

18

19

20

37

38

39

40

33

34

35

36

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

K J

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC

NC

NC

NC

NC

NC

NC

NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC

NC

NC

NC

NC

NC

NC

NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

Figure C-26

shows the pinout of the FMC LPC connector. Pins marked NC are not connected.

H

LA11_N

G ND

LA15_P

LA15_N

G ND

LA19_P

LA19_N

G ND

LA21_P

LA21_N

G ND

LA24_P

LA24_N

G ND

LA28_P

LA28_N

VR EF_A_M2C

PR SNT_M2C_L

GND

CLK0_M2C _P

CLK0_M2C _N

GND

LA02_P

LA02_N

GND

LA04_P

LA04_N

G ND

LA07_P

LA07_N

G ND

LA11_P

G ND

LA30_P

LA30_N

G ND

LA32_P

LA32_N

G ND

VADJ

G

GND

LA16_P

LA16_N

GND

LA20_P

LA20_N

GND

LA22_P

LA22_N

GND

LA25_P

LA25_N

GND

LA29_P

LA29_N

GND

GND

C LK1_M2C_P

C LK1_M2C_N

GND

GND

LA00_P _C C

LA00_N_C C

GND

LA03_P

LA03_N

GND

LA08_P

LA08_N

GND

LA12_P

LA12_N

LA31_P

LA31_N

GND

LA33_P

LA33_N

GND

VADJ

G ND

F E D

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC NC

P G_C2M

G ND

NC NC G ND

NC NC G BTCLK0_M2C _P

NC NC G BTCLK0_M2C _N

NC NC G ND

G ND NC NC

NC NC

NC

NC

NC

NC

NC NC

NC

LA01_P _C C

LA01_N_C C

GND

LA05_P

LA05_N

GND

LA09_P

LA09_N

GND

LA13_P

LA13_N

GND

LA17_P _C C

LA17_N_C C

GND

LA23_P

LA23_N

GND

LA26_P

LA26_N

GND

TCK

TDI

TDO

3P3VAUX

TMS

TR ST_L

G A1

3P 3V

GND

3P3V

GND

3P 3V

C

GND

LA14_P

LA14_N

G ND

G ND

LA18_P _C C

LA18_N_C C

GND

G ND

LA27_P

LA27_N

G ND

GND

S CL

S DA

GND

G ND

DP 0_C2M_P

DP 0_C2M_N

GND

GND

DP 0_M2C_P

DP 0_M2C_N

G ND

G ND

LA06_P

LA06_N

GND

G ND

LA10_P

LA10_N

G ND

G ND

GA0

12P0V

GND

12P0V

G ND

3P3V

GND

UG526_26_092709

B A

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

Figure C-26:

FMC LPC Connector Pinout

For more information, refer to the VITA 57.1 FMC LPC Connections table (

Table 1-28

).

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65

Appendix C: VITA 57.1 FMC LPC Connector Pinout

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Appendix D

SP605 Master UCF

The UCF template is provided for designs that target the SP605. Net names provided in the constraints below correlate with net names on the SP605 schematic. On identifying the appropriate pins, the net names below should be replaced with net names in the user RTL.

See the Constraints Guide for more information.

The latest version of the UCF can be found on the SP605 board documentation website at http://www.xilinx.com/sp605 .

NET "CLK_33MHZ_SYSACE" LOC = "N19"; ## 93 on U17

NET "CPU_RESET" LOC = "H8"; ## 2 on SW6 pushbutton (active-high)

##

NET "DVI_D0" LOC = "K16"; ## 63 on U31 (thru series R39 47.5 ohm)

NET "DVI_D1" LOC = "U19"; ## 62 on U31 (thru series R38 47.5 ohm)

NET "DVI_D2" LOC = "T20"; ## 61 on U31 (thru series R37 47.5 ohm)

NET "DVI_D3" LOC = "N16"; ## 60 on U31 (thru series R36 47.5 ohm)

NET "DVI_D4" LOC = "P16"; ## 59 on U31 (thru series R35 47.5 ohm)

NET "DVI_D5" LOC = "M17"; ## 58 on U31 (thru series R34 47.5 ohm)

NET "DVI_D6" LOC = "M18"; ## 55 on U31 (thru series R33 47.5 ohm)

NET "DVI_D7" LOC = "R15"; ## 54 on U31 (thru series R32 47.5 ohm)

NET "DVI_D8" LOC = "R16"; ## 53 on U31 (thru series R31 47.5 ohm)

NET "DVI_D9" LOC = "P17"; ## 52 on U31 (thru series R30 47.5 ohm)

NET "DVI_D10" LOC = "P18"; ## 51 on U31 (thru series R29 47.5 ohm)

NET "DVI_D11" LOC = "R17"; ## 50 on U31 (thru series R28 47.5 ohm)

NET "DVI_DE" LOC = "J17"; ## 2 on U31 (thru series R40 47.5 ohm)

NET "DVI_GPIO1" LOC = "D22"; ## 18 on U31

NET "DVI_H" LOC = "J16"; ## 4 on U31 (thru series R41 47.5 ohm)

NET "DVI_RESET_B" LOC = "L15"; ## 13 on U31

NET "DVI_V" LOC = "B22"; ## 5 on U31 (thru series R42 47.5 ohm)

NET "DVI_XCLK_N" LOC = "C22"; ## 56 on U31

NET "DVI_XCLK_P" LOC = "C20"; ## 57 on U31

##

NET "FLASH_A0" LOC = "N22"; ## 29 on U25

NET "FLASH_A1" LOC = "N20"; ## 25 on U25

NET "FLASH_A2" LOC = "M22"; ## 24 on U25

NET "FLASH_A3" LOC = "M21"; ## 23 on U25

NET "FLASH_A4" LOC = "L19"; ## 22 on U25

NET "FLASH_A5" LOC = "K20"; ## 21 on U25

NET "FLASH_A6" LOC = "H22"; ## 20 on U25

NET "FLASH_A7" LOC = "H21"; ## 19 on U25

NET "FLASH_A8" LOC = "L17"; ## 8 on U25

NET "FLASH_A9" LOC = "K17"; ## 7 on U25

NET "FLASH_A10" LOC = "G22"; ## 6 on U25

NET "FLASH_A11" LOC = "G20"; ## 5 on U25

NET "FLASH_A12" LOC = "K18"; ## 4 on U25

NET "FLASH_A13" LOC = "K19"; ## 3 on U25

NET "FLASH_A14" LOC = "H20"; ## 2 on U25

NET "FLASH_A15" LOC = "J19"; ## 1 on U25

NET "FLASH_A16" LOC = "E22"; ## 55 on U25

NET "FLASH_A17" LOC = "E20"; ## 18 on U25

NET "FLASH_A18" LOC = "F22"; ## 17 on U25

NET "FLASH_A19" LOC = "F21"; ## 16 on U25

NET "FLASH_A20" LOC = "H19"; ## 11 on U25

NET "FLASH_A21" LOC = "H18"; ## 10 on U25

NET "FLASH_A22" LOC = "F20"; ## 9 on U25

NET "FLASH_A23" LOC = "G19"; ## 26 on U25

NET "FPGA_D0_DIN_MISO_MISO1" LOC = "AA20"; ## 34 on U25, 8 on U32 (thru series R132 100 ohm), 6 on J17

NET "FPGA_D1_MISO2" LOC = "R13"; ## 36 on U25, 3 on J17

NET "FPGA_D2_MISO3" LOC = "T14"; ## 39 on U25, 2 on J17

NET "FLASH_D3" LOC = "AA6"; ## 41 on U25

NET "FLASH_D4" LOC = "AB6"; ## 47 on U25

NET "FLASH_D5" LOC = "Y5"; ## 49 on U25

NET "FLASH_D6" LOC = "AB5"; ## 51 on U25

NET "FLASH_D7" LOC = "W9"; ## 53 on U25

NET "FLASH_D8" LOC = "T7"; ## 35 on U25

NET "FLASH_D9" LOC = "U6"; ## 37 on U25

NET "FLASH_D10" LOC = "AB19"; ## 40 on U25

NET "FLASH_D11" LOC = "AA18"; ## 42 on U25

NET "FLASH_D12" LOC = "AB18"; ## 48 on U25

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67

Appendix D: SP605 Master UCF

NET "FLASH_D13" LOC = "Y13"; ## 50 on U25

NET "FLASH_D14" LOC = "AA12"; ## 52 on U25

NET "FLASH_D15" LOC = "AB12"; ## 54 on U25

NET "FLASH_WAIT" LOC = "T18"; ## 56 on U25

NET "FLASH_WE_B" LOC = "R20"; ## 14 on U25

NET "FLASH_OE_B" LOC = "P22"; ## 32 on U25

NET "FLASH_CE_B" LOC = "P21"; ## 30 on U25

NET "FLASH_ADV_B" LOC = "T19"; ## 46 on U25

## NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "V13"; ## 44 on U25 (this signal goes to multiple destinations, see below)

##

NET "FMC_CLK0_M2C_N" LOC = "G11"; ## H5 on J2

NET "FMC_CLK0_M2C_P" LOC = "H12"; ## H4 on J2

NET "FMC_CLK1_M2C_N" LOC = "F16"; ## G3 on J2

NET "FMC_CLK1_M2C_P" LOC = "E16"; ## G2 on J2

NET "FMC_DP0_C2M_N" LOC = "A16"; ## C3 on J2

NET "FMC_DP0_C2M_P" LOC = "B16"; ## C2 on J2

NET "FMC_DP0_M2C_N" LOC = "C15"; ## C7 on J2

NET "FMC_DP0_M2C_P" LOC = "D15"; ## C6 on J2

NET "FMC_GBTCLK0_M2C_N" LOC = "F12"; ## D5 on J2

NET "FMC_GBTCLK0_M2C_P" LOC = "E12"; ## D4 on J2

## NET "IIC_SCL_MAIN" LOC = "T21"; ## C30 on J2 (this signal goes to multiple destinations, see below)

## NET "IIC_SDA_MAIN" LOC = "R22"; ## C31 on J2 (this signal goes to multiple destinations, see below)

NET "FMC_LA00_CC_N" LOC = "F10"; ## G7 on J2

NET "FMC_LA00_CC_P" LOC = "G9"; ## G6 on J2

NET "FMC_LA01_CC_N" LOC = "F15"; ## D9 on J2

NET "FMC_LA01_CC_P" LOC = "F14"; ## D8 on J2

NET "FMC_LA02_N" LOC = "F9"; ## H8 on J2

NET "FMC_LA02_P" LOC = "G8"; ## H7 on J2

NET "FMC_LA03_N" LOC = "A18"; ## G10 on J2

NET "FMC_LA03_P" LOC = "B18"; ## G9 on J2

NET "FMC_LA04_N" LOC = "A19"; ## H11 on J2

NET "FMC_LA04_P" LOC = "C19"; ## H10 on J2

NET "FMC_LA05_N" LOC = "A4"; ## D12 on J2

NET "FMC_LA05_P" LOC = "C4"; ## D11 on J2

NET "FMC_LA06_N" LOC = "D5"; ## C11 on J2

NET "FMC_LA06_P" LOC = "D4"; ## C10 on J2

NET "FMC_LA07_N" LOC = "A2"; ## H14 on J2

NET "FMC_LA07_P" LOC = "B2"; ## H13 on J2

NET "FMC_LA08_N" LOC = "A20"; ## G13 on J2

NET "FMC_LA08_P" LOC = "B20"; ## G12 on J2

NET "FMC_LA09_N" LOC = "F8"; ## D15 on J2

NET "FMC_LA09_P" LOC = "F7"; ## D14 on J2

NET "FMC_LA10_N" LOC = "H11"; ## C15 on J2

NET "FMC_LA10_P" LOC = "H10"; ## C14 on J2

NET "FMC_LA11_N" LOC = "G15"; ## H17 on J2

NET "FMC_LA11_P" LOC = "H14"; ## H16 on J2

NET "FMC_LA12_N" LOC = "G13"; ## G16 on J2

NET "FMC_LA12_P" LOC = "H13"; ## G15 on J2

NET "FMC_LA13_N" LOC = "F17"; ## D18 on J2

NET "FMC_LA13_P" LOC = "G16"; ## D17 on J2

NET "FMC_LA14_N" LOC = "A17"; ## C19 on J2

NET "FMC_LA14_P" LOC = "C17"; ## C18 on J2

NET "FMC_LA15_N" LOC = "D19"; ## H20 on J2

NET "FMC_LA15_P" LOC = "D18"; ## H19 on J2

NET "FMC_LA16_N" LOC = "A5"; ## G19 on J2

NET "FMC_LA16_P" LOC = "C5"; ## G18 on J2

NET "FMC_LA17_CC_N" LOC = "AB11"; ## D21 on J2

NET "FMC_LA17_CC_P" LOC = "Y11"; ## D20 on J2

NET "FMC_LA18_CC_N" LOC = "U12"; ## C23 on J2

NET "FMC_LA18_CC_P" LOC = "T12"; ## C22 on J2

NET "FMC_LA19_N" LOC = "T11"; ## H23 on J2

NET "FMC_LA19_P" LOC = "R11"; ## H22 on J2

NET "FMC_LA20_N" LOC = "R8"; ## G22 on J2

NET "FMC_LA20_P" LOC = "R9"; ## G21 on J2

NET "FMC_LA21_N" LOC = "W11"; ## H26 on J2

NET "FMC_LA21_P" LOC = "V11"; ## H25 on J2

NET "FMC_LA22_N" LOC = "W8"; ## G25 on J2

NET "FMC_LA22_P" LOC = "V7"; ## G24 on J2

NET "FMC_LA23_N" LOC = "V9"; ## D24 on J2

NET "FMC_LA23_P" LOC = "U9"; ## D23 on J2

NET "FMC_LA24_N" LOC = "AB14"; ## H29 on J2

NET "FMC_LA24_P" LOC = "AA14"; ## H28 on J2

NET "FMC_LA25_N" LOC = "Y14"; ## G28 on J2

NET "FMC_LA25_P" LOC = "W14"; ## G27 on J2

NET "FMC_LA26_N" LOC = "U13"; ## D27 on J2

NET "FMC_LA26_P" LOC = "U14"; ## D26 on J2

NET "FMC_LA27_N" LOC = "AB10"; ## C27 on J2

NET "FMC_LA27_P" LOC = "AA10"; ## C26 on J2

NET "FMC_LA28_N" LOC = "AB16"; ## H32 on J2

NET "FMC_LA28_P" LOC = "AA16"; ## H31 on J2

NET "FMC_LA29_N" LOC = "U15"; ## G31 on J2

NET "FMC_LA29_P" LOC = "T15"; ## G30 on J2

NET "FMC_LA30_N" LOC = "AB15"; ## H35 on J2

NET "FMC_LA30_P" LOC = "Y15"; ## H34 on J2

NET "FMC_LA31_N" LOC = "V15"; ## G34 on J2

NET "FMC_LA31_P" LOC = "U16"; ## G33 on J2

NET "FMC_LA32_N" LOC = "Y18"; ## H38 on J2

NET "FMC_LA32_P" LOC = "W17"; ## H37 on J2

NET "FMC_LA33_N" LOC = "AB17"; ## G37 on J2

NET "FMC_LA33_P" LOC = "Y17"; ## G36 on J2

NET "FMC_PRSNT_M2C_L" LOC = "Y16"; ## H2 on J2

NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "V13"; ## D1 on J2, 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (thru series R260 DNP), 44 of U25

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##

NET "FPGA_AWAKE" LOC = "V19"; ## 2 on DS7 LED

NET "FPGA_CCLK" LOC = "Y20"; ## 7 on J17

NET "FPGA_CMP_CLK" LOC = "V17"; ## 3 on J3

NET "FPGA_CMP_CS_B" LOC = "V18"; ## 4 on J3

NET "FPGA_CMP_MOSI" LOC = "W18"; ## 2 on J3

## NET "FPGA_D0_DIN_MISO_MISO1" LOC = "AA20"; ## this pin is part of the FLASH_nn group

## NET "FPGA_D1_MISO2" LOC = "R13"; ## this pin is part of the FLASH_nn group

## NET "FPGA_D2_MISO3" LOC = "T14"; ## this pin is part of the FLASH_nn group

NET "FPGA_DONE" LOC = "AB21"; ## 2 on DS2 LED

NET "FPGA_HSWAPEN" LOC = "C3"; ## 1 on R125 100 ohm to GND

NET "FPGA_INIT_B" LOC = "Y4"; ## 1 on DS17 (thru sereis R69 75 ohm), 78 on U17

NET "FPGA_M0_CMP_MISO" LOC = "AA21"; ## 1 on SW1 DIP switch (active-high), 1 on J3

NET "FPGA_M1" LOC = "Y19"; ## 2 on SW1 DIP switch (active-high)

NET "FPGA_MOSI_CSI_B_MISO0" LOC = "AB20"; ## 15 on U32, 5 on J17

NET "FPGA_ONCHIP_TERM1" LOC = "M7"; ## 1 on R124 DNP to GND

NET "FPGA_ONCHIP_TERM2" LOC = "K7"; ## 1 on R126 100 ohm to GND

NET "FPGA_PROG_B" LOC = "AB2"; ## 1 on SW3 pushbutton (active-high) 1 on J17, 2 on J48, 2 on R260 DNP connected to

NET "FMC_PWR_GOOD_FLASH_RST_B"

NET "FPGA_SUSPEND" LOC = "AA22"; ## 2 on J47

NET "FPGA_TCK" LOC = "A21"; ## 80 on U17

NET "FPGA_TDI" LOC = "E18"; ## 82 on U17

NET "FPGA_TMS" LOC = "D20"; ## 85 on U17

NET "FPGA_VBATT" LOC = "T16"; ## 1 on B2 (battery), 2 on D11 (charging circuit)

NET "FPGA_VTEMP" LOC = "Y3"; ## 2 on R207 150 ohm to VCC1V5

##

NET "GPIO_BUTTON0" LOC = "F3"; ## 2 on SW4 pushbutton (active-high)

NET "GPIO_BUTTON1" LOC = "G6"; ## 2 on SW7 pushbutton (active-high)

NET "GPIO_BUTTON2" LOC = "F5"; ## 2 on SW5 pushbutton (active-high)

NET "GPIO_BUTTON3" LOC = "C1"; ## 2 on SW8 pushbutton (active-high)

##

NET "GPIO_HEADER_0_LS" LOC = "G7"; ## 1 on U52 (level shifter, U52.20 <-> GPIO_HEADER_0 <-> series R280 200 ohm <-> 1 on J55

NET "GPIO_HEADER_1_LS" LOC = "H6"; ## 3 on U52 (level shifter, U52.18 <-> GPIO_HEADER_0 <-> series R281 200 ohm <-> 2 on J55

NET "GPIO_HEADER_2_LS" LOC = "D1"; ## 4 on U52 (level shifter, U52.17 <-> GPIO_HEADER_0 <-> series R282 200 ohm <-> 3 on J55

NET "GPIO_HEADER_3_LS" LOC = "R7"; ## 5 on U52 (level shifter, U52.16 <-> GPIO_HEADER_0 <-> series R283 200 ohm <-> 4 on J55

##

NET "GPIO_LED_0" LOC = "D17"; ## 2 on DS3 LED

NET "GPIO_LED_1" LOC = "AB4"; ## 2 on DS4 LED

NET "GPIO_LED_2" LOC = "D21"; ## 2 on DS5 LED

NET "GPIO_LED_3" LOC = "W15"; ## 2 on DS6 LED

##

NET "GPIO_SWITCH_0" LOC = "C18"; ## 1 on S2 DIP switch (active-high)

NET "GPIO_SWITCH_1" LOC = "Y6"; ## 2 on S2 DIP switch (active-high)

NET "GPIO_SWITCH_2" LOC = "W6"; ## 3 on S2 DIP switch (active-high)

NET "GPIO_SWITCH_3" LOC = "E4"; ## 4 on S2 DIP switch (active-high)

##

NET "IIC_SCL_DVI" LOC = "W13"; ## 15 on U31, 2 on Q7 (level shifter, Q7.3 <-> IIC_CLK_DVI_F <-> series ferrite F9

220 ohm <-> 6 on P3

NET "IIC_SDA_DVI" LOC = "AA4"; ## 14 on U31, 2 on Q8 (level shifter, Q7.3 <-> IIC_SDA_DVI_F <-> series ferrite F8

220 ohm <-> 7 on P3

NET "IIC_SCL_MAIN" LOC = "T21"; ## C30 on J2

NET "IIC_SDA_MAIN" LOC = "R22"; ## C31 on J2

NET "IIC_SCL_SFP" LOC = "E5"; ## 5 on P2

NET "IIC_SDA_SFP" LOC = "E6"; ## 4 on P2

##

NET "MEM1_A0" LOC = "K2"; ## N3 on U42

NET "MEM1_A1" LOC = "K1"; ## P7 on U42

NET "MEM1_A2" LOC = "K5"; ## P3 on U42

NET "MEM1_A3" LOC = "M6"; ## N2 on U42

NET "MEM1_A4" LOC = "H3"; ## P8 on U42

NET "MEM1_A5" LOC = "M3"; ## P2 on U42

NET "MEM1_A6" LOC = "L4"; ## R8 on U42

NET "MEM1_A7" LOC = "K6"; ## R2 on U42

NET "MEM1_A8" LOC = "G3"; ## T8 on U42

NET "MEM1_A9" LOC = "G1"; ## R3 on U42

NET "MEM1_A10" LOC = "J4"; ## L7 on U42

NET "MEM1_A11" LOC = "E1"; ## R7 on U42

NET "MEM1_A12" LOC = "F1"; ## N7 on U42

NET "MEM1_A13" LOC = "J6"; ## T3 on U42

NET "MEM1_A14" LOC = "H5"; ## T7 on U42

NET "MEM1_BA0" LOC = "J3"; ## M2 on U42

NET "MEM1_BA1" LOC = "J1"; ## N8 on U42

NET "MEM1_BA2" LOC = "H1"; ## M3 on U42

NET "MEM1_CAS_B" LOC = "M4"; ## K3 on U42

NET "MEM1_CKE" LOC = "F2"; ## K9 on U42

NET "MEM1_CLK_N" LOC = "K3"; ## K7 on U42

NET "MEM1_CLK_P" LOC = "K4"; ## J7 on U42

NET "MEM1_DQ0" LOC = "R3"; ## G2 on U42

NET "MEM1_DQ1" LOC = "R1"; ## H3 on U42

NET "MEM1_DQ2" LOC = "P2"; ## E3 on U42

NET "MEM1_DQ3" LOC = "P1"; ## F2 on U42

NET "MEM1_DQ4" LOC = "L3"; ## H7 on U42

NET "MEM1_DQ5" LOC = "L1"; ## H8 on U42

NET "MEM1_DQ6" LOC = "M2"; ## F7 on U42

NET "MEM1_DQ7" LOC = "M1"; ## F8 on U42

NET "MEM1_DQ8" LOC = "T2"; ## C2 on U42

NET "MEM1_DQ9" LOC = "T1"; ## C3 on U42

NET "MEM1_DQ10" LOC = "U3"; ## A2 on U42

NET "MEM1_DQ11" LOC = "U1"; ## D7 on U42

NET "MEM1_DQ12" LOC = "W3"; ## A3 on U42

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NET "MEM1_DQ13" LOC = "W1"; ## C8 on U42

NET "MEM1_DQ14" LOC = "Y2"; ## B8 on U42

NET "MEM1_DQ15" LOC = "Y1"; ## A7 on U42

NET "MEM1_LDM" LOC = "N4"; ## E7 on U42

NET "MEM1_LDQS_N" LOC = "N1"; ## G3 on U42

NET "MEM1_LDQS_P" LOC = "N3"; ## F3 on U42

NET "MEM1_ODT" LOC = "L6"; ## K1 on U42

NET "MEM1_RAS_B" LOC = "M5"; ## J3 on U42

NET "MEM1_RESET_B" LOC = "E3"; ## T2 on U42

NET "MEM1_UDM" LOC = "P3"; ## D3 on U42

NET "MEM1_UDQS_N" LOC = "V1"; ## B7 on U42

NET "MEM1_UDQS_P" LOC = "V2"; ## C7 on U42

NET "MEM1_WE_B" LOC = "H2"; ## L3 on U42

##

NET "PCIE_250M_N" LOC = "B10"; ## 1 on series C301 0.1uF, C300 pin 2 -> PCIE_250M_MGT1_C_N -> 17 on U48

NET "PCIE_250M_P" LOC = "A10"; ## 1 on series C300 0.1uF, C300 pin 2 -> PCIE_250M_MGT1_C_P -> 18 on U48

NET "PCIE_PERST_B_LS" LOC = "J7"; ## 6 on U52 (level shifter, U52.20 <-> PCIE_PERST_B <-> series R55 15 ohm <-> A11 on P4

NET "PCIE_RX0_N" LOC = "C7"; ## B15 on P4

NET "PCIE_RX0_P" LOC = "D7"; ## B14 on P4

NET "PCIE_TX0_N" LOC = "A6"; ## 2 on series C26 0.1uF, C26 pin 1 -> PCIE_TX0_C_N -> A17 of P4

NET "PCIE_TX0_P" LOC = "B6"; ## 2 on series C27 0.1uF, C26 pin 1 -> PCIE_TX0_C_P -> A16 of P4

##

NET "PHY_COL" LOC = "M16"; ## 114 on U46

NET "PHY_CRS" LOC = "N15"; ## 115 on U46

NET "PHY_INT" LOC = "J20"; ## 32 on U46

NET "PHY_MDC" LOC = "R19"; ## 35 on U46

NET "PHY_MDIO" LOC = "V20"; ## 33 on U46

NET "PHY_RESET" LOC = "J22"; ## 36 on U46

NET "PHY_RXCLK" LOC = "P20"; ## 7 on U46

NET "PHY_RXCTL_RXDV" LOC = "T22"; ## 4 on U46

NET "PHY_RXD0" LOC = "P19"; ## 3 on U46

NET "PHY_RXD1" LOC = "Y22"; ## 128 on U46

NET "PHY_RXD2" LOC = "Y21"; ## 126 on U46

NET "PHY_RXD3" LOC = "W22"; ## 125 on U46

NET "PHY_RXD4" LOC = "W20"; ## 124 on U46

NET "PHY_RXD5" LOC = "V22"; ## 123 on U46

NET "PHY_RXD6" LOC = "V21"; ## 121 on U46

NET "PHY_RXD7" LOC = "U22"; ## 120 on U46

NET "PHY_RXER" LOC = "U20"; ## 8 on U46

NET "PHY_TXCLK" LOC = "L20"; ## 10 on U46

NET "PHY_TXCTL_TXEN" LOC = "T8"; ## 16 on U46

NET "PHY_TXC_GTXCLK" LOC = "AB7"; ## 14 on U46

NET "PHY_TXD0" LOC = "U10"; ## 18 on U46

NET "PHY_TXD1" LOC = "T10"; ## 19 on U46

NET "PHY_TXD2" LOC = "AB8"; ## 20 on U46

NET "PHY_TXD3" LOC = "AA8"; ## 24 on U46

NET "PHY_TXD4" LOC = "AB9"; ## 25 on U46

NET "PHY_TXD5" LOC = "Y9"; ## 26 on U46

NET "PHY_TXD6" LOC = "Y12"; ## 28 on U46

NET "PHY_TXD7" LOC = "W12"; ## 29 on U46

NET "PHY_TXER" LOC = "U8"; ## 13 on U46

##

NET "PMBUS_ALERT" LOC = "D3"; ## 35 on U26, 35 on U27

NET "PMBUS_CLK" LOC = "W10"; ## 19 on U26, 19 on U27

NET "PMBUS_CTRL" LOC = "H16"; ## 36 on U26, 36 on U27

NET "PMBUS_DATA" LOC = "Y10"; ## 20 on U26, 20 on U27

##

NET "SFPCLK_QO_N" LOC = "B12"; ## 2 on series C298 0.1uF, C298 pin 1 <- SFPCLK_QO_C_N <- 6 of U47

NET "SFPCLK_QO_P" LOC = "A12"; ## 2 on series C299 0.1uF, C299 pin 1 <- SFPCLK_QO_C_P <- 7 of U47

NET "SFP_LOS" LOC = "T17"; ## 8 on P2, 1 on J14

NET "SFP_RX_N" LOC = "C13"; ## 12 on P2

NET "SFP_RX_P" LOC = "D13"; ## 13 on P2

NET "SFP_TX_DISABLE_FPGA" LOC = "Y8"; ## 3 on P2, 1 on J44

NET "SFP_TX_N" LOC = "A14"; ## 19 on P2

NET "SFP_TX_P" LOC = "B14"; ## 18 on P2

##

NET "SMA_REFCLK_N" LOC = "D11"; ##

NET "SMA_REFCLK_P" LOC = "C11"; ##

NET "SMA_RX_N" LOC = "C9"; ##

NET "SMA_RX_P" LOC = "D9"; ##

NET "SMA_TX_N" LOC = "A8"; ##

NET "SMA_TX_P" LOC = "B8"; ##

##

NET "SPI_CS_B" LOC = "AA3"; ##

##

NET "SYSACE_CFGTDI" LOC = "G17"; ##

NET "SYSACE_D0_LS" LOC = "N6"; ##

NET "SYSACE_D1_LS" LOC = "N7"; ##

NET "SYSACE_D2_LS" LOC = "U4"; ##

NET "SYSACE_D3_LS" LOC = "T4"; ##

NET "SYSACE_D4_LS" LOC = "P6"; ##

NET "SYSACE_D5_LS" LOC = "P7"; ##

NET "SYSACE_D6_LS" LOC = "T3"; ##

NET "SYSACE_D7_LS" LOC = "R4"; ##

NET "SYSACE_MPA00_LS" LOC = "V5"; ##

NET "SYSACE_MPA01_LS" LOC = "V3"; ##

NET "SYSACE_MPA02_LS" LOC = "P5"; ##

NET "SYSACE_MPA03_LS" LOC = "P4"; ##

NET "SYSACE_MPA04_LS" LOC = "H4"; ##

NET "SYSACE_MPA05_LS" LOC = "G4"; ##

NET "SYSACE_MPA06_LS" LOC = "D2"; ##

NET "SYSACE_MPBRDY_LS" LOC = "AA1"; ##

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NET "SYSACE_MPCE_LS" LOC = "W4"; ##

NET "SYSACE_MPIRQ_LS" LOC = "AA2"; ##

NET "SYSACE_MPOE_LS" LOC = "T6"; ##

NET "SYSACE_MPWE_LS" LOC = "T5"; ##

##

NET "SYSCLK_N" LOC = "K22"; ##

NET "SYSCLK_P" LOC = "K21"; ##

##

NET "USB_1_CTS" LOC = "F18"; ##

NET "USB_1_RTS" LOC = "F19"; ##

NET "USB_1_RX" LOC = "B21"; ##

NET "USB_1_TX" LOC = "H17"; ##

##

NET "USER_CLOCK" LOC = "AB13"; ##

NET "USER_SMA_CLOCK_N" LOC = "M19"; ##

NET "USER_SMA_CLOCK_P" LOC = "M20"; ##

NET "USER_SMA_GPIO_N" LOC = "A3"; ##

NET "USER_SMA_GPIO_P" LOC = "B3"; ##

Note:

1.

Pullup and pulldown resistors which branch from nets are not included

2.

Pullup and pulldown resistors to a single point power or GND are included

3.

Series resistors are included

4.

DNP = do not populate, no component will be installed on the PCB at this location

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Appendix D: SP605 Master UCF

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Appendix E

Regulatory and Compliance

Information

This product is designed and tested to conform to the European Union directives and standards described in this section.

Directives

2006/95/EC, Low Voltage Directive (LVD)

2004/108/EC, Electromagnetic Compatibility (EMC) Directive

Standards

EN standards are maintained by the European Committee for Electrotechnical

Standardization (CENELEC). IEC standards are maintained by the International

Electrotechnical Commission (IEC).

Electromagnetic Compatibility

EN 55022:2010, Information Technology Equipment Radio Disturbance Characteristics – Limits

and Methods of Measurement

EN 55024:2010, Information Technology Equipment Immunity Characteristics – Limits and

Methods of Measurement

This is a Class A product. In a domestic environment, this product can cause radio interference, in which case the user might be required to take adequate measures.

Safety

IEC 60950-1:2005, Information technology equipment – Safety, Part 1: General requirements

EN 60950-1:2006, Information technology equipment – Safety, Part 1: General requirements

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Appendix E: Regulatory and Compliance Information

Markings

This product complies with Directive 2002/96/EC on waste electrical and electronic equipment (WEEE). The affixed product label indicates that the user must not discard this electrical or electronic product in domestic household waste.

This product complies with Directive 2002/95/EC on the restriction of hazardous substances

(RoHS) in electrical and electronic equipment.

This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and

2004/108/EC, Electromagnetic Compatibility (EMC) Directive.

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