SIA Road Map and DESIGN&TEST

SIA Road Map and DESIGN&TEST
SIA Road Map
and
DESIGN&TEST
Wojciech Maly
Department of Electrical and Computer Engineering
Carnegie Mellon University
Pittsburgh, Pa. 15213.
Copyright © W. Maly
1
Objective
To discuss fundamental research in
Design and Test (D&T) of VLSI ICs
D&T Current and Future Problems
Future of IC Technology
SIA Road Map
Copyright © W. Maly
2
Outline
1. SIA Road Map
Cost of silicon will have to
consume a rapidly increasing
portion of the available profit
margins
2. Future of IC Technology
3. D&T Current and Future
Problems
New and very efficient design
strategies capable of producing
very high QUALITY IC
DESIGNS will eventually
became the key enablers of the
SIA Road Map vision.
4. Proposal of an approach
to fundamental research
problems in D&T.
Copyright © W. Maly
3
SIA Road Map
Minimum Feature Size [µm]
5
256k DRAM
(1.6 µm)
1
0.8
0.4
4M DRAM
(0.8 µm)
16M DRAM
(0.5 µm)
H
64M DRAM
(0.35 µm)
H
H
Prediction
H
0.2
0.1
Year
0.05
1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010
Copyright © W. Maly
4
1994 SIA Road Map Assumptions
Year
1995
1998
2001
2004
2007
2010
Feature size [µm]
0.35
0.25
0.18
0.12
0.1
0.08
Wafer diameter [mm]
200
200
300
300
400
400
M E M O R Y
64
256
1024
4096
16384
65536
Cost per tr. [millicents]
Chip size [mm 2 ]
Tr. per chip [10 6 ]
0.017
0.007
0.003
0.001
0.0005
0.0002
190
280
420
640
960
1400
Tr. density [10 6 # tr. / cm 2 ]
34
91
244
640
1707
4681
µ P R O C S S O R
Tr. per chip [10 6 ]
10
21
46.8
107.5
260
558
Cost per tr. [millicents]
Chip size [mm 2 ]
1
0.5
0.2
0.1
0.05
0.02
250
300
360
430
520
620
Tr. density [10 6 # tr. / cm 2 ]
4
7
13
25
50
90
Copyright © W. Maly
5
SIA Road Map
v SIA Road Map is a collective view on the future of the
microelectronics industry;
v The objective of the SIA Road Map was a consolidation of the
vision for the entire semiconductor industry;
v Such a consolidation was a necessary step in focusing industry,
governments and universities on the same technology
development objectives;
v The SIA Road Map has a strong “technology/ manufacturing/
equipment” orientation;
v The SIA Road Map is a “linear extrapolation” of the trends
known from the past;
v The SIA Road Map is a “self-fulfilling prophecy” which
facilitates continuation of the evolution of the semiconductor
industry along Moore’s Law;
Copyright © W. Maly
6
SIA Road Map: Implications
( Chip size ) X( Tr. density) = Tr. per chip
( Cost per tr.) X( Tr. per chip) = Cost per chip
( Wafer area )
= Number of chips per wafer
( Chip size )
( Yield) X (Number of chips per wafer) = Number of good chips
( Number of good chips ) X(Cost per chip) = Cost per wafer
( Cost per wafer )
= Cost per mask per sq.
(( Number of masks ) X (Wafer area ))
Copyright © W. Maly
7
SIA Road Map : MEMORY
Year
1995
1998
2001
2004
2007
Feature size [µm]
0.35
0.25
0.18
0.12
0.1
0.08
64
256
1024
4096
16384
65536
Cost per tr. [millicents]
Chip size [mm2 ]
0.017
0.007
0.003
0.001
0.0005
0.0002
190
280
420
640
960
1400
Wafer diameter [mm]
Tr. density [10 6 # tr. / cm 2 ]
200
200
300
300
400
400
34
91
244
640
1707
4681
90
Tr. per chip [10 6 ]
2010
Yield [%]
90
90
90
90
90
Number of chips per wafer
142
93
148
91
110
72
Wafer area [cm 2 ]
314
314
706.5
706.5
1256
1256
127
83
133
81
99
64
Cost per chip [$]
10.88
17.92
30.72
40.96
81.92
131.07
Cost per wafer [$]
1382
1487
4086
3318
8110
8389
Number of masks
Cost per mask per sq.[$/cm 2 ]
18
20
20
22
22
24
0.24
0.24
0.29
0.21
0.29
0.28
Number of good chips
Copyright
W. Maly
Slide ©only
for
the discussion
8
SIA Road Map : µPROCESSOR
Year
1995
1998
2001
2004
2007
Feature size [µm]
0.35
0.25
0.18
0.12
0.1
0.08
Tr. per chip [10 6 ]
10
21
46.8
107.5
260
558
Cost per tr. [millicents]
Chip size [mm 2 ]
1
0.5
0.2
0.1
0.05
0.02
250
300
360
430
520
620
Wafer diameter [mm]
Tr. density [10 6 # tr. / cm 2 ]
200
200
300
300
400
400
4
7
13
25
50
90
Yield [%]
90
90
90
90
90
90
Number of chips per wafer
104
89
168
140
211
177
Wafer area [cm 2 ]
314
314
706.5
706.5
1256
1256
Number of good chips
93
80
151
126
189
159
Cost per chip [$]
100
105
93.6
107.5
130
111.6
Cost per wafer [$]
9300
8400
14134
13545
24570
17744
Number of masks
Cost per mask per sq.[$/cm 2 ]
18
22
22
24
24
26
1.65
1.22
0.91
0.80
0.82
0.54
Copyright
W. Maly
Slide ©only
for
2010
the discussion
9
SIA Road Map Assumptions Chip Size
B
B
J
µ
B
B
J
J
J
B
Copyright © W. Maly
J
B
B
J
J
10
SIA Road Map Assumptions Transistor Density
B
B
B
B
B
J
J
B
J
J
B
J
J
J
µ
Copyright © W. Maly
11
SIA Road Map Consequences Number of Transistors
B
B
B
J
B
µ
B
J
B
J
B
J
Copyright © W. Maly
J
J
J
12
SIA Road Map Assumptions Cost
J
J
J
µ
B
J
J
J
J
B
B
B
B
B
B
Copyright © W. Maly
13
SIA Road Map Consequences Chip Cost
J
J
J
J
J
B
J
B
B
B
B
Copyright © W. Maly
B
J
µ
B
14
SIA Road Map Consequences Manufacturing Costs
Cost of Manufacturing per Layer [$/cm 2 ]
J
J
B
Cost per layer per cm 2 - µProc.
Cost per layer per cm 2 - Memory
J
J
J
J
J
B
2010
B
2007
2008
2009
2003
2002
B
2004
2005
2006
B
2000
2001
B
1997
1998
1999
B
1994
1995
1996
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Year
Copyright © W. Maly
15
SIA Road Map Consequences Manufacturing Costs
1994 SIA Road Map assumes that:
– exponential growth in die size,
– exponential growth in transistor density and
– exponential decrease in cost per transistor,
can be handled with unchanged (or even
decreased) manufacturing cost per unit square.
Is such a goal really feasible ?
Copyright © W. Maly
16
Implications of SIA Road Map: Interconnect
Year
Min.
Interconnect Interconnect
Feature Density
Length
Size
[m/cm 2/level]
[m]
[µm]
1995
0.40
35
380
1998
0.30
50
840
2001
0.22
70
2100
2004
0.15
105
4100
2007
0.11
125
6300
2010
0.08
155
10,000
Copyright © W. Maly
17
Implications of SIA Road Map: Interconnect
Metal 2
Rc
Rw
W
x 100 000 000
Rc
Al
Rc
W
Rc
Metal 1
W
C
Copyright © W. Maly
18
Implications of SIA Road Map:
Interconnect
Complexity of the interconnect will strongly affect
the methodology of DESIGN,
MANUFACTURING and TEST.
Interconnect may become a main show
stopper of the SIA Road Map.
Copyright © W. Maly
19
Silicon Wafer
Edge of the
die (3x3 cm)
R = 15 cm
1 cm
D = 100µ m
Cross-section
of a human hair
Copyright
W. Maly
Slide ©only
for
the discussion
20
Human hair
D = 100µ m
D = 0.25µ m
Contamination
Copyright
W. Maly
Slide ©only
for
the discussion
21
Implications of SIA Road Map: Manufacturing
Die Area [cm 22]
14 B
B
13
12
11
B
B
10
9
B
B
8
B
B
7
B
B
6
5
4
0.05 0.1 0.15 0.2 0.25 0.3
Feature Size [µ m]
Copyright © W. Maly
1
Y=
1 +Ach D00
D0 = 1 - Y
YAch
For Y = 70%
D0 = .43
Ach
B
B
0.35
For Y = 90%
D0 = .11
Ach
22
Implications of SIA Road Map: Manufacturing
Acceptable number of defects per wafer
B Y=70% J Y=90%
39
34
29
24
B
19
14
9
4 J
0.05
B
B
B
B
J J
J
J
No more than
B 10 defects in
400 +
manufacturing
steps !
J
0.1 0.15 0.2 0.25 0.3 0.35 Feature Size [µm]
Copyright © W. Maly
23
Implications of SIA Road Map:
Manufacturing
Complexity of IC processes must cause rapid
increase in cost of IC manufacturing.
Cost of manufacturing may become a main
show stopper on the SIA Road Map.
Copyright © W. Maly
24
SIA Road Map Consequences Transistors per Test Point
J
J
B
J
J
B
J
J
B
J
B
B
B
B
Copyright © W. Maly
25
Implications of SIA Road Map: Testing
Metal 2
Rc
Rw
W
Rc
Al
W
Rd
Rd
Metal 1
W
C
Copyright © W. Maly
26
Implications of SIA Road Map: Testing
Testing will have to handle very large devices/
systems;
v New difficult-to-detect failures will have to be tested.
v
– Data dependent cross-talk failures;
– Power bus noise generated faults;
– R-F coupling generated faults.
v
v
Very high band-width testers will be required;
Massive application of DFT will be a must.
Copyright © W. Maly
27
Implications of SIA Road Map: Testing
Complexity of ICs to be tested will soon reach levels
impossible to be handled with the testing paradigm as it is
known today.
Tester limitations may become a main show
stopper on the SIA Road Map.
Copyright © W. Maly
28
500
O
Tr. per Chip
G
Tr. per Year per Designer
O
0.5
400
0.4
300
O
G
0.3
0.2
200
O
G
100
G
O
1995
0.6
G
O
1998
O
G
2001
2004
G
0.1
2007
2010
Design Productivity [Transistors per
6
]
600
Year per Designer * 10
Number of Transistors per Chip[ 10 6 ]
Implications of SIA Road Map: Design
Year
SEMATECH
Copyright © W. Maly
29
Implications of SIA Road Map: Design
Design productivity will have to increase by
orders of magnitude;
v Design verification (on all levels of design
abstraction) will become an absolute necessity;
v
Copyright © W. Maly
30
Implications of SIA Road Map: Design
Size of ICs to be designed will soon reach levels
impossible to be handled with the design paradigm as it is
known today.
Design productivity and design verification
may become key show stoppers on the SIA
Road Map.
Copyright © W. Maly
31
SIA Road Map Consequences Manufacturing Costs
1994 SIA Road Map assumes that
the substantial increase in complexity of :
–– manufacturing,
– test and
– design,
can be handled with unchanged (or even decreased)
manufacturing cost per unit square.
Is such a goal really feasible ?
Copyright © W. Maly
32
SIA Road Map Consequences Manufacturing Costs
1994 SIA Road Map assumes that
the substantial increase in complexity of :
– manufacturing,
– test and
– design,
can be handled with unchanged (or even decreased)
manufacturing cost per unit square.
Is such a goal really feasible ?
1997 Road Map says NO !
Cost of silicon will have to consume a rapidly increasing
portion of the available profit margins.
Copyright © W. Maly
33
SIA Road Map: Implications
1000
[$/ chip]
Cost and profit
Profit margin
v
v
500
D&T
Package
It is likely that the
cost of silicon will
grow more than the
SIA Road Map
allows.
Silicon
100
1997
Copyright © W. Maly
2003
2006
34
SIA Road Map: Implications
C
Profit
margin
D&T
= C
TE
+
C
D
+ C TG
V Ch
C TE
Cost of D&T can be
substantially reduced by increasing
volume of sold chips.
C TD
C
= C
+ C Own. +
Silicon
Material
V Ch
v
v
D&T
Package
Cost of silicon cannot be reduced
beyond a certain level by increasing
volume of sold chips.
v
v
Silicon
Copyright © W. Maly
35
SIA Road Map: Implications
1000
[$/ chip]
Cost and profit
v
v
Profit margin
500
D&T
Package
It is possible that the
only market
advantage for many
IC producers will be
achievable via high
efficiency and high
quality design and
test;
Silicon
100
1997
Copyright © W. Maly
2003
2006
36
Design Quality
Intel P6 ( Kalmath)
Type:
CISC (32 bit data/instr.)
Applications: Universal (MPEG2, ...)
Load for DVD: 100 %
Technology: 0.28 µm CMOS
Clock:
233 MHz;
# Trans. Total: 7.5 M (with 32K L1 cache)
2
Area:
203 mm
Price:
TBA
(PPro - 200 MHz = $1072)
Compiled
by
Copyright
© W. Maly
Mitsubishi D30V
DSP LIW (64 bit instr.)
M-Media (MPEG2, V-ph.)
90 %
0.3 µm CMOS
250 MHz;
300 K + 64K SRAM
2
37 mm
TBA
(Est. < $50)
Pierre Paulin of ST based on the data published in EE Times and µP Rep.
37
SIA Road Map Implications
SIA Road Map will cause:
– Cost
Cost of
of silicon
silicon to
to go
go up;
up;
–– Price
Price of
of chips
chips to
to go
go up
up (but
(but with
with well
well defined
defined upper
upper limit);
limit);
–– Progress
along
Moore’s
curve
to
slow
down;
Progress along Moore’s curve to slow down;
–– Design
Design and
and test
test budgets
budgets to
to go
go down;
down;
–– Design
Design efficiency
efficiency and
and design
design quality
quality to
to become
become the
the most
most important
important
knobs
knobs in
in profit
profit maximization.
maximization.
New and very efficient design strategies
capable of producing very high QUALITY IC
DESIGNS will eventually became the key
enablers of the SIA Road Map vision.
Copyright © W. Maly
38
Outline
1. SIA Road Map
2. Future of IC Technology
3. D&T Current and Future
Problems
4. Proposal of an approach
to fundamental research
problems in D&T.
Copyright © W. Maly
39
Fundamental Problems: TEST
FUNDAMENTAL TEST PROBLEMS
INSUFFICIENT TESTING BANDWIDTH
INSUFFICIENT SPEED
OF TESTING
Tester Pin
Electronics
Tester
Architecture
Copyright © W. Maly
DECREASING CIRCUIT
OBSERVABILITY
Growing
Die Size
Too Costly
DFT
INADEQUATE TEST QUALITY
INCOMPLETE TEST
SET
Immature Test
Generation
Methodologies
SIMPLISTIC FAULT
MODELS
Too High
Complexity of
Fault Simulation
Lack of
Understanding of
Fault Mechanism
40
Fundamental Test Problem
1.0E+8
Annual Volume
[# of dies per year]
DO NOT APPLY DFT
Curve obtained for
the “best set” of
DFT parameters
High
QUALITY
Design for
Testability
(DFT)
impossible !
1.0E+7
Uncertain
region
1.0E+6
Curve obtained for
the “worst set” of
DFT parameters
APPLY DFT
1.0E+5
0.5
1
1.5
2
2.5
Die Size [cm2]
3
3.5
4
Copyright © W. Maly
41
Fundamental Test Problem
Cost of
Testing
Test
Preparation
Test
Generation
Tester
Program
Manpower Test
Card
Cost
Cost
Copyright © W. Maly
Probe
Cost
Test
Execution
DFT Hardware
Design
Tester
Probe Depreciation
Life
Volume
Imperfect Test
Quality
Test-Related
Silicon
Escape
Lost
Performance
Tester
Setup
Time
Tester
Capital
Cost
Die
Area
Wafer Wafer
Cost Radius
Lost
Yield
Defect
Density
42
Fundamental Test Problem
Cprep = Ctest _ gen + Ctest _ prog + Cdesign _ of _ DFT
Ctest _ gen =
Rman_hour Ttest _ gen
0
V
Ttest _ gen = Ktest_gen e A0
Ctest _ prog = βtest_prog Ctest _ gen
Examples of FUNDAMENTAL test problems:
v
v Lack of the theory bridging the gap between circuit design
decisions and test generation complexity.
v
v Superficial understanding of delay testing needs and principles.
v
v......................................................................................................
Copyright © W. Maly
43
Fundamental Problems: DESIGN
FUNDAMENTAL DESIGN PROBLEMS
INADEQUATE
INSUFFICIENT
DESIGN SPEC
VERIFICATION
DESIGN
INSUFFICIENT
DESIGN
x -ABILITIES
INCREASING
INCOMPLETE
RESTRICTIVENESS
DESIGN
OF DESIGN
OBJECTIVES
DOMAIN
SPECIFICATION
Copyright © W. Maly
QUALITY
DESIGN
LIMITED
VOLUME
ACCEPTANCE
OF SUBOPTIMUM
SOLUTIONS
INSUFFICIENT DESIGN
PRODUCTIVITY
INSUFFICIENT
LEVELS OF DESIGN
REUSABILITY
INADEQUATE
CAD
ENVIRONMENTS
/TOOLS
INEFFECTIVE
AND UNRELIABLE
INTRA AND INTER
DESIGN TEAM
COMMUNICATION
CHANNELS
44
Limitations of Design Domain
x 100 000 000
Metal 2
Rc
Rw
Rc
Metal 1
Rc
Rc
C
Example of a
FUNDAMENTAL
CAD problem:
Lack of adequate
design data base
which:
– Allows to model
all timing relevant
interconnect
geometry details;
– Enables efficient
parasitic extraction
in VERY large
circuits;
– ..........................
Copyright © W. Maly
45
Sub-optimum Designs
Intel P6 ( Kalmath)
CISC (32 bit data/instr.)
MPEG2
7.5 M (with 32K L1 cache)
203 mm2
Mitsubishi D30V
DSP LIW (64 bit instr.)
MPEG2
300 K + 64K SRAM
37 mm2
Is Mitsubishi design close enough to optimum ?
Example of a FUNDAMENTAL design problem:
Lack of adequate objective functions for hardwaresoftware co-design which :
– Take into account cost and time of design process;
– Forecast volume to be sold;
– Predict true cost of manufacturing.
Copyright © W. Maly
46
Conclusions
v
v
v
v
v
v
Microelectronics industry may approach a highcost-of-manufacturing-based crisis;
Design&Test may need to:
– operate with lower time and “$” budgets;
– become a main and the only provider of market
advantage;
– deliver much better designs.
Design&Test community need to re-think the
traditional view on its role and strategy;
Copyright © W. Maly
47
Conclusions
D&T Research Strategy Proposal
v
v
v
v
v
v
v
v
Community-wide collaboration;
Consensus on the initial “Vision”.
SIA Focus Center ?
Multi-disciplinary cross-domain approaches;
Step #1:
INADEQUATE
Copyright © W. Maly
FUNDAMENTAL DESIGN PROBLEMS
DESIGN
QUALITY
INSUFFICIENT DESIGN
PRODUCTIVITY
48
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