sst89x5x4rx

sst89x5x4rx
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
SST89E/V564RD SST89E/VE554RC FlashFlex51 MCU
Preliminary Specifications
FEATURES:
• 8-bit 8051 Family Compatible Microcontroller
(MCU) with Embedded SuperFlash Memory
• SST89E564RD/SST89E554RC is 5V Operation
– 0 to 40 MHz Operation at 5V
• SST89V564RD/SST89V554RC is 3V Operation
– 0 to 33 MHz Operation at 3V
• Fully Software and Development Toolset
Compatible as well as Pin-For-Pin Package
Compatible with Standard 8xC5x Microcontrollers
• 1 KByte Internal RAM
• Dual Block SuperFlash EEPROM
– SST89E564RD/SST89V564RD: 64 KByte primary block + 8 KByte secondary block
(128-Byte sector size)
– SST89E554RC/SST89V554RC: 32 KByte primary block + 8 KByte secondary block
(128-Byte sector size)
– Individual Block Security Lock
– Concurrent Operation during In-Application
Programming (IAP)
– Block Address Re-mapping
• Support External Address Range up to 64
KByte of Program and Data Memory
• Three High-Current Drive Pins (16 mA each)
• Three 16-bit Timers/Counters
• Full-Duplex Enhanced UART
– Framing error detection
– Automatic address recognition
• Nine Interrupt Sources at 4 Priority Levels
• Programmable Watchdog Timer (WDT)
• Programmable Counter Array (PCA)
• Four 8-bit I/O Ports (32 I/O Pins)
• Second DPTR register
• Low EMI Mode (Inhibit ALE)
• SPI Serial Interface
• Standard 12 Clocks per cycle, the device has an
option to double the speed to 6 clocks per cycle.
• TTL- and CMOS-Compatible Logic Levels
• Brown-out Detection
• Low Power-Saving Modes
– Idle Mode
– Power Down Mode with External Interrupt Wake-up
• PDIP-40, PLCC-44 and TQFP-44 Packages
• Temperature Ranges:
– Commercial (0°C to +70°C)
– Industrial (-40°C to +85°C)
PRODUCT DESCRIPTION
firmware for SST’s device. During the power-on reset, the
device can be configured as a slave to an external host for
source code storage or as a master to an external host for
In-Application Programming (IAP) operation. The device is
designed to be programmed “In-System” and “In-Application” on the printed circuit board for maximum flexibility. The
device is pre-programmed with an example of bootstrap
loader in the memory, demonstrating the initial user program code loading or subsequent user code updating via
the “IAP” operation. An example bootstrap loader is available for the user’s reference and convenience. SST does
not guarantee the functionality or the usefulness of the
sample bootstrap loader. Chip-Erase or Block-Erase operations will erase the pre-programmed sample code.
SST89E564RD, SST89V564RD, SST89E554RC, and
SST89V554RC are members of the FlashFlex51 family of 8bit microcontrollers. The FlashFlex51 is a family of microcontroller products designed and manufactured on the state-ofthe-art SuperFlash CMOS semiconductor process technology. The device uses the same powerful instruction set and
is pin-for-pin compatible with standard 8xC5x microcontroller
devices.
The device comes with 72/40 KByte of on-chip flash
EEPROM program memory using SST’s patented and proprietary CMOS SuperFlash EEPROM technology with the
SST’s field-enhancing, tunneling injector, split-gate memory cells. The SuperFlash memory is partitioned into 2
independent program memory blocks. The primary SuperFlash Block 0 occupies 64/32 KByte of internal program
memory space and the secondary SuperFlash Block 1
occupies 8 KByte of internal program memory space. The
8-KByte secondary SuperFlash block can be mapped to
the lowest location of the 64/32 KByte address space; it
can also be hidden from the program counter and used as
an independent EEPROM-like data memory. The flash
memory blocks can be programmed via a standard 87C5x
OTP EPROM programmer fitted with a special adapter and
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
555
1
In addition to 72/40 KByte of SuperFlash EEPROM program memory on-chip, the device can address up to 64
KByte of external program memory. In addition to 1024 x 8
bits of on-chip RAM, up to 64 KByte of external RAM can
be addressed.
SST’s highly reliable, patented SuperFlash technology and
memory cell architecture have a number of important
advantages for designing and manufacturing flash
EEPROMs. These advantages translate into significant
cost and reliability benefits for our customers.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
FlashFlex, In-Application Programming, IAP, and SoftLock are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE OF CONTENTS
PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.0 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.0 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.0 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Program Memory Block Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.1 Reset Configuration of Program Memory Block Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Dual Data Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 Special Function Registers (SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.0 FLASH MEMORY PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1 External Host Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.1 Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2 Arming Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.3 Detail Explanation of the External Host Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.4 External Host Mode Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.5 Flash Operation Status Detection Via External Host Handshake . . . . . . . . . . . . . . . . . . . . . . . .
4.1.6 Step-by-step instructions to perform
External Host Mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
29
29
30
30
30
4.2 In-Application Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
In-Application Programming Mode Clock Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Bank Selection for In-Application Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . .
IAP Enable Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In-Application Programming Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
31
31
32
32
5.0 TIMERS/COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.0 SERIAL I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1 Enhanced Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1.1 Framing Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1.2 Automatic Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
2
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
7.0 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.0 PROGRAMMABLE COUNTER ARRAY (PCA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.1 PCA Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2 PCA Compare/Capture Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
Capture Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Bit Software Timer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Speed Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
39
39
39
39
9.0 SECURITY LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.1 Hard Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.2 SoftLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.3 Security Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10.0 SYSTEM POWER AND CLOCK OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.2 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.3 Brown-out Detection Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.4 Interrupt Priority and Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.5 Power-Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.5.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.5.2 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.6 System Clock and Clock Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.6.1 Clock Input Options and Recommended Capacitor Values for Oscillator . . . . . . . . . . . . . . . . . 45
10.6.2 Clock Doubling Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11.0 ELECTRICAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.1 Operation Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.2 Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.4 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.5 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.6 Flash Memory Programming Timing Diagrams with External Host Mode . . . . . . . . . . . . . . . . . . . . . . 56
12.0 PRODUCT ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.0 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
3
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
LIST OF FIGURES
FIGURE 2-1: Pin Assignments for 40-pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FIGURE 2-2: Pin Assignments for 44-lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FIGURE 2-3: Pin Assignments for 44-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FIGURE 3-1: Program Memory Organization for SST89E564RD and SST89V564RD . . . . . . . . . . . . . . . . 10
FIGURE 3-2: Program Memory Organization for SST89E554RC and SST89V554RC . . . . . . . . . . . . . . . . 11
FIGURE 4-1: I/O Pin Assignments for External Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FIGURE 6-1: SPI Master-slave Interconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FIGURE 6-2: SPI Transfer Format with CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
FIGURE 6-3: SPI Transfer Format with CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
FIGURE 7-1: Block Diagram of Programmable Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
FIGURE 9-1: Security Lock Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
FIGURE 10-1: Power-on Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
FIGURE 10-2: Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
FIGURE 11-1: IDD Test Condition, Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
FIGURE 11-2: IDD Test Condition, Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
FIGURE 11-3: IDD Test Condition, Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
FIGURE 11-4: IDD vs. Frequency (SST89V564RD/SST89V554RC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
FIGURE 11-5: IDD vs. Frequency (SST89E564RD/SST89E554RC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
FIGURE 11-6: AC Testing Input/Output, Float Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
FIGURE 11-7: External Program Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
FIGURE 11-8: External Data Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
FIGURE 11-9: External Data Memory Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
FIGURE 11-10: External Clock Drive Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
FIGURE 11-11: Shift Register Mode Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
FIGURE 11-12: Read-ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
FIGURE 11-13: Select-Block1 / Select-Block0 (For SST89E564RD/SST89V564RD only) . . . . . . . . . . . . . 56
FIGURE 11-14: Chip-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
FIGURE 11-15: Block-Erase for SST89E564RD/SST89V564RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
FIGURE 11-16: Block-Erase for SST89E554RC/SST89V554RC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
FIGURE 11-17: Sector-Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
FIGURE 11-18: Byte-Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
FIGURE 11-19: Prog-SB1 / Prog-SB2 / Prog-SB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
FIGURE 11-20: Prog-SC0 / Prog-SC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
FIGURE 11-21: Byte-Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
4
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
LIST OF TABLES
TABLE 2-1: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TABLE 3-1: SFCF Values for Program Memory Block Switching for SST89E/V564RD . . . . . . . . . . . . . . 11
TABLE 3-2: SFCF Values for Program Memory Block Switching for SST89E/V554RC . . . . . . . . . . . . . . 12
TABLE 3-3: SFCF Values Under Different Reset Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
TABLE 3-4: FlashFlex51 SFR Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TABLE 3-5: CPU related SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TABLE 3-6: Flash Memory Programming SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TABLE 3-7: Watchdog Timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TABLE 3-8: Timer/Counters SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TABLE 3-9: Interface SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TABLE 3-10: PCA SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TABLE 3-11: PCA Module Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TABLE 4-1: External Host Mode Commands for SST89E/V564RD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TABLE 4-2: External Host Mode Commands for SST89E/9V554RC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TABLE 4-3: Signature Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TABLE 4-4: IAP Address Resolution for SST89E564RD/SST89V564RD . . . . . . . . . . . . . . . . . . . . . . . . . 31
TABLE 4-5: In-Application Programming Mode Commands for SST89E/V564RD . . . . . . . . . . . . . . . . . . 33
TABLE 4-6: In-Application Programming Mode Commands for SST89E/V554RC . . . . . . . . . . . . . . . . . . 33
TABLE 4-7: External Mode Flash Memory Programming/Verification Parameters . . . . . . . . . . . . . . . . . . 34
TABLE 8-1: Count Pulse Selected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TABLE 8-2: Possible Modes and Associated Values for CCAPMn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TABLE 9-1: Security Lock Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
TABLE 9-2: Security Lock Access Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TABLE 10-1: Interrupt Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
TABLE 10-2: Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
TABLE 10-3: Clock Doubling Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
TABLE 11-1: Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
TABLE 11-2: Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
TABLE 11-3: DC Electrical Characteristics: 40MHz devices; 4.5-5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
TABLE 11-4: DC Electrical Characteristics: 33MHz devices; 2.7-3.6V . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
TABLE 11-5: AC Electrical Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
TABLE 11-6: External Clock Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
TABLE 11-7: Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
5
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
1.0 FUNCTIONAL BLOCKS
FUNCTIONAL BLOCK DIAGRAM
Interrupt
Control
Watchdog Timer
9 Interrupts
8051
CPU Core
SuperFlash
EEPROM
Primary
Block
32K/64K x81
RAM
1K x8
Secondary
Block
8K x8
I/O
I/O Port 0
8
I/O
I/O Port 1
Security
Lock
8
I/O
I/O Port 2
8
Timer 0 (16-bits)
I/O Port 3
I/O
Timer 1 (16-bits)
SPI
Timer 2 (16-bits)
8-bit
Enhanced
UART
PCA
555 ILL B1.0
1. 64K x8 for SST89E564RD and SST89V564RD
32K x8 for SST89E554RC and SST89V554RC
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
6
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
P1.1 (T2 Ex)
2.0 PIN ASSIGNMENTS
P0.2 (AD2)
(SS#) P1.4
5
36
P0.3 (AD3)
(MOSI) P1.5
6
35
P0.4 (AD4)
(MOSI) P1.5
1
33
P0.4 (AD4)
P0.5 (AD5)
(MISO) P1.6
2
32
P0.5 (AD5)
(SCK) P1.7
3
31
P0.6 (AD6)
RST
4
30
P0.7 (AD7)
(RXD) P3.0
5
29
EA#
DNU/RSTOUTL
6
28
DNU
(TXD) P3.1
7
27
ALE/PROG#
P0.3 (AD3)
37
P0.2 (AD2)
4
P0.1 (AD1)
P0.1 (AD1)
P1.3
P0.0 (AD0)
38
VDD
3
DNU
P0.0 (AD0)
P1.2
P1.0 (T2)
VDD
39
P1.2
40
2
P1.3
1
P1.4 (SS#)
(T2) P1.0
(T2 Ex) P1.1
44 43 42 41 40 39 38 37 36 35 34
(RXD) P3.0
34
40-pin PDIP
8 Top View 33
32
9
31
10
(TXD) P3.1
11
30
ALE/PROG#
(INT0#) P3.2
12
29
PSEN#
(INT0#) P3.2
8
26
PSEN#
(INT1#) P3.3
13
28
P2.7 (A15)
(INT1#) P3.3
9
25
P2.7 (A15)
(T0) P3.4
14
27
P2.6 (A14)
(T0) P3.4
10
24
P2.6 (A14)
(T1) P3.5
23
11
12 13 14 15 16 17 18 19 20 21 22
P2.5 (A13)
25
P2.4 (A12)
17
24
P2.3 (A11)
XTAL2
18
23
P2.2 (A10)
XTAL1
19
22
P2.1 (A9)
VSS
20
21
P2.0 (A8)
(A12) P2.4
16
(RD#) P3.7
(A11) P2.3
(WR#) P3.6
(A10) P2.2
P2.5 (A13)
(A9) P2.1
26
(A8) P2.0
15
DNU/DISIAPL
(T1) P3.5
44-lead TQFP
Top View
VSS
EA#
XTAL1
P0.7 (AD7)
XTAL2
RST
P0.6 (AD6)
(RD#) P3.7
(SCK) P1.7
7
(WR#) P3.6
(MISO) P1.6
Note: DNU = Do not use, must be kept floating
555 44-tqfp TQJ P2.0
555 40-pdip PI P1.0
2 1 44 43 42 41 40
VDD
P0.3 (AD3)
3
P0.2 (AD2)
4
P0.1 (AD1)
P1.0 (T2)
5
P0.0 (AD0)
P1.1 (T2 Ex)
6
DNU
P1.2
2-2: PIN ASSIGNMENTS FOR 44-LEAD TQFP
P1.3
FIGURE
P1.4 (SS#)
2-1: PIN ASSIGNMENTS FOR 40-PIN PDIP
(MOSI) P1.5
7
39
P0.4 (AD4)
(MISO) P1.6
8
38
P0.5 (AD5)
(SCK) P1.7
9
37
P0.6 (AD6)
RST
10
36
P0.7 (AD7)
(RXD) P3.0
11
35
EA#
DNU/RSTOUTL
12
34
DNU
ALE/PROG#
44-lead PLCC
Top View
P2.6 (A14)
P2.5 (A13)
555 44-plcc NJ P3.0
30
17
29
18 19 20 21 22 23 24 25 26 27 28
(A12) P2.4
16
(T1) P3.5
(A11) P2.3
(T0) P3.4
(A10) P2.2
P2.7 (A15)
(A9) P2.1
31
(A8) P2.0
15
DNU/DISIAPL
PSEN#
(INT1#) P3.3
VSS
32
XTAL1
33
14
XTAL2
13
(RD#) P3.7
(TXD) P3.1
(INT0#) P3.2
(WR#) P3.6
FIGURE
Note: DNU = Do not use, must be kept floating
FIGURE
2-3: PIN ASSIGNMENTS FOR 44-LEAD PLCC
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
7
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
2.1 Pin Descriptions
TABLE
2-1: PIN DESCRIPTIONS (1 OF 2)
Symbol
Type1
P0[7:0]
I/O
P1[7:0]
Name and Functions
Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can
sink several LS TTL inputs. Port 0 pins float that have “1”s written to them, and in this state
can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and
data bus during accesses to external memory. In this application, it uses strong internal pullups when transitioning to VOH. Port 0 also receives the code bytes during the external host
mode programming, and outputs the code bytes during the external host mode verification.
External pull-ups are required during program verification.
I/O with internal Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers
pull-ups
can drive LS TTL inputs. Port 1 pins are pulled high by the internal pull-ups when “1”s are
written to them and can be used as inputs in this state. As inputs, Port 1 pins that are externally pulled low will source current (IIL, see Tables 11-3 and 11-4) because of the internal pullups. P1[5, 6, 7] have high current drive of 16 mA. Port 1 also receives the low-order address
bytes during the external host mode programming and verification.
P1[0]
I/O
T2: External count input to Timer/Counter 2 or Clock-out from Timer/Counter 2
P1[1]
I
T2EX: Timer/Counter 2 capture/reload trigger and direction control
P1[2]
I
ECI: PCA Timer/Counter External Input:
This signal is the external clock input for the PCA timer/counter.
P1[3]
I/O
CEX0: Compare/Capture Module External I/O
Each compare/capture module connects to a Port 1 pin for external I/O. When not used by
the PCA, this pin can handle standard I/O.
P1[4]
I/O
SS#: Master Input or Slave Output for SPI.
OR
CEX1: Compare/Capture Module External I/O
P1[5]
I/O
MOSI: Master Output line, Slave Input line for SPI
OR
CEX2: Compare/Capture Module External I/O
P1[6]
I/O
MISO: Master Input line, Slave Output line for SPI
OR
CEX3: Compare/Capture Module External I/O
P1[7]
I/O
SCK: Master clock output, slave clock input line for SPI
OR
CEX4: Compare/Capture Module External I/O
P2[7:0]
I/O with internal Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins are pulled
pull-ups
high by the internal pull-ups when “1”s are written to them and can be used as inputs in this
state. As inputs, Port 2 pins that are externally pulled low will source current (IIL, see Tables
11-3 and 11-4) because of the internal pull-ups. Port 2 sends the high-order address byte
during fetches from external Program memory and during accesses to external Data Memory
that use 16-bit address (MOVX@DPTR). In this application, it uses strong internal pull-ups
when transitioning to VOH. Port 2 also receives some control signals and a partial of highorder address bits during the external host mode programming and verification.
P3[7:0]
I/O with internal Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers
pull-ups
can drive LS TTL inputs. Port 3 pins are pulled high by the internal pull-ups when “1”s are
written to them and can be used as inputs in this state. As inputs, Port 3 pins that are externally pulled low will source current (IIL, see Tables 11-3 and 11-4) because of the internal pullups. Port 3 also receives some control signals and a partial of high-order address bits during
the external host mode programming and verification.
P3[0]
I
RXD: Serial input line
P3[1]
O
TXD: Serial output line
P3[2]
I
INT0#: External Interrupt 0 Input
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
8
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
2-1: PIN DESCRIPTIONS (CONTINUED) (2 OF 2)
Symbol
Type1
P3[3]
I
INT1#: External Interrupt 1 Input
P3[4]
I
T0: External count input to Timer/Counter 0
P3[5]
I
T1: External count input to Timer/Counter 1
P3[6]
O
WR#: External Data Memory Write strobe
P3[7]
O
RD#: External Data Memory Read strobe
PSEN#
I/O
Program Store Enable: PSEN# is the Read strobe to External Program Store. When the
device is executing from Internal Program Memory, PSEN# is inactive (VOH). When the
device is executing code from External Program Memory, PSEN# is activated twice each
machine cycle, except when access to External Data Memory while one PSEN# activation is
skipped in each machine cycle. A forced high-to-low input transition on the PSEN# pin while
the RST input is continually held high for more than ten machine cycles will cause the device
to enter External Host mode for programming.
RST
I
Reset: While the oscillator is running, a high logic state on this pin for two machine cycles will
reset the device. After a reset, if the PSEN# pin is driven by a high-to-low input transition
while the RST input pin is held high, the device will enter the External Host mode, otherwise
the device will enter the Normal operation mode.
EA#
I
External Access Enable: EA# must be driven to VIL in order to enable the device to fetch
code from the External Program Memory. EA# must be driven to VIH for internal program execution. However, Security lock level 4 will disable EA#, and program execution is only possible from internal program memory. The EA# pin can tolerate a high voltage2 of 12V
(see “Absolute Maximum Stress Ratings” on page 46).
ALE/PROG#
I/O
Address Latch Enable: ALE is the output signal for latching the low byte of the address during accesses to external memory. This pin is also the programming pulse input (PROG#) for
the external host mode. ALE is activated twice each machine cycle, except when access to
External Data Memory, one ALE activation is skipped in the second machine cycle. However,
if AO is set to 1, ALE is disabled. (see “Auxiliary Register (AUXR)” on page 20)
DNU
I/O
DNU: Do not use, must be kept floating. In Figure 2-2 and Figure 2-3, RSTOUTL and
DISIAPL are used while the device is in normal operation. These two pins must be kept floating while the device is in external host mode.
RSTOUTL
O with internal
pull-ups
Name and Functions
RSTOUTL: This pin is active low during the watchdog timer reset and the brown-out reset.
DISIAPL
I
DISIAPL: If this pin is driven to VIL, the IAP function will be disable.
XTAL1
XTAL2
I
O
Oscillator: Input and output to the inverting oscillator amplifier. XTAL1 is input to internal
clock generation circuits from an external clock source.
VDD
I
Power Supply: Supply voltage during normal, Idle, and Power Down operations.
VSS
I
Ground: Circuit ground. (0V reference)
T2-1.1 555
1. I = Input; O = Output
2. It is not necessary to receive a 12V programming supply voltage during flash programming.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
9
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
3.0 MEMORY ORGANIZATION
The device has separate address spaces for program and
data memory.
Bank Selection. Please refer to Figure 3-1 and Figure 3-2
for the program memory configurations. Program Bank
Select is described in the next section.
3.1 Program Memory
The 64K/32K x8 primary SuperFlash block is organized as
512/256 sectors, each sector consists of 128 Bytes.
There are two internal flash memory blocks in the device.
The primary flash memory block (Block 0) has 64/32
KByte. The secondary flash memory block (Block 1) has 8
KByte. Since the total program address space is limited to
64/32 KByte, the SFCF[1:0] bit are used to control Program
The 8K x8 secondary SuperFlash block is organized as 64
sectors, each sector consists also of 128 Bytes.
For both blocks, the 7 least significant program address bits
select the byte within the sector. The remainder of the program address bits select the sector within the block.
EA# = 1
SFCF[1:0] = 00
EA# = 0
FFFFH
FFFFH
EA# = 1
SFCF[1:0] = 01, 10, 11
FFFFH
56 KByte
Block 0
64 KByte
Block 0
External
64 KByte
2000H
1FFFH
8 KByte
Block 1
0000H
0000H
0000H
555 ILL F02.0
FIGURE
3-1: PROGRAM MEMORY ORGANIZATION
FOR
©2002 Silicon Storage Technology, Inc.
SST89E564RD AND SST89V564RD
S71207-01-000 3/02
10
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
FFFFH
FFFFH
FFFFH
EA# = 1
SFCF[1:0] = 01
EA# = 1
SFCF[1:0] = 00
EA# = 0
8 KByte
Block 1
8 KByte
Block 1
E000H
DFFFH
E000H
External
32 KByte
DFFFH
External
24 KByte
External
64 KByte
EA# = 1
SFCF[1:0] = 10, 11
FFFFH
External
24 KByte
8000H
7FFFH
8000H
7FFFH
8000H
7FFFH
24 KByte
Block 0
2000H
32 KByte
Block 0
32 KByte
Block 0
1FFFH
8 KByte
Block 1
0000H
0000H
0000H
0000H
555 ILL F03.2
FIGURE
3-2: PROGRAM MEMORY ORGANIZATION
FOR
SST89E554RC AND SST89V554RC
3.2 Program Memory Block Switching
The program memory block switching feature of the device
allows either Block 1 or the lowest 8 KByte of Block 0 to be
used for the lowest 8 KByte of the program address space.
SFCF[1:0] controls program memory block switching.
TABLE
3-1: SFCF VALUES
FOR
PROGRAM MEMORY BLOCK SWITCHING
FOR
SST89E564RD/SST89V564RD
SFCF[1:0]
Program Memory Block Switching
01, 10, 11
Block 1 is not visible to the PC;
Block 1 is reachable only via In-Application Programming from 000H - 1FFFH.
00
Block 1 is overlaid onto the low 8K of the program address space; occupying address locations 0000H - 1FFFH.
When the PC falls within 0000H - 1FFFH, the instruction will be fetched from Block 1 instead of Block 0.
Outside of 0000H - 1FFFH, Block 0 is used. Locations 0000H - 1FFFH of Block 0 are reachable through
In-Application Programming.
T3-1.0 555
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
11
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
3-2: SFCF VALUES
SFCF[1:0]
10, 11
FOR
PROGRAM MEMORY BLOCK SWITCHING
FOR
SST89E554RC/SST89V554RC
Program Memory Block Switching
Block 1 is not visible to the PC;
Block 1 is reachable only via In-Application Programming from E000H - FFFFH.
01
Both Block 0 and Block 1 are visible to the PC.
Block 0 is occupied from 0000H - 7FFFH. Block 1 is occupied from E000H - FFFFH.
00
Block 1 is overlaid onto the low 8K of the program address space; occupying address locations 0000H - 1FFFH.
When the PC falls within 0000H - 1FFFH, the instruction will be fetched from Block 1 instead of Block 0.
Outside of 0000H - 1FFFH, Block 0 is used. Locations 0000H - 1FFFH of Block 0 are reachable through
In-Application Programming.
T3-2.0 555
3.3 Data Memory
3.2.1 Reset Configuration of Program Memory
Block Switching
The device has 1024 x8 bits of on-chip RAM and can
address up to 64 KByte of external data memory.
Program memory block switching is initialized after reset
according to the state of the Start-up Configuration bit SC0.
The SC0 bit is programmed via an External Host Mode
command or an IAP Mode command. See Table 4-2 and
Table 4-6.
The device has four sections of internal data memory:
1. The lower 128 Bytes of RAM (00H to 7FH) are
directly and indirectly addressable.
Once out of reset, the SFCF[0] bit can be changed dynamically by the program for desired effects. Changing SFCF[0]
will not change the SC0 bit.
2. The higher 128 Bytes of RAM (80H to FFH) are
indirectly addressable.
3. The Special Function Registers (SFRs, 80H to
FFH) are directly addressable only.
Caution must be taken when dynamically changing the
SFCF[0] bit. Since this will cause different physical memory
to be mapped to the logical program address space. The
user must avoid executing block switching instructions
within the address range 0000H to 1FFFH.
TABLE
4. The expanded RAM of 768 Bytes (00H to 2FFH) is
indirectly addressable by the move external
instruction (MOVX) and clearing the EXTRAM bit.
(See “Auxiliary Register (AUXR)” on page 20)
3-3: SFCF VALUES UNDER DIFFERENT
RESET CONDITIONS
3.4 Dual Data Pointers
The device has two 16-bit data pointers. The DPTR Select
(DPS) bit in AUXR1 determines which of the two data
pointers is accessed. When DPS=0, DPTR0 is selected;
when DPS=1, DPTR1 is selected. Quickly switching
between the two data pointers can be accomplished by a
single INC instruction on AUXR1.
State of SFCF[1:0] after:
Power-on
or
External
Reset
WDT
Reset
or
Brown-out
Reset
Software
Reset
SC11
SC0
1
1
00
(default)
x0
10
1
0
01
x1
11
0
1
10
10
10
0
0
11
11
3.5 Special Function Registers (SFR)
Most of the unique features of the FlashFlex51 microcontroller family are controlled by bits in special function registers (SFRs) located in the SFR Memory Map shown in
Table 3-4. Individual descriptions of each SFR are provided
and Reset values indicated in Tables 3-5 to 3-9.
11
T3-3.0 555
1. SC1 only applies to SST89E554RC and SST89V554RC.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
12
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
3-4: FLASHFLEX51 SFR MEMORY MAP
8 BYTES
F8H
IPA1
F0H
B1
E8H
IEA1
CH
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
CL
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
CMOD
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
T2MOD
RCAP2L
RCAP2H
TL2
FFH
IPAH
E0H
ACC1
D8H
CCON1
D0H
PSW1
C8H
T2CON1
C0H
WDTC1
B8H
IP1
B0H
P31
SFCF
SFCM
A8H
IE1
SADDR
SPSR
A0H
P21
98H
SCON1
90H
P11
88H
TCON1
TMOD
TL0
TL1
80H
P01
SP
DPL
DPH
F7H
EFH
E7H
DFH
SPCR
D7H
TH2
CFH
C7H
SADEN
BFH
SFAL
SFAH
SFDT
SFST
IPH
B7H
AFH
AUXR1
A7H
SBUF
9FH
97H
TH0
TH1
AUXR
WDTD
SPDR
8FH
PCON
87H
T3-4.1 555
1. SFRs are bit addressable.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
13
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
3-5: CPU
RELATED
Symbol Description
SFRS
Direct
Address
Bit Address, Symbol, or Alternative Port Function
MSB
LSB
RESET
Value
ACC1
Accumulator
B1
B Register
F0H
PSW1
Program Status
Word
D0H
SP
Stack Pointer
81H
SP[7:0]
07H
DPL
Data Pointer
Low
82H
DPL[7:0]
00H
DPH
Data Pointer
High
83H
DPH[7:0]
00H
IE1
Interrupt Enable
A8H
EA
EC
ET2
ES0
ET1
EX1
ET0
EX0
40H
IEA1
Interrupt
Enable A
E8H
-
-
-
-
EBO
-
-
-
xxxx0xxxb
IP1
Interrupt Priority
Reg
B8H
-
PPC
PT2
PS
PT1
PX1
PT0
PX0
x0000000b
IPH
Interrupt Priority
Reg High
B7H
-
PPCH
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
x0000000b
IPA1
Interrupt Priority
Reg A
F8H
-
-
-
-
PBO
-
-
-
xxxx0xxxb
IPAH
Interrupt Priority
Reg A High
F7H
-
-
-
-
PBO
H
-
-
-
xxxx0xxxb
PCON
Power Control
87H
BOF
POF
GF1
GF0
PD
IDL
00010000b
AUXR
Auxiliary Reg
8EH
-
-
-
-
-
-
EXTRAM
AO
xxxxxxx00b
AUXR1
Auxiliary Reg 1
A2H
-
-
-
-
GF2
0
-
DPS
xxxx00x0b
E0H
ACC[7:0]
00H
B[7:0]
CY
AC
SMOD1 SMOD0
F0
RS1
00H
RS0
OV
F1
P
00H
T3-5.1 555
1. Bit Addressable SFRs
TABLE
3-6: FLASH MEMORY PROGRAMMING SFRS
Symbol Description
Bit Address, Symbol, or Alternative Port Function
Direct
Address
MSB
LSB
RESET
Value
SFST
SuperFlash
Status
B6H
SECD1
SECD2
SECD3
-
-
FLASH_BUSY
-
-
xxxxx0xxb
SFCF
SuperFlash
Configuration
B1H
-
IAPEN
-
-
-
-
SWR
BSEL
x0xxxxxxb
SFCM
SuperFlash
Command
B2H
FIE
SFDT
SuperFlash
Data
B5H
SuperFlash Data Register
00H
SFAL
SuperFlash
Address Low
B3H
SuperFlash Low Order Byte Address Register - A7 to A0 (SFAL)
00H
SFAH
SuperFlash
Address High
B4H
SuperFlash High Order Byte Address Register - A15 to A8 (SFAH)
00H
FCM
00H
T3-6.0 555
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
14
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
3-7: WATCHDOG TIMER SFRS
Direct
Address
Symbol
Description
WDTC1
Watchdog Timer
Control
C0H
WDTD
Watchdog Timer
Data/Reload
85H
Bit Address, Symbol, or Alternative Port Function
MSB
-
-
-
WDOUT
WDRE
WDTS
WDT
LSB
RESET
Value
SWDT
xxx00x00b
Watchdog Timer Data/Reload
00H
T3-7.0 555
1. Bit Addressable SFRs
TABLE
3-8: TIMER/COUNTERS SFRS
Direct
Address
Symbol
Description
TMOD
Timer/Counter
Mode Control
89H
TCON1
Timer/Counter
Control
88H
TH0
Timer 0 MSB
8CH
TL0
Timer 0 LSB
TH1
Timer 1 MSB
TL1
Timer 1 LSB
Bit Address, Symbol, or Alternative Port Function
MSB
LSB
Timer 1
Timer 0
RESET
Value
00H
GATE
C/T#
M1
M0
GATE
C/T#
M1
M0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00H
TH0[7:0]
00H
8AH
TL0[7:0]
00H
8DH
TH1[7:0]
00H
8BH
TL1[7:0]
T2CON1 Timer / Counter 2
Control
C8H
TF2
T2MOD# Timer2
Mode Control
C9H
-
EXF2 RCLK TCLK EXEN2
-
-
-
-
00H
TR2
-
C/T2# CP/RL2#
T2OE
DCEN
00H
xxxxxx00b
TH2
Timer 2 MSB
CDH
TH2[7:0]
00H
TL2
Timer 2 LSB
CCH
TL2[7:0]
00H
RCAP2H Timer 2 Capture MSB
CBH
RCAP2H[7:0]
00H
RCAP2L Timer 2 Capture LSB
CAH
RCAP2L[7:0]
00H
T3-8.0 555
1. Bit Addressable SFRs
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
15
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
3-9: INTERFACE SFRS
Symbol Description
SBUF
Serial Data Buffer
SCON1
Serial Port Control
Direct
Address
Bit Address, Symbol, or Alternative Port Function
MSB
LSB
99H
98H
SBUF[7:0]
SM0/FE
SM1
SM2
REN
RESET
Value
Indeterminate
TB8
RB8
TI
RI
00H
SADDR Slave Address
A9H
SADDR#[7:0]
00H
SADEN Slave Address
Mask
B9H
SADEN#[7:0]
00H
SPCR
SPI Control
Register
D5H
SPIE
SPE
SPSR
SPI Status
Register
AAH
SPIF
WCOL
SPDR
SPI Data Register
86H
SPD7
SPD6
SPD5
P01
Port 0
80H
P11
Port 1
90H
-
-
-
-
P21
Port 2
A0H
P31
Port 3
B0H
RD#
WR#
T1
T0
DORD MSTR CPOL CPHA SPR1 SPR0
04H
00H
SPD4
SPD3
SPD2
SPD1 SPD0
00H
T2EX
T2
FFH
TXD
RXD
P0[7:0]
FFH
-
-
P2[7:0]
FFH
INT1# INT0#
FFH
T3-9.0 555
1. Bit Addressable SFRs
TABLE 3-10: PCA SFRS
Direct
Address MSB
Bit Address, Symbol, or Alternative Port Function
LSB
RESET
Value
Symbol
Description
CH
CL
PCA Timer/Counter
F9H
E9H
CCON1
PCA Timer/Counter
Control Register
D8H
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0
00x00000b
CMOD
PCA Timer/Counter
Mode Register
D9H
CIDL
WDTE
-
-
-
CPS1
CPS0
ECF
00xxx000b
CH[7:0]
CL[7:0]
00H
00H
CCAP0H PCA Module 0
CCAP0L Compare/Capture
Registers
FAH
CCAP0H[7:0]
00H
EAH
CCAP0L[7:0]
00H
CCAP1H PCA Module 1
CCAP1L Compare/Capture
Registers
FBH
CCAP1H[7:0]
00H
EBH
CCAP1L[7:0]
00H
CCAP2H PCA Module 2
CCAP2L Compare/Capture
Registers
FCH
CCAP2H[7:0]
00H
ECH
CCAP2L[7:0]
00H
CCAP3H PCA Module 3
CCAP3L Compare/Capture
Registers
FDH
CCAP3H[7:0]
00H
EDH
CCAP3L[7:0]
00H
CCAP4H PCA Module 4
CCAP4L Compare/Capture
Registers
FEH
CCAP4H[7:0]
00H
EEH
CCAP4L[7:0]
00H
CCAPM0 PCA
CCAPM1 Compare/Capture
Module Mode
CCAPM2
Registers
CCAPM3
CCAPM4
DAH
-
ECOM0 CAPP0 CAPN0 MAT0
TOG0 PWM0 ECCF0 x000 0000b
DBH
-
ECOM1 CAPP1 CAPN1 MAT1
TOG1 PWM1 ECCF1 x000 0000b
DCH
-
ECOM2 CAPP2 CAPN2 MAT2
TOG2 PWM2 ECCF2 x000 0000b
DDH
-
ECOM3 CAPP3 CAPN3 MAT3
TOG3 PWM3 ECCF3 x000 0000b
DEH
-
ECOM4 CAPP4 CAPN4 MAT4
TOG4 PWM4 ECCF4 x000 0000b
T3-10.1 555
1. Bit Addressable SFRs
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
16
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
SuperFlash Status Register (SFST) (Read Only Register)
Location
7
6
5
4
3
2
1
0
Reset Value
0B6H
SECD1
SECD2
SECD3
-
-
FLASH_BUSY
-
-
xxxxx0xxb
Symbol
Function
SECD1
Security bit 1.
SECD2
Security bit 2.
SECD3
Security bit 3.
Please refer to Table 9-1 for security lock options.
FLASH_BUSY Flash operation completion polling bit.
1: Device is busy with flash operation.
0: Device has fully completed the last command.
SuperFlash Configuration Register (SFCF)
Location
7
6
5
4
3
2
1
0
Reset Value
0B1H
-
IAPEN
-
-
-
-
SWR
BSEL
x0xxxxxxb
Symbol
Function
IAPEN
Enable IAP operation
0: IAP commands are disabled
1: IAP commands are enabled
SWR
Software Reset
See “10.2 Software Reset” on page 42
BSEL
Program memory block switching bit
See Figures 3-1 and 3-2.
SuperFlash Command Register (SFCM)
Location
7
6
5
4
3
2
1
0
Reset Value
0B2H
FIE
FCM6
FCM5
FCM4
FCM3
FCM2
FCM1
FCM0
00000000b
Symbol
Function
FIE
Flash Interrupt Enable.
0: INT1# is not reassigned.
1: INT1# is re-assigned to signal IAP operation completion.
External INT1# interrupts are ignored.
FCM[6:0]
Flash operation command
000_0001b
000_1011b
000_1101b
000_1100b
000_1110b
000_1111b
000_0011b
000_0101b
000_1001b
Chip-Erase
Sector-Erase
Block-Erase
Byte-Verify1
Byte-Program
Prog-SB1
Prog-SB2
Prog-SB3
Prog-SC0
000_1000b Enable-Clock-Double
All other combinations are not implemented, and reserved for future use.
1. Byte-Verify has a single machine cycle latency and will not generate any INT1# interrupt regardless of
FIE.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
17
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
SuperFlash Data Register (SFDT)
Location
7
6
5
0B5H
4
3
2
1
0
Reset Value
SuperFlash Data Register
00000000b
Symbol
Function
SFDT
Mailbox register for interfacing with flash memory block. (Data register).
SuperFlash Address Registers (SFAL)
Location
7
6
0B3H
5
4
3
2
1
0
Reset Value
SuperFlash Low Order Byte Address Register
00000000b
Symbol
Function
SFAL
Mailbox register for interfacing with flash memory block. (Low order address register).
SuperFlash Address Registers (SFAH)
Location
7
6
0B4H
5
4
3
2
1
0
Reset Value
SuperFlash High Order Byte Address Register
00000000b
Symbol
Function
SFAH
Mailbox register for interfacing with flash memory block. (High order address register).
Interrupt Enable (IE)
Location
7
6
5
4
3
2
1
0
Reset Value
A8H
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
00H
Symbol
Function
EA
Global Interrupt Enable.
0 = Disable
1 = Enable
EC
PCA Interrupt Enable.
ET2
Timer 2 Interrupt Enable.
ES
Serial Interrupt Enable.
ET1
Timer 1 Interrupt Enable.
EX1
External 1 Interrupt Enable.
ET0
Timer 0 Interrupt Enable.
EX0
External 0 Interrupt Enable.
Interrupt Enable A (IEA)
Location
7
6
5
4
3
2
1
0
Reset Value
E8H
-
-
-
-
EBO
-
-
-
xxxx0xxxb
Symbol
Function
EBO
Brown-out Interrupt Enable.
1 = Enable the interrupt
0 = Disable the interrupt
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
18
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
Interrupt Priority (IP)
Location
7
6
5
4
3
2
1
0
Reset Value
B8H
-
PPC
PT2
PS
PT1
PX1
PT0
PX0
x0000000b
Symbol
Function
PPC
PCA interrupt priority bit.
PT2
Timer 2 interrupt priority bit.
PS
Serial Port interrupt priority bit.
PT1
Timer 1 interrupt priority bit.
PX1
External interrupt 1 priority bit.
PT0
Timer 0 interrupt priority bit.
PX0
External interrupt 0 priority bit.
Interrupt Priority High (IPH)
Location
7
6
5
4
3
2
1
0
Reset Value
B7H
-
PPCH
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
x0000000b
Symbol
Function
PPCH
PCA interrupt priority bit high.
PT2H
Timer 2 interrupt priority bit high.
PSH
Serial Port interrupt priority bit high.
PT1H
Timer 1 interrupt priority bit high.
PX1H
External interrupt 1 priority bit high.
PT0H
Timer 0 interrupt priority bit high.
PX0H
External interrupt 0 priority bit high.
Interrupt Priority A (IPA)
Location
7
6
5
4
3
2
1
0
Reset Value
F8H
-
-
-
-
PBO
-
-
-
xxxx0xxxb
Symbol
Function
PBO
Brown-out interrupt priority bit.
Interrupt Priority A High (IPAH)
Location
7
6
5
4
3
2
1
0
Reset Value
F7H
-
-
-
-
PBOH
-
-
-
xxxx0xxxb
Symbol
Function
PBOH
Brown-out Interrupt priority bit high.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
19
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
Auxiliary Register (AUXR)
Location
7
6
5
4
3
2
1
0
Reset Value
8EH
-
-
-
-
-
-
EXTRAM
AO
xxxxxx00b
Symbol
Function
EXTRAM
0: Internal Expanded RAM access. For details, refer to “Data Memory” on page 12.
1: External data memory access.
AO
0: Normal ALE
1: ALE is normally off. ALE is active only during a MOVX or MOVC instruction. This will reduce
EMI.
Auxiliary Register 1 (AUXR1)
Location
7
6
5
4
3
2
1
0
Reset Value
A2H
-
-
-
-
GF2
0
-
DPS
xxxx00x0b
Symbol
Function
GF2
General purpose user-defined flag.
DPS
DPTR registers select bit.
0: DPTR0 is selected.
1: DPTR1 is selected.
Watchdog Timer Control Register (WDTC)
Location
7
6
5
4
3
2
1
0
Reset Value
0C0H
-
-
-
WDOUT
WDRE
WDTS
WDT
SWDT
xxx00x00b
Symbol
Function
WDOUT
Watchdog output enable.
0: Watchdog reset will not be exported on Reset pin.
1: Watchdog reset if enabled by WDRE, will assert Reset pin for 32 clocks.
WDRE
Watchdog timer reset enable.
0: Disable watchdog timer reset.
1: Enable watchdog timer reset.
WDTS
Watchdog timer reset flag.
0: External hardware reset clears the flag.
Flag can also be cleared by writing a 1.
Flag survives if chip reset happened because of watchdog timer overflow.
1: Hardware sets the flag on watchdog overflow.
WDT
Watchdog timer refresh.
0: Hardware resets the bit when refresh is done.
1: Software sets the bit to force a watchdog timer refresh.
SWDT
Start watchdog timer.
0: Stop WDT.
1: Start WDT.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
20
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
Watchdog Timer Data/Reload Register (WDTD)
Location
7
6
5
085H
4
3
2
1
0
Reset Value
Watchdog Timer Data/Reload
00000000b
Symbol
Function
WDTD
Initial/Reload value in Watchdog Timer. New value won’t be effective until WDT is set.
PCA Timer/Counter Control Register (CCON)
Location
7
6
5
4
3
2
1
0
Reset Value
D8H
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0
00x00000b
Symbol
Function
CF
PCA Timer/Counter Overflow Flag:
Set by hardware when the PCA timer/counter rolls over. This generates an interrupt
request if the ECF interrupt enable bit in CMOD is set. CF can be set by hardware or
software but can be cleared only by software.
CR
PCA Timer/Counter Run Control Bit:
Set and Cleared by software to turn the PCA timer/counter on and off.
CCF[4:0]
PCA Module Compare/Capture Flags:
Set by hardware when a match or capture occurs. This generates a PCA interrupt
request if the ECCFx interrupt enable bit in the corresponding CCAPMx register is set.
Must be cleared by software.
PCA Timer/Counter Mode Register (CMOD)
Location
7
6
5
4
3
2
1
0
Reset Value
D9H
CIDL
WDTE
-
-
-
CPS1
CPS0
ECF
00xxx000b
Symbol
Function
CIDL
PCA Timer/Counter Idle Control:
0: Allows the PCA timer/counter to run during idle mode.
1: Disables the PCA timer/counter during idle mode.
WDTE
Watchdog Timer Enable:
0: Disables the PCA watchdog timer output.
1: Enables the PCA watchdog timer output on PCA module 4.
CPS1,CPS0
PCA Timer/Counter Input Select:
ECF
CPS1
CPS0
0
0
1
1
0
1
0
1
fOSC /12
fOSC /4
Timer 0 overflow
External clock at ECI pin (maximum rate = fOSC /8)
PCA Timer/Counter Interrupt Enable:
0: Disables the CF bit in the CCON register.
1: Enables the CF bit in the CCON register to generate an interrupt request.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
21
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE 3-11: PCA MODULE MODES
ECOMy1
CAPPy1
CAPNy1
MATy1
TOGy1
PWNy1
ECCFy1 Module Code
0
0
0
0
0
0
0
No Operation
-
1
0
0
0
0
-
16-bit capture on positive-edge trigger at CEX[4:0]
-
0
1
0
0
0
-
16-bit capture on negative-edge trigger at CEX[4:0]
-
1
1
0
0
0
-
16-bit capture on positive-/negative-edge trigger
at CEX[4:0]
1
0
0
1
0
0
-
Compare: software timer
1
0
0
1
1
0
-
Compare: high-speed output
1
0
0
0
0
1
0
Compare: 8-bit PWM
1
0
0
1
-
0
-
Compare: PCA WDT (CCAPM4 only)2
T3-11.0 555
1. y = 0, 1, 2, 3, 4
2. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
22
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
PCA Compare/Capture Module Mode Register (CCAPM[4:0])
Location
7
6
5
4
3
2
1
0
Reset Value
DAH
-
ECOM0
CAPP0
CAPN0
MAT0
TOG0
PWM0
ECCF0
x0000000b
DBH
-
ECOM1
CAPP1
CAPN1
MAT1
TOG1
PWM1
ECCF1
x0000000b
DCH
-
ECOM2
CAPP2
CAPN2
MAT2
TOG2
PWM2
ECCF2
x0000000b
DDH
-
ECOM3
CAPP3
CAPN3
MAT3
TOG3
PWM3
ECCF3
x0000000b
DEH
-
ECOM4
CAPP4
CAPN4
MAT4
TOG4
PWM4
ECCF4
x0000000b
Symbol
Function
ECOM[4:0]
Compare Modes:
0: Disables the module comparator function.
1: Enables the module comparator function. The comparator is used to implement the
software timer, high-speed output, pulse width modulation, and watchdog timer modes.
CAPP[4:0]
0: Disables the capture function with capture triggered by a positive edge on pin
CEX[4:0].
1: Enables the capture function with capture triggered by a positive edge on pin
CEX[4:0].
CAPN[4:0]
0: Disables the capture function with capture triggered by a negative edge on pin
CEX[4:0].
1: Enables the capture function with capture triggered by a negative edge on pin
CEX[4:0].
MAT[4:0]
Match: Set ECOM[4:0] and MAT[4:0] to implement the software timer mode.
0: Disable the software timer mode
1: A match of the PCA timer/counter with the compare/capture register sets the
CCF[4:0] bit in the CCON register, flagging an interrupt.
TOG[4:0]
Toggle: Set ECOM[4:0], MAT[4:0], and TOG[4:0] to implement the high-speed output
mode.
0: Disable the toggle function
1: A match of the PCA timer/counter with the compare/capture register toggles the
CEX[4:0] pin.
PWM[4:0]
Pulse Width Modulation Mode:
0: Disable the pulse width modulation mode
1: Configures the module for operation as an 8-bit pulse width modulator with output
waveform on the CEX[4:0] pin.
ECCF[4:0]
Enable CCF[4:0] Interrupt:
0: Disables compare/capture flag CCF[4:0] in the CCON register to generate an
interrupt request.
1: Enables compare/capture flag CCF[4:0] in the CCON register to generate an
interrupt request.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
23
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
SPI Control Register (SPCR)
Location
7
6
5
4
3
2
1
0
Reset Value
D5H
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
00000100b
Symbol
Function
SPIE
If both SPIE and ES are set to one, SPI interrupts are enabled.
SPE
SPI enable bit.
0: Disables SPI.
1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1[4], P1[5], P1[6], P1[7].
DORD
Data Transmission Order.
0: MSB first in data transmission.
1: LSB first in data transmission.
MSTR
Master/Slave select.
0: Selects Slave mode.
1: Selects Master mode.
CPOL
Clock Polarity
0: SCK is low when idle (Active High).
1: SCK is high when idle (Active Low).
CPHA
Clock Phase control bit.
0: Shift triggered on the leading edge of the clock.
1: Shift triggered on the trailing edge of the clock.
SPR1, SPR0
SPI Clock Rate Select bits. These two bits control the SCK rate of the device
configured as master. SPR1 and SPR0 have no effect on the slave. The relationship
between SCK and the oscillator frequency, fOSC, is as follows:
SPR1
SPR0
SCK = fOSC divided by
0
0
1
1
0
1
0
1
4
16
64
128
SPI Status Register (SPSR)
Location
7
6
5
4
3
2
1
0
Reset Value
AAH
SPIF
WCOL
-
-
-
-
-
-
00xxxxxxb
Symbol
Function
SPIF
Upon completion of data transfer, this bit is set to 1. If SPIE =1 and ES =1, an interrupt
is then generated. To clear, read SPSR and then access SPDR.
WCOL
Set if the SPI data register is written to during data transfer. To clear, read SPSR and
then access SPDR.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
24
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
SPI Data Register (SPDR)
Location
7
6
5
4
3
2
1
0
Reset Value
86H
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
00H
Power Control Register (PCON)
Location
7
6
5
4
3
2
1
0
Reset Value
87H
SMOD1
SMOD0
BOF
POF
GF1
GF0
PD
IDL
00010000b
Symbol
Function
SMOD1
Double Baud rate bit. If SMOD1 = 1, Timer 1 is used to generate the baud rate.
SMOD0
FE/SM0 Selection bit.
0: SCON[7] = SM0
1: SCON[7] = FE,
BOF
Brown-out detection status bit, this bit will not be affected by any other reset. BOF
should be cleared by software. Power-on reset will also clear the BOF bit.
0: No Brown-out.
1: Brown-out occurred
POF
Power-on reset status bit, this bit will not be affected by any other reset. POF should be
cleared by software.
0: No Power-on reset.
1: Power-on reset occurred
GF1
General-purpose flag bit.
GF0
General-purpose flag bit.
PD
Power-down bit.
0: Power-down mode is not activated.
1: Activates Power-down mode.
IDL
Idle mode bit.
0: Idle mode is not activated.
1: Activates Idle mode.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
25
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
Serial Port Control Register (SCON)
Location
7
6
5
4
3
2
1
0
Reset Value
98H
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
00000000b
Symbol
Function
FE
Set SMOD0 = 1 to access FE bit.
0: No framing error
1: Framing Error. Set by receiver when an invalid stop bit is detected. This bit needs to
be cleared by software.
SM0
SMOD0 = 0 to access SM0 bit.
Serial Port Mode Bit 0
SM1
Serial Port Mode Bit 1
SM0
0
SM1
0
Mode
0
Description
Shift Register
0
1
1
0
1
2
8-bit UART
9-bit UART
1
1
3
9-bit UART
Baud Rate1
fOSC/6 (6 clock mode) or fOSC/
12 (12 clock mode)
Variable
fOSC/32 or fOSC/16 (6 clock
mode) or fOSC/64 or
fOSC/32 (12 clock mode)
Variable
1. fOSC = oscillator frequency
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then RI
will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and
the received byte is a Given or broadcast Address. In Mode 1, if SM2 = 1 then RI will
not be activated unless a valid stop bit was received, and the received byte is a Given
or Broadcast Address. In Mode 0, SM2 should be 0.
REN
Enables serial reception.
0: to disable reception.
1: to enable reception.
TB8
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as
desired.
RB8
In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 - 0, RB8 is the
stop bit that was received. In Mode 0, RB8 is not used.
TI
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at
the beginning of the stop bit in the other modes, in any serial transmission, Must be
cleared by software.
RI
Receive interrupt flag. Set by hardware at the end of the8th bit time in Mode 0, or
halfway through the stop bit time in the other modes, in any serial reception (except see
SM2). Must be cleared by software.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
26
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
4.0 FLASH MEMORY PROGRAMMING
The device internal flash memory can be programmed or
erased using the following two methods:
•
•
logic high to a logic low while RST input is being held continuously high. The device will stay in External Host Mode
as long as RST = 1 and PSEN# = 0.
External Host Mode
In-Application Programming (IAP) Mode
A Read-ID operation is necessary to “arm” the device in
External Host Mode, and no other External Host Mode commands can be enabled until a Read-ID is performed. In
External Host Mode, the internal Flash memory blocks are
accessed through the re-assigned I/O port pins (see Figure
4-1 for details) by an external host, such as a MCU programmer, a PCB tester or a PC-controlled development board.
4.1 External Host Programming Mode
External Host Programming Mode allows the user to program the Flash memory directly without using the CPU.
External Host Mode is entered by forcing PSEN# from a
TABLE
4-1: EXTERNAL HOST MODE COMMANDS
FOR
SST89E564RD/SST89V564RD
P2[6]
P0[7:0]
P3[5:4]
P2[5:0]
P1[7:0]
VIL
VIL
DO
AH
AL
VIL
VIH
X
X
X
VIH
VIL
VIH
X
X
X
VIL
VIH
VIH
X
AH
AL
VIH
VIH
VIH
VIL
DI
AH
AL
VIH
VIH
VIL
VIL
DO
AH
AL
RST
PSEN#
PROG#/
ALE
EA#
P3[7]
P3[6]
P2[7]
Read-ID
VIH1
VIL
VIH
VIH
VIL
VIL
Chip-Erase
VIH1
VIL
⇓
VIH
VIL
VIL
Block-Erase
VIH1
VIL
⇓
VIH
VIH
Sector-Erase
VIH1
VIL
⇓
VIH
VIH
Byte-Program
VIH1
VIL
⇓
VIH
Byte-Verify (Read)
VIH1
VIL
VIH
VIH
Operation
Select-Block0
VIH1
VIL
⇓
VIH
VIH
VIl
VIl
VIH
X
55H
X
Select-Block1
VIH1
VIL
⇓
VIH
VIH
VIl
VIl
VIH
X
A5H
X
Prog-SC0
VIH1
VIL
⇓
VIH
VIH
VIL
VIL
VIH
X
5AH
X
Prog-SB1
VIH1
VIL
⇓
VIH
VIH
VIH
VIH
VIH
X
X
X
Prog-SB2
VIH1
VIL
⇓
VIH
VIL
VIL
VIH
VIH
X
X
X
Prog-SB3
VIH1
VIL
⇓
VIH
VIL
VIH
VIL
VIH
X
X
X
Enable-Clock-Double
VIH1
VIL
⇓
VIH
VIH
VIL
VIL
VIL
X
55H
X
T4-1.1 555
Note: Symbol ⇓ signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input. All other combinations of
the above input pins are invalid and may result in unexpected behaviors.
Note: VIL = Input Low Voltage; VIH = Input High Voltage; VIH1 = Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte;
AH = Address high order byte; DI = Data Input; DO = Data Output
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
27
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
4-2: EXTERNAL HOST MODE COMMANDS
FOR
SST89E554RC/SST89V554RC
Operation
RST
PSEN#
PROG#/
ALE
EA#
P3[7]
P3[6]
P2[7]
P2[6]
P0[7:0]
P3[5:4]
P2[5:0]
P1[7:0]
Read-ID
VIH1
VIL
VIH
VIH
VIL
VIL
VIL
VIL
DO
AH
AL
Chip-Erase
VIH1
VIL
⇓
VIH
VIL
VIL
VIL
VIH
X
X
X
Block-Erase
VIH1
VIL
⇓
VIH
VIH
VIH
VIL
VIH
X
A[15:13]
X
Sector-Erase
VIH1
VIL
⇓
VIH
VIH
VIL
VIH
VIH
X
AH
AL
Byte-Program
VIH1
VIL
⇓
VIH
VIH
VIH
VIH
VIL
DI
AH
AL
Byte-Verify (Read)
VIH1
VIL
VIH
VIH
VIH
VIH
VIL
VIL
DO
AH
AL
Prog-SC0
VIH1
VIL
⇓
VIH
VIH
VIL
VIL
VIH
X
5AH
X
Prog-SC1
VIH1
VIL
⇓
VIH
VIH
VIL
VIL
VIH
X
AAH
X
Prog-SB1
VIH1
VIL
⇓
VIH
VIH
VIH
VIH
VIH
X
X
X
Prog-SB2
VIH1
VIL
⇓
VIH
VIL
VIL
VIH
VIH
X
X
X
Prog-SB3
VIH1
VIL
⇓
VIH
VIL
VIH
VIL
VIH
X
X
X
Enable-Clock-Double
VIH1
VIL
⇓
VIH
VIH
VIL
VIL
VIL
X
55H
X
T4-2.0 555
Note: Symbol ⇓ signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input.
All other combinations of the above input pins are invalid and may result in unexpected behaviors.
Note: VIL = Input Low Voltage; VIH = Input High Voltage; VIH1 = Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte;
AH = Address high order byte; DI = Data Input; DO = Data Output; A[15:13] = 0xxb for Block 0 and A[15:13] = 111b for Block 1
VSS VDD RST
0
XTAL1
Port 0
XTAL2
6
7
Input/
Output
Data
Bus
0
0
1
1
2
2
Ready/Busy#
3
A14
4
A15
5
Address Bus
A15-A14
Flash
Control Signals
Port 2
3
Address Bus
A13-A8
4
Port 3
5
6
7
6
Flash
Control Signals
0
7
Port 1
6
Address Bus
A7-A0
7
EA#
ALE / PSEN#
PROG#
555 ILL F04.1
FIGURE
4-1: I/O PIN ASSIGNMENTS
FOR
EXTERNAL HOST MODE
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
28
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
4.1.1 Product Identification
Following is a detailed description of the External Host
Mode commands:
The Read-ID command accesses the Signature Bytes that
identify the device and the manufacturer as SST. External
programmers primarily use these Signature Bytes in the
selection of programming algorithms. The Read-ID command is selected by the command code of 0H on P3[7:6]
and P2[7:6]. See Figure 11-12 for timing waveforms.
TABLE
The Select-Block0 command enables Block 0 to be programmed in External Host Mode. Once this command is
executed, all subsequent External Host Commands will be
directed at Block 0. See Figure 11-13 for timing waveforms.
This
command
applies
to
SST89E564RD/
SST89V564RD only.
4-3: SIGNATURE BYTES
Address
Data
30H
BFH
SST89E564RD
31H
91H
SST89V564RD
31H
90H
SST89E554RC
31H
99H
SST89V554RC
31H
Manufacturer’s ID
The Select-Block1 command enables Block 1 (8 KByte
Block) to be programmed. Once this command is executed, all subsequent External Host Commands that are
directed to the address range below 2000H will be directed
at Block 1. The Select-Block1 command only affects the
lowest 8 KByte of the program address space. For
addresses greater than or equal to 2000H, Block 0 is
accessed by default. Upon entering External Host Mode,
Block 1 is selected by default. See Figure 11-13 for timing
waveforms. This command applies to SST89E564RD/
SST89V564RD only.
Device ID
98H
T4-3.0 555
4.1.2 Arming Command
The Chip-Erase, Block-Erase, and Sector-Erase commands are used for erasing all or part of the memory
array. Erased data bytes in the memory array will be
erased to FFH. Memory locations that are to be programmed must be in the erased state prior to programming.
An arming command sequence must take place before
any External Host Mode sequence command is recognized by the device. This prevents accidental triggering of
External Host Mode Commands due to noise or programmer error. The arming command is as follows:
1. PSEN# goes low while RST is high. This will get
the machine in External Host Mode, re-configuring
the pins, and turning on the on-chip oscillator.
The Chip-Erase command erases all bytes in both memory
blocks, regardless of any previous Select-Block0 or SelectBlock1 commands. Chip-Erase ignores the Security Lock
status and will erase the Security Lock, returning the device
to its Unlocked state. The Chip-Erase command will also
erase the SC0 bit. Upon completion of Chip-Erase command, Block 1 will be the selected block. See Figure 11-14
for timing waveforms.
2. A Read-ID command is issued, and after 1 ms the
External Host Mode commands can be issued.
After the above sequence, all other External Host Mode
commands are enabled. Before the Read-ID command is
received, all other External Host Mode commands
received are ignored.
The Block-Erase command erases all bytes in the selected
memory blocks. This command will not be executed if the
security lock is enabled. The selection of the memory block
to be erased is determined by the prior execution SelectBlock0 or Select-Block1 command. See Figures 11-15 and
11-16 for the timing waveforms.
4.1.3 Detail Explanation of the External Host Mode
Commands
The External Host Mode commands are Read-ID, ChipErase, Block-Erase, Sector-Erase, Byte-Program, ByteVerify, Prog-SB1, Prog-SB2, Prog-SB3, Prog-SC0, ProgSC1, Select-Block0, Select-Block1. See Tables 4-1 and 4-2
for all signal logic assignments, Figure 4-1 for I/O pin
assignments, and Table 4-7 for the timing parameters. The
critical timing for all Erase and Program commands is generated by an on-chip flash memory controller. The high-tolow transition of the PROG# signal initiates the Erase or
Program commands, which are synchronized internally.
The Read commands are asynchronous reads, independent of the PROG# signal level.
The Sector-Erase command erases all of the bytes in a
sector. The sector size for the flash memory is 128 Bytes.
This command will not be executed if the Security lock is
enabled. See Figure 11-17 for timing waveforms.
The Byte-Program command is used for programming new
data into the memory array. Programming will not take
place if any security locks are enabled. See Figure 11-18
for timing waveforms.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
29
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
The Byte-Verify command allows the user to verify that the
device correctly performed an Erase or Program command. This command will be disabled if any security locks
are enabled. See Figure 11-21 for timing waveforms.
4.1.5.2 Data# Polling (P0[3])
During a Program operation, any attempts to read (ByteVerify), while the device is busy, will receive the complement of the data of the last byte loaded (logic low, i.e. “0” for
an erase) on P0[3] with the rest of the bits “0”. During a Program operation, the Byte-Verify command is reading the
data of the last byte loaded, not the data at the address
specified.
The Prog-SB1, Prog-SB2, Prog-SB3 commands program
the security bits, the functions of these bits are described in
the Security Lock section and also in Table 9-1. Once programmed, these bits can only be erased through a ChipErase command. See Figure 11-19 for timing waveforms.
4.1.6 Step-by-step instructions to perform
External Host Mode commands
Prog-SC0 command programs SC0 bit, which determines
the state of SFCF[0] out of reset. Once programmed, SC0
can only be restored to an erased state via a Chip-Erase
command. See Figure 11-20 for timing waveforms.
To program data into the memory array, apply power
supply voltage (VDD) to VDD and RST pins, and perform the following steps:
Prog-SC1 command programs SC1 bit, which determines
the state of SFCF[1] out of reset. Once programmed, SC1
can only be restored to an erased state via a Chip-Erase
command. See Figure 11-20 for timing waveforms. ProgSC1 is for SST89E554RC/SST89V554RC only.
1. Maintain RST high and set PSEN# from logic high
to low, in sequence according to the appropriate
timing diagram.
2. Raise EA# High (VIH).
3. Issue Read-ID command to enable the External
Host Mode.
4.1.4 External Host Mode Clock Source
In External Host Mode, an internal oscillator will provide
clocking for the device. The on-chip oscillator will be turned
on as the device enters External Host Mode; i.e. when
PSEN# goes low while RST is high. During External Host
Mode, the CPU core is held in reset. Upon exit from External Host Mode, the internal oscillator is turned off.
4. Verify that the memory blocks or sectors for programming is in the erased state, FFH. If they are
not erased, then erase them using the appropriate
Erase command.
5. Select the memory location using the address
lines (P3[5:4], P2[5:0], P1[7:0]).
4.1.5 Flash Operation Status Detection Via External
Host Handshake
6. Present the data in on P0[7:0].
7. Pulse ALE/PROG#, observing minimum pulse
width.
The device provides two methods for an external host to
detect the completion of a flash memory operation to optimize the Program or Erase time. The end of a flash memory operation cycle can be detected by:
8. Wait for low to high transition on READY/BUSY#
(P3[3]).
1. monitoring the Ready/Busy# bit at P3[3];
9. Repeat steps 5 - 8 until programming is finished.
2. monitoring the Data# Polling bit at P0[3].
10. Verify the flash memory contents.
4.1.5.1 Ready/Busy# (P3[3])
The progress of the flash memory programming can be
monitored by the Ready/Busy# output signal. P3[3] is
driven low, some time after ALE/PROG# goes low during a
flash memory operation to indicate the Busy# status of the
Flash Control Unit (FCU). P3[3] is driven high when the
Flash programming operation is completed to indicate the
Ready status.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
30
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
4.2 In-Application Programming Mode
4.2.2 Memory Bank Selection for In-Application
Programming Mode
The device offers either 72 or 40 KByte of In-Application
Programmable flash memory. During In-Application Programming, the CPU of the microcontroller enters IAP
Mode. The two blocks of flash memory allow the CPU to
execute user code from one block, while the other is being
erased or reprogrammed concurrently. The CPU may also
fetch code from an external memory while all internal flash
is being reprogrammed. The mailbox registers (SFST,
SFCM, SFAL, SFAH, SFDT and SFCF) located in the Special Function Register (SFR), control and monitor the
device’s erase and program process.
With the addressing range limited to 16 bit, only 64 KByte
of program address space is “visible” at any one time. As
shown in Table 4-4, Bank Selection (the configuration of
EA# and SFCF[1:0]), allows Block 1 memory to be overlaid
on the lowest 8 KByte of Block 0 memory, making Block 1
reachable. The same concept is employed to allow both
Block 0 and Block 1 Flash to be accessible to IAP operations. Code from a block that is not visible may not be used
as a source to program another address. However, a block
that is not “visible” may be programmed by code from the
other block through mailbox registers.
Table 4-6 outlines the commands and their associated
mailbox register settings.
The device allows IAP code in one block of memory to program the other block of memory, but may not program any
location in the same block. If an IAP operation originates
physically from Block 0, the target of this operation is implicitly defined to be in Block 1. If the IAP operation originates
physically from Block 1, then the target address is implicitly
defined to be in Block 0. If the IAP operation originates from
External program space, then, the target will depend on the
address and the state of Bank Select.
4.2.1 In-Application Programming Mode Clock
Source
During IAP Mode, both the CPU core and the flash controller unit are driven off the external clock. However, an internal oscillator will provide timing references for Program and
Erase operations. The internal oscillator is only turned on
when required, and is turned off as soon as the Flash operation is completed.
4-4: IAP ADDRESS RESOLUTION
TABLE
FOR
SST89E564RD/SST89V564RD
EA#
SFCF[1:0]
Address of IAP Inst.
Target Address
Block Being Programmed
1
00
>= 2000H (Block 0)
>= 2000H (Block 0)
None1
1
00
>= 2000H (Block 0)
< 2000H (Block 1)
Block 1
1
00
< 2000H (Block 1)
Any (Block 0)
Block 0
1
01, 10, 11
Any (Block 0)
>= 2000H (Block 0)
None1
1
01, 10, 11
Any (Block 0)
< 2000H (Block 1)
Block 1
0
00
From external
>= 2000H (Block 0)
Block 0
0
00
From external
< 2000H (Block 1)
Block 1
0
01, 10, 11
From external
Any (Block 0)
Block 0
T4-4.0 555
1. No operation is performed because code from one block may not program the same originating block
4.2.3 IAP Enable Bit
The Program command is for programming new data into
the memory array. The portion of the memory array to be
programmed should be in the erased state, FFH. If the
memory is not erased, it should first be erased with an
appropriate Erase command. Warning: Do not attempt to
write (program or erase) to a block that the code is currently fetching from. This will cause unpredictable program behavior and may corrupt program data.
The IAP Enable Bit, SFCF[6], enables In-Application Programming mode. Until this bit is set all flash programming
IAP commands will be ignored.
4.2.4 In-Application Programming Mode Commands
All of the following commands can only be initiated in the
IAP Mode. In all situations, writing the control byte to the
SFCM register will initiate all of the operations. All commands will not be enabled if the security locks are enabled
on the selected memory block.
The Block-Erase command erases all bytes in one of the
two memory blocks. The selection of the memory block to
be erased is determined by the source of Block-Erase
Command, as defined in Table 4-4.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
31
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
The Chip-Erase command erases all bytes in both memory
blocks. This command is only allowed when EA#=0 (external memory execution). Additionally this command is not
permitted when the device is in level 4 locking. In all other
instances, this command ignores the Security Lock status
and will erase the security lock bits and Re-Map bits.
SC0 bit previously in un-programmed state can be programmed by this command. The Prog-SC0 command
should reside only in Block 1.
Prog-SC1 command is used to program the SC1 bit. This
command only changes the SC1 bit and has no effect on
BSEL bit until after a reset cycle.
The Sector-Erase command erases all of the bytes in a
sector. The sector size for the flash memory Blocks is 128
Bytes. The selection of the sector to be erased is determined by the contents of SFAH and SFAL.
SC1 bit previously in un-programmed state can be programmed by this command. The Prog-SC1 command
should reside only in Block 1.
There are no IAP counterparts for the External Host commands Select-Block0 and Select-Block1.
The Byte-Program command programs data into a single
byte. The address is determined by the contents of SFAH
and SFAL. The data byte is in SFDT.
4.2.5 Polling
The Byte-Verify command allows the user to verify that the
device has correctly performed an Erase or Program command.
A command that uses the polling method to detect flash
operation completion should poll on the FLASH_BUSY bit
(SFST[2]). When FLASH_BUSY de-asserts (logic 0), the
device is ready for the next operation.
Byte-Verify command returns the data byte in SFDT if the
command is successful. The user is required to check that
the previous Flash operation has fully completed before
issuing a Byte-Verify. Byte-Verify command execution time
is short enough that there is no need to poll for command
completion and no interrupt is generated.
MOVC instruction may also be used for verification of the
Programming and Erase operation of the flash memory.
MOVC instruction will fail if it is directed at a flash block that
is still busy.
4.2.6 Interrupt Termination
Prog-SB3, Prog-SB2, Prog-SB1 commands are used to
program the Security bits (see Table 9-1). Completion of
any of these commands, the security options will be
updated immediately.
If interrupt termination is selected, (SFCM[7] is set), then
an interrupt (INT1) will be generated to indicate flash operation completion. Under this condition, the INT1 becomes an
internal interrupt source. The INT1# pin can now be used
as a general purpose port pin and it cannot be the source
of External Interrupt 1 during In-Application Programming.
Security bits previously in un-programmed state can be
programmed by these commands. Prog-SB3, Prog-SB2
and Prog-SB1 commands should only reside in Block 1.
In order to use an interrupt to signal flash operation termination. EX1 and EA bits of IE register must be set. The IT1
bit of TCON register must also be set for edge trigger
detection.
Prog-SC0 command is used to program the SC0 bit. This
command only changes the SC0 bit and has no effect on
BSEL bit until after a reset cycle.
.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
32
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
4-5: IN-APPLICATION PROGRAMMING MODE COMMANDS1 FOR SST89E564RD/SST89V564RD
SFCM [6:0]2
Operation
SFDT [7:0]
SFAH [7:0]
SFAL [7:0]
Chip-Erase3
01H
55H
X
X
Block-Erase4
0DH
55H
X5
X
Sector-Erase4
0BH
X
AH6
AL7
0EH
DI8
AH
AL
Byte-Program4
0CH
DO9
AH
AL
Prog-SB110
0FH
AAH
X
X
Prog-SB210
03H
AAH
X
X
Prog-SB310
05H
AAH
X
X
Byte-Verify
(Read)4
Prog-SC010
09H
AAH
5AH
X
Enable-Clock-Double
08H
AAH
55H
X
T4-5.2 555
1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands.
2. Interrupt/Polling enable for flash operation completion
SFCM[7] =1: Interrupt enable for flash operation completion
0: polling enable for flash operation completion
3. Chip-Erase only functions in IAP mode when EA#=0 (external memory execution) and device is not in level 4 locking.
4. Refer to Table 4-4 for address resolution
5. X can be VIL or VIH, but no other value.
6. AH = Address high order byte
7. AL = Address low order byte
8. DI = Data Input
9. DO = Data Output
All other values are in hex
10. Instruction must be located in Block 1 or external code memory.
.
TABLE
4-6: IN-APPLICATION PROGRAMMING MODE COMMANDS1 FOR SST89E554RC/SST89V554RC
Operation
Chip-Erase3
SFCM [6:0]2
SFDT [7:0]
SFAH [7:0]
SFAL [7:0]
01H
55H
X
X
X6
Block-Erase4
0DH
55H
AH5
Sector-Erase4
0BH
X
AH7
AL8
Byte-Program4
0EH
DI9
AH
AL
Byte-Verify (Read)4
0CH
DO10
AH
AL
Prog-SB111
0FH
AAH
X
X
Prog-SB211
03H
AAH
X
X
Prog-SB311
05H
AAH
X
X
Prog-SC011
09H
AAH
5AH
X
Prog-SC111
09H
AAH
AAH
X
Enable-Clock-Double
08H
AAH
55H
X
T4-6.1 555
1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands.
2. Interrupt/Polling enable for flash operation completion
SFCM[7] =1: Interrupt enable for flash operation completion
0: polling enable for flash operation completion
3. Chip-Erase only functions in IAP mode when EA#=0 (external memory execution) and device is not in level 4 locking.
4. Refer to Table 4-4 for address resolution
5. SFAH[7]=0: Selects Block 0; SFAH[7:5] = 111b selects Block 1
6. X can be VIL or VIH, but no other value.
7. AH = Address high order byte
8. AL = Address low order byte
9. DI = Data Input
10. DO = Data Output, All other values are in hex
11. Instruction must be located in Block 1 or external code memory.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
33
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
4-7: EXTERNAL MODE FLASH MEMORY PROGRAMMING/VERIFICATION PARAMETERS1
Parameter2,3
Symbol
Min
Reset Setup Time
TSU
3
µs
Read-ID Command Width
TRD
1
µs
PSEN# Setup Time
TES
40
µs
Address, Command, Data Setup Time
TADS
0
ns
Chip-Erase Time
TCE
125
ms
Block-Erase Time
TBE
100
ms
30
ms
Sector-Erase Time
Program Setup Time
TSE
TPROG
1.2
0
Max
Units
µs
Address, Command, Data Hold
TDH
Byte-Program Time4
TPB
50
ns
µs
Select-Block Program Time
TPSB
500
ns
Security bit Program Time
TPS
80
µs
Verify Command Delay Time
TOA
50
ns
Verify High Order Address Delay Time
TAHA
50
ns
Verify Low Order Address Delay Time
TALA
50
ns
T4-7.0 555
1.
2.
3.
4.
For IAP operations, the program execution overhead must be added to the above timing parameters.
Program and Erase times will scale inversely proportional to programming clock frequency.
All timing measurements are from the 50% of the input to 50% of the output.
Each byte must be erased before programming.
5.0 TIMERS/COUNTERS
all four modes, transmission is initiated by any instruction
that uses the SBUF register as a destination register.
Reception is initiated in mode 0 when the Receive Interrupt
(RI) flag bit of the Serial Port Control (SCON) SFR is
cleared and the Reception Enable/ Disable (REN) bit of the
SCON register is set. Reception is initiated in the other
modes by the incoming start bit if the REN bit of the SCON
register is set.
The device has three 16-bit registers that can be used as
either timers or event counters. The three Timers/Counters
are denoted Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2).
Each is designated a pair of 8-bit registers in the SFRs.
The pair consists of a most significant (high) byte and least
significant (low) byte. The respective registers are TL0,
TH0, TL1, TH1, TL2, and TH2.
6.1.1 Framing Error Detection
6.0 SERIAL I/O
Framing Error Detection allows the serial port to automatically check for valid stop bits in Modes 1, 2 or 3. If
a stop bit is missing the Framing Error bit (FE) will be
set. The software can then check this bit after a reception to detect communication errors. The FE bit must
be cleared by software.
6.1 Enhanced Universal Asynchronous
Receiver/Transmitter (UART)
The device Serial I/O port is a full duplex port that allows
data to be transmitted and received simultaneously in
hardware by the transmit and receive registers, respectively, while the software is performing other tasks. The
transmit and receive registers are both located in the
Serial Data Buffer (SBUF) special function register. Writing to the SBUF register loads the transmit register, and
reading from the SBUF register obtains the contents of
the receive register.
The FE bit is located in SCON and shares the same bit
address as SM0. The SMOD0 bit located in the PCON register determines which of these two bits is accessed. When
SMOD0 = 0, SCON[7] will act as SM0. When SMOD0 = 1,
SCON[7] will act as FE.
6.1.2 Automatic Address Recognition
Automatic Address Recognition (AAR) reduces the CPU
time required to service the serial port in a multiprocessor
environment. When using AAR, the serial port hardware
The UART has four modes of operation which are selected
by the Serial Port Mode Specifier (SM0 and SM1) bits of
the Serial Port Control (SCON) special function register. In
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
34
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
will only generate an interrupt when it receives its own
address, thus eliminating the software overhead required to
compare addresses.
In this example Slave 1 can be distinguished from Slave 2
by using bits 0 and 1. Slave 1 will not respond to an
address that has bit 1 set to 1 while Slave 2 will. Similarly,
Slave 2 will not respond to an address that has bit 0 set to 0
while Slave 1 will. Both slaves will respond to an address of
1111 0x01b so this is the Broadcast Address. The Broadcast Addresses is formed by the logical OR of SADDR and
SADEN with 0s treated as don’t-care bits.
AAR is only available when using the serial port in either
mode 2 or 3. Setting the SM2 bit in SCON enables AAR.
Each slave must have its SM2 bit set when waiting for an
address (9th bit = 1). The Receive Interrupt (RI) flag will only
be set when the received byte matches either the Given or
Broadcast Address. The slave then clears its SM2 bit to
enable reception of data bytes (9th bit = 0) from the master.
6.2 Serial Peripheral Interface (SPI)
The device SPI allows for high-speed full-duplex synchronous data transfer between the device and other compatible SPI devices.
The master can selectively communicate with groups of
slaves by sending the Given Address. Addressing all
slaves is also possible by sending the Broadcast address.
The SADDR and SADEN special function registers define
these addresses for each slave.
Figure 6-1 shows the correspondence between master
and slave SPI devices. The SCK pin is the clock output and
input for the master and slave modes, respectively. The SPI
clock generator will start following a write to the master
devices SPI data register. The written data is then shifted
out of the MOSI pin on the master device into the MOSI pin
of the slave device. Following a complete transmission of
one byte of data, the SPI clock generator is stopped and
the SPIF flag is set. An SPI interrupt request will be generated if the SPI interrupt enable bit (SPIE) and the serial port
interrupt enable bit (ES) are both set.
SADDR specifies a slaves individual address and SADEN
is a mask byte that defines don’t-care bits to form the Given
address when combined with SADDR. The following is an
example:
UART Slave 1
SADDR
=
1111 0001
SADEN
=
1111 1010
GIVEN
=
1111 0x0x
An external master drives the Slave Select input pin, SS#/
P1[4], low to select the SPI module as a slave. If SS#/P1[4]
has not been driven low, then the slave SPI unit is not
active and the MOSI/P1[5] port can also be used as an
input port pin.
UART Slave 2
SADDR
=
1111 0011
SADEN
=
1111 1001
GIVEN
=
1111 0xx1
MSB MASTER LSB
CPHA and CPOL control the phase and polarity of the SPI
clock. Figures 6-2 and 6-3 show the four possible combinations of these two bits.
MISO MISO
8-bit Shift Register
MSB SLAVE LSB
8-bit Shift Register
MOSI MOSI
SPI
Clock Generator
SCK
SS#
SCK
SS#
VIH
555 ILL F15.0
FIGURE
6-1: SPI MASTER-SLAVE INTERCONNECTION
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
35
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
SCK Cycle #
(for reference)
1
2
3
4
5
6
7
8
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
(from Master)
MSB
MISO
(from Slave)
MSB
6
5
4
3
2
1
LSB
6
5
4
3
2
1
LSB
*
SS# (to Slave)
555 ILL F16.0
* Not defined, but normally MSB of next received byte
FIGURE
6-2: SPI TRANSFER FORMAT
SCK Cycle #
(for reference)
1
WITH
2
CPHA = 0
3
4
5
6
7
8
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
(from Master)
MISO
(from Slave)
*
MSB
6
5
4
3
2
1
MSB
6
5
4
3
2
1
LSB
LSB
SS# (to Slave)
555 ILL F17.0
* Not defined but normally LSB of previously transmitted character
FIGURE
6-3: SPI TRANSFER FORMAT
WITH
CPHA = 1
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
36
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
7.0 WATCHDOG TIMER
The device offers a programmable Watchdog Timer (WDT)
for fail safe protection against software deadlock and automatic recovery.
The WDTS flag bit is set by WDT overflow and is not
changed by WDT reset. User software can clear WDTS by
writing “1” to it.
To protect the system against software deadlock, the user
software must refresh the WDT within a user-defined time
period. If the software fails to do this periodical refresh, an
internal hardware reset will be initiated if enabled (WDRE=
1). The software can be designed such that the WDT times
out if the program does not work properly.
Figure 7-1 provides a block diagram of the WDT. Two SFRs
(WDTC and WDTD) control watchdog timer operation.
During idle mode, WDT operation is temporarily suspended, and resumes upon an interrupt exit from idle.
The time-out period of the WDT is calculated as follows:
Period = (255 - WDTD) * 344064 * 1/fOSC
The WDT in the device uses the system clock (XTAL1) as
its time base. So strictly speaking, it is a watchdog counter
rather than a watchdog timer. The WDT register will increment every 344064 crystal clocks. The upper 8-bits of the
time base register (WDTD) are used as the reload register
of the WDT.
CLK (XTAL1)
where WDT is the value loaded into the WDT register and
fOSC is the oscillator frequency.
344064
clks
Counter
WDT Reset
WDT Upper Byte
Internal Reset
Ext. RST
WDTC
WDTD
555 ILL F18.0
FIGURE
7-1: BLOCK DIAGRAM
OF
PROGRAMMABLE WATCHDOG TIMER
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
37
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
8.0 PROGRAMMABLE COUNTER ARRAY (PCA)
The device is equipped with an integrated Program
Counter Array (PCA). The PCA consists of a dedicated
timer/counter that serves as the common time base for an
array of 5 compare/capture modules. Each of the modules
can be programmed in 1 of 4 modes. Additionally, the 5th
module can be programmed as a Watchdog Timer.
TABLE
CCAPMn Value
The timer/counter for the PCA is a free-running 16 timer
and consists of registers CH and CL (the high and low
bytes of the count values). These registers can be read and
written to at any time. The Count Pulse Select bits (CPS1 &
CPS0) in the CMOD register configure the timer/counter to
operate in 1 of 4 modes. See Table 8-1. The CMOD register also contains the Counter Idle (CIDL) bit. When CIDL=1
the PCA timer/counter will be turned off when the MCU
enters Idle Mode
CPS0
0
Internal Clock, FOSC / 12
0
1
Internal Clock, FOSC / 4
1
0
Timer 0 Overflow
1
1
External Clock at P1.2
Capture Positive Edge Only
20H
21H
Capture Negative Edge Only
10H
11H
Capture Both Edges
30H
31H
16-Bit Software Timer
48H
49H
High Speed Output
4CH
4DH
42H
43H
Watchdog Timer1
48H or 4CH
T8-2.0 555
1. Only for Module 4
Additionally each of the five modules has two 8-bit capture/
compare registers (CCAPnH & CCAPnL) and an external
input/output pin associated with it. The external input/output
pins are P1.3 for Module 0, P1.4 for Module 1, P1.5 for
Module 2, P1.6 for Module 3 and P1.7 for Module 4. Each
module also has an associated event flag CCFn located in
CCON register. These flags must be cleared by software.
8-1: COUNT PULSE SELECTED BITS
0
with
interrupt
enabled
Pulse Width Modulator
.
CPS1
without
interrupt
enabled
Module Function
8.1 PCA Timer/Counter
TABLE
8-2: POSSIBLE MODES AND ASSOCIATED
VALUES FOR CCAPMN
PCA Count Pulse Selected
Writing to CCAPnL will disable the compare feature of the
corresponding module and writing to CCAPnH will reenable it. Therefore, when using the compare feature (16Bit Software Timer, High Speed Output, Pulse Width Modulator & Watchdog Timer modes) the software should
always write to CCAPnL first and then write to CCAPnH
second.
T8-1.0 555
The Counter Run bit (CR) in CCON register turns the timer/
counter on and off. When CR = 1 the timer/counter is running and when CR = 0 the timer/counter will be disabled.
When the PCA timer/counter overflows the CF bit in CCON
register will be set and if the ECF bit in CMOD register is
set an interrupt will be generated.
8.2.1 Capture Mode
Capture Mode is used to capture the PCA timer/counter
value into a module’s capture registers (CCAPnH &
CCAPnL). The capture will occur on a positive edge, a negative edge or both edges of the input signal on the corresponding external input pin depending on which mode is
selected. Also, the event flag (CCFn) is set and an interrupt
is generated if ECCFn is set.
8.2 PCA Compare/Capture Modules
Each of the 5 Compare/Capture modules has a mode register called CCAPMn (n = 0, 1, 2, 3, or 4) which selects the
function it will perform. The seven possible modes and their
associated values for CCAPMn are shown in Table 8-2.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
38
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
9.0 SECURITY LOCK
8.2.2 16-Bit Software Timer Mode
In the 16-bit Software Timer mode the PCA timer/counter
value is compared with the 16-bit value pre-loaded into the
module’s compare registers (CCAPnH & CCAPnL). When
a match occurs, the event flag (CCFn) is set and an interrupt is generated if ECCFn is set.
The Security Lock protects against software piracy and
prevents the contents of the flash from being read by unauthorized parties. It also protects against code corruption
resulting from accidental erasing and programming to the
internal flash memory. There are two different types of
security locks in the device security lock system: Hard Lock
and SoftLock.
8.2.3 High Speed Output Mode
In the High Speed Output mode, the PCA timer/counter is
compared with the 16-bit value pre-loaded into the module’s
compare registers (CCAPnH & CCAPnL). When a match
occurs, the modules corresponding output pin is toggled.
Additionally the event flag (CCFn) is set and an interrupt is
generated if ECCFn is set. The frequency of the output is
only dependent on the PCA timer/counter and will be the
same for all 5 modules but the duty cycle can vary depending on the value pre-loaded into the compare registers.
9.1 Hard Lock
When Hard Lock is activated, MOVC or IAP instructions
executed from an unlocked or SoftLocked program
address space, are disabled from reading code bytes in
Hard Locked memory blocks (See Table 9-2). Hard Lock
can either lock both flash memory blocks or just lock the 8
KByte flash memory block (Block 1). All External Host and
IAP commands except for Chip-Erase are ignored for
memory blocks that are Hard Locked.
8.2.4 Pulse Width Modulator
The Pulse Width Modulator mode generates 1-bit PWMs
by comparing the low byte of the PCA timer (CL) with the
low byte of the compare registers (CCAPnL). When CL <
CCAPnL the corresponding output pin is low. When CL >
CCAPnL the corresponding output pin is high. The frequency of the PWM is only dependent on the PCA timer/
counter and will be the same for all 5 modules. The duty
cycle will vary depending on the value in CCAPnL.
CCAPnL can be changed dynamically by loading a new
value into CCAPnH. This new value will be shifted into
CCAPnL when CL rolls over from FFH to 00H.
9.2 SoftLock
SoftLock allows flash contents to be altered under a secure
environment. This lock option allows the user to update
program code in the SoftLocked memory block through InApplication Programming Mode under a predetermined
secure environment. For example, if Block 1 (8K) memory
block is locked (Hard Locked or SoftLocked), and Block 0
(64K for SST89E564RD/SST89V564RD) memory block is
SoftLocked, code residing in Block 1 can program Block 0.
The following IAP mode commands issued through the
command mailbox register, SFCM, executed from a
Locked (Hard Locked or SoftLocked) block, can be operated on a SoftLocked block: Block-Erase, Sector-Erase,
Byte-Program and Byte-Verify.
8.2.5 Watchdog Timer
Only Module 4 can be programmed as a Watchdog Timer
(but it can still be programmed to the other modes if the
Watchdog Timer mode is not used). The Watchdog Timer
compares the PCA timer/counter value (CH & CL) with
Module 4’s compare registers (CCAP4H & CCAP4L).
When a match occurs, an internal reset will be generated if
the WDTE bit in CMOD register is set. This internal reset
will not cause the RST pin to be driven high. In order to
hold of the reset the user must periodically change the
compare value so it will never match the PCA timer.
In External Host Mode, SoftLock behaves the same as a
Hard Lock.
9.3 Security Lock Status
The three bits that indicate the device security lock
status are located in SFST[7:5]. As shown in Figure 91 and Table 9-1, the three security lock bits control the
lock status of the primary and secondary blocks of
memory. There are four distinct levels of security lock
status. In the first level, none of the security lock bits
are programmed and both blocks are unlocked. In the
second level, although both blocks are now locked and
cannot be programmed, they are available for read
operation via Byte-Verify. In the third level, three different options are available: Block 1 Hard Lock / Block 0
SoftLock, SoftLock on both blocks, and Hard Lock on
both blocks. Locking both blocks is the same as Level
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
39
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
2, block 1 except read operation isn’t available. The
fourth level of security is the most secure level. It
doesn’t allow read/program of internal memory or boot
from external memory. For details on how to program
the security lock bits refer to the External Host Mode
and In-Application Programming Section.
UUU/NN
Level 1
PUU/SS
Level 2
UPU/SS
UUP/LS
Level 3
UPP/LL
PPU/LS
PUP/LL
UPP/LL
Level 4
PPP/LL
555 ILL F19.1
FIGURE
Note:
9-1: SECURITY LOCK LEVELS
P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1), N = Not Locked, L = Hard Locked, S = SoftLocked
.
TABLE
9-1: SECURITY LOCK OPTIONS
Security Lock Bits1,2
SB21
Security Status of:
SB31
Level
SFST[7:5]
SB1
1
000
U
U
U
Unlock
Unlock
No Security Features are Enabled.
2
100
P
U
U
SoftLock
SoftLock
MOVC instructions executed from
external program memory are disabled from fetching code bytes from
internal memory, EA# is sampled and
latched on Reset, and further programming of the flash is disabled.
3
011
101
U
P
P
U
P
P
Hard Lock
Hard Lock
Level 2 plus Verify disabled, both
blocks locked.
010
U
P
U
SoftLock
SoftLock
Level 2 plus Verify disabled. Code in
Block 1 may program Block 0 and vice
versa.
110
001
P
U
P
U
U
P
Hard Lock
SoftLock
Level 2 plus Verify disabled. Code in
Block 1 may program Block 0.
111
P
P
P
Hard Lock
Hard Lock
Same as Level 3 Hard Lock/Hard
Lock, but MCU will start code execution from the internal memory regardless of EA#.
4
Block 1
Block 0
Security Type
T9-1.0 555
1. P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1).
2. SFST[7:5] = Security Lock Decoding Bits (SECD)
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
40
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
Level
9-2: SECURITY LOCK ACCESS TABLE
SFST[7:5]
Source
Address
Block 0/1
4
111b
(Hard Lock on both blocks)
External
Block 0/1
011b/101b
(Hard Lock on both blocks)
External
Block 0
001b/110b
(Block 0 = SoftLock,
Block 1 = Hard Lock)
Block 1
3
External
Block 0
010b
(SoftLock on both blocks)
Block 1
External
Block 0
2
100b
(SoftLock on both blocks)
Block 1
External
Block 0
1
000b
(Unlock)
Block 1
External
External Host
Byte-Verify
Allowed2
IAP
Byte-Verify
Allowed
Block 0/1
N
N
Y
Y
External
N/A
N
N
N
Block 0/1
N
N
N
N
External
N/A
N
N
N
Block 0/1
N
N
Y
Y
External
N
N
N
Y
Block 0/1
N
N
N
N
External
N/A
N
Y
Y
Block 0
N
N
Y
Y
Block 1
N
N
N
N
External
N/A
N
N
Y
Block 0
N
Y
Y
Y
Target
Address1
MOVC
Allowed
on 564RD
MOVC
Allowed
on 554RC
Block 1
N
N
Y
Y
External
N/A
N
N
Y
Block 0/1
N
N
N
N
External
N/A
N
Y
Y
Block 0
N
N
Y
Y
Block 1
N
Y
Y
Y
External
N/A
N
N
Y
Block 0
N
Y
Y
Y
Block 1
N
N
Y
Y
External
N/A
N
N
Y
Block 0/1
N
N
N
N
External
N/A
N
Y
Y
Block 0
Y
N
Y
Y
Block 1
Y
Y
Y
Y
External
N/A
N
N
Y
Block 0
Y
Y
Y
Y
Block 1
Y
N
Y
Y
External
N/A
N
N
Y
Block 0/1
Y
N
N
N
External
N/A
N
Y
Y
Block 0
Y
N
Y
Y
Block 1
Y
Y
Y
Y
External
N/A
N
N
Y
Block 0
Y
Y
Y
Y
Block 1
Y
N
Y
Y
External
N/A
N
N
Y
Y
Block 0/1
Y
Y
N
External
N/A
N
Y
Y
T9-2.0 555
1. Location of MOVC instruction
2. External Host Byte-Verify access does not depend on a source address.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
41
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
10.0 SYSTEM POWER AND CLOCK
OPTIONS
For more information on system level design techniques,
please review the Design Considerations for the SST
FlashFlex51 Family Microcontroller application note.
A system reset initializes the MCU and begins program
execution at program memory location 0000H. The reset
input for the device is the RST pin. In order to reset the
device, a logic level high must be applied to the RST pin for
at least two machine cycles (24 clocks), after the oscillator
becomes stable. ALE, PSEN# are weakly pulled high during reset. During reset, ALE and PSEN# output a high level
in order to perform a proper reset. This level must not be
affected by external element. A system reset will not affect
the 1 KByte of on-chip RAM while the device is running,
however, the contents of the on-chip RAM during power up
are indeterminate. Following reset, all Special Function
Registers (SFR) return to their reset values outlined in
Tables 3-5 to 3-9.
VDD
+
10µF
VDD
RST
8.2K
SST89E5x4/V5x4
C2
XTAL2
XTAL1
C1
10.1 Power-On Reset
555 ILL F20.0
At initial power up, the port pins will be in a random state
until the oscillator has started and the internal reset algorithm has weakly pulled all pins high. Powering up the
device without a valid reset could cause the MCU to
start executing instructions from an indeterminate
location. Such undefined states may inadvertently corrupt the code in the flash.
FIGURE 10-1: POWER-ON RESET CIRCUIT
10.2 Software Reset
The software reset is executed by changing SFCF[1]
(SWR) from “0” to “1”. A software reset will reset the program counter to address 0000H. All SFR registers will be
set to their reset values, except SFCF[1] (SWR), WDTC[2]
(WDTS), and RAM data will not be altered.
When power is applied to the device, the RST pin must be
held high long enough for the oscillator to start up (usually
several milliseconds for a low frequency crystal), in addition
to two machine cycles for a valid Power-On Reset. An
example of a method to extend the RST signal is to implement a RC circuit by connecting the RST pin to VDD
through a 10 µF capacitor and to VSS through an 8.2KΩ
resistor as shown in Figure 10-1. Note that if an RC circuit
is being used, provisions should be made to ensure the
VDD rise time does not exceed 1 millisecond and the oscillator start-up time does not exceed 10 milliseconds.
10.3 Brown-out Detection Reset
The device includes a Brown-out detection circuit to protect
the system from severed supplied voltage VDD fluctuations.
SST89E564’s internal Brown-out detection threshold is
3.8V, SST89V564’s brown-out detection threshold is 2.35V,
For Brown-out voltage parameters, please refer to Tables
11-3 and 11-4.
When VDD drops below this voltage threshold, the Brownout detector triggers the circuit to generate a Brown-out
interrupt but the CPU still runs until the supplied voltage
returns to the Brown-out detection voltage VBOD. The
default operation for a Brown-out detection is to cause a
processor reset.
For a low frequency oscillator with slow start-up time the
reset signal must be extended in order to account for the
slow start-up time. This method maintains the necessary
relationship between VDD and RST to avoid programming
at an indeterminate location, which may cause corruption
in the code of the flash. The Power-On detection is
designed to work as power up initially, before the voltage
reaches the Brown-out detection level. When this feature is
activated, the POF flag in the PCON register is set to indicate an initial power up condition. The POF flag will remain
active until cleared by software. Please refer to Section 3.5,
PCON register definition for detail information.
VDD must stay below VBOD at least four oscillator clock periods before the Brown-out detection circuit will respond.
Brown-out interrupt can be enabled by setting the EBO bit
in IEA register (address E8H, bit 3). If EBO bit is set and a
Brown-out condition occurs, a Brown-out interrupt will be
generated to execute the program at location 004BH. It is
required that the EBO bit be cleared by software after the
Brown-out interrupt is serviced. Clearing EBO bit when the
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
42
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
10.4 Interrupt Priority and Polling
Sequence
Brown-out condition is active will properly reset the device.
If Brown-out interrupt is not enabled, a Brown-out condition
will reset the program to resume execution at location
0000H.
The device supports eight interrupt sources under a four
level priority scheme. Table 10-1 summarizes the polling
sequence of the supported interrupts. Note that the SPI
serial interface and the UART share the same interrupt
vector.
TABLE 10-1: INTERRUPT POLLING SEQUENCE
Description
Interrupt Flag
Vector
Address
Interrupt
Enable
Interrupt
Priority
Arbitration
Ranking
Wake-Up
Power Down
Ext. Int0
IE0
0003H
EX0
PX0/H
1(highest)
yes
Brown-out
BOF
004BH
EBO
PBO/H
2
no
T0
TF0
000BH
ET0
PT0/H
3
no
Ext. Int1
IE1
0013H
EX1
PX1/H
4
yes
T1
TF1
001BH
ET1
PT1/H
5
no
UART/SPI
TI/RI/SPIF
0023H
ES
PS/H
6
no
T2
TF2, EXF2
002BH
ET2
PT2/H
7
no
T10-1.0 555
10.5 Power-Saving Modes
10.5.2 Power Down Mode
The device provides two power saving modes of operation
for applications where power consumption is critical. The
two modes are Idle and Power Down, see Table 10-2.
The Power Down mode is entered by setting the PD bit in
the PCON register. In the Power Down mode, the clock is
stopped and external interrupts are active for level sensitive
interrupts only. To retain the on-chip RAM and all of the special function registers’ values, the minimum VDD level is 2.0V.
10.5.1 Idle Mode
The device exits Power Down mode through either an
enabled external level sensitive interrupt or a hardware
reset. The start of the interrupt clears the PD bit and exits
Power Down. Holding the external interrupt pin low restarts
the oscillator, the signal must hold low at least 1024 clock
cycles before bringing back high to complete the exit. After
exit the interrupt service routine program execution
resumes beginning at the instruction immediately following
the instruction which invoked Power Down mode. A hardware reset starts the device similar to power-on reset.
Idle mode is entered setting the IDL bit in the PCON register. In Idle mode, the program counter (PC) is stopped. The
system clock continues to run and all interrupts and peripherals remain active. The on-chip RAM and the special function registers hold their data during this mode.
The device exits Idle mode through either a system interrupt or a hardware reset. Exiting Idle mode via system
interrupt, the start of the interrupt clears the IDL bit and
exits Idle mode. After exit the Interrupt Service Routine, the
interrupted program resumes execution beginning at the
instruction immediately following the instruction which
invoked the Idle mode. A hardware reset starts the device
similar to a power-on reset.
To exit properly out of Power Down, the reset or external
interrupt should not be executed before the VDD line is
restored to its normal operating voltage. Be sure to hold
VDD voltage long enough at its normal operating level for
the oscillator to restart and stabilize (normally less than
10 ms).
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
43
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE 10-2: POWER SAVING MODES
Mode
Initiated by
State of MCU
Exited by
Idle Mode
Software
(Set IDL bit in
PCON)
CLK is running.
Interrupts, serial port and timers/counters are active. Program Counter is stopped.
ALE and PSEN# signals at a
HIGH level during Idle. All
registers remain unchanged.
Enabled interrupt or hardware reset.
Start of interrupt clears IDL bit and
exits Idle mode, after the ISR RETI
instruction, program resumes execution beginning at the instruction following the one that invoked Idle mode. A
user could consider placing two or
three NOP instructions after the
instruction that invokes idle mode to
eliminate any problems. A hardware
reset restarts the device similar to a
power-on reset.
Power Down
Mode
Software
(Set PD bit in
PCON)
CLK is stopped. On-chip
SRAM and SFR data is maintained. ALE and PSEN# signals at a LOW level during
Power Down. External Interrupts are only active for level
sensitive interrupts, if
enabled.
Enabled external level sensitive interrupt or hardware reset. Start of interrupt clears PD bit and exits Power
Down mode, after the ISR RETI
instruction program resumes execution
beginning at the instruction following
the one that invoked Power Down
mode. A user could consider placing
two or three NOP instructions after the
instruction that invokes Power Down
mode to eliminate any problems. A
hardware reset restarts the device similar to a power-on reset.
T10-2.0 555
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
44
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
10.6 System Clock and Clock Options
RECOMMENDED
10.6.1 Clock Input Options and Recommended
Capacitor Values for Oscillator
Shown in Figure 10-2 are the input and output of an internal inverting amplifier (XTAL1, XTAL2), which can be configured for use as an on-chip oscillator.
Frequency
C1 and C2
RS (Optional)
< 8MHz
90-110pF
100Ω
8-12MHz
18-22pF
200Ω
>12MHz
18-22pF
200Ω
More specific information about on-chip oscillator design
can be found in the FlashFlex 51 Oscillator Circuit Design
Considerations application note.
When driving the device from an external clock source,
XTAL2 should be left disconnected and XTAL1 should be
driven.
10.6.2 Clock Doubling Option
At start-up, the external oscillator may encounter a higher
capacitive load at XTAL1 due to interaction between the
amplifier and its feedback capacitance. However, the
capacitance will not exceed 15 pF once the external signal
meets the VIL and VIH specifications.
By default, the device runs at 12 clocks per machine cycle
(x1 mode). The device has a clock doubling option to
speed up to 6 clocks per machine cycle. Please refer to
Table 10-3 for detail.
Clock double mode can be enabled either via the External
Host mode or the IAP mode. Please refer to Table 4-1 and
Table 4-2 for the External Host mode enabling command
and to Tables 4-5 and 4-6 for the IAP mode enabling command.
Crystal manufacturer, supply voltage, and other factors
may cause circuit performance to differ from one application to another. C1 and C2 should be adjusted appropriately for each design. The table below, shows the typical
values for C1 and C2 at a given frequency. If following the
satisfactory selection of all external components, the circuit
is still over driven, a series resistor, Rs, may be added.
RS
VALUES FOR CRYSTAL OSCILLATOR
The clock double mode is only for doubling the internal system clock and the internal flash memory, i.e.
EA#=1. To access the external memory and the peripheral
devices, careful consideration must be taken. Also note
that the crystal output (XTAL2) will not be doubled.
XTAL2
C2
NC
EXTERNAL
OSCILLATOR
SIGNAL
C1
XTAL1
XTAL2
XTAL1
Vss
Vss
External Clock Drive
Using the On-Chip Oscillator
555 ILL F21.0
FIGURE 10-2: OSCILLATOR CHARACTERISTICS
TABLE 10-3: CLOCK DOUBLING FEATURES
Standard Mode (x1)
Device
SST89E564RD/
SST89E554RC
SST89V564RD/
SST89V554RC
Clock Double Mode (x2)
Clocks per
Machine Cycle
Max. External Clock Frequency
(MHz)
Clocks per
Machine Cycle
Max. External Clock Frequency
(MHz)
12
40
6
20
12
33
6
16
T10-3.3 555
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
45
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
11.0 ELECTRICAL SPECIFICATION
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 150°C
Voltage on EA# Pin to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V
Transient Voltage (<20ns) on Any Other Pin to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +6.5V
Maximum IOL per I/O Pins P1.5, P1.6, P1.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Maximum IOL per I/O for All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W
Through Hole Lead Soldering Temperature (10 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
(Based on package heat transfer limitations, not device power consumption.
Note: This specification contains preliminary information on new products in production.
The specifications are subject to change without notice.
11.1 Operation Range
TABLE 11-1: OPERATING RANGE
Symbol
Description
Min.
Max
Unit
Ta
Ambient Temperature Under Bias
Standard
0
+70
Industrial
-40
+85
°C
°C
VDD
Supply Voltage
2.7
5.5
V
fOSC
Oscillator Frequency
For In-Application Programming
0
40
MHz
0.25
40
MHz
T11-1.0 555
11.2 Reliability Characteristics
TABLE 11-2: RELIABILITY CHARACTERISTICS
Symbol
NEND
1
Parameter
Minimum Specification
Units
Endurance
10,000
Cycles
JEDEC Standard A117
100
Years
JEDEC Standard A103
100 + IDD
mA
TDR1
Data Retention
ILTH1
Latch Up
Test Method
JEDEC Standard 78
T11-2.0 555
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
46
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
11.3 DC Electrical Characteristics
TABLE 11-3: DC ELECTRICAL CHARACTERISTICS FOR SST89E564RD AND SST89E554RC
Tamb = 0°C TO +70°C OR -40°C TO +85°C, 40MHZ DEVICES; 4.5-5.5V; VSS = 0V
Symbol
Parameter
Test Conditions
Min
Max
Units
VIL
Input Low Voltage
4.5 < VDD < 5.5
-0.5
0.2VDD - 0.1
V
VIH
Input High Voltage
4.5 < VDD < 5.5
0.2VDD + 0.9
VDD + 0.5
V
VIH1
Input High Voltage (XTAL1, RST)
4.5 < VDD < 5.5
0.7VDD
VDD + 0.5
V
VOL
Output Low Voltage (Ports 1.5, 1.6, 1.7)
1.0
V
VOL
Output Low Voltage (Ports 1, 2, 3)1
IOL = 100µA2
0.3
V
IOL = 1.6mA2
0.45
V
3.5mA2
1.0
V
IOL = 200µA2
0.3
V
IOL = 3.2mA2
0.45
V
VDD = 4.5V
IOL = 16mA
VDD = 4.5V
IOL =
VOL1
VOH
VOH1
Output Low Voltage (Port 0, ALE, PSEN#)1,3
Output High Voltage (Ports 1, 2, 3, ALE,
PSEN#)4
Output High Voltage (Port 0 in External Bus
Brown-out Detection Voltage
IIL
Logical 0 Input Current (Ports 1, 2, 3)
ITL
Logical 1-to-0 Transition Current (Ports 1, 2, 3)5
ILI
Input Leakage Current (Port 0)
RST Pull-down Resistor
CIO
Pin Capacitance6
IDD
Power Supply Current
VDD = 4.5V
Mode)4
VBOD
RRST
VDD = 4.5V
IOH = -10µA
VDD - 0.3
V
IOH = -30µA
VDD - 0.7
V
IOH = -60µA
VDD - 1.5
V
IOH = -200µA
VDD - 0.3
V
IOH = -3.2mA
VDD - 0.7
VDD = 4.5V
3.85
VIN = 0.4V
-1
VIN = 2V
0.45 < VIN < VDD-0.3
V
4.15
V
-75
µA
-650
µA
±10
µA
225
kΩ
15
pF
@ 12 MHz
70
mA
@ 40 MHz
88
mA
@ 12 MHz
23
mA
@ 40 MHz
50
mA
20
mA
42
mA
Tamb = 0°C to +70°C
80
µA
Tamb = -40°C to +85°C
90
40
@ 1 MHz, 25°C
IAP Mode
Active Mode
Idle Mode
@ 12 MHz
@ 40 MHz
Minimum VDD = 2V
Power Down Mode
µA
T11-3.2 555
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
47
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE 11-4: DC ELECTRICAL CHARACTERISTICS FOR SST89V564RD AND SST89V554RC
Tamb = 0°C TO +70°C OR -40°C TO +85°C, 33MHZ DEVICES; 2.7-3.6V; VSS = 0V
Symbol
Parameter
Test Conditions
Min
Max
Units
VIL
Input Low Voltage
2.7 < VDD < 3.3
-0.5
0.7
V
VIH
Input High Voltage
2.7 < VDD < 3.3
0.2VDD + 0.9
VDD + 0.5
V
VIH1
Input High Voltage (XTAL1, RST)
2.7 < VDD < 3.3
0.7VDD
VDD + 0.5
V
VOL
Output Low Voltage (Ports 1.5, 1.6, 1.7)
1.0
V
IOL = 100µA2
0.3
V
1.6mA2
0.45
V
IOL = 3.5mA2
1.0
V
IOL = 200µA2
0.3
V
3.2mA2
0.45
V
VDD = 2.7V
IOL = 16mA
VOL
Output Low Voltage (Ports 1, 2,
3)1
VDD = 2.7V
IOL =
VOL1
Output Low Voltage (Port 0, ALE,
PSEN#)1,3
VDD = 2.7V
IOL =
VOH
VOH1
Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)4
VDD = 2.7V
Output High Voltage (Port 0 in External Bus Mode)4
VBOD
Brown-out Detection Voltage
IIL
Logical 0 Input Current (Ports 1, 2, 3)
ITL
Logical 1-to-0 Transition Current (Ports 1, 2, 3)5
ILI
Input Leakage Current (Port 0)
RRST
RST Pull-down Resistor
CIO
Pin Capacitance6
IDD
Power Supply Current
IOH = -10µA
VDD - 0.3
V
IOH = -30µA
VDD - 0.7
V
IOH = -60µA
VDD - 1.5
V
IOH = -200µA
VDD - 0.3
V
IOH = -3.2mA
VDD - 0.7
V
VDD = 2.7V
VIN = 0.4V
2.25
2.55
V
-1
-75
µA
VIN = 2V
-650
µA
0.45 < VIN < VDD-0.3
±10
µA
225
kΩ
15
pF
@ 12 MHz
40
mA
@ 33 MHz
47
mA
@ 12 MHz
11.5
mA
@ 33 MHz
30
mA
@ 12 MHz
8.5
mA
@ 33 MHz
21
mA
Tamb = 0°C to +70°C
40
µA
Tamb = -40°C to +85°C
50
@ 1 MHz, 25°C
IAP Mode
Active Mode
Idle Mode
Minimum VDD = 2V
Power Down Mode
µA
T11-4.4 555
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
15mA
Maximum IOL per port pin:
26mA
Maximum IOL per 8-bit port:
Maximum IOL total for all outputs: 71mA
If IOL exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to sink current greater than the
listed test conditions.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
48
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
2. Capacitive loading on Ports 0 & 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 & 3. The noise due
to external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to
qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
3. Load capacitance for Port 0, ALE & PSEN#= 100pF, load capacitance for all other outputs = 80pF.
4. Capacitive loading on Ports 0 & 2 may cause the VOH on ALE and PSEN# to momentarily fall below the VDD - 0.7 specification when
the address bits are stabilizing.
5. Pins of Ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2V.
6. Pin capacitance is characterized but not tested. EA# is 25pF (max).
VDD
VDD
IDD
VDD = 2V
VDD
VDD
RST
RST
EA#
(NC)
EA#
89x564
89x564
CLOCK
SIGNAL
VDD
P0
P0
VDD
VDD
IDD
XTAL2
XTAL1
VSS
(NC)
XTAL2
XTAL1
VSS
555 ILL F24.0
555 ILL F22.0
All other pins disconnected
All other pins disconnected
FIGURE 11-3: IDD TEST CONDITION,
POWER-DOWN MODE
FIGURE 11-1: IDD TEST CONDITION,
ACTIVE MODE
VDD
VDD
IDD
VDD
P0
RST
EA#
89x564
CLOCK
SIGNAL
(NC)
XTAL2
XTAL1
VSS
555 ILL F23.0
All other pins disconnected
FIGURE 11-2: IDD TEST CONDITION,
IDLE MODE
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
49
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
30
Maximum Active IDD
25
Maximum Idle IDD
IDD (mA)
20
15
Typical Active IDD
5
Typical Idle IDD
0
5
FIGURE 11-4: IDD
VS.
555 ILL F32.2
10
10
15
20
25
Internal Clock Frequency (MHz)
30
35
FREQUENCY (SST89V564RD/SST89V554RC)
50
Maximum Active IDD
Maximum Idle IDD
30
20
555 ILL F33.2
IDD (mA)
40
Typical Active IDD
10
Typical Idle IDD
0
5
10
15
20
25
30
35
40
Internal Clock Frequency (MHz)
FIGURE 11-5: IDD
VS.
FREQUENCY (SST89E564RD/SST89E554RC)
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
50
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
11.4 AC Electrical Characteristics
AC Characteristics: (Over Operating Conditions: Load Capacitance for Port 0, ALE#, and PSEN# = 100pF;
Load Capacitance for All Other Outputs = 80pF)
TABLE 11-5: AC ELECTRICAL CHARACTERISTICS (1 OF 2)
Tamb = 0°C TO +70°C OR -40°C TO +85°C, VDD =2.7-3.6V@33MHZ, 4.5-5.5V@40MHZ, VSS =0
Oscillator
33MHz
Symbol
Parameter
1/TCLCL
TLHLL
TAVLL
Oscillator Frequency
ALE Pulse Width
Address Valid to ALE Low
Min
Max
46
40MHz
Min
Max
35
5
10
TLLAX
Address Hold After ALE Low
5
10
TLLIV
ALE Low to Valid Instr In
Variable
Min
Max
Units
0
40
MHz
2TCLCL - 15
ns
TCLCL - 25 (3V)
ns
TCLCL - 15 (5V)
ns
TCLCL - 25 (3V)
ns
TCLCL - 15 (5V)
ns
56
4TCLCL - 65 (3V)
4TCLCL - 45 (5V)
55
TLLPL
ALE Low to PSEN# Low
TPLPH
PSEN# Pulse Width
TPLIV
PSEN# Low to Valid Instr In
5
ns
10
TCLCL - 15 (5V)
ns
3TCLCL - 25 (3V)
3TCLCL - 15 (5V)
ns
60
66
35
Input Instr Hold After PSEN#
Input Instr Float After PSEN#
3TCLCL - 55 (3V)
3TCLCL - 50 (5V)
0
25
10
TAVIV
Address to Valid Instr In
72
65
TPLAZ
TRLRH
TWLWH
PSEN# Low to Address Float
RD# Pulse Width
Write Pulse Width (WE#)
TRLDV
RD# Low to Valid Data In
TRHDX
TRHDZ
Data Hold After RD#
Data Float After RD#
10
10
142
0
Address to RD# or WR# Low
116
90
46
70
TQVWX
Data Valid to WR# High to Low
Transition
TWHQX
Data Hold After WR#
ns
5TCLCL - 50 (5V)
183
60
TAVWL
10
0
152
66
ns
5TCLCL - 90 (3V)
150
ALE Low to RD# or WR# Low
ns
5TCLCL - 60 (5V)
ns
150
TLLWL
5TCLCL - 80 (3V)
6TCLCL - 40 (3V)
6TCLCL - 30 (5V)
36
Address to Valid Data In
ns
ns
120
38
TAVDV
TCLCL - 5 (3V)
TCLCL - 15 (5V)
ns
62
ALE Low to Valid Data In
ns
ns
120
75
TLLDV
ns
6TCLCL - 40 (3V)
6TCLCL - 30 (5V)
142
0
ns
TCLCL - 25 (3V)
25
TPXIX
TPXIZ
ns
0
3TCLCL - 25 (3V)
3TCLCL - 15 (5V)
5
©2002 Silicon Storage Technology, Inc.
ns
ns
2TCLCL - 25 (3V)
ns
2TCLCL - 12 (5V)
ns
8TCLCL - 90 (3V)
ns
8TCLCL - 50 (5V)
ns
9TCLCL - 90 (3V)
ns
9TCLCL - 75 (5V)
ns
3TCLCL + 25 (3V)
3TCLCL + 15 (5V)
ns
4TCLCL - 75 (3V)
ns
4TCLCL - 30 (5V)
ns
0
3
ns
0
ns
TCLCL - 27 (3V)
ns
TCLCL - 20 (5V)
ns
S71207-01-000 3/02
51
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE 11-5: AC ELECTRICAL CHARACTERISTICS (CONTINUED) (2 OF 2)
Tamb = 0°C TO +70°C OR -40°C TO +85°C, VDD =2.7-3.6V@33MHZ, 4.5-5.5V@40MHZ, VSS =0
Oscillator
33MHz
Symbol
Parameter
Min
TQVWH
Data Valid to WR# High
142
Max
40MHz
Min
Variable
Max
Min
125
TRLAZ
TWHLH
RD# Low to Address Float
RD# to WR# High to ALE High
0
5
Max
ns
7TCLCL - 50 (5V)
ns
0
55
10
40
Units
7TCLCL - 70 (3V)
0
ns
TCLCL - 25 (3V)
TCLCL + 25 (3V)
ns
TCLCL - 15 (5V)
TCLCL + 15 (5V)
ns
T11-5.1 555
11.5 AC Characteristics
Explanation of Symbols Each timing symbol has 5 characters. The first character is always a ‘T’ (stands for
time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that
signal. The following is a list of all the characters and what they stand for.
A:
C:
D:
H:
I:
L:
P:
Address
Clock
Input data
Logic level HIGH
Instruction (program memory contents)
Logic level LOW or ALE
PSEN#
Q:
R:
T:
V:
W:
X:
Z:
Output data
RD# signal
Time
Valid
WR# signal
No longer a valid logic level
High Impedance (Float)
For example:
TAVLL = Time from Address Valid to ALE Low
TLLPL = Time from ALE Low to PSEN# Low
VIHT
VILT
VLOAD +0.1V
VHT
VLOAD
VLT
VLOAD -0.1V
Timing Reference
Points
VOH -0.1V
VOL +0.1V
555 ILL F26b.0
555 ILL F26a.0
For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs, and begins to float when a 100 mV
change from the loaded VOH/VOL level occurs. IOL/IOH = ± 20mA.
AC Inputs during testing are driven at VIHT (VDD -0.5V) for Logic "1" and
VILT (0.45V) for a Logic "0". Measurement reference points for inputs and
outputs are at VHT (0.2VDD + 0.9) and VLT (0.2VDD - 0.1)
Note: VHT- VHIGH Test
VLT- VLOW Test
VIHT-VINPUT HIGH Test
VILT- VINPUT LOW Test
FIGURE 11-6: AC TESTING INPUT/OUTPUT, FLOAT WAVEFORM
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
52
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TLHLL
ALE
TAVLL
TLLIV
TLLPL
TPLPH
TPLIV
PSEN#
TPLAZ
TLLAX
PORT 0
TPXIZ
TPXIX
A7 - A0
A7 - A0
INSTR IN
TAVIV
PORT 2
A15 - A8
A15 - A8
555 ILL F27.1
FIGURE 11-7: EXTERNAL PROGRAM MEMORY READ CYCLE
TLHLL
ALE
TWHLH
PSEN#
TLLDV
TRLRH
TLLWL
RD#
TLLAX
TAVLL
PORT 0
TRLDV
TRLAZ
TRHDZ
TRHDX
A7-A0 FROM RI or DPL
DATA IN
A7-A0 FROM PCL
INSTR IN
TAVWL
TAVDV
PORT 2
P2[7:0] or A15-A8 FROM DPH
A15-A8 FROM PCH
555 ILL F28.1
FIGURE 11-8: EXTERNAL DATA MEMORY READ CYCLE
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
53
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TLHLL
ALE
TWHLH
PSEN#
TWLWH
TLLWL
WR#
TLLAX
TQVWX
TAVLL
TWHQX
TQVWH
PORT 0
A7-A0 FROM RI or DPL
DATA OUT
A7-A0 FROM PCL
INSTR IN
TAVWL
PORT 2
P2[7:0] or A15-A8 FROM DPH
A15-A8 FROM PCH
555 ILL F29.1
FIGURE 11-9: EXTERNAL DATA MEMORY WRITE CYCLE
TABLE 11-6: EXTERNAL CLOCK DRIVE
Oscillator
12MHz
Symbol
1/TCLCL
TCHCX
TCLCX
TCLCH
TCHCL
Parameter
Oscillator Frequency
High Time
Low Time
Rise Time
Fall Time
Min
40MHz
Max
Min
20
20
Max
Variable
Min
0
0.35TCLCL
0.35TCLCL
10
10
Max
40
0.65TCLCL
0.65TCLCL
Units
MHz
ns
ns
ns
ns
T11-6.1 555
VDD - 0.5
0.45 V
0.7VDD
TCHCX
0.2 VDD - 0.1
TCLCX
TCLCH
TCLCL
TCHCL
555 ILL F30.2
FIGURE 11-10: EXTERNAL CLOCK DRIVE WAVEFORM
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
54
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE 11-7: SERIAL PORT TIMING
Oscillator
12MHz
Min
40MHz
Parameter
TXLXL
Serial Port Clock Cycle Time
1.0
0.3
12TCLCL
µs
TQVXH
Output Data Setup to Clock Rising Edge
733
150
10TCLCL - 100
ns
TXHQX
Output Data Hold After Clock Rising Edge
83
TCLCL
ns
25
TCLCL
ns
TXHDX
Input Data Hold After Clock Rising Edge
TXHDV
Clock Rising Edge to Input Data Valid
Max
Min
Variable
Symbol
0
Max
Min
0
733
Max
0
Units
ns
150
10TCLCL - 100
ns
T11-7.1 555
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
TXLXL
CLOCK
TXHQX
TQVXH
OUTPUT DATA
WRITE TO SBUF
INPUT DATA
0
1
2
TXHDV
VALID
3
4
5
6
TXHDX
VALID
VALID
7
SET TI
VALID
VALID
VALID
VALID
VALID
SET R I
CLEAR RI
555 ILL F31.1
FIGURE 11-11: SHIFT REGISTER MODE TIMING WAVEFORMS
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
55
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
11.6 Flash Memory Programming Timing Diagrams with External Host Mode
TSU
RST
TES
PSEN#
ALE/PROG#
EA#
P2[7:6] ,P3[7:6]
TRD
0000b
TRD
0000b
P3[5:4] ,P2[5:0] ,P1
0030H
0031H
P0
BFH
Device ID
555 ILL F05.1
Device ID = 91H for SST89E564RD
90H for SST89V564RD
99H for SST89E554RC
98H for SST89V554RC
FIGURE 11-12: READ-ID
Reads chip signature and identification registers at the addressed location.
TSU
RST
TES
PSEN#
TADS
ALE/PROG#
TPROG
TDH
EA#
P3[3]
TPSB
P3[5:4], P2[5:0]
A5H/55H
P3[7:6], P2[7:6]
1001b
555 ILL F06.1
FIGURE 11-13: SELECT-BLOCK1 / SELECT-BLOCK0 (FOR SST89E564RD/SST89V564RD
ONLY)
Enables the selection of either of the flash memory blocks prior to issuing a Byte-Verify, Block-Erase, SectorErase, or Byte-Program.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
56
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TSU
RST
TES
PSEN#
TADS
ALE/PROG#
TDH
TPROG
EA#
TCE
P3[3]
P3[7:6], P2[7:6]
0001b
555 ILL F07.1
FIGURE 11-14: CHIP-ERASE
Erases both flash memory blocks. Security lock is ignored and the security bits are erased too.
TSU
RST
PSEN#
TES
TADS
ALE/PROG#
TDH
TPROG
EA#
TBE
P3[3]
P3[7:6], P2[7:6]
1101b
555 ILL F08.1
FIGURE 11-15: BLOCK-ERASE FOR SST89E564RD/SST89V564RD
Erases one of the flash memory blocks, if the security lock is not activated on that flash memory block.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
57
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TSU
RST
TES
PSEN#
TADS
ALE/PROG#
TDH
TPROG
EA#
TBE
P3[3]
P3[7:6], P2[7:6]
1101b
P3[5:4], P2[5:0]
AH
555 ILL F09.1
FIGURE 11-16: BLOCK-ERASE FOR SST89E554RC/SST89V554RC
Erases one of the flash memory blocks, if the security lock is not activated on that flash memory block.
TSU
RST
PSEN#
TES
TADS
ALE/PROG#
TDH
TPROG
EA#
P3[3]
TSE
P3[7:6], P2[7:6]
1011b
P3[5:4], P2[5:0]
AH
P1
AL
555 ILL F10.1
FIGURE 11-17: SECTOR-ERASE
Erases the addressed sector if the security lock is not activated on that flash memory block.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
58
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TSU
RST
TES
PSEN#
TADS
ALE/PROG#
TDH
TPROG
EA#
P3[3]
TPS
P3[5:4], P2[5:0]
AH
P1
AL
P0
DI
P3[7:6], P2[7:6]
1110b
555 ILL F11.1
FIGURE 11-18: BYTE-PROGRAM
Programs the addressed code byte if the byte location has been successfully erased and not yet programmed.
Byte-Program operation is only allowed when the security lock is not activated on that flash memory block.
TSU
RST
TES
PSEN#
TADS
ALE/PROG#
TPROG
TDH
EA#
P3[3]
TPS
P3[7:6], P2[7:6]
1111b / 0011b / 0101b
555 ILL F12.2
FIGURE 11-19: PROG-SB1 / PROG-SB2 / PROG-SB3
Programs the Security bits SB1, SB2 and SB3 respectively. Only a Chip-Erase will erase a programmed security bit.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
59
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TSU
RST
TES
PSEN#
TADS
ALE/PROG#
TDH
TPROG
EA#
P3[3]
TPS
P3[5:4], P2[5:0]
5AH / AAH
P3[7:6], P2[7:6]
1001b
555 ILL F13.1
FIGURE 11-20: PROG-SC0 / PROG-SC1
Programs the start-up configuration bit SC0/SC1. Only a Chip-Erase will erase a programmed SC0/SC1 bit.
Prog-SC1 applies to SST89E554RC/SST89V554RC only.
TSU
RST
TES
PSEN#
ALE/PROG#
EA#
TOA
P3[7:6], P2[7:6]
1100b
TAHA
P0
DO
TALA
P1
AL
P3[5:4], P2[5:0]
AH
555 ILL F14.2
FIGURE 11-21: BYTE-VERIFY
Reads the code byte from the addressed flash memory location if the security lock is not activated on that flash
memory block.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
60
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
12.0 PRODUCT ORDERING INFORMATION
Device
SST89x5x4xx
Speed
-
XX
Suffix1
-
X
Suffix2
-
XX
Package Modifier
I = 40 pins
J = 44 pins
Package Type
P = PDIP
N = PLCC
TQ = TQFP
Operation Temperature
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Operating Frequency
33 = 0-33MHz
40 = 0-40MHz
Feature Set and Flash Memory Size
564RD = C52 feature set + 64(72)* KByte
554RC = C52 feature set + 32(40)* KByte
* = 8K additional flash can be enabled
Voltage Range
E = 4.5-5.5V
V = 2.7-3.6V
Device Family
89 = C51 Core
12.1 Valid Combinations
Valid combinations for SST89E564RD
SST89E564RD-40-C-PI
SST89E564RD-40-C-NJ
SST89E564RD-40-C-TQJ
SST89E564RD-40-I-PI
SST89E564RD-40-I-NJ
SST89E564RD-40-I-TQJ
Valid combinations for SST89V564RD
SST89V564RD-33-C-PI
SST89V564RD-33-C-NJ
SST89V564RD-33-C-TQJ
SST89V564RD-33-I-PI
SST89V564RD-33-I-NJ
SST89V564RD-33-I-TQJ
Valid combinations for SST89E554RC
SST89E554RC-40-C-PI
SST89E554RC-40-C-NJ
SST89E554RC-40-C-TQJ
SST89E554RC-40-I-PI
SST89E554RC-40-I-NJ
SST89E554RC-40-I-TQJ
Valid combinations for SST89V554RC
SST89V554RC-33-C-PI
SST89V554RC-33-C-NJ
SST89V554RC-33-C-TQJ
SST89V554RC-33-I-PI
SST89V554RC-33-I-NJ
SST89V554RC-33-I-TQJ
Note:
Valid combinations are those products in mass production or will be in mass production.
Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
61
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
13.0 PACKAGING DIAGRAMS
40
CL
.600
.625
1
Pin #1 Identifier
.530
.557
2.020
2.070
.065
.075
12˚
4 places
.220 Max.
Base Plane
Seating Plane
.015 Min.
.063
.090
Note:
.045
.055
.015
.022
.100 †
.200
.100 BSC
0˚
15˚
.008
.012
.600 BSC
1. Complies with JEDEC publication 95 MS-011 AC dimensions (except as noted), although some dimensions may be more stringent.
† = JEDEC min is .115; SST min is less stringent
2. All linear dimensions are in inches (min/max).
40.pdipPI-ILL.7
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
40-PIN PLASTIC DUAL IN-LINE PINS (PDIP)
SST PACKAGE CODE: PI
TOP VIEW
Optional
Pin #1 Identifier
.042
.048
.685
.695
.646 †
.656
1
44
SIDE VIEW
.020 R.
MAX.
.042 x45˚
.056
.147
.158
.025 R.
.045
.042
.048
.685
.695
BOTTOM VIEW
.013
.021
.646 †
.656
.500
REF.
.026
.032
.590
.630
.050
BSC.
.100
.112
.050
BSC.
.165
.180
Note:
.020 Min.
.026
.032
44.PLCC.NJ-ILL.7
1. Complies with JEDEC publication 95 MS-018 AC dimensions (except as noted), although some dimensions may be more stringent.
† = JEDEC min is .650; SST min is less stringent
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
4. Coplanarity: 4 mils.
44-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NJ
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
62
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
Pin #1 Identifier
34
44
33
1
.30
.45
10.00
BSC
12.00
BSC
11
.80 BSC
23
12
10.00
BSC
12.00
BSC
.09
.20
22
.95
1.05
.05
.15
1.2
max.
.45
.75
0˚- 7˚
1.00 ref
44.tqfp-TQJ-ILL.6
Note:
1. Complies with JEDEC publication 95 MS-026 ACB dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±0.05) mm.
4. Package body dimensions do not include mold flash. Maximum allowable mold flash is .25mm.
44-LEAD THIN QUAD FLAT PACK (TQFP)
SST PACKAGE CODE: TQJ
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
63
555
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2002 Silicon Storage Technology, Inc.
S71207-01-000 3/02
64
555
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising