NXP LPC1343FHN33 32kB Flash, 8kB SRAM, USB Device Data Sheet

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and

8 kB SRAM; USB device

Rev. 5 — 6 June 2012 Product data sheet

The LPC1311/13/42/43 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM

Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.

The LPC1311/13/42/43 operate at CPU frequencies of up to 72 MHz. The ARM

Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM

Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

The peripheral complement of the LPC1311/13/42/43 includes up to 32 kB of flash memory, up to 8 kB of data memory, USB Device (LPC1342/43 only), one Fast-mode Plus

I 2 C-bus interface, one UART, four general purpose timers, and up to 42 general purpose

I/O pins.

Remark: The LPC1311/13/42/43 series consists of the LPC1300 series (parts

LPC1311/13/42/43) and the LPC1300L series (parts LPC1311/01 and LPC1313/01). The

LPC1300L series features the following enhancements over the LPC1300 series:

• Power profiles with lower power consumption in Active and Sleep modes.

• Four levels for BOD forced reset.

• Second SSP controller (LPC1313FBD48/01 only).

• Windowed Watchdog Timer (WWDT).

• Internal pull-up resistors pull up pins to full V

DD

level.

• Programmable pseudo open-drain mode for GPIO pins.

2. Features and benefits

 ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

 32 kB (LPC1343/13)/16 kB (LPC1342)/8 kB (LPC1311) on-chip flash programming memory.

 8 kB (LPC1343/13)/4 kB (LPC1342/11) SRAM.

 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.

 Selectable boot-up: UART or USB (USB on LPC1342/43 only).

 On LPC1342/43: USB MSC and HID on-chip drivers.

NXP Semiconductors

LPC1311_13_42_43

Product data sheet

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

 Serial interfaces:

 USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43 only).

 UART with fractional baud rate generation, modem, internal FIFO, and

RS-485/EIA-485 support.

 SSP controller with FIFO and multi-protocol capabilities.

 Additional SSP controller on LPC1313FBD48/01.

 I 2 C-bus interface supporting full I 2 C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode.

 Other peripherals:

 Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.

 Four general purpose counter/timers with a total of four capture inputs and 13 match outputs.

 Programmable WatchDog Timer (WDT).

 Programmable Windowed Watchdog Timer (WWDT) on LPC1311/01 and

LPC1313/01.

 System tick timer.

 Serial Wire Debug and Serial Wire Trace port.

 High-current output driver (20 mA) on one pin.

 High-current sink drivers (20 mA) on two I 2 C-bus pins in Fast-mode Plus.

 Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, and Deep power-down modes.

 Power profiles residing in boot ROM allowing to optimize performance and minimize power consumption for any given application through one simple function call.

(LPC1300L series, on LPC1311/01 and LPC1313/01 only.)

 Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.

 Single power supply (2.0 V to 3.6 V).

 10-bit ADC with input multiplexing among 8 pins.

 GPIO pins can be used as edge and level sensitive interrupt sources.

 Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, or the watchdog clock.

 Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 40 of the functional pins.

 Brownout detect with four separate thresholds for interrupt and one threshold for forced reset (four thresholds for forced reset on the LPC1311/01 and LPC1313/01 parts).

 Power-On Reset (POR).

 Integrated oscillator with an operating range of 1 MHz to 25 MHz.

 12 MHz internal RC oscillator trimmed to 1 % accuracy over the entire temperature and voltage range that can optionally be used as a system clock.

 Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.

 System PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator.

 For USB (LPC1342/43), a second, dedicated PLL is provided.

 Code Read Protection (CRP) with different security levels.

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 6 June 2012

© NXP B.V. 2012. All rights reserved.

2 of 74


LPC1311/13/42/43


 Unique device serial number for identification.

 Available as 48-pin LQFP package and 33-pin HVQFN package.

3. Applications

 eMetering

 Lighting

 Alarm systems

 White goods

Table 1.

Ordering information

Type number Package

Name

LPC1311FHN33 HVQFN33

LPC1311FHN33/01 HVQFN33


LPC1313FHN33/01 HVQFN33

LPC1313FBD48 LQFP48

LPC1313FBD48/01 LQFP48


LPC1342FBD48

LPC1343FHN33

LPC1343FBD48

LQFP48

HVQFN33

LQFP48

Description

HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm




LQFP48: plastic low profile quad flat package; 48 leads; body 7

× 7 ×

1.4 mm


× 7 ×

1.4 mm



× 7 ×

1.4 mm



× 7 ×

1.4 mm

Version n/a n/a n/a n/a

SOT313-2

SOT313-2 n/a

SOT313-2 n/a

SOT313-2

4.1 Ordering options

Table 2.

Ordering options for LPC1311/13/42/43

Type number Flash Total

SRAM

USB Power profiles

LPC1311FHN33 8 kB 4 kB no

LPC1311FHN33/01

LPC1313FHN33

LPC1313FHN33/01

LPC1313FBD48

LPC1313FBD48/01

8 kB

32 kB

32 kB

32 kB

32 kB

4 kB

8 kB

8 kB

8 kB

8 kB

-

-

-

-

yes no yes no yes

1

1

1

1

1

UART

RS-485

1

1

1

1

1

1

I 2 C/

Fast+

1

1

1

1

1

2

SSP ADC channels

1 8

8

8

8

8

8

Pins Package

33

33

33

33

48

48

HVQFN33

HVQFN33

HVQFN33

HVQFN33

LQFP48

LQFP48

LPC1311_13_42_43



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LPC1311/13/42/43


Table 2.

Ordering options for LPC1311/13/42/43 …continued

Type number Flash Total

SRAM

USB Power profiles

UART

RS-485

LPC1342FHN33 16 kB 4 kB Device no 1

LPC1342FBD48

LPC1343FHN33

LPC1343FBD48

16 kB

32 kB

32 kB

4 kB

8 kB

8 kB

Device

Device

Device no no no

1

1

1

1

1

1

I 2 C/

Fast+

1

1

1

1

SSP ADC channels

1 8

8

8

8

Pins Package

33

48

33

48

HVQFN33

LQFP48

HVQFN33

LQFP48

LPC1311_13_42_43



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LPC1311/13/42/43


GPIO ports

PIO0/1/2/3

RXD

TXD

DTR, DSR

(2)

, CTS,

DCD

(2)

, RI

(2)

, RTS

CT32B0_MAT[3:0]

CT32B0_CAP0

CT32B1_MAT[3:0]

CT32B1_CAP0

CT16B0_MAT[2:0]

CT16B0_CAP0

CT16B1_MAT[1:0]

CT16B1_CAP0

SWD

TEST/DEBUG

INTERFACE

ARM

CORTEX-M3

I-code bus

D-code bus system bus

USB pins

XTALIN

XTALOUT

RESET

LPC1311/13/42/43

USB PHY

(1)

USB DEVICE

CONTROLLER

(1) slave

IRC

WDO

POR

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS clocks and controls slave

ROM

AHB-LITE BUS

HIGH-SPEED

GPIO slave slave

AHB TO

APB

BRIDGE slave

FLASH

8/16/32 kB slave

SRAM

4/8 kB

UART

32-bit COUNTER/TIMER 0




10-bit ADC

SSP0

SSP1

(3)

I

2

C-BUS

WDT/WWDT

(4)

IOCONFIG

SYSTEM CONTROL

002aae722

(1) LPC1342/43 only.

(2) LQFP48 package only.

(3) On LPC1313FBD48/01 only.

(4) Windowed WatchDog Timer (WWDT) on LPC1311/01 and LPC1313/01 only.

Fig 1.

Block diagram

CLKOUT

AD[7:0]

SCK0,SSEL0

MISO0, MOSI0

SCK1,SSEL1

MISO1, MOSI0

SCL

SDA

LPC1311_13_42_43



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6.1 Pinning

LPC1311/13/42/43


PIO2_6

PIO2_0/DTR

RESET/PIO0_0

PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE

V

SS

XTALIN

5

6

XTALOUT

V

DD

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL0/CT16B0_CAP0

PIO2_7

PIO2_8

7

8

9

10

11

12

3

4

1

2

LPC1342FBD48

LPC1343FBD48

32

31

30

29

36

35

34

33

PIO3_0

R/PIO1_2/AD3/CT32B1_MAT1


R/PIO1_0/AD1/CT32B1_CAP0


PIO2_11/SCK0

PIO1_10/AD6/CT16B1_MAT1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

28

27

26

25

PIO0_9/MOSI0/CT16B0_MAT1/SWO

PIO0_8/MISO0/CT16B0_MAT0

PIO2_2/DCD

PIO2_10

002aae505

Fig 2.

LPC1342/43 LQFP48 package

LPC1311_13_42_43



Rev. 5 — 6 June 2012


6 of 74


LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller terminal 1 index area

PIO2_0/DTR

RESET/PIO0_0

PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE

XTALIN

XTALOUT

V

DD

PIO1_8/CT16B1_CAP0


1

2

3

4

5

6

7

8

LPC1342FHN33

LPC1343FHN33

33 V

SS

24

23

22

21

20

19

18

17









002aae516

Fig 3.

LPC1342/43 HVQFN33 package

Transparent top view

LPC1311_13_42_43



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7 of 74


LPC1311/13/42/43


PIO2_6

PIO2_0/DTR/SSEL1

(1)

RESET/PIO0_0

PIO0_1/CLKOUT/CT32B0_MAT2

V

SS

XTALIN

5

6

XTALOUT

V

DD

PIO1_8/CT16B1_CAP0


PIO2_7

PIO2_8

7

8

9

10

11

12

3

4

1

2

LPC1313FBD48

LPC1313FBD48/01

32

31

30

29

36

35

34

33

PIO3_0





PIO2_11/SCK0



28 PIO0_9/MOSI0/CT16B0_MAT1/SWO

27

26


PIO2_2/DCD/MISO1

(1)

25 PIO2_10

002aae513

(1) SSP1 or UART function on LPC1313FBD48/01 only.

Fig 4.

LPC1313 LQFP48 package

LPC1311_13_42_43



Rev. 5 — 6 June 2012


8 of 74


LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller terminal 1 index area

PIO2_0/DTR

RESET/PIO0_0

PIO0_1/CLKOUT/CT32B0_MAT2

XTALIN

XTALOUT

V

DD

PIO1_8/CT16B1_CAP0


1

2

3

4

5

6

7

8

LPC1311FHN33

LPC1311FHN33/01

LPC1313FHN33

LPC1313FHN33/01

33 V

SS

24

23

22

21

20

19

18

17









002aae517

Transparent top view

Fig 5.

LPC1311/13 HVQFN33 package

LPC1311_13_42_43



Rev. 5 — 6 June 2012


9 of 74


LPC1311/13/42/43


6.2 Pin description

Table 3.

LPC1313/42/43 LQFP48 pin description table

Symbol

RESET/PIO0_0

Pin

3

[2]

Start logic input yes

Type Reset state

[1]

Description

PIO0_1/CLKOUT/

CT32B0_MAT2/

USB_FTOGGLE

4

[3]

yes

I

I/O -

I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter.

I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler or the USB device enumeration (USB on LPC1342/43 only, see description of

PIO0_3).

O CLKOUT — Clockout pin.

PIO0_2/SSEL0/

CT16B0_CAP0

10 [3]

yes

O

O

-

-

CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

USB_FTOGGLE — USB 1 ms Start-of-Frame signal (LPC1342/43 only).

I/O I; PU PIO0_2 — General purpose digital input/output pin.

I

I/O -

-

SSEL0 — Slave select for SSP0.

CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

PIO0_3/USB_VBUS

14 [3]

yes

PIO0_4/SCL

PIO0_5/SDA

PIO0_6/

USB_CONNECT/

SCK0

PIO0_7/CTS

PIO0_8/MISO0/

CT16B0_MAT0

15

16

22

23

27

[4]

[4]

[3]

[3]

[3]

yes yes yes yes yes

I

I/O I; PU PIO0_3 — General purpose digital input/output pin. LPC1342/43 only: A LOW level on this pin during reset starts the ISP command handler, a HIGH level starts the USB device enumeration.

USB_VBUS — Monitors the presence of USB bus power

(LPC1342/43 only).

I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain).

I/O SCL — I 2 C-bus clock input/output (open-drain). High-current sink only if I 2 C Fast-mode Plus is selected in the I/O configuration register.

I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain).

I/O SDA — I 2 C-bus data input/output (open-drain). High-current sink only if I 2 C Fast-mode Plus is selected in the I/O configuration register.


O USB_CONNECT — Signal used to switch an external 1.5 k

Ω resistor under software control. Used with the SoftConnect USB feature (LPC1342/43 only).

I/O SCK0 — Serial clock for SSP0.

I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current output driver).

I CTS — Clear To Send input for UART.


I/O -

O -

MISO0 — Master In Slave Out for SSP0.


LPC1311_13_42_43



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LPC1311/13/42/43


Table 3.

LPC1313/42/43 LQFP48 pin description table …continued

Symbol Pin

28 [3]



[1]

Description

PIO0_9/MOSI0/

CT16B0_MAT1/

SWO


I/O MOSI0 — Master Out Slave In for SSP0.

O

O -


SWO — Serial wire trace output.

SWCLK/PIO0_10/

SCK0/CT16B0_MAT2

29 [3]

yes I

I/O -

I; PU SWCLK — Serial wire clock.

PIO0_10 — General purpose digital input/output pin.

R/PIO0_11/

AD0/CT32B0_MAT3

32 [5]

yes -

I/O -

O -

SCK0 — Serial clock for SSP0.


I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block.

R/PIO1_0/

AD1/CT32B1_CAP0

R/PIO1_1/

AD2/CT32B1_MAT0

33

34

[5]

[5]

yes yes

I

I

-

I

I/O -

-


AD0 — A/D converter, input 0.

-

O

I/O -




-




R/PIO1_2/

AD3/CT32B1_MAT1

SWDIO/PIO1_3/

AD4/

CT32B1_MAT2

I

I/O -

-



-

O

I/O -




I

O -



I/O I; PU SWDIO — Serial wire debug input/output.

I/O PIO1_3 — General purpose digital input/output pin.

I

O

-

-




PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

35 [5]

yes

39 [5]

yes

40 [5]

yes

I

I

O -

-

-



WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch filter. This pin must be pulled HIGH externally to enter Deep power-down mode and pulled LOW to exit Deep power-down mode.

A LOW-going pulse as short as 50 ns wakes up the part.

LPC1311_13_42_43



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LPC1311/13/42/43


Table 3.


Symbol

PIO1_5/RTS/

CT32B0_CAP0

Pin

45 [3]


Type Reset

I/O

O state

[1]

I; PU

Description


RTS — Request To Send output for UART.

PIO1_6/RXD/

CT32B0_MAT0

46 [3]

yes

I CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.


I

O

-

-

RXD — Receiver input for UART.


PIO1_7/TXD/

CT32B0_MAT1

47 [3]

yes

PIO1_8/CT16B1_CAP0 9

[3]

yes

I/O

O -

I; PU PIO1_7 — General purpose digital input/output pin.

TXD — Transmitter output for UART.

O CT32B0_MAT1 — Match output 1 for 32-bit timer 0.


PIO1_9/CT16B1_MAT0 17

PIO1_10/AD6/

CT16B1_MAT1

PIO1_11/AD7

30

42

[3]

[5]

[5]

yes yes yes





I

O -



I



PIO2_0/DTR/SSEL1 2

[3]

yes

PIO2_1/DSR/SCK1

PIO2_2/DCD/MISO1

13

26

[3]

[3]

yes yes


O DTR — Data Terminal Ready output for UART.

I/O SSEL1 — Slave Select for SSP1 (LPC1313FBD48/01 only).


I

I/O -

DSR — Data Set Ready input for UART.

SCK1 — Serial clock for SSP1 (LPC1313FBD48/01 only).

I


DCD — Data Carrier Detect input for UART.

PIO2_3/RI/MOSI1

PIO2_4

PIO2_4

PIO2_5

PIO2_5

PIO2_6

PIO2_7

PIO2_8

PIO2_9

38

18

19

21

[3]

[3]

[3]

[3]

20 [3]

1

[3]

11 [3]

12 [3]

24 [3]

yes yes yes yes yes yes yes yes yes

I/O MISO1 — Master In Slave Out for SSP1 (LPC1313FBD48/01 only).


I

I/O -

RI — Ring Indicator input for UART.

MOSI1 — Master Out Slave In for SSP1 (LPC1313FBD48/01 only).

I/O I; PU PIO2_4 — General purpose digital input/output pin (LPC1342/43 only).

I/O I; PU PIO2_4 — General purpose digital input/output pin (LPC1313 only).







LPC1311_13_42_43



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LPC1311/13/42/43


Table 3.


Symbol

PIO2_10

PIO2_11/SCK0

Pin

25 [3]

31 [3]

Start logic input yes yes

Type Reset

I/O

I/O state

[1]

I; PU

I; PU

Description



PIO3_0/DTR

36 [3]

yes



PIO3_1/DSR

PIO3_2/DCD

PIO3_3/RI

37

43

48

[3]

[3]

[3]

yes yes yes

O DTR — Data Terminal Ready output for UART (LPC1311/01 and

LPC1313/01 only).


I DSR — Data Set Ready input for UART (LPC1311/01 and

LPC1313/01 only).


I DCD — Data Carrier Detect input for UART (LPC1311/01 and

LPC1313/01 only).

I


RI — Ring Indicator input for UART (LPC1311/01 and LPC1313/01 only).

PIO3_4

PIO3_5

USB_DM

USB_DP

V

DD

XTALIN

XTALOUT

V

SS

18 [3]

21 [3]

19 [6]

20 [6]

8;

44

6

[7]

-

no no no no

7

[7]

5;

41

-

I

I

I



I/O F USB_DM — USB bidirectional D − line (LPC1342/43 only).

I/O F USB_DP — USB bidirectional D+ line (LPC1342/43 only).

-

O -

-

3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage.

Input to the oscillator circuit and internal clock generator circuits.

Input voltage must not exceed 1.8 V.

Output from the oscillator amplifier.

Ground.

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (for V

DD

= 3.3 V, pin is pulled up to 2.6 V for parts LPC1311/13/42/43 and pulled up to 3.3 V for parts LPC1311/01 and LPC1313/01); IA = inactive, no pull-up/down enabled;

F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.

[2] 5 V tolerant pad. See

Figure 37

for pad characteristics. RESET functionality is not available in Deep power-down mode. Use the

WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the

Deep power-down mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see

Figure 36 ).

[4] I

2

C-bus pads compliant with the I

2

C-bus specification for I

2

C standard mode and I

2

C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see

Figure 36

).

[6] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant.

[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

LPC1311_13_42_43



Rev. 5 — 6 June 2012


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LPC1311/13/42/43


Table 4.

LPC1311/13/42/43 HVQFN33 pin description table

Symbol

RESET/PIO0_0

Pin Start logic input

2 [2]

yes I


[1]

Description

I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

PIO0_1/CLKOUT/

CT32B0_MAT2/

USB_FTOGGLE

3 [3]

I/O PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter.

yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler or the USB device enumeration (USB on LPC1342/43 only, see description of PIO0_3).

PIO0_2/SSEL0/

CT16B0_CAP0

PIO0_3/

USB_VBUS

PIO0_4/SCL

PIO0_5/SDA

PIO0_6/

USB_CONNECT/

SCK0

PIO0_7/CTS

PIO0_8/MISO0/

CT16B0_MAT0

PIO0_9/MOSI0/

CT16B0_MAT1/

SWO

O

O -

CLKOUT — Clock out pin.


O USB_FTOGGLE — USB 1 ms Start-of-Frame signal (LPC1342/43 only).

yes I/O I; PU PIO0_2 — General purpose digital input/output pin.

8 [3]

I

I/O -

-

SSEL0 — Slave select for SSP0.


9 [3]

yes I/O I; PU PIO0_3 — General purpose digital input/output pin. LPC1342/43 only: A

LOW level on this pin during reset starts the ISP command handler, a

HIGH level starts the USB device enumeration.

I USB_VBUS — Monitors the presence of USB bus power (LPC1342/43 only).

10

[4]

yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain).

I/O SCL — I 2 C-bus clock input/output (open-drain). High-current sink only if

I 2 C Fast-mode Plus is selected in the I/O configuration register.

11

[4]

yes I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain).

I/O SDA — I 2 C-bus data input/output (open-drain). High-current sink only if

I 2 C Fast-mode Plus is selected in the I/O configuration register.

15

[3]


O USB_CONNECT — Signal used to switch an external 1.5 k

Ω resistor under software control. Used with the SoftConnect USB feature

(LPC1342/43 only).


16

[3]

yes I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current output driver).

17

[3]

I CTS — Clear To Send input for UART.


I/O -

O -

MISO0 — Master In Slave Out for SSP0.


18

[3]


I/O MOSI0 — Master Out Slave In for SSP0.

O

O -


SWO — Serial wire trace output.

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Table 4.

LPC1311/13/42/43 HVQFN33 pin description table …continued

Symbol Pin

19

[3]

Start logic input yes I


[1]

I; PU

Description

SWCLK — Serial wire clock.

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2


I/O -

O -

SCK0 — Serial clock for SSP0.


R/PIO0_11/AD0/

CT32B0_MAT3

21

[5]

yes I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block.

I

I/O -

-



R/PIO1_0/AD1/

CT32B1_CAP0

R/PIO1_1/AD2/

CT32B1_MAT0

22

[5]

yes -

O

I/O -




23

[5]

yes -

I

I

-




R/PIO1_2/AD3/

CT32B1_MAT1

SWDIO/PIO1_3/

AD4/

CT32B1_MAT2

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

PIO1_5/RTS/

CT32B0_CAP0

PIO1_6/RXD/

CT32B0_MAT0

I

I/O -

-



24

[5]

yes -

O

I/O -




I

O -



25

[5]

yes I/O I; PU SWDIO — Serial wire debug input/output.


I

O -



26

[5]


I AD5 — A/D converter, input 5.

I

O -

-


WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch filter.

This pin must be pulled HIGH externally to enter Deep power-down mode and pulled LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part.

30

[3]


I

O

-

RTS — Request To Send output for UART.


31

[3]


I RXD — Receiver input for UART.


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Table 4.

LPC1311/13/42/43 HVQFN33 pin description table …continued

Symbol

PIO1_7/TXD/

CT32B0_MAT1

Pin

32

[3]


Type Reset

I/O

O state

[1]

I; PU

Description


TXD — Transmitter output for UART.

PIO1_8/

CT16B1_CAP0

7 [3]

O CT32B0_MAT1 — Match output 1 for 32-bit timer 0. yes I/O I; PU PIO1_8 — General purpose digital input/output pin.

PIO1_9/

CT16B1_MAT0

12

[3]



PIO1_10/AD6/

CT16B1_MAT1

20

[5]



PIO1_11/AD7

PIO2_0/DTR

PIO3_2

PIO3_4

PIO3_5

USB_DM

USB_DP

V

DD

XTALIN

XTALOUT

V

SS

28

[3]

13

[3]

14

[3]

13

[6]

14

[6]

6;

29

4 [7]

I

O -



27

[5]


I AD7 — A/D converter, input 7.

1 [3]

yes I/O

O -

I; PU PIO2_0 — General purpose digital input/output pin.

DTR — Data Terminal Ready output for UART.

5 [7]

-

-

yes no no no no

I

I

I/O

I/O

I; PU

I; PU


PIO3_4 — General purpose digital input/output pin (LPC1311/13 only).


I/O F USB_DM — USB bidirectional D − line (LPC1342/43 only).

I/O F USB_DP — USB bidirectional D+ line (LPC1342/43 only).

O -

-

3.3 V supply voltage to the internal regulator, the external rail, and the

ADC. Also used as the ADC reference voltage.

Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V.

Output from the oscillator amplifier.

33 Thermal pad. Connect to ground.

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (for V

DD

= 3.3 V, pin is pulled up to 2.6 V for parts LPC1311/13/42/43 and pulled up to 3.3 V for parts LPC1311/01 and LPC1313/01); IA = inactive, no pull-up/down enabled.

F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.

[2] 5 V tolerant pad. See

Figure 37

for pad characteristics. RESET functionality is not available in Deep power-down mode. Use the

WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the

Deep power-down mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see

Figure 36 ).

[4] I 2 C-bus pads compliant with the I 2 C-bus specification for I 2 C standard mode and I 2 C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant (see

Figure 36 ).

[6] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant.

[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

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7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus (see Figure 1

). The I-code and D-code core buses are faster than the system bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware multiply and divide, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller, and multiple core buses capable of simultaneous accesses.

Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical

Reference Manual which is available on the official ARM website.

7.3 On-chip flash program memory

The LPC1311/13/42/43 contain 32 kB (LPC1313 and LPC1343), 16 kB (LPC1342), or

8 kB (LPC1311) of on-chip flash memory.

7.4 On-chip SRAM

The LPC1311/13/42/43 contain a total of 8 kB (LPC1343 and LPC1313) or 4 kB (LPC1342 and LPC1311) on-chip static RAM memory.

7.5 Memory map

The LPC1311/13/42/43 incorporate several distinct memory regions. Figure 6

shows the overall map of the entire address space from the user program viewpoint following reset.

The interrupt vector area supports address remapping.

The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.

The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.

Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral.

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4 GB

1 GB

0.5 GB

I-code/D-code memory space

0 GB

LPC1311/13/42/43

AHB peripherals

0x5020 0000

0xFFFF FFFF reserved private peripheral bus reserved

AHB peripherals

0xE010 0000

0xE000 0000

0x5020 0000

0x5000 0000

12-15

8-11

4-7

0-3

16 - 127 reserved

GPIO PIO3

GPIO PIO2

GPIO PIO1

GPIO PIO0

0x5004 0000

0x5003 0000

0x5002 0000

0x5001 0000

0x5000 0000 reserved

APB peripherals reserved

0x4008 0000

0x4000 0000

APB peripherals

18

17

16

15

14

22

23 - 31 reserved

SSP1 (LPC1313FBD48/01)

19 - 21 reserved system control

IOCONFIG

SSP0 flash controller

PMU

0x4008 0000

0x4005 C000

0x4005 8000

0x4004 C000

0x4004 8000

0x4004 4000

0x4004 0000

0x4003 C000

0x4003 8000

0x2000 0000

10 - 13 reserved reserved

16 kB boot ROM reserved

8 kB SRAM (LPC1313/1343)

4 kB SRAM (LPC1311/1342) reserved

32 kB on-chip flash (LPC1313/43)

16 kB on-chip flash (LPC1342)

8 kB on-chip flash (LPC1311)

0x1FFF 4000

0x1FFF 0000

0x1000 2000

0x1000 1000

0x1000 0000

6

5

4

3

2

1

0

9

8

7 reserved

USB (LPC1342/43 only)

ADC

32-bit counter/timer 1




UART

WDT/WWDT

I

2

C-bus

0x0000 8000

0x0000 4000

0x0000 2000

+ 256 words active interrupt vectors

0x0000 0000

0x0000 0400

0x0000 0000

0x4002 8000

0x4002 4000

0x4002 0000

0x4001 C000

0x4001 8000

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

0x4000 4000

0x4000 0000

002aae723

Fig 6.

LPC1311/13/42/43 memory map

7.6 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.

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7.6.1 Features

• Controls system exceptions and peripheral interrupts.

• On the LPC1311/13/42/43, the NVIC supports up to 17 vectored interrupts. In addition, up to 40 of the individual GPIO inputs are NVIC-vector capable.

• 8 programmable interrupt priority levels, with hardware priority level masking

• Relocatable vector table.

• Software interrupt generation.

7.6.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both.

7.7 IOCONFIG block

The IOCONFIG block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.

7.8 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation.

LPC1311/13/42/43 use accelerated GPIO functions:

• GPIO block is a dedicated AHB peripheral so that the fastest possible I/O timing can be achieved.

• Entire port value can be written in one instruction.

Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both.

7.8.1 Features

• Bit level port registers allow a single instruction to set or clear any number of bits in one write operation.

• Direction control of individual bits.

• All I/O default to inputs with pull-up resistors enabled after reset with the exception of the I 2 C-bus pins PIO0_4 and PIO0_5.

• Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG block for each GPIO pin.

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• On the LPC1311/13/42/43, all GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 2.6 V (V

DD

= 3.3 V) if their pull-up resistor is enabled in the IOCONFIG block.

• On the LPC1311/01 and LPC1313/01, all GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (V

DD

= 3.3 V) if their pull-up resistor is enabled in the IOCONFIG block.

7.9 USB interface (LPC1342/43 only)

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot-plugging and dynamic configuration of the devices. All transactions are initiated by the host controller.

The LPC1342/43 USB interface is a device controller with on-chip PHY for device functions.

7.9.1 Full-speed USB device controller

The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, and endpoint buffer memory. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled.

7.9.1.1

Features

• Dedicated USB PLL available.

• Fully compliant with USB 2.0 specification (full speed).

• Supports 10 physical (5 logical) endpoints with up to 64 bytes buffer RAM per endpoint (see

Table 5

).

• Supports Control, Bulk, Isochronous, and Interrupt endpoints.

• Supports SoftConnect feature.

• Double buffer implementation for Bulk and Isochronous endpoints.

3

4

2

3

4

1

2

0

1

Table 5.

USB device endpoint configuration

Logical endpoint

Physical endpoint

Endpoint type Direction Packet size

(byte)

0 0 Control out 64

1

2

3

4

Control

Interrupt/Bulk

Interrupt/Bulk

Interrupt/Bulk in out in out

64

64

64

64

7

8

5

6

9

Interrupt/Bulk

Interrupt/Bulk

Interrupt/Bulk

Isochronous

Isochronous in out in out in

64

64

64

512

512

Double buffer no no no no no no yes yes yes yes

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7.10 UART

The LPC1311/13/42/43 contains one UART.

Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode.

The UART includes a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.10.1 Features

• Maximum UART data bit rate of 4.5 MBit/s.

• 16-byte receive and transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values.

• Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation.

• Support for RS-485/9-bit mode.

• Support for modem control.

7.11 SSP serial I/O controller

The LPC1311/13/42/43 contain one SSP controller. An additional SSP controller is available on the LPC1313FBD48/01 package.

The SSP controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data.

7.11.1 Features

• Maximum SSP speed of 36 Mbit/s (master) or 6 Mbit/s (slave)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

7.12 I 2 C-bus serial I/O controller

The LPC1311/13/42/43 contain one I 2 C-bus controller.

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The I 2 C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line

(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I 2 C is a multi-master bus and can be controlled by more than one bus master connected to it.

7.12.1 Features

• The I 2 C-bus interface is a standard I 2 C-bus compliant interface with true open-drain pins. The I 2 C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer.

• The I 2 C-bus can be used for test and diagnostic purposes.

• The I 2 C-bus controller supports multiple address recognition and a bus monitor mode.

7.13 10-bit ADC

The LPC1311/13/42/43 contains one ADC. It is a single 10-bit successive approximation

ADC with eight channels.

7.13.1 Features

• 10-bit successive approximation ADC.

• Input multiplexing among 8 pins.

• Power-down mode.

• Measurement range 0 V to V

DD

.

• 10-bit conversion time

≥ 2.44 μs (up to 400 kSamples/s).

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition of input pin or timer match signal.

• Individual result registers for each ADC channel to reduce interrupt overhead.

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7.14 General purpose external event counter/timers

The LPC1311/13/42/43 includes two 32-bit counter/timers and two 16-bit counter/timers.

The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt.

7.14.1 Features

• A 32-bit/16-bit counter/timer with a programmable 32-bit/16-bit prescaler.

• Counter or timer operation.

• One capture channel per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt.

• Four match registers per timer that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

7.15 System tick timer

The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval, normally set to 10 ms.

7.16 Watchdog timer

Remark: The standard Watchdog timer is available on parts LPC1311/13/42/43.

The purpose of the watchdog is to reset the microcontroller within a selectable time period. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time.

7.16.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.

• Incorrect/incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

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• Selectable time period from (T cy(WDCLK) multiples of T cy(WDCLK)

× 4.

× 256 × 4) to (T cy(WDCLK)

× 2 24 × 4) in

• The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator

(IRC), the watchdog oscillator, or the main clock. This gives a wide range of potential timing choices of watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability.

7.17 Windowed WatchDog Timer (WWDT)

Remark: The windowed watchdog timer is available on parts LPC1311/01 and

LPC1313/01.

The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window.

7.17.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out period.

• Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to watchdog time-out.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.

• Incorrect feed sequence causes reset or interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (T cy(WDCLK)

× 256 × 4) to (T cy(WDCLK) multiples of T cy(WDCLK)

× 4.

× 2 24 × 4) in

• The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated watchdog oscillator (WDO). This gives a wide range of potential timing choices of watchdog operation under different power conditions.

7.18 Clocking and power control

7.18.1 Integrated oscillators

The LPC1311/13/42/43 include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application.

Following reset, the LPC1311/13/42/43 will operate from the internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency.

See

Figure 7 for an overview of the LPC1311/13/42/43 clock generation.

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IRC oscillator watchdog oscillator

MAINCLKSEL

(main clock select)

IRC oscillator system oscillator

SYSPLLCLKSEL

(system PLL clock select)

SYSTEM PLL main clock

SYSTEM CLOCK

DIVIDER system clock

2

AHB clock 0

(system)

AHBCLKCTRL

(AHB clock enable)

AHB clock 1

(ROM)

14

AHBCLKCTRL

AHB clocks

2 to 15

(memories and peripherals)

AHB clock 16

(IOCONFIG)

AHBCLKCTRL

SSP0/1 PERIPHERAL

CLOCK DIVIDER

SSP0/1

UART PERIPHERAL

CLOCK DIVIDER

ARM TRACE

CLOCK DIVIDER

UART

ARM trace clock

SYSTICK TIMER

CLOCK DIVIDER

SYSTICK timer

IRC oscillator

WDT CLOCK

DIVIDER

WDT watchdog oscillator

WDTUEN

(WDT clock update enable) system oscillator USB PLL

USB 48 MHz CLOCK

DIVIDER

USB

USBPLLCLKSEL

(USB clock select) USBUEN

(USB clock update enable)

IRC oscillator system oscillator watchdog oscillator

CLKOUT PIN CLOCK

DIVIDER

CLKOUT pin

CLKOUTUEN

(CLKOUT update enable)

002aae859

The USB clock is available on LPC1342/43 only. SSP1 is available on LPC1313FBD48/01 only.

Fig 7.

LPC1311/13/42/43 clocking generation block diagram

7.18.1.1

Internal RC oscillator

The IRC may be used as the clock source for the WDT, and/or as the clock that drives the system PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range.

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Upon power-up, any chip reset, or wake-up from Deep power-down mode, the

LPC1311/13/42/43 use the IRC as the clock source. Software may later switch to one of the other available clock sources.

7.18.1.2

System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using the PLL. On the LPC1342/43, the system oscillator must be used to provide the clock source to USB.

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL.

7.18.1.3

Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and temperature is ±40 % (see also

Table 16

).

7.18.2 System PLL and USB PLL

The LPC1342/43 contain a system PLL and a dedicated PLL for generating the 48 MHz

USB clock. The LPC131x contain the system PLL only. The system and USB PLLs are identical.

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.

The PLL settling time is 100

μs.

7.18.3 Clock output

The LPC1311/13/42/43 features a clock output function that routes the IRC oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin.

7.18.4 Wake-up process

The LPC1311/13/42/43 begin operation at power-up and when awakened from Deep power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source.

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7.18.5 Power control

The LPC1311/13/42/43 support a variety of power control features. There are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements.

In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control.

7.18.5.1

Power profiles (LPC1300L series, LPC1311/01 and LPC1313/01 only)

The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile. The power configuration routine configures the

LPC1311/01 and the LPC1313/01 for one of the following power modes:

• Default mode corresponding to power configuration after reset.

• CPU performance mode corresponding to optimized processing capability.

• Efficiency mode corresponding to optimized balance of current consumption and CPU performance.

• Low-current mode corresponding to lowest power consumption.

In addition, the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock.

7.18.5.2

Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses.

7.18.5.3

Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut down. As an exception, the user has the option to keep the watchdog oscillator and the

BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows for additional power savings.

Up to 40 pins total can serve as external wake-up pins to the start logic to wake up the chip from Deep-sleep mode (see

Section 7.19.1

).

Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source should be switched to IRC before entering Deep-sleep mode, because the IRC can be switched on and off glitch-free.

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7.18.5.4

Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

WAKEUP pin. The LPC1311/13/42/43 can wake up from Deep power-down mode via the

WAKEUP pin.

A LOW-going pulse as short as 50 ns wakes up the part from Deep power-down mode.

When entering Deep power-down mode, an external pull-up resistor is required on the

WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from floating while in Deep power-down mode.

7.19 System control

7.19.1 Start logic

The start logic connects external pins to corresponding interrupts in the NVIC. Each pin

shown in Table 3 and

Table 4

as input to the start logic has an individual interrupt in the

NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when the chip is running. In addition, an input signal on the start logic pins can wake up the chip from Deep-sleep mode when all clocks are shut down.

The start logic must be configured in the system configuration block and in the NVIC before being used.

7.19.2 Reset

Reset has four sources on the LPC1311/13/42/43: the RESET pin, the Watchdog reset, power-on reset (POR), and the Brown-Out Detection (BOD) circuit. The RESET pin is a

Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller.

When the internal reset is removed, the processor begins executing at address 0, which is initially the reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

7.19.3 Brownout detection

The LPC1311/13/42/43 includes four levels for monitoring the voltage on the V

DD

pin. If this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the

NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. An additional threshold level can be selected to cause a forced reset of the chip.

7.19.4 Code security (Code Read Protection - CRP)

This feature of the LPC1311/13/42/43 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. In-Application

Programming (IAP) commands are not affected by the CRP.

In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP (NO_ISP mode). For details see the LPC13xx user manual.

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CAUTION

LPC1311/13/42/43


There are three levels of Code Read Protection:

1. CRP1 disables access to chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when

CRP is required and flash field updates are needed but all sectors can not be erased.

2. CRP2 disables access to chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to chip via the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via

UART.

If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.

7.19.5 Boot loader

The boot loader controls initial operation after reset and also provides the means to program the flash memory. This could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system.

The boot loader code is executed every time the part is reset or powered up. The loader can either execute the ISP command handler or the user application code, or, on the

LPC1342/43, it can program the flash image via an attached MSC device through USB

(Windows operating system only). A LOW level during reset applied to the PIO0_1 pin is considered as an external hardware request to start the ISP command handler or the USB device enumeration. The state of PIO0_3 determines whether the UART or USB interface will be used (LPC1342/43 only).

7.19.6 APB interface

The APB peripherals are located on one APB bus.

7.19.7 AHB-Lite

The AHB-Lite connects the instruction (I-code) and data (D-code) CPU buses of the ARM

Cortex-M3 to the flash memory, the main static RAM, and the boot ROM.

7.19.8 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs

serve as external interrupts (see Section 7.19.1

).

7.19.9 Memory mapping control

The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset

Register contained in the NVIC.

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The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table must be located on a 256 word boundary.

7.20 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M3. Serial wire debug is supported.

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Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol

V

DD

Parameter supply voltage (core and external rail)

Conditions

V

I input voltage

I

I

I

DD

SS latch

T stg

T j(max)

P tot(pack)

V

ESD supply current ground current

I/O latch-up current storage temperature maximum junction temperature

5 V tolerant I/O pins; only valid when the V

DD

supply voltage is present per supply pin per ground pin

−(0.5V

DD

) < V

I

< (1.5V

DD

);

T j

< 125 °C non-operating total power dissipation (per package) based on package heat transfer, not device power consumption electrostatic discharge voltage human body model; all pins

[2]

[3]

-

-

-

-

Min

2.0

−0.5

-

−65

Max

3.6

+5.5

100

100

100

+150

150

1.5

Unit

V

V mA mA mA

°C

°C

W

[4]

−6500

+6500 V

[1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

SS

unless otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC specification J-STD-033B.1 for further details.

[4] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k

Ω series resistor.

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Table 7.

Static characteristics

T amb

= −40 °C to +85 °C, unless otherwise specified.

Symbol Parameter Conditions

V

DD supply voltage (core and external rail)

I

LPC1300 series (LPC1311/13/42/43) power consumption

DD supply current Active mode; V

T amb

= 25

°C; code while(1){}

DD

= 3.3 V; executed from flash; system clock = 12 MHz

Min

[2]

2.0

Typ [1]

3.3

system clock = 72 MHz

[3][4][5]

[6][7]

-

[4][5][6]

[8][7]

-

4

17

Sleep mode;

V

DD

= 3.3 V; T amb

= 25 °C; system clock = 12 MHz

[3][4][5]

[6][7]

2

Deep-sleep mode; V

DD

= 3.3 V;

T amb

= 25 °C

[4][9][7]

30

Deep power-down mode;

V

DD

= 3.3 V; T amb

= 25 °C

[10]

-

LPC1300L series (LPC1311/01, LPC1313/01) power consumption in low-current mode

[11]

220

I

DD supply current Active mode; V

DD

= 3.3 V;

T amb

= 25

°C; code while(1){} executed from flash; system clock = 12 MHz

[3][4][5]

[6][7]

2 system clock = 72 MHz

[4][5][6]

[8][7]

-

I

I

Sleep mode;

V

DD

= 3.3 V; T amb

= 25 °C; system clock = 12 MHz

[3][4][5]

[6][7]

-

Deep-sleep mode; V

DD

= 3.3 V;

T amb

= 25 °C

Deep power-down mode;

V

DD

= 3.3 V; T amb

= 25 °C

[4][9][7]

[10]

-

-

Standard port pins and RESET pin; see Figure 21

,

Figure 22 , Figure 23

,

Figure 24

I

IL

-

IH

OZ

LOW-level input current V

I

= 0 V; on-chip pull-up resistor disabled

HIGH-level input current

OFF-state output current

V

I

= V

DD disabled

; on-chip pull-down resistor

V

O

= 0 V; V

O

= V

DD

; on-chip pull-up/down resistors disabled

-

-

V

I input voltage pin configured to provide a digital function

[12][13]

[14]

0 -

13

1

2

220

0.5

0.5

0.5

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-

-

-

-

-

-

-

-

-

-

Max

3.6

10

10

10

5.0

Unit

V mA mA mA

μA nA mA mA mA

μA nA nA nA nA

V


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Table 7.

Static characteristics …continued

T amb



V

O

V

IH output voltage

HIGH-level input voltage output active

I

I

I

V

IL

V hys

V

OH

V

OL

OH

OL

OHS

LOW-level input voltage hysteresis voltage

HIGH-level output voltage

LOW-level output voltage

HIGH-level output current

LOW-level output current

HIGH-level short-circuit output current

2.5 V

≤ V

DD

≤ 3.6 V; I

OH

=

−4 mA

2.0 V ≤ V

DD

< 2.5 V; I

OH

= −3 mA

2.5 V

≤ V

DD

≤ 3.6 V; I

OL

= 4 mA

2.0 V ≤ V

DD

< 2.5 V; I

OL

= 3 mA

2.5 V

≤ V

DD

V

OH

= V

DD

≤

3.6 V;

− 0.4 V

2.0 V

≤ V

DD

V

OH

= V

DD

< 2.5 V;

− 0.4 V

2.5 V

≤ V

DD

≤

3.6 V; V

OL

= 0.4 V

2.0 V ≤ V

DD

< 2.5 V; V

OL

= 0.4 V

V

OH

= 0 V

I

I

OLS

V

OL

= V

DD

I pd

I pu pull-down current pull-up current

V

V

I

I

= 5 V

= 0 V

V

DD

< V

I

< 5 V

High-drive output pin (PIO0_7); see

Figure 19

and Figure 21

I

IL

LOW-level short-circuit output current

IH

LOW-level input current V

I

= 0 V; on-chip pull-up resistor disabled

HIGH-level input current

V

I

= V

DD

; on-chip pull-down resistor disabled

I

OZ

V

I

OFF-state output current input voltage

V

O

= 0 V; V

O

= V

DD

; on-chip pull-up/down resistors disabled pin configured to provide a digital function

V

O

V

IH

V

V

V

V

IL hys

OH

OL output voltage

HIGH-level input voltage

LOW-level input voltage output active hysteresis voltage

HIGH-level output voltage

LOW-level output voltage

2.5 V ≤ V

2.0 V

≤ V

DD

DD

≤ 3.6 V; I

< 2.5 V; I

OH

OH

= −20 mA

=

−12 mA

2.5 V ≤ V

DD

≤ 3.6 V; I

OL

= 4 mA

2.0 V

≤ V

DD

< 2.5 V; I

OL

= 3 mA

[15]

-

[15]

-

-

-

-

-

-

-

Min

0

0.7V

DD

-

-

0.4

V

DD

− 0.4 -

V

DD

− 0.4 -

-

-

-

−4

-

-

−3

4

3

10

−15

0

[12][13]

[14]

0

0

0.7V

DD

0.4

V

DD

− 0.4 -

V

DD

− 0.4 -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Typ [1]

50

−50

0

0.5

0.5

0.5

-

-

−45

50

150

−85

0

Max

-

V

DD

-

-

-

-

0.3V

DD

-

0.4

0.4

Unit

V

V

V

V

V

V

V

V mA mA mA mA mA mA

μA

μA

μA

10

10

10

5.0

-

V

DD

-

-

0.3V

DD

-

0.4

0.4

V

V

V

V

V

V

V

V nA nA nA

V

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Table 7.


T amb


Symbol Parameter

I

I

OH

OL

HIGH-level output current


Conditions

2.5 V ≤ V

DD

≤ 3.6 V;

V

OH

= V

DD

− 0.4 V

2.0 V ≤ V

DD

V

OH

= V

DD

< 2.5 V;

− 0.4 V;

2.5 V ≤ V

DD

≤ 3.6 V; V

OL

= 0.4 V

2.0 V

≤ V

DD

< 2.5 V; V

OL

= 0.4 V

I

I pd pu pull-down current pull-up current

V

I

= 5 V

V

I

= 0 V

V

DD

< V

I

< 5 V

I 2 C-bus pins (PIO0_4 and PIO0_5); see

Figure 20

V

IH

HIGH-level input voltage

LOW-level input voltage

I

I

V

IL

V hys

I

OL

OL

LI hysteresis voltage


LOW-level output current input leakage current

V

OL

= 0.4 V; I 2 C-bus pins configured as standard mode pins

2.5 V ≤ V

DD

≤ 3.6 V

2.0 V ≤ V

DD

< 2.5 V

V

OL

= 0.4 V; I 2 C-bus pins configured as Fast-mode Plus pins

2.5 V ≤ V

DD

≤ 3.6 V

2.0 V

≤ V

DD

< 2.5 V

V

I

= V

DD

V

I

= 5 V

Oscillator pins

V i(xtal)

V o(xtal) crystal input voltage crystal output voltage

USB pins (LPC1342/43 only)

I

OZ

V

BUS

V

DI

OFF-state output current bus supply voltage differential input sensitivity voltage

0 V < V

I

< 3.3 V

|(D+) − (D−)|

V

CM differential common mode voltage range

V th(rs)se single-ended receiver switching threshold voltage

V

OL

LOW-level output voltage includes V

DI

range for low-/full-speed;

R

L

of 1.5 k

Ω to 3.6 V

[17]

-

Min

20

12

4

3

10

−15

0

-

-

-

-

Typ [1]

50

−50

0

-

-

-

-

Max

150

−85

0

-

-

0.7V

DD

-

-

0.05V

DD

-

0.3V

DD

V

V

V mA mA

μA

μA

μA

Unit mA mA

3.5

3.0

20

[16]

-

16

-

−0.5

−0.5

[17]

-

[17]

-

[17]

0.2

[17]

0.8

[17]

0.8

-

-

-

-

-

-

-

-

-

-

2

10

+1.8

+1.8

-

-

V

V

V

V

μA

V

V mA

μA

μA

-

-

4

22

+1.95

+1.95

±10

-

5.25

2.5

2.0

0.18

mA mA

V

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Table 7.


T amb



V

OH

C

Z trans

DRV

HIGH-level output voltage driven; for low-/full-speed;

R

L

of 15 k

Ω to GND transceiver capacitance pin to GND driver output impedance for driver which is not high-speed capable with 33

Ω series resistor; steady state drive

[17]

Min

2.8

[17]

-

[18][17]

36

-

-

-

Typ [1] Max

3.5

20

44.1

Unit

V pF

Ω

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25

°C), nominal supply voltages.

[2] For LPC1342 and LPC1343 only: For USB operation 3.0 V

≤ V

DD

≤ 3.6 V. Guaranteed by design.

[3] IRC enabled; system oscillator disabled; system PLL disabled.

[4] I

DD

measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[5] BOD disabled.

[6] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART, SSP, trace clock, and SysTick timer disabled in the syscon block.

[7] For LPC1342/43: USB_DP and USB_DM pulled LOW externally.

[8] IRC disabled; system oscillator enabled; system PLL enabled.

[9] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 0FFF.

[10] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode.

[11] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.

[12] Including voltage on outputs in 3-state mode.

[13] V

DD

supply voltage must be present.

[14] 3-state outputs go into 3-state mode in Deep power-down mode.

[15] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[16] To V

SS

.

[17] 3.0 V

≤ V

DD

≤ 3.6 V.

[18] Includes external resistors of 33

Ω ± 1 % on USB_DP and USB_DM.

Table 8.

ADC static characteristics

T amb

= −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz, V

DD

= 2.5 V to 3.6 V.

Symbol Parameter Conditions Min Typ analog input voltage 0 -

E

O

E

G

E

T

R vsi

V

IA

C ia

E

D

E

L(adj) analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error voltage source interface resistance

[1][2]

[3]

-

[4]

-

[5]

-

[6]

-

-

-

-

-

-

-

-

-

-

-

R i input resistance

[7][8]

2.5

[1] The ADC is monotonic, there are no missing codes.

[2] The differential linearity error (E

D

) is the difference between the actual step width and the ideal step width. See

Figure 8 .

Max

V

DD

1

±1

±1.5

±3.5

0.6

±4

40

Unit

V pF

LSB

LSB

LSB

%

LSB k

Ω

M

Ω

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[3] The integral non-linearity (E

L(adj)

) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See

Figure 8 .

[4] The offset error (E

O

) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 8

.

[5] The gain error (E

G

) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 8

.

[6] The absolute error (E

T

) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve. See Figure 8

.

[7] T amb

= 25

°C; maximum sampling frequency f s

= 400 kSamples/s and analog input capacitance C ia

= 1 pF.

[8] Input resistance R i

depends on the sampling frequency f s

: R i

= 1 / (f s

× C ia

).

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LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller offset error

E

O gain error

E

G

1020

1019

1018

1023

1022

1021

(2) code out

7

6

5

4

3

2

1

0

1 offset error

E

O

2

(4)

(5)

(3)

3 4

1 LSB

(ideal)

5 6 7

V

IA

(LSB ideal

)

(1)

1018 1019 1020 1021 1022 1023 1024

1 LSB =

V

DD

− V

SS

1024

002aaf426

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E

D

).

(4) Integral non-linearity (E

L(adj)

).

(5) Center of a step of the actual transfer curve.

Fig 8.

ADC characteristics

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9.1 BOD static characteristics for LPC1300 series

Remark: Applies to parts LPC1311/13/42/43 and all their packages.

Table 9.

BOD static characteristics [1]

T amb

= 25 °C.


V th threshold voltage interrupt level 0 assertion de-assertion interrupt level 1 assertion de-assertion interrupt level 2 assertion de-assertion interrupt level 3 assertion de-assertion reset level 0 assertion de-assertion

-

-

-

-

-

-

-

-

-

-

Min Typ

1.69

1.84

2.29

2.44

2.59

2.74

2.87

2.98

1.49

1.64

-

-

-

-

-

-

-

-

-

-

Max Unit

V

V

V

V

V

V

V

V

V

V

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC13xx

user manual.

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9.2 BOD static characteristics for LPC1300L series (LPC1311/01 and

LPC1313/01)

Remark: Applies to parts LPC1311/01 and LPC1313/01 and all packages.

Table 10.

BOD static characteristics [1]

T amb

= 25 °C.


V th threshold voltage interrupt level 0 assertion de-assertion interrupt level 1 assertion de-assertion interrupt level 2 assertion de-assertion interrupt level 3 assertion de-assertion reset level 0 assertion de-assertion reset level 1 assertion de-assertion reset level 2 assertion de-assertion reset level 3 assertion de-assertion

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Min Typ

1.65

1.80

2.22

2.35

2.52

2.66

2.80

2.90

1.46

1.63

2.06

2.15

2.35

2.43

2.63

2.71

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Max Unit

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC13xx

user manual.

9.3 Power consumption for LPC1300 series

Remark: Applies to parts LPC1311/13/42/43 and all their packages.

Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC13xx user manual):

• Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.

• Configure GPIO pins as outputs using the GPIOnDIR registers.

• Write 0 to all GPIOnDATA registers to drive the outputs LOW.

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72 MHz

002aae993

18

I

DD

(mA)

15

12

48 MHz

9

36 MHz

24 MHz

6

12 MHz

3

2.0

2.4

2.8

3.2

3.6

V

DD

(V)

Conditions: T amb

= 25

°C; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally (LPC1342/43).

Fig 9.

Typical supply current versus regulator supply voltage V

DD

in Active mode

(LPC1311/13/42/43)

002aae994

18

I

DD

(mA)

15

72 MHz

12 48 MHz

36 MHz

9

24 MHz

6

12 MHz

3

−

40

−

15 10 35 60 temperature ( ° C)

85

Conditions: V

DD

= 3.3 V; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally (LPC1342/43).

Fig 10. Typical supply current versus temperature in Active mode (LPC1311/13/42/43)

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72 MHz

48 MHz

36 MHz

24 MHz

12 MHz

002aae995

10

I

DD

(mA)

8

6

4

2

0

− 40 − 15 10 35 60 temperature (

°

C)

85

Conditions: V

DD

= 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally (LPC1342/43).

Fig 11. Typical supply current versus temperature in Sleep mode (LPC1311/13/42/43)

002aae998

80

I

DD

(

μ

A)

60

V

DD

= 3.6 V

3.3 V

2.0 V

40

20

0

− 40 − 15 10 35 60 temperature (

°

C)

85

Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 0FFF; USB_DP and USB_DM pulled LOW externally

(LPC1342/43).

Fig 12. Typical supply current versus temperature in Deep-sleep mode (analog blocks disabled; LPC1311/13/42/43)

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1.2

I

DD

(

μ

A)

0.6

LPC1311/13/42/43


002aae996

VDD = 3.6 V

3.3 V

2.0 V

0.4

0

− 40 − 15 10 35 60 temperature (

°

C)

85

Fig 13. Typical supply current versus temperature in Deep power-down mode

(LPC1311/13/42/43)

9.4 Power consumption for LPC1300L series (LPC1311/01 and

LPC1313/01)

Remark: Applies to parts LPC1311/01 and LPC1313/01 and all their packages.

Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC13xx user manual):

• Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.

• Configure GPIO pins as outputs using the GPIOnDIR registers.

• Write 0 to all GPIOnDATA registers to drive the outputs LOW.

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72 MHz

002aag235

16

I

DD

(mA)

12

8

4

48 MHz

36 MHz

24 MHz

12 MHz

0

2.0

2.4

2.8

3.2

3.6

V

DD

(V)

Conditions: T amb

= 25

°C; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; low-current mode.

Fig 14. Typical supply current versus regulator supply voltage V

DD

in Active mode

(LPC1311/01 and LPC1313/01)

002aag236

16

I

DD

(mA)

12

72 MHz

8

4

48 MHz

36 MHz

24 MHz

12 MHz

0

˗40 ˗15 10 35 60 temperature (°C)

85

Conditions: V

DD

= 3.3 V; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; low-current mode.

Fig 15. Typical supply current versus temperature in Active mode (LPC1311/01 and

LPC1313/01)

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72 MHz

002aag237

8

I

DD

(mA)

6

4

2

48 MHz

36 MHz

24 MHz

12 MHz

0

˗40 ˗15 10 35 60 temperature (°C)

85

Conditions: V

DD

= 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; low-current mode.

Fig 16. Typical supply current versus temperature in Sleep mode (LPC1311/01 and

LPC1313/01)

002aag238

I

DD

(μA)

8

6

4

VDD = 2.0 V

3.3 V

3.6 V

2

0

˗40 ˗15 10 35 60 temperature (°C)

85

Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 0FFF.

Fig 17. Typical supply current versus temperature in Deep-sleep mode (analog blocks disabled, LPC1311/01 and LPC1313/01)

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0.6

I

DD

(

µA)

0.4

LPC1311/13/42/43


002aag239

VDD = 3.6 V

3.3 V

2.0 V

0.2

0

˗40 ˗15 10 35 60 temperature (

°C)

85

Fig 18. Typical supply current versus temperature in Deep power-down mode

(LPC1311/01 and LPC1313/01)

9.5 Peripheral power consumption

The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG or

PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at T amb

= 25

°C. Unless noted otherwise, the system oscillator and PLL are running in both measurements.

The supply currents are shown for system clock frequencies of 12 MHz, 48 MHz, and

72 MHz.

Table 11.

Power consumption for individual analog and digital blocks

Peripheral Typical supply current in mA Notes

IRC n/a

0.23

-

12 MHz 48 MHz 72 MHz

-

0.23

-

System oscillator running; PLL off; independent of main clock frequency.

IRC running; PLL off; independent of main clock frequency.

System oscillator at 12 MHz

Watchdog oscillator at

500 kHz/2

0.002

System oscillator running; PLL off; independent of main clock frequency.

BOD

Main or USB PLL -

0.045

ADC

CLKOUT

-

-

CT16B0

CT16B1

CT32B0

CT32B1

-

-

-

-

-

0.26

0.07

0.14

0.01

0.01

0.01

0.01

-

0.34

0.25

0.56

0.05

0.04

0.05

0.04

-

0.48

0.37

0.82

0.08

0.06

0.07

0.06

-

-

-

-

-

-

Independent of main clock frequency.

Main clock divided by 4 in the CLKOUTDIV register.

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Table 11.

Power consumption for individual analog and digital blocks …continued

Peripheral Typical supply current in mA Notes n/a 12 MHz 48 MHz 72 MHz

GPIO 0.21

0.80

1.17

IOCONFIG -

I2C

ROM

SSP0

SSP1

UART

WDT

USB

USB

-

-

-

-

-

-

-

-

-

0.00

0.03

0.04

0.11

0.11

0.20

0.01

1.84

0.02

0.12

0.15

0.41

0.41

0.76

0.05

3.91

4.19

-

0.02

0.17

0.22

0.60

0.60

1.11

0.08

5.71

-

-

-

-

GPIO pins configured as outputs and set to LOW. Direction and pin state are maintained if the GPIO is disabled in the

SYSAHBCLKCFG register.

-

On LPC1313FBD48/01 only.

Main clock selected as clock source for the WDT.

Main clock selected as clock source for the USB. USB_DP and USB_DM pulled LOW externally.

Dedicated USB PLL selected as clock source for the USB.

USB_DP and USB_DM pulled LOW externally.

9.6 Electrical pin characteristics

3.6

V

OH

(V)

3.2

T = 85 ° C

25 ° C

−

40

°

C

002aae990

2.8

2.4

2

0 10 20 30 40 50

I

OH

(mA)

60

Conditions: V

DD

= 3.3 V; on pin PIO0_7.

Fig 19. High-drive output: Typical HIGH-level output voltage V

OH

versus HIGH-level output current I

OH

.

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60

I

OL

(mA)

40

LPC1311/13/42/43


T = 85

°

C

25

°

C

− 40 ° C

002aaf019

20

0

0 0.2

0.4

0.6

V

OL

(V)

Conditions: V

DD

= 3.3 V; on pins PIO0_4 and PIO0_5.

Fig 20. I 2 C-bus pins (high current sink): Typical LOW-level output current I

OL

versus

LOW-level output voltage V

OL

002aae991

15

I

OL

(mA)

10

T = 85 ° C

25 ° C

−

40

°

C

5

0

0 0.2

0.4

0.6

V

OL

(V)

Conditions: V

DD

= 3.3 V; standard port pins and PIO0_7.

Fig 21. Typical LOW-level output current I

OL

versus LOW-level output voltage V

OL

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T = 85

°

C

25 ° C

− 40 ° C

002aae992

3.6

V

OH

(V)

3.2

2.8

2.4

2

0 8 16 24

I

OH

(mA)

Conditions: V

DD

= 3.3 V; standard port pins.

Fig 22. Typical HIGH-level output voltage V

OH

versus HIGH-level output source current

I

OH

002aae988

10

I pu

( μ A)

−

10

−

30

−

50

T = 85 ° C

25

°

C

−

40

°

C

−

70

0 1 2 3

Conditions: V

DD


Fig 23. Typical pull-up current I pu

versus input voltage V i

4

V

I

(V)

5

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T = 85 ° C

25 ° C

− 40 ° C

002aae989

80

I pd

(

μ

A)

60

40

20

0

0 1 2 3

Conditions: V

DD


Fig 24. Typical pull-down current I pd

versus input voltage V i

4

V

I

(V)

5

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10. Dynamic characteristics

10.1 Power-up ramp conditions

Table 12.

Power-up characteristics

T amb

= −40 °C to +85 °C.

Symbol Parameter Conditions t r rise time at t = t

1

: 0 < V

I

≤ 400 mV t wait wait time

V

I input voltage at t = t

1

on pin V

DD

[1]

[1][2]

Min

0

12

0 -

-

-

Typ

-

Max

500

Unit ms

μs

400 mV

[1] See

Figure 25

.

[2] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up.

t r

V

DD

400 mV

0 t = t

1

Condition: 0 < V

I

≤ 400 mV at start of power-up (t = t

1

)

Fig 25. Power-up ramp t wait

002aag001

10.2 Flash memory

Table 13.

Flash characteristics

T amb

=

−40 °C to +85 °C, unless otherwise specified.


N endu t ret endurance retention time powered t er erase time unpowered sector or multiple consecutive sectors t prog programming time

Min

[1]

10000

10

20

95

[2]

0.95

Typ

-

100000

-

100

1

-

-

Max

-

105

1.05

ms

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.

Unit cycles years years ms

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10.3 External clock

Table 14.

Dynamic characteristic: external clock

T amb

=

−40 °C to +85 °C; V

DD

over specified ranges.

[1]

Symbol Parameter f osc

T cy(clk) t

CHCX t

CLCX t

CLCH t

CHCL oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time

Conditions Min

-

1

-

40

T cy(clk)

× 0.4

T cy(clk)

× 0.4

-

-

-

-

-

-

Typ [2]

[1] Parameters are valid over operating temperature range unless otherwise specified.



5

5

-

-

Max

25

1000 ns ns ns ns

Unit

MHz ns t

CHCL t

CLCX

T cy(clk) t

CHCX t

CLCH

Fig 26. External clock timing (with an amplitude of at least V i(RMS)

= 200 mV)

002aaa907

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10.4 Internal oscillators

Table 15.

Dynamic characteristics: IRC

T amb

=

−40 °C to +85 °C; 2.7 V ≤ V

DD

≤ 3.6 V

[1] .

Symbol Parameter f osc(RC) internal RC oscillator frequency -

Conditions Min

11.88

Typ [2]

12




Max

12.12

002aae987

12.15

f

(MHz)

12.05

V

DD

= 3.6 V

3.3 V

3.0 V

2.7 V

2.4 V

2.0 V

Unit

MHz

11.95

11.85

−

40

−

15 10 35 60 temperature ( ° C)

85

Conditions: Frequency values are typical values. 12 MHz

± 1 % accuracy is guaranteed for

2.7 V

≤ V

DD

≤ 3.6 V and T amb

=

−40 °C to +85 °C. Variations between parts may cause the IRC to fall outside the 12 MHz

± 1 % accuracy specification for voltages below 2.7 V.

Fig 27. Internal RC oscillator frequency f versus temperature

Table 16.

Dynamic characteristics: Watchdog oscillator

Symbol Parameter f osc(int) internal oscillator frequency

Conditions

DIVSEL = 0x1F, FREQSEL = 0x1 in the

WDTOSCCTRL register;

DIVSEL = 0x00, FREQSEL = 0xF in the

WDTOSCCTRL register

[2][3]

[2][3]

[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

[2] The typical frequency spread over processing and temperature (T amb

=

−40 °C to +85 °C) is ±40 %.

[3] See the LPC13xx user manual.

-

-

Min

Typ [1]

7.8

1700 -

-

Max Unit kHz kHz

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10.5 I/O pins

Table 17.

Dynamic characteristics: I/O pins

[1]

T amb

=

−40 °C to +85 °C; 3.0 V ≤ V

DD

≤ 3.6 V.

Symbol Parameter Conditions t r t f rise time fall time pin configured as output pin configured as output

[1] Applies to standard port pins and RESET pin.

Min

3.0

2.5

-

-

Typ Max

5.0

5.0

Unit ns ns

10.6 I 2 C-bus

Table 18.

Dynamic characteristic: I 2 C-bus pins

[1]

T amb

= −40 °C to +85 °C.

[2]

Symbol Parameter Conditions f

SCL

SCL clock frequency

Standard-mode t f fall time

[4][5][6][7]

Fast-mode

Fast-mode Plus of both SDA and SCL signals

Standard-mode t

LOW

LOW period of the

SCL clock

Fast-mode

Fast-mode Plus

Standard-mode

Fast-mode t t t

HIGH

HD;DAT

SU;DAT

HIGH period of the

SCL clock data hold time data set-up time

[3][4][8]

[9][10]

Fast-mode Plus

Standard-mode

Fast-mode

Fast-mode Plus

Standard-mode

Fast-mode

Fast-mode Plus

Standard-mode

Fast-mode

Fast-mode Plus

-

-

0

0

Min

0

20 + 0.1

× C b

4.7

1.3

0.5

4.0

0.6

0.26

0

0

0

250

100

50

-

-

-

-

-

-

-

-

-

-

-

-

Max

100

400

1

300

300

120

Unit kHz kHz

MHz ns ns ns

μs

μs

μs

μs

μs

μs

μs

μs

μs ns ns ns

[1] See the I

2

C-bus specification UM10204 for details.


[3] t

HD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V

IH

(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

[5] C b

= total capacitance of one bus line in pF.

[6] The maximum t f

for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t f

is specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t f

.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing.

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[8] The maximum t

HD;DAT

could be 3.45

μs and 0.9 μs for Standard-mode and Fast-mode but must be less than the maximum of t

VD;DAT

or t

VD;ACK

by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (t

LOW

) of the

SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[9] t

SU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge.

[10] A Fast-mode I

2

C-bus device can be used in a Standard-mode I

2

C-bus system but the requirement t

SU;DAT

= 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line t r(max)

+ t

SU;DAT

= 1000 + 250 = 1250 ns (according to the

Standard-mode I

2

C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

SDA

70 %

30 % t f

70 %

30 % t

HD;DAT t

SU;DAT

SCL t f

70 %

30 %

70 %

30 %

70 %

30 % t

LOW t

HIGH

70 %

30 % t

VD;DAT

S 1 / f

SCL

002aaf425

Fig 28. I 2 C-bus pins clock timing

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10.7 SSP0/1 interface

Remark: The SSP1 interface is available on the LPC1313FBD48/01 only.

Table 19.

Dynamic characteristics: SSP pins in SPI mode t t t t

Symbol

SSP master

Parameter

T cy(clk)

DS

DH v(Q) h(Q)

SSP slave

Conditions clock cycle time data set-up time data hold time data output valid time in SPI mode; in SPI mode

[2]

2.4 V ≤ V

DD

≤ 3.6 V

2.0 V ≤ V

DD

< 2.4 V

[2]

[2]

in SPI mode

[2]

data output hold time full-duplex mode

[1]

when only transmitting

[1]

in SPI mode

[2]

T cy(PCLK) t

DS t

DH t v(Q) t h(Q)

PCLK cycle time data set-up time data hold time data output valid time data output hold time in SPI mode in SPI mode in SPI mode in SPI mode

[3][4]

[3][4]

[3][4]

[3][4]

-

Min

40

27.8

15

20

0

0

13.9

-

0

-

3 × T cy(PCLK)

+ 4

-

-

-

-

-

-

Max

10

-

-

-

3 × T cy(PCLK)

+ 11

2 × T cy(PCLK)

+ 5

Unit ns ns ns ns ns ns ns ns ns ns ns ns

[1] T cy(clk)

= (SSPCLKDIV × (1 + SCR) × CPSDVSR) / f main

. The clock cycle time derived from the SPI bit rate T cy(clk)

is a function of the main clock frequency f main

, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).

[2] T amb

= −40 °C to +85 °C.

[3] T cy(clk)

= 12 × T cy(PCLK)

.

[4] T amb

= 25 °C; V

DD

= 3.3 V.

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T cy(clk) t clk(H) t clk(L)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

MISO t v(Q)

DATA VALID

DATA VALID

DATA VALID t

DS t

DH

DATA VALID t h(Q)

CPHA = 1

MOSI

MISO t v(Q)

DATA VALID

DATA VALID

DATA VALID t

DS t

DH

DATA VALID t h(Q)

CPHA = 0

002aae829

Fig 29. SSP master timing in SPI mode

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SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

MISO

LPC1311/13/42/43


T cy(clk) t clk(H) t clk(L)

DATA VALID t v(Q)

DATA VALID t

DS t

DH

DATA VALID

DATA VALID t h(Q) CPHA = 1

MOSI

MISO

DATA VALID t v(Q)

DATA VALID t

DS t

DH

DATA VALID

DATA VALID t h(Q)

Fig 30. SSP slave timing in SPI mode

CPHA = 0

002aae830

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10.8 USB interface (LPC1342/43 only)

Table 20.

Dynamic characteristics: USB pins (full-speed)

C

L

= 50 pF; R pu

= 1.5 k

Ω

on D+ to V

DD

, unless otherwise specified. 3.0 V

≤

V

DD

≤

3.6 V

Symbol Parameter Conditions Min t r t f t

FRFM

V

CRS t

FEOPT t

FDEOP t

JR1 t

JR2 t

EOPR1 t

EOPR2 rise time fall time differential rise and fall time matching output signal crossover voltage

10 % to 90 %

10 % to 90 %

t r

/ t f source SE0 interval of EOP source jitter for differential transition to SE0 transition see

Figure 31

see

Figure 31

receiver jitter to next transition receiver jitter for paired transitions

EOP width at receiver

EOP width at receiver

10 % to 90 % must reject as

EOP; see

Figure 31

must accept as

EOP; see

Figure 31

-

8.5

7.7

1.3

160

−2

[1]

−18.5

−9

40

[1]

82

[1] Characterized but not implemented as production test. Guaranteed by design.

T

PERIOD crossover point extended crossover point differential data lines

-

-

-

-

-

-

-

-

-

Typ Max

13.8

13.7

109

2.0

175

+5

-

+18.5

+9 ns ns ns

V ns ns

Unit ns ns

%

ns differential data to

SE0/EOP skew n × T

PERIOD

+ t

FDEOP source EOP width: t

FEOPT receiver EOP width: t

EOPR1

, t

EOPR2

002aab561

Fig 31. Differential data-to-EOP transition skew and EOP width

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11. Application information

11.1 Suggested USB interface solutions (LPC1342/43 only)

V

DD

LPC134x

USB_CONNECT soft-connect switch

USB_VBUS

USB_DP

RS = 33 Ω

USB_DM

RS = 33 Ω

V

SS

R1

1.5 k Ω

002aae608

USB-B connector

Fig 32. LPC1342/43 USB interface on a self-powered device

V

DD

LPC134x

R1

1.5 k Ω

USB_VBUS

USB_DP RS = 33

Ω

USB_DM RS = 33 Ω

V

SS

USB-B connector

002aae609

Fig 33. LPC1342/43 USB interface on a bus-powered device

LPC1311_13_42_43


11.2 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with

C i

= 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground C g

which attenuates the input voltage by a factor C i

/(C i

+ C g

). In slave mode, a minimum of 200 mV(RMS) is needed.


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LPC1xxx

XTALIN

Ci

100 pF

Cg

002aae788

Fig 34. Slave mode operation of the on-chip oscillator

In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF

(

Figure 34

), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in

Figure 35

and in

Table 21 and Table 22 . Since the feedback resistance is integrated on chip, only a crystal

and the capacitances C

X1

and C

X2

need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, C

L

and

R

S

). Capacitance C

P

in

Figure 35

represents the parallel package capacitance and should not be larger than 7 pF. Parameters F

OSC

, C

L

, R

S

and C

P

are supplied by the crystal manufacturer.

LPC1xxx

XTALIN XTALOUT

XTAL

=

L

CL CP

RS

CX1 CX2

002aaf424

Fig 35. Oscillator modes and models: oscillation mode of operation and external crystal model used for C

X1

/C

X2

evaluation

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Table 21.

Recommended values for C

X1

/C

X2

in oscillation mode (crystal and external components parameters) low frequency mode

Fundamental oscillation frequency F

OSC

1 MHz - 5 MHz

5 MHz - 10 MHz

10 MHz - 15 MHz

15 MHz - 20 MHz

Crystal load capacitance C

10 pF

20 pF

30 pF

10 pF

20 pF

30 pF

10 pF

20 pF

10 pF

L

Maximum crystal series resistance R

S

< 300 Ω

< 300 Ω

< 300

Ω

< 300 Ω

< 200

Ω

< 100 Ω

< 160

Ω

< 60 Ω

< 80

Ω

External load capacitors C

X1

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

, C

X2

Table 22.

Recommended values for C

X1

/C

X2

in oscillation mode (crystal and external components parameters) high frequency mode

Fundamental oscillation frequency F

OSC

15 MHz - 20 MHz

20 MHz - 25 MHz

Crystal load capacitance C

10 pF

20 pF

10 pF

20 pF

L

Maximum crystal series resistance R

S

< 180 Ω

< 100

Ω

< 160 Ω

< 80

Ω

External load capacitors C

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

39 pF, 39 pF

X1

, C

X2

11.3 XTAL Printed-Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C x1

, C x2

, and C x3

in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C x1

and C x2

should be chosen smaller accordingly to the increase in parasitics of the PCB layout.

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11.4 Standard I/O pad configuration

Figure 36

shows the possible pin modes for standard I/O pins with analog input function:

• Digital output driver

• Digital input: Pull-up enabled/disabled

• Digital input: Pull-down enabled/disabled

• Digital input: Repeater mode enabled/disabled

• Analog input

V

DD output enable ESD pin configured as digital output driver output PIN

ESD

V

SS pin configured as digital input repeater mode enable pull-up enable pull-down enable

V

DD weak pull-up weak pull-down data input pin configured as analog input analog input

Fig 36. Standard I/O pad configuration select analog input

002aaf304

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11.5 Reset pad configuration

V

DD

V

DD

Rpu

V

DD

ESD reset

20 ns RC

GLITCH FILTER

PIN

ESD

V

SS

002aaf274

Fig 37. Reset pad configuration

11.6 ADC usage notes

The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in

Table 8

:

• The ADC input trace must be short and as close as possible to the LPC1311/13/42/43 chip.

• The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines.

• Because the ADC and the digital core share the same power supply, the power supply line must be adequately filtered.

• To improve the ADC performance in a very noisy environment, put the device in Sleep mode during the ADC conversion.

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11.7 ElectroMagnetic Compatibility (EMC)

Radiated emission measurements according to the IEC61967-2 standard using the

TEM-cell method are shown for the LPC1343FBD48 in

Table 23

.

Table 23.

ElectroMagnetic Compatibility (EMC) for part LPC1343FBD48 (TEM-cell method)

V

DD

= 3.3 V; T amb

= 25

°

C.

Parameter Frequency band System clock = Unit

24 MHz 48 MHz 72 MHz 12 MHz

Input clock: IRC (12 MHz) maximum peak level

150 kHz - 30 MHz

−6

30 MHz - 150 MHz

150 MHz - 1 GHz

−1

+3

IEC level

[1]

O

Input clock: crystal oscillator (12 MHz) maximum peak level

150 kHz - 30 MHz -5

IEC level

[1]

-

30 MHz - 150 MHz

150 MHz - 1 GHz

0

3

O

−5

+3

+7

N

−5

+4

+8

N

−7

+9

+15

M

−7

+9

+15

M

−7

+13

+19

L

−7

+13

+20

L dB

μV

dB

μV dB μV dB

μV

dB

μV dB μV

[1] IEC levels refer to Appendix D in the IEC61967-2 Specification.

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12. Package outline

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y

X

37

36 25

24 Z E

A e

48 pin 1 index

13

1 e b p

D

H

D w

M

12

ZD

B w M b p v M A v M B

E H

E

A

A

2

A

1 detail X

L

L p

θ

0 2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

UNIT

A max.

A

1

A

2

A

3 b p c mm 1.6

0.20

0.05

1.45

1.35

0.25

0.27

0.17

0.18

0.12

D

(1)

7.1

6.9

E

(1)

7.1

6.9

e

0.5

H

D

H

E

9.15

8.85

9.15

8.85

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

L

1

L p

0.75

0.45

v

0.2

w y

0.12

0.1

Z

D

(1)

Z

E

(1)

0.95

0.55

0.95

0.55

θ

7 o

0 o

OUTLINE

VERSION

SOT313-2

IEC

136E05

REFERENCES

JEDEC JEITA

MS-026

EUROPEAN

PROJECTION

ISSUE DATE

00-01-19

03-02-25

Fig 38. Package outline SOT313-2 (LQFP48)

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HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;

33 terminals; body 7 x 7 x 0.85 mm

D B A terminal 1 index area

E A

A

1

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller c detail X

L

8

9 e

E h e

1 b

16 v w

C

C

A B

17 e e

2 y

1

C

C y terminal 1 index area

1

32

33

25

24

X

D h

0 2.5

scale

Dimensions

Unit A

(1)

A

1 b c D

(1)

D h

E

(1)

E h e e

1 e

2 mm max nom min

1.00

0.85

0.80

0.05

0.02

0.00

0.35

0.28

0.23

0.2

7.1

7.0

6.9

4.85

4.70

4.55

7.1

7.0

6.9

4.85

4.70

4.55

0.65

4.55

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

4.55

Outline version

IEC JEDEC

References

JEITA

L

0.75

0.60

0.45

5 mm v

0.1

w y

0.05

0.08

y

1

0.1

European projection

- - -

Fig 39. Package outline (HVQFN33)

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Issue date

09-03-17

09-03-23


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13. Soldering

Footprint information for reflow soldering of LQFP48 package

P2 P1

Hx

Gx

(0.125)

LPC1311/13/42/43


SOT313-2

Hy Gy By Ay

C

D2 (8 × ) D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout solder land occupied area

DIMENSIONS in mm

P1 P2 Ax Ay Bx By

0.500

0.560

10.350

10.350

7.350

7.350

C D1

1.500

0.280

D2 Gx Gy Hx Hy

0.500

7.500

7.500

10.650 10.650

Fig 40. Reflow soldering of the LQFP48 package

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Footprint information for reflow soldering of HVQFN33 package

OID = 8.20 OA

PID = 7.25 PA+OA

OwDtot = 5.10 OA evia = 4.25

0.20 SR chamfer (4×) e = 0.65

W = 0.30 CU

SPD = 1.00 SP

GapD = 0.70 SP evia = 2.40

SDhtot = 2.70 SP

4.55 SR

DHS = 4.85 CU

LbD = 5.80 CU

LaD = 7.95 CU

0.45 DM

B-side

Solder resist covered via

0.30 PH

0.60 SR cover

0.60 CU

(A-side fully covered) number of vias: 20 solder land solder paste deposit occupied area solder land plus solder paste solder resist

Dimensions in mm

Remark:

Stencil thickness: 0.125 mm

Fig 41. Reflow soldering of the HVQFN33 package

001aao134

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14. Abbreviations

MSC

PHY

PLL

SE0

SPI

SSI

SSP

SoF

TCM

TTL

UART

USB

BOD

EOP

ETM

FIFO

GPIO

HID

I/O

LSB

Table 24.

Abbreviations

Acronym

A/D

Description

Analog-to-Digital

ADC

AHB

AMBA

APB

Analog-to-Digital Converter

Advanced High-performance Bus

Advanced Microcontroller Bus Architecture

Advanced Peripheral Bus

BrownOut Detection

End Of Packet

Embedded Trace Macrocell

First-In, First-Out

General Purpose Input/Output

Human Interface Device

Input/Output

Least Significant Bit

Mass Storage Class

Physical Layer

Phase-Locked Loop

Single Ended Zero

Serial Peripheral Interface

Serial Synchronous Interface

Synchronous Serial Port

Start-of-Frame

Tightly-Coupled Memory

Transistor-Transistor Logic

Universal Asynchronous Receiver/Transmitter

Universal Serial Bus

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15. Revision history

Table 25.

Revision history

Document ID

LPC1311_13_42_43 v.5

Modifications:

LPC1311_13_42_43 v.4

LPC1311_13_42_43 v.3

LPC1311_13_42_43 v.2

LPC1311_13_42_43 v.1

Release date Data sheet status Change notice Supersedes

20120606 Product data sheet LPC1311_13_42_43 v.4

•

Parameters V

OL

, V

OH

, I

OL

, I

OH

updated for voltage range 2.0 V

≤ V

DD

< 2.5 V in

Table 7 .

•

Condition “The peak current is limited to 25 times the corresponding maximum current.” removed from parameters I

DD

and I

SS

in Table 6 .

20110620 Product data sheet LPC1311_13_42_43 v.3

20100810

20100506

20091211

Product data sheet

Product data sheet

Product data sheet

-

-

-

LPC1311_13_42_43 v.2

LPC1311_13_42_43 v.1

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16. Legal information

Document status

[1][2]

Objective [short] data sheet

Product status

[3]

Development

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

Definition

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

.

16.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the

Product data sheet.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

LPC1311_13_42_43


Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.


Rev. 5 — 6 June 2012


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LPC1311/13/42/43


Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

I 2 C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

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18. Contents

1

2

3

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4

4.1

5

Ordering information . . . . . . . . . . . . . . . . . . . . . 3

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6

6.1

6.2

Pinning information . . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10

7 Functional description . . . . . . . . . . . . . . . . . . 17

7.1

7.2

7.3

7.4

7.5

7.6

7.6.1

7.6.2

Architectural overview . . . . . . . . . . . . . . . . . . 17

ARM Cortex-M3 processor . . . . . . . . . . . . . . . 17

On-chip flash program memory . . . . . . . . . . . 17

On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 17

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 17

Nested Vectored Interrupt Controller (NVIC) . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 19

7.7

7.8

7.8.1

7.9

IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 19

Fast general purpose parallel I/O . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

USB interface (LPC1342/43 only) . . . . . . . . . 20

7.9.1 Full-speed USB device controller . . . . . . . . . . 20

7.9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.10 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.11 SSP serial I/O controller . . . . . . . . . . . . . . . . . 21

7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.12 I 2

C-bus serial I/O controller . . . . . . . . . . . . . . 21

7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.13 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.14 General purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.15 System tick timer . . . . . . . . . . . . . . . . . . . . . . 23

7.16 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 23

7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.17 Windowed WatchDog Timer (WWDT) . . . . . . 24

7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.18 Clocking and power control . . . . . . . . . . . . . . 24

7.18.1 Integrated oscillators . . . . . . . . . . . . . . . . . . . 24

7.18.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 25

7.18.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 26

7.18.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 26

7.18.2 System PLL and USB PLL . . . . . . . . . . . . . . . 26

7.18.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.18.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 26

7.18.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.18.5.1 Power profiles (LPC1300L series,

LPC1311/01 and LPC1313/01 only) . . . . . . . 27

7.18.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.18.5.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 27

7.18.5.4 Deep power-down mode . . . . . . . . . . . . . . . . 28

7.19 System control . . . . . . . . . . . . . . . . . . . . . . . . 28

7.19.1 Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.19.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.19.3 Brownout detection . . . . . . . . . . . . . . . . . . . . 28

7.19.4 Code security (Code Read Protection - CRP) 28

7.19.5 Boot loader. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.19.6 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.19.7 AHB-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.19.9 Memory mapping control . . . . . . . . . . . . . . . . 29

7.20 Emulation and debugging . . . . . . . . . . . . . . . 30

8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31

9

9.1

9.2

9.3

9.4

9.5

9.6

10 Dynamic characteristics. . . . . . . . . . . . . . . . . 50

10.1

10.2

10.3

10.4

Power-up ramp conditions . . . . . . . . . . . . . . . 50

Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 50

External clock. . . . . . . . . . . . . . . . . . . . . . . . . 51

Internal oscillators . . . . . . . . . . . . . . . . . . . . . 52

10.5 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.6 I 2

C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.7

10.8

SSP0/1 interface . . . . . . . . . . . . . . . . . . . . . . 55

USB interface (LPC1342/43 only) . . . . . . . . . 58

11

11.1

Static characteristics . . . . . . . . . . . . . . . . . . . 32

BOD static characteristics for LPC1300 series 38

BOD static characteristics for LPC1300L series

(LPC1311/01 and LPC1313/01) . . . . . . . . . . . 39

Power consumption for LPC1300 series . . . . 39

Power consumption for LPC1300L series

(LPC1311/01 and LPC1313/01) . . . . . . . . . . . 42

Peripheral power consumption . . . . . . . . . . . 45

Electrical pin characteristics. . . . . . . . . . . . . . 46

11.2

11.3

11.4

11.5

11.6

11.7

Application information . . . . . . . . . . . . . . . . . 59

Suggested USB interface solutions

(LPC1342/43 only) . . . . . . . . . . . . . . . . . . . . . 59

XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

XTAL Printed-Circuit Board (PCB) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Standard I/O pad configuration . . . . . . . . . . . 62

Reset pad configuration . . . . . . . . . . . . . . . . . 63

ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 63

ElectroMagnetic Compatibility (EMC) . . . . . . 64

continued >>

LPC1311_13_42_43



Rev. 5 — 6 June 2012


73 of 74


12

13

14

15

16

16.1

16.2

16.3

16.4

17

18

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 65

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Revision history . . . . . . . . . . . . . . . . . . . . . . . . 70

Legal information. . . . . . . . . . . . . . . . . . . . . . . 71

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 71

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Contact information. . . . . . . . . . . . . . . . . . . . . 72

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

LPC1311/13/42/43


Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2012.

All rights reserved.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 6 June 2012

Document identifier: LPC1311_13_42_43

NXP LPC1343FHN33 32kB Flash, 8kB SRAM, USB Device Data Sheet

32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and

8 kB SRAM; USB device

2. Features and benefits

3. Applications

10. Dynamic characteristics

11. Application information

12. Package outline

13. Soldering

14. Abbreviations

15. Revision history

16. Legal information

17. Contact information

18. Contents

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