AN928: EFR32 Layout Design Guide

AN928: EFR32 Layout Design Guide
AN928: EFR32 Layout Design Guide
The purpose of this application note is to help users design PCBs
for the EFR32 Wireless Gecko Portfolio using design practices
that allow for good RF performance. The matching principles are
described in the application note, AN930: EFR32 2.4 GHz Matching Guide. The MCU related subjects are detailed in the following
application notes: AN0918: EFM32 to EFM32 Gemstones Compatibility and Migration Guide, AN0948: Power Configurations
and DC-DC, and AN0955: CRYPTO. The RF performance
strongly depends on the PCB layout as well as the design of the
matching networks. For optimal performance, Silicon Labs recommends using the PCB layout design guidelines described in
the following sections.
silabs.com | Smart. Connected. Energy-friendly.
KEY POINTS
• A reference schematic and PCB layout is
provided.
• All main design principles are listed and
detailed.
• A summary checklist of all design
principles is provided.
Rev. 0.2
AN928: EFR32 Layout Design Guide
Design Recommendations When Using EFR32 Wireless MCUs
1. Design Recommendations When Using EFR32 Wireless MCUs
• Extensive testing has been completed using reference designs provided by Silicon Labs. It is recommended that designers use the
reference designs “as-is” since they minimize detuning effects caused by parasitics or generated by poor component placement and
PCB routing.
• The compact RF part of the designs (excluding the 50 Ω single-ended antenna) is highlighted by a red frame, and it is strongly recommended to use the same framed RF layout in order to avoid any possibility of detuning effects. The figure below shows the
framed compact RF part of the designs.
Figure 1.1. Top Layer of the Radio Board (Left Side) and Assembly Drawing of the RF Part (Right Side)
• When layouts cannot be followed as shown by the reference designs (due to PCB size and shape limitations), the layout design
rules described in the following sections are recommended.
1.1 Matching Network Types for the 2.4 GHz EFR32 Wireless MCUs
The 2.4 GHz EFR32 wireless MCU can provide maximum +20 dBm power. All EFR32 reference designs for 2.4 GHz use a series-L
parallel-C ladder structured matching network. For low power applications (<13 dBm) a 2-element L-C network is sufficient, while high
power solutions (>13 dBm) require a 4-element match.
It is not surprising that the increased TX output power of the EFR32 devices is accompanied by a corresponding increase in the absolute level of harmonic signals. Since most regulatory standards (e.g. FCC, ETSI, ARIB etc.) require the harmonic signals to be attenuated below some absolute power level (in watts or dBm), the amount of low-pass filtering required is generally greater on an RF radio
board using an EFR32 that was designed for higher output power.
All 2.4 GHz radio boards comprise a 50 Ω IFA (Inverted-F Antenna) connected to the 50 Ω output of the matching network to be able to
measure radiated performance. Optional conducted measurements are possible on these radio boards through an U.FL connector.
silabs.com | Smart. Connected. Energy-friendly.
Rev. 0.2 | 1
AN928: EFR32 Layout Design Guide
Guidelines for Layout Design When Using EFR32 Wireless MCUs
2. Guidelines for Layout Design When Using EFR32 Wireless MCUs
Some general guidelines for designing RF-related layouts for good RF performance are:
• Use as much continuous and unified ground plane metallization as possible, especially on the top and bottom layers.
• Avoid the separation of the ground plane metallization, especially between the ground of the matching network and the RFIC GND
pins / exposed pad.
• Use as many grounding vias (especially near the GND pins) as possible to minimize series parasitic inductance between the ground
pours of different layers and between the GND pins.
• Use a series of GND stitching vias along the PCB edges and internal GND metal pouring edges. The maximum distance between
the vias should be less than lambda/10 of the 10th harmonic (the typical distance between vias for 2.4 GHz is 40-50 mil). This distance is required to reduce the PCB radiation at higher harmonics caused by the fringing field of these edges.
• For designs with more than 2-layers, it is recommended to put as many traces (even the digital traces) as possible in an inner layer
and ensure large, continuous GND pours on the top and bottom layers.
• Avoid using long and/or thin transmission lines to connect the components. Otherwise, due to its distributed parasitic inductance,
some detuning effects can occur. Also shorten the interconnection lines as much as possible to reduce the parallel parasitic caps to
the ground. However, couplings between neighbor discretes may increase in this way.
• To reduce the coupling between the nearby discrete inductors, avoid placing them in the same orientation.
• Use tapered line between transmission lines with different width (i.e., different impedance) to reduce internal reflections.
• Avoid using loops and long wires to obviate their resonances. They also work well as unwanted radiators, especially at the harmonics.
• Always ensure good VDD filtering by using some bypass capacitors (especially at the range of the operating frequency). The series
self-resonance of the capacitor should be close to the filtered frequency. The bypass capacitor which filters the highest frequency
should be placed closest to the VDD pins of the EFR32. In addition to the fundamental frequency, the crystal/clock frequency and its
harmonics (up to the 3rd) should be filtered to avoid up-converted spurs.
• Connect the crystal case to the ground using many vias to avoid radiation of the ungrounded parts. Do not leave any metal unconnected and floating that may be an unwanted radiator. Avoid leading supply traces close or beneath the crystal or parallel with a
crystal signal or clock trace.
• Avoid routing GPIO lines close or beneath the RF lines, antenna or crystal, or in parallel with a crystal signal. Use as low a slew rate
as possible on GPIO lines to decrease crosstalk to RF or crystal signals.
• Use as short VDD traces as possible. The VDD trace can be a hidden, unwanted radiator so it is more important to simplify the VDD
routing as much as possible and use large, continuous GND pours with many stitching vias. To achieve the simplified VDD routing,
try to avoid star topology of VDD traces (i.e., avoid connecting all VDD traces in one common point).
• Using silkscreen near the antenna could slightly affect the dielectric environment of the antenna. Although this effect is usually negligible, if possible, try to avoid using silkscreen on the antenna or on the antenna copper pour keep out areas.
silabs.com | Smart. Connected. Energy-friendly.
Rev. 0.2 | 2
AN928: EFR32 Layout Design Guide
Guidelines for Layout Design When Using EFR32 Wireless MCUs
2.1 EFR32 Layout for the 2.4 GHz Frequency Band Using a 4-element Matching Network
Examples shown in this section are based on a general 2.4 GHz EFR32 Radio Board. The main layout design concepts are shown with
this layout to demonstrate the basic principles. Although these rules will be shown through a design that uses a 4-element matching,
similar design practices should be applied with a 2-element matching network as well.
The antenna and radio interface schematic for the 2.4 GHz EFR32 wireless MCU is shown in the figure below.
Figure 2.1. Schematic of the RF Section for the 2.4 GHz EFR32 Wireless MCU
Note: Matching network component values should be chosen based on power range.
In the figure above, there is an additional component (R1) beside the 4-element matching. Its purpose (besides connecting the antenna
to the matching output) is to improve the suppression of the radiated 2nd harmonic of the actual board. Further details on the necessity
of this component can be found in the application note, “AN930: EFR32 2.4 GHz Matching Guide”.
The layout structure for the RF part of the reference radio board is shown the figure below:
Figure 2.2. Layout of the RF Section for the 2.4 GHz EFR32 Wireless MCU
silabs.com | Smart. Connected. Energy-friendly.
Rev. 0.2 | 3
AN928: EFR32 Layout Design Guide
Guidelines for Layout Design When Using EFR32 Wireless MCUs
2.1.1 Layout Design Guidelines
• The L1 inductor should be placed as close as possible to the 2G4RF_IOP pin (pin 17 on the 7x7 mm sized package) of the EFR32
IC to reduce the series parasitic inductance and avoid any detuning effects.
• The neighboring matching network components should be placed as close to each other as possible to minimize any PCB parasitic
capacitance to the ground and the series parasitic inductances between the components.
• The grounding effect in the thermal straps used with capacitors should be improved. In addition, the trace near the GND pin of these
capacitors should be thickened. This will minimize series parasitic inductance between the ground pour and the GND pins. Additional vias placed close to the GND pin of capacitors (thus connecting it to the bottom or inner layer GND plane) will further help reduce
these effects.
• The smaller VDD bypass capacitors (the ones with ~pF values) should be kept as close to the VDD pins (RFVDD, PAVDD) as possible.
• The exposed pad footprint for the paddle of the EFR32 should use as many vias as possible to ensure good grounding and heat sink
capability. In the reference designs there are 25 vias for the 7x7 mm sized package ICs, each with 10 mil diameter. The paddle
ground should also be connected to the top layer GND metal, if possible, to further improve RF grounding; this may be accomplished with diagonal trace connections through the corners of the EFR32 footprint.
• The crystal should be placed as close to the RFIC as possible to ensure that wire parasitic capacitances are kept as low as possible;
this will reduce any frequency offsets.
• Use at least 0.5 mm separation between traces/pads to the adjacent GND pour in the areas of the matching networks. This technique will minimize the parasitic capacitance and reduce the detuning effects.
The figure below demonstrates the grounding of the RFIC, the crystal, and VDD filter capacitor positions on the reference radio board.
Figure 2.3. EFR32 IC GND Vias and GND Metallization (Top and First Inner Layer)
• To achieve good RF ground on the layout, it is recommended to add large, continuous GND metallization on the top layer in the area
of the RF section (at a minimum). Better performance may be obtained if this is applied to the entire PCB. To provide a good RF
ground, the RF voltage potentials should be equal along the entire GND area as this helps maintain good VDD filtering. Gaps should
ideally be filled with GND metal and the resulting sections on the top and bottom layers should be connected with as many vias as
possible. The reason for not using vias on the entire GND section is due to the restrictions of the actual radio board design. These
restrictions include traces routed on other layers or components on the bottom side, which are not shown in Figure 2.3 EFR32 IC
GND Vias and GND Metallization (Top and First Inner Layer) on page 4.
• The area under the RF chip and the matching network (in 4-layer PCBs, this is the first inner layer beneath the top layer) should be
filled with continuous ground metal as it will show good ground reference for the matching network and will ensure a good, low impedance return path to the RF chip’s ground as well. Board routing and wiring should not be placed in this region to prevent coupling
effects with the matching network. It is also recommended that the GND return path between the GND vias of the TX/RX matching
network and the GND vias of the RFIC paddle should not be blocked in any way; the return currents should see a clear, unhindered
pathway through the GND plane to the back of the RFIC.
• Use as many parallel grounding vias at the GND metal edges as possible, especially at the edge of the PCB and along the VDD
trace, to reduce their harmonic radiation caused by the fringing field.
• Use an isolating ground metal between the crystal and VDD traces to avoid any detuning effects on the crystal caused by the nearby
power supply and to avoid the leakage of the crystal/clk signal and its harmonics to the supply lines.
silabs.com | Smart. Connected. Energy-friendly.
Rev. 0.2 | 4
AN928: EFR32 Layout Design Guide
Guidelines for Layout Design When Using EFR32 Wireless MCUs
• If necessary, a shielding cap can be used to shield the harmonic radiations of the PCB; in that case, the shielding cap should cover
all of the RF-related components (excluding the antenna).
• Use 50 Ω grounded coplanar lines where possible for connecting the antenna or the U.FL connector to the matching to reduce sensitivity to PCB thickness variation. This will also reduce radiation and coupling effects. The interconnections between the elements
are not considered as transmission lines since their lengths are much lower than the wavelength and thus their impedance is not
critical. As a result, their recommended width is the smallest possible (i.e., equal to the width of the pad of the applied components).
In this way, the parasitic capacitances to the ground can be minimized. An example for the trace dimensions are shown in Table
2.1 Parmeters for 50 Ω Grounded Coplanar Lines on page 5.
• Use many vias near the coplanar lines to reduce as much radiation as possible.
The figure below demonstrates the 50 Ω grounded coplanar lines from the matching network to the antenna and to the U.FL connector.
Figure 2.4. 50 Ω Grounded Coplanar Line on 0.325 mm Thick Substrate
Table 2.1. Parmeters for 50 Ω Grounded Coplanar Lines
Lines
Parameters
f
2.4 GHz
T
0.018-0.035 mm
εr
4.3
H
0.325 mm
G
0.25 mm
W
0.45 mm
Note: Characteristic impedance is not “super sensitive” to the gap value. It should be between 0.25 and 0.4mm to have 47…53 Ω impedance.
Figure 2.5. Grounded Coplanar Line Parameters
silabs.com | Smart. Connected. Energy-friendly.
Rev. 0.2 | 5
AN928: EFR32 Layout Design Guide
Main Layout Design Principles Checklist
3. Main Layout Design Principles Checklist
1.
Is the first matching network component (L1) placed as
close to the corresponding TX pin as possible?
2.
Are the neighboring matching network components as
close to each other as possible?
3.
Are there multiple thermal straps used with the capacitors?
4.
Is there at least 0.5 mm separation in the matching between the traces/pads and the GND metal?
5.
Are the smallest value VDD filter capacitors kept closer
to the VDD pins (RFVDD, PAVDD) of the EFR32?
6.
Does the exposed pad footprint use multiple vias?
7.
Is the crystal as close to the RF IC as possible?
8.
Does ground metal exist between the crystal and the
VDD feed?
9.
Was large, continuous GND metallization added to at
least the RF sections?
10. Are the GND metal edges closed by "stitching vias"
where possible, with a via distance less than
lambda/10 of the highest (usually 10th) critical harmonic frequency?
11. Was the area on the first inner layer beneath the RF
chip and the matching network filled with continuous
GND metal, and was wiring and routing avoided in this
region?
silabs.com | Smart. Connected. Energy-friendly.
Rev. 0.2 | 6
AN928: EFR32 Layout Design Guide
Main Layout Design Principles Checklist
12. Were 50 Ω grounded coplanar lines used for connecting the matching network and the antenna?
silabs.com | Smart. Connected. Energy-friendly.
Rev. 0.2 | 7
Simplicity Studio
One-click access to MCU and
wireless tools, documentation,
software, source code libraries &
more. Available for Windows,
Mac and Linux!
IoT Portfolio
www.silabs.com/IoT
SW/HW
www.silabs.com/simplicity
Quality
www.silabs.com/quality
Support and Community
community.silabs.com
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using
or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and
"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to
make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the
included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses
granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent
of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
personal injury or death. Silicon Laboratories products are not designed or authorized for military applications. Silicon Laboratories products shall under no circumstances be used in
weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®,
EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®,
ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand
names mentioned herein are trademarks of their respective holders.
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
http://www.silabs.com
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising