TH7841A

TH7841A
Features
• Pixel Size: 11 µm x 13 µm (13 µm Pitch)
• High Data Output Rate: 20 MHz
• High Responsivity and Resolution Over a Wide Spectral Range: from Blue (400 nm) up
to Near Infrared (1,100 nm)
• Low Dark Signal and Improved Uniformity
• Low Temporal Noise and High Dynamic Range: Over 6000/1
• Ease and Flexibility of Operation:
– Only Two External Basic Drive Clocks
– Choice of Internal or External Sampling and Reset
• 28-lead DIL Package
• Available with Standard Window or Antireflective Window in the Bandwidth 450 to
750 nm
Pin Identification
Pin Number
Symbol
2
VOSA
3
ΦECHA
4
SΦECHA
5
ΦRA
A External Reset Clock Input Channel
9
VDD
Output Amplifier Drain And Internal Logic Supply
10
TP3
Test Point 3
11
TP2
Test Point 2
12
VT
13
TP1
Test Point 1
14, 15, 28
VSS
Substrate Bias (Ground)
16
VINH
Internal Sampling Clock Inhibiting Input (Dc Bias)
18
ΦP
Transfer Clock
19
ΦT
Register Transport Clock
20
VGS
Output Gate DC Bias
21
ΦRB
B External Reset Clock Output Channel
24
SΦECHB
25
ΦECHB
B Sample-and-hold Gate Input Channel
26
VOSB
Video Output Signal B (Even Channel)
27
VDR
Reset DC Bias
1, 6, 7, 8, 17, 22, 23
DNC
Do not Connect
DNC
VOSA
ΦECHA
SΦECHA
ΦRA
DNC
DNC
DNC
VDD
TP3
TP2
VT
TP1
VSS
Designation
Linear CCD
Image Sensor
(2048 Pixels)
Video Output Signal A (Odd Channel)
A Sample-and-hold Gate Input Channel
TH7841A
A Internal Sampling Clock Output Channel
Register and Photosensitive Zone DC Bias
B Internal Sampling Clock Output Channel
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
VDR
VOSB
ΦECHB
SΦECHB
DNC
DNC
ΦRB
VGS
ΦT
ΦP
DNC
VINH
VSS
Rev. 1998A–IMAGE–05/02
1
T
Absolute Maximum Ratings*
Storage Temperature ..................................... -55°C to +150°C
Operating Temperature........................................0°C to +70°C
Thermal Cycling..........................................................15°C/mn
*NOTICE:
Stresses above those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent
device failure. Functionality at or above these
limits is not implied. Exposure to absolute maximum ratings for extended periods may affect
device reliability.
Maximum Voltages:
• Pins: 3, 5, 9, 10, 11, 13,
16, 19, 20, 21, 25, 27........................................-0.3V to +18V
• Pins: 12. 18 ......................................................-0.3V to +16V
• Pins: 14, 15, 28 ................................................................. 0V
Operating Range
Operating range defines the temperature limits between which the functionality is guaranteed: 0°C to 70°C.
Operating
Precautions
Shorting the video output to VSS to VDD, even temporarily, can permanently damage the
output amplifier.
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TH7841A
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TH7841A
Operating Conditions (T = 25°C)
Table 1. DC Characteristics
Values
Parameter
Symbol
Min
Typ
Max
Unit
Output Amplifier Drain Supply
VDD
14
15
16
V
Reset DC Bias
VDR
12
13
14.5
V
Output Gate DC Bias
VGS
5.5
6
6.5
V
Photosensitive Zone and
Register DC Bias
VT
6
6.5
7
V
(2)
Substrate Bias
VSS
0.0
0.0
Test Point 1
TP1
VDD
V
(3)
TP2, TP3
VSS
V
(3)
Test Points 2 and 3
Notes:
Note
(1)
1. It is recommended to maintain VDR at VDD - 2V.
2. VT nominal =
( VΦ T )high + ( VΦ T )low
------------------------------------------------------------ ± 5%
2
3. No use for operation – For testing purpose only.
Basic Internal
Configuration
SΦECHA and ΦRA
SΦECHB and ΦRB
internal to TH7841A
Table 2. Selection of Nominal Mode
Option
Implementation
Internal Sampling
VINH (16) Connected to VSS
SΦECHA (4) and ΦECHA (3) Strapped
SΦECHB (24) and ΦECHB (25) Strapped
Internal Reset
ΦRA (5) and ΦRB (21) Connected to VDD
Note:
Note
(1)
1. Make the straps as short as possible to avoid any parasitic coupling to these connections. The load capacitance introduced by the strap should not exceed 5 pF.
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Figure 1. Timing Diagram — Clocks and Video Output Timing Diagram in Internal Sampling Mode
Table 3. Drive Clock Characteristics (see Figure 1)
Values
Parameter
Transfer Clock
Register Transport Clock
Register Transport Clock
Capacitance
Symbol
ΦPΦT
CΦT
Logic
Min
Typ
Max
Unit
Note
High
12
13
14
V
(1)
Low
0.0
0.4
0.6
800
1200
pF
Transfer Clock Capacitance
CΦP
200
300
pF
Note:
1. Transients under 0.0V in the clock pulses will lead to charge injection, causing a localized increase in the dark signal if such
spurious negative transients are present, they can be suppressed by inserting a serial resistor of appropriate value (typically
20 to 100Ω) in the corresponding driver output.
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TH7841A
Table 4. Static and Dynamic Electrical Characteristics
Values
Parameter
DC Output Level
Output Impedance
Symbol
Min
Typ
Max
Unit
VREF
8
10
12
V
ZS
Register Single-stage Transfer Efficiency
Max. Data Output Frequency
Input Current on Pins: 3, 5, 10,11,12, 13,
18, 19, 20, 21, 25
500
Ω
Note
CTE
99.992
99.998
%
VOS = 1V (1)
FS max.
12
20
MHz
(2)
µA
Ve = 15V
All other pins: 0V
Ie
2
Peak Current Sink on ΦT Clock
(IΦT )P
500
mA
trise = 15 ns
Peak Current Sink on ΦP Clock
(IΦP)P
125
mA
trise = 15 ns
Output Amplifier Drain Supply Current
IDD
17
mA
VINH = 0V
VDD = 15V
Static Power Dissipation
PD
255
mW
VINH = 0V
VDD = 15V
Notes:
300
1. VOS = average video output voltage. Measurement excludes first and last pixels.
2. FS = 2FΦT . The minimum clock frequency is limited by the increase in dark signal.
Electro-optical
Performance
General measurement conditions: TC = 25°C; Ti = 1 ms; FΦT = 2.5 MHz.
Light source: tungsten filament lamp (2854 K) + BG 38 filter (2 mm thick) + F/3.5 aperture. The filter limits the spectrum to 700 nm; in these conditions, 1 µJ/cm2 corresponds
to 3.5 lux.s.
Typical operating conditions; internal clock mode (see Table 2).
First and last pixels, as well as reference elements, are excluded from the specification.
Measurements taken on each output in succession.
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Table 5. Electro-optical Performance
Values
Parameter
Symbol
Min
Typ
Max
Unit
Note
Saturation Output Voltage
VSAT
1.3
1.8
2.2
V
(1)(2)
Saturation Exposure
ESAT
Responsivity
R
2.5
0.33
µJ/cm2
2.9
V/µJ/cm2
Responsivity Unbalance
∆R/R
2
8
%
(3)
Photo-response No-uniformity Peak-topeak
PRNU
±5
±10
% VOS
VOS = 50 mV to 1V
CTF
70
%
VOS = 0.75V
160
µVrms
(4)
(1)
Contrast Transfer Function at FN
(38 I p/mm)
Temporal Noise in Darkness
Dynamic Range (Relative to rms Noise)
DR
Average Dark Signal
VDS
3000
6000
0.08
0.5
mV
Dark Signal Non-uniformity
DSNU
0.15
Notes: 1. Value measured with respect to zero reference level (see Figure 1).
2. Conversion factor is typically 1.1 µV/e-.
3. ∆R/R is defined as
200
RA – RB--------------------------------RA + RB
0.5
mV
where RA is responsivity of video output A
RB is responsivity of video output B
4. Measured in Correlated Double Sampling (C.D.S.) mode.
Figure 2. Typical Spectral Response
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TH7841A
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TH7841A
Figure 3. CTF Typical Curves (2854 K Source)
Electro-optical
Performance Without
Infrared Cut-off
Filtering
The TH7841A special semiconductor process exploits the silicon’s high near infrared
sensitivity while maintaining good imaging performance in terms of response uniformity
and resolution. Typical changes in performance with and without IR filtering are summarized below.
With IR Cut-off Filter
No IR Cut-off Filter
Average Video Signal Due To a Given Scene Illumination
VOS
VOS x 4
PRNU (Single Defects Excluded)
±5%
±5%
CTF at Nyquist Frequency
70%
50%
Complementary
Operating Modes
The TH7841A may be used in several configurations in regards to video output sampling and charge sensing reset.
1. Sampling options
Inhibition of internal sampling pulses allows two possibilities:
a. no sampling: video output delivered in unsampled form,
b. sampling by external clocks: external sampling pulses directly applied to ΦECHA,
ΦECHB inputs.
If internal sampling clocks SΦ ECHA and SΦECHB are not used, it is recommended to
unpower the corresponding clock drivers, as this will greatly reduce on-chip power
consumption.
2. External reset position
The position and period of the charge reset clocks may be optimized by using external
clocks on ΦRA and ΦRB inputs. This is especially interesting to optimize the video outputs
for Correlated Double Sampling (in order to reduce noise and improve S/N Ratio).
Control signals to be applied in the different configurations are shown in Table 6.
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Table 6. Selection of Operating Modes
Option
Implementation
Note
No Sampling
ΦECHA (3) and ΦECHB (25) Connected to VDD
SΦECHA (4) and SΦECHB (24) Unconnected
(1)
VINH (16) Connected to V DD
Sampling Clocks Connected to ΦECHA - ΦECHB
SΦECHA and SΦECHB Unconnected
VINH (16) Connected to V DD
Sampling By External Clocks
Reset Control By External Clocks
Note:
1. Drain supply current IDD
15V).
See Figure 4 for sampling
clock timing (1)
Ext. ΦRA on ΦRA (5) Input
See Figure 4 for
reset clock timing
Ext. ΦRB on ΦRB (21) Input
decreases from 10 mA to 8 mA typically when internal sampling clock is disabled (VINH = V DD =
Table 7. External ΦRA, ΦRB, ΦECHA, ΦECHB Clocks Characteristics
Values
Parameter
External Reset Clock
Sampling Clock
Reset And Sampling Clock
Capacitance
Symbol
Logic
Min
Typ
Max
Unit
ΦRA, ΦRB,
ΦECHA, ΦECHB
High
12
13
14
V
Low
0.0
0.4
0.6
V
10
15
pF
CΦRA
CΦRB
CΦECHA
CΦECHB
Insertion of a serial resistor (typically 100Ω) at the driver output avoids spurious negative transients.
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TH7841A
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TH7841A
Figure 4. Timing Diagram — Clocks and Video Output Timing Diagram With and Without On-chip Sampling
Table 8. Performance Improvement with External ΦRA, ΦRB Configuration(1)(2)
Values
Parameter
Saturation Output Voltage
Responsivity
Dynamic Range
Notes:
Symbol
(Typ)
Unit
VSAT
2.0
V
R
5.0
V/µJ/cm 2
DR
8,000
1. Electro-optical performances obtained with complementary modes are not guaranteed for standard products.
2. The Conversion factor is typically 1.8 µV/e-.
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Packaging Information
TH 7841A with standard window.
Z = 1.28 ± 0.23
2.16
Notes:
1. If an optical reference is needed, it is recommended to use the window face plane.
2. Variation of Z (azimuth) on the photosensitive area of a device is ≤ 0.1 mm
3. Variation of Y between the first and the last pixel of the linear area is ≤ ±130 µm.
Ordering Code
10
The ordering code is: TH7841 ACC
TH7841A
1998A–IMAGE–05/02
TH7841A
TH7841A With Antireflective Window
Improvements in the bandwidth 450-750 nm:
•
5% increase in responsivity (typical value: 3.0 V/µJ/cm2).
•
limitation of the parasitic reflections.
Package Drawing
2.16
Notes:
1. If an optical reference is needed, it is recommended to use the window face plane.
2. Variation of Z (azimuth) on the photosensitive area of a device is ≤ 0.1 mm
3. Variation of Y between the first and the last pixel of the linear area is ≤ ±130 µm.
Ordering Code
The ordering code is: TH7841 ACC-R
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© Atmel Corporation 2002.
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