Stratix

Stratix
Section III. I/O Standards
This section provides information on Stratix® single-ended, voltagereferenced, and differential I/O standards.
It contains the following chapters:
Revision History
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Chapter 4, Selectable I/O Standards in Stratix & Stratix GX Devices
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Chapter 5, High-Speed Differential I/O Interfaces in Stratix Devices
The table below shows the revision history for Chapters 4 and 5.
Chapter
Date/Version
4
June 2006, v3.4
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Updated “AC Hot Socketing Specification” section.
July 2005, v3.3
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Updated “Non-Voltage-Referenced Standards” section.
Minor change to Table 4–6.
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Updated content throughout.
January 2005,
v3.2
Altera Corporation
Changes Made
Comments
Section III–1
I/O Standards
Chapter
Stratix Device Handbook, Volume 2
Date/Version
September 2004,
v3.1
Changes Made
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April 2004, v3.0
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November 2003,
v2.2
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October 2003,
v2.1
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July 2003, v2.0
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Section III–2
Comments
Table 4–1 on page 4–1: renamed table, updated table, and
added Note 1.
Deleted Figure named “1.5-V Differential HSTL Class II
Termination.”
Updated text describing “SSTL-18 Class I & II - EIA/JEDEC
Preliminary Standard JC42.3” on page 4–11.
Updated HyperTransport data rates on page 4–17.
Changed HyperTransport device speed from 800 MHz to
400 MHz on page 4–17.
Added four rows to Table 4–2 on page 4–18: 1.5V HSTL Class I, 1.8-V HSTL Class I, 1.5-V HSTL Class II,
and 1.8-V HSTL Class II.
Changed title of Table 4–3 on page 4–21.
Updated Table 4–4 on page 4–22.
Updated Figure 4–20 on page 4–29.
Added description of which clock pins support differential
on-chip termination on page 4–30.
Updated description of flip-chip packages on page 4–31.
Changed title of Figure 4–21 on page 4–31.
Updated milliamps for non-thermally enhanced cavity up
and non-thermally enhanced FineLine BGA packages on
page 4–35.
Updated equation for FineLine BGA package on
page 4–35.
Updated milliamps in non-thermally enhanced cavity up and
non-thermally enhanced FineLine BGA packages
onpage 4–37.
Updated notes to Figure 4–18.
New information added to the “Hot Socketing” section.
New information added to the “Differential Pad Placement
Guidelines” section.
Removed support for series and parallel on-chip
termination.
Updated Figure 4–22.
Added the Output Enable Group Logic Option in Quartus II
and Toggle Rate Logic Option in Quartus II sections.
Updated notes to Table 4–10.
Renamed impedance matching to series termination
throughout Chapter.
Removed wide range specs for LVTTL and LVCMOS
standards pages 4-3 to 4-5.
Relaxed restriction of input pins next to differential pins for
flipchip packages (pages 4-20, 4-35, and 4-36).
Added Drive Strength section on page 4-26.
Removed text “for 10 ns or less” from AC Hot socketing
specification on page 4-27.
Added Series Termination column to Table 4-9.
Altera Corporation
I/O Standards
Chapter
Date/Version
5
July 2005, v3.2
September 2004,
v3.1
Changes Made
Updated Table 5–14 on page 5–58.
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April 2004, v3.0
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November 2003,
v2.2
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Updated Note 3 in Table 5–10 on page 5–54.
Updated Table 5–7 on page 5–34.
Updated Table 5–8 on page 5–36.
Updated description of “RD Differential Termination” on
page 5–46.
Updated Note 5 in Table 5–14 on page 5–58.
Updated Notes 2, 5, and 7 in Table 5–11 on page 5–56
through Table 5–14 on page 5–58.
Added new text about spanning two I/O banks on
page 5–60.
Updated notes for Figure 5–17.
Updated Table 5–7, 5–8, and 5–10.
“Data Alignment with Clock” section, last sentence: change
made from 90 degrees to 180 degrees.
Removed support for series and parallel on-chip
termination.
Updated the number of channels per PLL in Tables 5-10
through 5-14.
October 2003,
v2.1
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Added -8 speed grade device information, including Tables
5-7 and 5-8.
July 2003, v2.0
●
Format changes throughout Chapter.
Relaxed restriction of input pins next to differential pins for
flip chip packages in Figure 5-1, Note 5.
Wire bond package performance specification for “high”
speed channels was increased to 624 Mbps from 462 Mbps
throughout Chapter.
Updated high-speed I/O specification for J=2 in Tables 5-7
and 5-8.
Updated Tables 5-10 to 5-14 to reflect PLL cross-bank
support for high-speed differential channels at full speed.
Increased maximum output clock frequency to 462 to 500
MHz on page 5-66.
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Altera Corporation
Comments
Section III–3
I/O Standards
Section III–4
Stratix Device Handbook, Volume 2
Altera Corporation
4. Selectable I/O Standards
in Stratix &
Stratix GX Devices
S52004-3.4
Introduction
The proliferation of I/O standards and the need for higher I/O
performance have made it critical that devices have flexible I/O
capabilities. Stratix® and Stratix GX programmable logic devices (PLDs)
feature programmable I/O pins that support a wide range of industry
I/O standards, permitting increased design flexibility. These I/O
capabilities enable fast time-to-market and high-performance solutions to
meet the demands of complex system designs. Additionally, Stratix and
Stratix GX devices simplify system board design and make it easy to
connect to microprocessors, peripherals, memories, gate arrays,
programmable logic circuits, and standard logic functions.
This chapter provides guidelines for using one or more industry I/O
standards in Stratix and Stratix GX devices, including:
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Stratix & Stratix
GX I/O
Standards
Stratix and Stratix GX I/O standards
High-speed interfaces
Stratix and Stratix GX I/O banks
Programmable current drive strength
Hot socketing
Differential on-chip termination
I/O pad placement guidelines
Quartus® II software support
Stratix and Stratix GX devices support a wide range of industry I/O
standards as shown in the Stratix Device Family Data Sheet section in the
Stratix Device Handbook, Volume 1 and the Stratix GX Device Family Data
Sheet section of the Stratix GX Device Handbook, Volume 1. Several
applications that use these I/O standards are listed in Table 4–1.
Table 4–1. I/O Standard Applications & Performance (Part 1 of 2) Note (1)
I/O Standard
Altera Corporation
June 2006
Application
Performance
3.3-V LVTTL/LVCMOS
General purpose
350 MHz
2.5-V LVTTL/LVCMOS
General purpose
350 MHz
1.8-V LVTTL/LVCMOS
General purpose
250 MHz
1.5-V LVCMOS
General purpose
225 MHz
PCI/CompactPCI
PC/embedded systems
66 MHz
4–1
Stratix & Stratix GX I/O Standards
Table 4–1. I/O Standard Applications & Performance (Part 2 of 2) Note (1)
I/O Standard
Application
Performance
PCI-X 1.0
PC/embedded systems
133 MHz
AGP 1× and 2×
Graphics processors
66 to 133 MHz
SSTL-3 Class I and II
SDRAM
167 MHz
SSTL-2 Class I and II
DDR I SDRAM
160 to 400 Mbps
HSTL Class I
QDR SRAM/SRAM/CSIX
150 to 225 MHz
HSTL Class II
QDR SRAM/SRAM/CSIX
150 to 250 MHz
Differential HSTL
Clock interfaces
150 to 225 MHz
GTL
Backplane driver
200 MHz
GTL+
Pentium processor interface
133 to 200 MHz
LVDS
Communications
840 Mbps
HyperTransport
technology
Motherboard interfaces
800 Mbps
LVPECL
PHY interface
840 Mbps
PCML
Communications
840 Mbps
Differential SSTL-2
DDR I SDRAM
160 to 400 Mbps
CTT
Back planes and bus interfaces 200 MHz
Note to Table 4–1:
(1)
These performance values are dependent on device speed grade, package type
(flip-chip or wirebond) and location of I/Os (top/bottom or left/right). See the
DC & Switching Characteristics chapter of the Stratix Device Handbook, Volume 1.
3.3-V Low Voltage Transistor-Transistor Logic (LVTTL) EIA/JEDEC Standard JESD8-B
The 3.3-V LVTTL I/O standard is a general-purpose, single-ended
standard used for 3.3-V applications. The LVTTL standard defines the DC
interface parameters for digital circuits operating from a 3.0-V or 3.3-V
power supply and driving or being driven by LVTTL-compatible devices.
The LVTTL input standard specifies a wider input voltage range of
–0.5 V ≤VI ≤ 3.8 V. Altera allows an input voltage range of –0.5 V ≤VI ≤ 4.1
V. The LVTTL standard does not require input reference voltages or board
terminations.
Stratix and Stratix GX devices support both input and output levels for
3.3-V LVTTL operation.
4–2
Stratix Device Handbook, Volume 2
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
3.3-V LVCMOS - EIA/JEDEC Standard JESD8-B
The 3.3-V low voltage complementary metal oxide semiconductor
(LVCMOS) I/O standard is a general-purpose, single-ended standard
used for 3.3-V applications. The LVCMOS standard defines the DC
interface parameters for digital circuits operating from a 3.0-V or 3.3-V
power supply and driving or being driven by LVCMOS-compatible
devices.
The LVCMOS standard specifies the same input voltage requirements as
LVTTL (–0.5 V ≤VI ≤ 3.8 V). The output buffer drives to the rail to meet the
minimum high-level output voltage requirements. The 3.3-V I/O
standard does not require input reference voltages or board terminations.
Stratix and Stratix GX devices support both input and output levels for
3.3-V LVCMOS operation.
2.5-V LVTTL Normal Voltage Range - EIA/JEDEC Standard
EIA/JESD8-5
The 2.5-V I/O standard is used for 2.5-V LVTTL applications. This
standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other
2.5-V devices. The input and output voltage ranges are:
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The 2.5-V normal range input standards specify an input voltage
range of – 0.3 V ≤ VI ≤ 3.0 V.
The normal range minimum high-level output voltage requirement
(VOH) is 2.1 V.
Stratix and Stratix GX devices support both input and output levels for
2.5-V LVTTL operation.
2.5-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard
EIA/JESD8-5
The 2.5-V I/O standard is used for 2.5-V LVCMOS applications. This
standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other
2.5-V parts. The input and output voltage ranges are:
■
■
Altera Corporation
June 2006
The 2.5-V normal range input standards specify an input voltage
range of – 0.5 V ≤ VI ≤ 3.0 V.
The normal range minimum VOH requirement is 2.1 V.
4–3
Stratix Device Handbook, Volume 2
Stratix & Stratix GX I/O Standards
Stratix and Stratix GX devices support both input and output levels for
2.5-V LVCMOS operation.
1.8-V LVTTL Normal Voltage Range - EIA/JEDEC Standard
EIA/JESD8-7
The 1.8-V I/O standard is used for 1.8-V LVTTL applications. This
standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other
1.8-V parts. The input and output voltage ranges are:
■
■
The 1.8-V normal range input standards specify an input voltage
range of – 0.5 V ≤ VI ≤ 2.3 V.
The normal range minimum VOH requirement is VCCIO – 0.45 V.
Stratix and Stratix GX devices support both input and output levels for
1.8-V LVTTL operation.
1.8-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard
EIA/JESD8-7
The 1.8-V I/O standard is used for 1.8-V LVCMOS applications. This
standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other
1.8-V devices. The input and output voltage ranges are:
■
■
The 1.8-V normal range input standards specify an input voltage
range of – 0.5 V ≤ VI ≤ 2.5 V.
The normal range minimum VOH requirement is VCCIO – 0.45 V.
Stratix and Stratix GX devices support both input and output levels for
1.8-V LVCMOS operation.
1.5-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard
JESD8-11
The 1.5-V I/O standard is used for 1.5-V applications. This standard
defines the DC interface parameters for high-speed, low-voltage, nonterminated digital circuits driving or being driven by other 1.5-V devices.
The input and output voltage ranges are:
■
■
The 1.5-V normal range input standards specify an input voltage
range of – 0.5 V ≤ VI ≤ 2.0 V.
The normal range minimum VOH requirement is 1.05 V.
4–4
Stratix Device Handbook, Volume 2
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Stratix and Stratix GX devices support both input and output levels for
1.5-V LVCMOS operation.
1.5-V HSTL Class I & II - EIA/JEDEC Standard EIA/JESD8-6
The high-speed transceiver logic (HSTL) I/O standard is used for
applications designed to operate in the 0.0- to 1.5-V HSTL logic switching
range. This standard defines single ended input and output specifications
for all HSTL-compliant digital integrated circuits. The single ended input
standard specifies an input voltage range of – 0.3 V ≤ VI ≤ VCCIO + 0.3 V.
Stratix and Stratix GX devices support both input and output levels
specified by the 1.5-V HSTL I/O standard. The input clock is
implemented using dedicated differential input buffers. Two singleended output buffers are automatically programmed to have opposite
polarity so as to implement a differential output clock. Additionally, the
1.5-V HSTL I/O standard in Stratix and Stratix GX devices is compatible
with the 1.8-V HSTL I/O standard in APEXTM 20KE and APEX 20KC
devices because the input and output voltage thresholds are compatible.
See Figures 4–1 and 4–2. Stratix and Stratix GX devices support both
input and output levels with VREF and VTT.
Figure 4–1. HSTL Class I Termination
VTT = 0.75 V
Output Buffer
50 Ω
Z = 50 Ω
Input Buffer
VREF = 0.75 V
Figure 4–2. HSTL Class II Termination
VTT = 0.75 V
VTT = 0.75 V
Output Buffer
50 Ω
50 Ω
Z = 50 Ω
Input Buffer
VREF = 0.75 V
Altera Corporation
June 2006
4–5
Stratix Device Handbook, Volume 2
Stratix & Stratix GX I/O Standards
1.5-V Differential HSTL - EIA/JEDEC Standard EIA/JESD8-6
The differential HSTL I/O standard is used for applications designed to
operate in the 0.0- to 1.5-V HSTL logic switching range such as quad data
rate (QDR) memory clock interfaces. The differential HSTL specification
is the same as the single ended HSTL specification. The standard specifies
an input voltage range of – 0.3 V ≤ VI ≤ VCCIO + 0.3 V. Differential HSTL
does not require an input reference voltage, however, it does require a
50 Ω resistor termination resistor to VTT at the input buffer (see
Figure 4–3). Stratix and Stratix GX devices support both input and output
clock levels for 1.5-V differential HSTL. The input clock is implemented
using dedicated differential input buffer. Two single-ended output
buffers are automatically programmed to have opposite polarity so as to
implement a differential output clock.
Figure 4–3. 1.5-V Differential HSTL Class I Termination
VTT = 0.75 V
Differential
Transmitter
50 Ω
VTT = 0.75 V
50 Ω
Differential
Receiver
Z0 = 50 Ω
Z0 = 50 Ω
3.3-V PCI Local Bus - PCI Special Interest Group PCI Local Bus
Specification Rev. 2.3
The PCI local bus specification is used for applications that interface to
the PCI local bus, which provides a processor-independent data path
between highly integrated peripheral controller components, peripheral
add-in boards, and processor/memory systems. The conventional PCI
specification revision 2.3 defines the PCI hardware environment
including the protocol, electrical, mechanical, and configuration
specifications for the PCI devices and expansion boards. This standard
requires 3.3-V VCCIO. Stratix and Stratix GX devices are fully compliant
with the 3.3-V PCI Local Bus Specification Revision 2.3 and meet
64-bit/66-MHz operating frequency and timing requirements. The 3.3-V
PCI standard does not require input reference voltages or board
terminations. Stratix and Stratix GX devices support both input and
output levels.
4–6
Stratix Device Handbook, Volume 2
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
3.3-V PCI-X 1.0 Local Bus - PCI-SIG PCI-X Local Bus
Specification Revision 1.0a
The PCI-X 1.0 standard is used for applications that interface to the PCI
local bus. The standard enables the design of systems and devices that
operate at clock speeds up to 133 MHz, or 1 gigabit per second (Gbps) for
a 64-bit bus. The PCI-X 1.0 protocol enhancements enable devices to
operate much more efficiently, providing more usable bandwidth at any
clock frequency. By using the PCI-X 1.0 standard, devices can be designed
to meet PCI-X 1.0 requirements and operate as conventional 33- and
66-MHz PCI devices when installed in those systems. This standard
requires 3.3-V VCCIO. Stratix and Stratix GX devices are fully compliant
with the 3.3-V PCI-X Specification Revision 1.0a and meet the 133-MHz
operating frequency and timing requirements. The 3.3-V PCI standard
does not require input reference voltages or board terminations. Stratix
and Stratix GX devices support both input and output levels.
3.3-V Compact PCI Bus - PCI SIG PCI Local Bus Specification
Revision 2.3
The Compact PCI local bus specification is used for applications that
interface to the PCI local bus. It follows the PCI Local Bus Specification
Revision 2.3 plus additional requirements in PCI Industrial Computers
Manufacturing Group (PICMG) specifications PICMG 2.0 R3.0,
CompactPCI specification, and the hot swap requirements in PICMG 2.1
R2.0, CompactPCI Hot Swap Specification. This standard has similar
electrical requirements as LVTTL and requires 3.3-V VCCIO. Stratix and
Stratix GX devices are compliant with the Compact PCI electrical
requirements. The 3.3-V PCI standard does not require input reference
voltages or board terminations. Stratix and Stratix GX devices support
both input and output levels.
3.3-V 1× AGP - Intel Corporation Accelerated Graphics Port
Interface Specification 2.0
The AGP interface is a platform bus specification that enables highperformance graphics by providing a dedicated high-speed port for the
movement of large blocks of 3-dimensional texture data between a PC's
graphics controller and system memory. The 1× AGP I/O standard is a
single-ended standard used for 3.3-V graphics applications. The 1× AGP
input standard specifies an input voltage range of
– 0.5 V ≤ VI ≤ VCCIO + 0.5 V. The 1× AGP standard does not require input
reference voltages or board terminations. Stratix and Stratix GX devices
support both input and output levels.
Altera Corporation
June 2006
4–7
Stratix Device Handbook, Volume 2
Stratix & Stratix GX I/O Standards
3.3-V 2× AGP - Intel Corporation Accelerated Graphics Port
Interface Specification 2.0
The 2× AGP I/O standard is a voltage-referenced, single-ended standard
used for 3.3-V graphics applications. The 2× AGP input standard
specifies an input voltage range of – 0.5V ≤ VI ≤ VCCIO + 0.5V. The 2× AGP
standard does not require board terminations. Stratix and Stratix GX
devices support both input and output levels.
GTL - EIA/JEDEC Standard EIA/JESD8-3
The GTL I/O standard is a low-level, high-speed back plane standard
used for a wide range of applications from ASICs and processors to
interface logic devices. The GTL standard defines the DC interface
parameters for digital circuits operating from power supplies of 2.5, 3.3,
and 5.0 V. The GTL standard is an open-drain standard, and Stratix and
Stratix GX devices support a 2.5- or 3.3-V VCCIO to meet this standard.
GTL requires a 0.8-V VREF and open-drain outputs with a 1.2-V VTT (see
Figure 4–4). Stratix and Stratix GX devices support both input and output
levels.
Figure 4–4. GTL Termination
VTT = 1.2 V
Output Buffer
VTT = 1.2 V
50 Ω
Z = 50 Ω
50 Ω
Input Buffer
VREF = 0.8 V
GTL+
The GTL+ I/O standard is used for high-speed back plane drivers and
Pentium processor interfaces. The GTL+ standard defines the DC
interface parameters for digital circuits operating from power supplies of
2.5, 3.3, and 5.0 V. The GTL+ standard is an open-drain standard, and
Stratix and Stratix GX devices support a 2.5- or 3.3-V VCCIO to meet this
standard. GTL+ requires a 1.0-V VREF and open-drain outputs with a
1.5-V VTT (see Figure 4–5). Stratix and Stratix GX devices support both
input and output levels.
4–8
Stratix Device Handbook, Volume 2
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Figure 4–5. GTL+ Termination
VTT = 1.5 V
VTT = 1.5 V
Output Buffer
50 Ω
50 Ω
Z = 50 Ω
Input Buffer
VREF = 1.0 V
CTT - EIA/JEDEC Standard JESD8-4
The CTT I/O standard is used for backplanes and memory bus interfaces.
The CTT standard defines the DC interface parameters for digital circuits
operating from 2.5- and 3.3-V power supplies. The CTT standard does not
require special circuitry to interface with LVTTL or LVCMOS devices
when the CTT driver is not terminated. The CTT standard requires a 1.5-V
VREF and a 1.5-V VTT (see Figure 4–6). Stratix and Stratix GX devices
support both input and output levels.
Figure 4–6. CTT Termination
VTT = 1.5 V
Output Buffer
50 Ω
Z = 50 Ω
Input Buffer
VREF = 1.5 V
SSTL-3 Class I & II - EIA/JEDEC Standard JESD8-8
The SSTL-3 I/O standard is a 3.3-V memory bus standard used for
applications such as high-speed SDRAM interfaces. This standard
defines the input and output specifications for devices that operate in the
SSTL-3 logic switching range of 0.0 to 3.3 V. The SSTL-3 standard specifies
an input voltage range of – 0.3 V ≤ VI ≤ VCCIO + 0.3 V. SSTL-3 requires a 1.5V VREF and a 1.5-V VTT to which the series and termination resistors are
connected (see Figures 4–7 and 4–8). Stratix and Stratix GX devices
support both input and output levels.
Altera Corporation
June 2006
4–9
Stratix Device Handbook, Volume 2
Stratix & Stratix GX I/O Standards
Figure 4–7. SSTL-3 Class I Termination
VTT = 1.5 V
Output Buffer
50 Ω
25 Ω
Z = 50 Ω
Input Buffer
VREF = 1.5 V
Figure 4–8. SSTL-3 Class II Termination
VTT = 1.5 V
VTT = 1.5 V
50 Ω
50 Ω
Output Buffer
25 Ω
Z = 50 Ω
Input Buffer
VREF = 1.5 V
SSTL-2 Class I & II - EIA/JEDEC Standard JESD8-9A
The SSTL-2 I/O standard is a 2.5-V memory bus standard used for
applications such as high-speed DDR SDRAM interfaces. This standard
defines the input and output specifications for devices that operate in the
SSTL-2 logic switching range of 0.0 to 2.5 V. This standard improves
operation in conditions where a bus must be isolated from large stubs.
The SSTL-2 standard specifies an input voltage range of
– 0.3 V ≤ VI ≤ VCCIO + 0.3 V. SSTL-2 requires a 1.25-V VREF and a 1.25-V
VTT to which the series and termination resistors are connected (see
Figures 4–9 and 4–10). Stratix and Stratix GX devices support both input
and output levels.
Figure 4–9. SSTL-2 Class I Termination
VTT = 1.25 V
Output Buffer
50 Ω
25 Ω
Z = 50 Ω
Input Buffer
VREF = 1.25 V
4–10
Stratix Device Handbook, Volume 2
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Figure 4–10. SSTL-2 Class II Termination
VTT = 1.25 V
VTT = 1.25 V
Output Buffer
50 Ω
25 Ω
50 Ω
Z = 50 Ω
Input Buffer
VREF = 1.25 V
SSTL-18 Class I & II - EIA/JEDEC Preliminary Standard JC42.3
The SSTL-18 I/O standard is a 1.8-V memory bus standard. This standard
is similar to SSTL-2 and defines input and output specifications for
devices that are designed to operate in the SSTL-18 logic switching range
0.0 to 1.8 V. SSTL-18 requires a 0.9-V VREF and a 0.9-V VTT to which the
series and termination resistors are connected. See Figures 4–11 and 4–12
for details on SSTL-18 Class I and II termination. Stratix and Stratix GX
devices support both input and output levels.
Figure 4–11. SSTL-18 Class I Termination
VTT = 0.9 V
Output Buffer
50 Ω
25 Ω
Z = 50 Ω
Input Buffer
VREF = 0.9 V
Figure 4–12. SSTL-18 Class II Termination
VTT = 0.9 V
VTT = 0.9 V
50 Ω
50 Ω
Output Buffer
25 Ω
Z = 50 Ω
Input Buffer
VREF = 0.9 V
Differential SSTL-2 - EIA/JEDEC Standard JESD8-9A
The differential SSTL-2 I/O standard is a 2.5-V standard used for
applications such as high-speed DDR SDRAM clock interfaces. This
standard supports differential signals in systems using the SSTL-2
Altera Corporation
June 2006
4–11
Stratix Device Handbook, Volume 2
Stratix & Stratix GX I/O Standards
standard and supplements the SSTL-2 standard for differential clocks.
The differential SSTL-2 standard specifies an input voltage range of
– 0.3 V ≤ VI ≤ VCCIO + 0.3 V. The differential SSTL-2 standard does not
require an input reference voltage differential. See Figure 4–13 for details
on differential SSTL-2 termination. Stratix and Stratix GX devices support
output clock levels for differential SSTL-2 Class II operation. The output
clock is implemented using two single-ended output buffers which are
programmed to have opposite polarity.
Figure 4–13. Differential SSTL-2 Class II Termination
VTT = 1.25 V
Differential
Transmitter
50 Ω
VTT = 1.25 V
50 Ω
VTT = 1.25 V
50 Ω
VTT = 1.25 V
50 Ω
Differential
Receiver
25 Ω
Z0 = 50 Ω
25 Ω
Z0 = 50 Ω
LVDS - ANSI/TIA/EIA Standard ANSI/TIA/EIA-644
The LVDS I/O standard is a differential high-speed, low-voltage swing,
low-power, general-purpose I/O interface standard requiring a 3.3-V
VCCIO. This standard is used in applications requiring high-bandwidth
data transfer, backplane drivers, and clock distribution. The
ANSI/TIA/EIA-644 standard specifies LVDS transmitters and receivers
capable of operating at recommended maximum data signaling rates of
655 Mbps. However, devices can operate at slower speeds if needed, and
there is a theoretical maximum of 1.923 Gbps. Stratix and Stratix GX
devices meet the ANSI/TIA/EIA-644 standard.
Due to the low voltage swing of the LVDS I/O standard, the
electromagnetic interference (EMI) effects are much smaller than CMOS,
TTL, and PECL. This low EMI makes LVDS ideal for applications with
low EMI requirements or noise immunity requirements. The LVDS
standard does not require an input reference voltage, however, it does
require a 100 Ω termination resistor between the two signals at the input
buffer. Stratix and Stratix GX devices include an optional differential
LVDS termination resistor within the device using differential on-chip
termination. Stratix and Stratix GX devices support both input and
output levels.
4–12
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June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
f
For more information on the LVDS I/O standard in Stratix devices, see
the High-Speed Differential I/O Interfaces in Stratix Devices chapter.
LVPECL
The LVPECL I/O standard is a differential interface standard requiring a
3.3-V VCCIO. The standard is used in applications involving video
graphics, telecommunications, data communications, and clock
distribution. The high-speed, low-voltage swing LVPECL I/O standard
uses a positive power supply and is similar to LVDS, however, LVPECL
has a larger differential output voltage swing than LVDS. The LVPECL
standard does not require an input reference voltage, but it does require
a 100-Ω termination resistor between the two signals at the input buffer.
See Figures 4–14 and 4–15 for two alternate termination schemes for
LVPECL. Stratix and Stratix GX devices support both input and output
levels.
Figure 4–14. LVPECL DC Coupled Termination
Output Buffer
Input Buffer
Z = 50 Ω
100 Ω
Z = 50 Ω
Figure 4–15. LVPECL AC Coupled Termination
VCCIO
VCCIO
Output Buffer
10 to 100 nF
Z = 50 Ω
R1
R1
R2
R2
Input Buffer
100 Ω
10 to 100 nF
Z = 50 Ω
Pseudo Current Mode Logic (PCML)
The PCML I/O standard is a differential high-speed, low-power I/O
interface standard used in applications such as networking and
telecommunications. The standard requires a 3.3-V VCCIO. The PCML I/O
standard consumes less power than the LVPECL I/O standard. The
Altera Corporation
June 2006
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Stratix Device Handbook, Volume 2
Stratix & Stratix GX I/O Standards
PCML standard is similar to LVPECL, but PCML has a reduced voltage
swing, which allows for a faster switching time and lower power
consumption. The PCML standard uses open drain outputs and requires
a differential output signal. See Figure 4–16 for details on PCML
termination. Stratix and Stratix GX devices support both input and
output levels.
Additionally, Stratix GX devices support 1.5-V PCML as described in the
Stratix GX Device Handbook, Volume 1.
Figure 4–16. PCML Termination
VTT
Output Buffer
50 Ω
50 Ω
Z = 50 Ω
50 Ω
50 Ω
Input Buffer
Z = 50 Ω
HyperTransport Technology - HyperTransport Consortium
The HyperTransport technology I/O standard is a differential highspeed, high-performance I/O interface standard requiring a 2.5-V VCCIO.
This standard is used in applications such as high-performance
networking, telecommunications, embedded systems, consumer
electronics, and Internet connectivity devices. The HyperTransport
technology I/O standard is a point-to-point standard in which each
HyperTransport technology bus consists of two point-to-point
unidirectional links. Each link is 2 to 32 bits. The HyperTransport
technology standard does not require an input reference voltage.
However, it does require a 100-Ω termination resistor between the two
signals at the input buffer. See Figure 4–17 for details on HyperTransport
technology termination. Stratix and Stratix GX devices support both
input and output levels.
Figure 4–17. HyperTransport Technology Termination
Output Buffer
Input Buffer
Z = 50 Ω
100 Ω
Z = 50 Ω
4–14
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Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
f
High-Speed
Interfaces
See the Stratix Device Family Data Sheet section in the Stratix Device
Handbook, Volume 1; the Stratix GX Device Family Data Sheet section of the
Stratix GX Device Handbook, Volume 1; and the High-Speed Differential I/O
Interfaces in Stratix Devices chapter for more information on differential
I/O standards.
In addition to current industry physical I/O standards, Stratix and
Stratix GX devices also support a variety of emerging high-speed
interfaces. This section provides an overview of these interfaces.
OIF-SPI4.2
This implementation agreement is widely used in the industry for
OC-192 and 10-Gbps multi-service system interfaces. SONET and SDH
are synchronous transmission systems over which data packets are
transferred. POS-PHY Level 4 is a standard interface for switches and
routers, and defines the operation between a physical layer (PHY) device
and link layer devices (ATM, Internet protocol, and Gigabit Ethernet) for
bandwidths of OC-192 ATM, POS, and 10-Gigabit Ethernet applications.
Some key POS-PHY Level 4 system features include:
■
■
■
■
■
■
■
■
■
Large selection of POS-PHY Level 4-based PHYs
Independent of data protocol
Wide industry support
LVDS I/O standard to improve signal integrity
Inband addressing/control
Out of band flow control
Scalable architecture
Over 622-Mbps operation
Dynamic interface timing mode
POS-PHY Level 4 operates at a wide range of frequencies.
OIF-SFI4.1
This implementation agreement is widely used in the industry for
interfacing physical layer (PHY) to the serializer-deserializer (SERDES)
devices in OC-192 and 10 Gbps multi-service systems. The POS-PHY
Level 4 interface standard defines the SFI-4 standard. POS-PHY
Level 4: SFI-4 is a standardized 16-bit × 622-Mbps line-side interface for
10-Gbps applications. Internet LAN and WAN architectures use
telecommunication SONET protocols for data transferring data over the
PHY layer. SFI-4 interfaces between OC-192 SERDES and SONET
framers.
Altera Corporation
June 2006
4–15
Stratix Device Handbook, Volume 2
High-Speed Interfaces
10 Gigabit Ethernet Sixteen Bit Interface (XSBI) - IEEE Draft
Standard P802.3ae/D2.0
10 Gigabit Ethernet XSBI is an interface standard for LANs, metropolitan
area networks (MANs), storage area networks (SANs), and WANs.
10 Gigabit Ethernet XSBI provides many features for efficient, effective
high-speed networking, including easy migration to higher performance
levels without disruption, lower cost of ownership including acquisition
and support versus other alternatives, familiar management tools and
common skills, ability to support new applications and data protocols,
flexibility in network design, and multiple vendor sourcing and
interoperability.
Under the ISO Open Systems Interconnection (OSI) model, Ethernet is a
Layer 2 protocol. 10 Gigabit Ethernet XSBI uses the IEEE 802.3 Ethernet
media access control (MAC) protocol, Ethernet frame format, and the
minimum/maximum frame size. An Ethernet PHY corresponding to OSI
layer 1 connects the media to the MAC layer that corresponds to OSI
layer 2. The PHY is divided into a physical media dependent (PMD)
element, such as optical transceivers, and a physical coding sub-layer
(PCS), which has coding and a serializer/multiplexor. This standard
defines two PHY types, including the LAN PHY and the WAN PHY,
which are distinguished by the PCS. The 10 Gigabit Ethernet XSBI
standard is a full-duplex technology standard that can increase the speed
and distance of Ethernet.
RapidIO Interconnect Specification Revision 1.1
The RapidIO interface is a communications standard used to connect
devices on a circuit board and circuit boards on a backplane. RapidIO is a
packet-switched interconnect standard designed for embedded systems
such as those used in networking and communications. The RapidIO
interface standard is a high-performance interconnect interface used for
transferring data and control information between microprocessors,
DSPs, system memory, communications and network processors, and
peripheral devices in a system.
RapidIO replaces existing peripheral bus and processor technologies
such as PCI. Some features of RapidIO include multiprocessing support,
an open standard, flexible topologies, higher bandwidth, low latency,
error management support in hardware, small silicon footprint, widely
available process and I/O technologies, and transparency to existing
applications and operating system software. The RapidIO standard
provides 10-Gbps device bandwidth using 8-bit-wide input and output
data ports. RapidIO uses LVDS technology, has the capability to be scaled
to multi-GHz frequencies, and features a 10-bit interface.
4–16
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Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
HyperTransport Technology - HyperTransport Consortium
The HyperTransport technology I/O standard is a differential
high-speed, high performance I/O interface standard developed for
communications and networking chip-to-chip communications.
HyperTransport technology is used in applications such as highperformance networking, telecommunications, embedded systems,
consumer electronics, and Internet connectivity devices. The
HyperTransport technology I/O standard is a point-to-point (one source
connected to exactly one destination) standard that provides a highperformance interconnect between integrated circuits in a system, such as
on a motherboard.
Stratix devices support HyperTransport technology at data rates up to
800 Mbps and 32 bits in each direction. HyperTransport technology uses
an enhanced differential signaling technology to improve performance.
HyperTransport technology supports data widths of 2, 4, 8, 16, or 32 bits
in each direction. HyperTransport technology in Stratix and Stratix GX
devices operates at multiple clock speeds up to 400 MHz.
UTOPIA Level 4 – ATM Forum Technical Committee Standard AFPHY-0144.001
The UTOPIA Level 4 frame-based interface standard allows device
manufacturers and network developers to develop components that can
operate at data rates up to 10 Gbps. This standard increases interface
speeds using LVDS I/O and advanced silicon technologies for fast data
transfers.
UTOPIA Level 4 provides new control techniques and a 32-, 16-, or 8-bit
LVDS bus, a symmetric transmit/receive bus structure for easier
application design and testability, nominal data rates of 10 Gbps, in-band
control of cell delimiters and flow control to minimize pin count, sourcesynchronous clocking, and supports variable length packet systems.
UTOPIA Level 4 handles sustained data rates for OC-192 and supports
ATM cells. UTOPIA Level 4 also supports interconnections across
motherboards, daughtercards, and backplane interfaces.
Stratix & Stratix
GX I/O Banks
Altera Corporation
June 2006
Stratix devices have eight I/O banks in addition to the four enhanced PLL
external clock output banks, as shown in Table 4–2 and Figure 4–18. I/O
banks 3, 4, 7, and 8 support all single-ended I/O standards. I/O banks 1,
2, 5, and 6 support differential HSTL (on input clocks), LVDS, LVPECL,
PCML, and HyperTransport technology, as well as all single-ended I/O
standards except HSTL Class II, GTL, SSTL-18 Class II, PCI/PCI-X 1.0,
and 1× /2× AGP. The four enhanced PLL external clock output banks
(I/O banks 9, 10, 11, and 12) support clock outputs all single-ended I/O
4–17
Stratix Device Handbook, Volume 2
Stratix & Stratix GX I/O Banks
standards in addition to differential SSTL-2 and HSTL (both on the output
clock only). Since Stratix devices support both non-voltage-referenced
and voltage-referenced I/O standards, there are different guidelines
when working with either separately or when working with both.
Table 4–2. I/O Standards Supported in Stratix I/O Banks (Part 1 of 2)
Enhanced PLL External
Clock Output Banks
I/O Bank
I/O Standard
1
2
3
4
5
6
7
8
9
10
11
12
3.3-V LVTTL/LVCMOS
v
v
v
v
v
v
v
v
v
v
v
v
2.5-V LVTTL/LVCMOS
v
v
v
v
v
v
v
v
v
v
v
v
1.8-V LVTTL/LVCMOS
v
v
v
v
v
v
v
v
v
v
v
v
1.5-V LVCMOS
v
v
v
v
v
v
v
v
v
v
v
v
PCI/PCIX//Compact PCI
v
v
v
v
v
v
v
v
AGP 1×
v
v
v
v
v
v
v
v
AGP 2×
v
v
v
v
v
v
v
v
SSTL-3 Class I
v
v
v
v
v
v
v
v
v
v
v
v
SSTL-3 Class II
v
v
v
v
v
v
v
v
v
v
v
v
SSTL-2 Class I
v
v
v
v
v
v
v
v
v
v
v
v
SSTL-2 Class II
v
v
v
v
v
v
v
v
v
v
v
v
SSTL-18 Class I
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
SSTL-18 Class II
Differential SSTL-2
(output clocks)
HSTL Class I
v
v
v
v
v
v
v
v
v
v
v
v
1.5-V HSTL Class I
v
v
v
v
v
v
v
v
v
v
v
v
1.8-V HSTL Class I
v
v
v
v
v
v
v
v
v
v
v
v
HSTL Class II
v
v
v
v
v
v
v
v
1.5-V HSTL Class II
v
v
v
v
v
v
v
v
1.8-V HSTL Class II
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Differential HSTL (input
clocks)
v
v
v
v
Differential HSTL (output
clocks)
GTL
4–18
Stratix Device Handbook, Volume 2
v
v
v
v
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Table 4–2. I/O Standards Supported in Stratix I/O Banks (Part 2 of 2)
Enhanced PLL External
Clock Output Banks
I/O Bank
I/O Standard
1
2
3
4
5
6
7
8
9
10
11
12
GTL+
v
v
v
v
v
v
v
v
v
v
v
v
CTT
v
v
v
v
v
v
v
v
v
v
v
v
LVDS
v
v
(1)
(1)
v
v
(1)
(1)
(2)
(2)
(2)
(2)
HyperTransport
technology
v
v
(1)
(1)
v
v
(1)
(1)
(2)
(2)
(2)
(2)
LVPECL
v
v
(1)
(1)
v
v
(1)
(1)
(2)
(2)
(2)
(2)
PCML
v
v
(1)
(1)
v
v
(1)
(1)
(2)
(2)
(2)
(2)
Notes to Table 4–2:
(1)
(2)
This I/O standard is only supported on input clocks in this I/O bank.
This I/O standard is only supported on output clocks in this I/O bank.
Altera Corporation
June 2006
4–19
Stratix Device Handbook, Volume 2
Stratix & Stratix GX I/O Banks
Figure 4–18. Stratix I/O Banks Notes (1), (2), (3)
DQS5T
9
DQS4T
PLL11
(5)
DQS1T
DQS0T
10
Bank 4
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
(5)
I/O Banks 1, 2, 5, and 6 Support All
Single-Ended I/O Standards Except
Differential HSTL Output Clocks,
Differential SSTL-2 Output Clocks,
HSTL Class II, GTL, SSTL-18 Class II,
PCI, PCI-X 1.0, and AGP 1×/2×
PLL2
Bank 1
DQS2T
I/O Banks 3, 4, 9 & 10 Support
All Single-Ended I/O Standards
PLL1
Bank 8
PLL3
DQS8B
DQS7B
DQS6B
DQS5B
(5)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
11
VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8
DQS9B
PLL4
I/O Banks 7, 8, 11 & 12 Support
All Single-Ended I/O Standards
(5)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
PLL8
DQS3T
VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4 PLL10
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
Bank 2
VREF1B2 VREF2B2 VREF3B2 VREF4B2
Bank 3
VREF1B1 VREF2B1 VREF3B1 VREF4B1
PLL5
12
PLL6
Bank 5
DQS6T
VREF4B5 VREF3B5 VREF2B5 VREF1B5
DQS7T
Bank 6
DQS8T
VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3
VREF4B6 VREF3B6 VREF2B6 VREF1B6
DQS9T
PLL7
Bank 7
PLL12
VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7
DQS4B
DQS3B
DQS2B
DQS1B
PLL9
DQS0B
Notes to Figure 4–18:
(1)
(2)
(3)
(4)
(5)
Figure 4–18 is a top view of the silicon die. This corresponds to a top-down view for non-flip-chip packages, but is
a reverse view for flip-chip packages.
Figure 4–18 is a graphic representation only. See the pin list and the Quartus II software for exact locations.
Banks 9 through 12 are enhanced PLL external clock output banks.
If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the
I/O standards except HSTL Class II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and AGP 1×/2×.
For guidelines on placing single-ended I/O pads next to differential I/O pads, see “I/O Pad Placement Guidelines”
on page 4–30.
4–20
Stratix Device Handbook, Volume 2
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Tables 4–3 and 4–4 list the I/O standards that Stratix GX enhanced and
fast PLL pins support. Figure 4–19 shows the I/O standards that each
Stratix GX I/O bank supports.
Table 4–3. I/O Standards Supported in Stratix & Stratix GX Enhanced PLL Pins
Input
Output
I/O Standard
INCLK
FBIN
PLLENABLE
EXTCLK
LVTTL
v
v
v
v
LVCMOS
v
v
v
v
2.5 V
v
v
v
1.8 V
v
v
v
1.5 V
v
v
v
3.3-V PCI
v
v
v
3.3-V PCI-X 1.0
v
v
v
LVPECL
v
v
v
3.3-V PCML
v
v
v
LVDS
v
v
v
HyperTransport technology
v
v
v
Differential HSTL
v
v
v
Differential SSTL
3.3-V GTL
v
v
v
3.3-V GTL+
v
v
v
1.5-V HSTL Class I
v
v
v
1.5-V HSTL Class II
v
v
v
SSTL-18 Class I
v
v
v
SSTL-18 Class II
v
v
v
SSTL-2 Class I
v
v
v
SSTL-2 Class II
v
v
v
SSTL-3 Class I
v
v
v
SSTL-3 Class II
v
v
v
AGP (1× and 2×)
v
v
v
CTT
v
v
v
Altera Corporation
June 2006
4–21
Stratix Device Handbook, Volume 2
Stratix & Stratix GX I/O Banks
Table 4–4. I/O Standards Supported in Stratix & Stratix GX Fast PLL Pins
Input
I/O Standard
INCLK
PLLENABLE
LVTTL
v
v
LVCMOS
v
v
2.5 V
v
1.8 V
v
1.5 V
v
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL
v
3.3-V PCML
v
LVDS
v
HyperTransport technology
v
Differential HSTL
v
Differential SSTL
3.3-V GTL
3.3-V GTL+
1.5V HSTL Class I
v
1.5V HSTL Class II
SSTL-18 Class I
v
SSTL-18 Class II
SSTL-2 Class I
v
SSTL-2 Class II
v
SSTL-3 Class I
v
SSTL-3 Class II
v
AGP (1× and 2×)
CTT
4–22
Stratix Device Handbook, Volume 2
v
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Figure 4–19. Stratix GX I/O Banks
I/O Bank 2
I/O Banks 1 & 2 Support:
■ Differential I/O Standards
- True LVDS
- LVPECL
- 3.3-V PCML
- HyperTransport Technology
■ Single-Ended I/O Standard
- 3.3 -, 2.5 -, 1.8 -V LVTTL
- GTL+
- CTT
- SSTL-18 Class I
- SSTL-2 Class I and II
- SSTL-3 Class I and II
- 1.5 -, 1.8 -V HSTL Class I
I/O Bank 1
I/O Bank 3
I/O Bank 4
I/O Banks 3, 4, 6 & 7 Support:
■ 3.3-, 2.5-, 1.8-V LVTTL
■ 3.3-V PCI, PCI-X 1.0
■ GTL
■ GTL+
■ AGP
■ CTT
■ SSTL-18 Class I and II
■ SSTL-2 Class I and II
■ SSTL-3 Class I and II
■ HSTL Class I and II
Individual
Power Bus
I/O Bank 7
I/O Bank 6
I/O Bank 5
I/O Bank 5 Contains Transceiver Blocks
There is some flexibility with the number of I/O standards each Stratix
I/O bank can simultaneously support. The following sections provide
guidelines for mixing non-voltage-referenced and voltage-referenced
I/O standards in Stratix devices.
Altera Corporation
June 2006
4–23
Stratix Device Handbook, Volume 2
Stratix & Stratix GX I/O Banks
Non-Voltage-Referenced Standards
Each Stratix I/O bank has its own VCCIO pins and supports only one
VCCIO, either 1.5, 1.8, 2.5 or 3.3 V. A Stratix I/O bank can simultaneously
support any number of input signals with different I/O standard
assignments, as shown in Table 4–5.
Table 4–5. Acceptable Input Levels for LVTTL/LVCMOS
Acceptable Input Levels
Bank VCCIO
3.3 V
2.5 V
1.8 V
1.5 V
3.3 V
v
v
2.5 V
v
v
1.8 V
v (2)
v (2)
v
v (1)
1.5 V
v (2)
v (2)
v
v
Notes to Table 4–5:
(1)
(2)
Because the input signal will not drive to the rail, the input buffer does not
completely shut off, and the I/O current will be slightly higher than the default
value.
These input values overdrive the input buffer, so the pin leakage current will be
slightly higher than the default value.
For output signals, a single I/O bank can only support non-voltagereferenced output signals driving at the same voltage as VCCIO. A Stratix
I/O bank can only have one VCCIO value, so it can only drive out that one
value for non-voltage referenced signals. For example, an I/O bank with
a 2.5-V VCCIO setting can support 2.5-V LVTTL inputs and outputs,
HyperTransport technology inputs and outputs, and 3.3-V LVCMOS
inputs (not output or bidirectional pins).
1
If the output buffer overdrives the input buffer, you must turn
on the Allow voltage overdrive for LVTTL/LVCMOS option in
the Quartus II software. To see this option, click the Device &
Pin Options button in the Device page of the Settings dialog
box (Assignments menu). Then click the Pin Placement tab in
the Device & Pin Options dialog box.
Voltage-Referenced Standards
To accommodate voltage-referenced I/O standards, each Stratix I/O
bank supports multiple VREF pins feeding a common VREF bus. The
number of available VREF pins increases as device density increases. If
these pins are not used as VREF pins, they can not be used as generic I/O
pins.
4–24
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Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
An I/O bank featuring single-ended or differential standards can support
voltage-referenced standards as long as all voltage-referenced standards
use the same VREF setting. For example, although one I/O bank can
implement both SSTL-3 and SSTL-2 I/O standards, I/O pins using these
standards must be in different banks since they require different VREF
values
For voltage-referenced inputs, the receiver compares the input voltage to
the voltage reference and does not take into account the VCCIO setting.
Therefore, the VCCIO setting is irrelevant for voltage referenced inputs.
Voltage-referenced bidirectional and output signals must be the same as
the I/O bank’s VCCIO voltage. For example, although you can place an
SSTL-2 input pin in any I/O bank with a 1.25-V VREF level, you can only
place SSTL-2 output pins in an I/O bank with a 2.5-V VCCIO.
Mixing Voltage Referenced & Non-Voltage Referenced
Standards
Non-voltage referenced and voltage referenced pins can safely be mixed
in a bank by applying each of the rule-sets individually. For example, on
I/O bank can support SSTL-3 inputs and 1.8-V LVCMOS inputs and
outputs with a 1.8-V VCCIO and a 1.5-V VREF. Similarly, an I/O bank can
support 1.5-V LVCMOS, 3.3-V LVTTL (inputs, but not outputs), and
HSTL I/O standards with a 1.5-V VCCIO and 0.75-V VREF.
For the voltage-referenced examples, see the “I/O Pad Placement
Guidelines” section. For details on how the Quartus II software supports
I/O standards, see the “Quartus II Software Support”section.
Altera Corporation
June 2006
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Stratix Device Handbook, Volume 2
Drive Strength
Drive Strength
Each I/O standard supported by Stratix and Stratix GX devices drives out
a minimum drive strength. When an I/O is configured as LVTTL or
LVCMOS I/O standards, you can specify the current drive strength, as
summarized in Table 4–7.
Standard Current Drive Strength
Each I/O standard supported by Stratix and Stratix GX devices drives out
a minimum drive strength. Table 4–6 summarizes the minimum drive
strength of each I/O standard.
Table 4–6. Minimum Current Drive Strength of Each I/O Standard
I/O Standard
Current Strength, IOL/IOH (mA)
GTL
40 (1)
GTL+
34 (1)
SSTL-3 Class I
8
SSTL-3 Class II
16
SSTL-2 Class I
8.1
SSTL-2 Class II
16.4
SSTL-18 Class I
6.7
SSTL-18 Class II
13.4
1.5-V HSTL Class I
8
1.5-V HSTL Class II
16
CTT
8
AGP 1×
IOL = 1.5, IOH = –0.5
Note to Table 4–6:
(1)
Because this I/O standard uses an open drain buffer, this value refers to IOL.
When the SSTL-2 Class I and II I/O standards are implemented on top or
bottom I/O pins, the drive strength is designed to be higher than the
drive strength of the buffer when implemented on side I/O pins. This
allows the top or bottom I/O pins to support 200-MHz operation with the
standard 35-pF load. At the same time, the current consumption when
using top or bottom I/O pins is higher than the side I/O pins. The high
current strength may not be necessary for certain applications where the
value of the load is less than the standard test load (e.g., DDR interface).
The Quartus II software allows you to reduce the drive strength when the
I/O pins are used for the SSTL-2 Class I or Class II I/O standard and
being implemented on the top or bottom I/O through the Current
Strength setting. Select the minimum strength for lower drive strength.
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June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Programmable Current Drive Strength
The Stratix and Stratix GX device I/O pins support various output
current drive settings as shown in Table 4–7. These programmable drive
strength settings help decrease the effects of simultaneously switching
outputs (SSO) in conjunction with reducing system noise. The supported
settings ensure that the device driver meets the IOH and IOL specifications
for the corresponding I/O standard.
Table 4–7. Programmable Drive Strength
I/O Standard
IOH / IOL Current Strength Setting (mA)
3.3-V LVTTL
24 (1), 16, 12, 8, 4
3.3-V LVCMOS
24 (2), 12 (1), 8, 4, 2
2.5-V LVTTL/LVCMOS
16 (1), 12, 8, 2
1.8-V LVTTL/LVCMOS
12 (1), 8, 2
1.5-V LVCMOS
8 (1), 4, 2
Notes to Table 4–7:
(1)
(2)
This is the Quartus II software default current setting.
I/O banks 1, 2, 5, and 6 do not support this setting.
These drive-strength settings are programmable on a per-pin basis (for
output and bidirectional pins only) using the Quartus II software. To
modify the current strength of a particular pin, see “Programmable Drive
Strength Settings” on page 4–40.
Hot Socketing
Stratix devices support hot socketing without any external components.
In a hot socketing situation, a device’s output buffers are turned off
during system power-up or power-down. Stratix and Stratix GX devices
support any power-up or power-down sequence (VCCIO and VCCINT) to
simplify designs. For mixed-voltage environments, you can drive signals
into the device before or during power-up or power-down without
damaging the device. Stratix and Stratix GX devices do not drive out until
the device is configured and has attained proper operating conditions.
Even though you can power up or down the VCCIO and VCCINT power
supplies in any sequence you should not power down any I/O bank(s)
that contains the configuration pins while leaving other I/O banks
powered on. For power up and power down, all supplies (VCCINT and all
VCCIO power planes) must be powered up and down within 100 ms of one
another. This prevents I/O pins from driving out.
Altera Corporation
June 2006
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Stratix Device Handbook, Volume 2
I/O Termination
You can power up or power down the VCCIO and VCCINT pins in any
sequence. The power supply ramp rates can range from 100 ns to 100 ms.
During hot socketing, the I/O pin capacitance is less than 15 pF and the
clock pin capacitance is less than 20 pF.
DC Hot Socketing Specification
The hot socketing DC specification is | IIOPIN | < 300 μ A.
AC Hot Socketing Specification
The hot socketing AC specification is | IIOPIN | < 8 mA for 10 ns or less.
This specification takes into account the pin capacitance, but not board
trace and external loading capacitance. Additional capacitance for trace,
connector, and loading must be considered separately.
IIOPIN is the current at any user I/O pin on the device. The DC
specification applies when all VCC supplies to the device are stable in the
powered-up or powered-down conditions. For the AC specification, the
peak current duration because of power-up transients is 10 ns or less. For
more information, refer to the Hot-Socketing & Power-Sequencing Feature &
Testing for Altera Devices white paper.
I/O Termination
Although single-ended, non-voltage-referenced I/O standards do not
require termination, Altera recommends using external termination to
improve signal integrity where required.
The following I/O standards do not require termination:
■
■
■
■
■
■
■
■
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI/Compact PCI
3.3-V PCI-X 1.0
3.3-V AGP 1×
Voltage-Referenced I/O Standards
Voltage-referenced I/O standards require both an input reference
voltage, VREF, and a termination voltage, VTT. Off-chip termination on the
board should be used for series and parallel termination.
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Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
For more information on termination for voltage-referenced I/O
standards, see the Selectable I/O Standards in Stratix & Stratix GX Devices
chapter in the Stratix Device Handbook, Volume 2; or the Stratix GX Device
Handbook, Volume 2.
Differential I/O Standards
Differential I/O standards typically require a termination resistor
between the two signals at the receiver. The termination resistor must
match the differential load impedance of the bus. Stratix and Stratix GX
devices provide an optional differential termination on-chip resistor
when using LVDS.
See the High-Speed Differential I/O Interfaces in Stratix Devices chapter for
more information on differential I/O standards and their interfaces.
For differential I/O standards, I/O banks support differential
termination when VCCIO equals 3.3 V.
Differential Termination (RD)
Stratix devices support differential on-chip termination for sourcesynchronous LVDS signaling. The differential termination resistors are
adjacent to the differential input buffers on the device. This placement
eliminates stub effects, improving the signal integrity of the serial link.
Using differential on-chip termination resistors also saves board space.
Figure 4–20 shows the differential termination connections for Stratix and
Stratix GX devices.
Figure 4–20. Differential Termination
Differential
Transmitter
Stratix LVDS
Receiver Buffer with
Differential On-Chip Termination
Z0
RD
Z0
Altera Corporation
June 2006
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Stratix Device Handbook, Volume 2
I/O Pad Placement Guidelines
Differential termination for Stratix devices is supported for the left and
right I/O banks. Differential termination for Stratix GX devices is
supported for the left, source-synchronous I/O bank. Some of the clock
input pins are in the top and bottom I/O banks, which do not support
differential termination. Clock pins CLK[1,3,8,10] support differential
on-chip termination. Clock pins CLK[0,2,9,11], CLK[4-7], and CLK[12-15]
do not support differential on-chip termination.
Transceiver Termination
Stratix GX devices feature built-in on-chip termination within the
transceiver at both the transmit and receive buffers. This termination
improves signal integrity and provides support for the 1.5-V PCML I/O
standard.
I/O Pad
Placement
Guidelines
This section provides pad placement guidelines for the programmable
I/O standards supported by Stratix and Stratix GX devices and includes
essential information for designing systems using the devices' selectable
I/O capabilities. These guidelines will reduce noise problems so that
FPGA devices can maintain an acceptable noise level on the line from the
VCCIO supply. Since Altera FPGAs require that a separate VCCIO power
each bank, these noise issues do not have any effect when crossing bank
boundaries and these guidelines do not apply. Although pad placement
rules need not be considered between I/O banks, some rules must be
considered if you are using a VREF signal in a PLLOUT bank. Note that the
signals in the PLLOUT banks share the VREF supply with neighboring I/O
banks and, therefore, must adhere to the VREF rules discussed in “VREF
Pad Placement Guidelines”.
Differential Pad Placement Guidelines
To avoid cross coupling and maintain an acceptable noise level on the
VCCIO supply, there are restrictions on the placement of single-ended I/O
pads in relation to differential pads. Use the following guidelines for
placing single-ended pads with respect to differential pads in Stratix
devices. These guidelines apply for LVDS, HyperTransport technology,
LVPECL, and PCML I/O standards. The differential pad placement
guidelines do not apply for differential HSTL and differential SSTL
output clocks since each differential output clock is essentially
implemented using two single-ended output buffers. These rules do not
apply to differential HSTL input clocks either even though the dedicated
input buffers are used. However, both differential HSTL and differential
SSTL output standards must adhere to the single-ended (VREF) pad
placement restrictions discussed in “VREF Pad Placement Guidelines”.
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June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
■
■
For flip-chip packages, there are no restrictions for placement of
single-ended input signals with respect to differential signals (see
Figure 4–21). For wire-bond packages, single ended input pads may
only be placed four or more pads away from a differential pad.
Single-ended outputs and bidirectional pads may only be placed five
or more pads away from a differential pad (see Figure 4–21),
regardless of package type.
Figure 4–21. Legal Pin Placement Note (1)
Wirebond
Input
Input, Output,
Bidirectional
Differential Pin
FlipChip
Input
Input
Input, Output,
Bidirectional
Note to Figure 4–21:
(1)
Input pads on a flip-chip packages have no restrictions.
VREF Pad Placement Guidelines
Restrictions on the placement of single-ended voltage-referenced I/O
pads with respect to VREF pads help maintain an acceptable noise level
on the VCCIO supply and to prevent output switching noise from shifting
the VREF rail. The following guidelines are for placing single-ended pads
in Stratix devices.
Input Pins
Each VREF pad supports a maximum of 40 input pads with up to 20 on
each side of the VREF pad.
Output Pins
When a voltage referenced input or bidirectional pad does not exist in a
bank, there is no limit to the number of output pads that can be
implemented in that bank. When a voltage referenced input exists, each
VREF pad supports 20 outputs for thermally enhanced FineLine BGA®
and thermally enhanced BGA cavity up packages or 15 outputs for Nonthermally enhanced cavity up and non-thermally enhanced
FineLine BGA packages.
Altera Corporation
June 2006
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Stratix Device Handbook, Volume 2
I/O Pad Placement Guidelines
Bidirectional Pins
Bidirectional pads must satisfy input and output guidelines
simultaneously. If the bidirectional pads are all controlled by the same OE
and there are no other outputs or voltage referenced inputs in the bank,
then there is no case where there is a voltage referenced input active at the
same time as an output. Therefore, the output limitation does not apply.
However, since the bidirectional pads are linked to the same OE, the
bidirectional pads act as inputs at the same time. Therefore, the input
limitation of 40 input pads (20 on each side of the VREF pad) applies.
If any of the bidirectional pads are controlled by different output enables
(OE) and there are no other outputs or voltage referenced inputs in the
bank, then there may be a case where one group of bidirectional pads is
acting as inputs while another group is acting as outputs. In such cases,
apply the formulas shown in Table 4–8.
Table 4–8. Input-Only Bidirectional Pin Limitation Formulas
Package Type
Formula
Thermally enhanced FineLine BGA and <Total number of bidirectional pads> – <Total number of pads from the
thermally enhanced BGA cavity up
smallest group of pads controlled by an OE> ≤20 (per VREF pad)
Non-thermally enhanced cavity up and <Total number of bidirectional pads> – <Total number of pads from the
non-thermally enhanced FineLine BGA smallest group of pads controlled by an OE> ≤15 (per VREF pad).
Consider a thermally enhanced FineLine BGA package with eight
bidirectional pads controlled by OE1, eight bidirectional pads controlled
by OE2, and six bidirectional pads controlled by OE3. While this totals 22
bidirectional pads, it is safely allowable because there would be a
maximum of 16 outputs per VREF pad possible assuming the worst case
where OE1 and OE2 are active and OE3 is inactive. This is particularly
relevant in DDR SDRAM applications.
When at least one additional voltage referenced input and no other
outputs exist in the same VREF bank, then the bidirectional pad limitation
must simultaneously adhere to the input and output limitations. See the
following equation.
<Total number of bidirectional pads> + <Total number of input pads> ≤40 (20 on
each side of the VREF pad)
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June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
The previous equation accounts for the input limitations, but you must
apply the appropriate equation from Table 4–9 to determine the output
limitations.
Table 4–9. Bidirectional pad Limitation Formulas (Where VREF Inputs Exist)
Package Type
Formula
Thermally enhanced FineLine BGA and <Total number of bidirectional pads> ≤20 (per VREF pad)
thermally enhanced BGA cavity up
Non-thermally enhanced cavity up and <Total number of bidirectional pads> ≤15 (per VREF pad)
non-thermally enhanced FineLine BGA
When at least one additional output exists but no voltage referenced
inputs exist, apply the appropriate formula from Table 4–10.
Table 4–10. Bidirectional Pad Limitation Formulas (Where VREF Outputs Exist)
Package Type
Formula
Thermally enhanced FineLine BGA and <Total number of bidirectional pads> + <Total number of additional
thermally enhanced BGA cavity up
output pads> – <Total number of pads from the smallest group of pads
controlled by an OE> ≤20 (per VREF pad)
Non-thermally enhanced cavity up and <Total number of bidirectional pads> + <Total number of additional
non-thermally enhanced FineLine BGA output pads> – <Total number of pads from the smallest group of pads
controlled by an OE> ≤15 (per VREF pad)
When additional voltage referenced inputs and other outputs exist in the
same VREF bank, then the bidirectional pad limitation must again
simultaneously adhere to the input and output limitations. See the
following equation.
<Total number of bidirectional pads> + <Total number of input pads> ≤40 (20 on
each side of the VREF pad)
Altera Corporation
June 2006
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Stratix Device Handbook, Volume 2
I/O Pad Placement Guidelines
The previous equation accounts for the input limitations, but you must
apply the appropriate equation from Table 4–9 to determine the output
limitations.
Table 4–11. Bidirectional Pad Limitation Formulas (Multiple VREF Inputs & Outputs)
Package Type
Formula
Thermally enhanced FineLine BGA and <Total number of bidirectional pads> + <Total number of additional
thermally enhanced BGA cavity up
output pads> ≤20 (per VREF pad)
non-thermally enhanced cavity up and <Total number of bidirectional pads> + <Total number of additional
non-thermally enhanced FineLine BGA output pads> ≤15 (per VREF pad)
In addition to the pad placement guidelines, use the following guidelines
when working with VREF standards:
■
■
Each bank can only have a single VCCIO voltage level and a single
VREF voltage level at a given time. Pins of different I/O standards can
share the bank if they have compatible VCCIO values (see Table 4–12
for more details).
In all cases listed above, the Quartus II software generates an error
message for illegally placed pads.
Output Enable Group Logic Option in Quartus II
The Quartus II software can check a design to make sure that the pad
placement does not violate the rules mentioned above. When the
software checks the design, if the design contains more bidirectional pins
than what is allowed, the Quartus II software returns a fitting error. When
all the bidirectional pins are either input or output but not both (for
example, in a DDR memory interface), you can use the Output Enable
Group Logic option. Turning on this option directs the Quartus II Fitter
to view the specified nodes as an output enable group. This way, the Fitter
does not violate the requirements for the maximum number of pins
driving out of a VREF bank when a voltaged-referenced input pin or
bidirectional pin is present.
In a design that implements DDR memory interface with dq, dqs and dm
pins utilized, there are two ways to enable the above logic options. You
can enable the logic options through the Assignment Editor or by adding
the following assignments to your project’s ESF file:
OPTIONS_FOR_INDIVIDUAL_NODES_ONLY
{
dq : OUTPUT_ENABLE_GROUP 1;
dqs : OUTPUT_ENABLE_GROUP 1;
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Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
dm : OUTPUT_ENABLE_GROUP 1;
}
As a result, the Quartus II Fitter does not count the bidirectional pin
potential outputs, and the number of VREF bank outputs remains in the
legal range.
Toggle Rate Logic Option in Quartus II
You should specify the pin’s output toggling rate in order to perform a
stricter pad placement check in the Quartus II software. Specify the
frequency at which a pin toggles in the Quartus II Assignment Editor.
This option is useful for adjusting the pin toggle rate in order to place
them closer to differential pins. The option directs the Quartus II Fitter
toggle-rate checking while allowing you to place a single-ended pin
closer to a differential pin.
DC Guidelines
Variables affecting the DC current draw include package type and desired
termination methods. This section provides information on each of these
variables and also shows how to calculate the DC current for pin
placement.
1
The Quartus II software automatically takes these variables into
account during compilation.
For any 10 consecutive output pads in an I/O bank, Altera recommends
a maximum current of 200 mA for thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up packages and 164 mA for
non-thermally enhanced cavity up and non-thermally enhanced FineLine
BGA packages. The following equation shows the current density
limitation equation for thermally enhanced FineLine BGA and thermally
enhanced BGA cavity up packages:
pin + 9
Σ
Ipin < 200 mA
pin
The following equation shows the current density limitation equation for
non-thermally enhanced cavity up and non-thermally enhanced
FineLine BGA packages:
Altera Corporation
June 2006
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Stratix Device Handbook, Volume 2
I/O Pad Placement Guidelines
pin + 9
Σ
Ipin < 164 mA
pin
Table 4–12 shows the DC current specification per pin for each I/O
standard. I/O standards not shown in the table do not exceed these
current limitations.
Table 4–12. I/O Standard DC Specification Note (1)
IPIN (mA)
Pin I/O Standard
3.3-V VCCIO
2.5-V VCCIO
1.5-V VCCIO
GTL
40
40
-
GTL+
34
34
-
SSTL-3 Class I
8
-
-
SSTL-3 Class II
16
-
-
CTT
8
-
-
SSTL-2 Class I
-
8.1
-
SSTL-2 Class II
-
16.4
-
HSTL Class I
-
-
8
HSTL Class II
-
-
16
Note to Table 4–12:
(1)
f
The current rating on a VREF pin is less than 10μA.
For more information on Altera device packaging, see the Package
Information for Stratix Devices chapter in the Stratix Device Handbook,
Volume 2.
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Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Figure 4–22. Current Draw Limitation Guidelines
I/O Pin Sequence
of an I/O Bank
Any 10 Consecutive I/O Pins,
VCC
GND
Any 10 consecutive I/O pads cannot exceed 200 mA in thermally
enhanced FineLine BGA and thermally enhanced BGA cavity up
packages or 164 mA in non-thermally enhanced cavity up and nonthermally enhanced FineLine BGA packages.
For example, consider a case where a group of 10 consecutive pads are
configured as follows for a thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up package:
■
■
■
Number of SSTL-3 Class I output pads = 3
Number of GTL+ output pads = 4
The rest of the surrounding I/O pads in the consecutive group of 10
are unused
In this case, the total current draw for these 10 consecutive I/O pads
would be:
(# of SSTL-3 Class I pads × 8 mA) +
(# of GTL+ output pads × 34 mA) = (3 × 8 mA) + (4 × 34 mA) = 160 mA
In the above example, the total current draw for all 10 consecutive I/O
pads is less than 200 mA.
Altera Corporation
June 2006
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Stratix Device Handbook, Volume 2
Power Source of Various I/O Standards
Power Source of
Various I/O
Standards
For Stratix and Stratix GX devices, the I/O standards are powered by
different power sources. To determine which source powers the input
buffers, see Table 4–13. All output buffers are powered by VCCIO.
Table 4–13. The Relationships Between Various I/O Standards and the
Power Sources
I/O Standard
Quartus II
Software
Support
Power Source
2.5V/3.3V LVTTL
VCCIO
PCI/PCI-X 1.0
VCCIO
AGP
VCCIO
1.5V/1.8V
VCCIO
GTL
VCCINT
GTL+
VCCINT
SSTL
VCCINT
HSTL
VCCINT
CTT
VCCINT
LVDS
VCCINT
LVPECL
VCCINT
PCML
VCCINT
HyperTransport
VCCINT
You specify which programmable I/O standards to use for Stratix and
Stratix GX devices with the Quartus II software. This section describes
Quartus II implementation, placement, and assignment guidelines,
including
■
■
■
■
■
■
Compiler Settings
Device & Pin Options
Assign Pins
Programmable Drive Strength Settings
I/O Banks in the Floorplan View
Auto Placement & Verification
Compiler Settings
You make Compiler settings in the Compiler Settings dialog box
(Processing menu). Click the Chips & Devices tab to specify the device
family, specific device, package, pin count, and speed grade to use for
your design.
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June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Device & Pin Options
Click Device & Pin Options in the Compiler Settings dialog box to
access the I/O pin settings. For example, in the Voltage tab you can select
a default I/O standard for all pins for the targeted device. I/O pins that
do not have a specific I/O standard assignment default this standard.
Click OK when you are done setting I/O pin options to return to the
Compiler Settings dialog box.
Assign Pins
Click Assign Pins in the Compiler Settings dialog box to view the
device’s pin settings and pin assignments (see Figure 4–23). You can view
the pin settings under Available Pins & Existing Assignments. The
listing does not include VREF pins because they are dedicated pins. The
information for each pin includes:
■
■
■
■
■
■
■
■
Number
Name
I/O Bank
I/O Standard
Type (e.g., row or column I/O and differential or control)
SignalProbe Source Name
Enabled (that is, whether SignalProbe routing is enabled or disabled
Status
Figure 4–23. Assign Pins
Altera Corporation
June 2006
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Stratix Device Handbook, Volume 2
Quartus II Software Support
When you assign an I/O standard that requires a reference voltage to an
I/O pin, the Quartus II software automatically assigns VREF pins. See the
Quartus II Help for instructions on how to use an I/O standard for a pin.
Programmable Drive Strength Settings
To make programmable drive strength settings, perform the following
steps:
1.
In the Tools menu, choose Assignment Organizer.
2.
Choose the Edit specific entity & node settings for: setting, then
select the output or bidirectional pin to specify the current strength
for.
3.
In the Assignment Categories dialog box, select Options for
Individual Nodes Only.
4.
Select Click here to add a new assignment.
5.
In the Assignment dialog box, set the Name field to Current
Strength and set the Setting field to the desired, allowable value.
6.
Click Add.
7.
Click Apply, then OK.
I/O Banks in the Floorplan View
You can view the arrangement of the device I/O banks in the Floorplan
View (View menu) as shown in Figure 4–24. You can assign multiple I/O
standards to the I/O pins in any given I/O bank as long as the VCCIO of
the standards is the same. Pins that belong to the same I/O bank must use
the same VCCIO signal.
Each device I/O pin belongs to a specific, numbered I/O bank. The
Quartus II software color codes the I/O bank to which each I/O pin and
VCCIO pin belong. Turn on the Show I/O Banks option to display the I/O
bank color and the bank numbers for each pin.
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June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Figure 4–24. Floorplan View Window
Auto Placement & Verification of Selectable I/O Standards
The Quartus II software automatically verifies the placement for all I/O
and VREF pins and performs the following actions.
■
■
■
■
■
Altera Corporation
June 2006
Automatically places I/O pins of different VREF standards without
pin assignments in separate I/O banks and enables the VREF pins of
these I/O banks.
Verifies that voltage-referenced I/O pins requiring different VREF
levels are not placed in the same bank.
Reports an error message if the current limit is exceeded for a Stratix
or Stratix GX power bank, as determined by the equation
documented in “DC Guidelines” on page 4–35.
Reserves the unused high-speed differential I/O channels and
regular user I/O pins in the high-speed differential I/O banks when
any of the high-speed differential I/O channels are being used.
Automatically assigns VREF pins and I/O pins such that the current
requirements are met and I/O standards are placed properly.
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Stratix Device Handbook, Volume 2
Conclusion
Conclusion
Stratix and Stratix GX devices provide the I/O capabilities to allow you
to work with current and emerging I/O standards and requirements.
Today’s complex designs demand increased flexibility to work with the
wide variety of available I/O standards and to simplify board design.
With Stratix and Stratix GX device features, such as hot socketing and
differential on-chip termination, you can reduce board design interface
costs and increase your development flexibility.
More
Information
For more information, see the following sources:
■
■
■
■
References
The Stratix Device Family Data Sheet section in the Stratix Device
Handbook, Volume 1
The Stratix GX Device Family Data Sheet section of the Stratix GX
Device Handbook, Volume 1
The High-Speed Differential I/O Interfaces in Stratix Devices chapter
AN 224: High-Speed Board Layout Guidelines
For more information, see the following references:
■
■
■
■
■
■
■
■
Stub Series Terminated Logic for 2.5-V (SSTL-2), JESD8-9B,
Electronic Industries Association, December 2000.
High-Speed Transceiver Logic (HSTL) – A 1.5-V Output Buffer
Supply Voltage Based Interface Standard for Digital Integrated
Circuits, EIA/JESD8-6, Electronic Industries Association, August
1995.
1.5-V +/- 0.1 V (Normal Range) and 0.9 V – 1.6 V (Wide Range)
Power Supply Voltage and Interface Standard for Non-terminated
Digital Integrated Circuits, JESD8-11, Electronic Industries
Association, October 2000.
1.8-V +/- 0.15 V (Normal Range) and 1.2 V – 1.95 V (Wide Range)
Power Supply Voltage and Interface Standard for Non-terminated
Digital Integrated Circuits, JESD8-7, Electronic Industries
Association, February 1997.
Center-Tap-Terminated (CTT) Low-Level, High-Speed Interface
Standard for Digital Integrated Circuits, JESD8-9A, Electronic
Industries Association, November 1993.
2.5-V +/- 0.2V (Normal Range) and 1.8-V to 2.7V (Wide Range)
Power Supply Voltage and Interface Standard for Non-terminated
Digital Integrated Circuits, JESD8-5, Electronic Industries
Association, October 1995.
Interface Standard for Nominal 3V/ 3.3-V Supply Digital Integrated
Circuits, JESD8-B, Electronic Industries Association, September 1999.
Gunning Transceiver Logic (GTL) Low-Level, High-Speed Interface
Standard for Digital Integrated Circuits, JESD8-3, Electronic
Industries Association, November 1993.
4–42
Stratix Device Handbook, Volume 2
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
■
■
■
■
■
■
■
■
Altera Corporation
June 2006
Accelerated Graphics Port Interface Specification 2.0, Intel
Corporation.
Stub Series Terminated Logic for 1.8-V (SSTL-18), Preliminary JC42.3,
Electronic Industries Association.
PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group,
December 1998.
PCI-X Local Bus Specification, Revision 1.0a, PCI Special Interest
Group.
UTOPIA Level 4, AF-PHY-0144.001, ATM Technical Committee.
POS-PHY Level 4: SPI-4, OIF-SPI4-02.0, Optical Internetworking
Forum.
POS-PHY Level 4: SFI-4, OIF-SFI4-01.0, Optical Internetworking
Forum.
Electrical Characteristics of Low Voltage Differential Signaling
(LVDS) Interface Circuits, ANSI/TIA/EIA-644, American National
Standards Institute/Telecommunications Industry/Electronic
Industries Association, October 1995.
4–43
Stratix Device Handbook, Volume 2
References
4–44
Stratix Device Handbook, Volume 2
Altera Corporation
June 2006
5. High-Speed Differential I/O
Interfaces in Stratix Devices
S52005-3.2
Introduction
To achieve high data transfer rates, Stratix® devices support TrueLVDSTM differential I/O interfaces which have dedicated
serializer/deserializer (SERDES) circuitry for each differential I/O pair.
Stratix SERDES circuitry transmits and receives up to 840 megabits per
second (Mbps) per channel. The differential I/O interfaces in Stratix
devices support many high-speed I/O standards, such as LVDS,
LVPECL, PCML, and HyperTransportTM technology. Stratix device highspeed modules are designed to provide solutions for many leading
protocols such as SPI-4 Phase 2, SFI-4, 10G Ethernet XSBI, RapidIO,
HyperTransport technology, and UTOPIA-4.
The SERDES transmitter is designed to serialize 4-, 7-, 8-, or 10-bit wide
words and transmit them across either a cable or printed circuit board
(PCB). The SERDES receiver takes the serialized data and reconstructs the
bits into a 4-, 7-, 8-, or 10-bit-wide parallel word. The SERDES contains the
necessary high-frequency circuitry, multiplexer, demultiplexer, clock,
and data manipulation circuitry. You can use double data rate I/O
(DDRIO) circuitry to transmit or receive differential data in by-one (×1)
or by-two (×2) modes.
1
Contact Altera Applications for more information on other B
values that the Stratix devices support and using ×7-mode in the
Quartus® II software. Stratix devices currently only support
B = 1 and B = 7 in ×7 mode.
This chapter describes the high-speed differential I/O capabilities of
Stratix programmable logic devices (PLDs) and provides guidelines for
their optimal use. You should use this document in conjunction with the
Stratix Device Family Data Sheet section of the Stratix Device Handbook,
Volume 1. Consideration of the critical issues of controlled impedance of
traces and connectors, differential routing, termination techniques, and
DC balance gets the best performance from the device. Therefore, an
elementary knowledge of high-speed clock-forwarding techniques is also
helpful.
Stratix I/O Banks
Altera Corporation
July 2005
Stratix devices contain eight I/O banks, as shown in Figure 5–1. The two
I/O banks on each side contain circuitry to support high-speed LVDS,
LVPECL, PCML, HSTL Class I and II, SSTL-2 Class I and II, and
HyperTransport inputs and outputs.
5–1
Stratix I/O Banks
Figure 5–1. Stratix I/O Banks Notes (1), (2), (3)
DQS5T
9
DQS4T
PLL11
(5)
DQS1T
DQS0T
10
Bank 4
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
(5)
I/O Banks 1, 2, 5, and 6 Support All
Single-Ended I/O Standards Except
Differential HSTL Output Clocks,
Differential SSTL-2 Output Clocks,
HSTL Class II, GTL, SSTL-18 Class II,
PCI, PCI-X 1.0, and AGP 1×/2×
PLL2
Bank 1
DQS2T
I/O Banks 3, 4, 9 & 10 Support
All Single-Ended I/O Standards
PLL1
Bank 8
PLL3
DQS8B
DQS7B
DQS6B
DQS5B
(5)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
11
VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8
DQS9B
PLL4
I/O Banks 7, 8, 11 & 12 Support
All Single-Ended I/O Standards
(5)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
PLL8
DQS3T
VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4 PLL10
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
Bank 2
VREF1B2 VREF2B2 VREF3B2 VREF4B2
Bank 3
VREF1B1 VREF2B1 VREF3B1 VREF4B1
PLL5
12
PLL6
Bank 5
DQS6T
VREF4B5 VREF3B5 VREF2B5 VREF1B5
DQS7T
Bank 6
DQS8T
VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3
VREF4B6 VREF3B6 VREF2B6 VREF1B6
DQS9T
PLL7
Bank 7
PLL12
VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7
DQS4B
DQS3B
DQS2B
DQS1B
PLL9
DQS0B
Notes to Figure 5–1:
(1)
(2)
(3)
(4)
(5)
Figure 5–1 is a top view of the Stratix silicon die, which corresponds to a top-down view of non-flip-chip packages
and a bottom-up view of flip-chip packages.
Figure 5–1 is a graphic representation only. See the pin list and the Quartus II software for exact locations.
Banks 9 through 12 are enhanced PLL external clock output banks.
If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the
I/O standards except HSTL Class I and II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and AGP 1× /2× .
See “Differential Pad Placement Guidelines” on page 4–30. You can only place single-ended output/bidirectional
pads five or more pads away from a differential pad. Use the Show Pads view in the Quartus II Floorplan Editor to
locate these pads. The Quartus II software gives an error message for illegal output or bidirectional pin placement
next to a high-speed differential I/O pin.
Stratix Differential I/O Standards
Stratix devices provide a multi-protocol interface that allows
communication between a variety of I/O standards, including LVDS,
HyperTransport technology, LVPECL, PCML, HSTL Class I and II, and
5–2
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
SSTL-2 Class I and II. This feature makes the Stratix device family ideal
for applications that require multiple I/O standards, such as a protocol
translator.
f
For more information on termination for Stratix I/O standards, see
“Differential I/O Termination” on page 5–46.
Figure 5–2 compares the voltage levels between differential I/O
standards supported in all the Stratix devices.
Figure 5–2. Differential I/O Standards Supported by Stratix Devices
4.0
3.3 V
PCML
3.0 V
3.0
2.1 V
Voltage
(V)
2.0
LVPECL
1.7 V
1.4 V
LVDS
1.0
1.0 V
0.9 V
HyperTransport
0.3 V
0.0
Technology
Altera Corporation
July 2005
5–3
Stratix Device Handbook, Volume 2
Stratix I/O Banks
LVDS
The LVDS I/O standard is a differential high-speed, low-voltage swing,
low-power, general-purpose I/O interface standard requiring a 3.3-V
VCCIO. This standard is used in applications requiring high-bandwidth
data transfer, backplane drivers, and clock distribution. The
ANSI/TIA/EIA-644 standard specifies LVDS transmitters and receivers
capable of operating at recommended maximum data signaling rates of
655 Mbps. However, devices can operate at slower speeds if needed, and
there is a theoretical maximum of 1.923 Gbps. Stratix devices meet the
ANSI/TIA/EIA-644 standard.
Due to the low voltage swing of the LVDS I/O standard, the
electromagnetic interference (EMI) effects are much smaller than CMOS,
transistor-to-transistor logic (TTL), and PECL. This low EMI makes LVDS
ideal for applications with low EMI requirements or noise immunity
requirements. The LVDS standard specifies a differential output voltage
range of 0.25 V × VOD ≤ 0.45 V. The LVDS standard does not require an
input reference voltage, however, it does require a 100-Ω termination
resistor between the two signals at the input buffer. Stratix devices
include an optional differential termination resistor within the device. See
Section I, Stratix Device Family Data Sheet of the Stratix Device Handbook,
Volume 1 for the LVDS parameters.
HyperTransport Technology
The HyperTransport technology I/O standard is a differential highspeed, high-performance I/O interface standard requiring a 2.5-V
VCCIO. This standard is used in applications such as high-performance
networking, telecommunications, embedded systems, consumer
electronics, and Internet connectivity devices. The HyperTransport
technology I/O standard is a point-to-point standard in which each
HyperTransport technology bus consists of two point-to-point
unidirectional links. Each link is 2 to 32 bits. See the Stratix Device Family
Data Sheet section of the Stratix Device Handbook, Volume 1 for the
HyperTransport parameters.
LVPECL
The LVPECL I/O standard is a differential interface standard requiring a
3.3-V VCCIO. The standard is used in applications involving video
graphics, telecommunications, data communications, and clock
distribution. The high-speed, low-voltage swing LVPECL I/O standard
uses a positive power supply and is similar to LVDS, however, LVPECL
has a larger differential output voltage swing than LVDS. See the Stratix
Device Family Data Sheet section of the Stratix Device Handbook, Volume 1
for the LVPECL signaling characteristics.
5–4
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
PCML
The PCML I/O standard is a differential high-speed, low-power I/O
interface standard used in applications such as networking and
telecommunications. The standard requires a 3.3-V VCCIO. The PCML I/O
standard achieves better performance and consumes less power than the
LVPECL I/O standard. The PCML standard is similar to LVPECL, but
PCML has a reduced voltage swing, which allows for a faster switching
time and lower power consumption.See the Stratix Device Family Data
Sheet section of the Stratix Device Handbook, Volume 1 for the PCML
signaling characteristics.
Differential HSTL (Class I & II)
The differential HSTL I/O standard is used for applications designed to
operate in the 0.0- to 1.5-V HSTL logic switching range such as quad data
rate (QDR) memory clock interfaces. The differential HSTL specification
is the same as the single ended HSTL specification. The standard specifies
an input voltage range of – 0.3 V ≤ VI ≤ VCCIO + 0.3 V. The differential
HSTL I/O standard is only available on the input and output clocks. See
the Stratix Device Family Data Sheet section of the Stratix Device Handbook,
Volume 1 for the HSTL signaling characteristics
Differential SSTL-2 (Class I & II)
The differential SSTL-2 I/O standard is a 2.5-V memory bus standard
used for applications such as high-speed double data rate (DDR) SDRAM
interfaces. This standard defines the input and output specifications for
devices that operate in the SSTL-2 logic switching range of 0.0 to 2.5 V.
This standard improves operation in conditions where a bus must be
isolated from large stubs. The SSTL-2 standard specifies an input voltage
range of – 0.3 V ≤ VI ≤ VCCIO + 0.3 V. Stratix devices support both input
and output levels. The differential SSTL-2 I/O standard is only available
on output clocks. See the Stratix Device Family Data Sheet section of the
Stratix Device Handbook, Volume 1 for the SSTL-2 signaling characteristics.
Stratix Differential I/O Pin Location
The differential I/O pins are located on the I/O banks on the right and
left side of the Stratix device. Table 5–1 shows the location of the Stratix
device high-speed differential I/O buffers. When the I/O pins in the I/O
banks that support differential I/O standards are not used for high-speed
Altera Corporation
July 2005
5–5
Stratix Device Handbook, Volume 2
Principles of SERDES Operation
signaling, you can configure them as any of the other supported I/O
standards. DDRIO capabilities are detailed in “SERDES Bypass DDR
Differential Signaling” on page 5–42.
Table 5–1. I/O Pin Locations on Each Side of Stratix Devices
Differential Input
Differential Output
DDRIO
Left
Device Side (1)
v
v
v
Right
v
v
v
Top
v
Bottom
v
Note to Table 5–1:
(1)
Principles of
SERDES
Operation
Device sides are relative to pin A1 in the upper left corner of the device (top view
of the package).
Stratix devices support source-synchronous differential signaling up to
840 Mbps. Serial data is transmitted and received along with a lowfrequency clock. The PLL can multiply the incoming low-frequency clock
by a factor of 1 to 10. The SERDES factor J can be 4, 7, 8, or 10 and does not
have to equal the clock multiplication value. ×1 and ×2 operation is also
possible by bypassing the SERDES; it is explained in “SERDES Bypass
DDR Differential Interface Review” on page 5–42.
On the receiver side, the high-frequency clock generated by the PLL shifts
the serial data through a shift register (also called deserializer). The
parallel data is clocked out to the logic array synchronized with the lowfrequency clock. On the transmitter side, the parallel data from the logic
array is first clocked into a parallel-in, serial-out shift register
synchronized with the low-frequency clock and then transmitted out by
the output buffers.
There are four dedicated fast PLLs in EP1S10 to EP1S25 devices, and eight
in EP1S30 to EP1S80 devices. These PLLs are used for the SERDES
operations as well as general-purpose use.
The differential channels and the high-speed PLL layout in Stratix
devices are described in the “Differential I/O Interface & Fast PLLs”
section on page 5–16.
5–6
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Stratix Differential I/O Receiver Operation
You can configure any of the Stratix differential input channels as a
receiver channel (see Figure 5–3). The differential receiver deserializes
the incoming high-speed data. The input shift register continuously
clocks the incoming data on the negative transition of the high-frequency
clock generated by the PLL clock (×W).
The data in the serial shift register is shifted into a parallel register by the
RXLOADEN signal generated by the fast PLL counter circuitry on the third
falling edge of the high-frequency clock. However, you can select which
falling edge of the high frequency clock loads the data into the parallel
register, using the data-realignment circuit. For more information on the
data-realignment circuit, see “Data Realignment Principles of Operation”
on page 5–25.
In normal mode, the enable signal RXLOADEN loads the parallel data into
the next parallel register on the second rising edge of the low-frequency
clock. You can also load data to the parallel register through the
TXLOADEN signal when using the data-realignment circuit.
Figure 5–3 shows the block diagram of a single SERDES receiver channel.
Figure 5–4 shows the timing relationship between the data and clocks in
Stratix devices in ×10 mode. W is the low-frequency multiplier and J is
data parallelization division factor.
Altera Corporation
July 2005
5–7
Stratix Device Handbook, Volume 2
Principles of SERDES Operation
Figure 5–3. Stratix High-Speed Interface Deserialized in ×10 Mode
Receiver Circuit
Serial Shift
Registers
RXIN+
RXIN−
Parallel
Registers
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
×W
RXCLKIN+
RXCLKIN−
Parallel
Registers
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
Stratix
Logic Array
×W/J (1)
Fast RXLOADEN
PLL (2)
TXLOADEN
Notes to Figure 5–3:
(1)
(2)
W = 1, 2, 4, 7, 8, or 10.
J = 4, 7, 8, or 10.
W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, the device uses DDRIO registers.
This figure does not show additional circuitry for clock or data manipulation.
Figure 5–4. Receiver Timing Diagram
Internal ×1 clock
Internal ×10 clock
RXLOADEN
Receiver
data input
n–1
n–0
9
8
7
6
5
4
3
2
1
0
n–1
n–0
9
8
7
6
5
4
3
2
1
0
Internal ×1 clock
Internal ×10 clock
RXLOADEN
Receiver
data input
5–8
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Stratix Differential I/O Transmitter Operation
You can configure any of the Stratix differential output channels as a
transmitter channel. The differential transmitter is used to serialize
outbound parallel data.
The logic array sends parallel data to the SERDES transmitter circuit
when the TXLOADEN signal is asserted. This signal is generated by the
high-speed counter circuitry of the logic array low-frequency clock’s
rising edge. The data is then transferred from the parallel register into the
serial shift register by the TXLOADEN signal on the third rising edge of the
high-frequency clock.
Figure 5–5 shows the block diagram of a single SERDES transmitter
channel and Figure 5–6 shows the timing relationship between the data
and clocks in Stratix devices in ×10 mode. W is the low-frequency
multiplier and J is the data parallelization division factor.
Figure 5–5. Stratix High-Speed Interface Serialized in ×10 Mode
Transmitter Circuit
Stratix
Logic Array
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Parallel
Register
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Serial
Register
TXOUT+
TXOUT−
×W
Fast
PLL
Altera Corporation
July 2005
TXLOADEN
5–9
Stratix Device Handbook, Volume 2
Principles of SERDES Operation
Figure 5–6. Transmitter Timing Diagram
Internal ×1 clock
Internal ×10 clock
TXLOADEN
Receiver
data input
n–1
n–0
9
8
7
6
5
4
3
2
1
0
Transmitter Clock Output
Different applications and protocols call for various clocking schemes.
Some applications require you to center-align the rising or falling clock
edge with the data. Other applications require a divide version of the
transmitted clock, or the clock and data to be at the same high-speed
frequency. The Stratix device transmitter clock output is versatile and
easily programmed for all such applications.
Stratix devices transmit data using the source-synchronous scheme,
where the clock is transmitted along with the serialized data to the
receiving device. Unlike APEXTM 20KE and APEX II devices, Stratix
devices do not have a fixed transmitter clock output pin. The Altera®
Quartus II software generates the transmitter clock output by using a fast
clock to drive a transmitter dataout channel. Therefore, you can place
the transmitter clock pair close to the data channels, reducing clock-todata skew and increasing system margins. This approach is more flexible,
as any channel can drive a clock, not just specially designated clock pins.
Divided-Down Transmitter Clock Output
You can divide down the high-frequency clock by 2, 4, 8, or 10, depending
on the system requirements. The various options allow Stratix devices to
accommodate many different types of protocols. The divided-down clock
is generated by an additional transmitting data channel.
5–10
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Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Table 5–2 shows the divided-down version of the high-frequency clock
and the selected serialization factor J (described in pervious sections). The
Quartus II software automatically generates the data input to the
additional transmitter data channel.
Table 5–2. Differential Transmitter Output Clock Division
J
Data Input
Output Clock Divided By (1)
4
1010
2
4
0011
4
8
10101010
2
8
00110011
4
8
11000011
8
10
1010101010
2
10
1110000011
10
Note to Table 5–2:
(1)
This value is usually referred to as B.
Center-Aligned Transmitter Clock Output
A negative-edge-triggered D flipflop (DFF) register is located between
the serial register of each data channel and its output buffer, as show in
Figure 5–7. The negative-edge-triggered DFF register is used when
center-aligned data is required. For center alignment, the DFF only shifts
the output from the channel used as the transmitter clock out. The
transmitter data channels bypass the negative-edge DFF. When you use
the DFF register, the data is transmitted at the negative edge of the
multiplied clock. This delays the transmitted clock output relative to the
data channels by half the multiplied clock cycle. This is used for
HyperTransport technology, but can also be used for any interface
requiring center alignment.
Altera Corporation
July 2005
5–11
Stratix Device Handbook, Volume 2
Principles of SERDES Operation
Figure 5–7. Stratix Programmable Transmitter Clock
Transmitter Circuit
Stratix
Logic Array
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Parallel
Register
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Serial
Register
TXOUT+
TXOUT−
×W
Fast
PLL
TXLOADEN
SDR Transmitter Clock Output
You can route the high-frequency clock internally generated by the PLL
out as a transmitter clock output on any of the differential channels. The
high-frequency clock output allows Stratix devices to support
applications that require a 1-to-1 relationship between the clock and data.
The path of the high-speed clock is shown in Figure 5–8. A programmable
inverter allows you to drive the signal out on either the negative edge of
the clock or 180º out of phase with the streaming data.
5–12
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–8. High-Speed 1-to-1 Transmitter Clock Output
Transmitter Circuit
Stratix
Logic Array
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Parallel
Register
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Serial
Register
Inverter
TXOUT+
TXOUT−
×W
Fast
PLL (1)
TXLOADEN
Note to Figure 5–8:
(1)
This figure does not show additional circuitry for clock or data manipulation.
Using SERDES
to Implement
DDR
Some designs require a 2-to-1 data-to-clock ratio. These systems are
usually based on Rapid I/O, SPI-4 Phase 2 (POS_PHY Level 4), or
HyperTransport interfaces, and support various data rates. Stratix
devices meet this requirement for such applications by providing a
variable clock division factor. The SERDES clock division factor is set to 2
for double data rate (DDR).
An additional differential channel (as described in “Transmitter Clock
Output” on page 5–10) is automatically configured to produce the
transmitter clock output signal with half the frequency of the data.
For example, when a system is required to transmit 6.4 Gbps with a
2-to-1 clock-to-data ratio, program the SERDES with eight high-speed
channels running at 800 Mbps each. When you set the output clock
division factor (2 for this example), the Quartus II software automatically
assigns a ninth channel as the transmitter clock output. You can edge- or
center-align the transmitter clock by selecting the default PLL phase or
selecting the negative-edge transmitter clock output. On the receiver side,
the clock signal is connected to the receiver PLL's clock.
The multiplication factor W is also calculated automatically. The data rate
divides by the input clock frequency to calculate the W factor. The
deserialization factor (J) may be 4, 7, 8, or 10.
Altera Corporation
July 2005
5–13
Stratix Device Handbook, Volume 2
Using SERDES to Implement SDR
Figure 5–9 shows a DDR clock-to-data timing relationship with the clock
center-aligned with respect to data. Figure 5–10 shows the connection
between the receiver and transmitter circuits.
Figure 5–9. DDR Clock-to-Data Relationship
inclock
DDR
XX
B0
A0
B1
A1
B2
A2
B3
A3
Figure 5–10. DDR Receiver & Transmitter Circuit Connection
Stratix SERDES DDR Receiver
rx_d[0]
Channel
0
Serial-to-Parallel
Register
Stratix SERDES DDR Transmitter
Parallel
Register
8
8
Parallel
Register
Parallel-to-Serial
Register
Parallel
Register
Parallel-to-Serial
Register
Parallel
Register
Parallel-to-Serial
Register
Channel
0
tx_d[0]
data rate = 800 Mbps
Stratix
Logic
Array
rx_d[15]
data rate = 800 Mbps
Channel
15
Serial-to-Parallel
Register
Parallel
Register
rxclk
LVDS PLL
8
8
input clock × W
400 MHz
8
rxloadena
Channel
15
Channel
16
÷2
txclk_out
800 Mbps
txclk_out
400 MHz
txloaden
LVDS PLL
input clock × W
txclk_in
100 MHz
Using SERDES
to Implement
SDR
Stratix devices support systems based on single data rate (SDR)
operations applications by allowing you to directly transmit out the
multiplied clock (as described in “SDR Transmitter Clock Output” on
page 5–12). These systems are usually based on Utopia-4, SFI-4, or XSBI
interfaces, and support various data rates.
An additional differential channel is automatically configured to produce
the transmitter clock output signal and is transmitted along with the data.
For example, when a system is required to transmit 10 Gbps with a 1-to1 clock-to-data ratio, program the SERDES with sixteen high-speed
channels running at 624 Mbps each. The Quartus II software
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July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
automatically assigns a seventeenth channel as the transmitter clock
output. You can edge- or center-align the transmitter clock output by
selecting the default PLL phase or selecting the 90° phase of the PLL
output. On the receiver side, the clock signal is connected to the receiver
PLL's clock input, and you can assign identical clock-to-data alignment.
The multiplication factor W is calculated automatically. The data rate is
dividing by the input clock frequency to calculate the W factor. The
deserialization factor J may be 4, 7, 8, or 10.
Figure 5–11 shows an SDR clock-to-data timing relationship, with clock
center aligned with respect to data. Figure 5–12 shows the connection
between the receiver and transmitter circuits.
Figure 5–11. SDR Clock-to-Data Relationship
inclock
SDR
XX
B0
B1
B2
B3
Figure 5–12. SDR Receiver & Transmitter Circuit Connection
Stratix SERDES SDR Receiver
rx_d[0]
Channel
0
Serial-to-Parallel
Register
Stratix SERDES SDR Transmitter
Parallel
Register
8
8
Parallel
Register
Parallel-to-Serial
Register
Parallel
Register
Parallel-to-Serial
Register
Channel
0
tx_d[0]
data rate = 624 Mbps
Stratix
Logic
Array
rx_d[15]
data rate = 624 Mbps
Channel
15
Serial-to-Parallel
Register
Parallel
Register
8
8
input clock × W
Channel
15
Channel
16
txloaden
tx_d[15]
txclk_out
624 MHz
rxclk
624 MHz
LVDS PLL
rxloaden
LVDS PLL
input clock × W
txclk_in
624 MHz
Altera Corporation
July 2005
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Stratix Device Handbook, Volume 2
Differential I/O Interface & Fast PLLs
Differential I/O
Interface & Fast
PLLs
Stratix devices provide 16 dedicated global clocks, 8 dedicated fast
regional I/O pins, and up to 16 regional clocks (four per device quadrant)
that are fed from the dedicated global clock pins or PLL outputs. The 16
dedicated global clocks are driven either by global clock input pins that
support all I/O standards or from enhanced and fast PLL outputs.
Stratix devices use the fast PLLs to implement clock multiplication and
division to support the SERDES circuitry. The input clock is either
multiplied by the W feedback factor and/or divided by the J factor. The
resulting clocks are distributed to SERDES, local, or global clock lines.
Fast PLLs are placed in the center of the left and right sides for EP1S10 to
EP1S25 devices. For EP1S30 to EP1S80 devices, fast PLLs are placed in the
center of the left and right sides, as well as the device corners (see
Figure 5–13). These fast PLLs drive a dedicated clock network to the
SERDES in the rows above and below or top and bottom of the device as
shown in Figure 5–13.
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July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–13. Stratix Fast PLL Positions & Clock Naming Convention Note (1)
CLK[15..12]
5
11
FPLLCLK0
7
10
FPLLCLK3
CLK[3..0]
1
2
4
3
CLK[11..8]
8
9
FPLLCLK2
PLLs
FPLLCLK1
6
12
CLK[7..4]
Notes to Figure 5–13:
(1)
(2)
Dedicated clock input pins on the right and left sides do not support PCI or PCI-X 1.0.
PLLs 7, 8, 9, and 10 are not available on the EP1S30 device in the 780-pin FineLine BGA® package.
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July 2005
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Stratix Device Handbook, Volume 2
Differential I/O Interface & Fast PLLs
Clock Input & Fast PLL Output Relationship
Table 5–3 summarizes the PLL interface to the input clocks and the enable
signal (ENA). Table 5–4 summarizes the clock networks each fast PLL can
connect to across all Stratix family devices.
Table 5–3. Fast PLL Clock Inputs (Including Feedback Clocks) & Enables Note (1)
All Stratix Devices
EP1S30 to EP1S80 Devices Only
Input Pin
PLL 1
CLK0 (2)
v
CLK1
v
PLL 2
PLL 3
PLL 4
PLL 7
PLL 8
PLL 9
PLL 10
v (3)
CLK2 (2)
v
CLK3
v
v (3)
CLK4
CLK5
CLK6
CLK7
CLK8
v
CLK9 (2)
v
v (3)
CLK10
v
CLK11 (2)
v
v (3)
CLK12
CLK13
CLK14
CLK15
v
ENA
v
FPLL7CLK
FPLL8CLK
FPLL9CLK
FPLL10CLK
v
v
v
v
v
v
v
v
v
v
Notes to Table 5–3:
(1)
(2)
(3)
PLLs 5, 6, 11, and 12 are not fast PLLs.
Clock pins CLK0, CLK2, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential on-chip
termination.
Either a FPLLCLK pin or a CLK pin can drive the corner fast PLLs (PLL7, PLL8, PLL9, and PLL10) when used for
general purpose. CLK pins cannot drive these fast PLLs in high-speed differential I/O mode.
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High-Speed Differential I/O Interfaces in Stratix Devices
Table 5–4. Fast PLL Relationship with Stratix Clock Networks (Part 1 of 2) Notes (1), (2)
All Stratix Devices
EP1S30 to EP1S80 Devices Only
Output Signal
PLL 1
GCLK0
v
GCLK1
v
PLL 2
GCLK2
v
GCLK3
v
PLL 3
GCLK4
v
GCLK9
v
PLL 4
GCLK10
v
GCLK11
v
PLL 7
PLL 8
RCLK1
v
v
v
RCLK2
v
v
v
RCLK3
v
v
v
RCLK4
v
v
v
PLL 9
PLL 10
RCLK9
v
v
v
RCLK10
v
v
v
RCLK11
v
v
v
RCLK12
v
v
v
DIFFIOCLK1
v
DIFFIOCLK2
v
DIFFIOCLK3
v
DIFFIOCLK4
v
DIFFIOCLK5
v
DIFFIOCLK6
v
DIFFIOCLK7
v
DIFFIOCLK8
v
DIFFIOCLK9
v
DIFFIOCLK10
v
DIFFIOCLK11
v
DIFFIOCLK12
v
DIFFIOCLK13
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July 2005
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Stratix Device Handbook, Volume 2
Differential I/O Interface & Fast PLLs
Table 5–4. Fast PLL Relationship with Stratix Clock Networks (Part 2 of 2) Notes (1), (2)
All Stratix Devices
EP1S30 to EP1S80 Devices Only
Output Signal
PLL 1
PLL 2
PLL 3
PLL 4
PLL 7
PLL 8
PLL 9
PLL 10
v
DIFFIOCLK14
DIFFIOCLK15
v
DIFFIOCLK16
v
Notes to Table 5–4:
(1)
(2)
PLLs 5, 6, 11, and 12 are not fast PLLs.
The input clock for PLLs used to clock receiver the rx_inclock port on the altlvds_rx megafunction must be
driven by a dedicated clock pin (CLK[3..0] and CLK[8..11]) or the corner pins that clock the corner PLLs
(FPLL[10..7]CLK).
Fast PLL Specifications
You can drive the fast PLLs by an external pin or any one of the sectional
clocks [21..0]. You can connect the clock input directly to local or global
clock lines, as shown in Figure 5–14. You cannot use the sectional-clock
inputs to the fast PLL’s input multiplexer for the receiver PLL. You can
only use the sectional clock inputs in the transmitter only mode or as a
general purpose PLL.
5–20
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July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–14. Fast PLL Block Diagram
Post-Scale
Counters
DIFFIOCLK1 (1)
÷k
Regional clock
TXLOADEN (2)
VCO Phase Selection
Selectable at each PLL
Output Port
RXLOADEN (2)
÷v
Global or
regional clock
Clock Input
Phase
Frequency
Detector
Charge
Pump
8
Loop
Filter
Regional clock
DIFFIOCLK2 (1)
VCO
÷l
Global or
regional clock
rxclkin
÷m
Notes to Figure 5–14:
(1)
(2)
In high-speed differential I/O mode, the high-speed PLL clock feeds the SERDES. Stratix devices only support one
rate of data transfer per fast PLL in high-speed differential I/O mode.
Control signal for high-speed differential I/O SERDES.
You can multiply the input clock by a factor of 1 to 16. The multiplied
clock is used for high-speed serialization or deserialization operations.
Fast PLL specifications are shown in the Stratix Device Family Data Sheet
section of the Stratix Device Handbook, Volume 1. The voltage controlled
oscillators (VCOs) are designed to operate within the frequency range of
300 to 840 MHz, to provide data rates of up to 840 Mbps.
High-Speed Phase Adjust
There are eight phases of the multiplied clock at the PLL output, each
delayed by 45° from the previous clock and synchronized with the
original clock. The three multiplexers (shown in Figure 5–14) select one of
the delayed, multiplied clocks. The PLL output drives the three counters
k, v, and l. You can program the three individual post scale counters (k, v,
and l) independently for division ratio or phase. The selected PLL output
is used for the serialization or deserialization process in SERDES.
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July 2005
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Stratix Device Handbook, Volume 2
Differential I/O Interface & Fast PLLs
Counter Circuitry
The multiplied clocks bypass the counter taps k and v to directly feed the
SERDES serial registers. These two taps also feed to the quadrant local
clock network and the dedicated RXLOADENA or TXLOADENA pins, as
shown in Figure 5–15. Both k and v are utilized simultaneously during the
data-realignment procedure. When the design does not use the data
realignment, both TXLOADEN and RXLOADEN pins use a single counter.
Figure 5–15. Fast PLL Connection to Logic Array
Counter Circuitry
Post-Scale
Counters
VCO Phase Selection
Selectable at each PLL
Output Port
÷k
CLK1 SERDES
Circuitry
×1 CLK1 to logic array
or local clocks
TXLOADEN
RXLOADEN
8
÷v
PLL Output
Clock
Distribution
Circuitry
×1 CLK2 to logic array
or local clocks
CLK2 SERDES
Circuitry
÷l
Regional clock
clkin
The Stratix device fast PLL has another GCLK connection for generalpurpose applications. The third tap l feeds the quadrant local clock as
well as the global clock network. You can use the l counter's multiplexer
for applications requiring the device to connect the incoming clock
directly to the local or global clocks. You can program the multiplexer to
connect the RXCLKIN signal directly to the local or global clock lines.
Figure 5–15 shows the connection between the incoming clock, the l tap,
and the local or global clock lines.
The differential clock selection is made per differential bank. Since the
length of the clock tree limits the performance, each fast PLL should drive
only one differential bank.
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High-Speed Differential I/O Interfaces in Stratix Devices
Fast PLL SERDES Channel Support
The Quartus II MegaWizard Plug-In Manager only allows you to
implement up to 20 receiver or 20 transmitter channels for each fast PLL.
These channels operate at up to 840 Mbps. For more information on
implementing more than 20 channels, see “Fast PLLs” on page 5–52. The
receiver and transmitter channels are interleaved such that each I/O bank
on the left and right side of the device has one receiver channel and one
transmitter channel per row. Figure 5–16 shows the fast PLL and channel
layout in EP1S10, EP1S20, and EP1S25 devices. Figure 5–17 shows the fast
PLL and channel layout in EP1S30 to EP1S80 devices.
f
For more the number of channels in each device, see Tables 5–10 through
5–14.
Figure 5–16. Fast PLL & Channel Layout in EP1S10, EP1S20 & EP1S25 Devices Note (1)
Up to 20 Receiver and
Transmitter Channels (2)
Transmitter
Up to 20 Receiver and
Transmitter Channels (2)
Transmitter
Receiver
Receiver
CLKIN
Fast
PLL 1
CLKIN
Fast
PLL 2
(3)
Transmitter
Receiver
Up to 20 Receiver and
Transmitter Channels (2)
Fast
PLL 4
CLKIN
Fast
PLL 3
CLKIN
(3)
Transmitter
Receiver
Up to 20 Receiver and
Transmitter Channels (2)
Notes to Figure 5–16:
(1)
(2)
(3)
Wire-bond packages only support up to 624 Mbps until characterization shows otherwise.
See Tables 5–10 through 5–14 for the exact number of channels each package and device density supports.
There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of
its bank quadrant (e.g., if PLL 2 clocks PLL 1’s channel region), those clocked channels support up to 840 Mbps.
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July 2005
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Stratix Device Handbook, Volume 2
Differential I/O Interface & Fast PLLs
Figure 5–17. Fast PLL & Channel Layout in EP1S30 to EP1S80 Devices Note (1)
FPLL7CLK
Fast
PLL 7
Fast
PLL 10
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
Transmitter
FPLL10CLK
Transmitter
Receiver
Receiver
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
Transmitter
Transmitter
Receiver
CLKIN
CLKIN
Receiver
Fast
PLL 1
(3)
(3)
Fast
PLL 2
Fast
PLL 4
CLKIN
Fast
PLL 3
CLKIN
Transmitter
Transmitter
Receiver
Receiver
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
Transmitter
Transmitter
Receiver
FPLL8CLK
Receiver
Fast
PLL 8
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
Fast
PLL 9
FPLL9CLK
Notes to Figure 5–17:
(1)
(2)
(3)
Wire-bond packages only support up to 624-Mbps until characterization shows otherwise.
See Tables 5–10 through 5–14 for the exact number of channels each package and device density supports.
There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of
its bank quadrant (e.g., if PLL 2 clocks PLL 1’s channel region), those clocked channels support up to 840 Mbps.
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High-Speed Differential I/O Interfaces in Stratix Devices
Advanced Clear & Enable Control
There are several control signals for clearing and enabling PLLs and their
outputs. You can use these signals to control PLL resynchronization and
to gate PLL output clocks for low-power applications.
The PLLENABLE pin is a dedicated pin that enables and disables Stratix
device enhanced and fast PLLs. When the PLLENABLE pin is low, the
clock output ports are driven by GND and all the PLLs go out of lock.
When the PLLENABLE pin goes high again, the PLLs relock and
resynchronize to the input clocks.
The reset signals are reset/resynchronization inputs for each enhanced
PLL. Stratix devices can drive these input signals from an input pin or
from LEs. When driven high, the PLL counters reset, clearing the PLL
output and placing the PLL out of lock. When driven low again, the PLL
resynchronizes to its input as it relocks.
Receiver Data
Realignment
Most systems using serial differential I/O data transmission require a
certain data-realignment circuit. Stratix devices contain embedded datarealignment circuitry. While normal I/O operation guarantees that data
is captured, it does not guarantee the parallelization boundary, as this
point is randomly determined based on the power-up of both
communicating devices. The data-realignment circuitry corrects for bit
misalignments by shifting, or delaying, data bits.
Data Realignment Principles of Operation
Stratix devices use a realignment and clock distribution circuitry
(described in “Counter Circuitry” on page 5–22) for data realignment.
Set the internal rx_data_align node end high to assert the datarealignment circuitry. When this node is switched from a low to a high
state, the realignment circuitry is activated and the data is delayed by one
bit. To ensure the rising edge of the rx_data_align node end is latched
into the PLL, the rx_data_align node end should stay high for at least
two low-frequency clock cycles.
An external circuit or an internal custom-made state machine using LEs
can generate the signal to pull the rx_data_align node end to a high
state.
When the data realignment circuitry is activated, it generates an internal
pulse Sync S1 or Sync S2 that disables one of the two counters used for the
SERDES operation (described in “Counter Circuitry” on page 5–22). One
counter is disabled for one high-frequency clock cycle, delaying the
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July 2005
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Stratix Device Handbook, Volume 2
Receiver Data Realignment
RXLOADEN signal and dropping the first incoming bit of the serial input
data stream located in the first serial register of the SERDES circuitry
(shown in Figure 5–3 on page 5–8).
Figure 5–18 shows the function-timing diagram of a Stratix SERDES in
normal ×8 mode, and Figure 5–19 shows the function-timing diagrams of
a Stratix SERDES when data realignment is used.
Figure 5–18. SERDES Function Timing Diagram in Normal Operation
×8 clock
Serial data
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
×1 clock
PD7
D2
D2
D2
PD6
D3
D3
D3
PD5
D4
D4
D4
PD4
D5
D5
D5
PD3
D6
D6
D6
PD2
D7
D7
D7
PD1
D0
D0
D0
PD0
D1
D1
D1
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July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–19. SERDES Function Timing Diagram with Data-Realignment Operation
×8 clock
Serial data
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
×1 clock
PD7
D2
D3
D3
PD6
D3
D4
D4
PD5
D4
D5
D5
PD4
D5
D6
D6
PD3
D6
D7
D7
PD2
D7
D0
D0
PD1
D0
D1
D1
PD0
D1
D2
D2
Generating the TXLOADEN Signal
The TXLOADEN signal controls the transfer of data between the SERDES
circuitry and the logic array when data realignment is used. To prevent
the interruption of the TXLOADEN signal during data realignment, both k
and v counter are used.
In normal operation the TXLOADEN signal is generated by the k counter.
However, during the data-realignment operation this signal is generated
by either counter. When the k counter is used for realignment, the
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July 2005
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Stratix Device Handbook, Volume 2
Receiver Data Realignment
TXLOADEN signal is generated by the v counter, and when the v counter
is used for realignment, the TXLOADEN signal is generated by the k
counter, as shown in Figure 5–20.
Figure 5–20. Realignment Circuit TXLOADEN Signal Control Note (1)
Counter Circuitry
Clock
Distribution
Circuitry
CLK1 LVDS
Circuitry
×1 CLK1 to logic array
÷k
TXLOADEN
Sync S1
Data
Realignment
Circuit
Realignment CLK
8
PLL Output
SYNC
Realignment CLK
Data
Realignment
Circuit
Sync S2
RXLOADEN
÷v
×1 CLK2 to logic array
CLK2 LVDS
Circuitry
÷l
GCLK/LCLK
Note to Figure 5–20:
(1)
This figure does not show additional realignment circuitry.
Realignment Implementation
The realignment signal (SYNC) is used for data realignment and
reframing. An external pin (RX_DATA_ALIGN) or an internal signal
controls the rx_data_align node end. When the rx_data_align
node end is asserted high for at least two low-frequency clock cycles, the
RXLOADEN signal is delayed by one high-frequency clock period and the
parallel bits shift by one bit. Figure 5–21 shows the timing relationship
between the high-frequency clock, the RXLOADEN signal, and the parallel
data.
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July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–21. Realignment by rx_data_align Node End
10× clock
1× clock
SYNC
rxloaden
6
datain
receiver A
receiver B
5
7
6
8
7
9
8
0
9
1
0
2
1
3
2
0123456789
4
3
5
4
6
5
7
6
8
7
9
8
0
9
1
0
2
1
0123456789
3
2
4
3
5
4
6
5
7
6
8
7
9
8
0
9
1
0
1234567890
2
1
3
2
4
3
4
1234567890
A state machine can generate the realignment signal to control the
alignment procedure. Figure 5–22 shows the connection between the
realignment signal and the rx_data_align node end.
Figure 5–22. SYNC Signal Path to Realignment Circuit
Stratix Logic Array
Receiver Circuit
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
Parallel
Register
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
Register
Array
SYNC Out
10
Pattern
Detection
State Machine
Hold
Register
TXLOADEN
×1
×W/J
Realignment
Circuit
SYNC
To guarantee that the rx_data_align signal generated by a user state
machine is latched correctly by the counters, the user circuit must meet
certain requirements.
■
Altera Corporation
July 2005
The design must include an input synchronizing register to ensure
that data is synchronized to the ×1 clock.
5–29
Stratix Device Handbook, Volume 2
Source-Synchronous Timing Budget
■
■
■
■
SourceSynchronous
Timing Budget
After the pattern detection state machine, use another synchronizing
register to capture the generated SYNC signal and synchronize it to
the ×1 clock.
Since the skew in the path from the output of this synchronizing
register to the PLL is undefined, the state machine must generate a
pulse that is high for two ×1 clock periods.
Since the SYNC generator circuitry only generates a single fast clock
period pulse for each SYNC pulse, you cannot generate additional
SYNC pulses until the comparator signal is reset low.
To guarantee the pattern detection state machine does not incorrectly
generate multiple SYNC pulses to shift a single bit, the state machine
must hold the SYNC signal low for at least three ×1 clock periods
between pulses.
This section discusses the timing budget, waveforms, and specifications
for source-synchronous signaling in Stratix devices. LVDS, LVPECL,
PCML, and HyperTransport I/O standards enable high-speed data
transmission. This high data-transmission rate results in better overall
system performance. To take advantage of fast system performance, you
must understand how to analyze timing for these high-speed signals.
Timing analysis for the differential block is different from traditional
synchronous timing analysis techniques.
Rather than focusing on clock-to-output and setup times, sourcesynchronous timing analysis is based on the skew between the data and
the clock signals. High-speed differential data transmission requires you
to use timing parameters provided by IC vendors and to consider board
skew, cable skew, and clock jitter. This section defines the sourcesynchronous differential data orientation timing parameters, and timing
budget definitions for Stratix devices, and explains how to use these
timing parameters to determine a design's maximum performance.
Differential Data Orientation
There is a set relationship between an external clock and the incoming
data. For operation at 840 Mbps and W = 10, the external clock is
multiplied by 10 and phase-aligned by the PLL to coincide with the
sampling window of each data bit. The third falling edge of highfrequency clock is used to strobe the incoming high-speed data.
Therefore, the first two bits belong to the previous cycle. Figure 5–23
shows the data bit orientation of the ×10 mode as defined in the
Quartus II software.
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July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–23. Bit Orientation in the Quartus II Software
inclock/outclock
10 LVDS Bits
MSB
data in
n-1
n-0
9
8
7
6
5
4
LSB
3
2
1
0
high-frequency clock
Differential I/O Bit Position
Data synchronization is necessary for successful data transmission at
high frequencies. Figure 5–24 shows the data bit orientation for a receiver
channel operating in ×8 mode. Similar positioning exists for the most
significant bits (MSBs) and least significant bits (LSBs) after
deserialization, as listed in Table 5–5.
Figure 5–24. Bit Order for One Channel of Differential Data
inclock/outclock
Previous Cycle
Data in/
Data out
Current Cycle
D7
MSB
D6
D5
0
0
D4
D3
Next Cycle
D2
D1
D0
LSB
1
0
Example: Sending the Data 10010110
Previous Cycle
Data in/
Data out
Current Cycle
1
MSB
Altera Corporation
July 2005
1
0
Next Cycle
1
LSB
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Source-Synchronous Timing Budget
Table 5–5 shows the conventions for differential bit naming for
18 differential channels. However, the MSB and LSB are increased with
the number of channels used in a system.
Table 5–5. LVDS Bit Naming
Receiver Data Channel
Number
Internal 8-Bit Parallel Data
MSB Position
LSB Position
1
7
0
2
15
8
3
23
16
4
31
24
5
39
32
6
47
40
7
55
48
8
63
56
9
71
64
10
79
72
11
87
80
12
95
88
13
103
96
14
111
104
15
119
112
16
127
120
17
135
128
18
143
136
Timing Definition
The specifications used to define high-speed timing are described in
Table 5–6.
Table 5–6. High-Speed Timing Specifications & Terminology (Part 1 of 2)
High-Speed Timing Specification
Terminology
tC
High-speed receiver/transmitter input and output clock period.
fHSCLK
High-speed receiver/transmitter input and output clock frequency.
tRISE
Low-to-high transmission time.
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July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Table 5–6. High-Speed Timing Specifications & Terminology (Part 2 of 2)
High-Speed Timing Specification
Terminology
tFALL
High-to-low transmission time.
Timing unit interval (TUI)
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = tC/w).
fHSDR
Maximum LVDS data transfer rate (fHSDR = 1/TUI).
Channel-to-channel skew (TCCS)
The timing difference between the fastest and slowest output edges,
including tCO variation and clock skew. The clock is included in the TCCS
measurement.
Sampling window (SW)
The period of time during which the data must be valid in order for you to
capture it correctly. The setup and hold times determine the ideal strobe
position within the sampling window.
SW = tSW (max) – tSW (min).
Input jitter (peak-to-peak)
Peak-to-peak input jitter on high-speed PLLs.
Output jitter (peak-to-peak)
Peak-to-peak output jitter on high-speed PLLs.
tDUTY
Duty cycle on high-speed transmitter output clock.
tLOCK
Lock time for high-speed transmitter and receiver PLLs.
Altera Corporation
July 2005
5–33
Stratix Device Handbook, Volume 2
Table 5–7. High-Speed I/O Specifications for Flip-Chip Packages (Part 1 of 3) Notes (1), (2)
-5 Speed Grade
Symbol
fHSDR Device
operation
(LVDS, LVPECL,
HyperTransport
technology)
5–34
Stratix Device Handbook, Volume 2
fHSCLK (Clock
frequency)
(PCML)
fHSCLK = fHSDR / W
-7 Speed Grade
-8 Speed Grade
Unit
Min
fHSCLK (Clock
frequency)
(LVDS, LVPECL,
HyperTransport
technology)
fHSCLK = fHSDR / W
-6 Speed Grade
Conditions
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
W = 4 to 30
10
210
10
210
10
156
10
115.5
MHz
W = 2 (Serdes
bypass)
50
231
50
231
50
231
50
231
MHz
W = 2 (Serdes used)
150
420
150
420
150
312
150
231
MHz
W = 1 (Serdes
bypass)
100
462
100
462
100
462
100
462
MHz
W = 1 (Serdes used)
300
717
300
717
300
624
300
462
MHz
J = 10
300
840
300
840
300
640
300
462
Mbps
J=8
300
840
300
840
300
640
300
462
Mbps
J=7
300
840
300
840
300
640
300
462
Mbps
J=4
300
840
300
840
300
640
300
462
Mbps
J=2
100
462
100
462
100
640
100
462
Mbps
J = 1 (LVDS and
LVPECL only)
100
462
100
462
100
640
100
462
Mbps
W = 4 to 30 (Serdes
used)
10
100
10
100
10
77.75
10
77.75
MHz
W = 2 (Serdes
bypass)
50
200
50
200
50
150
50
150
MHz
W = 2 (Serdes used)
150
200
150
200
150
155.5
150
155.5
MHz
W = 1 (Serdes
bypass)
100
250
100
250
100
200
100
200
MHz
W = 1 (Serdes used)
300
400
300
400
300
311
300
311
MHz
Source-Synchronous Timing Budget
Altera Corporation
July 2005
Tables 5–7 and 5–8 show the high-speed I/O timing for Stratix devices
-5 Speed Grade
Symbol
-7 Speed Grade
-8 Speed Grade
Unit
Min
fHSDR Device
operation (PCML)
-6 Speed Grade
Conditions
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
J = 10
300
400
300
400
300
311
300
311
Mbps
J=8
300
400
300
400
300
311
300
311
Mbps
J=7
300
400
300
400
300
311
300
311
Mbps
J=4
300
400
300
400
300
311
300
311
Mbps
J=2
100
400
100
400
100
300
100
300
Mbps
J=1
100
250
100
250
100
200
100
200
Mbps
300
ps
TCCS
All
SW
PCML (J = 4, 7, 8,
10)
200
750
200
300
750
800
800
ps
5–35
Stratix Device Handbook, Volume 2
PCML (J = 2)
900
900
1,200
1,200
ps
PCML (J = 1)
1,500
1,500
1,700
1,700
ps
LVDS and LVPECL
(J = 1)
500
500
550
550
ps
LVDS, LVPECL,
HyperTransport
technology (J = 2
through 10)
440
440
500
500
ps
Input jitter tolerance All
(peak-to-peak)
250
250
250
250
ps
Output jitter (peakto-peak)
All
160
160
200
200
ps
Output tRISE
LVDS
80
110
120
80
110
120
80
110
120
80
110
120
ps
HyperTransport
technology
110
170
200
110
170
200
120
170
200
120
170
200
ps
LVPECL
90
130
150
90
130
150
100
135
150
100
135
150
ps
PCML
80
110
135
80
110
135
80
110
135
80
110
135
ps
Source-Synchronous Timing Budget
Altera Corporation
July 2005
Table 5–7. High-Speed I/O Specifications for Flip-Chip Packages (Part 2 of 3) Notes (1), (2)
-5 Speed Grade
Symbol
Output tFALL
tDUTY
-7 Speed Grade
-8 Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
LVDS
80
110
120
80
110
120
80
110
120
80
110
120
ps
HyperTransport
technology
110
170
200
110
170
200
110
170
200
110
170
200
ps
LVPECL
90
130
160
90
130
160
100
135
160
100
135
160
ps
PCML
105
140
175
105
140
175
110
145
175
110
145
175
ps
LVDS (J = 2 through
10)
47.5
50
52.5
47.5
50
52.5
47.5
50
52.5
47.5
50
52.5
%
45
50
55
45
50
55
45
50
55
45
50
55
%
100
μs
LVDS (J =1) and
LVPECL, PCML,
HyperTransport
technology
tLOCK
-6 Speed Grade
Conditions
All
100
100
100
Notes to Table 5–7:
(1)
(2)
When J = 4, 7, 8, and 10, the SERDES block is used.
When J = 2 or J = 1, the SERDES is bypassed.
Table 5–8. High-Speed I/O Specifications for Wire-Bond Packages (Part 1 of 3)
-6 Speed Grade
Symbol
-8 Speed Grade
Unit
Min
Altera Corporation
July 2005
fHSCLK (Clock frequency)
(LVDS,LVPECL, HyperTransport
technology)
fHSCLK = fHSDR / W
-7 Speed Grade
Conditions
W = 4 to 30 (Serdes used)
10
Typ
Max
Min
156
Typ
Max
Min
Typ
Max
10
115.5
10
115.5
MHz
W = 2 (Serdes bypass)
50
231
50
231
50
231
MHz
W = 2 (Serdes used)
150
312
150
231
150
231
MHz
W = 1 (Serdes bypass)
100
311
100
270
100
270
MHz
W = 1 (Serdes used)
300
624
300
462
300
462
MHz
Source-Synchronous Timing Budget
5–36
Stratix Device Handbook, Volume 2
Table 5–7. High-Speed I/O Specifications for Flip-Chip Packages (Part 3 of 3) Notes (1), (2)
-6 Speed Grade
Symbol
fH S C L K (Clock frequency)
(PCML)
fHSCLK = fHSDR / W
Device operation, fH S D R
(PCML)
-8 Speed Grade
Unit
Min
fHSDR Device operation,
(LVDS,LVPECL, HyperTransport
technology)
-7 Speed Grade
Conditions
Typ
Max
Min
Typ
Max
Min
Typ
Max
J = 10
300
624
300
462
300
462
Mbps
J=8
300
624
300
462
300
462
Mbps
J=7
300
624
300
462
300
462
Mbps
J=4
300
624
300
462
300
462
Mbps
J=2
100
462
100
462
100
462
Mbps
J = 1 (LVDS and LVPECL only)
100
311
100
270
100
270
Mbps
W = 4 to 30 (Serdes used)
10
77.75
W = 2 (Serdes bypass)
50
150
W = 2 (Serdes used)
150
155.5
W = 1 (Serdes bypass)
100
200
W = 1 (Serdes used)
300
311
MHz
50
77.5
50
77.5
MHz
MHz
100
155
100
155
MHz
MHz
5–37
Stratix Device Handbook, Volume 2
J = 10
300
311
Mbps
J=8
300
311
Mbps
J=7
300
311
Mbps
J=4
300
311
Mbps
J=2
100
300
100
155
100
155
Mbps
J=1
100
200
100
155
100
155
Mbps
TCCS
All
SW
PCML (J = 4, 7, 8, 10) only
400
400
400
ps
800
800
800
ps
PCML (J = 2) only
1,200
1,200
1,200
ps
PCML (J = 1) only
1,700
1,700
1,700
ps
LVDS and LVPECL (J = 1) only
550
550
550
ps
LVDS, LVPECL, HyperTransport
technology (J = 2 through 10) only
500
500
500
ps
Source-Synchronous Timing Budget
Altera Corporation
July 2005
Table 5–8. High-Speed I/O Specifications for Wire-Bond Packages (Part 2 of 3)
-6 Speed Grade
Symbol
-7 Speed Grade
-8 Speed Grade
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Input jitter tolerance (peak-topeak)
All
250
250
250
ps
Output jitter (peak-to-peak)
All
200
200
200
ps
Output tR I S E
LVDS
80
110
120
80
110
120
80
110
120
ps
HyperTransport technology
120
170
200
120
170
200
120
170
200
ps
LVPECL
100
135
150
100
135
150
100
135
150
ps
PCML
80
110
135
80
110
135
80
110
135
ps
Output tFA L L
tD U T Y
LVDS
80
110
120
80
110
120
80
110
120
ps
HyperTransport
110
170
200
110
170
200
110
170
200
ps
LVPECL
100
135
160
100
135
160
100
135
160
ps
PCML
110
145
175
110
145
175
110
145
175
ps
LVDS (J =2..10) only
47.5
50
52.5
47.5
50
52.5
47.5
50
52.5
%
45
50
55
45
50
55
45
50
55
%
100
μs
LVDS (J =1) and LVPECL, PCML,
HyperTransport technology
tL O C K
All
100
100
Source-Synchronous Timing Budget
Altera Corporation
July 2005
Table 5–8. High-Speed I/O Specifications for Wire-Bond Packages (Part 3 of 3)
5–38
Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Input Timing Waveform
Figure 5–25 illustrates the essential operations and the timing
relationship between the clock cycle and the incoming serial data. For a
functional description of the SERDES, see “Principles of SERDES
Operation” on page 5–6.
Figure 5–25. Input Timing Waveform Note (1)
Input Clock
(Differential
Signal)
Previous Cycle
bit 0
Input Data
Next
Cycle
Current Cycle
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
tsw0 (min)
MSB
tsw0 (max)
tsw1 (min)
tsw1 (max)
tsw2 (min)
tsw2 (max)
tsw3 (min)
tsw3 (max)
tsw4 (min)
tsw4 (max)
tsw5 (min)
tsw5 (max)
tsw6 (min)
tsw6 (max)
tsw7 (min)
tsw7 (max)
bit 7
LSB
Note to Figure 5–25:
(1)
The timing specifications are referenced at a 100-mV differential voltage.
Altera Corporation
July 2005
5–39
Stratix Device Handbook, Volume 2
Source-Synchronous Timing Budget
Output Timing
The output timing waveform in Figure 5–26 illustrates the relationship
between the output clock and the serial output data stream.
Figure 5–26. Output Timing Waveform Note (1)
Output Clock
(Differential
Signal)
Previous Cycle
Output Data
bit 0
Next
Cycle
Current Cycle
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TPPos0 (min)
MSB
TPPos0 (max)
LSB
TPPos1 (min)
TPPos1 (max)
TPPos2 (min)
TPPos2 (max)
TPPos3 (min)
TPPos3 (max)
TPPos4 (min)
TPPos4 (max)
TPPos5 (min)
TPPos5 (max)
TPPos6 (min)
TPPos6 (max)
TPPos7 (min)
TPPos7 (max)
Note to Figure 5–26:
(1)
The timing specifications are referenced at a 250-mV differential voltage.
Receiver Skew Margin
Change in system environment, such as temperature, media (cable,
connector, or PCB) loading effect, a receiver's inherent setup and hold,
and internal skew, reduces the sampling window for the receiver. The
timing margin between receiver’s clock input and the data input
sampling window is known as RSKM. Figure 5–27 illustrates the
relationship between the parameter and the receiver’s sampling window.
5–40
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–27. Differential High-Speed Timing Diagram & Timing Budget
Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Internal
Clock
TCCS
TCCS
Receiver
Input Clock
Sampling
Window (SW)
RSKM
RSKM
TPPos (max)
Bit n + 1
TPPos (max)
Bit n
tSW (min)
Bit n
TPPos (min)
Bit n
Timing Budget
Internal tSW (max)
Clock
Bit n
Falling Edge
TPPos (min)
Bit n + 1
TUI
External
Clock
Clock Placement
Internal
Clock
Synchronization
Transmitter
Output Data
RSKM
RSKM
TCCS
TCCS
2
TSWEND
Receiver
Input Data
TSWBEGIN
Altera Corporation
July 2005
Sampling
Window
5–41
Stratix Device Handbook, Volume 2
SERDES Bypass DDR Differential Signaling
Switching Characteristics
Timing specifications for Stratix devices are listed in Tables 5–7 and 5–8.
You can also find Stratix device timing information in the Stratix Device
Family Data Sheet section of the Stratix Device Handbook, Volume 1.
Timing Analysis
Differential timing analysis is based on skew between data and the clock
signals. For static timing analysis, the timing characteristics of the
differential I/O standards are guaranteed by design and depend on the
frequency at which they are operated. Use the values in the Stratix Device
Family Data Sheet section of the Stratix Device Handbook, Volume 1 to
calculate system timing margins for various I/O protocols. For detailed
descriptions and implementations of these protocols, see the Altera web
site at www.altera.com.
SERDES Bypass
DDR Differential
Signaling
Each Stratix device high-speed differential I/O channel can transmit or
receive data in by-two (×2) mode at up to 624 Mbps using PLLs. These
pins do not require dedicated SERDES circuitry and they implement
serialization and deserialization with minimal logic.
SERDES Bypass DDR Differential Interface Review
Stratix devices use dedicated DDR circuitry to implement ×2 differential
signaling. Although SDR circuitry samples data only at the positive edge
of the clock, DDR captures data on both the rising and falling edges for
twice the transfer rate of SDR. Stratix device shift registers, internal global
PLLs, and I/O cells can perform serial-to-parallel conversions on
incoming data and parallel-to-serial conversion on outgoing data.
SERDES Clock Domains
The SERDES bypass differential signaling can use any of the many clock
domains available in Stratix devices. These clock domains fall into four
categories: global, regional, fast regional, and internally generated.
General-purpose PLLs generate the global clock domains. The fast PLLs
can generate additional global clocks domains. Each PLL features two
taps that directly drive two unique global clock networks. A dedicated
clock pin drives each general-purpose PLL. These clock lines are utilized
when designing for speeds up to 420 Mbps. Tables 5–3 and 5–4 on
page 5–19, respectively, show the available clocks in Stratix devices.
5–42
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
SERDES Bypass DDR Differential Signaling Receiver Operation
The SERDES bypass differential signaling receiver uses the Stratix device
DDR input circuitry to receive high-speed serial data. The DDR input
circuitry consists of a pair of shift registers used to capture the high-speed
serial data, and a latch.
One register captures the data on the positive edge of the clock (generated
by PLL) and the other register captures the data on the negative edge of
the clock. Because the data captured on the negative edge is delayed by
one-half of the clock cycle, it is latched before it interfaces with the system
logic.
Figure 5–28 shows the DDR timing relationship between the incoming
serial data and the clock. In this example, the inclock signal is running
at half the speed of the incoming data. However, other combinations are
also possible. Figure 5–29 shows the DDR input and the other modules
used in a Flexible-LVDS receiver design to interface with the system logic.
Figure 5–28. ×2 Timing Relation between Incoming Serial Data & Clock
clock
datain
B0
neg_reg_out XX
Altera Corporation
July 2005
A0
B1
B0
A1
B2
B1
A2
B3
B2
A3
B3
dataout_l
XX
B0
B1
B2
dataout_h
XX
A0
A1
A2
5–43
Stratix Device Handbook, Volume 2
SERDES Bypass DDR Differential Signaling
Figure 5–29. ×2 Data Rate Receiver Channel with Deserialization Factor of 8
DDR IOE
datain
Shift
Register
DFF
D0, D2, D4, D6
Register
D1, D3, D5, D7
Stratix
Logic
Array
Latch
DFF
Shift
Register
inclock
PLL
×4
Clock
×1
SERDES Bypass DDR Differential Signaling Transmitter
Operation
The ×2 differential signaling transmitter uses the Stratix device DDR
output circuitry to transmit high-speed serial data. The DDR output
circuitry consists of a pair of shift registers and a multiplexer. The shift
registers capture the parallel data on the clock’s rising edge (generated by
the PLL), and a multiplexer transmits the data in sync with the clock.
Figure 5–30 shows the DDR timing relation between the parallel data and
the clock. In this example, the inclock signal is running at half the speed
of the data. However, other combinations are possible. Figure 5–31 shows
the DDR output and the other modules used in a ×2 transmitter design to
interface with the system logic.
5–44
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–30. ×2 Timing Relation between Parallel Data & Clock
outclock
datain_l XX
B0
B1
B2
B3
datain_h XX
A0
A1
A2
A3
dataout
XX
A0
B0
A1
B1
A2
B2
A3
Figure 5–31. ×2 Data Rate Transmitter Channel with Serialization Factor of 8
DDR IOE
DFF
D0, D2,
D4, D6
Stratix
Logic
Array
Shift
Register
dataout
DFF
D1, D3,
D5, D7
Shift
Register
×1
PLL
×4
×1
inclock
High-Speed
Interface Pin
Locations
Stratix high-speed interface pins are located at the edge of the package to
limit the possible mismatch between a pair of high-speed signals. Stratix
devices have eight programmable I/O banks. Figure 5–32 shows the I/O
pins and their location relative to the package.
Altera Corporation
July 2005
5–45
Stratix Device Handbook, Volume 2
Differential I/O Termination
Figure 5–32. Differential I/O Pin Locations
Differential I/O Pins
(LVDS, LVPECL,
PCML, HyperTransport)
Regular I/O Pins
Differential I/O Pins
(LVDS, LVPECL,
PCML, HyperTransport)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Regular I/O Pins
Differential I/O
Termination
Stratix devices implement differential on-chip termination to reduce
reflections and maintain signal integrity. On-chip termination also
minimizes the number of external resistors required. This simplifies
board design and places the resistors closer to the package, eliminating
small stubs that can still lead to reflections.
RD Differential Termination
Stratix devices support differential on-chip termination for the LVDS I/O
standard. External termination is required on output pins for PCML
transmitters. HyperTransport, LVPECL, and LVDS receivers require
100 ohm termination at the input pins. Figure 5–33 shows the device with
differential termination for the LVDS I/O standard.
f
For more information on differential on-chip termination technology, see
the Selectable I/O Standards in Stratix & Stratix GX Devices chapter.
5–46
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–33. LVDS Differential On-Chip Termination
LVDS Receiver with
On-Chip 100-Ω Termination
LVDS Transmitter
Z0 = 50 Ω
RD
Z0 = 50 Ω
HyperTransport & LVPECL Differential Termination
HyperTransport and LVPECL I/O standards are terminated by an
external 100-Ω resistor on the input pin. Figure 5–34 shows the device
with differential termination for the HyperTransport or LVPECL I/O
standard.
Figure 5–34. HyperTransport & LVPECL Differential Termination
Differential
Transmitter
Differential Receiver
Z0 = 50 Ω
RD
Z0 = 50 Ω
PCML Differential Termination
The PCML I/O technology is an alternative to the LVDS I/O technology,
and use an external voltage source (VTT), a pair of 100-Ω resistors on the
input side and a pair of 50-Ω resistors on the output side. Figure 5–35
shows the device with differential termination for PCML I/O standard.
Altera Corporation
July 2005
5–47
Stratix Device Handbook, Volume 2
Differential I/O Termination
Figure 5–35. PCML Differential Termination
VTT
Differential
Transmitter
50 Ω
50 Ω
50 Ω
Differential
Receiver
50 Ω
Z0 = 50 Ω
Z0 = 50 Ω
Differential HSTL Termination
The HSTL Class I and II I/O standards require a 0.75-V VREF and a 0.75V VTT. Figures 5–36 and 5–37 show the device with differential
termination for HSTL Class I and II I/O standard.
Figure 5–36. Differential HSTL Class I Termination
VTT = 0.75 V
Differential
Transmitter
50 Ω
VTT = 0.75 V
50 Ω
Differential
Receiver
Z0 = 50 Ω
Z0 = 50 Ω
5–48
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–37. Differential HSTL Class II Termination
VTT = 0.75 V
Differential
Transmitter
50 Ω
VTT = 0.75 V
VTT = 0.75 V
50 Ω
50 Ω
VTT = 0.75 V
Differential
Receiver
50 Ω
Z0 = 50 Ω
Z0 = 50 Ω
Differential SSTL-2 Termination
The SSTL-2 Class I and II I/O standards require a 1.25-V VREF and a
1.25-V VTT. Figures 5–37 and 5–38 show the device with differential
termination for SSTL-2 Class I and II I/O standard.
Figure 5–38. Differential SSTL-2 Class I Termination
VTT = 1.25 V
Differential
Transmitter
50 Ω
VTT = 1.25 V
50 Ω
Differential
Receiver
25 Ω
Z0 = 50 Ω
25 Ω
Z0 = 50 Ω
Altera Corporation
July 2005
5–49
Stratix Device Handbook, Volume 2
Board Design Consideration
Figure 5–39. Differential SSTL-2 Class II Termination
VTT = 1.25 V
Differential
Transmitter
50 Ω
VTT = 1.25 V
50 Ω
VTT = 1.25 V
50 Ω
VTT = 1.25 V
50 Ω
Differential
Receiver
25 Ω
Z0 = 50 Ω
25 Ω
Z0 = 50 Ω
Board Design
Consideration
This section is a brief explanation of how to get the optimal performance
from the Stratix high-speed I/O block and ensure first-time success in
implementing a functional design with optimal signal quality. For more
information on detailed board layout recommendation and I/O pin
terminations see AN 224: High-Speed Board Layout Guidelines.
You must consider the critical issues of controlled impedance of traces
and connectors, differential routing, and termination techniques to get
the best performance from the IC. For more information, use this chapter
and the Stratix Device Family Data Sheet section of the Stratix Device
Handbook, Volume 1.
The Stratix high-speed module generates signals that travel over the
media at frequencies as high as 840 Mbps. Board designers should use the
following general guidelines:
■
■
■
■
■
■
■
Baseboard designs on controlled differential impedance. Calculate
and compare all parameters such as trace width, trace thickness, and
the distance between two differential traces.
Place external reference resistors as close to receiver input pins as
possible.
Use surface mount components.
Avoid 90° or 45° corners.
Use high-performance connectors such as HS-3 connectors for
backplane designs. High-performance connectors are provided by
Teradyne Corp (www.teradyne.com) or Tyco International Ltd.
(www.tyco.com).
Design backplane and card traces so that trace impedance matches
the connector’s and/or the termination’s impedance.
Keep equal number of vias for both signal traces.
5–50
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
■
■
■
■
■
Software
Support
Create equal trace lengths to avoid skew between signals. Unequal
trace lengths also result in misplaced crossing points and system
margins as the TCCS value increases.
Limit vias because they cause discontinuities.
Use the common bypass capacitor values such as 0.001 µF, 0.01 µF,
and 0.1 µF to decouple the fast PLL power and ground planes.
Keep switching TTL signals away from differential signals to avoid
possible noise coupling.
Do not route TTL clock signals to areas under or above the
differential signals.
This section provides information on using the Quartus II software to
create Stratix designs with LVDS transmitters or receivers. You can use
the altlvds megafunction in the Quartus II software to implement the
SERDES circuitry. You must bypass the SERDES circuitry in ×1 and ×2
mode designs and use the altddio megafunction to implement the
deserialization instead. You can use either the logic array or the M512
RAM blocks closest to the differential pins for deserialization in SERDES
bypass mode.
Differential Pins in Stratix
Stratix device differential pins are located in I/O banks 1, 2, 5, and 6 (see
Figure 5–1 on page 5–2). Each bank has differential transmitter and
differential receiver pin pairs. You can use each differential transmitter
pin pair as either a differential data pin pair or a differential clock pin pair
because Stratix devices do not have dedicated LVDS tx_outclock pin
pairs. The differential receiver pin pairs can only function as differential
data pin pairs. You can use these differential pins as regular user I/O pins
when not used as differential pins. When using differential signaling in
an I/O bank, you cannot place non-differential output or bidirectional
pads within five I/O pads of either side of the differential pins to avoid a
decrease in performance on the LVDS signals.
You only need to make assignments to the positive pin of the pin-pair.
The Quartus II software automatically reserves and makes the same
assignment to the negative pin. If you do not assign any differential I/O
standard to the differential pins, the Quartus II software sets them as
LVDS differential pins during fitting, if the design uses the SERDES
circuitry. Additionally, if you bypass the SERDES circuitry, you can still
use the differential pins by assigning a differential I/O standard to the
pins in the Quartus II software. However, when you bypass the SERDES
circuitry in the ×1 and ×2 mode, you must assign the correct differential
I/O standard to the associated pins in the Assignment Organizer. For
more information on how to use the Assignment Organizer, see the
Quartus II On-Line Help.
Altera Corporation
July 2005
5–51
Stratix Device Handbook, Volume 2
Software Support
Stratix devices can drive the PLL_LOCK signal to both output pins and
internal logic. As a result, you do not need a dedicated LOCK pin for your
PLLs. In addition, there is only one PLL_ENABLE pin that enables all the
PLLs on the device, including the fast PLLs. You must use either the
LVTTL or LVCMOS I/O standard with this pin.
Table 5–9 displays the LVDS pins in Stratix devices.
Table 5–9. LVDS Pin Names
Pin Names
Functions
DIFFIO_TX#p
Transmitter positive data or output clock pin
DIFFIO_TX#n
Transmitter negative data or output clock pin
DIFFIO_RX#p
Receiver positive data pin
DIFFIO_RX#n
Receiver negative data pin
FPLLCLK#p
Positive input clock pin to the corner fast PLLs (1), (2)
FPLLCLK#n
Negative input clock pin to the corner fast PLLs (1), (2)
CLK#p
Positive input clock pin (2)
CLK#n
Negative input clock pin (2)
Notes to Table 5–9:
(1)
(2)
The FPLLCLK pin-pair is only available in EP1S30, EP1S40, EP1S60, EP1S80
devices.
Either a FPLLCLK pin or a CLK pin can drive the corner fast PLLs (PLL7, PLL8,
PLL9, and PLL10) when used for general purpose. CLK pins cannot drive these
fast PLLs in high-speed differential I/O mode.
Fast PLLs
Each fast PLL features a multiplexed input path from a global or regional
clock net. A clock pin or an output from another PLL in the device can
drive the input path. The input clock for PLLs used to clock receiver the
rx_inclock port on the altlvds_rx megafunction must be driven by
a dedicated clock pin (CLK[3..0,8..11]) or the corner pins that clock the
corner PLLs (FPLL[10..7]CLK). EP1S10, EP1S20, and EP1S25 devices have
a total of four fast PLLs located in the center of both sides of the device
(see Figure 5–16 on page 5–23). EP1S30 and larger devices have two
additional fast PLLs per side at the top and bottom corners of the device.
As shown in Figure 5–17 on page 5–24, the corner fast PLL shares an I/O
bank with the closest center fast PLL (e.g., PLLs 1 and 7 share an I/O
bank). The maximum input clock frequency for enhanced PLLs is 684
MHz and 717 MHz for fast PLLs.
f
For more information on Stratix PLLs, see the General-Purpose PLLs in
Stratix & Stratix GX Devices chapter.
5–52
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
One fast PLL can drive the 20 transmitter channels and 20 receiver
channels closest to it with data rates of up to 840 Mbps. Wire-bond
packages support a data rate of 624 Mbps. The corner fast PLLs in EP1S80
devices support data rates of up to 840 Mbps. See Tables 5–10 through
5–14 for the number of high-speed differential channels in a particular
Stratix device density and package.
Since the fast PLL drives the 20 closest differential channels, there are
coverage overlaps in the EP1S30 and larger devices that have two fast
PLLs per I/O bank. In these devices, either the center fast PLL or the
corner fast PLL can drive the differential channels in the middle of the
I/O bank.
Fast PLLs can drive more than 20 transmitter and 20 receiver channels
(see Tables 5–10 through 5–14 and Figures 5–16, and 5–17 for the number
of channels each PLL can drive). In addition, the center fast PLLs can
drive either one I/O bank or both I/O banks on the same side (left or
right) of the device, while the corner fast PLLs can only drive the
differential channels in its I/O bank. Neither fast PLL can drive the
differential channels in the opposite side of the device.
The center fast PLLs can only drive two I/O at 840 Mbps. For example,
EP1S20 device fast PLL 1 can drive all 33 differential channels on its side
(17 channels from I/O bank 2 and 16 channels from I/O bank 1) running
at 840 Mbps in 4× mode. When a center fast PLL drives the opposite bank
on the same side of the device, the other center fast PLL cannot drive any
differential channels on the device.
See Tables 5–10 through 5–14 for the maximum number of channels that
one fast PLL can drive. The number of channels is also listed in the
Quartus II software. The Quartus II software gives an error message if
you try to compile a design exceeding the maximum number of channels.
f
Altera Corporation
July 2005
Additional high-speed DIFFIO pin information for Stratix devices is
available in Volume 3 of the Stratix Device Handbook.
5–53
Stratix Device Handbook, Volume 2
Software Support
Table 5–10 shows the number of channels and fast PLLs in EP1S10,
EP1S20, and EP1S25 devices. Tables 5–11 through 5–14 show this
information for EP1S30, EP1S40, EP1S60, and EP1S80 devices.
Table 5–10. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 1 of 2) Note (1)
Device
EP1S10
Package
Transmitter/
Receiver
484-pin FineLine BGA Transmitter
(2)
Receiver
672-pin FineLine BGA Transmitter
672-pin BGA
(2)
Receiver
780-pin FineLine BGA Transmitter
(2)
Receiver
EP1S20
484-pin FineLine BGA Transmitter
(2)
Receiver
672-pin FineLine BGA Transmitter
672-pin BGA
(2)
Receiver
780-pin FineLine BGA Transmitter
(2)
Receiver
5–54
Stratix Device Handbook, Volume 2
Total
Channels
20
20
36
36
44
44
24
20
48
50
66
66
Maximum
Speed
(Mbps)
Center Fast PLLs
PLL 1
PLL 2
PLL 3
PLL 4
840
5
5
5
5
840 (3)
10
10
10
10
840
5
5
5
5
840 (3)
10
10
10
10
624 (4)
9
9
9
9
624 (3)
18
18
18
18
624 (4)
9
9
9
9
624 (3)
18
18
18
18
840
11
11
11
11
840 (3)
22
22
22
22
840
11
11
11
11
840 (3)
22
22
22
22
840
6
6
6
6
840 (3)
12
12
12
12
840
5
5
5
5
840 (3)
10
10
10
10
624 (4)
12
12
12
12
624 (3)
24
24
24
24
624 (4)
13
12
12
13
624 (3)
25
25
25
25
840
17
16
16
17
840 (3)
33
33
33
33
840
17
16
16
17
840 (3)
33
33
33
33
Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Table 5–10. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 2 of 2) Note (1)
Device
EP1S25
Package
Transmitter/
Receiver
672-pin FineLine BGA Transmitter
672-pin BGA
(2)
Receiver
780-pin FineLine BGA Transmitter
(2)
Receiver
1,020-pin FineLine
BGA
Total
Channels
Maximum
Speed
(Mbps)
PLL 1
PLL 2
PLL 3
PLL 4
56
624 (4)
14
14
14
14
624 (3)
28
28
28
28
624 (4)
14
15
15
14
624 (3)
29
29
29
29
58
70
66
Transmitter
(2)
78
Receiver
78
Center Fast PLLs
840
18
17
17
18
840 (3)
35
35
35
35
840
17
16
16
17
840 (3)
33
33
33
33
840
19
20
20
19
840 (3)
39
39
39
39
840
19
20
20
19
840 (3)
39
39
39
39
Notes to Table 5–10:
(1)
(2)
(3)
(4)
The first row for each transmitter or receiver reports the number of channels driven directly by the PLL. The second
row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center
PLL. For example, in the 484-pin FineLine BGA EP1S10 device, PLL 1 can drive a maximum of five channels at
840 Mbps or a maximum of 10 channels at 840 Mbps. The Quartus II software may also merge receiver and
transmitter PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive both the maximum
numbers of receiver and transmitter channels.
The number of channels listed includes the transmitter clock output (tx_outclock) channel. If the design
requires a DDR clock, it can use an extra data channel.
These channels span across two I/O banks per side of the device. When a center PLL clocks channels in the
opposite bank on the same side of the device it is called cross-bank PLL support. Both center PLLs can clock crossbank channels simultaneously if, for example, PLL_1 is clocking all RX channels and PLL_2 is clocking all TX
channels. You cannot have two adjacent PLLs simultaneously clocking cross-bank RX channels or two adjacent
PLLs simultaneously clocking TX channels. Cross-bank allows for all receiver channels on one side of the device to
be clocked on one clock while all transmitter channels on the device are clocked on the other center PLL. Crossbank
PLLs are supported at full-speed, 840 Mbps. For wire-bond devices, the full-speed is 624 Mbps.
These values show the channels available for each PLL without crossing another bank.
Altera Corporation
July 2005
5–55
Stratix Device Handbook, Volume 2
Software Support
Table 5–11. EP1S30 Differential Channels Note (1)
Package
780-pin
FineLine
BGA
956-pin
FineLine
BGA
1,020-pin
FineLine
BGA
Transmitter
Total
/Receiver Channels
Transmitter
(4)
70
Receiver
66
Transmitter
(4)
80 (7)
Receiver
80 (7)
Transmitter
(4)
80 (2) (7)
Receiver
80 (2) (7)
Maximum
Center Fast PLLs
Corner Fast PLLs (2), (3)
Speed
(Mbps) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
840
18
17
17
18
(6)
(6)
(6)
(6)
840 (5)
35
35
35
35
(6)
(6)
(6)
(6)
840
17
16
16
17
(6)
(6)
(6)
(6)
840 (5)
33
33
33
33
(6)
(6)
(6)
(6)
840
19
20
20
19
20
20
20
20
840 (5)
39
39
39
39
20
20
20
20
840
20
20
20
20
19
20
20
19
840 (5)
40
40
40
40
19
20
20
19
840
19
(1)
20
20
19
(1)
20
20
20
20
840 (5),(8)
39
(1)
39
(1)
39
(1)
39
(1)
20
20
20
20
840
20
20
20
20
19 (1)
20
20
19 (1)
840 (5),(8)
40
40
40
40
19 (1)
20
20
19 (1)
Table 5–12. EP1S40 Differential Channels (Part 1 of 2) Note (1)
Package
780-pin
FineLine
BGA
956-pin
FineLine
BGA
Transmitter
Total
/Receiver Channels
Transmitter
(4)
68
Receiver
66
Transmitter
(4)
80
Receiver
80
5–56
Stratix Device Handbook, Volume 2
Maximum
Speed
(Mbps)
Center Fast PLLs
Corner Fast PLLs (2), (3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
840
18
16
16
18
(6)
(6)
(6)
(6)
840 (5)
34
34
34
34
(6)
(6)
(6)
(6)
840
17
16
16
17
(6)
(6)
(6)
(6)
840 (5)
33
33
33
33
(6)
(6)
(6)
(6)
840
18
17
17
18
20
20
20
20
840 (5)
35
35
35
35
20
20
20
20
840
20
20
20
20
18
17
17
18
840 (5)
40
40
40
40
18
17
17
18
Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Table 5–12. EP1S40 Differential Channels (Part 2 of 2) Note (1)
Package
1,020-pin
FineLine
BGA
Transmitter
Total
/Receiver Channels
Transmitter
(4)
Receiver
1,508-pin
FineLine
BGA
Transmitter
(4)
Receiver
80 (10)
(7)
80 (10)
(7)
80 (10)
(7)
80 (10)
(7)
Maximum
Speed
(Mbps)
Center Fast PLLs
Corner Fast PLLs (2), (3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
840
18
(2)
17
(3)
17
(3)
18
(2)
20
20
20
20
840 (5), (8)
35
(5)
35
(5)
35
(5)
35
(5)
20
20
20
20
840
20
20
20
20
18
(2)
17
(3)
17
(3)
18 (2)
840 (5), (8)
40
40
40
40
18
(2)
17
(3)
17
(3)
18 (2)
840
18
(2)
17
(3)
17
(3)
18
(2)
20
20
20
20
840 (5), (8)
35
(5)
35
(5)
35
(5)
35
(5)
20
20
20
20
840
20
20
20
20
18
(2)
17
(3)
17
(3)
18 (2)
840 (5), (8)
40
40
40
40
18
(2)
17
(3)
17
(3)
18 (2)
Table 5–13. EP1S60 Differential Channels (Part 1 of 2) Note (1)
Package
956-pin
FineLine
BGA
1,020-pin
FineLine
BGA
Transmitter
Total
/Receiver Channels
Transmitter
(4)
80
Receiver
80
Transmitter
(4)
80 (12)
(7)
Receiver
Altera Corporation
July 2005
80 (10)
(7)
Maximum
Center Fast PLLs
Corner Fast PLLs (2), (3)
Speed
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
(Mbps)
840
12
10
10
12
20
20
20
20
840 (5), (8)
22
22
22
22
20
20
20
20
840
20
20
20
20
12
10
10
12
840 (5), (8)
40
40
40
40
12
10
10
12
840
12
(2)
10
(4)
10
(4)
12
(2)
20
20
20
20
840 (5), (8)
22
(6)
22
(6)
22
(6)
22
(6)
20
20
20
20
840
20
20
20
20
12
(8)
10
(10)
10
(10)
12 (8)
840 (5), (8)
40
40
40
40
12
(8)
10
(10)
10
(10)
12 (8)
5–57
Stratix Device Handbook, Volume 2
Software Support
Table 5–13. EP1S60 Differential Channels (Part 2 of 2) Note (1)
Package
1,508-pin
FineLine
BGA
Transmitter
Total
/Receiver Channels
Transmitter
(4)
Receiver
80 (36)
(7)
80 (36)
(7)
Maximum
Center Fast PLLs
Corner Fast PLLs (2), (3)
Speed
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
(Mbps)
840
12
(8)
10
(10)
10
(10)
12
(8)
20
20
20
20
840 (5),(8)
22
(18)
22
(18)
22
(18)
22
(18)
20
20
20
20
840
20
20
20
20
12
(8)
10
(10)
10
(10)
12 (8)
840 (5),(8)
40
40
40
40
12
(8)
10
(10)
10
(10)
12 (8)
Table 5–14. EP1S80 Differential Channels (Part 1 of 2) Note (1)
Package
956-pin
FineLine
BGA
1,020-pin
FineLine
BGA
Transmitter
Total
/Receiver Channels
Transmitter
(4)
80 (40)
(7)
Receiver
80
Transmitter
(4)
80 (12)
(7)
Receiver
80 (10)
(7)
5–58
Stratix Device Handbook, Volume 2
Maximum
Center Fast PLLs
Corner Fast PLLs (2)
Speed
(Mbps) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
840
10
10
10
10
20
20
20
20
840 (5),(8)
20
20
20
20
20
20
20
20
840
20
20
20
20
10
10
10
10
840 (5),(8)
40
40
40
40
10
10
10
10
840
10
(2)
10
(4)
10
(4)
10
(2)
20
20
20
20
840 (5),(8)
20
(6)
20
(6)
20
(6)
20
(6)
20
20
20
20
840
20
20
20
20
10
(2)
10
(3)
10 (3)
10 (2)
840 (5),(8)
40
40
40
40
10
(2)
10
(3)
10 (3)
10 (2)
Altera Corporation
July 2005
High-Speed Differential I/O Interfaces in Stratix Devices
Table 5–14. EP1S80 Differential Channels (Part 2 of 2) Note (1)
Package
1,508-pin
FineLine
BGA
Transmitter
Total
/Receiver Channels
Transmitter
(4)
Receiver
80 (72)
(7)
80 (56)
(7)
Maximum
Center Fast PLLs
Corner Fast PLLs (2)
Speed
(Mbps) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
840
10
(10)
10
(10)
10
(10)
10
(10)
20
(8)
20
(8)
20 (8)
20 (8)
840 (5),(8)
20
(20)
20
(20)
20
(20)
20
(20)
20
(8)
20
(8)
20 (8)
20 (8)
840
20
20
20
20
10
(14)
10
(14)
10
(14)
10
(14)
840 (5),(8)
40
40
40
40
10
(14)
10
(14)
10
(14)
10
(14)
Notes to Tables 5–11 through 5–14.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
The first row for each transmitter or receiver reports the number of channels driven directly by the PLL. The second
row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center
PLL. For example, in the 780-pin FineLine BGA EP1S30 device, PLL 1 can drive a maximum of 18 transmitter
channels at 840 Mbps or a maximum of 35 transmitter channels at 840 Mbps. The Quartus II software may also
merge transmitter and receiver PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive
both the maximum numbers of receiver and transmitter channels.
Some of the channels accessible by the center fast PLL and the channels accessible by the corner fast PLL overlap.
Therefore, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and
4 with the number of channels accessible by PLLs 7, 8, 9, and 10. For more information on which channels overlap,
see the Fast PLL to High-Speed I/O Connections section in the relevant device pin table available on the web
(www.altera.com).
The corner fast PLLs in this device support a data rate of 840 Mbps for channels labeled “high” speed in the device
pin tables.
The numbers of channels listed include the transmitter clock output (tx_outclock) channel. You can use an extra
data channel if you need a DDR clock.
These channels span across two I/O banks per side of the device. When a center PLL clocks channels in the opposite
bank on the same side of the device it is called cross-bank PLL support. Both center PLLs can clock cross-bank
channels simultaneously if, for example, PLL_1 is clocking all receiver channels and PLL_2 is clocking all
transmitter channels. You cannot have two adjacent PLLs simultaneously clocking cross-bank receiver channels or
two adjacent PLLs simultaneously clocking transmitter channels. Cross-bank allows for all receiver channels on one
side of the device to be clocked on one clock while all transmitter channels on the device are clocked on the other
center PLL. Crossbank PLLs are supported at full-speed, 840 Mbps. For wire-bond devices, the full-speed is
624 Mbps.
PLLs 7, 8, 9, and 10 are not available in this device.
The number in parentheses is the number of slow-speed channels, guaranteed to operate at up to 462 Mbps. These
channels are independent of the high-speed differential channels. For the location of these channels, see the Fast
PLL to High-Speed I/O Connections section in the relevant device pin table available on the web (www.altera.com).
See device pin-outs channels marked “high” speed are 840 Mbps and “low” speed channels are 462 MBps.
The Quartus II software may also merge transmitter and receiver PLLs
when a receiver block is driving a transmitter block if the Use Common
PLLs for Rx and Tx option is set for both modules. The Quartus II
software does not merge the PLLs in multiple transmitter-only or
multiple receiver-only modules fed by the same clock.
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When you span two I/O banks using cross-bank support, you can route
only two load enable signals total between the plls. When you enable
rx_data_align, you use both rxloadena and txloadena of a PLL.
That leaves no loadena for the second PLL.
The only way you can use the rx_data_align is if one of the following
is true:
■
■
The RX PLL is only clocking RX channels (no resources for TX)
If all channels can fit in one I/O bank
LVDS Receiver Block
You only need to enter the input clock frequency, deserialization factor,
and the input data rate to implement an LVDS receiver block. The
Quartus II software then automatically sets the clock boost (W) factor for
the receiver. In addition, you can also indicate the clock and data
alignment for the receiver or add the pll_enable, rx_data_align,
and rx_locked output ports. Table 5–15 explains the function of the
available ports in the LVDS receiver block.
Table 5–15. LVDS Receiver Ports
Port Name
Direction
rx_in[number_of_channels - 1..0] Input
Function
Input Port
Source/Output Port
Destination
Input data channel
Pin
rx_inclock
Input
Reference input clock
Pin or output from a PLL
rx_pll_enable
Input
Enables fast PLL
Pin (1), (2), (3)
rx_data_align
Input
Control for the data
realignment circuitry
Pin or logic array (1),
(3), (4)
rx_locked
Output
Fast PLL locked pin
Pin or logic array (1), (3)
rx_out[Deserialization_factor *
number_of_channels -1..0]
Output
De-serialized data
Logic array
rx_outclock
Output
Internal reference clock
Logic array
Notes to Table 5–15:
(1)
(2)
(3)
(4)
This is an optional port.
Only one rx_pll_enable pin is necessary to enable all the PLLs in the device.
This is a non-differential pin.
See “Realignment Implementation” on page 5–28 for more information. For guaranteed performance and data
alignment, you must synchronize rx_data_align with rx_outclock.
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Use the altlvds MegaWizard Plug-In Manager to create an LVDS
receiver block. The following sections explain the parameters available in
the Plug-In Manager when creating an LVDS receiver block.
Page 3 of the altlvds_rx MegaWizard Plug-In Manager
On page 3 of the altlvds MegaWizard Plug-In Manager, you can
choose to create either an LVDS transmitter or receiver. Depending on
what you select, the MegaWizard Plug-In Manager provides you with
different options. Figure 5–40 shows page 3 of the altlvds MegaWizard
Plug-In Manager with options for creating an LVDS receiver.
Figure 5–40. Page 3 of the altlvds_rx MegaWizard Plug-In Manager
Number of Channels
The What is the number of channels? parameter specifies the number of
receiver channels required and the width of rx_out port. To set a fast
PLL to drive over 20 channels, type the required number in the Quartus II
window instead of choosing a number from the drop-down menu, which
only has selections of up to 20 channels.
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Deserialization Factor
Use the What is the deserialization factor? parameter to specify the
number of bits per channel. The Stratix LVDS receiver supports 4, 7, 8,
and 10 for deserialization factor (J) values. Based on the factor specified,
the Quartus II software determines the multiplication and/or division
factor for the LVDS PLL to deserialize the data.
See Table 5–5 for the differential bit naming convention. The parallel data
for the nth channel spans from the MSB (rx_out bit [(J × n) – 1]) to the
LSB (rx_out bit [J × (n – 1)]), where J is the deserialization factor. The
total width of the receiver rx_out port is equal to the number of channels
multiplied by your deserialization factor.
Input Data Rate
The What is the inclock boost(W)? parameter sets the data rate coming
into the receiver and is usually the deserialization factor (J) multiplied by
the inclock frequency. This parameter’s value must be larger than the
input clock frequency and has a maximum input data rate of 840 Mbps
for Stratix devices. You do not have to provide a value for the inclock
boost (W) when designing with Stratix devices because the Quartus II
software can calculate it automatically from this parameter and the clock
frequency or clock period.
The rx_outclock frequency is (W/J) × input frequency. The parallel
data coming out of the receiver has the same frequency as the
rx_outclock port. The clock-to-data alignment of the parallel data
output from the receiver depends on the What is the alignment of data
with respect to rx_inclock? parameter.
Data Alignment with Clock
The What is the alignment of data with respect to rx_inclock? parameter
adjusts the clock-to-data skew. For most applications, the data is source
synchronous to the clock. However, there are applications where you
must center-align the data with respect to the clock. You can use the What
is the alignment of data with respect to rx_inclock? parameter to align
the input data with respect to the rx_inclock port. The MegaWizard
Plug-In automatically calculates the phase for the fast PLL outputs from
the What is the alignment of data with respect to rx_inclock? parameter.
This parameter’s default value is EDGE_ALIGNED, and other values
available from the pull-down menu are EDGE_ALIGNED,
CENTER_ALIGNED, 45_DEGREES, 135_DEGREES, 180_DEGREES,
225_DEGREES, 270_DEGREES, and 315_DEGREES. CENTER_ALIGNED
is the same as 90 degrees aligned and is useful for applications like
HyperTransport technology.
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Clock Frequency or Clock Period
The fields in the Specify the input clock rate by box specify the input
frequency or the period of the input clock going into the fast PLL. When
using the same input clock to feed a transmitter and receiver
simultaneously, the Quartus II software can use one fast PLL for both the
transmitter and receiver.
Page 4 of the altlvds_rx MegaWizard Plug-In Manager
This section describes the parameters found on page 4 of the
altlvds_rx MegaWizard Plug-In Manager (see Figure 5–41).
Figure 5–41. Page 4 of the altlvds_rx MegaWizard Plug-In Manager
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Data Realignment
Check the Use the “rx_data_align” input port box within the Input Ports
box to add the rx_data_align output port and enable the data
realignment circuitry in Stratix SERDES. See “Receiver Data
Realignment” on page 5–25 for more information. If necessary, you can
create a state machine to send a pulse to the rx_data_align port to
realign the data coming in the LVDS receiver. You need to assert the port
for at least two clock cycles to enable the data realignment circuitry. Go
to the Altera web site at www.altera.com for a sample design written in
Verilog HDL.
For guaranteed performance when using data realignment, check the
Add Extra registers for rx_data_align input box when using the
rx_data_align port. The Quartus II software places one
synchronization register in the LE closest to the rx_data_align port.
Register Outputs
Check the Register outputs box to register the receiver’s output data. The
register acts as the module’s register boundary. If the module fed by the
receiver does not have a register boundary for the data, turn this option
on. The number of registers used is proportional to the deserialization
factor (J). The Quartus II software places the synchronization registers in
the LEs closest to the SERDES circuitry.
Use Common PLL for Both Transmitter & Receiver
Check the Use Common PLLs for Rx and Tx box to place both the LVDS
transmitter and the LVDS receiver in the same Stratix device I/O bank.
The Quartus II software allows the transmitter and receiver to share the
same fast PLL when they use the same input clock. Although you must
separate the transmitter and receiver modules in your design, the
Quartus II software merges the fast PLLs when appropriate and give you
the following message:
Receiver fast PLL <lvds_rx PLL name> and transmitter fast PLL <lvds_tx
PLL name> are merged together
The Quartus II software provides the following message when it cannot
merge the fast PLLs for the LVDS transmitter and receiver pair in the
design:
Can't merge transmitter-only fast PLL <lvds_tx PLL name> and receiveronly fast PLL <lvds_rx PLL name>
rx_outclock Resource
You can use either the global or regional clock for the rx_outclock
signal. If you select Auto in the Quartus II software, the tool uses any
available lines.
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LVDS Transmitter Module
The Quartus II software calculates the inclock boost (W) factor for the
LVDS transmitter based on input data rate, input clock frequency, and
the deserialization factor. In addition to setting the data and clock
alignment, you can also set the outclock divide factor (B) for the
transmitter output clock and add the pll_enable, tx_locked, and
tx_coreclock ports. Table 5–16 explains the function of the available
ports in the LVDS transmitter block.
Table 5–16. LVDS Transmitter Ports
Port Name
Direction
Function
Input port
Source/Output port
Destination
tx_in[Deserialization_factor *
number_of_channels - 1..0]
Input
Input data
Logic array
tx_inclock
Input
Reference input clock
Pin or output clock
from a PLL
tx_pll_enable
Input
tx_out[number_of_channels - 1..0] Output
Fast PLL enable
Pin (1), (2), (3)
Serialized LVDS data
signal
Pin
tx_outclock
Output
External reference clock
Pin
tx_coreclock
Output
Internal reference clock
Pin, logic array, or
input clock to a fast
PLL (1)
tx_locked
Output
Fast PLL locked pin
Pin or logic array (1),
(2), (3)
Notes to Table 5–16:
(1)
(2)
(3)
This is an optional port.
Only one tx_pll_enable pin is necessary to enable all the PLLs in the device.
This is a non-differential pin.
You can also use the altlvds MegaWizard Plug-In Manager to create an
LVDS transmitter block. The following sections explain the parameters
available in the Plug-In Manager when creating an LVDS transmitter
block.
Page 3 of the altlvds_tx MegaWizard Plug-In Manager
This section describes the parameters found on page 3 of the
altlvds_tx MegaWizard Plug-In Manager (see Figure 5–42).
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Figure 5–42. Page 3 of the Transmitter altlvds MegaWizard Plug-In Manager
Number of Channels
The What is the number of channels? parameter specifies the number of
transmitter channels required and the width of the tx_in port. You can
have more than 20 channels in a transmitter or receiver module by typing
in the required number instead of choosing a number from the drop
down menu, which only has selections of up to 20 channels.
Deserialization Factor
The What is the deserialization factor? parameter specifies the number
of bits per channel. The transmitter block supports deserialization factors
of 4, 7, 8, and 10. Based on the factor specified, the Quartus II software
determines the multiplication and/or division factor for the LVDS PLL in
order to serialize the data.
Table 5–5 on page 5–32 lists the differential bit naming convention. The
parallel data for the nth channel spans from the MSB (rx_out bit
[(J × n) – 1]) to the LSB (rx_out bit [J × (n – 1)]), where J is the
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deserialization factor. The total width of the tx_in port of the transmitter
is equal to the number of channels multiplied by the deserialization
factor.
Outclock Divide Factor
The What is the Output data rate? parameter specifies the ratio of the
tx_outclock frequency compared to the data rate. The default value for
this parameter is the value of the deserialization factor parameter. The
tx_outclock frequency is equal to [W/B] x input clock frequency.
There is also an optional tx_coreclock port which has the same
frequency as the [W/J] × input frequency.
The outclock divide factor is useful for applications that do not require
the data rate to be the same as the clock frequency. For example,
HyperTransport technology uses a half-clock data rate scheme where the
clock frequency is half the data rate. Table 5–17 shows the supported
outclock divide factor for a given deserialization factor.
Table 5–17. Deserialization Factor (J) vs. Outclock Divide Factor (B)
Deserialization Factor (J)
Outclock Divide Factor (B)
4
1, 2, 4
7
1, 7(1)
8
1, 2, 4, 8
10
1, 2, 10
Note to Table 5–17:
(1)
The clock does not have a 50% duty cycle when b=7 in x7 mode.
Output Data Rate
The What is the Output data rate parameter specifies the data rate out of
the fast PLL and determines the input clock boost/multiplication factor
needed for the transmitter. This parameter must be larger than the input
clock frequency and has a maximum rate of 840 Mbps for Stratix devices.
The input clock boost factor (W) is the output data rate divided by the
input clock frequency. The Stratix SERDES circuitry supports input clock
boost factors of 4, 7, 8, or 10. The maximum output data rate is 840 Mbps,
while the clock has a maximum output of 500 MHz.
Data Alignment with Clock
Use the What is the alignment of data with respect to tx_inclock?
parameter and the What is the alignment of tx_outclock? to align the
input and output data, respectively, with the clock. For most applications,
the data is edge-aligned with the clock. However, there are applications
where the data must be center-aligned with respect to the clock. With
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Stratix devices, you can align the input data with respect to the
tx_inclock port and align the output data with respect to the
tx_outclock port. The MegaWizard Plug-In Manager uses the
alignment of input and output data to automatically calculate the phase
for the fast PLL outputs. Both of these parameters default to
EDGE_ALIGNED, and other values are CENTER_ALIGNED, 45_DEGREES,
135_DEGREES, 180_DEGREES, 225_DEGREES, 270_DEGREES, and
315_DEGREES. CENTER_ALIGNED is the same as 180 degrees aligned
and is required for the HyperTransport technology I/O standard.
Clock Frequency & Clock Period
The fields in the Specify the input clock rate by box specify either the
frequency or the period of the input clock going into the fast PLL.
However, you cannot specify both. If your design uses the same input
clock to feed a transmitter and a receiver module simultaneously, the
Quartus II software can merge the fast PLLs for both the transmitter and
receiver when the Use common PLLs for Tx & Rx option is turned on.
Page 4 of the altlvds_tx MegaWizard Plug-In Manager
This section describes the parameters found on page 4 of the
altlvds_tx MegaWizard Plug-In Manager (see Figure 5–43).
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Figure 5–43. Page 4 of the Transmitter altlvds MegaWizard Plug-In Manager
Registered Inputs
Check the Register inputs box if the input data to the transmitter is not
registered just before it feeds the transmitter module. You can choose
either tx_clkin or tx_coreclk to clock the transmitter data
(tx_in[]) signal. This serves as the register boundary. The number of
registers used is proportional to the deserialization factor (J). The
Quartus II software places the synchronization registers with the LEs in
the same row and closest to the SERDES circuitry.
Use Common PLL for Transmitter & Receiver
Check the Use Common PLLs for Rx and Tx box to place both the LVDS
transmitter and receiver in the same I/O bank in Stratix devices. The
Quartus II software also allows the transmitter and receiver to share the
PLL when the same input clock is used for both. Although you must
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separate the transmitter and receiver in your design, the Quartus II
software merges the fast PLLs when appropriate and gives you the
following message:
Receiver fast PLL <lvds_rx pll name> and transmitter fast PLL
<lvds_tx pll name> are merged together
The Quartus II software gives the following message when it cannot
merge the fast PLLs for the LVDS transmitter and receiver pair in the
design:
Can't merge transmitter-only fast PLL
<lvds_tx pll name> and receiver-only fast PLL
<lvds_rx pll name>
tx_outclock Resource
You can use either the global or regional clock for the tx_outclock
signal. If you select Auto in the Quartus II software, the tool uses any
available lines.
SERDES Bypass Mode
You can bypass the SERDES block if your data rate is less than 624 Mbps,
and you must bypass the SERDES block for the ×1 and ×2 LVDS modules.
Since you cannot route the fast PLL output to an output pin, you must
create additional DDR I/O circuitry for the transmitter clock output. To
create an ×J transmitter output clock, instantiate an alt_ddio
megafunction clocked by the ×J clock with datain_h connected to VCC
and datain_l connected to GND.
×1 Mode
For ×1 mode, you only need to specify the I/O standard of the pins to tell
the Quartus II software that you are using differential signaling.
However, Altera recommends using the DDRIO circuitry when the input
or output data rate is higher than 231 Mbps. The maximum output clock
frequency for ×1 mode is 420 MHz.
×2 Mode
You must use the DDRIO circuitry for ×2 mode. The Quartus II software
provides the altddio_in and altddio_out megafunctions to use for
×2 receiver and ×2 transmitter, respectively. The maximum data rate in
×2 mode is 624 Mbps. Figure 5–44 shows the schematic for using DDR
circuitry in ×2 mode.
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High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–44. LVDS x2 Mode Schematic Using DDR I/O Circuitry
DDIO In
RXp
RXn
datain[0]
inclock
DDIO Out
dataout_h[0]
dataout_l[0]
datain_h[0]
dataout[0]
TXp
TXn
datain_l[0]
Custom Logic
outclock
DDIO Out
RX_PLL
rx_inclk
inclock
/1 clock1
VCC
datain_h[0]
/2 clock0
GND
datain_l[0]
dataout[0]
tx_outclk
outclock
The transmitter output clock requires extra DDR output circuitry that has
the input high and input low connected to VCC and GND respectively. The
output clock frequency is the same as the input frequency of the DDR
output circuitry.
Other Modes
For other modes, you can still to use the DDR circuitry for better
frequency performance. You can use either the LEs or the M512 RAM
block for the deserialization.
M512 RAM Block as Serializer/Deserializer Interface
In addition to using the DDR circuitry and the M512 RAM block, you
need two extra counters per memory block to provide the address for the
memory: a fast counter powering up at 0 and a slow counter powering up
at 2. The M512 RAM block is configured as a simple dual-port memory
block, where the read enable and the write enable signals are always tied
high. Figures 5–45 and 5–46 show the block diagram for the SERDES
bypass receiver and SERDES bypass transmitter, respectively.
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Figure 5–45. SERDES Bypass LVDS Receiver Using M512 RAM Block as the Deserializer
waddr[7..5]
Simple Dual Port
RX_SESB
512 Bits
DDIO In
RXp
datain[0]
RXn
inclock
dataout_h[0]
datain[1..0]
dataout_l[0]
waddr[7..0]
dataout[7..0]
Core data
wclock
clock
q[4..0]
raddr[5..0]
rclock
W-UpCounter
RX_PLL
rx_inclk
inclock
÷1 clock1
÷2 clock0
clock
raddr[5..3]
q[2..0]
R-UpCounter
Core clock
Figure 5–46. SERDES Bypass LVDS Transmitter Using M512 RAM Block as Deserializer
waddr[7..5]
Simple Dual Port ×2×8
TX_SESB
512 Bits
core_data
datain[7..0]
clock
q[2..0]
DDIO Out
dataout[7..0]
datain_h[0]
dataout_h[0]
waddr[5..0]
datain_l[0]
dataout_l[0]
wclock
outclock
TXp
TXn
raddr[7..0]
rclock
W-UpCounter
RX_PLL
core_clk
inclock
÷1 clock1
×2 clock0
clock
q[5..0]
R-UpCounter
raddr[5..3]
RX_PLL
VCC
datain_h[0]
/1 clock1
GND
datain_l[0]
/2 clock0
tx_outclk
outclock
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High-Speed Differential I/O Interfaces in Stratix Devices
For the transmitter, the read counter is the fast counter and the write
counter is the slow counter. For the receiver, the write counter is the fast
counter and the read counter is the slow counter. Tables 5–18 and 5–19
provide the address counter configurations for the transmitter and the
receiver, respectively.
Table 5–18. Address Counters for SERDES Bypass LVDS Receiver
M512 Mode
Deserialization
Factor
Write Up-Counter
(Fast Counter)
Read Up-Counter
(Slow Counter)
Width
Starts at
Width
Starts at
Write
Read
Invalid Initial Cycles
×2×4
4
4
0
3
2
12
6
×2×8
8
5
0
3
2
24
6
×4×16
8
5
0
3
2
24
6
×2×16
16
6
0
3
2
48
6
Table 5–19. Address Counters for SERDES Bypass LVDS Transmitter
M512 Mode
Deserialization
Factor
Write Up-Counter
(Fast Counter)
Read Up-Counter
(Slow Counter)
Width
Starts at
Width
Starts at
Write
Read
Invalid Initial Cycles
×2×4
4
4
0
3
2
2
4
×2×8
8
5
0
3
2
2
8
×4×16
8
5
0
3
2
2
8
×2×16
16
6
0
3
2
2
16
In different M512 memory configurations, the counter width is smaller
than the address width, so you must ground some of the most significant
address bits. Table 5–20 summarizes the address width, the counter
width, and the number of bits to be grounded.
Table 5–20. Address & Counter Width
M512 Mode
Number of Grounded Bits
Write Counter Read Counter Write Address Read Address
Width
Width
Width
Width
Write Address Read Address
×2×4
4
3
8
7
4
4
×2×8
5
3
8
6
3
3
×4×16
6
3
7
5
1
2
×2×16
5
3
8
5
3
2
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Logic Array as Serializer/Deserializer Interface
The design can use the lpm_shift_reg megafunction instead of a
simple dual port memory block to serialize/deserialize data. The receiver
requires an extra flip-flop clocked by the slow clock to latch on to the
deserialized data. The transmitter requires a counter to generate the
enable signal for the shift register to indicate the times to load and
serialize the data. Figures 5–47 and 5–48 show the schematic of the ×8
LVDS receiver and ×8 LVDS transmitter, respectively, with the logic
array performing the deserialization.
This scheme can also be used for APEX II and Mercury device flexible
LVDS solutions.
Figure 5–47. SERDES Bypass LVDS Receiver with Logic Array as Deserializer
clock
Shift
Register
Serial
data in
×4 clock0
Clock
PLL
data_h
data
data[1, 3, 5, 7]
data[7..0]
D
DDR
Input
DFF[7..0]
Q
Data to
logic array
÷2 clock1
data_l
data
data[0, 2, 4, 6]
Shift
Register
CLK
clock
rx_clk
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Figure 5–48. SERDES Bypass LVDS Transmitter with Logic Array as Deserializer
Counter
Shift
Register
clock
load
data
Data[7..0]
data_l
×4 clock
Clock
PLL
×1 clock
DDR
Output
Shift
Register
data
Serial
data out
data_h
load
clock
tx_clk
Summary
Altera Corporation
July 2005
The Stratix device family of flexible, high-performance, high-density
PLDs delivers the performance and bandwidth necessary for complex
system-on-a-programmable-chip (SOPC) solutions. Stratix devices
support multiple I/O protocols to interface with other devices within the
system. Stratix devices can easily implement processing-intensive datapath functions that are received and transmitted at high speeds. The
Stratix family of devices combines a high-performance enhanced PLD
architecture with dedicated I/O circuitry in order to provide I/O
standard performances of up to 840 Mbps.
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Summary
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Altera Corporation
July 2005
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