Lecture 4 ECEN 4517/5517 Experiment 3 weeks 2 and 3: interleaved flyback and feedback loop 12 VDC Battery HVDC: 120 - 200 VDC DC-DC converter DC-AC inverter + Isolated flyback H-bridge vac(t) – d(t) Feedback controller d(t) –+ Vref Step-up dc-dc converter with isolation (flyback) Parallel two flybacks with phase-shifted gate drive signals Feedback controller to regulate HVDC ECEN 4517 Digital controller 1 AC load 120 Vrms 60 Hz Due dates and goals Right now: Prelab assignment for Exp. 4 Part 1 (one from every student) Due within five minutes of beginning of lecture This week in lab (Feb. 3-5): Final reports for Exps. 1 and 2 due Begin Exp. 3: construct and debug basic flyback power stage Next week in lab (Feb. 10-13): Get parallel flyback power stages working at 85 W Begin simulation of ac transfer functions and feedback loop design ECEN 4517 2 Goals in upcoming weeks Exp. 3: Flyback step-up dc-dc converter vHVDC Exp. 3 Part 1: Design and fabrication of flyback transformer Snubber circuit Demonstrate flyback converter power stage operating open loop Vbatt snubber Exp. 3 Part 2: PWM Compensator Construct, debug, and demonstrate paralleled flyback converters producing 85 W Exp. 3 Part 3: Design feedback loop Measure loop gain, compare with simulation and theory Demonstrate closed-loop control of converter output voltage ECEN 4517 3 –+ Vref Layout of power stage Identify loops having high di/dt (pulsating currents). Since v = L di/di, stray inductance in these loops leads to voltage spikes and ringing on components (usually the MOSFET) that can exceed their peak voltage ratings. Minimize the inductance of the critical loops: keep area of loop small, use twisted pairs, add bypass capacitors. ECEN 4517 4 Effect of transformer leakage inductance Transformer model Ll ig + vl – i 1:n LM Vg + D1 C R + – v – Q1 + – Voltage spike caused by leakage inductance { • Ll induces a voltage spike across Q1 Vg + v/n iRon t DTs ECEN 4517 • Leakage inductance is effectively in series with transistor Q1 • When MOSFET switches off, it interrupts the current in Ll vT(t) vT(t) • Leakage inductance Ll is caused by imperfect coupling of primary and secondary windings 4 If the peak magnitude of the voltage spike exceeds the voltage rating of the MOSFET, then the MOSFET will fail. Protection of Q1 using a voltage-clamp snubber Snubber { Flyback transformer ig – Rs Vg + – vs 1:n Cs + D1 C R v + – Q1 + vT(t) • Snubber provides a place for current in leakage inductance to flow after Q1 has turned off • Peak transistor voltage is clamped to Vg + vs • vs > V/n – • Energy stored in leakage inductance (plus more) is transferred to capacitor Cs, then dissipated in Rs Usually, Cs is large Decreasing Rs decreases the peak transistor voltage but increases the snubber power loss See supplementary flyback notes for an example of estimating Cs and Rs ECEN 4517 5 Overvoltage on output diode Diode turn-off (reverse recovery) transition: secondary induced voltage iL(t) L + – vL(t) vi(t) + – Silicon diode ig + vl – i Ll2 1:n + D1 LM Transformer leakage inductance causes voltage ringing and overshoot on secondary diode Leakage inductance plus diode output capacitance form resonant circuit: Transformer model Ll1 Vg C + – Q1 + vT(t) – iL(t) leakage inductance iB(t) + vB(t) – v – 0 diode capacitance Area – Qr t vB(t) t 0 C –V2 t1 ECEN 4517 R 6 t2 t3 Diode snubber Damp the ringing with R-C snubber network Transformer model Ll1 ig + vl1 – i 1:n Ll2 + – vl2 + LM Vg D1 Diode snubber C R + – v – Q1 + vT(t) – Snubber capacitance similar in value to diode capacitance Snubber resistance similar in value to resonant circuit characteristic impedance More capacitance and/or smaller resistance lower peak voltage, larger snubber loss ECEN 4517 7 Limits on maximum output power Week 1 circuit • • • • Wiring inductance causes ac component of iflyback to flow through capacitor C, while the dc component flows from the battery Capacitor rms current must not exceed the rating of 4.42 A Decreasing converter efficiency caused by snubber and other losses, along with capacitor current rating, limit the maximum output power How much output power can you produce? ECEN 4517 8 Increasing the output power Week 2 circuit Interleaving of parallel-connected flyback converters: AC components of phase-shifted • input current waveforms partially cancel out • Less rms capacitor current per unit of output power ECEN 4517 Produce 85 W output power by end of week 2 9 Exp. 3 Part 3 Regulation of output voltage via feedback vHVDC • Model and measure control-to-output transfer function Gvd(s) Vbatt snubber • Design and build feedback loop • Measure loop gain to verify phase margin and crossover frequency PWM • Demonstrate closed-loop regulation of vHVDC ECEN 4517 10 Compensator –+ Vref Negative feedback: a switching regulator system Power input Switching converter Load + vg + – iload v H(s) – Transistor gate driver Pulse-width vc Gc(s) modulator Compensator –+ Error signal ve Reference vref input ECEN 4517 11 Hv Sensor gain Transfer functions of some basic CCM converters Table 8.2. S alient features of the small-signal CCM transfer functions of some basic dc-dc converters Converter buck boost buck-boost Gg0 Gd0 D 1 D' D – D' V D V D' V 2 D D' 0 1 LC D' LC D' LC z Q C L D'R C L D'R C L R D' 2R L D' 2 R DL where the transfer functions are written in the standard forms Gvd(s) = Gd0 1 – s z 1 + s + s Q0 0 Gvg(s) = Gg0 2 1 1 + s + s Q0 0 2 Flyback: push L and C to same side of transformer, then use buck-boost equations. DC gains Gg0 and Gd0 have additional factors of n (turns ratio). ECEN 4517 12 Bode plot: control-to-output transfer function buck-boost or flyback converter example 80 dBV Gvd Gvd 60 dBV Gvd Gd0 = 187 V 45.5 dBV Q = 4 12 dB f0 40 dBV 400 Hz 20 dBV 0 dBV 10 -1/2Q f0 300 Hz 0˚ Gvd –20 dBV –40 dB/decade fz 0˚ 2.6 kHz RHP fz /10 260 Hz –40 dBV 10 f0 533 Hz 100 Hz 1 kHz 10 kHz f ECEN 4517 –90˚ –180˚ 10fz 26 kHz 1/2Q 10 Hz –20 dB/decade 13 –270˚ 100 kHz –270˚ 1 MHz The loop gain T(s) More loop gain ||T|| leads to better regulation of output voltage Power input Switching converter + vg + – iload v H(s) – Transistor gate driver Error signal ve Pulse-width vc Gc(s) modulator Compensator Reference vref input T(s) = Gvd(s) H(s) Gc(s) / VM Gvd(s) = power stage control-to-output transfer function PWM gain = 1/VM. VM = pk-pk amplitude of PWM sawtooth ECEN 4517 Load –+ Loop gain T(s) = product of gains around the feedback loop 14 Hv Sensor gain Phase Margin A test on T(s), to determine stability of the feedback loop The crossover frequency fc is defined as the frequency where || T(j2fc) || = 1, or 0 dB The phase margin m is determined from the phase of T(s) at fc , as follows: m = 180˚ + (T(j2fc)) If there is exactly one crossover frequency, and if T(s) contains no RHP poles, then the quantities T(s)/(1+T(s)) and 1/(1+T(s)) contain no RHP poles whenever the phase margin m is positive. ECEN 4517 15 Example: a loop gain leading to a stable closed-loop system T 60 dB T T 40 dB fp1 fz 20 dB 0 dB Crossover frequency fc T 0˚ –90˚ –20 dB m –40 dB –180˚ –270˚ 1 Hz 10 Hz 100 Hz f (T(j2fc)) = – 112˚ m = 180˚ – 112˚ = + 68˚ ECEN 4517 1 kHz 16 10 kHz 100 kHz Transient response vs. damping factor 2 Q = 50 v(t) Q = 10 Q=4 1.5 Q=2 Q=1 1 Q = 0.75 Q = 0.5 Q = 0.3 Q = 0.2 0.5 Q = 0.1 Q = 0.05 Q = 0.01 0 0 5 10 c t, radians ECEN 4517 17 15 Q vs. m 20 dB Q 15 dB 10 dB 5 dB 0 dB Q = 1 0 dB m = 52˚ –5 dB Q = 0.5 –6 dB m = 76˚ –10 dB –15 dB –20 dB 0 10 20 30 40 50 m ECEN 4517 18 60 70 80 90 8.4. Measurement of ac transfer functions and impedances Network Analyzer Injection source vz magnitude Measured inputs vz frequency vy vx vx input vy input + + – – + – vz output Fundamentals of Power Electronics Data 94 vy vx 17.3 dB Data bus to computer – 134.7˚ Chapter 8: Converter Transfer Functions Swept sinusoidal measurements • Injection source produces sinusoid vz of controllable amplitude and frequency • Signal inputs vx and vy perform function of narrowband tracking voltmeter: Component of input at injection source frequency is measured Narrowband function is essential: switching harmonics and other noise components are removed • Network analyzer measures vy vx Fundamentals of Power Electronics and vy ∠v x 95 Chapter 8: Converter Transfer Functions Measurement of an ac transfer function Network Analyzer Injection source vz magnitude Measured inputs Data vz frequency vx input vy input + + – vy vx – + – vz output vy vx Data bus to computer –4.7 dB – 162.8˚ vy(s) = G(s) vx(s) DC blocking capacitor input output G(s) • Injection sinusoid coupled to device input via dc blocking capacitor • Actual device input and output voltages are measured as vx and vy VCC DC bias adjust • Potentiometer establishes correct quiescent operating point • Dynamics of blocking capacitor are irrelevant Device under test Fundamentals of Power Electronics 96 Chapter 8: Converter Transfer Functions 9.6.1. Voltage injection – Block 1 Z1(s) 0 vref (s) +– ve (s) G1 (s) ve (s) + – vz + Zs(s) – Block 2 i(s) + vy (s) vx (s) + – Z2(s) G2 (s) vx (s) = v(s) Tv (s) H(s) • Ac injection source vz is connected between blocks 1 and 2 • Dc bias is determined by biasing circuits of the system itself • Injection source does modify loading of block 2 on block 1 Fundamentals of Power Electronics 64 Chapter 9: Controller design Averaged switch modeling Basic approach (CCM) Given a switching converter operating in CCM 1:n Vg Flyback converter example Separate the switching elements from the remainder of the converter + – + D1 C LM Q1 – + 1:n vg Define the terminal voltages and currents of the two-port switch network + – C LM + – v2 + v1 – 1 v – i1 i2 Q1 D1 Switch network ECEN 4517 V Terminal waveforms of the switch network v1(t) vg + v2/n 〈v1(t)〉T 0 vg 0 i1(t) 0 s dTs 0 Ts v2(t) ECEN 4517 iM 0 – Ts t dTs 0 – v2 + i2 Switch network Relationship between average terminal waveforms: d′(t) v1(t) T = v (t) nd(t) 2 T d′(t) i 2(t) T = i 1(t) T nd(t) s Ts t Ts t iM (t)/n s 0 dTs 2 v – i1 d(t) 0 0 C v1 nvg + v i2(t) 0 LM 〈i1(t)〉Ts dTs 〈i2(t)〉T + – + 〈v2(t)〉T 0 t iM (t) 0 + 1:n Averaged model of switch network From previous slide: d′(t) v1(t) T = v (t) nd(t) 2 T d′(t) i 2(t) T = i 1(t) T nd(t) 〈i1(t)〉Ts 〈i2(t)〉T + + 〈v1(t)〉Ts d′(t) v (t) nd(t) 2 T + – d′(t) i (t) nd(t) 1 T – Modeling the switch network via averaged dependent sources ECEN 4517 〈v2(t)〉Ts – Averaged switch network 3 s PSpice model CCM3 ********************************************************** * MODEL: CCM3 * Application: two-switch PWM converters, * with (possibly) transformer * Limitations: ideal switches, CCM only ********************************************************** * Parameters: * n=transformer turns ratio 1:n (primary:secondary) ********************************************************** * Nodes: * 1: transistor positive (drain of an n-channel MOS) * 2: transistor negative (source of an n-channel MOS) * 3: diode cathode * 4: diode anode * 5: duty cycle control input ********************************************************** .subckt CCM3 1 2 3 4 5 +params: n=1 Et 1 2 value={(1-v(5))*v(3,4)/v(5)/n} Gd 4 3 value={(1-v(5))*i(Et)/v(5)/n} .ends *$ ********************************************************** ECEN 4517 4 i 1(t) + v1(t) – i 2(t) Ts 1 CCM3 3 Ts + v2(t) Ts 2 4 5 d Included in the file Switch.lib on course website – Ts PSPICE simulation Open-loop simulation of control-to-output transfer function + 1:n vg + – LM C iM v – 1 2 CCM3 3 4 5 d • Replace flyback converter switches with averaged switch model • CCM3 and other PSPICE model library elements are linked on course web page • Apply dc voltage (to set steady-state duty cycle) plus ac variation to terminal 5 of CCM3. Plot output voltage magnitude and phase ECEN 4517 5

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