ITS18951212

ITS18951212
ISL36411
Features
The ISL36411 is a settable quad receive-side equalizer
with extended functionality for advanced protocols
operating with line rates up to 11.1Gbps such as
InfiniBand (QDR) and 40G Ethernet (40GBase-CR4/
SR4). The ISL36411 compensates for the frequency
dependent attenuation of copper twin-axial cables,
extending the signal reach up to at least 10m on 28AWG
cable.
The small form factor, highly-integrated quad design is
ideal for high-density data transmission applications
including active copper cable assemblies. The four
equalizing filters within the ISL36411 can each be set to
provide optimal signal fidelity for a given media and
length. The compensation level for the filters is set by
two external control pins.
Operating on a single 1.2V power supply, the ISL36411
enables per channel throughputs of 10Gbps to 11.1Gbps
while supporting lower data rates including 8.5, 6.25, 5,
4.25, 3.125, and 2.5Gbps. The ISL36411 uses current
mode logic (CML) inputs/outputs and is packaged in a
4mmx7mm 46-lead QFN. Individual lane LOS support is
included for module applications.
• Supports four channels with data rates up to
11.1Gbps
• Low power (~110mW per channel)
• Low latency (<500ps)
• Four equalizers in 4mmx7mm QFN package for
straight route-through architecture and simplified
routing
• Equalizer boost is pin selectable
• Pin selectable equalizer boosts
• Supports 64b/66b encoded data - long run lengths
• Line silence preservation & individual lane LOS
support
• 1.2V power supply
• LOS support
Applications
• QSFP Active Copper Cable Modules
• InfiniBand QDR
• 40G Ethernet (40GBase-CR4/SR4)
• 100G Ethernet (100GBase-CR10/SR10)
• High-Speed Active Cable Assemblies
• High-Speed Printed Circuit Board (PCB) Traces
Benefits
• Thinner gauge cable
• Extends cable reach 3x
• Improved BER
Typical Application Circuit
Active Copper Cable Assembly
1.2V
Host Channel
Adapter
10nF
1.2V
100pF
VDD
10nF
CP LOSB
0.1µF
100pF
TDSBL
DE
VDD
0.1µF
IN1[P,N]
OUT1[P,N]
IN2[P,N]
OUT2[P,N]
0.1µF
OUT1[P,N]
0.1µF
Rx1[P,N]
0.1µF
IN2[P,N]
OUT2[P,N]
Rx2[P,N]
0.1µF
Tx2[P,N]
ISL36411
0.1µF
ISL35411
0.1µF
IN3[P,N]
OUT3[P,N]
0.1µF
IN4[P,N]
OUT4[P,N]
100pF
Fabric Switch
Connector Paddle Card
1
= 10m 28AWG
1.2V
DT
March 25, 2010
FN6965.1
1.2V
10nF
0.1µF
OUT3[P,N]
OUT4[P,N]
Rx4[P,N]
DT
100pF
IN3[P,N]
10nF
Tx4[P,N]
0.1µF
IN4[P,N]
0.1µF
Tx3[P,N]
Rx3[P,N]
Host ASIC
Host ASIC
Tx1[P,N]
8-Pair Differential 100O
Ω
Twin-Axial Cable
IN1[P,N]
Connector Paddle Card
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL36411
Quad Lane Extender
ISL36411
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
TEMP. RANGE
(°C)
PART MARKING
PACKAGE
(Pb-Free)
PKG. DWG. #
ISL36411DRZ-TS
ISL36411DRZ
0 to +85
46 Ld QFN (7’’ 100 pcs.)
L46.4x7
ISL36411DRZ-T7
ISL36411DRZ
0 to +85
46 Ld QFN (7” 1k pcs.)
L46.4x7
NOTES:
1. “-TS” and “-T7” suffix is for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL36411. For more information on MSL please
see techbrief TB363.
Pin Configuration
VDD
GND
NC
CP1A
CP1B
DT1
NC
GND
ISL36411
(46 LD QFN)
TOP VIEW
46 45 44 43 42 41 40 39
VDD
1
38 OUT1[P]
IN1[P]
2
37 OUT1[N]
IN1[N]
3
36 VDD
LOSB1
4
35 VDD
VDD
5
34 OUT2[P]
IN2[P] 6
33 OUT2[N]
IN2[N] 7
32 VDD
EXPOSED PAD
(GND)
LOSB2 8
31 VDD
VDD 9
30 OUT3[P]
IN3[P] 10
29 OUT3[N]
IN3[N] 11
28 VDD
LOSB3 12
27 VDD
VDD 13
26 OUT4[P]
IN4[P] 14
25 OUT4[N]
IN4[N] 15
24 VDD
2
GND
NC
NC
CP2B
CP2A
DT2
GND
LOSB4
16 17 18 19 20 21 22 23
FN6965.1
March 25, 2010
ISL36411
Pin Functions and Definitions
PIN NAME
PIN NUMBER
DESCRIPTION
VDD
1, 5, 9, 13, 24,
27, 28, 31, 32,
35, 36, 39
Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to
ground is recommended for each of these pins for broad high-frequency noise suppression.
IN1[P, N]
2, 3
Equalizer 1 differential input, CML. the use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
LOSB1
4
IN2[P, N]
6, 7
LOSB2
8
IN3[P, N]
10, 11
LOSB3
12
IN4[P, N]
14, 15
LOSB4
16
GND
17, 23, 40, 46
DT2
18
Detection Threshold for equalizers 3 and 4. Reference DC voltage threshold for input signal
power detection. Data output OUT3 and OUT4 are muted when the power of IN3 and IN4,
respectively, fall below the threshold. Tie to ground to disable electrical idle preservation and
always enable the limiting amplifier.
CP2[A,B]
19, 20
Control pins for setting equalizers 3 and 4. CMOS logic inputs. Pins are read as a 2-digit number
to set the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a
25kΩ resistor.
NC
21, 22, 41, 45
OUT4[N, P]
25, 26
Equalizer 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
OUT3[N, P]
29, 30
Equalizer 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
OUT2[N, P]
33, 34
Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
OUT1[N, P]
37, 38
Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
CP1[B, A]
42, 43
Control pins for setting equalizers 1 and 2. CMOS logic inputs. Pins are read as a 2-digit number
to set the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a
25kΩ resistor.
DT1
44
Detection Threshold for equalizers 1 and 2. Reference DC voltage threshold for input signal
power detection. Data output OUT1 and OUT2 are muted when the power of IN1 and IN2,
respectively, fall below the threshold. Tie to ground to disable electrical idle preservation and
always enable the limiting amplifier.
Exposed Pad
-
LOS BAR indicator 1. Low output when IN1 signal is below DT threshold.
Equalizer 2 differential input, CML. the use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
LOS BAR indicator 2. Low output when IN2 signal is below DT threshold.
Equalizer 3 differential input, CML. the use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
LOS BAR indicator 3. Low output when IN3 signal is below DT threshold.
Equalizer 4 differential input, CML. the use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
LOS BAR indicator 4. Low output when IN4 signal is below DT threshold.
These pins should be grounded.
not connected: do not make any connections to these pins.
Exposed ground pad. For proper electrical and thermal performance, this pad should be
connected to the PCB ground plane.
3
FN6965.1
March 25, 2010
ISL36411
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD to GND).
Voltage at All Input Pins . . . .
ESD Ratings
Human Body Model
High-Speed Pins . . . . . . .
All Other Pins . . . . . . . . .
Thermal Resistance (Typical)
. . . . . . . . . . . . -0.3V to 1.5V
. . . . . . . . . . . . -0.3V to 1.5V
. . . . . . . . . . . . . . . . . . 1.5kV
. . . . . . . . . . . . . . . . . . . 2kV
θJA (°C/W) θJC (°C/W)
46 Ld QFN Package (Notes 4, 5) . .
33
2.8
Operating Ambient Temperature Range. . . . . . 0°C to +85°C
Storage Ambient Temperature Range . . . . . -55°C to +150°C
Maximum Junction Temperature. . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTE:
4. θJA measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Operating Conditions
PARAMETER
SYMBOL
Supply Voltage
Operating Ambient Temperature
Bit Rate
CONDITION
MIN
TYP
MAX
UNITS
VDD
1.1
1.2
1.3
V
TA
0
25
85
°C
11.1
Gbps
NRZ data applied to any channel
2.5
Control Pin Characteristics VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise noted.
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Output LOW Logic Level
VOL
LOS[k]
0
250
mV
Output HIGH Logic Level
VOH
LOS[k]
750
VDD
mV
200
µA
Input Current
Current draw on digital pin, i.e.,
CP[k][A,B]
Electrical Specifications
PARAMETERS
VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise noted.
SYMBOL
Supply Current
IDD
Cable Input Amplitude
Range
VIN
100
CONDITION
MIN
TYP
MAX
368
Measured differentially at data source
before encountering channel loss; Up to
10m 28AWG standard twin-axial cable
(approx. -27dB @ 5GHz)
600
UNITS
mA
1600
mVP-P
DC Differential Input
Resistance
Measured on input channel IN[k]
80
100
120
Ω
DC Single-Ended Input
Resistance
Measured on input channel IN[k]P or
IN[k]N, with respect to VDD
40
50
60
Ω
Input Return Loss Limit
(Differential)
SDD11
Input Return Loss Limit
(Common Mode)
SCC11
Input Return Loss Limit
(Com. to Diff. Conversion)
SDC11
Output Amplitude Range
VOUT
Differential Output
Impedance
6
100MHz to 4.1GHz
Note 7
dB
7
4.1GHz to 11.1GHz
Note 8
dB
8
100MHz to 2.5GHz
Note 9
dB
9
2.5GHz to 11.1GHz
-3
dB
14
100MHz to 11.1GHz
-10
dB
14
Measured differentially at OUT[k]P and
OUT[k]N with 50Ω load on both output
pins
Measured on OUT[k]
4
NOTES
450
600
850
mVP-P
80
105
120
Ω
FN6965.1
March 25, 2010
ISL36411
Electrical Specifications
PARAMETERS
VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise noted. (Continued)
SYMBOL
Output Return Loss Limit
(Differential)
SDD22
Output Return Loss Limit
(Common Mode)
SCC22
Output Return Loss Limit
(Com. to Diff. Conversion)
SDC22
Output Residual Jitter
Output Transition Time
tr, tf
CONDITION
MIN
TYP
MAX
UNITS
NOTES
100MHz to 4.1GHz
Note 7
dB
7
4.1MHz to 11.1GHz
Note 8
dB
8
100MHz to 2.5GHz
Note 9
dB
9
2.5MHz to 11.1GHz
-3
dB
14
100MHz to 11.1GHz
-10
dB
14
10Gbps; Up to 10m 28AWG std twinaxial cable (~ -27dB @ 5GHz);
1200mVP-P ≤ VIN ≤ 1600mVP-P
0.35
UI
6, 10,
11
32
ps
12
50
ps
14
500
ps
14
20% to 80%
Lane-to-Lane Skew
Propagation Delay
From IN[k] to OUT[k]
LOS Assert Time
Time to assert Loss-of-Signal indicator
when transitioning from active data
mode to line silence mode
50
µs
13
LOS De-Assert Time
Time to assert Loss-of-Signal indicator
when transitioning from line silence
mode to active data mode
50
µs
13
Data-to-Line Silence
Response Time
K28.5 data pattern at 10Gbps
100
µs
13
Data-to-Line Silence
Response Time
K28.5 data pattern at 10Gbps
100
µs
13
NOTES:
6. After channel loss, differential amplitudes at ISL36411 inputs must meet the input voltage range specified in “Absolute
Maximum Ratings” on page 4.
7. Maximum Reflection Coefficient given by equation SDDXX(dB)= -12 + 2*√(f), with f in GHz. Established by characterization
and not production tested.
8. Maximum Reflection Coefficient given by equation SDDXX(dB)= -6.3+13Log10(f/5.5), with f in GHz. Established by
characterization and not production tested.
9. Reflection Coefficient given by equation SCCXX(dB) < -7 + 1.6*f, with f in GHz. Established by characterization and not
production tested.
10. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted
signal (as measured at the input to the channel). Total jitter (TJ) is DJPP + 14.1 x RJRMS.
11. Measured using a PRBS 27-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent,
media-induced loss only.
12. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
13. For active data mode, cable input amplitude is 300mVP-P (differential) or greater. For line silence mode, cable input amplitude
is 20mVP-P (differential) or less. Established by characterization and not production tested.
14. Limits established by characterization and are not production tested.
5
FN6965.1
March 25, 2010
ISL36411
Typical Performance Characteristics
Performance is measured using the test setup illustrated in Figure 1. The signal from the pattern generator is launched
into the twin-ax cable using an SMA adapter card. The chip evaluation board is connected to the output of the cable
through another adapter card. The ISL36411 output signal is then visualized on a scope to determine signal integrity
parameters such as jitter.
Pattern
Generator
SMA
Adapter
Card
Ω Twin-Axial
100O
Cable
SMA
Adapter
Card
ISL36411 Eval
Board
Oscilloscope
FIGURE 1. DEVICE CHARACTERIZATION SET UP
FIGURE 2. ISL36411 10.3125Gb/s OUTPUT FOR A 10M 28AWG CABLE
6
FN6965.1
March 25, 2010
CPB
CPA
ISL36411
Limiting
Amplifier
IN[P]
Output
Driver
OUT[P]
Adjustable
Equalizer
IN[N]
OUT[N]
Signal
Detector
DT
LOSB
FIGURE 3. FUNCTIONAL DIAGRAM OF A SINGLE CHANNEL WITHIN THE ISL36411
Operation
Adjustable Equalization Boost
The ISL36411 is an advanced quad lane-extender for
high-speed interconnects. A functional diagram of one of
the four channels in the ISL36411 is shown in Figure 3.
In addition to a robust equalization filter to compensate
for channel loss and restore signal fidelity, the ISL36411
contains unique integrated features to preserve special
signaling protocols typically broken by other equalizers.
The signal detect function is used to mute the channel
output when the equalized signal falls below the level
determined by the Detection Threshold (DT) pin voltage.
This function is intended to preserve periods of line
silence (“quiescent state” in InfiniBand contexts).
Furthermore, the output of the signal detect / DT
comparator is used as a loss of signal (LOS) indicator to
indicate the absence of a received signal.
As illustrated in Figure 3, the core of each high-speed
signal path in the ISL36411 is a sophisticated equalizer
followed by a limiting amplifier. The equalizer
compensates for skin loss, dielectric loss, and impedance
discontinuities in the transmission channel. Each
equalizer is followed by a limiting amplification stage that
provides a clean output signal with full amplitude swing
and fast rise-fall times for reliable signal decoding in a
subsequent receiver.
7
Each channel in the ISL36411 features a settable (in
pairs) equalizer for custom signal restoration. The
flexibility of this adjustable compensation architecture
enables signal fidelity to be optimized on a
channel-by-channel basis, providing support for a wide
variety of channel characteristics and data rates ranging
from 2.5Gbps to 11.1Gbps. Because the boost level is
externally set rather than internally adapted, the
ISL36411 provides reliable communication from the very
first bit transmitted. There is no time needed for
adaptation and control loop convergence. Furthermore,
there are no pathological data pat-terns that will cause
the ISL36411 to move to an incorrect boost level.
Control Pin Boost Setting
The connectivity of the CP pins is used to determine the
boost level of each pair of channels. CP1 controls the
boost of channels 1 and 2, CP2 controls the boosts of
channels 3 and 4. Table 1 defines the mapping from the
2-bit CP word to the 8 possible boost levels.
TABLE 1. MAPPING BETWEEN BOOST LEVEL AND
CP-PIN CONNECTIVITY
CPA
CPB
BOOST LEVEL
Float
Float
0
Float
GND
1
GND
VDD
2
Float
VDD
3
VDD
Float
4
GND
Float
5
GND
GND
6
VDD
GND
7
VDD
VDD
8
FN6965.1
March 25, 2010
ISL36411
ISL36411 CML Input and Output Buffers
LOS Bar Indicator
The input and output buffers for the high-speed data
channels in the ISL36411 are implemented using CML
(shown in Figures 4 and 5).
Pins LOSB[k] are used to output the state of the muting
circuitry to serve as a loss of signal indicator for channel
k. This signal is directly derived from the muting signal
off the DT-threshold signal detector output. The LOS
signal goes LOW when the power signal is below the DT
threshold and HIGH when the power goes above the DT
threshold. This feature is meant to be used in optical
systems (e.g. QSFP) where there are no quiescent or
electrical-idle states. In these cases, the DT threshold is
used to determine the sensitivity of the LOS indicator.
V DD
IN[P]
Ω
50O
Detection Thereshold (DT) Pin Functionality
st
1 Filter
Stage
Ω
50O
IN[N]
FIGURE 4. CML INPUT EQUIVALENT CIRCUIT
The ISL36411 is capable of maintaining periods of line
silence by monitoring the channel for loss of signal (LOS)
conditions and subsequently muting the output driver
when such a condition is detected. A reference voltage
applied to the detection threshold (DT) pins is used to set
the LOS threshold of the internal signal detection
circuitry (one pin for a pair of channels). The DT voltage
is set with an external pull-up resistor, RDT. For typical
applications, a 15kΩ resistor is recommended for
channels with loss greater than 12dB at 5GHz, and a
0.9kΩ resistor is recommended for lower loss channels.
Other values of the resistor may also be applicable;
therefore DT settings should be verified on an
application-specific basis.
PCB Layout Considerations
Because of the high speed of the ISL36411 signals,
careful PCB layout is critical to maximize performance.
The following guidelines should be adhered to as closely
as possible:
• All high speed differential pair traces should have a
characteristic impedance of 50Ω with respect to
ground plane and 100Ω with respect to each other.
• Avoid using vias for high speed traces as this will
create discontinuity in the traces’ characteristic
impedance.
FIGURE 5. CML OUTPUT EQUIVALENT CIRCUIT
LINE SILENCE/QUIESCENT MODE
Line silence is commonly broken by the limiting
amplification in other equalizers. This disruption can be
detrimental in many systems that rely on line silence as
part of the protocol. The ISL36411 contains special lane
management capabilities to detect and preserve periods
of line silence while still providing the fidelity-enhancing
benefits of limiting amplification during active data
transmission. Line silence is detected by measuring the
amplitude of the equalized signal and comparing that to
a threshold set by the voltage at the DT pin. When the
amplitude falls below the threshold, the output driver
stages are muted and held at their nominal common
mode voltage1.
• Input and output traces need to have DC blocking
capacitors (100nF). Capacitors should be placed as
close to the chip as possible.
• For each differential pair, the positive trace and the
negative trace need to be of the same length in order
to avoid intra-pair skew. A Serpentine technique may
be used to match trace lengths.
• Maintain a constant solid ground plane underneath
the high-speed differential traces.
• Each VDD pin should be connected to 1.2V and also
bypassed to ground through a 10nF and a 100pF
capacitor in parallel. Minimize the trace length and
avoid vias between the VDD pin and the bypass
capacitors in order to maximize the power supply
noise rejection.
• If 4 channels of the device are set to the same boost,
then the quantity of CP resistors can be reduced by
tying both CP pins together.
1. The output common mode voltage remains constant during both active data transmission and output muting modes
8
FN6965.1
March 25, 2010
ISL36411
Application Information
Typical application schematic for ISL36411 is shown in Figure 6.
IN1[P]
IN1[N]
LOSB1
1.2V
1.2V
GND
NC
39
40
41
CP1[B]
A
42
CP1[A]
43
44
DT1
NC
45
1.2V
46
GND
EQ Boost
Control
for Channels
1 and 2
1
38
2
37
3
36
4
35
5
34
IN2[P]
6
LOSB2
1.2V
IN3[P]
IN3[N]
33
ISL36411
IN2[N]
7
32
8
31
OUT1[N]
1.2V
1.2V
OUT2[P]
OUT2[N]
1.2V
1.2V
OUT3[P]
9
30
10
29
11
28
12
27
13
26 OUT4[P]
14
25 OUT4[N]
15
24
OUT3[N]
LOSB3
1.2V
IN4[P]
OUT1[P]
1.2V
23
22
1.2V
GND
NC
21
NC
20
CP3[B]
19
17
18
CP3[A]
DT2
GND
LOSB4
16
IN4[N]
1.2V
EQ Boost
Control
for Channels
3 and 4
100pF*
10nF
1.2V
Bypass circuit for each VDD pin
(*100pF capacitor should be positioned closest to the pin)
ISL36411
LANE EXTENDER
A) DC Blocking Capacitors = X7R or COG
0.1µF (>6GHz bandwidth)
NOTES:
15. See “Control Pin Boost Setting” on page 7 for information on how to connect the CP pins.
16. See “Detection Thereshold (DT) Pin Functionality” on page 8 for details on DT pin operation.
FIGURE 6. TYPICAL APPLICATION REFERENCE SCHEMATIC FOR ISL36411
9
FN6965.1
March 25, 2010
ISL36411
About Q:ACTIVE® Technology
Intersil has long realized that to enable the complex
server clusters of next generation datacenters, it is
critical to manage the signal integrity issues of electrical
interconnects. To address this, Intersil has developed its
groundbreaking Q:ACTIVE® product line. By integrating
its analog ICs inside cabling interconnects, Intersil is able
to achieve unsurpassed improvements in reach, power
consumption, latency, and cable gauge size as well as
increased airflow in tomorrow’s datacenters. This new
technology transforms passive cabling into intelligent
“roadways” that yield lower operating expenses and
capital expenditures for the expanding datacenter.
Intersil Lane Extenders allow greater reach over existing
cabling while reducing the need for thicker cables. This
significantly reduces cable weight and clutter, increases
airflow, and improves power consumption.
10
FN6965.1
March 25, 2010
ISL36411
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
3/16/10
FN6965.1
CHANGE
page 4
• Control pin characteristics:
VOL : delete typical “0”
• Input current: max 200, typ 100
page 5
• Output res jitter: 0.35
• In Entries from Lane-to-Lane Skew all the way down, all the numbers should
move to typ column
Added High-Speed pins to ESD Ratings as follows to Abs Max Ratings:
ESD Ratings
Human Body Model
High-Speed Pins 1.5kV
All Other Pins 2kV
Removed board footprint from page 10 due to information covered in outline drawing.
2/8/10
FN6965.0
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL36411
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN6965.1
March 25, 2010
ISL36411
Package Outline Drawing
L46.4x7
46 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (TQFN)
Rev 0, 9/09
2.80
4.00
42X 0.40
A
B
46
39
6
PIN 1
INDEX AREA
7.00
38
5.50 ±0.1
Exp. DAP
5.60
15
24
(4X)
6
PIN 1
INDEX AREA
1
0.05
46X 0.20 4
0.10 M C A B
SIDE VIEW
TOP VIEW
16
23
2.50 ±0.1
Exp. DAP
46X 0.40
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0.70 ±0.05
C
SEATING PLANE
0.05 C
SIDE VIEW
C
0.152 REF
5
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
( 3.80 )
( 2.50)
NOTES:
( 6.80 )
( 42X 0.40)
( 5.50 )
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
(46X 0.20)
either a mold or mark feature.
( 46 X 0.60)
TYPICAL RECOMMENDED LAND PATTERN
12
FN6965.1
March 25, 2010
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising