27” TFT TV (17MB15) SERVICE MANUAL

27” TFT TV (17MB15) SERVICE MANUAL
27” TFT TV
(17MB15)
SERVICE MANUAL
TABLE OF CONTENTS
1.
INTRODUCTION ...................................................................................................................................... 1
2.
TUNER...................................................................................................................................................... 1
3.
IF PART (TDA9886) ................................................................................................................................. 1
4.
MULTI STANDARD SOUND PROCESSOR ............................................................................................ 2
5.
VIDEO SWITCH TEA6415 ....................................................................................................................... 2
6.
AUDIO AMPLIFIER STAGE WITH TPA3002D2 ...................................................................................... 2
7.
MICROCONTROLLER ............................................................................................................................. 3
8.
EEPROM 24C32....................................................................................................................................... 3
9.
CLASS AB STEREO HEADPHONE DRIVER TDA1308 ......................................................................... 3
10.
SAW FILTERS.......................................................................................................................................... 3
11.
IC DESCRIPTIONS .................................................................................................................................. 4
11.1.
TEA6415C ......................................................................................................................................... 5
11.1.1.
General Description ................................................................................................................. 5
11.1.2.
Features .................................................................................................................................... 5
11.1.3.
Pinning ...................................................................................................................................... 5
11.2.
24LC02 .............................................................................................................................................. 6
11.2.1.
Description................................................................................................................................ 6
11.2.2.
Features .................................................................................................................................... 6
11.2.3.
Pinning ...................................................................................................................................... 6
11.3.
TCET1102G Optocoupler.................................................................................................................. 7
11.3.1.
General Description ................................................................................................................. 7
11.3.2.
General Features...................................................................................................................... 7
11.3.3.
Applications.............................................................................................................................. 8
11.4.
SVP-EX 52 ........................................................................................................................................ 8
11.4.1.
General Description ................................................................................................................. 8
11.5.
TL431 ................................................................................................................................................ 8
11.5.1.
General Description ................................................................................................................. 8
11.5.2.
Features..................................................................................................................................... 8
11.6.
24C32 ................................................................................................................................................ 8
11.6.1.
General Description ................................................................................................................. 8
11.6.2.
Features .................................................................................................................................... 8
11.6.3.
Pinning ...................................................................................................................................... 9
11.7.
74LVC14A ....................................................................................................................................... 10
11.7.1.
Description.............................................................................................................................. 10
11.7.2.
Features .................................................................................................................................. 10
11.7.3.
Pinning .................................................................................................................................... 10
11.8.
TEA6420.......................................................................................................................................... 11
11.8.1.
Features .................................................................................................................................. 11
11.8.2.
Description.............................................................................................................................. 11
11.8.3.
Pin Connections ..................................................................................................................... 11
11.9.
CS4334............................................................................................................................................ 11
11.9.1.
Features .................................................................................................................................. 11
11.9.2.
General Description ............................................................................................................... 11
11.9.3.
Pin Descriptions ..................................................................................................................... 12
11.10. GAL16LV8 ....................................................................................................................................... 12
11.10.1. Description.............................................................................................................................. 12
11.10.2. Features .................................................................................................................................. 12
11.10.3. Pin connections...................................................................................................................... 13
11.11. K6R4008V1D................................................................................................................................... 13
11.11.1. Description.............................................................................................................................. 13
11.11.2. Features .................................................................................................................................. 13
11.11.3. Pin Description ....................................................................................................................... 14
11.12. L6562............................................................................................................................................... 14
11.12.1. Features .................................................................................................................................. 14
11.12.2. Description.............................................................................................................................. 14
11.12.3. Pin Connections and Descriptions ...................................................................................... 15
11.13. LM1117............................................................................................................................................ 15
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11.13.1. General Description ............................................................................................................... 15
11.13.2. Features .................................................................................................................................. 15
11.13.3. Applications............................................................................................................................ 15
11.13.4. Connection Diagrams ............................................................................................................ 16
11.14. LM317.............................................................................................................................................. 16
11.14.1. General Description ............................................................................................................... 16
11.14.2. Features .................................................................................................................................. 16
11.14.3. Pin Description ....................................................................................................................... 16
11.15. LM809.............................................................................................................................................. 16
11.15.1. General Description ............................................................................................................... 16
11.15.2. Features .................................................................................................................................. 16
11.15.3. Pinning .................................................................................................................................... 17
11.16. MSP34X1G...................................................................................................................................... 17
11.16.1. Introduction ............................................................................................................................ 17
11.16.2. Features .................................................................................................................................. 18
11.16.3. Pin connections...................................................................................................................... 18
11.17. M29W040B...................................................................................................................................... 20
11.17.1. Description.............................................................................................................................. 20
11.17.2. Features .................................................................................................................................. 20
11.17.3. Pin Descriptions ..................................................................................................................... 21
11.18. MC33202 ......................................................................................................................................... 21
11.18.1. General Description ............................................................................................................... 21
11.18.2. Features .................................................................................................................................. 21
11.18.3. Pin Connections ..................................................................................................................... 21
11.19. PCF8574 ......................................................................................................................................... 22
11.19.1. General Description ............................................................................................................... 22
11.19.2. Features .................................................................................................................................. 22
11.19.3. Pinning .................................................................................................................................... 22
11.20. PI5V330........................................................................................................................................... 23
11.20.1. General Description ............................................................................................................... 23
11.21. SDA55XX (SDA5550)...................................................................................................................... 23
11.21.1. General description ............................................................................................................... 23
11.22. Sil 9993............................................................................................................................................ 23
11.22.1. General Description ............................................................................................................... 23
11.22.2. Features .................................................................................................................................. 24
11.23. NCP1014 ......................................................................................................................................... 24
11.23.1. General Description ............................................................................................................... 24
11.23.2. Features .................................................................................................................................. 24
11.23.3. Pin Connections and Descriptions ...................................................................................... 25
11.24. SN74CB3Q3305.............................................................................................................................. 25
11.24.1. General Description ............................................................................................................... 25
11.24.2. Features .................................................................................................................................. 25
11.24.3. Pin Connections ..................................................................................................................... 26
11.25. ST24LC21 ....................................................................................................................................... 26
11.25.1. Description.............................................................................................................................. 26
11.25.2. Features .................................................................................................................................. 26
11.25.3. Pin connections...................................................................................................................... 26
11.26. LM2576............................................................................................................................................ 27
11.26.1. General Description ............................................................................................................... 27
11.26.2. Features .................................................................................................................................. 27
11.26.3. Pin description ....................................................................................................................... 27
11.27. TDA1308 ......................................................................................................................................... 27
11.27.1. General Description ............................................................................................................... 27
11.27.2. Features .................................................................................................................................. 27
11.27.3. Pinning .................................................................................................................................... 28
11.28. TDA9886 ......................................................................................................................................... 28
11.28.1. General Description ............................................................................................................... 28
11.28.2. Features .................................................................................................................................. 28
11.28.3. Pinning .................................................................................................................................... 28
11.29. TPA3002D2 ..................................................................................................................................... 29
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11.29.1. General Description ............................................................................................................... 29
11.29.2. Features .................................................................................................................................. 29
11.29.3. Pinning .................................................................................................................................... 30
11.30. µPA672T.......................................................................................................................................... 31
11.30.1. General Description ............................................................................................................... 31
11.30.2. Features .................................................................................................................................. 31
11.30.3. Pin Connection ....................................................................................................................... 31
11.31. VPC3230D....................................................................................................................................... 31
11.31.1. General Description ............................................................................................................... 31
11.31.2. Pin Connections and Short Descriptions ............................................................................ 32
12.
SERVICE MENU SETTINGS ................................................................................................................. 33
12.1.
Picture Adjust .................................................................................................................................. 33
12.2.
SOUND1.......................................................................................................................................... 34
12.3.
SOUND 2......................................................................................................................................... 34
12.4.
Options ............................................................................................................................................ 34
12.5.
TV Norm .......................................................................................................................................... 35
12.6.
Features .......................................................................................................................................... 35
12.7.
Teletext............................................................................................................................................ 35
12.8.
Source ............................................................................................................................................. 35
12.9.
Menu Languages 1 & 2 ................................................................................................................... 35
13.
BLOCK DIAGRAM.................................................................................................................................... 1
14.
CIRCUIT DIAGRAM ................................................................................................................................. 1
15.
CIRCUIT DIAGRAMS ............................................................................................................................... 3
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1. INTRODUCTION
27” TFT TV is a progressive TV control system with built-in de-interlacer and scaler. It uses a
1366*768 panel with 16:9 aspect ratio. The TV is capable of operation in PAL, SECAM, NTSC
(playback) colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L’ including
German and NICAM stereo. Sound system output is supplying 2x8W (10%THD) for stereo 8Ω
speakers. The chassis is equipped with many inputs and outputs allowing it to be used as a center of a
media system.
It supports following peripherals:
2 SCART sockets
1 AV input (CVBS + Stereo Audio)
1 SVHS input
1 Stereo Headphone input
1 Component input (YPbPr + Stereo Audio)
1 D-Sub 15 PC input
1 HDMI input
1 Stereo audio input for PC
Audio line out is taken from the scart with given scart-to-line out connector
2. TUNER
The tuners used in the design are combined VHF, UHF tuners suitable for CCIR systems B/G, H, L, L’,
I/I’, and D/K. The tuning is available through the digitally controlled I2C bus (PLL). Below you will find
info on one of the Tuners in use.
General description of UV1316:
The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of
applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. The low
IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient
suppression of triple transient.
Features of UV1316:
1. Member of the UV1300 family small sized UHF/VHF tuners
2. Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K
3. Digitally controlled (PLL) tuning via I2C-bus
4. Off-air channels, S-cable channels and Hyper band
5. World standardised mechanical dimensions and world standard pinning
6. Compact size
7. Complies to “CENELEC EN55020” and “EN55013”
Pinning:
1.
Gain control voltage (AGC)
2.
Tuning voltage
3.
I²C-bus address select
4.
I²C-bus serial clock
5.
I²C-bus serial data
6.
Not connected
7.
PLL supply voltage
8.
ADC input
9.
Tuner supply voltage
10.
Symmetrical IF output 1
11.
Symmetrical IF output 2
:
4.0V, Max: 4.5V
:
:
:
Max: 5.5V
Min:-0.3V, Max: 5.5V
Min:-0.3V, Max: 5.5V
:
5.0V, Min: 4.75V, Max: 5.5V
:
33V, Min: 30V, Max: 35V
3. IF PART (TDA9886)
The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal
PLL. The following figure shows the simplified block diagram of the integrated circuit.
The integrated circuit comprises the following functional blocks:
VIF amplifier, Tuner and VIF-AGC, VIF-AGC detector, Frequency Phase-Locked Loop (FPLL) detector,
VCO and divider, Digital acquisition help and AFC, Video demodulator and amplifier, Sound carrier trap,
SIF amplifier, SIF-AGC detector, Single reference QSS mixer, AM demodulator, FM demodulator and
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acquisition help, Audio amplifier and mute time constant, I²C-bus transceivers and MAD (module
address), Internal voltage stabilizer.
4. MULTI STANDARD SOUND PROCESSOR
The MSP34x1G family of single-chip Multistandard Sound Processors covers the sound processing of
all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound
processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on
a single chip.
These TV sound processing ICs include versions for processing the multichannel television sound
(MTS) signal conforming to the standard recommended by the Broadcast Television Systems
Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is
performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard
(EIA-J) and the FM Stereo Radio standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for
BTSC and EIA-J. The MSP34x1G has optimum stereo performance without any adjustments.
5. VIDEO SWITCH TEA6415
In case of three or more external sources are used, the video switch IC TEA6415 is used. The main
function of this device is to switch 8 video-input sources on the 6 outputs.
Each output can be switched on only one of each input. On each input an alignment of the lowest level
of the signal is made (bottom of sync. top for CVBS or black level for RGB signals).
Each nominal gain between any input and output is 6.5dB.For D2MAC or Chroma signal the alignment
is switched off by forcing, with an external resistor bridge, 5VDC on the input. Each input can be used
as a normal input or as a MAC or Chroma input (with external Resistor Bridge). All the switching
possibilities are changed through the BUS. Driving 75ohm load needs an external resistor. It is possible
to have the same input connected to several outputs.
6. AUDIO AMPLIFIER STAGE WITH TPA3002D2
The TPA3004D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo
speakers. The TPA3004D2 can drive stereo speakers as low as 8 Ω. The high efficiency of the
TPA3004D2 eliminates the need for external heatsinks when playing music.
Stereo speaker volume is controlled with a dc voltage applied to the volume control terminal offering a
range of gain from –40 dB to 36 dB. Line outputs, for driving external headphone amplifier inputs, are
also dc voltage controlled with a range of gain from –56 dB to 20 dB.
An integrated 5-V regulated supply is provided for powering an external headphone amplifier.
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7. MICROCONTROLLER
The Micronas SDA 55xx TV microcontroller is dedicated to 8 bit applications for TV control and
provides dedicated graphic features designed for modern low class to mid range TV sets. The SDA
55xx provides also an integrated general purposefully 8051-compatible microcontroller with specific
hardware features especially suitable in TV sets. The microcontroller core has been enhanced to
provide powerful features such as memory banking, data pointers and additional interrupts, etc. The
internal XRAM consists of up to 16 kBytes. The microcontroller provides an internal ROM of up to 128
kBytes. ROMless versions can access up to 1 MByte of external RAM and ROM. The 8-bit
microcontroller runs at 33.33 MHz internal clock. SDA 55xx is realized in 0.25 micron technology with
2.5 V supply voltage for the core and 3.3 V for the I/O port pins to make them TTL compatible. Based
on the SDA 55xx microcontroller the MINTS software package was developed and provides dedicated
device drivers for many Micronas video & audio products and includes a full blown TV control SW for
the PEPER application chassis. The SDA 55xx is also supported with powerful design tools like
emulators from Hitex, Kleinhenz, iSystems, the Keil C51 Compiler and TEDIpro OSD development SW
by Tara Systems.
8. EEPROM 24C32
The Microchip Technology Inc. 24C32 is a 4Kx8 (32 Kbit) Electrically Erasable PROM. This device has
been developed for advanced, low power applications such as personal communications or data
acquisition. The 24C32 features an input cache for fast write loads with a capacity of eight 8-byte
pages, or 64 bytes. It also features a fixed 4K-bit block of ultra-high endurance memory for data that
changes frequently. The 24C32 is capable of both random and sequential reads up to the 32K
boundary. Functional address lines allow up to 8 - 24C32 devices on the same bus, for up to 256K bits
address space. Advanced CMOS technology makes this device ideal for low-power non-volatile code
and data applications.
9. CLASS AB STEREO HEADPHONE DRIVER TDA1308
The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package.
The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital
audio applications.
10. SAW FILTERS
K9656M:
Standard:
• B/G
• D/K
•I
• L/L’
Features
• TV IF audio filter with two channels
• Channel 1 (L’) with one pass band for sound carriers at 40.40 MHz (L’) and 39.75 MHz (L’- NICAM)
• Channel 2 (B/G, D/K, L, I) with one pass band for sound carriers between 32.35 MHz and 33.40 MHz
Terminals
• Tinned CuFe alloy
Pin configuration
1 Input
2 Switching input
3 Chip carrier - ground
4 Output
5 Output
K3958M:
Standard:
• B/G
• D/K
•I
• L/L’
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Features
• TV IF video filter with Nyquist slopes at 33.90 MHz and 38.90 MHz
• Constant group delay
Terminals
Tinned CuFe alloy
Pin configuration
1 Input
2 Input - ground
3 Chip carrier - ground
4 Output
5 Output
11. IC DESCRIPTIONS
TEA6415C
24LC02
4MX32 DDR SDRAM (128M)
TCET1102G OPTOCOUPLER
SVP-EX 52
TL431
24C32
74LVC14A
TEA6420D
CS4334
GAL16LV8
K6R4008V1
L6562D
LM1086
LM1117
LM317T
LM809
MSP3410G
M29W040B
MC33202
PCF8574
PI5V330
SDA5550
SG3525
SII9993
NCP1014
SN74CB3Q3305
ST24LC21
LM2576
MC34063
TDA1308
TDA9886T
TPA3002D2
µPA672T
VPC3230D
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11.1.
TEA6415C
11.1.1.
General Description
The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be
switched on only one of each input. On each input an alignment of the lowest level of the signal is made
(bottom of synch. top for CVBS or black level for RGB signals). Each nominal gain between any input
and output is 6.5dB. For D2MAC or Chroma signal the alignment is switched off by forcing, with an
external resistor bridge, 5 VDC on the input. Each input can be used as a normal input or as a MAC or
Chroma input (with external resistor bridge). All the switching possibilities are changed through the
BUS. Driving 75Ω load needs an external transistor. It is possible to have the same input connected to
several outputs. The starting configuration upon power on (power supply: 0 to 10V) is undetermined. In
this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1 word of 16
bits is necessary to determine one configuration.
11.1.2.
Features
• 20MHz Bandwidth
• Cascadable with another TEA6415C (Internal address can be changed by pin 7 voltage)
• 8 Inputs (CVBS, RGB, MAC, CHROMA,...)
• 6 Outputs
• Possibility of MAC or chroma signal for each input by switching-off the clamp with an external resistor
bridge
• Bus controlled
• 6.5dB gain between any input and output
• 55dB crosstalk at 5mHz
• Fully ESD protected
11.1.3.
1.
Input
2.
Data
Pinning
:
:
3.
4.
Input
Clock
:
:
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
Input
Input
Prog
Input
Vcc
Input
Input
Ground
Output
Output
Output
Output
Output
Output
Ground
Input
:
:
Max
Low level
High level
Max
Low level
High level
Max
Max
:
:
:
:
Max
12V
Max
Max
:
:
:
:
:
:
5.5Vpp,
5.5Vpp,
5.5Vpp,
5.5Vpp,
5.5Vpp,
5.5Vpp,
:
: 2Vpp, Input Current: 1mA, Max : 3mA
: -0.3V Max: 1.5V,
: 3.0V Max
: Vcc+0.5V
: 2Vpp, Input Current: 1mA,
Max
: 3mA
: -0.3V Max: 1.5V,
: 3.0V Max
: Vcc+0.5V
: 2Vpp, Input Current: 1mA, Max : 3mA
: 2Vpp, Input Current: 1mA, Max : 3mA
: 2Vpp, Input Current: 1mA, Max: 3mA
: 2Vpp, Input Current: 1mA, Max : 3mA
: 2Vpp, Input Current: 1mA, Max : 3mA
Min : 4.5Vpp
Min : 4.5Vpp
Min : 4.5Vpp
Min : 4.5Vpp
Min : 4.5Vpp
Min : 4.5Vpp
Max : 2Vpp, Input Current
: 1mA, Max
: 3mA
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11.2.
24LC02
11.2.1.
Description
The Microchip Technology Inc. 24AA02/24LC02B (24XX02*) is a 2 Kbit Electrically Erasable PROM.
The device is organized as one block of 256 x 8-bit memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.8V, with standby and active currents of only 1µA and 1mA,
respectively. The 24XX02 also has a page write capability for up to 8 bytes of data.
11.2.2.
Features
• Single supply with operation down to 1.8V
• Low-power CMOS technology
-1mA active current typical
-1µA standby current typical (I-temp)
• Organized as 1 block of 256 bytes (1 x 256 x 8)
• 2-wire serial interface bus, I2C™ compatible
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (24AA02) and 400 kHz (24LC02B) compatibility
• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 8 bytes
• 2ms typical write cycle time for page write
• Hardware write-protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles
• Data retention > 200 years
• 8-lead PDIP, SOIC, TSSOP and MSOP packages
• 5-lead SOT-23 package
• Pb-free finish available
• Available for extended temperature ranges:
-Industrial (I): -40°C to +85°C
-Automotive (E): -40°C to +125°C
11.2.3.
Pinning
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11.3.
TCET1102G Optocoupler
11.3.1.
General Description
The TCET110. / TCET2100/ TCET4100 consist of a phototransistor optically coupled to a gallium
arsenide infrared-emitting diode in a 4-lead up to 16-lead plastic dual inline package.
The elements are mounted on one lead frame using a coplanar technique, providing a fixed distance
between input and output for highest safety requirements.
11.3.2.
•
•
•
•
•
•
•
•
•
•
General Features
CTR offered in 9 groups
Isolation materials according to UL94-VO
Pollution
degree
(DIN/VDE 0110 / resp. IEC 664)
Climatic classification 55/100/21 (IEC 68 part 1)
Special construction:
Therefore, extra low coupling capacity of typical 0.2 pF, high Common Mode Rejection
Low temperature coefficient of CTR
G=Leadform10.16mm;
provides
creepage
distance
>
8
for TCET2100/ TCET4100 optional;
suffix letter 'G' is not marked on the optocoupler
Coupling System U
2
mm,
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11.3.3.
Applications
Circuits for safe protective separation against electrical shock according to safety class II (reinforced
isolation):
For appl. class I – IV at mains voltage ≤300 V
For appl. class I – III at mains voltage ≤600 V
According to VDE 0884, table 2, suitable for: Switch-mode power supplies, line receiver, computer
peripheral interface, microprocessor system interface.
11.4.
SVP-EX 52
11.4.1.
General Description
SVP EX52 supports two CVBS and one Svideo,two HD YPbPr component or PC RGB input and one
24-bit digital input ports.Supports HD YPbPr de-interlacing mode and 3D-comb video mode.
LVDS "single" port is built-in, supporting output resolution up to SXGA, 1280x1024x60P.
11.5.
TL431
11.5.1.
General Description
The TL431/TL431Aare three-terminal adjustable regulator series with a guaranteed thermal stability
over applicable temperature ranges. The output voltage may be set to any value between Vref
(approximately 2.5 volts) and 36 volts with two external resistors These devices have a typical dynamic
output impedance of 0.2W Active output circuitry provides a very sharp turn-on characteristic, making
these devices excel lent replacement for zener diodes in many applications.
11.5.2.
•
•
•
•
•
•
•
Features
Programmable Output Voltage to 36 Volts
Low Dynamic Output Impedance 0.20 Typical
Sink Current Capability of 1.0 to 100mA
Equivalent Full-Range Temperature Coefficient of
50ppm/°C Typical
Temperature Compensated For Operation Over Full Rated
Operating Temperature Range
Low Output Noise Voltage
Fast Turn-on Response
11.6.
24C32
11.6.1.
General Description
The Microchip Technology Inc. 24C32 is a 4K x 8 (32K bit) Serial Electrically Erasable PROM. This
device has been developed for advanced, low power applications such as personal communications or
data acquisition. The 24C32 features an input cache for fast write loads with a capacity of eight 8-byte
pages, or 64 bytes. It also features a fixed 4K-bit block of ultra-high endurance memory for data that
changes frequently. The 24C32 is capable of both random and sequential reads up to the 32K
boundary. Functional address lines allow up to 8 - 24C32 devices on the same bus, for up to 256K bits
address space. Advanced CMOS technology makes this device ideal for low-power non-volatile code
and data applications.
11.6.2.
Features
• Voltage operating range: 4.5V to 5.5V
- Peak write current 3 mA at 5.5V
- Maximum read current 150µA at 5.5V
- Standby current 1µA typical
• Industry standard two-wire bus protocol, I2C™ compatible
-Including 100 kHz and 400 kHz modes
• Self-timed write cycle (including auto-erase)
• Power on/off data protection circuitry
• Endurance:
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- 10,000,000 Erase/Write cycles guaranteed for High Endurance Block
- 10,000,000 E/W cycles guaranteed for Standard Endurance Block
• 8 byte page, or byte modes available
• 1 page x 8 line input cache (64 bytes) for fast write
loads
• Schmitt trigger, filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to 8 chips may be connected to the same bus for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• Temperature ranges:
-Commercial (C): 0°C to +70°C
-Industrial (I): -40°C to +85°C
11.6.3.
Pinning
PIN Function Table
PIN DESCRIPTIONS
A0, A1, A2 Chip Address Inputs
The A0...A2 inputs are used by the 24C32 for multiple device operation and conform to the two-wire
bus standard. The levels applied to these pins define the address block occupied by the device in the
address map. A particular device is selected by transmitting the corresponding bits (A2, A1, and A0) in
the control byte.
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an
open drain terminal; therefore the SDA bus requires a pull-up resistor to VCC (typical 10KQ for 100
kHz, 1KQ for 400 kHz).
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For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are
reserved for indicating the START and STOP conditions.
SCL Serial Clock
This input is used to synchronize the data transfer from and to the device.
11.7.
74LVC14A
11.7.1.
Description
The 74LVC14A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5V devices. This
feature allows the use of these devices as translators in a mixed 3.3 and 5V environment. The
74LVC14A provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
11.7.2.
Features
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard no.8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000V
MM EIA/JESD22-A115-A exceeds 200V.
• Specified from -40 to +85C and -40 to +125C.
11.7.3.
Pinning
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11.8.
TEA6420
11.8.1.
Features
• 5 Stereo Inputs
• 4 Stereo Outputs
• Gain Control 0/2/4/6dB/Mute for each Output
• Cascadable (2 different addresses)
• Serial Bus Controlled
• Very low Noise
• Very low Distortion
11.8.2.
Description
The TEA6420 switches 5 stereo audio inputs on4stereo outputs. All the switching possibilities are
changed through the I2C bus.
11.8.3.
11.9.
Pin Connections
CS4334
11.9.1.
Features
• Complete Stereo DAC System: Interpolation, D/A, Output Analog Filtering
• 24-Bit Conversion
• 96 dB Dynamic Range
• -88 dB THD+N
• Low Clock Jitter Sensitivity
• Single +5V Power Supply
• Filtered Line Level Outputs
• On-Chip Digital De-emphasis
• Popgaurd® Technology
• Functionally Compatible with CS4330/31/33
11.9.2.
General Description
The CS4334 family members are complete, stereo digital-to-analog output systems including
interpolation, 1-bitD/A conversion and output analog filtering in an 8-pinpackage. The CS4334/5/6/7/8/9
support all major audio data interface formats, and the individual devices differ only in the supported
interface format. The CS4334 family is based on delta-sigma modulation, where the modulator output
controls the reference voltage input to an ultra-linear analog low-pass filter. This architecture allows for
infinite adjustment of sample rate between 2 kHz and 100 kHz simply by changing the master clock
frequency. The CS4334 family contains on-chip digital de-emphasis, operates from a single +5V power
supply, and requires minimal support circuitry. These features are ideal for set-top boxes, DVD players,
SVCD players, and A/V receivers.
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11.9.3.
Pin Descriptions
11.10. GAL16LV8
11.10.1.
Description
The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance
available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5Vsignal levels. The
GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which
combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and efficiently.
The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and
supports all architectural features such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during
manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality
of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are
specified.
11.10.2.
Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
- 3.5 ns Maximum Propagation Delay
- Fmax = 250 MHz
- 2.5 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology
• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE
- JEDEC-Compatible 3.3V Interface Standard
- 5V Compatible Inputs
- I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C)
• ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/100% Yields
- High Speed Electrical Erasure (<100ms)
- 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
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• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- Glue Logic for 3.3V Systems
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
11.10.3.
Pin connections
11.11. K6R4008V1D
11.11.1.
Description
The K6R4008V1D is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288
words by 8 bits. TheK6R4008V1D uses 8 common input and output lines and has an output enable pin
which operates faster than address access time at read cycle. The device is fabricated using
SAMSUNG′s advanced CMOS process and designed for high-speed circuit technology. It is particularly
well suited for use in high-density high-speed system applications. The K6R4008V1D is packaged in a
400 mil 36-pin plastic SOJ and 44-pin plastic TSOP type II.
11.11.2.
Features
• Fast Access Time 8, 10ns(Max.)
• Low Power Dissipation
- Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
- Operating K6R4008V1D-08 : 80mA(Max.)
K6R4008V1D-10 : 65mA(Max.)
• Single 3.3 ±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R4008V1D-J : 36-SOJ-400
K6R4008V1D-K : 36-SOJ-400(Lead-Free)
K6R4008V1D-T : 44-TSOP2-400BF
K6R4008V1D-U : 44-TSOP2-400BF(Lead-Free)
• Operating in Commercial and Industrial Temperature range.
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11.11.3.
Pin Description
11.12. L6562
11.12.1.
Features
• TRANSITION-MODE CONTROL OF PFC PRE-REGULATORS
• PROPRIETARY MULTIPLIER DESIGN FOR MINIMUM THD OF AC INPUT CURRENT
• VERY PRECISE ADJUSTABLE OUTPUT OVERVOLTAGE PROTECTION
• ULTRA-LOW (≤70µA) START-UP CURRENT
• LOW (≤4 mA) QUIESCENT CURRENT
• EXTENDED IC SUPPLY VOLTAGE RANGE
• ON-CHIP FILTER ON CURRENT SENSE
• DISABLE FUNCTION
• 1% (@ Tj = 25 °C) INTERNAL REFERENCE VOLTAGE
11.12.2.
Description
The L6562 is a current-mode PFC controller operating in Transition Mode (TM). Pin-to-pin compatible
with the predecessor L6561, it offers improved performance. The highly linear multiplier includes a
special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with
an extremely low THD, even over a large load range.
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11.12.3.
Pin Connections and Descriptions
11.13. LM1117
11.13.1.
General Description
The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load
current. It has the same pin-out as National Semiconductor’s industry standard LM317. The LM1117 is
available in an adjustable version, which can set the output voltage from 1.25V to 13.8V with only two
external resistors. In addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V.
The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap
reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT223, TO-220, and TO-252 D-PAK packages. A minimum of 10µF tantalum capacitor is required at the
output to improve the transient response and stability.
11.13.2.
Features
• Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
• Space Saving SOT-223 Package
• Current Limiting and Thermal Protection
• Output Current 800mA
• Line Regulation 0.2% (Max)
• Load Regulation 0.4% (Max)
• Temperature Range
— LM1117 0°C to 125°C
— LM1117I -40°C to 125°C
11.13.3.
Applications
• 2.85V Model for SCSI-2 Active Termination
• Post Regulator for Switching DC/DC Converter
• High Efficiency Linear Regulators
• Battery Charger
• Battery Powered Instrumentation
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11.13.4.
Connection Diagrams
11.14. LM317
11.14.1.
General Description
This monolithic integrated circuit is an adjustable 3-terminal positive voltage regulator designed to
supply more than 1.5A of load current with an output voltage adjustable over a 1.2 to 37V. It employs
internal current limiting, thermal shut-down and safe area compensation.
11.14.2.
Features
• Output Current In Excess of 1.5A
• Output Adjustable Between 1.2V and 37V
• Internal Thermal Overload Protection
• Internal Short Circuit Current Limiting
• Output Transistor Safe Operating Area Compensation
• TO-220 Package
11.14.3.
Pin Description
11.15. LM809
11.15.1.
General Description
The LM809/810 microprocessor supervisory circuits can be used to monitor the power supplies in
microprocessor and digital systems. They provide a reset to the microprocessor during power-up,
power-down and brown-out conditions. The function of the LM809/810 is to monitor the VCC supply
voltage, and assert a reset signal whenever this voltage declines below the factory-programmed reset
threshold. The reset signal remains asserted for 240 ms after VCC rises above the threshold. The
LM809 has an active-low RESET output, while the LM810 has an active-high RESET output. Seven
standard reset voltage options are available, suitable for monitoring 5V, 3.3V, and 3V supply voltages.
With a low supply current of only 15µA, the LM809/810 are ideal for use in portable equipment.
11.15.2.
Features
• Precise monitoring of 3V, 3.3V, and 5V supply voltages
• Superior upgrade to MAX809/810
• Fully specified overtemperature
• 140 ms min. Power-On Reset pulse width, 240 ms typical
Active-low RESET Output(LM809)
Active-high RESET Output(LM810)
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• Guaranteed RESET Output valid for VCC≥1V
• Low Supply Current, 15µAtyp
• Power supply transient immunity
11.15.3.
Pinning
11.16. MSP34X1G
Multistandard Sound Processor Family
11.16.1.
Introduction
The MSP 34x1G family of single-chip Multistandard Sound Processors covers the sound processing of
all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound
processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on
a single chip. Figure shows a simplified functional block diagram of the MSP 34x1G.
The MSP 34x1G has all functions of the MSP 34x0G with the addition of a virtual surround sound
feature.
Surround sound can be reproduced to a certain extent with two loudspeakers. The MSP 34x1G
includes the Micronas virtualizer algorithm “3D-PANORAMA” which has been approved by the Dolby 1)
Laboratories for with the "Virtual Dolby Surround" technology. In addition, the MSP 34x1G includes the
“PAN-ORAMA” algorithm.
These TV sound processing ICs include versions for processing the multichannel television sound
(MTS) signal conforming to the standard recommended by the Broadcast Television Systems
Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is
performed alignment free.
Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo
Radio standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for
BTSC and EIA-J. The MSP 34x1G has optimum stereo performance without any adjustments.
The MSP 34x1G has built-in automatic functions: The IC is able to detect the actual sound standard
automat-ically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can
be evaluated internally with subsequent switching between mono/stereo/bilingual; no I 2 C interaction is
necessary (Automatic Sound Selection).
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Source Select
I2S bus interface consists of five pins:
1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling
cycle (32 kHz) are transmitted.
2. I2S_DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted.
3. I2S_CL: Gives the timing for the transmission of I2S serial data (1.024 MHz).
4. I2S_WS: The I2S_WS word strobe line defines the left and right sample.
11.16.2.
Features
• Standard Selection with single I2C transmission
• Automatic Standard Detection of terrestrial TV standards
• Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS
• Two selectable sound IF (SIF) inputs
• Automatic Carrier Mute function
• Interrupt output programmable (indicating status change)
• Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness
• AVC: Automatic Volume Correction
• Subwoofer output with programmable low-pass and complementary high-pass filter
• 5-band graphic equalizer for loudspeaker channel
• Spatial effect for loudspeaker channel
• Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs
• Complete SCART in/out switching matrix
• Two I2S inputs; one I2S output
• Dolby Pro Logic with DPL 351xA coprocessor
• All analog FM-Stereo A2 and satellite standards; AM-SECAM L standard
• Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM
• Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification)
• ASTRA Digital Radio (ADR) together with DRP 3510A
• All NICAM standards
• Korean FM-Stereo A2 standard
11.16.3.
Pin connections
NC = not connected; leave vacant
LV = if not used, leave vacant
OBL = obligatory; connect as described in circuit diagram
DVSS: if not used, connect to DVSS
AHVSS: connect to AHVSS
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Pin No.
Pin Name
Type
Connection
(if not used)
PLCC
68-pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
PSDIP
64-pin
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
-
PSDIP
52-pin
14
13
12
11
10
9
8
7
6
5
4
3
-
PQFP
80-pin
9
8
7
6
5
4
3
2
1
80
79
78
77
76
75
-
PLQFP
64-pin
8
7
6
5
4
3
2
1
64
63
62
61
60
59
58
-
ADR_WS
NC
ADR_DA
I2S_DA_IN1
I2S_DA_OUT
I2S_WS
I2S_CL
I2C_DA
I2C_CL
NC
STANDBYQ
ADR_SEL
D_CTR_I/O_0
D_CTR_I/O_1
NC
NC
NC
OUT
18
1
2
74
57
AUD_CL_OUT
OUT
LV
19
20
21
22
64
63
62
61
1
52
51
50
73
72
71
70
56
55
54
53
TP
XTAL_OUT
XTAL_IN
TESTEN
OUT
IN
IN
LV
OBL
OBL
OBL
23
60
49
69
52
ANA_IN2+
IN
AVSS via
56 pF/LV
24
59
48
68
51
ANA_IN-
IN
AVSS via
56 pF/LV
25
26
27
28
-
58
57
56
55
-
47
46
45
44
-
67
66
65
64
63
62
61
60
59
50
49
48
47
-
ANA_IN1+
AVSUP
AVSUP
NC
NC
AVSS
AVSS
MONO_IN
NC
IN
29
54
43
58
46
VREFTOP
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SC1_IN_R
SC1_IN_L
ASG1
SC2_IN_R
SC2_IN_L
ASG2
SC3_IN_R
SC3_IN_L
ASG4
SC4_IN_R
SC4_IN_L
NC
AGNDC
AHVSS
AHVSS
NC
NC
CAPL_M
AHVSUP
CAPL_A
SC1_OUT_L
SC1_OUT_R
VREF1
SC2_OUT_L
SC2_OUT_R
NC
NC
DACM_SUB
OUT
IN
OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN
IN
IN/OUT
IN/OUT
IN
LV
LV
LV
LV
LV
LV
LV
OBL
OBL
LV
OBL
OBL
LV
LV
LV
LV
LV
LV
OBL
OBL
LV
LV
OBL
OBL
LV
LV
OBL
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
LV
LV
AHVSS
LV
LV
AHVSS
LV
LV
AHVSS
LV
LV
LV or AHVSS
OBL
OBL
OBL
LV
LV
OBL
OBL
OBL
LV
LV
OBL
LV
LV
LV
LV
LV
Short Description
ADR word strobe
Not connected
ADR Data Output
2
I S1 data input
2
I S data output
2
I S word strobe
2
I S clock
2
I C data
2
I C clock
Not connected
Stand-by (low-active)
2
I C bus address select
D_CTR_I/O_0
D_CTR_I/O_1
Not connected
Not connected
Not connected
Audio clock output
(18.432 MHz)
Test pin
Crystal oscillator
Crystal oscillator
Test pin
IF Input 2 (can be left
vacant, only if IF input 1 is
also not in use)
IF common (can be left
vacant, only if IF input 1 is
also not in use)
IF input 1
Analog power supply 5V
Analog power supply 5V
Not connected
Not connected
Analog ground
Analog ground
Mono input
Not connected
Reference voltage IF A/D
converter
SCART 1 input, right
SCART 1 input, left
Analog Shield Ground 1
SCART 2 input, right
SCART 2 input, left
Analog Shield Ground 2
SCART 3 input, right
SCART 3 input, left
Analog Shield Ground 4
SCART 4 input, right
SCART 4 input, left
Not connected
Analog reference voltage
Analog ground
Analog ground
Not connected
Not connected
Volume capacitor MAIN
Analog power supply 8V
Volume capacitor AUX
SCART output 1, left
SCART output 1, right
Reference ground 1
SCART output 2, left
SCART output 2, right
Not connected
Not connected
Subwoofer output
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55
56
57
58
59
60
61
62
63
64
65
66
67
68
30
29
28
27
26
25
24
23
22
21
20
19
18
17
25
24
23
22
21
20
19
18
17
16
15
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
22
21
20
19
18
17
16
15
14
13
12
11
10
9
NC
DACM_L
DACM_R
VREF2
DACA_L
DACA_R
NC
NC
RESETQ
NC
NC
NC
I2S_DA_IN2
DVSS
DVSS
DVSS
DVSUP
DVSUP
DVSUP
ADR_CL
OUT
OUT
OUT
OUT
IN
IN
OUT
LV
LV
LV
OBL
LV
LV
LV
LV
OBL
LV
LV
LV
LV
OBL
OBL
OBL
OBL
OBL
OBL
LV
Not connected
Loudspeaker out, left
Loudspeaker out, right
Reference ground 2
Headphone out, left
Headphone out, right
Not connected
Not connected
Power-on-reset
Not connected
Not connected
Not connected
2
I S2-data input
Digital ground
Digital ground
Digital ground
Digital power supply 5V
Digital power supply 5V
Digital power supply 5V
ADR clock
11.17. M29W040B
11.17.1.
Description
The M29W040B is a 4 Mbit (512Kb x8) non-volatile memory that can be read, erased and
reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On
power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or
EPROM. The M29W040B is fully backward compatible with the M29W040.The memory is divided into
blocks that can be erased independently so it is possible to preserve valid data while old data is erased.
Each block can be protected independently to prevent accidental Program or Erase commands from
modifying the memory. Program and Erase commands are writ-ten to the Command Interface of the
memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the
memory by taking care of all of the special operations that are required to update the memory contents.
The end of a program or erase operation can be detected and any error conditions identified. The
command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output
Enable and Write Enable signals control the bus operation of the memory. They allow simple
connection to most microprocessors, often without additional logic.
11.17.2.
Features
• SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS
• ACCESS TIME: 55ns
• PROGRAMMING TIME
- 10µs per Byte typical8
• UNIFORM 64 Kbytes MEMORY BLOCKS
• PROGRAM/ERASE CONTROLLER
- Embedded Byte Program algorithm
- Embedded Multi-Block/Chip Erase algorithm
- Status Register Polling and Toggle Bits
• ERASE SUSPEND and RESUME MODES
- Read and Program another Block during Erase Suspend
• UNLOCK BYPASS PROGRAM COMMAND
- Faster Production/Batch Programming
• LOW POWER CONSUMPTION
- Standby and Automatic Standby
• 100,000 PROGRAM/ERASE CYCLES per BLOCK
• 20 YEARS DATA RETENTION
- Defectivity below 1 ppm/year
• ELECTRONIC SIGNATURE
- Manufacturer Code: 20h
- Device Code: E3h
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11.17.3.
Pin Descriptions
11.18. MC33202
11.18.1.
General Description
The MC33201/2/4 family of operational amplifiers provide rail−to−rail operation on both the input and
output. The inputs can be driven as high as 200mV beyond the supply rails without phase reversal on
the outputs, and the output can swing within 50 mV of each rail. This rail−to−rail operation enables the
user to make full use of the supply voltage range available. It is designed to work at very low supply
voltages (±0.9 V) yet can operate with a supply of up to +12V and ground. Output current boosting
techniques provide a high output current capability while keeping the drain current of the amplifier to a
minimum. Also, the combination of low noise and distortion with a high slew rate and drive capability
make this an ideal amplifier for audio applications.
11.18.2.
Features
• Low Voltage, Single Supply Operation (+1.8 V and Ground to +12 V and Ground)
• Input Voltage Range Includes both Supply Rails
• Output Voltage Swings within 50 mV of both Rails
• No Phase Reversal on the Output for Over−driven Input Signals
• High Output Current (ISC = 80 mA, Typ)
• Low Supply Current (ID = 0.9 mA, Typ)
• 600 Ω Output Drive Capability
• Extended Operating Temperature Ranges (−40° to +105°C and −55° to +125°C)
• Typical Gain Bandwidth Product = 2.2 MHz
• Pb−Free Packages are Available
11.18.3.
Pin Connections
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11.19. PCF8574
11.19.1.
General Description
The PCF8574 is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most
microcontroller families via the two-line bidirectional bus (I2C).The device consists of an 8-bit quasibidirectional port and an I2C-bus interface. The PCF8574 has a low current consumption and includes
latched outputs with high current drive capability for directly driving LEDs. It also possesses an interrupt
line (INT) which can be connected to the interrupt logic of the microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports
without having to communicate via the I2C-bus. This means that the PCF8574 can remain a simple
slave device.
11.19.2.
Features
• Operating supply voltage 2.5 to 6V
• Low standby current consumption of 10 µA maximum
• I2C to parallel port expander
• Open-drain interrupt output
• 8-bit remote I/O port for the I2C-bus
• Compatible with most microcontrollers
• Latched outputs with high current drive capability for directly driving LEDs
• Address by 3 hardware address pins for use of up to 8 devices (up to 16 with PCF8574A)
• DIP16, or space-saving SO16 or SSOP20 packages.
11.19.3.
Pinning
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11.20. PI5V330
11.20.1.
General Description
The PI5V330 is well suited for video applications when switching composite or RGB analogue. A
picture-in-picture application will be described in this brief. The pixel-rate creates video overlays so two
or more pictures can be viewed at the same time. An inexpensive NTSC titler can be implemented by
superimposing the output of a character generator on a standard composite video background.
11.21. SDA55XX (SDA5550)
11.21.1.
General description
The SDA55XX is a single chip teletext decoder for decoding World System Teletext data as well as
Video Programming System (VPS), Program Delivery Control (PDC), and Wide Screen Signalling
(WSS) data used for PAL plus transmissions (Line 23). The device also supports Closed caption
acquisition and decoding. The device provides an integrated general-purpose, fully 8051-compatible
Microcontroller with television specific hardware features. Microcontroller has been enhanced to provide
powerful features such as memory banking, data pointers, and additional interrupts etc. The on-chip
display unit for displaying Level 1.5 teletext data can also be used for customer defined on screen
displays. Internal XRAM consists of up to16 Kbytes. Device has an internal ROM of up to 128 KBytes.
ROMless versions can access up to 1 MByte of external RAM and ROM. The SDA 55XX supports a
wide range of standards including PAL, NTSC and contains a digital slicer for VPS, WSS, PDC, TTX
and Closed Caption, an accelerating acquisition hardware module, a display generator for Level 1.5
TTX data and powerful On screen Display capabilities based on parallel attributes, and Pixel oriented
characters (DRCS).
The 8-bit Microcontroller runs at 360 ns. cycle time (min.). Controller with dedicated hardware does
most of the internal TTX acquisition processing, transfers data to/from external memory interface and
receives/ transmits data via I2C-firmware user-interface. The slicer combined with dedicated hardware
stores TTX data in a VBI buffer of 1 Kilobyte. The Microcontroller firmware performs all the acquisition
tasks (hamming and parity-checks, page search and evaluation of header control bits) once per field.
Additionally, the firmware can provide high-end Teletext features like Packet-26-handling, FLOF, TOP
and list-pages. The interface to user software is optimized for minimal overhead. SDA 55XX is realized
in 0.25 micron technology with 2.5 V supply voltage and 3.3 V I/O (TTL compatible). The software and
hardware development environment (TEAM) is available to simplify and speed up the development of
the software and On Screen Display. TEAM stands for TVT Expert Application Maker. It improves the
TV controller software quality in following aspects:
– Shorter time to market
– Re-usability
– Target independent development
– Verification and validation before targeting
– General test concept
– Graphical interface design requiring minimum programming and controller know how.
– Modular and open tool chain, configurable by customer.
11.22. Sil 9993
11.22.1.
General Description
The SiI 9993 is the first generation of PanelLink receivers that are designed for the HDMI 1.0 (High
Definition Multimedia Interface) specification. DTVs, plasma displays, LCD TVs and projectors can now
provide the purest level of protected digital audio/video over a simple, low cost cable. Backwards
compatibility with DVI 1.0 allows HDMI systems to connect to any DVI 1.0 host (DVD players, HD set
top boxes, D-VHS players and receivers, PC). The SiI 9993 incorporates a flexible audio and video
interface. The receiver can connect to RGB input and output YCbCr using an integrated color space
converter. This allows full backward compatibility to DVI, and interfaces to all major video processors.
A S/PDIF port can output PCM encoded data as well as Dolby Digital, DTS and all other formats
capable of being sent over S/PDIF. A 2-channel I2S port outputs data converted from S/PDIF. The SiI
9993 comes pre-programmed with HDCP keys, greatly simplifying the manufacturing process, lowering
costs, all the while providing the highest level of HDCP key security. Silicon Image’s PanelLink
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receivers use the latest generation of PanelLink TMDS core technology. These PanelLink cores pass
all HDMI compliancy tests.
11.22.2.
Features
• HDMI 1.0 and DVI 1.0 compliant receiver
• Integrated PanelLink core supports DTV resolutions (480i/576i/480p/576p/720p/1080i)
• Digital video interface supports video processors:
o 24-bit RGB 4:4:4
o 24-bit YCbCr 4:4:4
o 16/20/24-bit YCbCr 4:2:2
o 8/10/12-bit YCbCr 4:2:2 embedded syncs
• Analog RGB and YPbPr output:
o 10-bit DAC
o Separate or Composite Syncs (Sync on G)
• S/PDIF output supports PCM, Dolby Digital, DTS digital audio transmission (32-48kHz Fs) using IEC
60958 and IEC 61937.
• Programmable I2S interface for connection to low-cost audio DACs.
• Integrated HDCP decryption engine for receiving protected audio and video content
• Pre-programmed HDCP keys provide highest level of key security, simplifies manufacturing
• Programmable registers via slave I2C interface
• 3.3V operation in 100-pin TQFP package
• Flexible power management
11.23. NCP1014
11.23.1.
General Description
The NCP101X series integrates a fixed−frequency current−modecontroller and a 700 V MOSFET.
Housed in a PDIP−7 or SOT−223package, the NCP101X offers everything needed to build a rugged
and low−cost power supply, including soft−start, frequency jittering, short−circuit protection, skip−cycle,
a maximum peak current setpoint and a Dynamic Self−Supply (no need for an auxiliary winding). Unlike
other monolithic solutions, the NCP101X is quiet by nature: during nominal load operation, the part
switches at one of the available frequencies (65−100−130 kHz). When the current setpoint falls below a
given value, e.g. the output power demand diminishes, the IC automatically enters the so−called skip
cycle mode and provides excellent efficiency at light loads. Because this occurs at typically 1/4 of the
maximum peak value, no acoustic noise takes place. As a result, standby power is reduced to the
minimum without acoustic noise generation. Short−circuit detection takes place when the feedback
signal fades away, e.g. in true short−circuit conditions or in broken Optocoupler cases. External
disabling is easily done either simply by pulling the feedback pin down or latching it to ground through
an inexpensive SCR for complete latched−off. Finally soft−start and frequency jittering further ease the
designer task to quickly develop low−cost and robust offline power supplies. For improved standby
performance, the connection of an auxiliary winding stops the DSS operation and helps to consume
less than100 mW at high line. In this mode, a built−in latched overvoltage protection prevents from
lethal voltage runaways in case the Optocoupler would brake.
11.23.2.
Features
• Built−in 700 V MOSFET with Typical RDSon of 11 Ω and 22 Ω
• Large Creepage Distance Between High−Voltage Pins
• Current−Mode Fixed Frequency Operation: 65 kHz–100 kHz−130 kHz
• Skip−Cycle Operation at Low Peak Currents Only: No Acoustic Noise!
• Dynamic Self−Supply, No Need for an Auxiliary Winding
• Internal 1.0 ms Soft−Start
• Latched Overvoltage Protection with Auxiliary Winding Operation
• Frequency Jittering for Better EMI Signature
• Auto−Recovery Internal Output Short−Circuit Protection
• Below 100 mW Standby Power if Auxiliary Winding is Used
• Internal Temperature Shutdown
• Direct Optocoupler Connection
• SPICE Models Available for TRANsient Analysis
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11.23.3.
Pin Connections and Descriptions
11.24. SN74CB3Q3305
11.24.1.
General Description
The SN74CB3Q3305 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate
voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ONstate resistance allows for minimal propagation delay and supports rail-to-rail switching on the data
input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive
loading and signal distortion on the data bus. Specifically designed to support high-bandwidth
applications, the SN74CB3Q3305 provides an optimized interface solution ideally suited for broadband
communications, networking, and data-intensive computing systems.
11.24.2.
Features
• High-Bandwidth Data Path (Up To 500 MHz)
• 5-V Tolerant I/Os with Device Powered-Up or Powered-Down
• Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 3 Ω Typical)
• Rail-to-Rail Switching on Data I/O Ports
− 0- to 5-V Switching With 3.3-V VCC
− 0- to 3.3-V Switching With 2.5-V VCC
• Bidirectional Data Flow, With Near-Zero Propagation Delay
• Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical)
• Fast Switching Frequency (fOE = 20 MHz Max)
• Data and Control Inputs Provide Undershoot Clamp Diodes
• Low Power Consumption (ICC = 0.25 mA Typical)
• VCC Operating Range From 2.3 V to 3.6 V
• Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
• Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II
• ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model (A114-B, Class II)
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− 1000-V Charged-Device Model (C101)
• Supports Both Digital and Analog Applications: USB Interface, Differential Signal Interface, Bus
Isolation, Low-Distortion Signal Gating
11.24.3.
Pin Connections
11.25. ST24LC21
11.25.1.
Description
The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits.
This device can operate in two modes: Transmit Only mode and I2C bidirectional mode. When powered,
the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal
applied on VCLK. The device will switch to the I2C bidirectional mode upon the falling edge of the signal
applied on SCL pin. The ST24LC21 can not switch from the I2C bidirectional mode to the Transmit Only
mode (except when the power supply is removed). The device operates with a power supply value as
low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available.
11.25.2.
Features
• 1 million Erase/Write cycles
• 40 years data retention
• 2.5V to 5.5V single supply voltage
• 400k Hz compatibility over the full range of supply voltage
• Two wire serial interface I2C bus compatible
• Page Write (Up To 8 Bytes)
• Byte, random and sequential read modes
• Self timed programming cycle
• Automatic address incrementing
• Enhanced ESD/Latch up
• Performances
11.25.3.
Pin connections
DIP Pin connections
CO Pin connections
NC: Not connected
Signal names
SDA
SCL
Vcc
Vss
VCLK
Serial data Address Input/Output
Serial Clock (I2C mode)
Supply voltage
Ground
Clock transmit only mode
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11.26. LM2576
11.26.1.
General Description
The LM2576 series of regulators are monolithic integrated circuits ideally suited for easy and
convenient design of a step–down switching regulator (buck converter). All circuits of this series are
capable of driving a 3.0 A load with excellent line and load regulation.
These devices are available in fixed output voltages of 3.3 V, 5.0 V, 12 V, 15 V, and an adjustable
output version. These regulators were designed to minimize the number of external components to
simplify the power supply design. Standard series of inductors optimized for use with the LM2576 are
offered by several different inductor manufacturers.
Since the LM2576 converter is a switch–mode power supply, its efficiency is significantly higher in
comparison with popular three–terminal linear regulators, especially with higher input voltages. In many
cases, the power dissipated is so low that no heatsink is required or its size could be reduced
dramatically.
A standard series of inductors optimized for use with the LM2576 are available from several different
manufacturers. This feature greatly simplifies the design of switch–mode power supplies.
The LM2576 features include a guaranteed ±4% tolerance on output voltage within specified input
voltages and output load conditions, and ±10% on the oscillator frequency (±2% over 0°C to 125°C).
External shutdown is included, featuring 80 mA (typical) standby current. The output switch includes
cycle–by–cycle current limiting, as well as thermal shutdown for full protection under fault conditions.
11.26.2.
Features
• 3.3 V, 5.0 V, 12 V, 15 V, and Adjustable Output Versions
• Adjustable Version Output Voltage Range, 1.23 to 37 V ±4% Maximum Over Line and Load
Conditions
• Guaranteed 3.0 A Output Current
• Wide Input Voltage Range
• Requires Only 4 External Components
• 52 kHz Fixed Frequency Internal Oscillator
• TTL Shutdown Capability, Low Power Standby Mode
• High Efficiency
• Uses Readily Available Standard Inductors
• Thermal Shutdown and Current Limit Protection
• Moisture Sensitivity Level (MSL) Equals 1
11.26.3.
Pin description
11.27. TDA1308
11.27.1.
General Description
The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic
package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for
portable digital audio applications.
11.27.2.
Features
• Wide temperature range
• No switch ON/OFF clicks
• Excellent power supply ripple rejection
• Low power consumption
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• Short-circuit resistant
• High performance
• high signal-to-noise ratio
• High slew rate
• Low distortion
• Large output voltage swing.
11.27.3.
SYMBOL
OUTA
INA(neg)
INA(pos)
VSS
INB(pos)
INB(neg)
OUTB
VDD
Pinning
PIN
1
2
3
4
5
6
7
8
DESCRIPTION
Output A (Voltage swing)
Inverting input A
Non-inverting input A
Negative supply
Non-inverting input B
Inverting input B
Output B (Voltage swing)
Positive supply
PIN VALUE
Min : 0.75V, Max : 4.25V
Vo(clip) : Min : 1400mVrms
2.5V
0V
2.5V
Vo(clip) : Min : 1400mVrms
Min : 0.75V, Max : 4.25V
5V, Min : 3.0V, Max : 7.0V
11.28. TDA9886
11.28.1.
General Description
The TDA9886 is an alignment-free single standard (without positive modulation) vision and sound IF
signal PLL.
11.28.2.
Features
• 5 V supply voltage
• Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (AC-coupled)
• Multistandard true synchronous demodulation with active carrier regeneration (very linear
demodulation, good intermodulation figures, reduced harmonics, excellent pulse response)
• Gated phase detector for L/L accent standard
• Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free; frequencies switchable for all
negative and positive modulated standards via I2C-bus
• Digital acquisition help, VIF frequencies of 33.4, 33.9, 38.0, 38.9, 45.75 and 58.75 MHz
• 4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning system] or operating
as crystal oscillator
• VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for
negative modulated signals and as a peak white detector for positive modulated signals
• Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analogue
converter; AFC bits via I2C -bus readable
• TakeOver Point (TOP) adjustable via I2C-bus or alternatively with potentiometer
• Fully integrated sound carrier trap for 4.5, 5.5, 6.0 and 6.5 MHz, controlled by FM-PLL oscillator
• Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode (PLL controlled)
• SIF AGC for gain controlled SIF amplifier; single reference QSS mixer able to operate in high
performance single reference QSS mode and in intercarrier mode, switchable via I2C-bus
• AM demodulator without extra reference circuit
• Alignment-free selective FM-PLL demodulator with high linearity and low noise
• I2C-bus control for all functions
• I2C-bus transceiver with pin programmable Module Address (MAD).
11.28.3.
Pinning
SYMBOL
VIF1
PIN
1
2
3
4
VIF2
OP1
FMPLL
DESCRIPTION
VIF differential input 1
VIF differential input 2
output 1 (open-collector)
FM-PLL for loop filter
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DEEM
AFD
DGND
AUD
TOP
SDA
SCL
SIOMA
n.c.
TAGC
REF
VAGC
CVBS
AGND
VPLL
VP
AFC
OP2
SIF1
SIF2
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
de-emphasis output for capacitor
AF decoupling input for capacitor
digital ground
audio output
tuner AGC TakeOver Point (TOP)
I2C-bus data input/output
I2C-bus clock input
sound intercarrier output and MAD select
not connected
tuner AGC output
4 MHz crystal or reference input
VIF-AGC for capacitor; note 1
video output
analog ground
VIF-PLL for loop filter
supply voltage (+5 V)
AFC output
output 2 (open-collector)
SIF differential input 1
SIF differential input 2
11.29. TPA3002D2
11.29.1.
General Description
The TPA3002D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied
stereo speakers. The TPA3002D2 can drive stereo speakers as low as 8 O. The high efficiency of the
TPA3002D2 eliminates the need for external heatsinks when playing music.
Stereo speaker volume is controlled with a dc voltage applied to the volume control terminal
offering a range of gain from -40 dB to 36 dB. Line outputs, for driving external headphone amplifier
inputs, are also dc voltage controlled with a range of gain from -56 dB to 20 dB.
An integrated 5-V regulated supply is provided for powering an external headphone amplifier.
11.29.2.
Features
•
•
9-W/Ch into an 8-Q Load from 12-V Supply
Efficient, Class-D Operation Eliminates
Heatsinks and Reduces Power Supply
Requirements
• 32-Step DC Volume Control From -40 dB to
36 dB
• Line Outputs for External Headphone
Amplifier with Volume Control
• Regulated 5-V Supply Output for Powering
TPA6110A2
• Space-Saving, Thermally-Enhanced
PowerPAD™ Packaging
• Thermal and Short-Circuit Protection
Applications
• LCD Monitors and TVs
• Powered Speakers
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11.29.3.
Pinning
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NO.
AGND
NAME
26, 30
-
Analog ground for digital/analog cells in core
AVCC
33
-
High-voltage analog power supply (8.5 V to 14 V)
AVDD
29
O
5-V Regulated output capable of 100-mA output
AVDDREF
7
O
5-V Reference output—provided for connection to adjacent VREF terminal.
BSLN
13
I/O
Bootstrap I/O for left channel, negative high-side FET
BSLP
24
I/O
Bootstrap I/O for left channel, positive high-side FET
BSRN
48
I/O
Bootstrap I/O for right channel, negative high-side FET
BSRP
37
I/O
Bootstrap I/O for right channel, positive high-side FET
COSC
28
I/O
I/O for charge/discharging currents onto capacitor for ramp generator triangle wave biased at V2P5
LINN
6
I
Negative differential audio input for left channel
LINP
5
I
Positive differential audio input for left channel
16, 17
O
Class-D 1/2-H-bridge negative output for left channel
LOUTN
LOUTP
20, 21
O
Class-D 1/2-H-bridge positive output for left channel
MODE
34
I
MODE_OUT
35
O
PGNDL
18, 19
-
Input for MODE control. A logic high on this pin places the amplifier in the variable output mode and the Class-D
outputs are disabled. A logic low on this pin places the amplifier in the Class-D mode and Class-D stereo outputs
are enabled. Variable outputs (VAROUTL and VAROUTR) are still enabled in Class-D mode to be used as
line-level outputs for external amplifiers.
Output for control of the variable output amplifiers. When the MODE pin (34) is a logic high, the MODE_OUT
pin is driven low. When the MODE pin (34) is a logic low, the MODE_OUT pin is driven high. This pin is
intended for MUTE control of an external headphone amplifier. Leave unconnected when not used for
headphone amplifier control.
Power ground for left channel H-bridge
PGNDR
42, 43
-
Power ground for right channel H-bridge
PVCCL
14, 15
-
Power supply for left channel H-bridge (tied to pins 22 and 23 internally), not connected to PVCCR or AVCC.
PVCCL
22, 23
-
Power supply for left channel H-bridge (tied to pins 14 and 15 internally), not connected to PVCCR or AVCC.
PVCCR
38,39
-
Power supply for right channel H-bridge (tied to pins 46 and 47 internally), not connected to PVCCL or AVCC.
PVCCR
46, 47
-
Power supply for right channel H-bridge (tied to pins 38 and 39 internally), not connected to PVCCL or AVCC.
12
—
REFGND
Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect the DAC
ground to this terminal.
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RINP
3
I
Positive differential audio input for right channel
RINN
2
I
Negative differential audio input for right channel
ROSC
27
I/O
ROUTN
44, 45
O
Class-D 1/2-H-bridge negative output for right channel
ROUTP
40, 41
O
Class-D 1/2-H-bridge positive output for right channel
1
Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to VCC.
9
I
I
VARMAX
10
I
VAROUTL
31
O
DC voltage that sets the maximum gain for the VAROUT outputs. Connect to GND or AVDDREF if
VAROUT outputs are unconnected.
Variable output for left channel audio. Line level output for driving external HP amplifier.
VAROUTR
32
O
Variable output for right channel audio. Line level output for driving external HP amplifier.
VCLAMPL
25
-
Internally generated voltage supply for left channel bootstrap capacitors.
VCLAMPR
36
-
Internally generated voltage supply for right channel bootstrap capacitors.
VOLUME
11
I
DC voltage that sets the gain of the Class-D and VAROUT outputs.
VREF
8
I
Analog reference for gain control section.
V2P5
4
O
2.5-V Reference for analog cells, as well as reference for unused audio input when using single-ended inputs.
Thermal
-
Connect to AGND and PGND—should be center point for both grounds.
SD
VARDIFF
—
Pad
Current setting resistor for ramp generator. Nominally equal to 1/8*VCC
DC voltage to set the difference in gain between the Class-D and VAROUT outputs. Connect to GND or
AVDDREF if VAROUT outputs are unconnected.
11.30. µPA672T
11.30.1.
General Description
The µPA672T is a super-mini-mold device provided with two MOS FET elements. It achieves highdensity mounting and saves mounting costs.
11.30.2.
Features
• Two MOS FET circuits in package the same size as SC-70
• Automatic mounting supported
11.30.3.
Pin Connection
11.31. VPC3230D
11.31.1.
General Description
The VPC 323xD is a high-quality, single-chip video front-end, which is targeted for 4:3 and 16:9, 50/60Hz and 100/120 Hz TV sets. It can be combined with other members of the DIGIT3000 IC family (such
as DDP 331x) and/or it can be used with 3rd-party products.
The main features of the VPC 323xD are
• high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking
• multi-standard colour decoder PAL/NTSC/SECAM including all substandards
• four CVBS, one S-VHS input, one CVBS output
• two RGB/YCr Cb component inputs, one Fast Blank (FB) input
• integrated high-quality A/D converters and associated clamp and AGC circuits
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• multi-standard sync processing
• linear horizontal scaling (0.25 ... 4), as well as non-linear horizontal scaling ‘Panorama-vision’
• PAL+ preprocessing
• line-locked clock, data and sync, or 656-output interface
• peaking, contrast, brightness, color saturation and tint for RGB/ YC r C b and CVBS/ S-VHS
• high-quality soft mixer controlled by Fast Blank
• PIP processing for four picture sizes (1/4, 1/9, 1/16 or 1/36 of normal size) with 8-bit resolution
• 15 predefined PIP display configurations and expert mode (fully programmable)
• control interface for external field memory
• I2C-bus interface
• one 20.25-MHz crystal, few external components
• 80-pin PQFP package
11.31.2.
Pin Connections and Short Descriptions
NC = not connected
LV = if not used, leave vacant
X = obligatory; connect as described in circuit diagram
SUPPLYA = 4.75...5.25 V, SUPPLYD = 3.15...3.45 V
Pin No.
PQFP
80-pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Pin Name
Type
Connection
(if not used)
Short Description
B1/CB1IN
G1/Y1IN
R1/CR1IN
B2/CB2IN
G2/Y2IN
R2/CR2IN
ASGF
FFRSTWIN
VSUPCAP
VSUPD
GNDD
GNDCAP
SCL
SDA
RESQ
TEST
VGAV
YCOEQ
FFIE
FFWE
FFRSTW
FFRE
FFOE
CLK20
GNDPA
VSUPPA
LLC2
LLC1
VSUPLLC
GNDLLC
Y7
Y6
Y5
Y4
GNDY
VSUPY
Y3
Y2
Y1
Y0
C7
IN
IN
IN
IN
IN
IN
VREF
VREF
VREF
VREF
VREF
VREF
X
LV or GNDD
X
X
X
X
X
X
X
GNDD
GNDD
GNDD
LV
LV
LV
LV
LV
LV
X
X
LV
LV
X
X
GNDY
GNDY
GNDY
GNDY
X
X
GNDY
GNDY
GNDY
GNDY
GNDC
Blue1/Cb1 Analog Component Input
Green1/Y1 Analog Component Input
Read1/Cr1 Analog Component Input
Blue2/Cb2 Analog Component Input
Green2/Y2 Analog Component Input
Read2/Cr2 Analog Component Input
Analog Shield GNDF
FIFO Reset Write Input
Digital Decoupling Circuitry Supply Voltage
Supply Voltage, Digital Circuitry
Ground, Digital Circuitry
Digital Decoupling Circuitry GND
I2C Bus Clock
I2C Bus Data
Reset Input, Active Low
Test Pin, connect to GNDD
VGAV Input
Y/C Output Enable Input, Active Low
FIFO Input Enable
FIFO Write Enable
FIFO Reset Write/Read
FIFO Read Enable
FIFO Output Enable
Main Clock output 20.25 MHz
Pad Decoupling Circuitry GND
Pad Decoupling Circuitry Supply Voltage
Double Clock Output
Clock Output
Supply Voltage, LLC Circuitry
Ground, LLC Circuitry
Picture Bus Luma (MSB)
Picture Bus Luma
Picture Bus Luma
Picture Bus Luma
Ground, Luma Output Circuitry
Supply Voltage, Luma Output Circuitry
Picture Bus Luma
Picture Bus Luma
Picture Bus Luma
Picture Bus Luma (LSB)
Picture Bus Chroma (MSB)
IN
OUT
SUPPLYD
SUPPLYD
OUT
IN/OUT
IN/OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN/OUT
OUT
OUT
OUT
IN/OUT
SUPPLYD
SUPPLYD
OUT
OUT
OUT
OUT
SUPPLYD
SUPPLYD
OUT
OUT
OUT
OUT
OUT
32
TFT TV Service Manual
11/04/2006
42
43
44
45
46
47
48
49
50
51
52
53
54
55
C6
C5
C4
VSUPC
GNDC
C3
C2
C1
C0
GNDSY
VSUPSY
INTLC
AVO
FSY/HC/HSYA
OUT
OUT
OUT
SUPPLYD
SUPPLYD
OUT
OUT
OUT
OUT
SUPPLYD
SUPPLYD
OUT
OUT
OUT
GNDC
GNDC
GNDC
X
X
GNDC
GNDC
GNDC
GNDC
X
X
LV
LV
LV
56
57
58
MSY/HS
VS
FPDAT/VSYA
IN/OUT
OUT
IN/OUT
LV
LV
LV
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
VSTBYY
CLK5
NC
XTAL1
XTAL2
ASGF
GNDF
VRT
I2CSEL
ISGND
VSUPF
VOUT
CIN
VIN1
VIN2
VIN3
VIN4
VSUPAI
GNDAI
VREF
SUPPLYA
OUT
IN
OUT
SUPPLYA
OUTPUT
IN
SUPPLYA
SUPPLYA
OUT
IN
IN
IN
IN
IN
SUPPLYA
SUPPLYA
OUTPUT
X
LV
LV or GNDD
X
X
X
X
X
X
X
X
LV
LV
VRT
VRT
VRT
VRT
X
X
X
79
80
FB1IN
AISGND
IN
SUPPLYA
VREF
X
Picture Bus Chroma
Picture Bus Chroma
Picture Bus Chroma
Supply Voltage, Chroma Output Circuitry
Ground, Chroma Output Circuitry
Picture Bus Chroma
Picture Bus Chroma
Picture Bus Chroma
Picture Bus Chroma (LSB)
Ground Sync Pad Circuitry
Supply Voltage, Sync Pad Circuitry
Interlace Output
Active Video Output
Front Sync/ Horizontal Clamp Pulse/Front-End
Horizontal Sync Output
Main Sync/Horizontal Sync Pulse
Vertical Sync Pulse
Front End/Back-End Data/Front-End Vertical Sync
Output
Standby Supply Voltage
CCU 5 MHz Clock Output
Not Connected
Analog Crystal Input
Analog Crystal Output
Analog Shield GNDF
Ground, Analog Front-End
Reference Voltage Top, Analog
I2C Bus Address Select
Signal Ground for Analog Input, connect to GNDF
Supply Voltage, Analog Front-End
Analog Video Output
Chroma/Analog Video 5 Input
Video 1 Analog Input
Video 2 Analog Input
Video 3 Analog Input
Video 4 Analog Input
Supply Voltage, Analog Component Inputs Front-End
Ground, Analog Component Inputs Front-End
Reference Voltage Top, Analog Component Inputs
Front-End
Fast Blank Input
Signal Ground for Analog Component Inputs, connect
to GNDAI
12. SERVICE MENU SETTINGS
To enter the service menu, first enter the MENU by pressing “MENU” button and then press the digits 4, 7, 2
and 5 respectively.
12.1.
Picture Adjust
•
•
•
•
•
Source
=> All possible sources given with the chasis as a list.
Mode
=> Three items as a list; NATURAL, DYNAMIC, CINEMA
Colour Temp
=> Three items as a list; COOL, NORMAL, WARM
Contrast => Slider Bar. Changing value between 0 to 63.
Brightness
=> Slider Bar. Changing value between 0 to 63.
33
TFT TV Service Manual
11/04/2006
•
Sharpness
=> Slider Bar. Changing value between 0 to 31.
•
Colour
=> Slider Bar. Changing value between 0 to 99.
•
R
=> Slider Bar. Changing value between 0 to 31.
•
G
=> Slider Bar. Changing value between 0 to 31.
•
B
=> Slider Bar. Changing value between 0 to 31.
•
Backlight
=> Slider Bar. Changing value between 0 to 255.
In this menu preset values for each Mode (Contrast, Brightness, Sharpness, Colour values for each
Mode-NATURAL, DYNAMIC, CINEMA) and for each Colour Temp. (R, G, B values for each Colour
Temp- COOL, NORMAL, WARM) are determined for each source.
12.2.
SOUND1
•
Menu Subwoofe
=> If ON, Subwoofer option is available in TV set, and the item is
visible in sound menu, else Subwoofer is not available.
•
Subwoofer Level (dB)
=> This value is gain value of Subwoofer output in dB. -30...12
•
Subwoofer Corner Freq. (x10Hz) => Last low frequency value that is amplified. 5...40
•
Menu Equalizer
=> If ON, visible in sound menu, else invisible.
•
Menu Headphone
=> If ON, visible in sound menu, else invisible.
•
Menu Effect
=> If ON, visible in sound menu, else invisible.
•
Menu Wide Sound
=> If ON, visible in sound menu, else invisible.
•
Menu Dynamic Bass
=> If ON, visible in sound menu, else invisible.
•
Menu Virtual Dolby
=> If ON, visible in sound menu, else invisible.
•
Carrier Mute
=> If ON, in the absence of an FM carrier the output is muted,
else not.
•
Virtual Dolby Text
=> Active if VIRTUAL DOLBY is ON. According to the selection;
seen in sound menu as 3D PANORAMA or VIRTUAL DOLBY.
12.3.
SOUND 2
•
AVL
=> AVL is controlled from this menu by service user. ON/OFF
•
Menu AVL
=> If ON, AVL item is visible in sound menu, and AVL can be controlled
from sound menu by normal user, else AVL is invisible to normal user.
•
FM PRESCALE AVL ON
=> If AVL ON, set value in this item is used as prescale
value for the related standard. 0...127
•
NICAM PRESCALE AVL ON
=> If AVL ON, set value in this item is used as prescale
value for the related standard. 0...127
•
SCART PRESCALE AVL ON
=> If AVL ON, set value in this item is used as prescale
value for scart outputs. 0...127
•
SCART VOLUME AVL ON
=> If AVL ON, set value in this item is used as volume
value for scart1 and scart2. 0...127
•
FM PRESCALE AVL OFF
=> If AVL OFF, set value in this item is used as prescale
value for the related standard. 0...127
•
NICAM PRESCALE AVL OFF
=> If AVL OFF, set value in this item is used as prescale
value for the related standard. 0...127
•
SCART PRESCALE AVL OFF
=> If AVL OFF, set value in this item is used as prescale
value for scart outputs. 0...127
•
SCART VOLUME AVL OFF
=> If AVL OFF, set value in this item is used as volume
value for scart1 and scart2. 0...127
12.4.
Options
•
Burn-In Mode
=> If ON, When TV is powered ON Green, Blue, Red is displayed in
sequence until Menu button is pressed.
•
FIRST APS
=> If ON, “First APS” menu is displayed when the TV is switched on
with the factory default settings.
•
APS Volume
=> After First APS function finishes, the volume of the TV is that
value.
•
AGC (dB)
=> Tuner AGC value.
•
Power-Up Mode
=> Mode defines the TV set power on state.
Stand-by : When TV is ON set is in stand-by mode
Normal : When TV is ON set is in normal mode
Last State: When TV is ON set is in Last State mode
34
TFT TV Service Manual
11/04/2006
•
Factory Reset
=> OK to activate. When OK is pressed on this item, factory defaults
loaded.
•
Enter Flash Mode => Before uploading SW this mode must be selected.
•
Reset Eeprom
=> Initialize default settings
12.5.
TV Norm
•
•
•
•
•
•
12.6.
12.7.
BG
DK
I
L
LP
M
=> If ON, supported, else not supported
=> If ON, supported, else not supported.
=> If ON, supported, else not supported.
=> If ON, supported, else not supported.
=> If ON, supported, else not supported.
=> If ON, supported, else not supported.
Features
•
•
•
•
•
•
PIP/PAP
Blue Background
Menu Transparency
Menu Timeout
Backlight
Single Tuner
•
Dynamic WB
=> If ON, PIP/PAP available else not.
=> If ON, Blue Background is visible in Feature Menu else not.
=> If ON, Menu Transparency is visible in Feature Menu else not.
=> If ON, Menu Timeout is visible in Feature Menu else not.
=> If ON, Backlight is visible in Feature Menu else not.
=> If TV set has one tuner Single Tuner must be ON.
If TV set has double tuner Single Tuner must be OFF.
=> Dynamic White Balance
Teletext
•
TOP TXT
=> If ON, Top Text feature is available else not.
•
Fast TXT
=> If ON, Fast Text feature is available else not.
•
Teletext Language
=> Teletext Language may be controlled from this menu by service
user.
•
Menu Teletext Language
=> If ON, Teletext Language item is visible in Feature Menu, and
Teletext Language can be controlled from Feature Menu by normal user, else Teletext Language is
invisible to normal user.
12.8.
Source
•
TV
•
SC1
•
SC2
•
SC2 SVHS
•
SC3
•
SC3 SVHS
•
YPBPR
•
FAV
•
SVHS
•
HDMI
•
PC
This menu is related with the options of the chassis. These items may be ON or OFF. If ON, the source is available
in TV set, and the item is visible in source menu, else the source may be available but invisible to user.
12.9.
Menu Languages 1 & 2
The language options for the Language item in Feature menu can be set ON or OFF from this menu.
35
TFT TV Service Manual
11/04/2006
GENERAL BLOCK DIAGRAM
13. BLOCK DIAGRAM
MAIN BOARD
AUDIO AMPL. BOARD
MAIN_L, MAIN_R,
AUDIO/VIDEO/GRAPHICS IN/OUT
AUDIO
AUDIO
DECODING
DECODING
MSP3411G
MSP3411G
MICRONAS
MICRONAS
AUDIO
AUDIO
AMPLIFIER
AMPLIFIER
D-CLASS
D-CLASS
IDTV,SVHS,MMC (RGB),PC IN
SVP-EX
SVP-EX59
59
LVDS OUT
VPC3230D
VPC3230D
VIDEO
VIDEOPROCESSOR
PROCESSOR
PIP
PIPPICTURE
PICTURE
MICRONAS
MICRONAS
HDMI
HDMIDECODER
DECODER
SIL9993
SIL9993
8-BIT YUV
SDA5550
SDA5550
MCU
MCU
MICRONAS
MICRONAS
24 BIT RGB
PSU
PSU
2
QSS_TUN2
L1003
22u
SC1_AUDIO_L_OUT
270p
470p
50V
50V
C1081
C1086
L2
AVSUP
ANA_IN1+
ANA_IN-
ANA_IN2+
10u
R2008
1k
C1152
1n5
C1144
49
50
51
52
53
54
TESTEN
XTAL_IN
XTAL_OUT
TP
AUD_CL_OUT
32CAPL_M
31AHVSUP
30 CAPL_A
29 SC1_OUT_L
28 SC1_OUT_R
27 VREF1
26 SC2_OUT_L
25 SC2_OUT_R
24DACM_S
C251
100n
16V
C300
1
PL1002
2
3
10u
AUDIO_L_OUT
C1167
OUTB
INA-
2
C1184
2n2
C1179
220p
C1181
10u
47k
R1102
7
C1183
1n
C1180
100u
R1112
47k
1
TDA1308
6
INB-
INA+
3
5
INB+
VSS
4
2n2
C1168
50V
1u
L1030
L1029
C1133
1n
50V
100R
R1098
AUDIO_R_OUT
100u
OUTA
10k
R1113
22u
SC2_AUDIO_L_OUT
1n
50V
D1005
LOUT4 17
13 LOUT2
ROUT3 16
14 ROUT2
LOUT3 15
R101
4k7
R100
4k7
S107
MUTE_AMP
L216
R102
4k7
Q100
BC848B
HEADPHONE
S108
PC_AUDIO_R_IN
PC_AUDIO_L_IN
MUTE_AMP
R103
4k7
ROUT4 18
S2010 & R2208 are for mute option
Mute is active high
L219
L218
C257
DAC_AOR
330n
C255
R2023
1k
C2036
50V
4n7
R5 19
2
L2019
BLM21B201S
VDD
220p C1173
50V
4k7
R1100
AUDIO_L_LINE_OUT
C2037
12 ROUT1
C254
50V
22u
C295
10u
C1134
50V
100R
R1093
100R
R1089
50V
1n
C1121
1n
50V
C2024
L2018
4
VCC_8V
C1118
1n
C2202
YPBPR_AUDIO_R_IN
330n
11 L0UT1
C1000
AUDIO_R_LINE_OUT
1n
AUDIO_R2
R2022
1k
C2022
22u
50V
22u
1n
50V
R2204
100R
VCC5V_FILTERED
L1017
BZT55C5V1
50V
D10044n7
100R
C2023
AUDIO_L2
1u
16V
R1115
R4 20
330n
BLM21B201S
1n
AUDIO_R
8
IC209
STBY_3V3
C2034
L4
C1001
22u
L2002
R2203
100R
10n
50V
C1186
R1116
10k
1k
R1117
C2021
R2016
100R
IF
C2018
BLM21B201S
1n
AUDIO_L
22u
100u
C1172
NC3 21
C2033
10 L5
L2001
R2015
100R
L1031
BA782
NC2
C2020
R2014
1k
BC848B
C1187
C1188
8
NC4 22
330n
Q1013
S2012
D1002
NC1
9
1n
10k
R1119
C2017
R2013
1k
YPBPR_AUDIO_L_IN
DAC_AOL
47k
R1118
7
TEA6420
Z1002
IN1
OUT1 4
C1189
16V
100n
S1005
Q1014
PC_AUDIO_R_IN
330n
GND
OUT2 5
10k
R1120
BC848B
R2021
1k
R3 23
R1097
100R
L3
R1091
100R
C2031
6
C2019
1
SW01=L BG,DK,I,L
SC3_AUDIO_R_IN
C2032
22u
C2016
K9356M
L1027
VCC5V_FILTERED
IDTV/MMC/DVD_R_IN
S2003
1 3
IF
IN2
1n
330n
C2015
3
2
SW01=H L’
S2009
R2020
1k
24
IC201
L1028
SC2_AUDIO_R_IN
C2029
R2 24
22u
C1178
HP_L
330n
C2030
R1103
4k7
C1185
2n2
50V
C1165
R1129
4R7
50V
330n
C2014
R2019
1k
JK200
JACK-AK16
SIF2
HP_R
C1136
C2027
SC2_AUDIO_R_OUT
VIF1
50V
1u
C1151
22u
C1132
C2028
1n
1
16V
100u
BC848B
Q1011
50V
R1 25
C1124
L1
330n
16V
OUT1 4
R2009
1k
R2006
1k
56p
C1125
X10021p8
R2007
1k
C1122
50V
C1120
18.432MHz
55
56
57
58
50V
100u
4
C2012
50V
1n
10u
16V
R2012
1k
PC_AUDIO_L_IN
D1006
ADDR 26
K D1001 A
2
1
C1182
2n2
50V
C1150
R1096
1k
BC848B
Q1009
50V
1n
50V
1n
50V
1n
50V
10n
23
1n
50V
BA591
VS
A D1000 K
1
2
C1126
R1092
1k
SCL
50V
1n
SIF1
C1154
S2000
3
8V_FILTERED
4R7
R1130
100n
R2018
100R
1n
VIF2
50V
1n
2
GND
OUT2 5
IDTV/MMC/DVD_L_IN
HEADPHONE
50V
470p
47p
5
IDTV/MMC/DVD_R_IN
S2010
C1162
C2026
330n
1n
50V
IN1
C1047
R2201
47R
C1043
SC3_AUDIO_L_IN
C2013
SAW_SW1
K3953M
Z1001
1
R2011
1k
S2001
SAW_SW1
C1056
IN2
S2002
IDTV/MMC/DVD_L_IN
C247
2
1n
50V
C2011
100n
SDA
SCL 27
8V_FILTERED
R2010
1k
C1149
3u3
C2025
CAPACITANCE
22u
50V
100n
16V
C1145
R2017
100R
SDA 28
C2009
R1027
22k
GND
47p
C2010
S2005
50V
1n5
100R
R1095
75R
SUBW
R1040
R2202
220R
PL1001
22n
50V
C1054
R1039
1N4148
12k
47k
MAIN_L
C2201
SC2_AUDIO_L_IN
100n
25V
390p
50V
S1006
50V
1n
C1106
50V
1n
C1117
2
L1026
SC3_AUDIO_L_IN
10u 50V
50V
1n
C1196
100n
C249
C1009
C1049
R1023
22k
OP2 22
3
11
C1041
VCC_5V
10n
50V
C1027
S1007
10
1u
IF1
C1097
IDTV/MMC/DVD_R_IN
AFC 21
3 OP1
L1000
IF2
MAIN_R
IDTV/MMC/DVD_L_IN
VCC5V_FILTERED
R1024
6k8
C1012
10u
C1003
50V
10u
4 FMPLL
2k2
150R
VP 20
10n
50V
C1026
9
C1004
50V
1n5
33p
25V
5 DEEM
5k6
R1041
VPLL 19
220n
16V
VCC_5V
33V_FILTERED
R1001
VST
C1040
470n
63V
C1031
7
8
3
1
1
R1109
1k
AUDIO_L2
BZT55C5V1
33p
25V
C1008
6 AFD
6
R1012
NC/ADC
TDA9885T
C1030
16V
100n
VS
4
50V
47u
AGND18
S2007
S2006
50V
1n
C1114
IC2000
7 DGND
100n
NC
5
R1035
2k2
47R
CVBS 17
C1112
1n
50V
MUTE_AMP
R1026
5
C1015
SDA
8 AUD
4
59
HP_R
2
BC848B
Q1002
L1025
C1163
100R
R1094
470n 63V
SCL
R1034
10k
VAGC16
C1175
R1111
1k
AHVSS 33
50V
1n
C1119
22n
50V
3
S2008
330n
AGNDC 34
16 RESETQ
100R
R1090
9 TOP
3
4MHz
AUDIO_R2
AUDIO_L
SC3_AUDIO_R_IN
1n
C1147
AUDIO_R
L1024
1k
1n
C1153
330n
SC4_IN_L 35
C1087
470p
1kV
1
AV_AUDIO_L_IN
L1021
1n
RESETQ_MSP
PL1003
L1023
R1110
SC4_IN_R 36
14 NC2
R1107
1k
AV_AUDIO_R_IN
S2011
C1171
330n
SC3_IN_L 38
330n
L1020
R1108
1k
1n
ASG3 37
R1106
1k
C1170
C1158
13 NC1
C1079
1n5
50V
QSS_TUN1
R1044
22p
25V
C1039
S1000
AS
REF 15
VCC_5V
10 SDA
33p
25V
C1023
2
33p
25V
C1022
SDA
TU
X1001
330n
SC3_IN_R 39
15 NC3
100R
C1038
R1009
100R
1n
C1140
SC1_AUDIO_L_IN
C1176
C1164
C1078
10u
50V
TUN1_CVBS
330n
SC2_IN_L 41
11 DVSS
2
TAGC 14
1n
C1148
12 12S_DA_IN2
R1030
11 SCL
C1157
ASG2 40
L1022
C1177
SC2_IN_R 42
22u
R1052
560R
R1005
100R
SCL
1
NC 13
IC205
47u
50V
C1010
L1001
AGC
NC4
NC5
10 DVSUP
HP_L
12SIOMAD
50V
1p8
R104
4k7
C_CTR_I/O_0
ADR_CL
1n
R1049
4k7
R1122
10k
R1010
100R
R1114
2k2
60
61
63
62
ADR_SEL
ADR_WS
10p
25V
BC848B
SC1_AUDIO_R_IN
R1105
1k
C1174
1n
ASG1 43
MSP3452G
IC208
ADR_DA
1N4148
R1050
2k4
R1048
15k
BA591
D1007
12S_DA_IN1
7
8
ESD
Q1005
BC848B
330n
R1101
10k
VCC_5V
S1003
6
23
DACM_SUB
100n
16V
D1003
SC1_IN_L 44
IC207
R1051
75R
100n
16V
C1191
Q1016
I2S_DA_IN1
L1008
K9356M
Z1003
1 IN1
OUT1 4
C1052
L1019
R1104
1k
C1156
C1159
GND
OUT2 5
S1010
R1123
47k
BC848B
10u
C1169
MONO_IN 47
SC1_IN_R 45
22DACM_C
IN2
C1166
AVSS 48
12S_DA_OUT
470R
C1080
100u
C1055
Q1015
SAW_SW2
R1126
1k
L1032
S2013
R1121
10k
C1194
C1192
10k
R1125
16V
1u
C1193
100n
12S_WS
9
470R
R1067
VCC5V_FILTERED
BA782
IF1
560p
N.C
5
C1116
S1009
2
50V
10n
C1137
VREFTOP 46
21DACM_L
IC200
VCC5V_FILTERED
3
R1124
VCC_5V
4
20DACM_R
24
100R
12S_CL
C2008 SC3_AUDIO_R_OUT
22u
330n
1
2
A IC206 K
1n
50V
IF1
Q1007
BZT55C3V6
SIF2
C1206
VIF1
C1205
50V
100n
1
C1200
50V
100n
OUT1 4
R1127
4R7
C1199
50V
100n
IN1
3
22u
L1018
C1138
I2S_DA_OUT
R1069
VCC_5V
100n
50V
50V
100n
1
12C_DA
22uSC1_AUDIO_R_OUT
C2007
50V
C1130
56p
BC858B
C1198
C1057
AUDIO_R_OUT
C1123
56p
8V_FILTERED
23
SF_63962
Z1000
11
2
19 VREF2
SIF1
12C_CL
17DACA_R
VIF2
64
39p
C1085
1k
R1068
2
GND
OUT2 5
1
STANDBYQ
SDA
I2S_WS
C1197
L1002
1n
50V
IN2
100R
Q2004
BC848B
1n
SAW_SW2
3
2
R1071
I2S_CL
390p
50V
C1005
NC6
50V
39p
C1084
C1203
50V
100n
100n
50V
50V
100n
C1202
C1201
33V_FILTERED
C1204
VCC_33V
10u
16V
R1128
4R7
50V
10u
22k
R1028
VCCA_3V3
FB_CONTROL
SCL
C1045
VCC5V_FILTERED
100n
25V
OP2 22
QSS_TUN2
QSS_TUN1
R1043
R2200
47R
C1042
50V
1n5
C1048
R1022
22k
AFC 21
10n
50V
C1025
3 OP1
10
1u
IF1
C1035
R2005
100R
100R
VCC5V_FILTERED
33V_FILTERED
S1008
IF2
R1070
50V
10u
9
4 FMPLL
C1006
50V
10u
R1000
2k2
330R
VP 20
10n
50V
C1024
5k6
16V
100n
C1195
VPLL 19
5 DEEM
7
8
R1038
100n
25V
C2200
R1031
6k8
C1011
C1002
50V
10u
25V
100n
VST
C1037
50V
10n
6 AFD
C1113
100n
25V
R1078
100R
470n
63V
C1029
R1011
NC/ADC
BC848B
Q1003
50V
47u
AGND18
TDA9885T
6
VCC_5V
VS
220R
R1025
47R
CVBS 17
7 DGND
33p
25V
C1013
5
C1028
NC
R1036
12k
47k
R1042
33p
25V
C1007
CTF5543_HOR
TU1000
4
Q2003
BC848B
50V
D_CTR_I/O_1
VAGC16
8 AUD
R2004
100R
AUDIO_L_OUT
C1128
56p
22u
C2006SC3_AUDIO_L_OUT
4MHz
18DACA_L
9 TOP
R1037
75R
REF 15
22p
25V
3
R1032
10 SDA
VCC_5V
33p
25V
C1021
R1008
100R
2
TUN2_CVBS
X1000
10k
33p
25V
C1020
SDA
100R
C1034
470n
63V
SDA
MAIN BOARD(17MB15E)
TAGC 14
VCC_5V
SCL
50V
R1029
11 SCL
C1036
AS
1N4148
NC 13
IC204
47u
50V
C1014
TU
12SIOMAD
N.C
1
C2005
Q2001
BC848B
R1013
100R
R1004
100R
SCL
AGC
VCC5V_FILTERED
CTF5543_HOR
50V
26R_100MHZ_1.5A
VESTEL ELECTRONICS
TV R&D GROUP
TFT TV
VER. E0
17MB15E-5 TFT TV Tuner/IF/Audio
DATE
21/4/2004
M.KURSAT
SARIARSLAN
VESTEL R&D
Sheet 01
10
12
16
7
9
11
17
2
1
K D2101 A
C270
BZT55C10
50V
1n
C301
50V
150p
SC3_AUDIO_R_IN
PIN8_SC2
D205
VCCA_3V3
VCC_5V
1
3
L2114
L2125
L2006
7
L2004
9
10
A
1
BZT55C5V1
D2100
K
2 D207
TV_LINK
11
1
A
75R
R289
75R
R290
12
D222
BZT55C10
R288
2
K
D208
SC2_G
1
A
SC2_R
S204
21
C2049
SVHSfromSC2_C
15
S205
C293
100n
150p
16V
SC1_B
150p
C248
16
17
1
A
D218
18
2
K
19
330R
D211
1
A
20
R254
C267
330R
R252
50V
1n
L210
L205
R287
75R
A
1
D202
K
2
1
2
A D204 K
2
K
75R
R276
SC2_V_IN
C286
150p
50V
2
1
K D2500 A
150p
BZT55C10
PIN8_SC1
SCSDA
BZT55C10
BZT55C10
C269
SC2_FB
R275
SC2_V_OUT
K D2102 A
2
1
C296
50V
4n7
50V
C253
1
2
A D224 K
SC1_G
1n
150p
C278
SEL
S633
VCC 16
2
Q2
Q0 15
3
Q3
DSERIAL 14
4
Q4
OE 13
VCCA_3V3
100n
C281
100n
C2053
Q1
100n
C2051
1
R280
150k
S634
STBY_5V
IC214
C_SELECTED
Q206
BC848C
100n
R269
47k
C2052
R268
47k
SVHSfromSC2_C
CHROMA_SW
EXTERNAL INPUT
Q205
BC848C
220n
16V
19
75R
BZT55C10
D206
SCSCL
SC1_R
SC1_V_OUT
SC1_V_IN
Q204
C246
BC848C
220n
16V
MMC_G
6
MMC_B
MMC_R
5
4
3
PL1
1n
50V
C272
S213
MMC_CVBS
AV_AUDIO_L_IN
L201
CIN
DVD_12V_SENSE
C271
1n
8
20
L208
K
2
AV_AUDIO_R_IN
R270
100R
100n
16V
7
C245
C2050
L202
4n7 C266
D203
S652
MMC/DVD
VIDEO INPUTS
6
4k7
R271
C262
2
K
K
2
S651
R267
10k
R232
75R
2
K
2
D216
1
1
A
5
DIMMING SELECTION
CIN
4
R266
18k
220n
S635
R273
10k
2
K
R274
1k
D217
1
A
A
1
A D213 K
1
2
R261
SC1_FB
C261
1
A
SC2_AUDIO_L_IN
21
SCL2
5
SVHS_Y_IN
1
A
SC1_AUDIO_R_IN
SDA
15
S220 BZT55C10
2
K
S221
1
A
K
2
D210
SCL_PANEL
VSS
13
R286
75R
2
K
D209
V8
3
18
SC1_AUDIO_R_OUT
6
D223
75R
2
K
CHROMA SWITCH
C263
39p
42
SC1_AUDIO_L_OUT
SCL
BZT55C10
2
K
L214
14
5
150p
C250
150p
50V
K
2
40
L206
3
7
SDA_PANEL
1
41
SC1_AUDIO_L_IN
ST24LC21
D214
AV1_V_IN
2
SC3_AUDIO_R_OUT
38
2
1
K D220 A
NC3
1
A
BZT55C5V1
D215
330R
R2025
2
14
1
A
3
VCLK
2
1
K D2103 A
1n
50V
13
8
R285
75R
NC2
8
BZT55C10
2
K
36
39
C258
34
37
50V
4n7
35
PL205
32
D219
MMC_CVBS
2
VCC
SC2_AUDIO_L_OUT
150p
C277
C264
8
S646
TXOUT0-
TXOUT0+
TXOUT1-
S647
30
33
75R
A
1
330R
R2024
L2005
BZT55C10
L2003
S636
D2001
150p
C2039
30
28
26
24
22
20
SC3_AUDIO_L_OUT
SC3_AUDIO_L_IN
PIN8_SC3
SVHSfromSC2_C
K D2002 A
2
1
27
25
29
28
31
A
1
IDTV/MMC/DVD_CVBS
S212
29
6
A
1
39p
BZT55C10
NC1
R253
330R
N.C
N.C
SDA2
4
PL201
1n
L2008
L209
6
S639
S638
23
21
19
17
15
13
9
11
A
1
1
220n
16V
S645
39p
50V
C268
R202
75R
IC215
SC3_V_OUT
R2003
1k
R231
75R
C291
SC3_V_IN
I2C BUFFER FOR PANEL
R2002
75R
4n7
C2045
L204
Q2000
BC848B
TUN2_CVBS
220n
16V
4
1
SC1_V_OUT
D212
INPUT7 11
N.C
10 INPUT6
27
26
2
R1045
1k
C275
24
LVDS OUTPUT
GND1 12
R2001
100R
SC2_AUDIO_R_IN
C2042
L213
VCC_5V
VCC
220n
16V
C273
C299
50V
22u
16V
100u
VCC_8V
C283
9
50V
1n
C2040
K
2
L200
R1046
75R
BC848B
V8
10k
R225
25
R260
75R
OUTPUT1 13
SELECTABLE VIDEO OUT
FOR SCART 2
BZT55C10
2
K
INPUT5
220n
16V
Q1004
R1033
100R
C276
39p
N.C
50V
C297
8
SC2_V_OUT
1k
R242
50V
150p
C252
10k
R224
CONNECT C288
R201
75R
4n7
C2044
L2007
1
A
OUTPUT2 14
S200
VCC_8V
SVHS_Y_IN
BZT55C10
2
1
K D2104 A
PARITY
PROG
BZT55C10
2
1
K D2105 A
4n7
50V
L207
SC2_B
23
22
S644
7
R237
75R
TXOUT1+
Q202
BC848B
10k
R223
TXOUT2-
220n
16V
N.C
S201
TXOUT2+
R230
100R
OUTPUT3 15
TXCLKOUT-
INPUT4
TXCLKOUT+
6
N.C
TXOUT3-
TEA6415C
TXOUT3+
220n
16V
C279
OUTPUT4 16
V8
39p
50V
INPUT3
V8
C280
R205
75R
AV1_V_IN
5
39p
50V
R200
75R
C259
C265
N.C
SC3_V_OUT
R250
4k7
SDA_PANEL
SCL_PANEL
R251
4k7
SC3_V_IN
VCCA_3V3
S109
18
TUN1_CVBS
GOES TO VPC3230
FOR PIP PICTURE
16
1k
R241
10k
R222
14
OUTPUT5 17
10
CLOCK
VxtoVPC
12
4
R227
100R
BZT55C10
BZT55C10
7
10k
R221
SCL
K D2004 A
2
1
A D2000 K
1
2
S640
8
47p
25V
C287
R207
100R
R249
SC2_AUDIO_R_OUT
K D2003 A
2
1
Q203
BC848B
R240
75R
330R
L203
C284
PANEL_VCC
50V
150p
C2038
R226
100R
OUTPUT6 18
5
INPUT2
220n
16V
39p
50V
R204
75R
C292
3
N.C
BZT55C10
PL203
VCC_12V
6
C260
SC2_V_IN
A D221 K
1
2
S641
10k
R220
PDP_GO/BL_ON_OFF CPU_GO
S642
GND2 19
S643
DATA
3
2
4
SDA
CVBS_SVP
1k
R239
1
C303
R206
100R
V8
220n
16V
47p
25V
39p
50V
220n
16V
DISP_EN/PDWN
MAIN PICTURE
TO SVP
R235
75R
S648
Q200
BC848B
INPUT8 20
PL103
INPUT1
2
1
N.C
R203
75R
C285
C282
VCCA_3V3
N.C
SC1_V_IN
S113
IC210
C274
VCCA_3V3
S111
PANEL_VCC
LG_1/IRQPDP
100n
16V
VCC_12V
C298
5V
S112
R264
V8
C294
IDTV/MMC/DVD_CVBS
V8
75R
4R7
R229
10u
39p
C304
VCCA_3V3
VCC_8V
VIDEO SWITCH TEA6415C
R279
10k
STBY_3V3
P1
LG_1/IRQPDP
9
P2
P6 11
RGB_SW3
6
VGA_HSIN
5
7
RGB_SW1
P3
P5 10
gnd
VSS
P4
3
2A
4
2Y
3
75R
R208
PANEL_VCC_ON/OFF
2
75R
R209
1
75R
R210
6Y 12
STOP 12
6
Q6
SHCP 11
Q7
8
GND
MR 10
Q7OUT
9
PC_STBY
IC212
Q207
BC848C
5A 11
VGA_VSIN
3A
7
R283
10k
D201
R281
10k
100n
16V
C302
6A 13
8
VCC
7
VCLK
5Y 10
VGA_VSIN
R214
22R
22R
R238
SW_ENABLE
9
Q5
VCCA_3V3
R217
10k
1Y
DDC_5VVCC_5V
VCCA_3V3
D200
R216
10k
R213
22R
5
4
8
1N4148
74LVC14A
PGAGND
7
6
BZT55C12
10
8
RGB_SW2
100n
16V
C289
2
12
P7 12
VCC 14
1N4148
11
5
R282
10k
5
1A
DDC_DATA_PC
A D2502 K
1
2
INT 13
1
13
BZT55C12
P0
330R
R256
R215
22R
14
A D2501 K
1
2
SCL 14
S223
A2
R258
4k7
3
PCF8574
DISP_EN/PDWN
330R
R255
15
DDC_5V
SDA 15
SCL2
4
CHROMA_SW
A1
R257
4k7
R248
4k7
R246
4k7
R265
4k7
R277
4k7
2
74HC595D
IC211
DDC_CLK_PC
VCCA_3V3
S649
SDA2
R212
2k
R211
2k
VDD 16
STBY_3V3
A0
4k7
R259
1
VGA_HSIN
100n
16V
STBY_3V3
gnd
S637
S650
IC213
VGA_VSIN
gnd
VCC_5V
6
3Y
4A
9
7
GND
4Y
8
DDC_CLK_PC
100R
R218
6
SCL
DDC_DATA_PC
100R
R219
5
SDA
ST24LC21
NC1
1
NC2
2
NC3
3
VSS
4
Q208
BC848C
R284
47k
C290
PC STAND-BY
PGAGND
VGA_BIN
VGA_GIN
PORT EXPANDER
VGA_RIN
PL200
D-SUB 15 PC INPUT & DDC CIRDUIT
VESTEL ELECTRONICS
TV R&D GROUP
TFT TV
VER. E0
17MB15E-5 TFT TV IN/OUT
DATE
21/4/2004
M.KURSAT
SARIARSLAN
VESTEL R&D
Sheet 02
VCC_5V
I2S_DA_OUT
10k
R315
41
SC2_R
3
C
N 14
4
D
M 13
SC1_G
5
E
L 12
SC2_G
6
F
K 11
SC1_B
7
G
J 10
SC2_B
8
H
I
C7
C6
C5
O 15
46
PI5V330_SOIC
SC2_FB
FB_VPC
9
RGB_B_VPC
DIN[0]
Y0 40
1
R1
8
66 VRT
Y1 39
2
R2
7
67 I2CSEL
Y2 38
68 ISGND
Y3 37
69 VSUPF
VSUPY 36
C344
70 VOUT
GNDY 35
100n
16V
DIN[1]
DIN[2]
3
R3
6
680n
R2
7
CLK20
78 VREF
DIN[6]
3
R3
6
DIN[7]
4
VSUPLLC 29
R4
5
L315
BLM21B201S
LLC1 28
LLC2 27
DIN[0-23]
DIN[5]
VCCD2_3V3
R321
22R
CLK_2EX
PL301
R 16
2
B
O 15
3
C
N 14
100n
A
VCC_5V
S309
VGA_RIN
RIN2
S314
4
RCA_Y
D
M 13
PI5V330_SOIC
5
E
L 12
6
F
K 11
7
G
J 10
8
H
I
BIN2
VGA&YPbPr SWITCHING
S337
VGA_BIN
S336
9
SDA
RESQ
14
15
MMC_G
N.C
R310
75R
C324
220n
16V
A
R 16
2
B
O 15
SC2_R
3
C
N 14
SC1_FB
SC2_FB
C334
25V
560p
C337
220n
16V
N.C
50V
1n5
4
D
SC1_G
5
E
L 12
SC2_G
6
F
K 11
SC1_B
7
G
J 10
SC2_B
8
H
I
S310
M 13
VCC_5V
S340
1
SC1_R
100n
16V
100R
R320
R325
1k
PI5V330_SOIC
C335
16V
220n
C336
C339
SDA3
C338
16V
100n
S311
RGB_GIN
9
S312
RGB_RIN
C325
220n
16V
R311
75R
L312
R309
75R
C309
MMC_B
N.C
C342
RX1_RST#
C329
100R
R319
100R
R318
16V
220n
50V
390p
SCL3
N.C
R2029
10k
25V
47n
C347
SCL
13
FFWE
GNDCAP
12
20
GNDD
11
FFIE
VSUPD
10
YCOEQ
VSUPCAP
9
19
NC1
8
18
ASGF1
7
TEST
R2/CR2IN
6
VGAV
G2/Y2IN
5
16
B2/CB2IN
4
17
R1/CR1IN
C328
N.C
RGB_BIN
FB
C326
220n
16V
RCA_PB
GIN2
S307
3
RGB_G_VPC
MMC_R
S308
VGA_GIN
50V
270p
16V
220n
VCCD2_3V3
N.C
bu caplerin yerine tek 100nf takabilirsin.
BLM21B201S
50V
330p
C312
C308
C353
1
G1/Y1IN
C327
C310
RCA_PR
R326
1k
RGB_SW1
RGB_R_VPC
D106
BAV99
MMC RGB INPUTS
IC318
RGB_SW2
S301
330p
50V
75R
R333
D104
BAV99
IC317
16V
220n
RGB_B_VPC
50V
330p
C313
D102
BAV99
N.C
C352
50V
330p
C311
330p
50V
VCC_5V
C358
220p
50V
R313
1k
RCA_PR
C365
75R
R332
C357
220p
50V
1 3
2
Pr
1 3
RCA_PB
75R
R331
C356
220p
50V
2
1 3
C364
220n
2
A
A
Pb
30032234
A
Y
30032233
JK302
JK301
JK300
1P_RED_FAV WHITE_FAV WHITE_FAV
220n
330p
50V
C363
SCART RGB
220n
SUBW
RCA_Y
AUDIO_L_LINE_OUT
S326
4
B1/CB1IN
S316
2
FB_VPC
1
3
GNDPA 25
80 AISGND
R312
4k
2
C345
AUDIO_R_LINE_OUT
S325
50V
1n5
VSUPPA 26
79 FB1IN
1
M.KURSAT
SARIARSLAN
VESTEL R&D
2
C346
77 GNDAI
FFOE
10u
50V
47n
25V
C316
C305
C306
1n8
50V
390p
220n
16V
C349
C348
C350
Y5 33
GNDLLC 30
24
75 VIN4
23
75R
R300
16V
100u
8
Y7 31
FFRE
74 VIN3
76 VSUPAI
VCC_5V
R1
Y6 32
22
75R
R307
VCC_5V
N.C
1
DATE
73 VIN2
L300
Y4 34
SVP ENTEGRESINE
RGB SWITCHING FOR SVP
VER. E0
IC216
VPC323XD
C322
FFRSTW
NC14
1n
75R
R306
DIN[4]
1n
72 VINI
75R
R305
R323
33R
16V
100n
C361
VCCD2_3V3
BLM21B201S
21/4/2004
5
17MB15E-5 TFT TV VPC3230
R4
Sheet 03
DIN[3]
4
TFT TV
51
GNDSY
49
52
VSUPSY
C1
53
INTLC
50
54
AVO
C0
55
FSY/HC
58
FPDAT
56
59
VSTBY
57
60
CLK5
VS
61
R322
33R
65 GNDF
VESTEL ELECTRONICS
TV R&D GROUP
VxtoVPC
MSY/HS
C359
470p
50V
RGB SWITCHING FOR VPC
71 CIN
75R
R304
22
NC13
SC1_FB
C341
21
I2S_DEL_IN4
21
100n
42
43
44
C4
B
L2011
JK304
NC15 23
20
I2S_DEL_IN3
19
I2S_DEL_IN2
18
DVSS2
17
2
RGB_G_VPC
C321
DVSUP2
SC1_R
VCC_5V
45
L314
VSUPC
BLM21B201S
S324
50V
68n
R AUDIO FAV
NC16 24
16
I2S_DEL_OUT4
15
I2S_DEL_OUT3
14
I2S_DEL_OUT2
BACK RIGHT
BACK LEFT
JK303
L AUDIO FAV
NC2
NC17 25
62
NC9
3 1
XTAL1
9
2
63
NC18 26
3 1
64
NC8
2
ASGF2
8
NC19 27
XTAL2
NC7
NC20 28
C323
CIN
7
IC2001
MAD4868A
25V
47n
SVHSfromSC2_C
NC6
BZT55C10
6
A D226 K
1
2
NC21 29
L317
NC5
BLM21A601S
5
10u
50V
C360
470p
50V
NC22 30
L316
NC4
BLM21A601S
4
C317
BZT55C10
NC23 31
A D225 K
1
2
NC3
13
S323
S330
S331
RESETQ
TEST
DVSS1
DVSUP1
I2S_DEL_WS
I2S_DEL_CL
I2S_DEL_IN1
I2S_DEL_OUT1
ADR_SEL
3
NC24 32
A
SDA
NC2
A
SCL
R 16
C343
2
NC12
A
C320
NC1
12
S302
50V
1n5
50V
390p
C362
1
NC25 33
1
11 NC11
47
22R
R317
C340
C319
10 NC10
VCCD2_3V3
C3
X300
25V
47n
48
20.25MHz
50V
1n5
IC316
R2030
1k
RGB_R_VPC
C2
L311
C318
22R
R316
50V
3p3
C330
50V
3p3
C332
R2031
33R
16V
220n
BLM21B201S
L313
L308
VCC_5V
GNDC
25V
2n2
10u
50V
C333
R2032
33R
VCC_5V
VCCD_3V3
RGB_SW3
BLM21B201S
AUDIO_L_LINE_OUT
AUDIO_R_LINE_OUT
YPBPR_AUDIO_R_IN
YPBPR_AUDIO_L_IN
BLM21B201S
BLM21B201S
35
100n
25V
36
37
38
39
40
41
42
43
C331
RESETQ_MSP
C2048
STBY_5V
34
R4 5
4
R3 6
R2 7
2
3
R2028
10R
R1 8
1
C2047
VCCD2_3V3
L2010
10u
50V
10n
50V
44
DHS_2EX
BLM21B201S
I2S_WS
L2009
I2S_CL
I2S_DA_IN1
DVS_2EX
C2046
R2027
100R
R2026
100R
SCL SDA
S303
VCCD2_3V3
CS0#
RAS#
WE#
CAS#
100n
C435
VD1_8
100n
C434
1Y
VCC
4
5
GND
3
1B
2
6
1A
7
VDDMQ_2V5
C470
C471
100n
16V
100n
16V
DVS_2EX
VCCA_3V3
R434
1k
MCLK0
MCLK0#
MVREF
R2215
33R
MD[16]
MD[17]
MD[18]
MD[19]
DQS[2]
DQM[2]
MD[20]
MD[21]
MD[22]
MD[23]
MD[24]
MD[25]
MD[26]
MD[27]
DQS[3]
DQM[3]
MD[28]
MD[29]
MD[30]
MD[31]
MPUGPIO4
5
R4 5
R4
4
R3 6
3
R2 7
1
R1 8
100n
2
100n
16V
R2216
33R
R2213
VD1_8
16V
100n
C424
12
11
10
9
8
7
6
R3
8
1
CLKE
BA0
BA1
VD1_8
DIN[0]
DIN[1]
DIN[2]
DIN[3]
DIN[4]
DIN[5]
R2
100n
16V
C459
MD[0]
MD[1]
MD[2]
C437
MD[3]
MD[4]
MCA[14]
100n
16V
S413
MD[5]
MD[6]
MCA[15]
MD[7]
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
MA[0-11]
MD[27]
MD[28]
MD[29]
MA[8]
MD[30]
VD1_8
MD[31]
MA[9]
MA[10]
DQM[0-3]
DQM[0]
MA[11]
DQM[1]
MD[15]
VD1_8
C448
MD[13]
100n
16V
DQM[2]
DQM[3]
DQS[0]
MD[12]
16V
100n
DQS[1]
C456
DQS[0-3]
MD[14]
DQS[1]
DQS[2]
DQS[3]
VDDMQ_2V5 DIN[0]
DIN[1]
DQM[1]
DIN[2]
MD[11]
DIN[3]
DIN[4]
MD[10]
MD[9]
C449
MD[8]
100n
16V
DIN[5]
DIN[6]
DIN[7]
MD[7]
DIN[8]
VD1_8
DIN[9]
DIN[0-23]
DIN[10]
MD[6]
DIN[11]
DIN[12]
MD[5]
DIN[13]
DIN[14]
MD[4]
DIN[15]
DIN[16]
DQS[0]
DIN[17]
DIN[18]
DIN[19]
DQM[0]
DIN[20]
MD[3]
DIN[21]
VDDMQ_2V5
MD[1]
DIN[22]
DIN[23]
100n
16V
C451
MD[2]
MD[0]
C452
DIN[21]
DIN[22]
100n
DIN[20]
DIN[23]
VD1_8
VREFN_3
VREFP_3
VREFP_2
VREFN_2
VDDH
100n
16V
C467
C463
100n
16V
C462
100n
16V
C460
100n
16V
C457
100n
16V
C450
2u2
R2218
33R
AVDD_ADC3
L404
VA1_8
C427
100n
16V
C445
16V
10u
100n
16V
C442
100n
16V
C2234
100n
16V
100n
16V
C429
100n
100n
16V
C2233
C426
100n
26R_100MHZ_1.5A
AVDD_ADC1
L406
L409
C458
100n
16V
10u
C454
26R_100MHZ_1.5A
AVDD_ADC2
100n
16V
VA1_8
100n
16V
C2242
VCCA_3V3
VA1_8
26R_100MHZ_1.5A
150R 600mA lik ferit
L408
PAVDD
L402
VL1_8
C469
AVDD3_AVSP2
100n
16V
C2224
S445
MD[26]
VCCA_3V3
C2223
FB
Q401
BC848B
Q402
BC848B
C423
16V
10u
100n
16V
100n
16V
C421
100n
16V
C2222
100n
16V
C2254
100n
16V
C2221
S442
C2220
68p
C412
68p
SC2_FB_SVP
VCCA_3V3
100n 16V
MD[25]
C436
VCCA_3V3
R440
1R
L400
C410
STBY_5V
R428
1k
150R 600mA lik ferit
VDDH
C473
SCL3
10p
R414
68R
LVDS OUT
FB_CONTROL
100n
SCL_EX
C472
SDA3
R439
1k
R413
68R
MA[7]
100n
16V
C2241
VD1_8
R426
10k
SDA_EX
MA[6]
C446
100n
16V
C2232
C420
16V
100n
C2404
100n
16V
16V
10u
C2403
100n
16V
C2402
100n
16V
C2401
100n
16V
C2400
C433
16V
10u
100n
16V
100n
16V
C431
100n
16V
C2215
100n
16V
C2214
100n
16V
C2213
VD1_8
R425
10k
R423
10k
C2212
L401
STBY_3V3
MD[24]
MA[5]
100n
16V
C2240
26R_100MHZ_1.5A
MPUGPIO4
R424
1k
MPUCSON
MD[23]
100n 16V
10u
VCCA_3V3
VCCA_3V3
MAIN RGB INPUT
VDDL
MD[22]
C2231
C415
PAVDD1
R405
75R
50V
20p
MD[21]
MA[4]
C447
C2239
PB_B1
100n
16V C408
MD[20]
MA[3]
100n
S427
RGB_BIN
X400
C414
MD[19]
MA[2]
VREFP_1
50V
20p
MD[18]
VREFN_1
100n
16V C407
14.31818MHz
R404
75R
RGB_RIN
MD[17]
MA[1]
100n
PR_R1
MD[16]
MA[0]
C466
S426
C2238
PAVDD
100n
PDVDD
100n
VD1_8
C2237
C409
MD[15]
VDDL
C468
100n
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
DIN[0]
R403
75R
Y_G2
DIN[1]
100n
16V
R418
RGB_GIN
Y_G1
DIN[2]
Y_G1
PLF2
S425
C2236
C406
DIN[3]
S438
CVBS3
16V
10u
CVBS2
100n
S439
DIN[4]
VREFP_1
DIN[5]
VREFN_1
DIN[6]
S441
AVDD_ADC1
100n
16V
75R
C2235
R427
DIN[7]
AVDD3_AVSP2
100n
16V
PAVDD2
R402
75R
CVBS_SVP
PB_B2
DIN[9]
CVBS3
R2217 DIN[8]
33R
PB_B1
VDDMQ_2V5
CLK_2EX
C
100n
16V
C465
VREFP_2
100n
16V
R400
75R
C402
S431
VREFN_2
DIN[10]
CVBS2
DIN[11]
CVBS_SVP
MD[14]
VDDL
VSSL
MA0
MA1
VDDM8
MA2
MA3
VSSM8
MA4
VDDM7
MA5
MA6
VSSM7
MA7
MA8
VDDC6
MA9
MA10
VSSC6
MA11
MD15
VDDC5
MD14
VSSM6
MD13
VDDM6
MD12
VSSM5
DQS1
VDDM5
VSSM4
DQM1
MD11
VDDM4
MD10
MD9
VSSC5
MD8
MD7
VDDC4
MD6
VSSM3
MD5
VDDM3
MD4
VSSM2
DQS0
VDDM2
VSSM1
DQM0
MD3
VDDM1
MD2
MD1
VSSC4
MD0
DIN20
DIN21
DIN22
DIN23
VSSC3
VDDC3
VSSH3
VDDH3
SVP_EX_51
100n
16V
C2230
C400
MD[13]
VDDH
AVDD_ADC2
DIN[12]
MAIN PICTURE
DIN[13]
PR_R2
MD[12]
IC224
MLF1
R401
75R
PR_R1
DIN[14]
VREFP_3
100n
100n
16V
C2229
VREFN_3
DIN[15]
C
DIN[16]
S430
DIN[17]
AVDD_ADC3
100n
16V
C2228
R244
DIN[18]
5
R4
MD[11]
XTALO
PAVDD1
MLF1
PAVSS1
PAVDD2
PLF2
PAVSS2
VSSC1
VDDC1
AIN_HS
AIN_VS
TESTMODE
RESET
SCL
V5SF
SDA
PWM
FLD_IO
VDDH1
VSSH1
H
V
DE
PLL_VCC
PLL_GND
TD1+
TD1TCLK+
TCLKTC1+
TC1LVDSGND
LVDSVCC
TB1+
TB1TA1+
TA1LVDSVDDP
GPO
VDDC2
VSSC2
DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
DIN13
DIN12
VDDH2
VSSH2
DIN11
DIN10
DIN9
DIN8
CLK
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
C_SELECTED
4
DIN[19]
MPUCSON
C401
100R
VD1_8
INT#
C2227
C411
6
R3
MD[9]
R422
10k
7
TXOUT0-
R2
3
VCCA_3V3
2
100n
VD1_8
TXOUT0+
8
TXOUT1-
ALE_EMU
R1
TXOUT1+
WR_EMU
1
C432
RD_EMU
TXCLKOUT-
5
TXOUT2-
R4
TXCLKOUT-
4
TXOUT2+
MCA[7]
TXCLKOUT-
R243
100R
TXCLKOUT+
6
R2212
10k
R3
7
TXCLKOUT+
R2
16V
10u
3
100n
16V
MCA[6]
TXOUT3-
2
PR_R2
100n
16V
TXCLKOUT+
MCA[5]
TXOUT3+
8
S440
R1
R2211
10k
1
DE_2EX
5
R228
100R
MCA[4]
C405
R4
100n
16V
C430
4
SC2_FB_SVP
MCA[3]
DVS_2EX
STBY_3V3
DHS_2EX
6
S415
5
100n
16V
C2226
R4
DIGITAL SINC
MCAD[7]
VDDH
6
PARITY
7
R3
SDA_EX
3
PWM2
MCAD[6]
7
100n
16V
8
R2
1N4148
R3
8
100n
16V
C2225
2
4
3
R1
MD[8]
MD[10]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
R407
75R
MCAD[4]
MCA[2]
100n
16V
PC&YPbPr INPUT
R408
75R
R2
VD1_8
SCL_EX
2
5
R234
100R
MCA[1]
PB_B2
RIN2
R1
R4
MPUGPIO0
A_D0
A_D1
A_D2
A_D3
VDDC12
VSSC12
A_D4
A_D5
A_D6
A_D7
VDDH5
VSSH5
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
VDDC11
VSSC11
RD
WR
ALE
MPUCSON
INT
AVDD_ADC3
AVSS_ADC3
VREFN_3
VREFP_3
PR_R1
PR_R2
AVDD_ADC2
AVSS_ADC2
VREFN_2
VREFP_2
C
PB_B1
PB_B2
AVDD3_AVSP2
AVSS3_BG_ASS
CVBS_OUTP
CVBS_OUTN
AVDD_ADC1
AVSS_ADC1
VREFN_1
VREFP_1
CVBS1
CVBS2
CVBS3
AIN_N1
Y_G1
AIN_N2
Y_G2
AIN_N3
VSSC13
VDDC13
PDVDD
PDVSS
PAVDD
PAVSS
XTALI
D101
1
C404
BIN2
4
MCAD[5]
R233
100R
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
MCAD[3]
1
MCA[0]
6
100n
16V
100n
16V
MCA[0-19]
R406
75R
Y_G2
R3
C413
MCAD[0-7]
C403
GIN2
RST_H
3
R420
MCAD[2]
C422
7
4k7
R2
R419
2
MCAD[1]
22R
8
22R
R1
VGA_VSIN
1
VGA_HSIN
MCAD[0]
NC
MPUGPIO1
MPUGPIO2
MPUGPIO3
MPUGPIO4
VSSH4
VDDH4
VSSC10
VDDC10
MD31
VSSC9
MD30
MD29
VDDM16
MD28
DQM3
VSSM16
VDDM15
DQS3
VSSM15
MD27
VDDM14
MD26
VSSM14
MD25
VDDC9
MD24
MD23
VSSC8
MD22
MD21
VDDM13
MD20
DQM2
VSSM13
VDDM12
DQS2
VSSM12
MD19
VDDM11
MD18
VSSM11
MD17
VDDC8
MD16
BA1
VSSC7
BA0
CLKE
VDDC7
WE
VSSR
MVREF
VDDR
CAS
RAS
VDDM10
CS1
VDDM9
CS0_
VSSM10
MCK0_
MCK0
VSSM9
S411
R236
100R
100n
16V
16V
10u
100n
16V
C455
100n
16V
100n
16V
C2219
100n
16V
C2218
C428
S437
VL1_8
100n
16V
C2217
R1
4
C418
L407
C2216
1
ODD_PINK
DIGITAL IDTV INPUTS [ITU 601]
26R_100MHZ_1.5A
VD1_8
STBY_3V3
DIN[0]
DIN[1]
DIN[2]
DIN[3]
DIN[4]
DIN[5]
DIN[6]
DIN[7]
DIN[6]
5
4
3
2
PL104
2n7
50V
74LX1G86STR
R2214
3
C425
R433
10k
PDVDD
VDDMQ_2V5
VDDMQ_2V5
DHS_2EX
R432
10k
C443
16V
10u
100n
16V
100n
16V
C2211
100n
16V
C2210
C439
100n
16V
C2209
100n
16V
C2208
C2207
R436
22R
IC107
2
DIN[7]
S110
PAVDD2
R429
22R
22R
R430 R431
22R
C438
2n7
50V
PLF2
ODD_PINK
R2210
10k
C444
16V
10u
100n
16V
100n
16V
C2205
100n
16V
C2204
100n
16V
C2203
VL1_8
1
MLF1
100n
16V
C440
C2206
R435
22R
CLK_2EX
PAVDD1
VESTEL ELECTRONICS
TV R&D GROUP
TFT TV
17MB15E-5 TFT VIDEO DECODER
VER E0
DATE
21/4/2004
M.KURSAT SHEET4
SARIARSLAN
VESTEL ELEKTRONICS
TV R&D GROUP
R516
15R
DDQS3
MCLK01
R503
R518
33R
5
MA[11]
BA1
MA[10]
R519
33R
MA[9]
MA[7]
MA[0-11]
R521
33R
R520
33R
MA[8]
MA[6]
MA[5]
MA[4]
MA[3]
MA[2]
MA[1]
DQM[1]
DQM[2]
VDDMQ_2V5_FLT
VCCA_2V5_FLT
R510
1k
C501
10R
R508
1u
DDQS3
DDQS2
DQM[3]
VDDMQ_2V5_FLT
MVREF
VDDMQ_2V5_FLT
C517
MD[31]
1
MD[30]
VCCA_2V5_FLT
VDD_D3
VDD_K10
VDD_K7
VDD_K6
VDD_K3
VSS_H8
VSS_H7
VSS_H6
VSS_H5
VSS_G8
VSS_G7
VSS_G6
VSS_G5
VSS_F8
VSS_F7
VSS_F6
VSS_F5
VSS_E8
VSS_E7
VSS_E6
VSS_E5
VSS_D9
VSS_D7
VSS_D6
VSS_D4
VSS_J8
VSS_J7
VSS_J6
VSS_J5
VSS_K9
VSS_K4
VSQ_J9
VSSQ_H9
VSSQ_J4
VSSQ_H4
VSSQ_G9
39
118
115
114
111
92
91
90
89
80
79
78
77
68
67
66
65
56
55
54
53
45
43
42
40
104
103
102
101
117
112
105
93
100
88
81
25V
10n
C504
16V
100n
C511
25V
10n
C503
16V
100n
C512
25V
10n
C2253
16V
100n
C513
25V
10n
C2252
16V
100n
R505
47R
C2250
16V
100n
C520
L501
R2208
10R
MCLK0#
C2251
16V
100n
C519
25V
10n
MCLK01
R2209
10R
MCLK01#
BLM21B201S
MCLK0
R4 5
MD[0]
C515
16V
100n
C510
25V
10n
4
R3 6
MD[1]
3
R2 7
MD[2]
2
R511
10R
R1 8
MD[3]
1
R4 5
C527
16V
100n
C509
R4 5
4
C528
16V
100n
C508
25V
10n
10n
25V
MD[4]
C529
16V
100n
C507
25V
10n
C500
1
C530
16V
100n
C506
50V
4n7
4
R3 6
3
MD[8]
2
R2 7
MD[9]
MD[10]
MD[11]
R507
10R
1
R1 8
C531
16V
100n
C521
50V
4n7
R504
47R
DDQS0
DDQS1
DQM[0]
DQM[1]
R4 5
R3 6
MD[12]
MD[13]
MD[14]
C532
16V
100n
C514
25V
10n
4
R2 7
2
3
R506
10R
R1 8
1
16V
100n
C522
50V
4n7
6
17
5
4
13
26
25
37
50
49
62
61
86
85
97
98
2
74
1
73
132
3
10
27
28
29
32
33
34
41
44
52
57
64
69
76
DQM[3]
MD[15]
DQM[0-3]
DQM[0]
100u
16V
C523
50V
4n7
DQ0_A6
DQ1_B5
DQ2_A5
DQ3_A4
DQ4_B1
DQ5_C2
DQ6_C1
DQ7_D1
DQ16_E2
DQ17_E1
DQ18_F2
DQ19_F1
DQ20_H2
DQ21_H1
DQ22_J1
DQ23_J2
DM0_A2
DM2_G2
DQS0_A1
DQS2_G1
NC_L12
VSSQ_A3
VSSQ_A10
VSSQ_C3
VSSQ_C4
VSSQ_C5
VSSQ_C8
VSSQ_C9
VSSQ_C10
VSSQ_D5
VSSQ_D8
VSSQ_E4
VSSQ_E9
VSSQ_F4
VSSQ_F9
VSSQ_G4
MA[0]
R3 6
R4
R2 7
4
CS0#
BA0
3
6
2
R3
3
RAS#
MD[5]
7
EM6A9320
IC1
MD[6]
R2
R517
33R
CLKE
DQ28_A9
DQ29_A8
DQ30_B8
DQ31_A7
NC_B10
NC_G10
NC_K12
NC_K11
NC_L3
NC_M2
NC_L2
NC_G3
NC_B3
NC_K8
NC_L9
CK-_L11
CK_L10
CKE_M11
WE-_K2
CAS-_K1
RAS-_L1
CS-_M1
BA0_M3
BA1_L4
A11_L6
A10_K5
A9_L7
A8/AP_M10
A7_M9
A6_M8
A5_L8
A4_M7
A3_M6
A2_L5
A1_M5
A0_M4
R509
10R
R1 8
2
C524
50V
4n7
C526
BLM21B201S
DDQS2
8
MUHAMMET KURSAT
SHEET 5
SARIARSLAN
C525
50V
4n7
1u
50V
L500
DDQS1MCLK01#
R515
15R
R1
50V
4n7
C502
VCCA_2V5
R514
15R
DQS[2]
1
100u
16V
VDDMQ_2V5
DQS[1]
CAS#
2
100n
DDQS0
WE#
7
8
R513
15R
DQS[3]
6
DQM[2]
5
9
8
20
7
22
82
120
119
123
134
122
75
15
116
129
131
130
143
110
109
121
133
135
124
126
113
127
142
141
140
128
139
138
125
137
136
MD[7]
DQS[0-3]
DQS[0]
DATE
21/4/2004
C505
24
35
36
48
59
60
71
72
95
96
107
108
11
83
12
84
144
14
16
18
19
21
23
38
47
51
63
87
99
58
70
94
106
31
30
46
MD[0-31]
MD[16]
R4
C518
R512
1k
DQ27_B12
DQ26_C11
DQ25_C12
DQ24_D12
DQ15_E11
DQ14_E12
DQ13_F11
DQ12_F12
DQ11_H11
DQ10_H12
DQ9_J11
DQ8_J12
DM3_A11
DM1_G11
DQS3_A12
DQS1_G12
VREF_M12
VDDQ_B2
VDDQ_B4
VDDQ_B6
VDDQ_B7
VDDQ_B9
VDDQ_B11
VDDQ_D2
VDDQ_D11
VDDQ_E3
VDDQ_F3
VDDQ_H3
VDDQ_J3
VDDQ_E10
VDDQ_F10
VDDQ_H10
VDDQ_J10
VDD_C7
VDD_C6
VDD_D10
5
R4
100n
VER E0
17MB15E-5 TV DDR RAM
C516
R502
MD[19] 10R
1 R1 8
MD[18]
2
7
R2
MD[17]
3
R3 6
4
MD[29]
4
5
5
R4
R501
MD[23] 10R
1 R1 8
MD[22]
2
7
R2
MD[21]
3
R3 6
MD[20]
4
R1
6
R3
R3
MD[24]
4
R4
MD[25]
3
R2
R500
MD[27] 10R
1 R1 8
MD[26]
2 R2 7
3
MD[28]
TFT TV
R412
22R
Q400
BC337
R417
22R
BRT_CNTL
R604
4k7
STBY_5V
BRIGHTNESS CONTROL
VCCA_2V5
R6015
220R
R6016
220R
SCL
LEVEL SHIFTER
SDA
E2
STBY_3V3
C604
VCCA_3V3
PDP_GO1/BL_ON_OFF
BC848B
S600
R6037
1k
R6038
1k
L601
PDP_GO/BL_ON_OFF
D600
BZT55C5V1
2
1
LOC_KEY
1
PL606
2
3
C611
22u
PL604
UP_RXD
UP_IRQ
22u
50V
100n
FL_A15
BLM21B201S
C613
CPU_GO
Q6009
UART SOCKET FOR IDTV
S629
PL308
S628
UP_TXD
S627
2
4
25V
100n
C622
25V
100n
R653
3k9
C625
3k9
R660
Q6008
BC848B
CPU_GO1/STBY
PL605
1
P1_0 41
4
VSS1 39
93 A2
P3_7 38
3
94 A1
P3_6 37
LOC_KEY
P3_4 35
100n
P3_3 34
C633
4k7
98 D6
P3_2 33
99 D0
P3_1 32
100 D5
P3_0 31
R2306
100R
VCCD3.3V_FLT
R6014
4k7
Q6010
BC848B
VER. E0
TFT TV
C621
C626
C628
100n
25V
SC2_FB
STBY_5V
MMC_IR GIRISI
21/4/2004
DATE
TV-LINK
R6044
4k7
R6041
4k7
R6017
4k7
R682
4k7
4k7
R681
4k7
R680
R679
4k7
C630
30
29
28
27
26
25
MCA[5]
MCA[3]
83 A9
P4_2 48
8
R1
1
84 A5
P1_6 47
GAL_IAP
R2
2
85 A11
P1_5 46
UP_IRQ
3
86 A4
P1_4 45
NVM_WP
87 ALE
P1_3 44
SCL3
88 PSEN
P1_2 43
SDA3
P1_1 42
PORT
VS
HS_SSC
NC
P2_3
P2_2
P2_1
4
VCCD_3V3
R691
4k7
P3_5 36
R692
R6039
100R
25V
100n
S6313
PC_STBY
SDA_TVLINK
2k7
R2300
M.KURSAT
SARIARSLAN
STBY_3V3
VDD3_3_1 40
25V
100n
SDA5550M
R693
4k7
BC848B
P2_0
24
MCA[9]
S6314
VSSA
23
P4_3 49
69
68
67
66
65
A16
A18
A19
NC5
RD
55
54
53
52
51
VSSA1
NC2
XTAL1
XTAL2
NC1
56
70
A17
VDDA2_5_1
71
A15
72
74
FL_PGM
VSS2
73
RST 50
HDMI_CEC
VDDA2_5
22
82 A6
R6040
4k7
CVBS
21
81 A8
3
4
MCA[19]
R686
75R
R685
75R
R684
75R
100k
R687
33p
50V
C627
C624
50V
33p
NC3
P1_7
NC4
WR
R640
4k7
4k7
R676
C631
25V
100n
L604
61
62
63
64
MCA[18]
MCA[16]
MCA[17]
RD_EMU
R4 5
R3 6
R2 7
2
3
R639
10R
R1 8
1
LM809
IC221
R2302
47k
C620
Q2301
EXTIF
20
2
3
S613
OCF
19
R2
VDD2_5_1
MCA[15]
MCA[14]
STBY_2V5
1k
BLANK_COR
R6042
100n
C615
STBY_3V3
MCA[19]
MCA[18]
MCA[16]
MCA[17]
STBY_2V5
VCCD3.3V_FLT
STBY_3V3
BC848B
25V
100n
57
58
R
59
B
G
60S601
R648
4k7
R6043
4k7
STBY_3V3
VCCD3.3V_FLT
R2301
47k
STOP
18
97 A0
Q2300
ENE
17
96 D7
R624
10R
S614
P0_7
16
91 VSS3
STBY_3V3
R697
PIN8_SC3
3k9
3k9
R657
P0_6
15
1
95 FL_CE
15k
R656
P0_5
14
2
1k
R661
C607
L603
S615
S610
4k7
IC220
15k
R655
SDA3
STBY_2V5
DVD_12V_SENSE
15k
R698
R696
76
A14
MCA[15]
MCA[12]
MCA[13]
STBY_3V3
RST_H
TV_LINK
R2304
100R
STBY_3V3
P0_4
89 A3
BC848B
SW_ENABLE
13
77
A12
C612
Q2299
SCL3
75
78
A13
R4 5
MCA[14]
MCA[12]
MCA[13]
R632
4k7
STBY_2V5
S608
15k
R654
STBY_2V5
4k7
1
VDD3_3_2
79
A7
4
R3 6
R2 7
2
3
R629
10R
R1 8
MCA[18]
MCA[12]
STBY_3V3
PIN8_SC2
SCL2
22u
50V
PIN8_SC1
S607
P0_3
90 A10
CPU_GO1/STBY
SDA2
C608
RX1_INT
PSEN_UP
25V
100n
R695
5
12
92 VDD3_3_3
RX1_RST#
R4
4k7
6
R694
R3
4k7
4
R690
MCAD[5]
R6031
47R
3
1
MCA[12]
MCAD[4]
MCAD[5]
MCAD[6]
MCAD[7]
WR_EMU
R2305
10k
16V
100n
7
MUTE_AMP
S622
R2
P0_2
MCAD[0]
2
11
MCAD[0]
8
AC_INFO
MCAD[6]
R1
P0_1
MCAD[6]
1
10
30
A17
25V
100n
4k7
31
W
MCA[10]
MCA[11]
MCA[12]
MCA[13]
100n
25V
R6013
10R
R625
R6030
47R
MCAD[7]
C609
SCL2
MCAD[7]
8
P0_0
MCA[0]
9
MCA[0]
7
4k7
MCA[1]
6
R689
MCA[1]
SDA2
32
VCC
FL_WE
VDD3_3
MCA[2]
VSS
1
A18
S604
8
2
A16
80
3
A15
MCAD[4]
MCAD[5]
MCAD[6]
MCAD[7]
MCA[14]
MCA[16]
MCA[17]
MCA[18]
MCA[19]
FL_A15
7
MCA[2]
5
VDD2_5
MCA[10]
R688
4k7
MCAD[5]
ALE_EMU
XROM
MCA[10]
R1
7
FL_RST
4
MCA[10]
MCA[11]
MCA[12]
MCA[13]
MCA[14]
A12
23
S623
MCA[16]
MCA[17]
MCA[18]
MCA[19]
100n
25V
6
PSEN_UP
5
MCAD[7]
D3
MCAD[7]
D2
MCA[11]
R4
R4 4
R626
10R
4
DQ7 21
5
3
MCA[3]
1
MCA[4]
5
R3
STBY_3V3
L600
8
MCAD[0]
MCA[5]
MCAD[3]
E 22
6
MCAD[3]
MCA[11]
D4
MCA[10]
2
MCA[10]
7
2
A10 23
MCA[4]
3
MCA[11]
7
FL_OE
6
A11 25
MCA[9]
MCAD[2]
MCA[6]
8
R3
MCAD[2]
MCA[9]
6
D1
MCA[11]
MCA[6]
1
MCA[8]
4
A9 26
R627
10R
MCAD[4]
5
MCA[8]
MCAD[4]
MCA[9]
MCA[8]
R6036
4k7
MCAD[1]
10R
R628
MCA[7]
STBY_3V3
MCAD[1]
MCA[7]
R6035
A8 27
STBY_3V3
MCA[8]
C606
MCA[13]
25V
100n
VCCD3.3V_FLT
MCA[4]
4k7
IC218
24
25
26
27
28
29
30
31
32
FL_A14
C610
100n
16V
SDA SCL
BSN20
Q603
1
13 DQ0
A0
MCA[1]
2
DQ6
20
G 24
A1
DQ5
19
MCA[5]
8 VCC
SDA3
24LC32A
DQ4
18
A13 28
7 WP
DQ3
17
CORRESPONDS TO
Winbound W27E040 EPROM &
ST M29F040 Flash
3
MCAD[6]
MCAD[5]
MCAD[4]
IC219
M29W040B
A2
MCAD[6]
MCAD[5]
MCAD[4]
MCAD[3]
VSS
16
A4
4
60
MCAD[3]
A5
VSS
SDA3
59
ALE_EMU
DQ2
15
A6
S602
R6010
10k
58
RST#
MCAD[2]
33
34
35
36
37
38
39
40
41
42
NC5
6
C603
100u
16V
R610
10k
57
56
MCAD[2]
NC6
NC7
A10
A11
A12
A13
A14
I/O5
I/O6
MCA[13]
A14 29
NVM_WP
BSN20
Q602
DQ1
SRAM_WE
14
A3
55
S6317
MCAD[1]
12 A0
54
MCAD[1]
MCA[0]
STBY_3V3
WR_EMU
11 A1
53
S6318
NC4
NC3
A9
10 A2
S603
R607
10k
52
22
21
20
MCA[2]
SCL
R601
4k7
50
MCAD[0]
51
MCA[0]
SRAM_WE
MCA[9]
MCA[1]
RD_EMU
SRAM_OE
PSEN_UP
FL_OE
MCA[15]
MCA[14]
MCA[13]
MCA[12]
MCA[11]
MCA[10]
MCA[9]
MCA[8]
MCAD[7]
MCAD[6]
MCA[9]
A8
A7
A6
A5
WE
I/O4
I/O3
9
49
S6319
S6320
MCA[15]
MCA[14]
MCA[13]
MCA[12]
MCA[11]
MCA[10]
MCA[9]
MCA[8]
MCAD[7]
MCAD[6]
MCAD[5]
MCAD[4]
MCAD[3]
MCAD[2]
MCAD[1]
MCAD[0]
19
18
17
16
15
14
13
MCA[2]
48
46
44
42
40
38
36
34
32
30
28
26
24
22
MCAD[5]
MCAD[4]
MCA[16]
MCA[8]
MCA[7]
MCA[6]
VCC1
VSS1
I/O7
I/O8
OE
A15
A16
A17
A18
NC8
43
44
K6R4008V1C-I/C-P
VSS
VCC
I/O2
I/O1
CS
A4
A3
MCA[3]
47
45
43
41
39
37
35
33
31
29
27
25
23
21
20
18
MCAD[3]
MCAD[2]
MCAD[1]
MCAD[0]
MCA[8]
S624
MCA[5]
MCAD[3]
MCAD[2]
12
11
10
9
8
7
6
8
6
SCL3
VCCA_3V3
MCA[7]
MCA[6]
19
17
16
14
12
10
8
MCA[17]
MCA[18]
MCA[7]
MCA[6]
MCA[5]
MCAD[1]
MCAD[0]
MCA[15]
MCA[4]
MCA[3]
A2
A1
A0
MCA[3]
5 SDA
Q601
STBY_3V3
MCA[7]
MCA[6]
MCA[5]
MCA[4]
15
13
11
9
7
MCA[16]
MCA[17]
MCA[18]
MCA[19]
MCAD[3]
MCAD[2]
MCAD[1]
MCAD[0]
MCA[15]
MCA[4]
MCA[3]
5
4
3
NC9
NC10
MCA[6]
A7
SCL2
R6007
10k
MCA[5]
MCA[4]
MCA[3]
MCA[2]
MCA[1]
MCA[0]
6
4
2
19
Q7
MCA[14]
MCA[15]
MCA[16]
MCA[2]
MCA[1]
MCA[0]
NC2
NC1
MCA[4]
SDA2
Q600
7
100R
R611
Q605
S6316
R6005
47k
MCA[3]
MCA[2]
MCA[1]
MCA[0]
5
3
1
1
20
CLK
MCA[14]
2
MCA[15]
3
VCC
I0
I1
MCA[2]
MCA[1]
MCA[0]
2
1
MCA[5]
STBY_5V
4k7
R600
S606
Q604
100R
R606
100R
R6011
100R
R6006
SCL3
SCSDA
STBY_5V
SCSCL
FL_A16
S6315
FL_A17
Q2 14
S605
Q3 15
PL607
MCA[19]
SRAM_OE
STBY_3V3
Q4 16
STBY_5V
I4
S6311
6
PL600
SRAM_WE
1
Q5 17
2
I3
3
5
4
MCA[18]
S6312
FL_A14
5
FL_OE
S6310
IR
S6300
BC848B
Q6006
Q1
Q0
OE
Q6 18
BC848B
Q6007
R6018
22k
GAL_IAP
LED1
13
12
11
GND
I7
MCA[16]
FL_WE
CIRCUIT OF SW UPDATE FROM SCART2
100n
16V
C419
VCC_5V
C417
9
I6
10
I5
8
16V
100u
I2
LED2
S414
R416
4k7
4
R6019
22k
PWM
C416
S412
50V
10u
R415
1k2
STBY_3V3
MCA[6]
5
R1
S621
7
STBY_3V3
MCA[7]
R1
PWM2
MCA[17]
IC622
GAL16LV8
100n
16V
MCA[7]
R2
C600
FL_A16
R2
WR_EMU
C601
MCA[18]
R3
RD_EMU
16V
100n
C605
R4
S620
SRAM_OE
R3
MCA[19]
STBY_3V3
R4
IC217
STBY_3V3
BLM21B201S
L609
VCCD_3V3
Q6011
BC848B
1
2
RST#
25V
100n
6MHz
FL_A17
C623
X600
RST#
PDP_GO1/BL_ON_OFF
INT#
PWM
STBY_3V3
UP_RXD
STBY_3V3
LED1
PROTECT
LED2
SDA_TVLINK
UP_TXD
IR
VCCA_2V5
FB
R2303
10k
VCC_8V
IR
2
1
VESTEL ELECTRONICS
TV R&D GROUP
3
17MB15E-5 TFT TV MCU INTERFACE
Sheet 06
IC3000
LM1117
P1_5V
R2067
470k
R2066
470k
P1_EVCC5
IC2013
1
S1
52
53
54
55
S2
R2069
10k
Q12
C2100
AMP_PIN7
DIN[23]
DIN[22]
DIN[21]
DIN[20]
DIN[16]
R4 5
R4 5
AUDIO_AVCC5
AMP_PIN6
4
51
5
5
R4
S816
96 RX2-
1
97 RX2+
PL2001
PLLIN
2
24
95 AVCC3
PVCC2
3
AVCC_SII
PGND2
94 AGND4
23
AGND_SII
S810
22
4
OVCC
93 AVCC2
21
AVCC_SII
5
DHS_2EX
1
R1
8
WS 31
2
R2
7
R3
6
R4
5
SPDIF 29
OGND1 28
99 GND4
MCLKIN 27
VCC_SII
100 VCC4
MCLKOUT 26
4
DAC_SCK
2n7
50V
DAC_WS
DAC_SD0
OGND_SII
R2040
33R
R2073
270k
AUDIO_AGND
R2041
33R
VCC_5V
OGND_SII
P1_EVCC5
BZT55C5V6
1n
50V
C2087
100n
25V
C2086
100n
25V
C2085
C2084
C2083
16V
10u
1n
50V
S804
D2021
R2071
10R
A D2020 K
1
2
P1_CBL5V
0VCC_SII
D2022
GND_SII
S803
1N5817
E
6
AMP_PIN3
AUDIO_AGND
AOUTL
SDATA
IC2006
DAC_SD0
1
1OE
2
1A
A8
8
2OE
7
D
4
R2095
10k
S808
RSVDO2
20
HDMI_3V3
VCC_5V
HDMI_3V3
S809
0VCC_SII
RSVDO1
VCC1
17
RSVDL1
GND1
16
GND_SII
19
ANBPB
15
18
DACVCCB
14
100n
25V
1N5817
S802
HDMI_3V3
pin8
P1_5V
1n
50V
1n
50V
C2082
100n
25V
C2081
100n
25V
C2080
C2079
C2078
16V
10u
VCC_SII
C2065
R2074
270k
25V
100n
SN74CB3Q3305
S807
HDMI_CEC
3
1B
2B
6
4
A4
2A
5
Q1
2N7002
S801
close to
1
S806
CEC
BZT55C5V6
AUDIO_AGND
330R_100MHZ_3A
HDMI_3V3
10u
16V
Place cap.s
C2064
IC2014
C2066
D2023
L2017
AGND_SII
C2063
50V
10u
R2096
27k
S800
TOCOMP
C2067
R2097
330k
AUDIO_AVCC5
330R_100MHZ_3A
25V
10u
25V
47n
60R_100MHZ_3A
10n
25V
C2061
3k9
R2039
C2062
25V
100n
L2013
VCC_5V
1n
50V
100n
25V
C2077
100n
25V
C2076
C2075
C2074
16V
10u
100n
25V
C2073
L2015
L2016
AVCC_SII
chip as possible
HDMI_3V3_PLL
60R_100MHZ_3A
HDMI_3V3
R2038
4k7
DACGNDB
13
C2060
compact and as close to
50V
1n
10u
50V
C2094
Place PLL circuit as
Place close to pins 22&23
S805
Close to pin9
VCC_SII
ANGY
12
COMP
8
DACVCCG
ANRPR
7
TOCOMP
11
DACVCCR
6
RSET
DACGNDR
5
DACGNDG
NC2
4
1n
9
NC1
3
10
DACGND
2
C2059
R2035
100R
DACVCC
1
1n
100n
C2058
100n
C2057
C2056
C2055
L2012
10u
C2054
100n
25V
RX1_AVCC3
60R_100MHZ_3A
HDMI_3V3
AUDIO_AGND
2n7
50V
C2095
DAC_MCLK
8
GND_SII
3
C2089
AUDIO_AGND
SCK 32
SDO 30
98 AGND5
AGND_SII
R2042
33R
C2097
3u3
50V
HSYNC 33
R2043
33R
S811
2n7
50V
5
92 RX1+
6
2n7
50V
4k7
R2084
VSYNC 34
DVS_2EX
R2082
2k32
DE_2EX
R2044
33R
C2096
DE 35
91 RX1S812
AUDIO_AGND
C2090
AUDIO_AGND
R2045
33R
S813
7
5
R4
C2098
R2083
2k32
4
Q23 36
6
R3
7
90 AGND3
Q22 37
7
R2
VA
AGND_SII
3
DEM/SCLK
8
2
2k32
R2076
89 AVCC1
Q21 38
8
R1
2k32
R2075
AVCC_SII
1
AUDIO_AGND
9
NC3
IC2002
SII9993
88 AGND2
AGND_SII
10
R2046
33R
Q20 39
25
87 RX0+
11
MCLK
VCC_SII
4
VCC2 40
S814
DAC_MCLK
86 RX0-
AGND_SII
S815
12
270p
50V
AUDIO_AGND
GND_SII
R2079
1k2
GND2 41
AUDIO_AVCC5
85 AGND1
AUDIO_AGND
3u3
50V
CEC
F
7
MC33202
C2092
C2091
14
4
Q19 42
84 RXC+
C2093
AMP_PIN7
S817
50V
10u
R2081
560R
DAC_AOL
AMP_PIN6
6
R3
AMP_PIN3
3
R2078
5k6
Q18 43
R2077
4k7
83 RXC-
R2086
5k6
7
R2085
1k2
R2
C2088
Q17 44
R2080
100k
P1_DDC_SCL
82 AVCC
AUDIO_AGND
15
AVCC_SII
C
8
3
R1
2
1
1
G
H
R2047
33R
OGND_SII
6
OGND2 45
AGND
ODCK 46
0VCC_SII
R2048
33R
CS4334
OVCC2 47
LRCK
79 PGND1
3
Q16 48
DAC_WS
78 OGND5
R2094
33R
B
Q15 49
AUDIO_AVCC5
R2090
47k
270p
50V
8
Q13
77 DSCL
R2089
47k
100n
25V
AOUTR
R3 6
R2 7
2
3
R2049
33R
R1 8
1
4
Q6
Q5
Q4
Q3
VCC3
GND3
OVCC4
OGND4
Q2
Q1
Q0
INT
RESET
CSCL
Q14 50
2n7
50V
P1_DDC_SDA
AUDIO_AGND
10u
50V
C2104
AUDIO_AGND
CLK_2EX
76 DSDA
AUDIO_AGND
C2103
C2102
C2099
81 EXT_RES
RX1_AVCC3
C3009
100u
16V
R2091
20k
10u
50V
25V
100n
80 PVCC1
P1_CBL5V
16
13
560R
R2087
A
OGND_SII
P1_HPD
17
DIN[7]
DIN[6]
DIN[5]
DIN[4]
DIN[3]
DIN[2]
56
R3 6
3
OVCC3
0VCC_SII
DIN[1]
57
58
Q8
R2 7
2
OGND_SII
R3 6
R4 5
4
3
60
R2 7
2
61
62
OGND3
DIN[0]
DIN[15]
Q7
59
R2050
33R
1
R1 8
DIN[14]
DIN[13]
DIN[12]
DIN[11]
R3 6
R4 5
63
R2051
33R
1
R1 8
4
3
VCC_SII
64
R2 7
2
65
GND_SII
R2052
33R
R1 8
1
0VCC_SII
OGND_SII
66
67
68
69
70
71
RX1_RST#
72
R2053
4k7
73
74
75
DSDA
DSCL
1n
50V
C3008
100n
16V
C2101
DAC_AOR
MC33202
TP100
100n
25V
C2071
RSVDL2
10u
50V
C2070
HDMI_3V3
AUDIO_AGND
CSDA
L2014
Place close to pins 79&80
C2069
RX1_INT
SCL3
SDA3
C2068
S819
S818
60R_100MHZ_3A
25V
100n
18
DIN[9]
R2065
56R
DIN[10]
P1_DDC_SDA
DIN[8]
HDMI_3V3_PLL
R2064
56R
C3006
100u
16V
4
DIN[0-23]
P1_DDC_SCL
3 IN OUT 2
GND VOUT
C3007 1
4
100n
16V
VCC_5V
C3005
100n
16V
24LC02
19
4
DSCL
2
5
D2
IC3001
LM1117
2
SDA
3
C3004
100u
16V
SOGUTULMALI
DAC_SCK
VSS
RX1_RST#
DIN[19]
4
5
AUDIO_AGND
6
C3003
100n
16V
R2088
100k
SCL
5
S2
G2
IC2008
A2
D2
G1
DIN[18]
3
HDMI_3V3_PLL
REGULATORLAR COK IYI
AUDIO_AGND
7
C3001
100u
16V
2n7
50V
WP
P1_HPD
DIN[17]
A1
G2
SW_ENABLE
3
2
C3000
100n
16V
MUMKUN OLDUGUNCA 9993 E YAKIN OLMALILAR
Q11
R2098
100R
G1
2
4k7
R2068
6
Q10
2
Q2
BC848B
8
D1
Q9
VCC
S1
UPA672T
R2063
47k
R2062
4k7
100n
25V
C2072
1
IC2003
A0
6
UPA672T
VCC_5V
1
D1
3 IN OUT 2
GND VOUT
C3002 1
4
100n
16V
VCC_5V
DSDA
IC2012
24LC02
R2070
1k
HDMI_3V3
VESTEL ELECTRONICS
17MB15E-5
TV R&D GROUP
PART
HDMI/DAC
AUTHOR
DATE
METEHAN
30.10.2004
ALTUNLU
Sheet
8 of 9
1
PL904
2
3
4
L918
VCC_12V
PL903
VCC_5V
VESTEL ELECTRONICS
TV R&D GROUP
1
S908
PANEL_VCC1
PDP_GO1/BL_ON_OFF
L906
VCC_12V
C900
5V
PL900
STBY_3V3
TFT TV
STBY_5V
VER. E0
17MB15E-5 TFT TV POWER SUPPLY
S910
3
LG_1/IRQPDP
4
AC_INFO
16V
100u
5V
S909
7
6
5
4
3
1
2
2
PL902
L917
VCCA_3V3
VCCA_3V3
DATE
M.KURSAT
SARIARSLAN
21/4/2004
MMC
SUPPLY
L909
Sheet 09
STBY_5V
N.C
STBY_5V
D905
FAN1616AS-3.3
2
+12V
3
C914
16V
220u
1N4007
2
D906
1
10u
STBY_2V5
IC904
1N4007
R922
3k3
D912
S907
C939
100n
16V
16V
100u
C936
C927
16V
100u
10k
R924
VA1_8
C941
16V
100u
100n
16V
C938
C930
22u
C929
100u
22u
100n
16V
L916
1_8VMAIN
C926
100n
16V
C913
SS33
C911
22u
D911
10u
16V
S912
C940
100n
16V
16V
100u
C937
C928
ON/OFF
5
100n
16V
VD1_8
16V
100u
22u
100n
16V
FEEDBACK
4
C925
L914
1_8VMAIN
C924
GND
3
C921
OUTPUT
2
VL1_8
Q903
1_8VMAIN
L910
BRT_CNTL
S901
DIG_DIM_PWM
R904
330R
L911
22u
S902
22uH_3.9A_SMD
S900
A_DIM_PWM
1_8VMAIN
S911
R905
160R
22u
C947
L915
S905
L908
16V
1000u
VCC_12V
STPS745
D904
10
BLM21B201S
SAP 30030067 ADJ TYPE
1.8V_ON/OFF
C905
9
16V
100u
PORT
D915
S913
VIN
8
VCC_12V
1
7
VCCD_3V3
D914
VCC_33V
VCCA_3V3
CPU_GO1/STBY
LM2576
VCCA_2V5
L922
C923
100n
16V
R925
10k
2
D913
IC903
LD1117
1N4148
3
PANEL_VCC
10u
C946
BLM21B201S
47u
50V
IC223
22u
L924
STBY_2V5
SOT 223
1
PROTECT
VCC_12V
100p
C944
R915
470R
N.C
1R
R913
L921
SEL
PANEL_VCC1
R909
120R
120R
R911
6
6
1N4007
VDDMQ_2V5
C922
100n
16V
Q902
5
D903
C919
100u
16V
C943
1
1N4007
VCC_8V
5
4
1N4148
2
D902
3 VIN VOUT2
GND
1
4
1N4007
3
56p
FDC642P
2
5
3
A_DIM_PWM
DIG_DIM_PWM
COMP.
330R
R923
D901
GND
VCC_33V
1
4
R919
2k2
R910
10k
1N4007
D910
C918
C915
100n
16V
16V
100n
PL901
PDP_GO/BL_ON_OFF
6
22u
1N4148
D900
N.C
VCC
C945
D909
CS52015-3
IC901
50V
22u C917
C931
16V
100u
L912
C902
CAP.
VCCD_3V3
47u
R901
470R
7
3
1N4148
100n
C935
100n
100n
C934
100n
C933
C932
C912
N.C
R900
470R
STBY_3V3
SENSE
MC34063A
56k
R921
VCCA_3V3
1.8V_ON/OFF
VCC_5V
22u
16V
1000u
100n
8
D908
L919
C903
VCC_5V
1N4148
R908
10k
Q900
BC848B
12
D907
1N4148
11
EMITTER
DRI.COL.
56p
R912
10k
BC858B
Q901
PROTECT
2
C942
STBY_2V5
5k6
R903
10
C910
100n
16V
47u
50V
C909
9
VCC_8V
R914
10k
L904
8
47u
50V
C901
7
STBY_3V3
3 IN OUT 2
ADJ
1
C904
100n
16V
R902
1k
R907
10k
L903
SW.COLL.
R917
100R
LM317
IC900
L902
6
1
R916
100R
R918
5
R920
6k8
L901
L923
L913
IC902
C916
100n
16V
L907
100n
50V
C908
L900
4
C906
16V
1000u
L920
3
SOT 223
C920
L905
16V
220u
S903
S904
STBY_3V3
1
PANEL_VCC_ON/OFF
D104"
D102"
R214"
R2069"
IC2013"
IC2012"
R2063"
R2067"
R2039"
C2066"
C2063"
R2038"
C2059"
C2058"
R2035"
C2057"
C2056"
C2081"
C2078"
S801"
C2055"
C2072"
IC2002"
C2074"
LF"
C2061"
PL205"
1"
PL203"
IC316"
R2030"
C270"
S636"
1"
R2014"
C2019"
PL1"
C2010"
C2011" C2012"
C2013" C2014"
C2015" C2016"
C2017"
IC317"
R325"
S213"
C327"
C2020"
C2026"
S2000"
C2028"
C2030"
C2031"
C2034"
C2037"
R1102"
D1001"
IC209"
C326"
R311"
R310"
R1103"
PL1003"
C1179"
R1112"
TU1001"
S1005"
C1189"
Q1013"
R1118"
R1120"
C1038"
R1044"
"
"
35 02
10 10 R1026"
R Q
C2201"
C1173"
C1040"
R1023"
C1168"
R1100"
X1001"
C1162"
IC201"
Z1001"
3"
E"
C1049"
R2201"
C1196"
PCB KENARI"
FD20"
L1031"
C1030"
C1159"
C1199"
C1181"
R1127"
TU1000"
C1205" C2200"
R1042"
R1043"
C1036"
C1048"
S110"
C423"
C921"
L908"
C1006"
PL103"
S643"
S109"
S445"
R1124"
S1009"
C1201"
PL1001"
PL604"
D911"
L1032"
C1191"
R1123"
Q1016"
S1010"
D1007"
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3
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HP_L
HP_L
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2
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3 1
2
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FPD TV DESIGN GROUP
VESTEL
Author
20/05/2005
L119
3 1
2
D109
100p
50V
LINE_OUT_L
600R_100MHZ_200mA
600R_100MHZ_200mA
L120
600R_100MHZ_200mA
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4
1
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5
8
7
3
6
9
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2
2
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HEADPHONE
1
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100p
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HP_R
4
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12
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2
11
LINE_OUT_R
A
LINE_OUT_L
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1
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JK100
4P
JK102
1P_RED_FAV
9
FRONT_AUDIO_L
FRONT_AUDIO_L
C104
8
FRONT_AUDIO_R
SVHS_Y
SVHS_C
C103
8
R108
R107
D104
FRONT_AUDIO_L
7
6
5
4
3
100p
50V
6
5
4
3
2
7
FRONT_VIDEO
R110
C102
L106
3 1
FRONT_AUDIO_R
SVHS_Y
2
C101
600R_100MHZ_200mA
600R_100MHZ_200mA
L107
D103
2
R100
BZT55C10
L104
2
R109
FRONT_AUDIO_R
1
3 1
SVHS_C
FRONT_VIDEO
BZT55C10
600R_100MHZ_200mA
600R_100MHZ_200mA
L105
100p
50V
1
1
FRONT_VIDEO
33p
50V
PL100
S101
S100
BZT55C10
L102
BZT55C10
600R_100MHZ_200mA
600R_100MHZ_200mA
D102
PL104
1
PL103
33p
50V
L103
D101
SVHS_C
L100
BZT55C10
3
600R_100MHZ_200mA
600R_100MHZ_200mA
C100
SVHS_Y
33p
50V
L101
D100
2
JK101
YELLOW_FAV
JK105
WHITE_FAV
JK106
WHITE_FAV
JK107
1P_RED_FAV
A
A
A
3 1
LINE_OUT_R
17FAV15-1
ILHAN TAYGURT
Sheet 01 of 01
IC708
5
R765
12k
15V_AUD
Q715
BC848B
50R_100MHZ_3A
40uH
PGNDL2
20
LOUTP1
ROUTP2 41
21
LOUTP2
ROUTP1 40
22
PVCCL3
23
PVCCL4
50V
10n
C775
R772
4k
9k1
R768
S738
25V
100n
C825
Q710
BC848B
S734
Sheet 1/1
Q709
BC848B
Q603
BSN20
S735
LM8093
IC703
R756
100k
Q604
BSN20
S736
100n
25V
MUTE_3V3
C824
22n
50V
C817
S737
R766
12k
22n
50V
RESET OUT
1
2
470n
63V
C806
C786
100n
25V
pinlere mumkun oldugunca yakin olacak
MUTE
C818
RASIT GOKALAN
VESTEL R&D
15V_AUD
15V supply voltage ait 100n decoupling capasiteler
D-CLASS AMPLIFIER
DATE
15V_AUD
37
C777
25V
220u
1u
16V
50V
100n
MUTE
S732
40uH
vialarla alt layerdaki ground a birlestirilecek ve stencil
bilgisinde lehim yeri olarak belirtilecek.
S733
R767
3k3
VESTEL ELECTRONICS
TV R&D GROUP
L724
50R_100MHZ_3A
C781
MODE_OUT
VCLAMPR
36
35
MODE
34
PVCCR1 38
L719
2
IC nin PCB ye temas ettigi yer ,isinin transferi icin
C776
AVCC
33
VAROUTR
32
AGND2
VAROUTL
31
30
C811
AVDD
29
PVCCR2 39
vcc 5v
26-05-2005
C814
PGNDR1 42
BSRP
PL703
1
PGNDR2 43
C778
COSC
28
50V 100n C779
PL707
1
2
25V
100u
50V 220p
AGND1
26
ROSC
120k
R742
1u
16V
C792
27
VCLAMPL
50V
10n
25
BSLP
L723
40uH
L718
470n
63V
19
TPA3004D2
IC702
C784
PGNDL1
100n
25V
25V
220u
18
C782
C813
LOUTN2
24
VER. E1
50V
100n
ROUTN1 44
17
L722
15V_AUD
18AMP05-1
15V_AUD
50R_100MHZ_3A
C805
ROUTN2 45
C785
PVCCR3 46
LOUTN1
50V
1n
2
RINN
PVCCL2
16
50V
1n
3
RINP
R773
3k3
4
V2P5
15
C780
5
LINP
SD_NOT 1
6
LINN
AVDDREF 7
8
VREF
VARDIFF 9
VARMAX10
PVCCR4 47
C783
100n
50V
C802
C796
50V
1n
100n
25V
C815
L726
C794
PL702
PVCCL1
50V
100n
220u
25V
100n
50V
C801
C803
C795
50V
1n
100n
25V
50R_100MHZ_3A
2
1
BSRN 48
BSLN
14
L721
C816
470n
63V
40uH
LOW=OFF
50V
10n
C793
13
15V_AUD
L725
470n
63V
22uN.C
C807
L729
4
C808
3
50V
10n
2
VOLUME 11
REFGND 12
100n
25V
C826
HIGH=ON
C820
1
25V
1000u
C821
35V
470u
22u
PL700
C823
S739
100n
25V
C787
4
BU TERMINALLERE GROUND MSP DEN GELECEK
C788
R771
1k
1u
15V_AUD
3
2
1u
C790
L727
MUTE_3V3
15V_AUD
S730
1u
opsiyonel
18k
R746
33k
R745
R754
1k8
kadar kisa olacak++
C822
25V
1000u
loop mumkun oldugu
1u
R755
22k
S723
C791
SS33
STPS745
D904
D901
22u
MAIN_OUT_R
FEED BACK CAPASITORDEN SONRA ALINACAK
L904
MAIN_OUT_L
S724
BU TERMINALLERE GROUND MSP DEN GELECEK
C789
R770
1k
22uH_3.9A_SMD
1u
L109
1
PL701
5 ON/OFF
4 FEEDBACK
3 GND
1 VIN
2 OUTPUT
LM2576
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