AT32UC3B0512

Features

High Performance, Low Power 32-Bit Atmel

®

AVR

®

Microcontroller

– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set

– Read-Modify-Write Instructions and Atomic Bit Manipulation

– Performing up to 1.39 DMIPS / MHz

• Up to 83 DMIPS Running at 60 MHz from Flash

• Up to 46 DMIPS Running at 30 MHz from Flash

– Memory Protection Unit

Multi-hierarchy Bus System

– High-Performance Data Transfers on Separate Buses for Increased Performance

– 7 Peripheral DMA Channels Improves Speed for Peripheral Communication

Internal High-Speed Flash

– 512K Bytes, 256K Bytes, 128K Bytes, 64K Bytes Versions

– Single Cycle Access up to 30 MHz

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 4ms Page Programming Time and 8ms Full-Chip Erase Time

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User Defined Configuration Area

Internal High-Speed SRAM, Single-Cycle Access at Full Speed

– 96K Bytes (512KB Flash), 32K Bytes (256KB and 128KB Flash), 16K Bytes (64KB

Flash)

Interrupt Controller

– Autovectored Low Latency Interrupt Service with Programmable Priority

System Functions

– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator

– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing

Independant CPU Frequency from USB Frequency

– Watchdog Timer, Real-Time Clock Timer

Universal Serial Bus (USB)

– Device 2.0 and Embedded Host Low Speed and Full Speed

– Flexible End-Point Configuration and Management with Dedicated DMA Channels

– On-chip Transceivers Including Pull-Ups

– USB Wake Up from Sleep Functionality

One Three-Channel 16-bit Timer/Counter (TC)

– Three External Clock Inputs, PWM, Capture and Various Counting Capabilities

One 7-Channel 20-bit Pulse Width Modulation Controller (PWM)

Three Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces

– Support for Hardware Handshaking, RS485 Interfaces and Modem Line

One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals

One Synchronous Serial Protocol Controller

– Supports I

2

S and Generic Frame-Based Protocols

One Master/Slave Two-Wire Interface (TWI), 400kbit/s I

2

C-compatible

One 8-channel 10-bit Analog-To-Digital Converter, 384ks/s

16-bit Stereo Audio Bitstream DAC

– Sample Rate Up to 50 KHz

QTouch

®

Library Support

– Capacitive Touch Buttons, Sliders, and Wheels

– QTouch and QMatrix Acquisition

32-bit ATMEL

AVR

Microcontroller

AT32UC3B0512

AT32UC3B0256

AT32UC3B0128

AT32UC3B064

AT32UC3B1512

AT32UC3B1256

AT32UC3B1128

AT32UC3B164

32059L–01/2012

On-Chip Debug System (JTAG interface)

– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace

64-pin TQFP/QFN (44 GPIO pins), 48-pin TQFP/QFN (28 GPIO pins)

5V Input Tolerant I/Os, including 4 high-drive pins

Single 3.3V Power Supply or Dual 1.8V-3.3V Power Supply

AT32UC3B

32059L–AVR32–01/2012

2

AT32UC3B

1. Description

The AT32UC3B is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 60 MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance.

The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems.

Higher computation capability is achieved using a rich set of DSP instructions.

The AT32UC3B incorporates on-chip Flash and SRAM memories for secure and fast access.

The Peripheral Direct Memory Access controller enables data transfers between peripherals and memories without processor involvement. PDCA drastically reduces processing overhead when transferring continuous and large data streams between modules within the MCU.

The Power Manager improves design flexibility and security: the on-chip Brown-Out Detector monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external oscillator sources, a Real-Time Clock and its associated timer keeps track of the time.

The Timer/Counter includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.

The PWM modules provides seven independent channels with many configuration options including polarity, edge alignment and waveform non overlap control. One PWM channel can trigger ADC conversions for more accurate close loop control implementations.

The AT32UC3B also features many communication interfaces for communication intensive applications. In addition to standard serial interfaces like USART, SPI or TWI, other interfaces like flexible Synchronous Serial Controller and USB are available. The USART supports different communication modes, like SPI mode.

The Synchronous Serial Controller provides easy access to serial communication protocols and audio standards like I

2

S, UART or SPI.

The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time thanks to the rich End-Point configuration. The Embedded Host interface allows device like a

USB Flash disk or a USB printer to be directly connected to the processor.

Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and included fully debounced reporting of touch keys and includes Adjacent Key

Suppression

®

(AKS

®

) technology for unambiguous detection of key events. The easy-to-use

QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications.

AT32UC3B integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. The

Nanotrace interface enables trace feature for JTAG-based debuggers.

3

32059L–AVR32–01/2012

AT32UC3B

2. Overview

2.1

Blockdiagram

Figure 2-1.

Block diagram

TCK

TDO

TDI

TMS

JTAG

INTERFACE

MCKO

MDO[5..0]

MSEO[1..0]

EVTI_N

EVTO_N

NEXUS

CLASS 2+

OCD

AVR32 UC

CPU

MEMORY PROTECTION UNIT

INSTR

INTERFACE

DATA

INTERFACE

LOCAL BUS

INTERFACE

16/32/96 KB

SRAM

FAST GPIO

PA

PB

XIN32

XOUT32

115 kHz

RCOSC

32 KHz

OSC

XIN0

XOUT0

XIN1

XOUT1

OSC0

OSC1

PLL0

PLL1

GCLK[3..0]

RESET_N

A[2..0]

B[2..0]

CLK[2..0]

M M M S

VBUS

D+

D-

ID

VBOF

USB

INTERFACE

DMA

S

M

HIGH SPEED

BUS MATRIX

S

S

S

M

PB HSB

HSB-PB

BRIDGE B

CONFIGURATION REGISTERS BUS

HSB

HSB-PB

BRIDGE A

PB

PERIPHERAL

DMA

CONTROLLER

EXTINT[7..0]

KPS[7..0]

NMI

INTERRUPT

CONTROLLER

EXTERNAL

INTERRUPT

CONTROLLER

REAL TIME

COUNTER

WATCHDOG

TIMER

POWER

MANAGER

CLOCK

GENERATOR

CLOCK

CONTROLLER

SLEEP

CONTROLLER

RESET

CONTROLLER

TIMER/COUNTER

64/128/

256/512 KB

FLASH

USART1

USART0

USART2

RXD

TXD

CLK

RTS, CTS

DSR, DTR, DCD, RI

RXD

TXD

CLK

RTS, CTS

SCK

MISO, MOSI

NPCS[3..0]

SERIAL

PERIPHERAL

INTERFACE

SYNCHRONOUS

SERIAL

CONTROLLER

TWO-WIRE

INTERFACE

TX_CLOCK, TX_FRAME_SYNC

TX_DATA

RX_CLOCK, RX_FRAME_SYNC

RX_DATA

SCL

SDA

ANALOG TO

DIGITAL

CONVERTER

AUDIO

BITSTREAM

DAC

AD[7..0]

ADVREF

DATA[1..0]

DATAN[1..0]

PULSE WIDTH

MODULATION

CONTROLLER

PWM[6..0]

PA

PB

4

32059L–AVR32–01/2012

AT32UC3B

3. Configuration Summary

The table below lists all AT32UC3B memory and package configurations:

Table 3-1.

Configuration Summary

Feature

Flash

SRAM

GPIO

External Interrupts

TWI

USART

Peripheral DMA Channels

SPI

Full Speed USB

SSC

Audio Bitstream DAC

Timer/Counter Channels

PWM Channels

Watchdog Timer

Real-Time Clock Timer

Power Manager

Oscillators

AT32UC3B0512

512 KB

96KB

AT32UC3B0256/128/64

256/128/64 KB

32/32/16KB

AT32UC3B1512

512 KB

96KB

44

8

1

3

7

1

Mini-Host + Device

1

1 0 1

1

1

3

7

1

PLL 80-240 MHz (PLL0/PLL1)

Crystal Oscillators 0.4-20 MHz (OSC0)

Crystal Oscillator 32 KHz (OSC32K)

RC Oscillator 115 kHz (RCSYS)

Crystal Oscillators 0.4-20 MHz (OSC1)

28

6

Device

0

AT32UC3B1256/128/64

256/128/64 KB

32/16/16KB

0

10-bit ADC number of channels

JTAG

Max Frequency

Package

8

TQFP64, QFN64

1

60 MHz

6

TQFP48, QFN48

5

32059L–AVR32–01/2012

AT32UC3B

4. Package and Pinout

4.1

Package

The device pins are multiplexed with peripheral functions as described in the Peripheral Multiplexing on I/O Line section.

Figure 4-1.

TQFP64 / QFN64 Pinout

GND

DP

DM

VBUS

VDDPLL

PB08

PB09

VDDCORE

PB10

PB11

PA24

PA25

PA26

PA27

RESET_N

VDDIO

53

54

55

56

49

50

51

52

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VDDIO

PA12

PA11

PA10

PA09

PB05

PB04

PB03

PB02

GND

VDDCORE

VDDIN

VDDOUT

VDDANA

ADVREF

GNDANA

6

32059L–AVR32–01/2012

AT32UC3B

Figure 4-2.

TQFP48 / QFN48 Pinout

GND

DP

DM

VBUS

VDDPLL

VDDCORE

PA24

PA25

PA26

PA27

RESET_N

VDDIO

43

44

45

46

37

38

39

40

41

42

47

48

20

19

18

17

16

15

14

13

24

23

22

21

VDDIO

PA12

PA11

PA10

PA09

GND

VDDCORE

VDDIN

VDDOUT

VDDANA

ADVREF

GNDANA

Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability.

4.2

Peripheral Multiplexing on I/O lines

4.2.1

Multiplexed signals

Each GPIO line can be assigned to one of 4 peripheral functions; A, B, C or D (D is only available for UC3Bx512 parts). The following table define how the I/O lines on the peripherals A, B,C or D are multiplexed by the GPIO.

Table 4-1.

GPIO Controller Function Multiplexing

48-pin

3

4

5

7

8

9

64-pin

3

4

5

9

10

11

PIN

PA00

PA01

PA02

PA03

PA04

PA05

GPIO Pin

GPIO 0

GPIO 1

GPIO 2

GPIO 3

GPIO 4

GPIO 5

Function A

ADC - AD[0]

ADC - AD[1]

EIC - EXTINT[0]

Function B

PM - GCLK[0]

PM - GCLK[1]

ADC - AD[2]

Function C

USBB - USB_ID

USBB - USB_VBOF

USART1 - DCD

Function D

(only for UC3Bx512)

ABDAC - DATA[0]

ABDAC - DATAN[0]

ABDAC - DATA[1]

7

32059L–AVR32–01/2012

AT32UC3B

Table 4-1.

10

11

23

25

26

27

12

20

21

22

28

29

30

31

32

33

34

35

43

44

45

46

45

24

25

26

27

6

7

15

16

38

43

61

62

41

42

46

47

59

60

54

13

31

33

34

35

14

28

29

30

36

37

39

40

44

GPIO Controller Function Multiplexing

12 PA06 GPIO 6 EIC - EXTINT[1]

PWM - PWM[0]

PWM - PWM[1]

TWI - SCL

TWI - SDA

USART0 - RTS

USART0 - CTS

EIC - NMI

SPI0 - MOSI

SPI0 - SCK

SPI0 - NPCS[0]

SPI0 - NPCS[1]

USART0 - RXD

USART0 - TXD

USART1 - CLK

PWM - PWM[2]

PWM - PWM[6]

USART1 - TXD

USART1 - RXD

SPI0 - MISO

USBB - USB_ID

USBB - USB_VBOF

USART0 - CLK

TC - CLK0

ADC - AD[6]

ADC - AD[7]

TC - A0

TC - B0

EIC - EXTINT[6]

EIC - EXTINT[7]

USART1 - CTS

USART1 - RTS

SSC - RX_CLOCK

SSC - RX_DATA

SSC -

RX_FRAME_SYNC

PA21

PA30

PA31

PB00

PB01

PB02

PB03

PB04

PB05

PB06

PB07

PA22

PA23

PA24

PA25

PA26

PA27

PA28

PA29

PB08

PA07

PA08

PA09

PA10

PA11

PA12

PA13

PA14

PA15

PA16

PA17

PA18

PA19

PA20

GPIO 21

GPIO 30

GPIO 31

GPIO 32

GPIO 33

GPIO 34

GPIO 35

GPIO 36

GPIO 37

GPIO 38

GPIO 39

GPIO 22

GPIO 23

GPIO 24

GPIO 25

GPIO 26

GPIO 27

GPIO 28

GPIO 29

GPIO 40

GPIO 7

GPIO 8

GPIO 9

GPIO 10

GPIO 11

GPIO 12

GPIO 13

GPIO 14

GPIO 15

GPIO 16

GPIO 17

GPIO 18

GPIO 19

GPIO 20

TC - A1

TC - B1

SPI0 - NPCS[1]

SPI0 - NPCS[0]

PWM - PWM[3]

USART2 - TXD

USART2 - RXD

PWM - PWM[4]

TC - CLK1

EIC - SCAN[0]

EIC - SCAN[1]

EIC - SCAN[2]

EIC - SCAN[3]

TC - A1

TC - B1

SPI0 - NPCS[3]

SPI0 - NPCS[2]

USART1 - DCD

USART1 - DSR

USART1 - DTR

ADC - AD[3]

ADC - AD[4]

ADC - AD[5]

SPI0 - NPCS[2]

SPI0 - NPCS[3]

TC - A2

TC - B2

PWM - PWM[2]

PWM - PWM[3]

PWM - PWM[4]

TC - CLK1

TC - CLK2

PWM - PWM[5]

PWM - PWM[6]

TC - CLK0

USART2 - TXD

ADC - TRIGGER

EIC - EXTINT[3]

EIC - EXTINT[4]

EIC - EXTINT[5]

TC - A0

TC - B0

SPI0 - MISO

SPI0 - MOSI

PM - GCLK[2]

PWM - PWM[6]

USART2 - CTS

USART2 - RTS

USART1 - TXD

USART1 - RXD

TC - CLK2

PWM - PWM[5]

EIC - SCAN[4]

EIC - SCAN[5]

EIC - SCAN[6]

USART1 - DSR

USART1 - DTR

USART1 - RI

USART1 - CTS

USART1 - RTS

PWM - PWM[0]

PWM - PWM[1]

USART0 - CLK

EIC - EXTINT[2]

USART2 - CLK

PWM - PWM[4]

SPI0 - SCK

SPI0 - MISO

SPI0 - MOSI

USART2 - RXD

ABDAC - DATAN[1]

SSC -

RX_FRAME_SYNC

SSC - RX_CLOCK

SSC - RX_DATA

USART1 - TXD

SSC - RX_CLOCK

PM - GCLK[2]

USART1 - RXD

SSC -

RX_FRAME_SYNC

SSC - TX_CLOCK

SSC - TX_DATA

SSC -

TX_FRAME_SYNC

ABDAC - DATA[0]

PWM - PWM[0]

PWM - PWM[1]

ABDAC - DATA[1]

ABDAC - DATAN[1]

ABDAC - DATAN[0]

ABDAC - DATA[0]

ABDAC - DATAN[0]

ABDAC - DATA[1]

8

32059L–AVR32–01/2012

AT32UC3B

Table 4-1.

4.2.2

GPIO Controller Function Multiplexing

55

57

58

PB09

PB10

PB11

GPIO 41

GPIO 42

GPIO 43

SSC - TX_CLOCK

SSC - TX_DATA

SSC -

TX_FRAME_SYNC

USART1 - RI

TC - A2

TC - B2

EIC - SCAN[7]

USART0 - RXD

USART0 - TXD

ABDAC - DATAN[1]

JTAG Port Connections

If the JTAG is enabled, the JTAG will take control over a number of pins, irrespective of the I/O

Controller configuration.

Table 4-2.

JTAG Pinout

64QFP/QFN 48QFP/QFN

4

5

2

3

4

5

2

3

Pin name

TCK

PA00

PA01

PA02

JTAG pin

TCK

TDI

TDO

TMS

4.2.3

4.2.4

Nexus OCD AUX port connections

If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespectively of the PIO configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Technical Reference Manual.

Table 4-3.

Pin

EVTI_N

MDO[5]

MDO[4]

MDO[3]

MDO[2]

MDO[1]

MDO[0]

EVTO_N

MCKO

MSEO[1]

MSEO[0]

Nexus OCD AUX port connections

AXS=0

PB05

PB04

PB03

PB02

PB01

PB00

PA31

PA15

PA30

PB06

PB07

AXS=1

PA14

PA08

PA07

PA06

PA05

PA04

PA03

PA15

PA13

PA09

PA10

Oscillator Pinout

The oscillators are not mapped to the normal A, B or C functions and their muxings are controlled by registers in the Power Manager (PM). Please refer to the power manager chapter for more information about this.

9

32059L–AVR32–01/2012

AT32UC3B

Table 4-4.

Oscillator pinout

QFP48 pin

30

22

31

23

QFP64 pin

39

41

30

40

42

31

Pad

PA18

PA28

PA11

PA19

PA29

PA12

Oscillator pin

XIN0

XIN1

XIN32

XOUT0

XOUT1

XOUT32

4.3

High Drive Current GPIO

Ones of GPIOs can be used to drive twice current than other GPIO capability (see Electrical

Characteristics section).

Table 4-5.

High Drive Current GPIO

GPIO Name

PA20

PA21

PA22

PA23

5. Signals Description

The following table gives details on the signal name classified by peripheral.

Table 5-1.

Signal Description List

Signal Name Function Type

Active

Level Comments

Power

VDDPLL

VDDCORE

VDDIO

VDDANA

VDDIN

PLL Power Supply

Core Power Supply

I/O Power Supply

Analog Power Supply

Voltage Regulator Input Supply

Power

Input

Power

Input

Power

Input

Power

Input

Power

Input

1.65V to 1.95 V

1.65V to 1.95 V

3.0V to 3.6V

3.0V to 3.6V

3.0V to 3.6V

10

32059L–AVR32–01/2012

AT32UC3B

Table 5-1.

Signal Description List (Continued)

Signal Name

VDDOUT

GNDANA

GND

Function

Voltage Regulator Output

Analog Ground

Ground

Crystal 0, 1, 32 Input

Type

Power

Output

Ground

Ground

Clocks, Oscillators, and PLL’s

Analog

Active

Level

XIN0, XIN1, XIN32

XOUT0, XOUT1,

XOUT32

Crystal 0, 1, 32 Output Analog

TCK

TDI

TDO

TMS

Test Clock

Test Data In

Test Data Out

Test Mode Select

JTAG

Input

Input

Output

Input

Auxiliary Port - AUX

Output

Output

MCKO

MDO0 - MDO5

MSEO0 - MSEO1

EVTI_N

EVTO_N

PA0 - PA31

PB0 - PB11

Trace Data Output Clock

Trace Data Output

Trace Frame Control

Event In

Event Out

Output

Output

Output

Power Manager - PM

GCLK0 - GCLK2

RESET_N

Generic Clock Pins

Reset Pin

Output

Input

EXTINT0 - EXTINT7 External Interrupt Pins

External Interrupt Controller - EIC

Input

KPS0 - KPS7

NMI

Keypad Scan Pins

Non-Maskable Interrupt Pin

General Purpose I/O pin- GPIOA, GPIOB

Parallel I/O Controller GPIOA I/O

Parallel I/O Controller GPIOB

Output

Input

I/O

Low

Low

Low

Low

Comments

1.65V to 1.95 V

11

32059L–AVR32–01/2012

AT32UC3B

Table 5-1.

Signal Name

MISO

MOSI

NPCS0 - NPCS3

SCK

Signal Description List (Continued)

Function Type

Serial Peripheral Interface - SPI0

I/O Master In Slave Out

Master Out Slave In

SPI Peripheral Chip Select

Clock

I/O

I/O

Output

Synchronous Serial Controller - SSC

Active

Level

Low

Comments

A0

A1

A2

B0

B1

B2

CLK0

CLK1

CLK2

RX_CLOCK

RX_DATA

RX_FRAME_SYNC

TX_CLOCK

TX_DATA

TX_FRAME_SYNC

SCL

SDA

CLK

CTS

SSC Receive Clock

SSC Receive Data

SSC Receive Frame Sync

SSC Transmit Clock

I/O

Input

I/O

I/O

SSC Transmit Data

SSC Transmit Frame Sync

Output

I/O

Timer/Counter - TIMER

I/O Channel 0 Line A

Channel 1 Line A

Channel 2 Line A

Channel 0 Line B

Channel 1 Line B

Channel 2 Line B

Channel 0 External Clock Input

Channel 1 External Clock Input

Channel 2 External Clock Input

Serial Clock

Two-wire Interface - TWI

I/O

I/O

Input

Input

Input

I/O

I/O

I/O

I/O

Serial Data I/O

Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2

Clock

Clear To Send

I/O

Input

12

32059L–AVR32–01/2012

Table 5-1.

Signal Name

DCD

DSR

DTR

RI

RTS

RXD

TXD

AD0 - AD7

ADVREF

DATA0 - DATA1

DATAN0 - DATAN1

PWM0 - PWM6

DDM

DDP

VBUS

USBID

USB_VBOF

Signal Description List (Continued)

Function

Data Carrier Detect

Data Set Ready

Data Terminal Ready

Ring Indicator

Request To Send

Receive Data

Transmit Data

Analog input pins

Type

Output

Input

Output

Analog to Digital Converter - ADC

Analog positive reference voltage input

Analog input

Analog input

D/A Data out

D/A Data inverted out

Audio Bitstream DAC - ABDAC

Output

Output

Pulse Width Modulator - PWM

PWM Output Pins

USB Device Port Data -

USB Device Port Data +

Output

Universal Serial Bus Device - USBB

USB VBUS Monitor and Embedded Host

Negociation

Analog

Analog

Analog

Input

ID Pin of the USB Bus

USB VBUS On/off: bus power control port

Input output

Active

Level Comments

Only USART1

Only USART1

Only USART1

Only USART1

2.6 to 3.6V

AT32UC3B

5.1

JTAG pins

TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has no pull-up resistor. These 3 pins can be used as GPIO-pins. At reset state, these pins are in

GPIO mode.

TCK pin cannot be used as GPIO pin. JTAG interface is enabled when TCK pin is tied low.

13

32059L–AVR32–01/2012

AT32UC3B

5.2

RESET_N pin

The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product.

5.3

TWI pins

When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering. When used as GPIO-pins or used for other peripherals, the pins have the same characteristics as GPIO pins.

5.4

GPIO pins

All the I/O lines integrate a pull-up resistor

. Programming of this pull-up resistor is performed independently for each I/O line through the GPIO Controllers. After reset, I/O lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column “Reset

Value” of the GPIO Controller user interface table.

5.5

High drive pins

The four pins PA20, PA21, PA22, PA23 have high drive output capabilities.

5.6

Power Considerations

5.6.1

Power Supplies

The AT32UC3B has several types of power supply pins:

VDDIO: Powers I/O lines. Voltage is 3.3V nominal.

VDDANA: Powers the ADC Voltage is 3.3V nominal.

VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal.

VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal.

VDDPLL: Powers the PLL. Voltage is 1.8V nominal.

The ground pins GND are common to VDDCORE, VDDIO and VDDPLL. The ground pin for

VDDANA is GNDANA.

Refer to Electrical Characteristics section for power consumption on the various supply pins.

The main requirement for power supplies connection is to respect a star topology for all electrical connection.

14

32059L–AVR32–01/2012

AT32UC3B

Figure 5-1.

Power Supply

3.3V

Single Power Supply

VDDANA

VDDIO

ADVREF

VDDIN

VDDOUT

1.8V

Regulator

VDDCORE

3.3V

Dual Power Supply

VDDANA

VDDIO

1.8

V

ADVREF

VDDIN

VDDOUT

VDDCORE

1.8V

Regulator

VDDPLL

VDDPLL

5.6.2

5.6.2.1

Voltage Regulator

Single Power Supply

The AT32UC3B embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDOUT that should be externally connected to the 1.8V domains.

Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. Two input decoupling capacitors must be placed close to the chip.

Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel between VDDOUT and

GND as close to the chip as possible

Figure 5-2.

Supply Decoupling

3.3V

C

IN2

1.8V

C

OUT2

VDDIN

C

IN1

C

OUT1

VDDOUT

1.8V

Regulator

15

32059L–AVR32–01/2012

AT32UC3B

Refer to

Section 28.3 on page 610

for decoupling capacitors values and regulator characteristics.

For decoupling recommendations for VDDIO, VDDANA, VDDCORE and VDDPLL, please refer to the Schematic checklist.

5.6.2.2

5.6.3

Dual Power Supply

In case of dual power supply, VDDIN and VDDOUT should be connected to ground to prevent from leakage current.

To avoid over consumption during the power up sequence, VDDIO and VDDCORE voltage dif-

ference needs to stay in the range given Figure 5-3 .

Figure 5-3.

VDDIO versus VDDCORE during power up sequence

4

Extra consumption on VDDIO

3.5

3

2.5

2

1.5

1

0.5

0

0 0.2

0.4

0.6

Extra consumption on VDDCORE

0.8

1

VDDCORE (V)

1.2

1.4

1.6

1.8

2

Analog-to-Digital Converter (ADC) reference.

The ADC reference (ADVREF) must be provided from an external source. Two decoupling capacitors must be used to insure proper decoupling.

Figure 5-4.

ADVREF Decoupling

3.3V

C

VREF2

C

VREF1

ADVREF

Refer to

Section 28.4 on page 610 for decoupling capacitors values and electrical

characteristics.

In case ADC is not used, the ADVREF pin should be connected to GND to avoid extra consumption.

16

32059L–AVR32–01/2012

AT32UC3B

6. Processor and Architecture

Rev: 1.0.0.0

This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the

AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical

Reference Manual.

6.1

Features

32-bit load/store AVR32A RISC architecture

– 15 general-purpose 32-bit registers

– 32-bit Stack Pointer, Program Counter and Link Register reside in register file

– Fully orthogonal instruction set

– Privileged and unprivileged modes enabling efficient and secure Operating Systems

– Innovative instruction set together with variable instruction length ensuring industry leading code density

– DSP extention with saturating arithmetic, and a wide variety of multiply instructions

3-stage pipeline allows one instruction per clock cycle for most instructions

– Byte, halfword, word and double word memory access

– Multiple interrupt priority levels

MPU allows for operating systems with memory protection

6.2

AVR32 Architecture

AVR32 is a high-performance 32-bit RISC microprocessor architecture, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications.

Through a quantitative approach, a large set of industry recognized benchmarks has been compiled and analyzed to achieve the best code density in its class. In addition to lowering the memory requirements, a compact code size also contributes to the core’s low power characteristics. The processor supports byte and halfword data types without penalty in code size and performance.

Memory load and store operations are provided for byte, halfword, word, and double word data with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely linked to the architecture and is able to exploit code optimization features, both for size and speed.

In order to reduce code size to a minimum, some instructions have multiple addressing modes.

As an example, instructions with immediates often have a compact format with a smaller immediate, and an extended format with a larger immediate. In this way, the compiler is able to use the format giving the smallest code size.

Another feature of the instruction set is that frequently used instructions, like add, have a compact format with two operands as well as an extended format with three operands. The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution.

17

32059L–AVR32–01/2012

AT32UC3B

The register file is organized as sixteen 32-bit registers and includes the Program Counter, the

Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions.

6.3

The AVR32UC CPU

The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced OCD system, no caches, and a Memory Protection Unit (MPU). Java acceleration hardware is not implemented.

AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch, one High Speed Bus master for data access, and one High Speed Bus slave interface allowing other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the

CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing.

Also, power consumption is reduced by not needing a full High Speed Bus access for memory accesses. A dedicated data RAM interface is provided for communicating with the internal data

RAMs.

A local bus interface is provided for connecting the CPU to device-specific high-speed systems, such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the

LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the

CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory range allocated to it, and data transfers are performed using regular load and store instructions.

Details on which devices that are mapped into the local bus space is given in the Memories chapter of this data sheet.

Figure 6-1 on page 19

displays the contents of AVR32UC.

18

32059L–AVR32–01/2012

Figure 6-1.

Overview of the AVR32UC CPU

OCD system

Power/

Reset control

Instruction memory controller

High Speed Bus master

AVR32UC CPU pipeline

MPU

Data memory controller

High

Speed

Bus master

High

Speed

Bus slave

CPU Local

Bus master

AT32UC3B

6.3.1

Pipeline Overview

AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruction Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic

(ALU) section, one multiply (MUL) section, and one load/store (LS) section.

Instructions are issued and complete in order. Certain operations require several clock cycles to complete, and in this case, the instruction resides in the ID and EX stages for the required number of clock cycles. Since there is only three pipeline stages, no internal data forwarding is required, and no data dependencies can arise in the pipeline.

Figure 6-2 on page 20

shows an overview of the AVR32UC pipeline stages.

19

32059L–AVR32–01/2012

AT32UC3B

Figure 6-2.

The AVR32UC Pipeline

IF ID

Pref etch unit Decode unit

Regfile

Read

MUL

A LU

LS

Multiply unit

Regfile w rite

A LU unit

Load-store unit

6.3.2

6.3.3

6.3.4

6.3.5

AVR32A Microarchitecture Compliance

AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts. Additionally, it does not provide hardware registers for the return address registers and return status registers. Instead, all this information is stored on the system stack. This saves chip area at the expense of slower interrupt handling.

Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These registers are pushed regardless of the priority level of the pending interrupt. The return address and status register are also automatically pushed to stack. The interrupt handler can therefore use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are restored, and execution continues at the return address stored popped from stack.

The stack is also used to store the status register and return address for exceptions and scall.

Executing the rete or rets instruction at the completion of an exception or system call will pop this status register and continue execution at the popped return address.

Java Support

AVR32UC does not provide Java hardware acceleration.

Memory Protection

The MPU allows the user to check all memory accesses for privilege violations. If an access is attempted to an illegal memory address, the access is aborted and an exception is taken. The

MPU in AVR32UC is specified in the AVR32UC Technical Reference manual.

Unaligned Reference Handling

AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses.

20

32059L–AVR32–01/2012

AT32UC3B

6.3.6

6.3.7

The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses.

Table 6-1.

Instruction

ld.d

st.d

Instructions with Unaligned Reference Support

Supported alignment

Word

Word

Unimplemented Instructions

The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented

Instruction Exception if executed:

• All SIMD instructions

• All coprocessor instructions if no coprocessors are present

• retj, incjosp, popjc, pushjc

• tlbr, tlbs, tlbw

• cache

CPU and Architecture Revision

Three major revisions of the AVR32UC CPU currently exist.

The Architecture Revision field in the CONFIG0 system register identifies which architecture revision is implemented in a specific device.

AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled for revision 1 or 2 is binary-compatible with revision 3 CPUs.

21

32059L–AVR32–01/2012

AT32UC3B

6.4

Programming Model

6.4.1

Register File Configuration

The AVR32UC register file is shown below.

Figure 6-3.

The AVR32UC Register File

Application

Supervisor INT0 INT1 INT2

Bit 31 Bit 0

PC

LR

SP_APP

R12

R11

R10

R9

R8

Bit 31 Bit 0

PC

LR

SP_SYS

R12

R11

R10

R9

R8

Bit 31 Bit 0

PC

LR

SP_SYS

R12

R11

R10

R9

R8

Bit 31 Bit 0

PC

LR

SP_SYS

R12

R11

R10

R9

R8

Bit 31 Bit 0

PC

LR

SP_SYS

R12

R11

R10

R9

R8

INT3

Bit 31 Bit 0

PC

LR

SP_SYS

R12

R11

R10

R9

R8

Exception

Bit 31 Bit 0

PC

LR

SP_SYS

R12

R11

R10

R9

R8

NMI

Bit 31 Bit 0

PC

LR

SP_SYS

R12

R11

R10

R9

R8

Secure

Bit 31 Bit 0

PC

LR

SP_SEC

R12

R11

R10

R9

R8

6.4.2

R3

R2

R1

R0

SR

R3

R2

R1

R0

SR

R3

R2

R1

R0

SR

R3

R2

R1

R0

SR

R3

R2

R1

R0

SR

SS_STATUS

SS_ADRF

SS_ADRR

SS_ADR0

SS_ADR1

SS_SP_SYS

SS_SP_APP

SS_RAR

SS_RSR

R3

R2

R1

R0

SR

R3

R2

R1

R0

SR

R3

R2

R1

R0

SR

R3

R2

R1

R0

SR

Status Register Configuration

The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 6-4 on page 22

and

Figure 6-5 on page 23 . The lower word contains the C, Z, N, V, and Q condition

code flags and the R, T, and L bits, while the upper halfword contains information about the mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details.

Figure 6-4.

The Status Register High Halfword

Bit 31

DM D M2 M1 M0 EM I3M

0

1

0 0 0 0 0 0 0 0 1 1 0 0

I1M

Bit 16

I0M GM

Bit name

0 0 1

Initial value

Global Interrupt Mask

Interrupt Level 0 Mask

Interrupt Level 1 Mask

Interrupt Level 2 Mask

Interrupt Level 3 Mask

Exception Mask

Mode Bit 0

Mode Bit 1

Mode Bit 2

Reserved

Debug State

Debug State Mask

Reserved

22

32059L–AVR32–01/2012

AT32UC3B

Figure 6-5.

The Status Register Low Halfword

Bit 15

T -

Bit 0

L Q V N Z C

Bit name

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Initial value

Carry

Zero

Sign

Overflow

Saturation

Lock

Reserved

Scratch

Reserved

6.4.3

6.4.3.1

Processor States

Normal RISC State

The AVR32 processor supports several different execution contexts as shown in

Table 6-2 on page 23 .

Table 6-2.

Overview of Execution Modes, their Priorities and Privilege Levels.

Priority Mode

1 Non Maskable Interrupt

Security Description

Privileged Non Maskable high priority interrupt mode

4

5

2

3

6

N/A

N/A

Exception

Interrupt 3

Interrupt 2

Interrupt 1

Interrupt 0

Supervisor

Application

Privileged

Privileged

Privileged

Privileged

Privileged

Privileged

Unprivileged

Execute exceptions

General purpose interrupt mode

General purpose interrupt mode

General purpose interrupt mode

General purpose interrupt mode

Runs supervisor calls

Normal program execution mode

6.4.3.2

Mode changes can be made under software control, or can be caused by external interrupts or exception processing. A mode can be interrupted by a higher priority mode, but never by one with lower priority. Nested exceptions can be supported with a minimal software overhead.

When running an operating system on the AVR32, user processes will typically execute in the application mode. The programs executed in this mode are restricted from executing certain instructions. Furthermore, most system registers together with the upper halfword of the status register cannot be accessed. Protected memory areas are also not available. All other operating modes are privileged and are collectively called System Modes. They have full access to all privileged and unprivileged resources. After a reset, the processor will be in supervisor mode.

Debug State

The AVR32 can be set in a debug state, which allows implementation of software monitor routines that can read out and alter system information for use during application development. This implies that all system and application registers, including the status registers and program counters, are accessible in debug state. The privileged instructions are also available.

23

32059L–AVR32–01/2012

AT32UC3B

6.4.4

All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register.

Debug state can be entered as described in the AVR32UC Technical Reference Manual.

Debug state is exited by the retd instruction.

System Registers

The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. The table below lists the system registers specified in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is responsible for maintaining correct sequencing of any instructions following a mtsr instruction.

For detail on the system registers, refer to the AVR32UC Technical Reference Manual.

Table 6-3.

19

20

21

22

15

16

17

18

23

24

25

11

12

13

14

7

8

9

10

5

6

3

4

1

2

Reg #

0

System Registers

76

80

84

88

60

64

68

72

92

96

100

44

48

52

56

28

32

36

40

12

16

20

24

4

8

Address

0

RAR_INT1

RAR_INT2

RAR_INT3

RAR_EX

RAR_NMI

RAR_DBG

JECR

JOSP

JAVA_LV0

JAVA_LV1

JAVA_LV2

Name

SR

EVBA

ACBA

CPUCR

ECR

RSR_SUP

RSR_INT0

RSR_INT1

RSR_INT2

RSR_INT3

RSR_EX

RSR_NMI

RSR_DBG

RAR_SUP

RAR_INT0

Function

Status Register

Exception Vector Base Address

Application Call Base Address

CPU Control Register

Exception Cause Register

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Return Status Register for Debug mode

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Return Address Register for Debug mode

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

24

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

Table 6-3.

81

82

83

84

77

78

79

80

73

74

75

76

69

70

71

72

89

90

91

85

86

87

88

65

66

67

68

31

32

33-63

64

Reg #

26

27

28

29

30

System Registers (Continued)

324

328

332

336

308

312

316

320

292

296

300

304

276

280

284

288

340

344

348

352

356

360

364

Address

104

108

112

116

120

260

264

268

272

124

128

132-252

256

PCNT1

PCCR

BEAR

MPUAR0

MPUAR1

MPUAR2

MPUAR3

MPUAR4

TLBELO

PTBR

TLBEAR

MMUCR

TLBARLO

TLBARHI

PCCNT

PCNT0

Name

JAVA_LV3

JAVA_LV4

JAVA_LV5

JAVA_LV6

JAVA_LV7

JTBA

JBCR

Reserved

CONFIG0

CONFIG1

COUNT

COMPARE

TLBEHI

MPUAR5

MPUAR6

MPUAR7

MPUPSR0

MPUPSR1

MPUPSR2

MPUPSR3

Function

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Reserved for future use

Configuration register 0

Configuration register 1

Cycle Counter register

Compare register

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Unused in AVR32UC

Bus Error Address Register

MPU Address Register region 0

MPU Address Register region 1

MPU Address Register region 2

MPU Address Register region 3

MPU Address Register region 4

MPU Address Register region 5

MPU Address Register region 6

MPU Address Register region 7

MPU Privilege Select Register region 0

MPU Privilege Select Register region 1

MPU Privilege Select Register region 2

MPU Privilege Select Register region 3

25

AT32UC3B

Table 6-3.

Reg #

92

93

94

95

96

97

98

99

100

101

102

103-191

192-255

System Registers (Continued)

Address

368

372

376

380

384

388

392

396

400

404

408

448-764

768-1020

Name

MPUPSR4

MPUPSR5

MPUPSR6

MPUPSR7

MPUCRA

MPUCRB

MPUBRA

MPUBRB

MPUAPRA

MPUAPRB

MPUCR

Reserved

IMPL

Function

MPU Privilege Select Register region 4

MPU Privilege Select Register region 5

MPU Privilege Select Register region 6

MPU Privilege Select Register region 7

Unused in this version of AVR32UC

Unused in this version of AVR32UC

Unused in this version of AVR32UC

Unused in this version of AVR32UC

MPU Access Permission Register A

MPU Access Permission Register B

MPU Control Register

Reserved for future use

IMPLEMENTATION DEFINED

6.5

Exceptions and Interrupts

AVR32UC incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a welldefined behavior when multiple exceptions are received simultaneously. Additionally, pending exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower priority class.

When an event occurs, the execution of the instruction stream is halted, and execution control is passed to an event handler at an address specified in

Table 6-4 on page 29

. Most of the handlers are placed sequentially in the code space starting at the address specified by EVBA, with four bytes between each handler. This gives ample space for a jump instruction to be placed there, jumping to the event routine itself. A few critical handlers have larger spacing between them, allowing the entire event routine to be placed directly at the address specified by the

EVBA-relative offset generated by hardware. All external interrupt sources have autovectored interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as

(EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including external interrupt requests, yielding a uniform event handling scheme.

An interrupt controller does the priority handling of the external interrupts and provides the autovector offset to the CPU.

6.5.1

System Stack Issues

Event handling in AVR32UC uses the system stack pointed to by the system stack pointer,

SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section, since the timing of accesses to this memory section is both fast and deterministic.

26

32059L–AVR32–01/2012

AT32UC3B

6.5.2

6.5.3

6.5.4

The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter an UNDEFINED state.

Exceptions and Interrupt Requests

When an event other than scall or debug request is received by the core, the following actions are performed atomically:

1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and GM bits in the Status Register are used to mask different events. Not all events can be masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and

Bus Error) can not be masked. When an event is accepted, hardware automatically sets the mask bits corresponding to all sources with equal or lower priority. This inhibits acceptance of other events of the same or lower priority, except for the critical events listed above. Software may choose to clear some or all of these bits after saving the necessary state if other priority schemes are desired. It is the event source’s responsability to ensure that their events are left pending until accepted by the CPU.

2. When a request is accepted, the Status Register and Program Counter of the current context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also automatically stored to stack. Storing the Status

Register ensures that the core is returned to the previous execution mode when the current event handling is completed. When exceptions occur, both the EM and GM bits are set, and the application may manually enable nested exceptions if desired by clearing the appropriate bit. Each exception handler has a dedicated handler address, and this address uniquely identifies the exception source.

3. The Mode bits are set to reflect the priority of the accepted event, and the correct regis-

ter file bank is selected. The address of the event handler, as shown in Table 6-4, is

loaded into the Program Counter.

The execution of the event handler routine then continues from the effective address calculated.

The rete instruction signals the end of the event. When encountered, the Return Status Register and Return Address Register are popped from the system stack and restored to the Status Register and Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also popped from the system stack. The restored Status Register contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling.

Supervisor Calls

The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers.

The scall instruction behaves differently depending on which mode it is called from. The behaviour is detailed in the instruction set reference. In order to allow the scall routine to return to the correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC

CPU, scall and rets uses the system stack to store the return address and the status register.

Debug Requests

The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the

27

32059L–AVR32–01/2012

AT32UC3B

6.5.5

status register. Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the

Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated registers remove the need for storing this data to the system stack, thereby improving debuggability. The mode bits in the status register can freely be manipulated in Debug mode, to observe registers in all contexts, while retaining full privileges.

Debug mode is exited by executing the retd instruction. This returns to the previous context.

Entry Points for Events

Several different event handler entry points exists. In AVR32UC, the reset address is

0x8000_0000. This places the reset address in the boot flash memory area.

TLB miss exceptions and scall have a dedicated space relative to EVBA where their event handler can be placed. This speeds up execution by removing the need for a jump instruction placed at the program address jumped to by the event hardware. All other exceptions have a dedicated event routine entry point located relative to EVBA. The handler routine address identifies the exception source directly.

AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation.

ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of the entries in the MPU. TLB multiple hit exception indicates that an access address did map to multiple TLB entries, signalling an error.

All external interrupt requests have entry points located at an offset relative to EVBA. This autovector offset is specified by an external Interrupt Controller. The programmer must make sure that none of the autovector offsets interfere with the placement of other code. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes.

Special considerations should be made when loading EVBA with a pointer. Due to security considerations, the event handlers should be located in non-writeable flash memory, or optionally in a privileged memory protection region if an MPU is present.

If several events occur on the same instruction, they are handled in a prioritized way. The priority

ordering is presented in Table 6-4. If events occur on several instructions at different locations in

the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A.

The addresses and priority of simultaneous events are shown in Table 6-4. Some of the excep-

tions are unused in AVR32UC since it has no MMU, coprocessor interface, or floating-point unit.

28

32059L–AVR32–01/2012

AT32UC3B

Table 6-4.

Priority and Handler Addresses for Events

20

21

22

23

16

17

18

19

24

25

26

27

28

12

13

14

15

8

9

10

11

6

7

4

5

2

3

Priority Handler Address

1 0x8000_0000

Provided by OCD system

EVBA+0x00

EVBA+0x04

EVBA+0x08

EVBA+0x0C

EVBA+0x10

Autovectored

Autovectored

Autovectored

Autovectored

EVBA+0x14

EVBA+0x50

EVBA+0x18

EVBA+0x1C

EVBA+0x20

EVBA+0x24

EVBA+0x28

EVBA+0x2C

EVBA+0x30

EVBA+0x100

EVBA+0x34

EVBA+0x38

EVBA+0x60

EVBA+0x70

EVBA+0x3C

EVBA+0x40

EVBA+0x44

Name

Reset

OCD Stop CPU

Unrecoverable exception

TLB multiple hit

Bus error data fetch

Bus error instruction fetch

NMI

Interrupt 3 request

Interrupt 2 request

Interrupt 1 request

Interrupt 0 request

Instruction Address

ITLB Miss

ITLB Protection

Breakpoint

Illegal Opcode

Unimplemented instruction

Privilege violation

Floating-point

Coprocessor absent

Supervisor call

Data Address (Read)

Data Address (Write)

DTLB Miss (Read)

DTLB Miss (Write)

DTLB Protection (Read)

DTLB Protection (Write)

DTLB Modified

Instruction

Instruction

Instruction

UNUSED

Instruction

Instruction

CPU

CPU

MPU

MPU

MPU

MPU

UNUSED

Event source

External input

OCD system

Internal

MPU

Data bus

Data bus

External input

External input

External input

External input

External input

CPU

MPU

MPU

OCD system

Stored Return Address

Undefined

First non-completed instruction

PC of offending instruction

First non-completed instruction

First non-completed instruction

First non-completed instruction

First non-completed instruction

First non-completed instruction

First non-completed instruction

First non-completed instruction

PC of offending instruction

PC of offending instruction

First non-completed instruction

PC of offending instruction

PC of offending instruction

PC of offending instruction

PC of offending instruction

PC(Supervisor Call) +2

PC of offending instruction

PC of offending instruction

PC of offending instruction

PC of offending instruction

29

32059L–AVR32–01/2012

AT32UC3B

6.6

Module Configuration

All AT32UC3B parts do not implement the same CPU and Architecture Revision.

Table 6-5.

CPU and Architecture Revision

Part Name

AT32UC3Bx512

AT32UC3Bx256

AT32UC3Bx128

AT32UC3Bx64

Architecture Revision

2

1

1

1

32059L–AVR32–01/2012

30

AT32UC3B

7. Memories

7.1

Embedded Memories

Internal High-Speed Flash

– 512KBytes (AT32UC3B0512, AT32UC3B1512)

– 256 KBytes (AT32UC3B0256, AT32UC3B1256)

– 128 KBytes (AT32UC3B0128, AT32UC3B1128)

– 64 KBytes (AT32UC3B064, AT32UC3B164)

• - 0 Wait State Access at up to 30 MHz in Worst Case Conditions

• - 1 Wait State Access at up to 60 MHz in Worst Case Conditions

• - Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding penalty of 1 wait state access

• - 100 000 Write Cycles, 15-year Data Retention Capability

• - 4 ms Page Programming Time, 8 ms Chip Erase Time

• - Sector Lock Capabilities, Bootloader Protection, Security Bit

• - 32 Fuses, Erased During Chip Erase

• - User Page For Data To Be Preserved During Chip Erase

Internal High-Speed SRAM, Single-cycle access at full speed

– 96KBytes ((AT32UC3B0512, AT32UC3B1512)

– 32KBytes (AT32UC3B0256, AT32UC3B0128, AT32UC3B1256 and AT32UC3B1128)

– 16KBytes (AT32UC3B064 and AT32UC3B164)

7.2

Physical Memory Map

The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32UC Technical Architecture Manual. The 32-bit physical address space is mapped as follows:

Table 7-1.

AT32UC3B Physical Memory Map

Device

Start Address

Size

AT32UC3B0512

AT32UC3B1512

AT32UC3B0256

AT32UC3B1256

AT32UC3B0128

AT32UC3B1128

AT32UC3B064

AT32UC3B164

Embedded

SRAM

0x0000_0000

96 Kbytes

32 Kbytes

32 Kbytes

16 Kbytes

Embedded

Flash

USB Data

0x8000_0000 0xD000_0000

512 Kbytes 64 Kbytes

256 Kbytes

128 Kbytes

64 Kbytes

64 Kbytes

64 Kbytes

64 Kbytes

HSB-PB

Bridge A

0xFFFF_0000

64 Kbytes

64 Kbytes

64 Kbytes

64 Kbytes

HSB-PB

Bridge B

0xFFFE_0000

64 Kbytes

64 Kbytes

64 Kbytes

64 Kbytes

31

32059L–AVR32–01/2012

7.3

Peripheral Address Map

Table 7-2.

Peripheral Address Mapping

Address

0xFFFE0000

USB

0xFFFE1000

HMATRIX

0xFFFE1400

HFLASHC

0xFFFF0000

PDCA

0xFFFF0800

INTC

0xFFFF0C00

PM

0xFFFF0D00

RTC

0xFFFF0D30

WDT

0xFFFF0D80

EIM

0xFFFF1000

GPIO

0xFFFF1400

USART0

0xFFFF1800

USART1

0xFFFF1C00

USART2

0xFFFF2400

SPI0

0xFFFF2C00

TWI

0xFFFF3000

PWM

0xFFFF3400

SSC

0xFFFF3800

TC

Peripheral Name

USB 2.0 Interface - USB

HSB Matrix - HMATRIX

Flash Controller - HFLASHC

Peripheral DMA Controller - PDCA

Interrupt controller - INTC

Power Manager - PM

Real Time Counter - RTC

Watchdog Timer - WDT

External Interrupt Controller - EIM

General Purpose Input/Output Controller - GPIO

Universal Synchronous/Asynchronous

Receiver/Transmitter - USART0

Universal Synchronous/Asynchronous

Receiver/Transmitter - USART1

Universal Synchronous/Asynchronous

Receiver/Transmitter - USART2

Serial Peripheral Interface - SPI0

Two-wire Interface - TWI

Pulse Width Modulation Controller - PWM

Synchronous Serial Controller - SSC

Timer/Counter - TC

AT32UC3B

32

32059L–AVR32–01/2012

AT32UC3B

Table 7-2.

Peripheral Address Mapping

0xFFFF3C00

ADC

0xFFFF4000

ABDAC

Analog to Digital Converter - ADC

Audio Bitstream DAC - ABDAC

7.4

CPU Local Bus Mapping

Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus.

Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at

CPU speed, one write or read operation can be performed per clock cycle to the local busmapped GPIO registers.

The following GPIO registers are mapped on the local bus:

Table 7-3.

Local bus mapped GPIO registers

Port

0

1

Register

Output Driver Enable Register (ODER)

Output Value Register (OVR)

Pin Value Register (PVR)

Output Driver Enable Register (ODER)

Output Value Register (OVR)

Pin Value Register (PVR)

TOGGLE

-

WRITE

SET

CLEAR

TOGGLE

WRITE

SET

Mode

WRITE

SET

CLEAR

TOGGLE

WRITE

SET

CLEAR

CLEAR

TOGGLE

-

Local Bus

Address

0x4000_0040

0x4000_0044

0x4000_0048

0x4000_004C

0x4000_0050

0x4000_0054

0x4000_0058

0x4000_005C

0x4000_0060

0x4000_0140

0x4000_0144

0x4000_0148

0x4000_014C

0x4000_0150

0x4000_0154

0x4000_0158

0x4000_015C

0x4000_0160

Access

Write-only

Write-only

Write-only

Write-only

Write-only

Write-only

Write-only

Write-only

Read-only

Write-only

Write-only

Write-only

Write-only

Write-only

Write-only

Write-only

Write-only

Read-only

33

32059L–AVR32–01/2012

AT32UC3B

8. Boot Sequence

This chapter summarizes the boot sequence of the AT32UC3B. The behaviour after power-up is controlled by the Power Manager. For specific details, refer to section Power Manager (PM).

8.1

Starting of clocks

After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the internal RC Oscillator as clock source.

On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have a divided frequency, all parts of the system recieves a clock with the same frequency as the internal RC Oscillator.

8.2

Fetching of initial instructions

After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset address, which is 0x8000_0000. This address points to the first address in the internal Flash.

The code read from the internal Flash is free to configure the system to use for example the

PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals.

When powering up the device, there may be a delay before the voltage has stabilized, depending on the rise time of the supply used. The CPU can start executing code as soon as the supply is above the POR threshold, and before the supply is stable. Before switching to a high-speed clock source, the user should use the BOD to make sure the VDDCORE is above the minimum level.

34

32059L–AVR32–01/2012

AT32UC3B

9. Power Manager (PM)

Rev: 2.3.0.2

9.1

Features

Controls integrated oscillators and PLLs

Generates clocks and resets for digital logic

Supports 2 crystal oscillators 0.4-20 MHz

Supports 2 PLLs 80-240 MHz

Supports 32 KHz ultra-low power oscillator

Integrated low-power RC oscillator

On-the fly frequency change of CPU, HSB, PBA, and PBB clocks

Sleep modes allow simple disabling of logic clocks, PLLs, and oscillators

Module-level clock gating through maskable peripheral clocks

Wake-up from internal or external interrupts

Generic clocks with wide frequency range provided

Automatic identification of reset sources

Controls brownout detector (BOD), RC oscillator, and bandgap voltage reference through control and calibration registers

9.2

Description

The Power Manager (PM) controls the oscillators and PLLs, and generates the clocks and resets in the device. The PM controls two fast crystal oscillators, as well as two PLLs, which can multiply the clock from either oscillator to provide higher frequencies. Additionally, a low-power

32 KHz oscillator is used to generate the real-time counter clock for high accuracy real-time measurements. The PM also contains a low-power RC oscillator with fast start-up time, which can be used to clock the digital logic.

The provided clocks are divided into synchronous and generic clocks. The synchronous clocks are used to clock the main digital logic in the device, namely the CPU, and the modules and peripherals connected to the HSB, PBA, and PBB buses. The generic clocks are asynchronous clocks, which can be tuned precisely within a wide frequency range, which makes them suitable for peripherals that require specific frequencies, such as timers and communication modules.

The PM also contains advanced power-saving features, allowing the user to optimize the power consumption for an application. The synchronous clocks are divided into three clock domains, one for the CPU and HSB, one for modules on the PBA bus, and one for modules on the PBB bus.The three clocks can run at different speeds, so the user can save power by running peripherals at a relatively low clock, while maintaining a high CPU performance. Additionally, the clocks can be independently changed on-the-fly, without halting any peripherals. This enables the user to adjust the speed of the CPU and memories to the dynamic load of the application, without disturbing or re-configuring active peripherals.

Each module also has a separate clock, enabling the user to switch off the clock for inactive modules, to save further power. Additionally, clocks and oscillators can be automatically switched off during idle periods by using the sleep instruction on the CPU. The system will return to normal on occurrence of interrupts.

The Power Manager also contains a Reset Controller, which collects all possible reset sources, generates hard and soft resets, and allows the reset source to be identified by software.

35

32059L–AVR32–01/2012

AT32UC3B

9.3

Block Diagram

Figure 9-1.

Power Manager block diagram

RCOSC

Oscillator 0

PLL0

Synchronous

Clock Generator

Synchronous clocks

CPU, HSB,

PBA, PBB

Oscillator 1

PLL1

Voltage Regulator

fuses

Calibration

Registers

Brown-Out

Detector

Power-On

Detector

OSC/PLL

Control signals

Oscillator and

PLL Control

Generic Clock

Generator

Generic clocks

32 KHz

Oscillator

RC

Oscillator

Slow clock

Startup

Counter

32 KHz clock for RTC

Interrupts

Sleep Controller

Sleep instruction

Reset Controller resets

Other reset sources

External Reset Pad

36

32059L–AVR32–01/2012

AT32UC3B

9.4

Product Dependencies

9.4.1

I/O Lines

The PM provides a number of generic clock outputs, which can be connected to output pins, multiplexed with GPIO lines. The programmer must first program the GPIO controller to assign these pins to their peripheral function. If the I/O pins of the PM are not used by the application, they can be used for other purposes by the GPIO controller.

9.4.2

9.4.3

Interrupt

The PM interrupt line is connected to one of the internal sources of the interrupt controller. Using the PM interrupt requires the interrupt controller to be programmed first.

Clock implementation

In AT32UC3B, the HSB shares the source clock with the CPU. This means that writing to the

HSBDIV and HSBSEL bits in CKSEL has no effect. These bits will always read the same as

CPUDIV and CPUSEL.

9.5

Functional Description

9.5.1

9.5.2

Slow clock

The slow clock is generated from an internal RC oscillator which is always running, except in

Static mode. The slow clock can be used for the main clock in the device, as described in ”Synchronous clocks” on page 39

. The slow clock is also used for the Watchdog Timer and measuring various delays in the Power Manager.

The RC oscillator has a 3 cycles startup time, and is always available when the CPU is running.

The RC oscillator operates at approximately 115 kHz, and can be calibrated to a narrow range by the RCOSCCAL fuses. Software can also change RC oscillator calibration through the use of the RCCR register. Please see the Electrical Characteristics section for details.

RC oscillator can also be used as the RTC clock when crystal accuracy is not required.

Oscillator 0 and 1 operation

The two main oscillators are designed to be used with an external crystal and two biasing capacitors, as shown in

Figure 9-2 . Oscillator 0 can be used for the main clock in the device, as

described in

”Synchronous clocks” on page 39 . Both oscillators can be used as source for the

generic clocks, as described in

”Generic clocks” on page 43

.

The oscillators are disabled by default after reset. When the oscillators are disabled, the XIN and

XOUT pins can be used as general purpose I/Os. When the oscillators are configured to use an external clock, the clock must be applied to the XIN pin while the XOUT pin can be used as a general purpose I/O.

The oscillators can be enabled by writing to the OSCnEN bits in MCCTRL. Operation mode

(external clock or crystal) is chosen by writing to the MODE field in OSCCTRLn. Oscillators are automatically switched off in certain sleep modes to reduce power consumption, as described in

Section 9.5.7 on page 42

.

After a hard reset, or when waking up from a sleep mode that disabled the oscillators, the oscillators may need a certain amount of time to stabilize on the correct frequency. This start-up time can be set in the OSCCTRLn register.

37

32059L–AVR32–01/2012

AT32UC3B

The PM masks the oscillator outputs during the start-up time, to ensure that no unstable clocks propagate to the digital logic. The OSCnRDY bits in POSCSR are automatically set and cleared according to the status of the oscillators. A zero to one transition on these bits can also be configured to generate an interrupt, as described in

”MODE: Oscillator Mode” on page 57

.

Figure 9-2.

Oscillator connections

C

2

XOUT

XIN

C

1

9.5.3

9.5.4

32 KHz oscillator operation

The 32 KHz oscillator operates as described for Oscillator 0 and 1 above. The 32 KHz oscillator is used as source clock for the Real-Time Counter.

The oscillator is disabled by default, but can be enabled by writing OSC32EN in OSCCTRL32.

The oscillator is an ultra-low power design and remains enabled in all sleep modes except Static mode.

While the 32 KHz oscillator is disabled, the XIN32 and XOUT32 pins are available as general purpose I/Os. When the oscillator is configured to work with an external clock (MODE field in

OSCCTRL32 register), the external clock must be connected to XIN32 while the XOUT32 pin can be used as a general purpose I/O.

The startup time of the 32 KHz oscillator can be set in the OSCCTRL32, after which OSC32RDY in POSCSR is set. An interrupt can be generated on a zero to one transition of OSC32RDY.

As a crystal oscillator usually requires a very long startup time (up to 1 second), the 32 KHz oscillator will keep running across resets, except Power-On-Reset.

PLL operation

The device contains two PLLs, PLL0 and PLL1. These are disabled by default, but can be enabled to provide high frequency source clocks for synchronous or generic clocks. The PLLs can take either Oscillator 0 or 1 as reference clock. The PLL output is divided by a multiplication factor, and the PLL compares the resulting clock to the reference clock. The PLL will adjust its output frequency until the two compared clocks are equal, thus locking the output frequency to a multiple of the reference clock frequency.

The Voltage Controlled Oscillator inside the PLL can generate frequencies from 80 to 240 MHz.

To make the PLL output frequencies under 80 MHz the OTP[1] bitfield could be set. This will divide the output of the PLL by two and bring the clock in range of the max frequency of the

CPU.

38

32059L–AVR32–01/2012

O s c 0 c lo c k

O s c 1 c lo c k

0

1

P L L O S C

In p u t

D iv id e r

P L L D I V

AT32UC3B

When the PLL is switched on, or when changing the clock source or multiplication factor for the

PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital logic is automatically masked when the PLL is unlocked, to prevent connected digital logic from receiving a too high frequency and thus become unstable.

Figure 9-3.

PLL with control logic and filters

P L L M U L

O u t p u t

D iv id e r

P h a s e

D e t e c t o r

V C O f v c o

1 /2

P L L O P T [ 1 ]

0

1 f

P L L

M a s k

L o c k

D e t e c t o r

P L L c lo c k

L o c k b it

P L L O P T

9.5.4.1

9.5.5

Enabling the PLL

PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1 as clock source. The PLLMUL and PLLDIV bitfields must be written with the multiplication and division factors, respectively, creating the voltage controlled ocillator frequency f

VCO frequency f

PLL

: and the PLL f

VCO

= (PLLMUL+1)/(PLLDIV) • f

OSC if PLLDIV > 0.

f

VCO

= 2*(PLLMUL+1) • f

OSC if PLLDIV = 0.

If PLLOPT[1] field is set to 0: f

PLL

= f

VCO.

If PLLOPT[1] field is set to 1: f

PLL

= f

VCO

/ 2

.

The PLLn:PLLOPT field should be set to proper values according to the PLL operating frequency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2.

The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be generated on a 0 to 1 transition of these bits.

Synchronous clocks

The slow clock (default), Oscillator 0, or PLL0 provide the source for the main clock, which is the common root for the synchronous clocks for the CPU/HSB, PBA, and PBB modules. The main clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from

39

32059L–AVR32–01/2012

AT32UC3B

any tapping of this prescaler, or the undivided main clock, as long as f

CPU f

PBA,B,

. The synchronous clock source can be changed on-the fly, responding to varying load in the application. The clock domains can be shut down in sleep mode, as described in

”Sleep modes” on page 42

.

Additionally, the clocks for each module in the four domains can be individually masked, to avoid power consumption in inactive modules.

Figure 9-4.

Synchronous clock generation

Sleep instruction

Sleep

Controller

Slow clock

Osc0 clock

PLL0 clock

MCSEL

Prescaler

0

1

Main clock

CPUSEL

CPUDIV

Mask

CPUMASK

CPU clocks

HSB clocks

PBAclocks

PBB clocks

9.5.5.1

9.5.5.2

Selecting PLL or oscillator for the main clock

The common main clock can be connected to the slow clock, Oscillator 0, or PLL0. By default, the main clock will be connected to the slow clock. The user can connect the main clock to Oscillator 0 or PLL0 by writing the MCSEL bitfield in the Main Clock Control Register (MCCTRL). This must only be done after that unit has been enabled, otherwise a deadlock will occur. Care should also be taken that the new frequency of the synchronous clocks does not exceed the maximum frequency for each clock domain.

Selecting synchronous clock division ratio

The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks.

By default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock by writing CKSEL:CPUDIV to 1 and CPUSEL to the prescaling value, resulting in a CPU clock frequency: f

CPU

= f main

/ 2

(CPUSEL+1)

40

32059L–AVR32–01/2012

AT32UC3B

9.5.5.3

9.5.6

9.5.6.1

9.5.6.2

Similarly, the clock for the PBA, and PBB can be divided by writing their respective bitfields. To ensure correct operation, frequencies must be selected so that f

CPU f

PBA,B must never exceed the specified maximum frequency for each clock domain.

. Also, frequencies

CKSEL can be written without halting or disabling peripheral modules. Writing CKSEL allows a new clock setting to be written to all synchronous clocks at the same time. It is possible to keep one or more clocks unchanged by writing the same value a before to the xxxDIV and xxxSEL bitfields. This way, it is possible to e.g. scale CPU and HSB speed according to the required performance, while keeping the PBA and PBB frequency constant.

For modules connected to the HSB bus, the PB clock frequency must be set to the same frequency than the CPU clock.

Clock Ready flag

There is a slight delay from CKSEL is written and the new clock setting becomes effective. During this interval, the Clock Ready (CKRDY) flag in ISR will read as 0. If IER:CKRDY is written to

1, the Power Manager interrupt can be triggered when the new clock setting is effective. CKSEL must not be re-written while CKRDY is 0, or the system may become unstable or hang.

Peripheral clock masking

By default, the clock for all modules are enabled, regardless of which modules are actually being used. It is possible to disable the clock for a module in the CPU, HSB, PBA, or PBB clock domain by writing the corresponding bit in the Clock Mask register (CPU/HSB/PBA/PBB) to 0.

When a module is not clocked, it will cease operation, and its registers cannot be read or written.

The module can be re-enabled later by writing the corresponding mask bit to 1.

A module may be connected to several clock domains, in which case it will have several mask bits.

Table 9-6 contains a list of implemented maskable clocks.

Cautionary note

Note that clocks should only be switched off if it is certain that the module will not be used.

Switching off the clock for the internal RAM will cause a problem if the stack is mapped there.

Switching off the clock to the Power Manager (PM), which contains the mask registers, or the corresponding PBx bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset.

Mask Ready flag

Due to synchronization in the clock generator, there is a slight delay from a mask register is written until the new mask setting goes into effect. When clearing mask bits, this delay can usually be ignored. However, when setting mask bits, the registers in the corresponding module must not be written until the clock has actually be re-enabled. The status flag MSKRDY in ISR provides the required mask status information. When writing either mask register with any value, this bit is cleared. The bit is set when the clocks have been enabled and disabled according to the new mask setting. Optionally, the Power Manager interrupt can be enabled by writing the

MSKRDY bit in IER.

41

32059L–AVR32–01/2012

AT32UC3B

9.5.7

Sleep modes

In normal operation, all clock domains are active, allowing software execution and peripheral operation. When the CPU is idle, it is possible to switch off the CPU clock and optionally other clock domains to save power. This is activated by the sleep instruction, which takes the sleep mode index number as argument.

9.5.7.1

Entering and exiting sleep modes

The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains.

The modules will be halted regardless of the bit settings of the mask registers.

Oscillators and PLLs can also be switched off to save power. Some of these modules have a relatively long start-up time, and are only switched off when very low power consumption is required.

The CPU and affected modules are restarted when the sleep mode is exited. This occurs when an interrupt triggers. Note that even if an interrupt is enabled in sleep mode, it may not trigger if the source module is not clocked.

9.5.7.2

Table 9-1.

Index

0

1

4

5

2

3

Supported sleep modes

The following sleep modes are supported. These are detailed in Table 9-1

.

•Idle: The CPU is stopped, the rest of the chip is operating. Wake-up sources are any interrupt.

•Frozen: The CPU and HSB modules are stopped, peripherals are operating. Wake-up sources are any interrupts from PB modules.

•Standby: All synchronous clocks are stopped, but oscillators and PLLs are running, allowing quick wake-up to normal mode. Wake-up sources are RTC or external interrupt (EIC), external reset or any asynchronous interrupts from PB modules.

•Stop: As Standby, but Oscillator 0 and 1, and the PLLs are stopped. 32 KHz (if enabled) and

RC oscillators and RTC/WDT will still operate. Wake-up are the same as for Standby mode.

•DeepStop: All synchronous clocks, Oscillator 0 and 1 and PLL 0 and 1 are stopped. 32 KHz oscillator can run if enabled. RC oscillator still operates. Bandgap voltage reference and BOD is turned off. Wake-up sources are RTC, external interrupt in asynchronous mode, external reset or any asynchronous interrupts from PB modules.

•Static: All oscillators, including 32 KHz and RC oscillator are stopped. Bandgap voltage reference BOD detector is turned off. Wake-up sources are external interrupt (EIC) in asynchronous mode only, external reset pin or any asynchronous interrupts from PB modules.

Sleep modes

Sleep Mode

Idle

Frozen

Standby

Stop

DeepStop

Static

CPU

Stop

Stop

Stop

Stop

Stop

Stop

HSB

Run

Stop

Stop

Stop

Stop

Stop

PBA,B

GCLK

Run

Run

Stop

Stop

Stop

Stop

Run

Stop

Stop

Stop

Osc0,1

PLL0,1,

SYSTIMER

Run

Run

Osc32

Run

Run

Run

Run

Run

Stop

RCOsc

Run

Run

Run

Run

Run

Stop

On

On

Off

Off

BOD &

Bandgap

On

On

Voltage

Regulator

Full power

Full power

Full power

Low power

Low power

Low power

42

32059L–AVR32–01/2012

AT32UC3B

9.5.7.3

9.5.7.4

9.5.8

The power level of the internal voltage regulator is also adjusted according to the sleep mode to reduce the internal regulator power consumption.

Precautions when entering sleep mode

Modules communicating with external circuits should normally be disabled before entering a sleep mode that will stop the module operation. This prevents erratic behavior when entering or exiting sleep mode. Please refer to the relevant module documentation for recommended actions.

Communication between the synchronous clock domains is disturbed when entering and exiting sleep modes. This means that bus transactions are not allowed between clock domains affected by the sleep mode. The system may hang if the bus clocks are stopped in the middle of a bus transaction.

The CPU is automatically stopped in a safe state to ensure that all CPU bus operations are complete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is necessary.

When entering a sleep mode (except Idle mode), all HSB masters must be stopped before entering the sleep mode. Also, if there is a chance that any PB write operations are incomplete, the CPU should perform a read operation from any register on the PB bus before executing the sleep instruction. This will stall the CPU while waiting for any pending PB operations to complete.

When entering a sleep mode deeper or equal to DeepStop, the VBus asynchronous interrupt should be disabled (USBCON.VBUSTE = 0).

Wake Up

The USB can be used to wake up the part from sleep modes through register AWEN of the

Power Manager.

Generic clocks

Timers, communication modules, and other modules connected to external circuitry may require specific clock frequencies to operate correctly. The Power Manager contains an implementation defined number of generic clocks that can provide a wide range of accurate clock frequencies.

Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source can optionally be divided by any even integer up to 512. Each clock can be independently enabled and disabled, and is also automatically disabled along with peripheral clocks by the

Sleep Controller.

43

32059L–AVR32–01/2012

AT32UC3B

Figure 9-5.

Generic clock generation

Sleep

Controller

Osc0 clock

Osc1 clock

PLL0 clock

PLL1 clock

0

1

PLLSEL

OSCSEL

Divider

DIV

0

1

DIVEN

Mask

Generic Clock

CEN

9.5.8.1

9.5.8.2

9.5.8.3

Enabling a generic clock

A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use either Oscillator 0 or 1 or PLL0 or 1 as source, as selected by the PLLSEL and OSCSEL bits.

The source clock can optionally be divided by writing DIVEN to 1 and the division factor to DIV, resulting in the output frequency: f

GCLK

= f

SRC

/

(2*(DIV+1))

Disabling a generic clock

The generic clock can be disabled by writing CEN to 0 or entering a sleep mode that disables the PB clocks. In either case, the generic clock will be switched off on the first falling edge after the disabling event, to ensure that no glitches occur. If CEN is written to 0, the bit will still read as

1 until the next falling edge occurs, and the clock is actually switched off. When writing CEN to 0, the other bits in GCCTRL should not be changed until CEN reads as 0, to avoid glitches on the generic clock.

When the clock is disabled, both the prescaler and output are reset.

Changing clock frequency

When changing generic clock frequency by writing GCCTRL, the clock should be switched off by the procedure above, before being re-enabled with the new clock source or division setting. This prevents glitches during the transition.

44

32059L–AVR32–01/2012

AT32UC3B

9.5.8.4

9.5.9

9.5.10

9.5.11

Generic clock implementation

In AT32UC3B, there are 5 generic clocks. These are allocated to different functions as shown in

Table 9-2 .

Table 9-2.

Generic clock allocation

Clock number Function

2

3

0

1

4

GCLK0 pin

GCLK1 pin

GCLK2 pin

USBB

ABDAC

Divided PB clocks

The clock generator in the Power Manager provides divided PBA and PBB clocks for use by peripherals that require a prescaled PBx clock. This is described in the documentation for the relevant modules.

The divided clocks are not directly maskable, but are stopped in sleep modes where the PBx clocks are stopped.

Debug operation

During a debug session, the user may need to halt the system to inspect memory and CPU registers. The clocks normally keep running during this debug operation, but some peripherals may require the clocks to be stopped, e.g. to prevent timer overflow, which would cause the program to fail. For this reason, peripherals on the PBA and PBB buses may use “debug qualified” PBx clocks. This is described in the documentation for the relevant modules. The divided PBx clocks are always debug qualified clocks.

Debug qualified PB clocks are stopped during debug operation. The debug system can optionally keep these clocks running during the debug operation. This is described in the documentation for the On-Chip Debug system.

Reset Controller

The Reset Controller collects the various reset sources in the system and generates hard and soft resets for the digital logic.

The device contains a Power-On Detector, which keeps the system reset until power is stable.

This eliminates the need for external reset circuitry to guarantee stable operation when powering up the device.

It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pullup, and does not need to be driven externally when negated.

Table 9-4

lists these and other reset sources supported by the Reset Controller.

45

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

Figure 9-6.

Reset Controller block diagram

R C _ R C A U S E

R E S E T _ N

P o w e r-O n

D e te cto r

B ro w n o u t

D e te cto r

J T A G

O C D

W a tc h d o g R e s e t

R e se t

C o n tro lle r

C P U , H S B ,

P B A , P B B

O C D , R T C /W D T

C lo ck G e n e ra to

In addition to the listed reset types, the JTAG can keep parts of the device statically reset through the JTAG Reset Register. See JTAG documentation for details.

Table 9-3.

Reset source

Power-on Reset

External Reset

Brownout Reset

CPU Error

Reset description

Watchdog Timer

OCD

Description

Supply voltage below the power-on reset detector threshold voltage

RESET_N pin asserted

Supply voltage below the brownout reset detector threshold voltage

Caused by an illegal CPU access to external memory while in Supervisor mode

See watchdog timer documentation.

See On-Chip Debug documentation

When a Reset occurs, some parts of the chip are not necessarily reset, depending on the reset source. Only the Power On Reset (POR) will force a reset of the whole chip.

46

AT32UC3B

Table 9-4 lists parts of the device that are reset, depending on the reset source.

Table 9-4.

Effect of the different reset events

Power-On

Reset

Y CPU/HSB/PBA/PBB

(excluding Power Manager)

32 KHz oscillator

RTC control register

GPLP registers

Watchdog control register

Voltage Calibration register

Y

Y

Y

Y

Y

RC Oscillator Calibration register

BOD control register

Bandgap control register

Clock control registers

Osc0/Osc1 and control registers

PLL0/PLL1 and control registers

OCD system and OCD registers

Y

Y

Y

Y

Y

Y

Y

External

Reset

Y

Y

Y

Y

Y

Y

N

Y

N

Y

N

N

N

Watchdog

Reset

Y

Y

Y

N

N

Y

N

N

N

N

N

N

N

BOD

Reset

Y

Y

Y

Y

N

Y

N

N

N

Y

N

N

N

CPU Error

Reset

Y

Y

Y

Y

N

Y

N

N

N

Y

N

N

N

OCD

Reset

Y

Y

Y

N

N

Y

N

N

N

Y

N

N

N

The cause of the last reset can be read from the RCAUSE register. This register contains one bit for each reset source, and can be read during the boot sequence of an application to determine the proper action to be taken.

9.5.11.1

9.5.11.2

Power-On Detector

The Power-On Detector monitors the VDDCORE supply pin and generates a reset when the device is powered on. The reset is active until the supply voltage from the linear regulator is above the power-on threshold level. The reset will be re-activated if the voltage drops below the power-on threshold level. See Electrical Characteristics for parametric details.

Brown-Out Detector

The Brown-Out Detector (BOD) monitors the VDDCORE supply pin and compares the supply voltage to the brown-out detection level, as set in BOD.LEVEL. The BOD is disabled by default, but can be enabled either by software or by flash fuses. The Brown-Out Detector can either generate an interrupt or a reset when the supply voltage is below the brown-out detection level. In any case, the BOD output is available in bit POSCR.BODET bit.

Note 1 : Any change to the BOD.LEVEL field of the BOD register should be done with the BOD deactivated to avoid spurious reset or interrupt.

Note 2 : If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will be in constant reset. In order to leave reset state, an external voltage higher than the BOD level should be applied. Thus, it is possible to disable BOD.

47

32059L–AVR32–01/2012

AT32UC3B

9.5.11.3

9.5.12

See Electrical Characteristics for parametric details.

External Reset

The external reset detector monitors the state of the RESET_N pin. By default, a low level on this pin will generate a reset.

Calibration registers

The Power Manager controls the calibration of the RC oscillator, voltage regulator, bandgap voltage reference through several calibration registers.

Those calibration registers are loaded after a Power On Reset with default values stored in factory-programmed flash fuses.

Although it is not recommended to override default factory settings, it is still possible to override these default values by writing to those registers. To prevent unexpected writes due to software bugs, write access to these registers is protected by a “key”. First, a write to the register must be made with the field “KEY” equal to 0x55 then a second write must be issued with the “KEY” field equal to 0xAA

48

32059L–AVR32–01/2012

AT32UC3B

0x0050

0x0054

0x0060-0x070

0x00C0

0x00C4

0x00C8

0x00D0

0x0140

0x0144

0x0200

0x0204

0x0024

0x0028

0x002C

0x0030

0x0040

0x0044

0x0048

0x004C

Offset

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0020

9.6

User Interface

Table 9-5.

PM Register Memory Map

Register

Main Clock Control Register

Clock Select Register

CPU Mask Register

HSB Mask Register

PBA Mask Register

PBB Mask Register

PLL0 Control Register

PLL1 Control Register

Oscillator 0 Control Register

Oscillator 1 Control Register

Oscillator 32 Control Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Interrupt Status Register

Interrupt Clear Register

Power and Oscillators Status Register

Generic Clock Control Register

RC Oscillator Calibration Register

Bandgap Calibration Register

Linear Regulator Calibration Register

BOD Level Register

Reset Cause Register

Asynchronous Wake Up Enable Register

General Purpose Low-Power Register 0

General Purpose Low-Power Register 1

ICR

POSCSR

GCCTRL

RCCR

BGCR

VREGCR

BOD

RCAUSE

AWEN

GPLP0

GPLP1

Register Name

MCCTRL

CKSEL

CPUMASK

HSBMASK

PBAMASK

PBBMASK

PLL0

PLL1

OSCCTRL0

OSCCTRL1

OSCCTRL32

IER

IDR

IMR

ISR

Write-Only

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read-Only

Read/Write

Read/Write

Read/Write

Access

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Write-Only

Write-Only

Read-Only

Read-Only

Reset

0x00000000

0x00000000

0x00000003

0x0000007F

0x00007FFF

0x0000003F

0x00000000

0x00000000

0x00000000

0x00000000

0x00010000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

Factory settings

Factory settings

Factory settings

BOD fuses in Flash

Latest Reset Source

0x00000000

0x00000000

0x00000000

49

32059L–AVR32–01/2012

AT32UC3B

9.6.1

Main Clock Control Register

Name: MCCTRL

Access Type:

Offset:

Reset Value:

Read/Write

0x000

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

15

-

14

-

13

-

7

-

6

-

5 4

• OSC1EN: Oscillator 1 Enable

0: Oscillator 1 is disabled.

1: Oscillator 1 is enabled.

• OSC0EN: Oscillator 0 Enable

0: Oscillator 0 is disabled.

1: Oscillator 0 is enabled.

• MCSEL: Main Clock Select

0: The slow clock is the source for the main clock.

1: Oscillator 0 is the source for the main clock.

2: PLL0 is the source for the main clock.

3: Reserved.

12

-

28

-

20

-

11

-

3

OSC1EN

27

-

19

-

10

-

2

OSC0EN

26

-

18

-

9

-

1

25

-

17

-

MCSEL

8

-

0

24

-

16

-

50

32059L–AVR32–01/2012

AT32UC3B

9.6.2

Clock Select Register

Name: CKSEL

Access Type:

Offset:

Reset Value:

Read/Write

0x004

0x00000000

31

PBBDIV

23

PBADIV

15

HSBDIV

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

26

18

10

25

PBBSEL

17

PBASEL

9

HSBSEL

24

16

8

7

CPUDIV

6

-

5

-

4

-

3

-

2 1

CPUSEL

0

• PBBDIV, PBBSEL: PBB Division and Clock Select

PBBDIV = 0: PBB clock equals main clock.

PBBDIV = 1: PBB clock equals main clock divided by 2

(PBBSEL+1)

.

• PBADIV, PBASEL: PBA Division and Clock Select

PBADIV = 0: PBA clock equals main clock.

PBADIV = 1: PBA clock equals main clock divided by 2

(PBASEL+1)

.

• HSBDIV, HSBSEL: HSB Division and Clock Select

For the

AT32UC3B

, HSBDIV always equals CPUDIV, and HSBSEL always equals CPUSEL, as the HSB clock is always equal to the CPU clock.

• CPUDIV, CPUSEL: CPU Division and Clock Select

CPUDIV = 0: CPU clock equals main clock.

CPUDIV = 1: CPU clock equals main clock divided by 2

(CPUSEL+1)

.

Note that if xxxDIV is written to 0, xxxSEL should also be written to 0 to ensure correct operation.

Also note that writing this register clears POSCSR:CKRDY. The register must not be re-written until CKRDY goes high.

51

32059L–AVR32–01/2012

AT32UC3B

9.6.3

Clock Mask Register

Name: CPU/HSB/PBA/PBBMASK

Access Type:

Offset:

Reset Value:

-

Read/Write

0x008, 0x00C, 0x010, 0x014

15

7

31

23

14

6

30

22

13

5

29

21

28

MASK[31:24]

27

20

MASK[23:16]

19

12

MASK[15:8]

11

4

MASK[7:0]

3

10

2

26

18

9

1

25

17

8

0

24

16

52

32059L–AVR32–01/2012

AT32UC3B

• MASK: Clock Mask

If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is shown in

Table 9-6 .

Table 9-6.

11

12

13

14

9

10

7

8

15

16

5

6

3

4

Bit

0

1

2

31:

17

Maskable module clocks in AT32UC3B.

-

-

-

-

-

-

-

-

CPUMASK

-

OCD

(1)

-

-

-

-

-

-

SYSTIMER

(COMPARE/COUNT

REGISTERS CLK)

-

-

-

-

-

-

-

-

-

-

-

HSBMASK

FLASHC

PBA bridge

PBB bridge

USBB

PDCA

-

-

PBAMASK

INTC

GPIO

PDCA

PM/RTC/EIC

ADC

SPI

TWI

USART0

USART1

USART2

PWM

SSC

TC

ABDAC

-

-

-

-

-

-

-

-

-

-

-

-

-

-

PBBMASK

HMATRIX

USBB

FLASHC

-

-

-

-

-

Note: 1. This bit must be one if the user wishes to debug the device with a JTAG debugger.

53

32059L–AVR32–01/2012

AT32UC3B

9.6.4

PLL Control Register

Name: PLL0,1

Access Type:

Offset:

Reset Value:

Read/Write

0x020, 0x024

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

29

21

-

13

-

28

20

-

12

-

27

19

11

PLLCOUNT

26

18

10

25

PLLMUL

17

PLLDIV

9

24

16

8

7

-

6

-

5

-

4 3

PLLOPT

2 1

PLLOSC

0

PLLEN

• PLLCOUNT: PLL Count

Specifies the number of slow clock cycles before ISR:LOCKn will be set after PLLn has been written, or after PLLn has been automatically re-enabled after exiting a sleep mode.

• PLLMUL: PLL Multiply Factor

• PLLDIV: PLL Division Factor

These fields determine the ratio of the ouput frequency of the internal VCO of the PLL (f

VCO

) to the source oscillator frequency:

f

VCO

= (PLLMUL+1)/(PLLDIV) * f

OSC if PLLDIV > 0.

• f

VCO

= 2 * (PLLMUL+1) * f

OSC if PLLDIV = 0.

If PLLOPT[1] bit is set to 0: f

PLL

= f

VCO.

If PLLOPT[1] bit is set to 1: f

PLL

= f

VCO

/ 2

.

Note that the PLLMUL field cannot be equal to 0 or 1, or the behavior of the PLL will be undefined.

PLLDIV gives also the input frequency of the PLL (f

IN

): if the PLLDIV field is set to 0: f

IN

= f

OSC.

if the PLLDIV field is greater than 0: f

IN

= f

• PLLOPT: PLL Option

OSC

/ (2 * PLLDIV).

Select the operating range for the PLL.

PLLOPT[0]: Select the VCO frequency range.

PLLOPT[1]: Enable the extra output divider.

PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time).

54

32059L–AVR32–01/2012

Table 9-7.

PLLOPT Fields Description in AT32UC3B

Description

PLLOPT[0]: VCO frequency

0

1

PLLOPT[1]: Output divider

0

1

PLLOPT[2]

0

1

160MHz<f vco

<240MHz

80MHz<f vco

<180MHz f

PLL

= f vco f

PLL

= f vco

/2

Wide Bandwidth Mode enabled

Wide Bandwidth Mode disabled

• PLLOSC: PLL Oscillator Select

0: Oscillator 0 is the source for the PLL.

1: Oscillator 1 is the source for the PLL.

• PLLEN: PLL Enable

0: PLL is disabled.

1: PLL is enabled.

AT32UC3B

55

32059L–AVR32–01/2012

AT32UC3B

9.6.5

Name:

Oscillator 0/1 Control Register

OSCCTRL0,1

Access Type:

Offset:

Reset Value:

Read/Write

0x028, 0x02C

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

26

-

18

-

10

7

-

6

-

5

-

4

-

3

-

• STARTUP: Oscillator Startup Time

Select startup time for the oscillator.

Table 9-8.

STARTUP

0

1

4

5

2

3

6

7

Startup time for oscillators 0 and 1

Number of RC oscillator clock cycle

0

64

128

2048

4096

8192

16384

Reserved

Approximative Equivalent time

(RCOsc = 115 kHz)

0

560 us

1.1 ms

18 ms

36 ms

71 ms

142 ms

Reserved

2 1

MODE

• MODE: Oscillator Mode

Choose between crystal, or external clock

0: External clock connected on XIN, XOUT can be used as an I/O (no crystal).

1 to 3: reserved .

4: Crystal is connected to XIN/XOUT - Oscillator is used with gain G0 ( XIN from

0.4 MHz to 0.9 MHz ).

5: Crystal is connected to XIN/XOUT - Oscillator is used with gain G1 ( XIN from

0.9 MHz to 3.0 MHz ).

6: Crystal is connected to XIN/XOUT - Oscillator is used with gain G2 ( XIN from

3.0 MHz to 8.0 MHz ).

7: Crystal is connected to XIN/XOUT - Oscillator is used with gain G3 ( XIN from

8.0 Mhz).

25

-

17

-

9

STARTUP

24

-

16

-

8

0

56

32059L–AVR32–01/2012

AT32UC3B

9.6.6

Name:

32 KHz Oscillator Control Register

OSCCTRL32

Access Type:

Offset:

Reset Value:

Read/Write

0x030

0x00010000

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

26

-

18

10

7

-

6

-

5

-

4

-

3

-

Note: This register is only reset by Power-On Reset

• STARTUP: Oscillator Startup Time

Select startup time for 32 KHz oscillator.

Table 9-9.

STARTUP

0

1

2

5

6

3

4

7

Startup time for 32 KHz oscillator

Number of RC oscillator clock cycle

0

Approximative Equivalent time

(RCOsc = 115 kHz)

0

128

8192

16384

65536

131072

262144

524288

1.1 ms

72.3 ms

143 ms

570 ms

1.1 s

2.3 s

4.6 s

• MODE: Oscillator Mode

Choose between crystal, or external clock.

0: External clock connected on XIN32, XOUT32 can be used as a I/O (no crystal).

1: Crystal is connected to XIN32/XOUT32.

2 to 7: reserved .

• OSC32EN: Enable the 32 KHz oscillator

0: 32 KHz Oscillator is disabled.

1: 32 KHz Oscillator is enabled.

2

-

25

-

17

STARTUP

9

MODE

1

-

24

-

16

8

0

OSC32EN

57

32059L–AVR32–01/2012

AT32UC3B

9.6.7

Interrupt Enable Register

Name: IER

Access Type:

Offset:

Reset Value:

Write-only

0x040

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

7

OSC0RDY

6

MSKRDY

5

CKRDY

4

-

3

-

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will set the corresponding bit in IMR.

27

-

19

-

11

-

2

-

10

-

26

-

18

-

25

-

17

-

9

OSC32RDY

1

LOCK1

24

-

16

BODDET

8

OSC1RDY

0

LOCK0

58

32059L–AVR32–01/2012

AT32UC3B

9.6.8

Interrupt Disable Register

Name: IDR

Access Type:

Offset:

Reset Value:

Write-only

0x044

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

7

OSC0RDY

6

MSKRDY

5

CKRDY

4

-

3

-

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will clear the corresponding bit in IMR.

2

-

10

-

26

-

18

-

25

-

17

-

9

OSC32RDY

1

LOCK1

24

-

16

BODDET

8

OSC1RDY

0

LOCK0

59

32059L–AVR32–01/2012

AT32UC3B

9.6.9

Interrupt Mask Register

Name: IMR

Access Type:

Offset:

Reset Value:

Read-only

0x048

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

7

OSC0RDY

6

MSKRDY

5

CKRDY

4

-

3

-

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

A bit in this register is cleared when the corresponding bit in IDR is written to one.

A bit in this register is set when the corresponding bit in IER is written to one.

2

-

26

-

18

-

10

-

25

-

17

-

9

OSC32RDY

1

LOCK1

24

-

16

BODDET

8

OSC1RDY

0

LOCK0

60

32059L–AVR32–01/2012

AT32UC3B

9.6.10

Interrupt Status Register

Name: ISR

Access Type:

Offset:

Reset Value:

Read-only

0x04C

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

26

-

18

-

10

-

25

-

17

-

9

OSC32RDY

24

-

16

BODDET

8

OSC1RDY

7

OSC0RDY

6

MSKRDY

5

CKRDY

4

-

3

-

2

-

1

LOCK1

0

LOCK0

• BODDET: Brown out detection

Set to 1 when 0 to 1 transition on POSCSR:BODDET bit is detected:

BOD has detected that power supply is going below

BOD reference value.

• OSC32RDY: 32 KHz oscillator Ready

Set to 1 when 0 to 1 transition on the POSCSR:OSC32RDY bit is detected:

The 32 KHz oscillator is stable and ready to be used as clock source.

• OSC1RDY: Oscillator 1 Ready

Set to 1 when 0 to 1 transition on the POSCSR:OSC1RDY bit is detected:

Oscillator 1 is stable and ready to be used as clock source.

• OSC0RDY: Oscillator 0 Ready

Set to 1 when 0 to 1 transition on the POSCSR:OSC1RDY bit is detected:

Oscillator 1 is stable and ready to be used as clock source.

• MSKRDY: Mask Ready

Set to 1 when 0 to 1 transition on the POSCSR:MSKRDY bit is detected:

Clocks are now masked according to the

(CPU/HSB/PBA/PBB)_MASK registers.

• CKRDY: Clock Ready

0: The CKSEL register has been written, and the new clock setting is not yet effective.

1: The synchronous clocks have frequencies as indicated in the CKSEL register.

Note: Writing ICR:CKRDY to 1 has no effect.

• LOCK1: PLL1 locked

Set to 1 when 0 to 1 transition on the POSCSR:LOCK1 bit is detected:

PLL 1 is locked and ready to be selected as clock source.

• LOCK0: PLL0 locked

Set to 1 when 0 to 1 transition on the POSCSR:LOCK0 bit is detected:

PLL 0 is locked and ready to be selected as clock source.

61

32059L–AVR32–01/2012

AT32UC3B

9.6.11

Interrupt Clear Register

Name: ICR

Access Type:

Offset:

Reset Value:

Write-only

0x050

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

7

OSC0RDY

6

MSKRDY

5

CKRDY

4

-

3

-

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will clear the corresponding bit in ISR.

2

-

10

-

26

-

18

-

25

-

17

-

9

OSC32RDY

1

LOCK1

24

-

16

BODDET

8

OSC1RDY

0

LOCK0

62

32059L–AVR32–01/2012

AT32UC3B

9.6.12

Power and Oscillators Status Register

Name: POSCSR

Access Type:

Offset:

Reset Value:

Read-only

0x054

0x00000000

31

-

30

-

29

-

28

-

23

-

15

-

22

-

14

-

21

-

13

-

20

-

12

-

27

-

19

-

11

-

7

OSC0RDY

6

MSKRDY

5

CKRDY

4

-

3

-

2

WAKE

• BODDET: Brown out detection

0: No BOD event.

1: BOD has detected that power supply is going below BOD reference value.

• OSC32RDY: 32 KHz oscillator Ready

0: The 32 KHz oscillator is not enabled or not ready.

1: The 32 KHz oscillator is stable and ready to be used as clock source.

• OSC1RDY: OSC1 ready

0: Oscillator 1 not enabled or not ready.

1: Oscillator 1 is stable and ready to be used as clock source.

• OSC0RDY: OSC0 ready

0: Oscillator 0 not enabled or not ready.

1: Oscillator 0 is stable and ready to be used as clock source.

• MSKRDY: Mask ready

0: Mask register has been changed, masking in progress.

1: Clock are masked according to xxx_MASK.

• CKRDY:

0: The CKSEL register has been written, and the new clock setting is not yet effective.

1: The synchronous clocks have frequencies as indicated in the CKSEL register.

• LOCK1: PLL 1 locked

0:PLL 1 is unlocked.

1:PLL 1 is locked, and ready to be selected as clock source.

• LOCK0: PLL 0 locked

0: PLL 0 is unlocked.

1: PLL 0 is locked, and ready to be selected as clock source.

26

-

18

-

10

-

25

-

17

-

9

OSC32RDY

1

LOCK1

24

-

16

BODDET

8

OSC1RDY

0

LOCK0

63

32059L–AVR32–01/2012

AT32UC3B

9.6.13

Generic Clock Control Register

Name: GCCTRL

Access Type:

Offset:

Reset Value:

Read/Write

0x060 - 0x070

0x00000000

31

-

23

-

15

30

-

22

-

14

29

-

21

-

13

28

-

20

-

12

DIV[7:0]

7

-

6

-

5

-

4

DIVEN

There is one GCCTRL register per generic clock in the design.

• DIV: Division Factor

• DIVEN: Divide Enable

0: The generic clock equals the undivided source clock.

1: The generic clock equals the source clock divided by 2*(DIV+1).

• CEN: Clock Enable

0: Clock is stopped.

1: Clock is running.

• PLLSEL: PLL Select

0: Oscillator is source for the generic clock.

1: PLL is source for the generic clock.

• OSCSEL: Oscillator Select

0: Oscillator (or PLL) 0 is source for the generic clock.

1: Oscillator (or PLL) 1 is source for the generic clock.

3

-

27

-

19

-

11

26

-

18

-

10

2

CEN

25

-

17

-

9

24

-

16

-

8

1

PLLSEL

0

OSCSEL

64

32059L–AVR32–01/2012

AT32UC3B

9.6.14

Name:

RC Oscillator Calibration Register

RCCR

Access Type:

Offset:

Reset Value:

-

Read/Write

0x0C0

31 30 29 28 27 26 25 24

KEY

23

-

15

-

22

-

14

-

21

-

13

-

20

-

12

-

19

-

11

-

18

-

10

-

17

-

16

FCD

9

CALIB[9:8]

8

7 6 5 4 3 2 1

CALIB[7:0]

• KEY: Register Write protection

This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.

• CALIB: Calibration Value

Calibration Value for the RC oscillator.

• FCD: Flash Calibration Done

Set to 1 when the CALIB field has been updated by the Flash fuses after power-on reset or Flash fuses update.

• 0: Allow subsequent overwriting of the CALIB value by Flash fuses.

• 1: The CALIB value will not be updated again by Flash fuses.

0

65

32059L–AVR32–01/2012

AT32UC3B

9.6.15

Name:

Bandgap Calibration Register

BGCR

Access Type:

Offset:

Reset Value:

-

Read/Write

0x0C4

31 30 29 28 27 26 25 24

KEY

23

-

15

-

22

-

14

-

21

-

13

-

20

-

12

-

19

-

11

-

18

-

10

-

9

-

17

-

7

-

6

-

5

-

4

-

3

-

2 1

CALIB

• KEY: Register Write protection

This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.

• CALIB: Calibration value

Calibration value for Bandgap. See Electrical Characteristics for voltage values.

• FCD: Flash Calibration Done

Set to 1 when the CALIB field has been updated by the Flash fuses after power-on reset or Flash fuses update.

• 0: Allow subsequent overwriting of the CALIB value by Flash fuses.

• 1: The CALIB value will not be updated again by Flash fuses.

0

16

FCD

8

-

66

32059L–AVR32–01/2012

AT32UC3B

9.6.16

Name::

Voltage Regulator Calibration Register

VREGCR

Register access:

Offset:

Reset Value:

-

Read/Write

0x0C8

31 30 29 28 27 26 25 24

KEY

23

-

15

-

22

-

14

-

21

-

13

-

20

-

12

-

19

-

11

-

18

-

10

-

9

-

17

-

16

FCD

8

-

7

-

6

-

5

-

4

-

3

-

2 1

CALIB

0

• KEY: Register Write protection

• This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.

• CALIB: Calibration value

• Calibration value for Voltage Regulator. The user can change this value to decrease or increase the Voltage Regulator output voltage.

• FCD: Flash Calibration Done

Set to 1 when the CALIB field has been updated by the Flash fuses after power-on reset or Flash fuses update.

• 0: Allow subsequent overwriting of the CALIB value by Flash fuses.

• 1: The CALIB value will not be updated again by Flash fuses.

67

32059L–AVR32–01/2012

AT32UC3B

9.6.17

Name:

BOD Level Register

BOD

Access Type:

Offset:

Reset Value:

-

Read/Write

0x0D0

31 30 29 28 27 26 25 24

KEY

23

-

15

-

22

-

14

-

21

-

13

-

20

-

12

-

19

-

11

-

18

-

10

-

17

-

9

CTRL

16

FCD

8

7

-

6

HYST

5 4 3

LEVEL

2 1 0

• KEY: Register Write protection

This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.

• FCD: BOD Fuse calibration done

Set to 1 when CTRL, HYST and LEVEL fields has been updated by the Flash fuses after power-on reset or Flash fuses update.

• 0: Allow subsequent overwriting of the value by Flash fuses.

• 1: The CTRL, HYST and LEVEL values will not be updated again by Flash fuses.

• CTRL: BOD Control

• 0: BOD is off.

• 1: BOD is enabled and can reset the chip.

• 2: BOD is enabled and but cannot reset the chip. Only interrupt will be sent to interrupt controller, if enabled in the IMR register.

• 3: BOD is off.

• HYST: BOD Hysteresis

• 0: No hysteresis

• 1: Hysteresis On

• LEVEL: BOD Level

• This field sets the triggering threshold of the BOD. See Electrical Characteristics for actual voltage levels.

• Note that any change to the LEVEL field of the BOD register should be done with the BOD deactivated to avoid spurious reset or interrupt.

68

32059L–AVR32–01/2012

AT32UC3B

9.6.18

Reset Cause Register

Name: RCAUSE

Access Type:

Offset:

Reset Value:

Read-only

0x140

Latest Reset Source

31

-

30

-

29

-

23

-

15

-

22

-

14

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

26

-

18

-

10

-

25

-

17

-

9

-

7

-

6

-

5

-

4

JTAG

3

WDT

2

EXT

1

BOD

• OCDRST: OCD Reset

• The CPU was reset because the RES strobe in the OCD Development Control register has been written to one.

• JTAG: JTAG reset

• The CPU was reset by setting the bit RC_CPU in the JTAG reset register.

• WDT: Watchdog Reset

• The CPU was reset because of a watchdog time-out.

• EXT: External Reset Pin

• The CPU was reset due to the RESET pin being asserted.

• BOD: Brown-out Reset

• The CPU was reset due to the supply voltage being lower than the brown-out threshold level.

• POR Power-on Reset

• The CPU was reset due to the supply voltage being lower than the power-on threshold level.

0

POR

24

-

16

-

8

OCDRST

69

32059L–AVR32–01/2012

AT32UC3B

9.6.19

Name:

Asynchronous Wake Up Enable Register

AWEN

Access Type:

Offset:

Reset Value:

Read/Write

0x144

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

7

-

6

-

• USB_WAKEN : USB Wake Up Enable

0: The USB wake up is disabled.

• 1: The USB wake up is enabled.

5

-

29

-

21

-

13

-

4

-

12

-

28

-

20

-

3

-

11

-

27

-

19

-

2

-

10

-

26

-

18

-

1

-

9

-

25

-

17

-

24

-

16

-

8

-

0

USB_WAKEN

70

32059L–AVR32–01/2012

AT32UC3B

9.6.20

Name:

General Purpose Low-power Register 0/1

GPLP

Access Type:

Offset:

Reset Value:

Read/Write

0x200

0x00000000

31 30 29 28

DATA[31:24]

27 26 25 24

23

15

22

14

21

13

20

DATA[23:16]

19

12

DATA[15:8]

11

18

10

17

9

16

8

7 6 5 4 3 2 1 0

DATA[7:0]

These registers are general purpose 32-bit registers that are reset only by power-on-reset. Any other reset will keep the content of these registers untouched. User software can use these registers to save context variables in a very low power mode.

Two GPLP register are implemented in AT32UC3B.

71

32059L–AVR32–01/2012

AT32UC3B

10. Real Time Counter (RTC)

Rev: 2.3.1.1

10.1 Features

32-bit real-time counter with 16-bit prescaler

Clocked from RC oscillator or 32KHz oscillator

Long delays

– Max timeout 272years

High resolution: Max count frequency 16KHz

Extremely low power consumption

Available in all sleep modes except Static

Interrupt on wrap

10.2 Overview

The Real Time Counter (RTC) enables periodic interrupts at long intervals, or accurate measurement of real-time sequences. The RTC is fed from a 16-bit prescaler, which is clocked from the system RC oscillator or the 32KHz crystal oscillator. Any tapping of the prescaler can be selected as clock source for the RTC, enabling both high resolution and long timeouts. The prescaler cannot be written directly, but can be cleared by the user.

The RTC can generate an interrupt when the counter wraps around the value stored in the top register (TOP), producing accurate periodic interrupts.

10.3 Block Diagram

Figure 10-1. Real Time Counter Block Diagram

CTRL

TOP

CLK_32

CLK32

1

RCSYS

0

EN PSEL

16-bit Prescaler

32-bit counter TOPI

IRQ

VAL

10.4 Product Dependencies

In order to use this module, other parts of the system must be configured correctly, as described below.

72

32059L–AVR32–01/2012

AT32UC3B

10.4.1

10.4.2

10.4.3

10.4.4

Power Management

The RTC remains operating in all sleep modes except Static mode. Interrupts are not available in DeepStop mode.

Clocks

The RTC can use the system RC oscillator as clock source. This oscillator is always enabled whenever this module is active. Please refer to the Electrical Characteristics chapter for the characteristic frequency of this oscillator (f

RC

).

The RTC can also use the 32 KHz crystal oscillator as clock source. This oscillator must be enabled before use. Please refer to the Power Manager chapter for details.

The clock for the RTC bus interface (CLK_RTC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the

RTC before disabling the clock, to avoid freezing the RTC in an undefined state.

Interrupts

The RTC interrupt request line is connected to the interrupt controller. Using the RTC interrupt requires the interrupt controller to be programmed first.

Debug Operation

The RTC prescaler is frozen during debug operation, unless the OCD system keeps peripherals running in debug operation.

10.5 Functional Description

10.5.1

10.5.1.1

RTC Operation

Source clock

The RTC is enabled by writing a one to the Enable bit in the Control Register (CTRL.EN). The

16-bit prescaler will then increment on the selected clock. The prescaler cannot be read or written, but it can be reset by writing a one to the Prescaler Clear bit in CTRL register (CTRL.PCLR).

The 32KHz Oscillator Select bit in CTRL register (CTRL.CLK32) selects either the RC oscillator or the 32 KHz oscillator as clock source (defined as INPUT in the formula below) for the prescaler.

The Prescale Select field in CTRL register (CTRL.PSEL) selects the prescaler tapping, selecting the source clock for the RTC:

f

RTC

=

f

INPUT

2

( )

10.5.1.2

Counter operation

When enabled, the RTC will increment until it reaches TOP, and then wraps to 0x0. The status bit TOPI in Interrupt Status Register (ISR) is set to one when this occurs. From 0x0 the counter will count TOP+1 cycles of the source clock before it wraps back to 0x0.

73

32059L–AVR32–01/2012

AT32UC3B

10.5.1.3

10.5.1.4

10.5.1.5

RTC interrupt

The RTC interrupt is enabled by writing a one to the Top Interrupt bit in the Interrupt Enable Register (IER.TOPI), and is disabled by writing a one to the Top Interrupt bit in the Interrupt Disable

Register (IDR.TOPI). The Interrupt Mask Register (IMR) can be read to see whether or not the interrupt is enabled. If enabled, an interrupt will be generated if the TOPI bit in the Interrupt Status Register (ISR) is set. The TOPI bit in ISR can be cleared by writing a one to the TOPI bit in the Interrupt Clear Register (ICR.TOPI).

The RTC interrupt can wake the CPU from all sleep modes except DeepStop and Static modes.

RTC wakeup

The RTC can also wake up the CPU directly without triggering an interrupt when the ISR.TOPI

bit is set. In this case, the CPU will continue executing from the instruction following the sleep instruction.

This direct RTC wake-up is enabled by writing a one to the Wake Enable bit in the CTRL register

(CTRL.WAKEN). When the CPU wakes from sleep, the CTRL.WAKEN bit must be written to zero to clear the internal wake signal to the sleep controller, otherwise a new sleep instruction will have no effect.

The RTC wakeup is available in all sleep modes except Static mode. The RTC wakeup can be configured independently of the RTC interrupt.

Busy bit

The RTC count value can be read from or written to the Value register (VAL). Due to synchronization, continuous reading of the VAL register with the lowest prescaler setting will skip every other value.

Due to the crossing of clock domains, the RTC uses a few clock cycles to propagate the values stored in CTRL, TOP, and VAL to the RTC. The RTC Busy bit in CTRL (CTRL.BUSY) indicates that a register write is still going on and all writes to TOP, CTRL, and VAL will be discarded until the CTRL.BUSY bit goes low again.

74

32059L–AVR32–01/2012

AT32UC3B

10.6 User Interface

Table 10-1.

RTC Register Memory Map

Offset

0x00

0x04

0x08

0x10

0x14

0x18

0x1C

0x20

Register

Control Register

Value Register

Top Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Interrupt Status Register

Interrupt Clear Register

Register Name

CTRL

VAL

TOP

IER

IDR

IMR

ISR

ICR

Access

Read/Write

Read/Write

Read/Write

Write-only

Write-only

Read-only

Read-only

Write-only

Reset

0x00010000

0x00000000

0xFFFFFFFF

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

32059L–AVR32–01/2012

75

AT32UC3B

10.6.1

Control Register

Name: CTRL

Access Type:

Offset:

Reset Value:

Read/Write

0x00

0x00010000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

11 15

-

14

-

13

-

12

-

7

-

6

-

5

-

4

BUSY

3

CLK32

2

WAKEN

• CLKEN: Clock Enable

1: The clock is enabled.

0: The clock is disabled.

• PSEL: Prescale Select

Selects prescaler bit PSEL as source clock for the RTC.

• BUSY: RTC Busy

This bit is set when the RTC is busy and will discard writes to TOP, VAL, and CTRL.

This bit is cleared when the RTC accepts writes to TOP, VAL, and CTRL.

• CLK32: 32 KHz Oscillator Select

1: The RTC uses the 32 KHz oscillator as clock source.

0: The RTC uses the RC oscillator as clock source.

• WAKEN: Wakeup Enable

1: The RTC wakes up the CPU from sleep modes.

0: The RTC does not wake up the CPU from sleep modes.

• PCLR: Prescaler Clear

Writing a one to this bit clears the prescaler.

Writing a zero to this bit has no effect.

This bit always reads as zero.

• EN: Enable

1: The RTC is enabled.

0: The RTC is disabled.

26

-

18

-

10

PSEL

1

PCLR

25

-

17

-

9

24

-

16

CLKEN

8

0

EN

76

32059L–AVR32–01/2012

AT32UC3B

10.6.2

Value Register

Name: VAL

Access Type:

Offset:

Reset Value:

Read/Write

0x04

0x00000000

31

23

30

22

29

21

28

VAL[31:24]

27

20

VAL[23:16]

19

15 14 13 12

VAL[15:8]

11

7 6 5 4 3

VAL[7:0]

• VAL[31:0]: RTC Value

This value is incremented on every rising edge of the source clock.

10

2

26

18

9

1

25

17

8

0

24

16

77

32059L–AVR32–01/2012

AT32UC3B

10.6.3

Top Register

Name: TOP

Access Type:

Offset:

Reset Value:

Read/Write

0x08

0xFFFFFFFF

31

23

30

22

15 14 13

7 6

• VAL[31:0]: RTC Top Value

VAL wraps at this value.

5

29

21

28

VAL[31:24]

27

20

VAL[23:16]

19

12

VAL[15:8]

11

4 3

VAL[7:0]

10

2

26

18

9

1

25

17

8

0

24

16

78

32059L–AVR32–01/2012

AT32UC3B

10.6.4

Interrupt Enable Register

Name: IER

Access Type:

Offset:

Reset Value:

Write-only

0x10

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

-

7

-

6

-

5

-

4

-

3

-

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will set the corresponding bit in IMR.

2

-

10

-

26

-

18

-

1

-

9

-

25

-

17

-

8

-

0

TOPI

24

-

16

-

79

32059L–AVR32–01/2012

AT32UC3B

10.6.5

Interrupt Disable Register

Name: IDR

Access Type:

Offset:

Reset Value:

Write-only

0x14

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

-

7

-

6

-

5

-

4

-

3

-

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will clear the corresponding bit in IMR.

2

-

10

-

26

-

18

-

1

-

9

-

25

-

17

-

8

-

0

TOPI

24

-

16

-

80

32059L–AVR32–01/2012

AT32UC3B

10.6.6

Interrupt Mask Register

Name: IMR

Access Type:

Offset:

Reset Value:

Read-only

0x18

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

-

7

-

6

-

5

-

4

-

3

-

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

A bit in this register is cleared when the corresponding bit in IDR is written to one.

A bit in this register is set when the corresponding bit in IER is written to one.

2

-

10

-

26

-

18

-

1

-

9

-

25

-

17

-

8

-

0

TOPI

24

-

16

-

81

32059L–AVR32–01/2012

AT32UC3B

10.6.7

Interrupt Status Register

Name: ISR

Access Type:

Offset:

Reset Value:

Read-only

0x1C

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

15

-

14

-

13

-

12

-

11

-

7

-

6

-

5

-

4

-

3

-

• TOPI: Top Interrupt

This bit is set when VAL has wrapped at its top value.

This bit is cleared when the corresponding bit in ICR is written to one.

27

-

19

-

2

-

10

-

26

-

18

-

1

-

9

-

25

-

17

-

8

-

0

TOPI

24

-

16

-

82

32059L–AVR32–01/2012

AT32UC3B

10.6.8

Interrupt Clear Register

Name: ICR

Access Type:

Offset:

Reset Value:

Write-only

0x20

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

25

-

17

-

15

-

14

-

13

-

12

-

11

-

10

-

9

-

8

-

7

-

6

-

5

-

4

-

3

-

2

-

1

-

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request.

0

TOPI

24

-

16

-

83

32059L–AVR32–01/2012

AT32UC3B

11. Watchdog Timer (WDT)

Rev: 2.3.1.1

11.1 Features

Watchdog timer counter with 32-bit prescaler

Clocked from the system RC oscillator (RCSYS)

11.2 Overview

The Watchdog Timer (WDT) has a prescaler generating a time-out period. This prescaler is clocked from the RC oscillator. The watchdog timer must be periodically reset by software within the time-out period, otherwise, the device is reset and starts executing from the boot vector. This allows the device to recover from a condition that has caused the system to be unstable.

11.3 Block Diagram

Figure 11-1. WDT Block Diagram

CLR

RCSYS

32-bit

Prescaler

Watchdog

Detector

Watchdog Reset

EN

CTRL

11.4 Product Dependencies

In order to use this module, other parts of the system must be configured correctly, as described below.

11.4.1

11.4.2

11.4.3

Power Management

When the WDT is enabled, the WDT remains clocked in all sleep modes, and it is not possible to enter Static mode.

Clocks

The WDT can use the system RC oscillator (RCSYS) as clock source. This oscillator is always enabled whenever these modules are active. Please refer to the Electrical Characteristics chapter for the characteristic frequency of this oscillator (f

RC

).

Debug Operation

The WDT prescaler is frozen during debug operation, unless the On-Chip Debug (OCD) system keeps peripherals running in debug operation.

84

32059L–AVR32–01/2012

AT32UC3B

11.5 Functional Description

The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.EN). This also enables the system RC clock (CLK_RCSYS) for the prescaler. The Prescale Select field

(PSEL) in the CTRL register selects the watchdog time-out period:

T

WDT

= 2

(PSEL+1)

/ f

RC

The next time-out period will begin as soon as the watchdog reset has occurred and count down during the reset sequence. Care must be taken when selecting the PSEL field value so that the time-out period is greater than the startup time of the chip, otherwise a watchdog reset can reset the chip before any code has been run.

To avoid accidental disabling of the watchdog, the CTRL register must be written twice, first with the KEY field set to 0x55, then 0xAA without changing the other bits. Failure to do so will cause the write operation to be ignored, and the CTRL register value will not change.

The Clear register (CLR) must be written with any value with regular intervals shorter than the watchdog time-out period. Otherwise, the device will receive a soft reset, and the code will start executing from the boot vector.

When the WDT is enabled, it is not possible to enter Static mode. Attempting to do so will result in entering Shutdown mode, leaving the WDT operational.

11.6 User Interface

Table 11-1.

WDT Register Memory Map

Offset Register

0x00

0x04

Control Register

Clear Register

Register Name

CTRL

CLR

Access

Read/Write

Write-only

Reset

0x00000000

0x00000000

85

32059L–AVR32–01/2012

11.6.1

Control Register

Name: CTRL

Access Type:

Offset:

Reset Value:

Read/Write

0x00

0x00000000

31 30 29 28 27 26 25

KEY

23

-

15

-

22

-

14

-

21

-

13

-

20

-

12

19

-

11

18

-

10

PSEL

17

-

9

7

-

6

-

5

-

4

-

3

-

2

-

1

-

KEY: Write protection key

This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective.

This field always reads as zero.

PSEL: Prescale Select

PSEL is used as watchdog timeout period.

EN: WDT Enable

1: WDT is enabled.

0: WDT is disabled.

AT32UC3B

24

16

-

8

0

EN

86

32059L–AVR32–01/2012

AT32UC3B

11.6.2

Clear Register

Name: CLR

Access Type:

Offset:

Reset Value:

Write-only

0x04

0x00000000

31

23

30

22

29

21

28

CLR[31:24]

27

20

CLR[23:16]

19

26

18

25

17

24

16

15 14 13 12

CLR[15:8]

11 10 9 8

7 6 5 4 3 2 1 0

CLR[7:0]

• CLR:

Writing periodically any value to this field when the WDT is enabled, within the watchdog time-out period, will prevent a watchdog reset.

This field always reads as zero.

87

32059L–AVR32–01/2012

AT32UC3B

12. Interrupt Controller (INTC)

Rev: 1.0.1.5

12.1 Features

Autovectored low latency interrupt service with programmable priority

– 4 priority levels for regular, maskable interrupts

– One Non-Maskable Interrupt

Up to 64 groups of interrupts with up to 32 interrupt requests in each group

12.2 Overview

The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an interrupt request and an autovector to the CPU. The AVR32 architecture supports 4 priority levels for regular, maskable interrupts, and a Non-Maskable Interrupt (NMI).

The INTC supports up to 64 groups of interrupts. Each group can have up to 32 interrupt request lines, these lines are connected to the peripherals. Each group has an Interrupt Priority Register

(IPR) and an Interrupt Request Register (IRR). The IPRs are used to assign a priority level and an autovector to each group, and the IRRs are used to identify the active interrupt request within each group. If a group has only one interrupt request line, an active interrupt group uniquely identifies the active interrupt request line, and the corresponding IRR is not needed. The INTC also provides one Interrupt Cause Register (ICR) per priority level. These registers identify the group that has a pending interrupt of the corresponding priority level. If several groups have a pending interrupt of the same level, the group with the lowest number takes priority.

12.3 Block Diagram

Figure 12-1

gives an overview of the INTC. The grey boxes represent registers that can be accessed via the user interface. The interrupt requests from the peripherals (IREQn) and the

NMI are input on the left side of the figure. Signals to and from the CPU are on the right side of the figure.

88

32059L–AVR32–01/2012

AT32UC3B

Figure 12-1. INTC Block Diagram

Interrupt Controller

NMIREQ

IREQ63

IREQ34

IREQ33

IREQ32

IREQ31

IREQ2

IREQ0

OR

IRRn

GrpReqN

.

.

.

ValReqN

Request

Masking

IPRn

.

.

.

ValReq1

OR

GrpReq1

IPR1

IRR1

ValReq0

OR

GrpReq0

IPR0

IRR0

IRR Registers

INT_level, offset

INT_level, offset

INT_level, offset

IPR Registers

.

.

.

ICR Registers

CPU

Masks

SREG

Masks

I[3-0]M

GM

INTLEVEL

AUTOVECTOR

12.4 Product Dependencies

In order to use this module, other parts of the system must be configured correctly, as described below.

12.4.1

12.4.2

12.4.3

Power Management

If the CPU enters a sleep mode that disables CLK_SYNC, the INTC will stop functioning and resume operation after the system wakes up from sleep mode.

Clocks

The clock for the INTC bus interface (CLK_INTC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager.

The INTC sampling logic runs on a clock which is stopped in any of the sleep modes where the system RC oscillator is not running. This clock is referred to as CLK_SYNC. This clock is enabled at reset, and only turned off in sleep modes where the system RC oscillator is stopped.

Debug Operation

When an external debugger forces the CPU into debug mode, the INTC continues normal operation.

12.5 Functional Description

All of the incoming interrupt requests (IREQs) are sampled into the corresponding Interrupt

Request Register (IRR). The IRRs must be accessed to identify which IREQ within a group that is active. If several IREQs within the same group are active, the interrupt service routine must prioritize between them. All of the input lines in each group are logically ORed together to form the GrpReqN lines, indicating if there is a pending interrupt in the corresponding group.

The Request Masking hardware maps each of the GrpReq lines to a priority level from INT0 to

INT3 by associating each group with the Interrupt Level (INTLEVEL) field in the corresponding

89

32059L–AVR32–01/2012

AT32UC3B

12.5.1

12.5.2

12.5.3

Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the

CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not masked by the CPU status register, gets its corresponding ValReq line asserted.

Masking of the interrupt requests is done based on five interrupt mask bits of the CPU status register, namely Interrupt Level 3 Mask (I3M) to Interrupt Level 0 Mask (I0M), and Global Interrupt Mask (GM). An interrupt request is masked if either the GM or the corresponding interrupt level mask bit is set.

The Prioritizer hardware uses the ValReq lines and the INTLEVEL field in the IPRs to select the pending interrupt of the highest priority. If an NMI interrupt request is pending, it automatically gets the highest priority of any pending interrupt. If several interrupt groups of the highest pending interrupt level have pending interrupts, the interrupt group with the lowest number is selected.

The INTLEVEL and handler autovector offset (AUTOVECTOR) of the selected interrupt are transmitted to the CPU for interrupt handling and context switching. The CPU does not need to know which interrupt is requesting handling, but only the level and the offset of the handler address. The IRR registers contain the interrupt request lines of the groups and can be read via user interface registers for checking which interrupts of the group are actually active.

The delay through the INTC from the peripheral interrupt request is set until the interrupt request to the CPU is set is three cycles of CLK_SYNC.

Non-Maskable Interrupts

A NMI request has priority over all other interrupt requests. NMI has a dedicated exception vector address defined by the AVR32 architecture, so AUTOVECTOR is undefined when

INTLEVEL indicates that an NMI is pending.

CPU Response

When the CPU receives an interrupt request it checks if any other exceptions are pending. If no exceptions of higher priority are pending, interrupt handling is initiated. When initiating interrupt handling, the corresponding interrupt mask bit is set automatically for this and lower levels in status register. E.g, if an interrupt of level 3 is approved for handling, the interrupt mask bits I3M,

I2M, I1M, and I0M are set in status register. If an interrupt of level 1 is approved, the masking bits I1M and I0M are set in status register. The handler address is calculated by logical OR of the AUTOVECTOR to the CPU system register Exception Vector Base Address (EVBA). The

CPU will then jump to the calculated address and start executing the interrupt handler.

Setting the interrupt mask bits prevents the interrupts from the same and lower levels to be passed through the interrupt controller. Setting of the same level mask bit prevents also multiple requests of the same interrupt to happen.

It is the responsibility of the handler software to clear the interrupt request that caused the interrupt before returning from the interrupt handler. If the conditions that caused the interrupt are not cleared, the interrupt request remains active.

Clearing an Interrupt Request

Clearing of the interrupt request is done by writing to registers in the corresponding peripheral module, which then clears the corresponding NMIREQ/IREQ signal.

The recommended way of clearing an interrupt request is a store operation to the controlling peripheral register, followed by a dummy load operation from the same register. This causes a

90

32059L–AVR32–01/2012

AT32UC3B

pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is cleared.

32059L–AVR32–01/2012

91

AT32UC3B

12.6 User Interface

Table 12-1.

INTC Register Memory Map

Offset

0x000

0x004

...

0x0FC

0x100

0x104

...

0x1FC

0x200

0x204

0x208

0x20C

Register

Interrupt Priority Register 0

Interrupt Priority Register 1

...

Interrupt Priority Register 63

Interrupt Request Register 0

Interrupt Request Register 1

...

Interrupt Request Register 63

Interrupt Cause Register 3

Interrupt Cause Register 2

Interrupt Cause Register 1

Interrupt Cause Register 0

Register Name

IPR0

IPR1

...

IPR63

IRR0

IRR1

...

IRR63

ICR3

ICR2

ICR1

ICR0

Access

Read/Write

Read/Write

...

Read/Write

Read-only

Read-only

...

Read-only

Read-only

Read-only

Read-only

Read-only

Reset

0x00000000

0x00000000

...

0x00000000

N/A

N/A

...

N/A

N/A

N/A

N/A

N/A

92

32059L–AVR32–01/2012

AT32UC3B

12.6.1

Name:

Interrupt Priority Registers

IPR0...IPR63

Access Type: Read/Write

Reset Value:

0x00000000

31

23

-

15

-

INTLEVEL

30

22

-

14

-

29

-

21

-

13

28

-

20

-

12

27

-

19

-

26

-

18

-

25

-

17

-

9 11 10

AUTOVECTOR[13:8]

7 6 5 4 3

AUTOVECTOR[7:0]

2 1 0

• INTLEVEL: Interrupt Level

Indicates the EVBA-relative offset of the interrupt handler of the corresponding group:

00: INT0: Lowest priority

01: INT1

10: INT2

11: INT3: Highest priority

• AUTOVECTOR: Autovector Address

Handler offset is used to give the address of the interrupt handler. The least significant bit should be written to zero to give halfword alignment.

24

-

16

-

8

93

32059L–AVR32–01/2012

AT32UC3B

12.6.2

Name:

Interrupt Request Registers

IRR0...IRR63

Access Type: Read-only

Offset: 0x0FF - 0x1FC

Reset Value:

N/A

31 30 29 28 27 26 25 24

IRR[32*x+31] IRR[32*x+30] IRR[32*x+29] IRR[32*x+28] IRR[32*x+27] IRR[32*x+26] IRR[32*x+25] IRR[32*x+24]

23 22 21 20 19 18 17 16

IRR[32*x+23] IRR[32*x+22] IRR[32*x+21] IRR[32*x+20] IRR[32*x+19] IRR[32*x+18] IRR[32*x+17] IRR[32*x+16]

15 14 13 12 11 10 9

IRR[32*x+15] IRR[32*x+14] IRR[32*x+13] IRR[32*x+12] IRR[32*x+11] IRR[32*x+10] IRR[32*x+9]

8

IRR[32*x+8]

7

IRR[32*x+7]

6

IRR[32*x+6]

5

IRR[32*x+5]

4

IRR[32*x+4]

3

IRR[32*x+3]

2

IRR[32*x+2]

1

IRR[32*x+1]

0

IRR[32*x+0]

• IRR: Interrupt Request line

This bit is cleared when no interrupt request is pending on this input request line.

This bit is set when an interrupt request is pending on this input request line.

The are 64 IRRs, one for each group. Each IRR has 32 bits, one for each possible interrupt request, for a total of 2048 possible input lines. The IRRs are read by the software interrupt handler in order to determine which interrupt request is pending. The

IRRs are sampled continuously, and are read-only.

94

32059L–AVR32–01/2012

AT32UC3B

12.6.3

Name:

Interrupt Cause Registers

ICR0...ICR3

Access Type: Read-only

Reset Value:

N/A

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

25

-

17

-

24

-

16

-

15

-

14

-

13

-

12

-

11

-

10

-

9

-

8

-

7

-

6

-

5 4 3

CAUSE

2 1 0

• CAUSE: Interrupt Group Causing Interrupt of Priority n

ICRn identifies the group with the highest priority that has a pending interrupt of level n. This value is only defined when at least one interrupt of level n is pending.

95

32059L–AVR32–01/2012

AT32UC3B

12.7 Interrupt Request Signal Map

The various modules may output Interrupt request signals. These signals are routed to the Interrupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64 groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt signals in the same group share the same autovector address and priority level. Refer to the documentation for the individual submodules for a description of the semantics of the different interrupt requests.

The interrupt request signals are connected to the INTC as follows.

4

5

2

3

0

1

8

9

6

7

4

5

2

3

0

1

6

0

4

5

2

3

0

1

Table 12-2.

Interrupt Request Signal Map

Group Line Module

0

1

2

3

4

5

0

0

AVR32 UC CPU with optional MPU and optional OCD

External Interrupt Controller

External Interrupt Controller

External Interrupt Controller

External Interrupt Controller

External Interrupt Controller

External Interrupt Controller

External Interrupt Controller

External Interrupt Controller

Real Time Counter

Power Manager

General Purpose Input/Output Controller

General Purpose Input/Output Controller

General Purpose Input/Output Controller

General Purpose Input/Output Controller

General Purpose Input/Output Controller

General Purpose Input/Output Controller

Peripheral DMA Controller

Peripheral DMA Controller

Peripheral DMA Controller

Peripheral DMA Controller

Peripheral DMA Controller

Peripheral DMA Controller

Peripheral DMA Controller

Flash Controller

Universal Synchronous/Asynchronous

Receiver/Transmitter

Signal

SYSREG COMPARE

RTC

PM

GPIO 0

GPIO 1

GPIO 2

GPIO 3

GPIO 4

GPIO 5

EIC 0

EIC 1

EIC 2

EIC 3

EIC 4

EIC 5

EIC 6

EIC 7

PDCA 0

PDCA 1

PDCA 2

PDCA 3

PDCA 4

PDCA 5

PDCA 6

FLASHC

USART0

96

32059L–AVR32–01/2012

32059L–AVR32–01/2012

Table 12-2.

Interrupt Request Signal Map

6

7

14

15

17

18

9

11

12

13

0

0

2

0

0

1

0

0

0

0

0

0

Universal Synchronous/Asynchronous

Receiver/Transmitter

Universal Synchronous/Asynchronous

Receiver/Transmitter

Serial Peripheral Interface

Two-wire Interface

Pulse Width Modulation Controller

Synchronous Serial Controller

Timer/Counter

Timer/Counter

Timer/Counter

Analog to Digital Converter

USB 2.0 Interface

Audio Bitstream DAC

AT32UC3B

USART1

USART2

SPI

TWI

PWM

SSC

TC0

TC1

TC2

ADC

USBB

ABDAC

97

AT32UC3B

13. External Interrupt Controller (EIC)

Rev: 2.3.1.0

13.1 Features

Dedicated interrupt request for each interrupt

Individually maskable interrupts

Interrupt on rising or falling edge

Interrupt on high or low level

Asynchronous interrupts for sleep modes without clock

Filtering of interrupt lines

Maskable NMI interrupt

Keypad scan support

13.2 Overview

The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. Each external interrupt has its own interrupt request and can be individually masked. Each external interrupt can generate an interrupt on rising or falling edge, or high or low level. Every interrupt input has a configurable filter to remove spikes from the interrupt source. Every interrupt pin can also be configured to be asynchronous in order to wake up the part from sleep modes where the

CLK_SYNC clock has been disabled.

A Non-Maskable Interrupt (NMI) is also supported. This has the same properties as the other external interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any other interrupt mode.

The EIC can wake up the part from sleep modes without triggering an interrupt. In this mode, code execution starts from the instruction following the sleep instruction.

The External Interrupt Controller has support for keypad scanning for keypads laid out in rows and columns. Columns are driven by a separate set of scanning outputs, while rows are sensed by the external interrupt lines. The pressed key will trigger an interrupt, which can be identified through the user registers of the module.

98

32059L–AVR32–01/2012

AT32UC3B

13.3 Block Diagram

Figure 13-1. EIC Block Diagram

E N

D I S

E X T IN T n

N M I

E n a b le

C T R L

L E V E L

M O D E

E D G E

P o la r it y c o n t r o l

F I L T E R

F ilt e r

A S Y N C

A s y n c h r o n u s d e t e c t o r

L E V E L

M O D E

E D G E

E d g e / L e v e l

D e t e c t o r

I C R

C T R L

I N T n

I S R

I E R

ID R

M a s k

I M R

I R Q n

W a k e d e t e c t

E I C _ W A K E

C L K _ S Y N C

C L K _ R C S Y S

P r e s c a le r

P R E S C

S h if t e r

E N

S C A N

P I N

S C A N m

13.4 I/O Lines Description

Table 13-1.

I/O Lines Description

Pin Name Pin Description

NMI

EXTINTn

SCANm

Non-Maskable Interrupt

External Interrupt

Keypad scan pin m

Type

Input

Input

Output

13.5 Product Dependencies

In order to use this module, other parts of the system must be configured correctly, as described below.

13.5.1

13.5.2

I/O Lines

The external interrupt pins (EXTINTn and NMI) are multiplexed with I/O lines. To generate an external interrupt from an external source the source pin must be configured as an input pins by the I/O Controller. It is also possible to trigger the interrupt by driving these pins from registers in the I/O Controller, or another peripheral output connected to the same pin.

Power Management

All interrupts are available in all sleep modes as long as the EIC module is powered. However, in sleep modes where CLK_SYNC is stopped, the interrupt must be configured to asynchronous mode.

99

32059L–AVR32–01/2012

AT32UC3B

13.5.3

13.5.4

13.5.5

Clocks

The clock for the EIC bus interface (CLK_EIC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager.

The filter and synchronous edge/level detector runs on a clock which is stopped in any of the sleep modes where the system RC oscillator is not running. This clock is referred to as

CLK_SYNC. Refer to the Module Configuration section at the end of this chapter for details.

The Keypad scan function operates on the system RC oscillator clock CLK_RCSYS.

Interrupts

The external interrupt request lines are connected to the interrupt controller. Using the external interrupts requires the interrupt controller to be programmed first.

Using the Non-Maskable Interrupt does not require the interrupt controller to be programmed.

Debug Operation

The EIC is frozen during debug operation, unless the OCD system keeps peripherals running during debug operation.

13.6 Functional Description

13.6.1

External Interrupts

The external interrupts are not enabled by default, allowing the proper interrupt vectors to be set up by the CPU before the interrupts are enabled.

Each external interrupt INTn can be configured to produce an interrupt on rising or falling edge, or high or low level. External interrupts are configured by the MODE, EDGE, and LEVEL registers. Each interrupt n has a bit INTn in each of these registers. Writing a zero to the INTn bit in the MODE register enables edge triggered interrupts, while writing a one to the bit enables level triggered interrupts.

If INTn is configured as an edge triggered interrupt, writing a zero to the INTn bit in the EDGE register will cause the interrupt to be triggered on a falling edge on EXTINTn, while writing a one to the bit will cause the interrupt to be triggered on a rising edge on EXTINTn.

If INTn is configured as a level triggered interrupt, writing a zero to the INTn bit in the LEVEL register will cause the interrupt to be triggered on a low level on EXTINTn, while writing a one to the bit will cause the interrupt to be triggered on a high level on EXTINTn.

Each interrupt has a corresponding bit in each of the interrupt control and status registers. Writing a one to the INTn bit in the Interrupt Enable Register (IER) enables the external interrupt from pin EXTINTn to propagate from the EIC to the interrupt controller, while writing a one to

INTn bit in the Interrupt Disable Register (IDR) disables this propagation. The Interrupt Mask

Register (IMR) can be read to check which interrupts are enabled. When an interrupt triggers, the corresponding bit in the Interrupt Status Register (ISR) will be set. This bit remains set until a one is written to the corresponding bit in the Interrupt Clear Register (ICR) or the interrupt is disabled.

Writing a one to the INTn bit in the Enable Register (EN) enables the external interrupt on pin

EXTINTn, while writing a one to INTn bit in the Disable Register (DIS) disables the external interrupt. The Control Register (CTRL) can be read to check which interrupts are enabled. If a bit in the CTRL register is set, but the corresponding bit in IMR is not set, an interrupt will not propa-

100

32059L–AVR32–01/2012

AT32UC3B

13.6.2

gate to the interrupt controller. However, the corresponding bit in ISR will be set, and

EIC_WAKE will be set.

If the CTRL.INTn bit is zero, then the corresponding bit in ISR will always be zero. Disabling an external interrupt by writing to the DIS.INTn bit will clear the corresponding bit in ISR.

Synchronization and Filtering of External Interrupts

In synchronous mode the pin value of the EXTINTn pin is synchronized to CLK_SYNC, so spikes shorter than one CLK_SYNC cycle are not guaranteed to produce an interrupt. The synchronization of the EXTINTn to CLK_SYNC will delay the propagation of the interrupt to the

interrupt controller by two cycles of CLK_SYNC, see Figure 13-2 on page 101

and

Figure 13-3 on page 101 for examples (FILTER off).

It is also possible to apply a filter on EXTINTn by writing a one to INTn bit in the FILTER register.

This filter is a majority voter, if the condition for an interrupt is true for more than one of the latest three cycles of CLK_SYNC the interrupt will be set. This will additionally delay the propagation of the interrupt to the interrupt controller by one or two cycles of CLK_SYNC, see

Figure 13-2 on page 101 and Figure 13-3 on page 101 for examples (FILTER on).

Figure 13-2. Timing Diagram, Synchronous Interrupts, High Level or Rising Edge

CLK_SYNC

EXTINTn/NMI

ISR.INTn:

FILTER off

ISR.INTn:

FILTER on

Figure 13-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge

CLK_SYNC

EXTINTn/NMI

ISR.INTn:

FILTER off

ISR.INTn:

FILTER on

101

32059L–AVR32–01/2012

AT32UC3B

13.6.3

13.6.4

Non-Maskable Interrupt

The NMI supports the same features as the external interrupts, and is accessed through the same registers. The description in

Section 13.6.1

should be followed, accessing the NMI bit

instead of the INTn bits.

The NMI is non-maskable within the CPU in the sense that it can interrupt any other execution mode. Still, as for the other external interrupts, the actual NMI input can be enabled and disabled by accessing the registers in the EIC.

Asynchronous Interrupts

Each external interrupt can be made asynchronous by writing a one to INTn in the ASYNC register. This will route the interrupt signal through the asynchronous path of the module. All edge interrupts will be interpreted as level interrupts and the filter is disabled. If an interrupt is configured as edge triggered interrupt in asynchronous mode, a zero in EDGE.INTn will be interpreted as low level, and a one in EDGE.INTn will be interpreted as high level.

EIC_WAKE will be set immediately after the source triggers the interrupt, while the corresponding bit in ISR and the interrupt to the interrupt controller will be set on the next rising edge of

CLK_SYNC. Please refere to

Figure 13-4 on page 102

for details.

When CLK_SYNC is stopped only asynchronous interrupts remain active, and any short spike on this interrupt will wake up the device. EIC_WAKE will restart CLK_SYNC and ISR will be updated on the first rising edge of CLK_SYNC.

Figure 13-4. Timing Diagram, Asynchronous Interrupts

CLK_SYNC CLK_SYNC

EXTINTn/NMI EXTINTn/NMI

13.6.5

Wakeup

ISR.INTn: rising EDGE or high

LEVEL

EIC_WAKE: rising EDGE or high

LEVEL

ISR.INTn: rising EDGE or high

LEVEL

EIC_WAKE: rising EDGE or high

LEVEL

The external interrupts can be used to wake up the part from sleep modes. The wakeup can be interpreted in two ways. If the corresponding bit in IMR is one, then the execution starts at the interrupt handler for this interrupt. If the bit in IMR is zero, then the execution starts from the next instruction after the sleep instruction.

102

32059L–AVR32–01/2012

AT32UC3B

13.6.6

Keypad scan support

The External Interrupt Controller also includes support for keypad scanning. The keypad scan feature is compatible with keypads organized as rows and columns, where a row is shorted against a column when a key is pressed.

The rows should be connected to the external interrupt pins with pull-ups enabled in the I/O Controller. These external interrupts should be enabled as low level or falling edge interrupts. The columns should be connected to the available scan pins. The I/O Controller must be configured to let the required scan pins be controlled by the EIC. Unused external interrupt or scan pins can be left controlled by the I/O Controller or other peripherals.

The Keypad Scan function is enabled by writing SCAN.EN to 1, which starts the keypad scan counter. The SCAN outputs are tri-stated, except SCAN[0], which is driven to zero. After

2

(SCAN.PRESC+1)

RC clock cycles this pattern is left shifted, so that SCAN[1] is driven to zero while the other outputs are tri-stated. This sequence repeats infinitely, wrapping from the most significant SCAN pin to SCAN[0].

When a key is pressed, the pulled-up row is driven to zero by the column, and an external interrupt triggers. The scanning stops, and the software can then identify the key pressed by the interrupt status register and the SCAN.PINS value.

The scanning stops whenever there is an active interrupt request from the EIC to the CPU.

When the CPU clears the interrupt flags, scanning resumes.

103

32059L–AVR32–01/2012

AT32UC3B

13.7 User Interface

Table 13-2.

EIC Register Memory Map

0x01C

0x020

0x024

0x028

0x2C

0x030

0x034

0x038

Offset

0x000

0x004

0x008

0x00C

0x010

0x014

0x018

Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Interrupt Status Register

Interrupt Clear Register

Mode Register

Edge Register

Level Register

Filter Register

Test Register

Asynchronous Register

Scan Register

Enable Register

Disable Register

Control Register

Register Name

IER

IDR

IMR

ISR

ICR

MODE

EDGE

LEVEL

FILTER

TEST

ASYNC

SCAN

EN

DIS

CTRL

Access

Write-only

Write-only

Read-only

Read-only

Write-only

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Write-only

Write-only

Read-only

Reset

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

104

32059L–AVR32–01/2012

AT32UC3B

13.7.1

Interrupt Enable Register

Name: IER

Access Type:

Write-only

Offset: 0x000

Reset Value: 0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

15

-

14

-

13

-

12

-

11

-

7

INT7

6

INT6

5

INT5

4

INT4

• INTn: External Interrupt n

Writing a zero to this bit has no effect.

Writing a one to this bit will set the corresponding bit in IMR.

• NMI: Non-Maskable Interrupt

Writing a zero to this bit has no effect.

Writing a one to this bit will set the corresponding bit in IMR.

3

INT3

27

-

19

-

10

-

2

INT2

26

-

18

-

9

-

1

INT1

25

-

17

-

8

NMI

0

INT0

24

-

16

-

105

32059L–AVR32–01/2012

AT32UC3B

13.7.2

Interrupt Disable Register

Name: IDR

Access Type:

Write-only

Offset: 0x004

Reset Value: 0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

15

-

14

-

13

-

12

-

11

-

7

INT7

6

INT6

5

INT5

4

INT4

• INTn: External Interrupt n

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the corresponding bit in IMR.

• NMI: Non-Maskable Interrupt

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the corresponding bit in IMR.

3

INT3

27

-

19

-

10

-

2

INT2

26

-

18

-

9

-

1

INT1

25

-

17

-

8

NMI

0

INT0

24

-

16

-

106

32059L–AVR32–01/2012

AT32UC3B

13.7.3

Interrupt Mask Register

Name: IMR

Access Type:

Read-only

Offset: 0x008

Reset Value: 0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

15

-

14

-

13

-

12

-

11

-

7

INT7

6

INT6

5

INT5

4

INT4

3

INT3

• INTn: External Interrupt n

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

This bit is cleared when the corresponding bit in IDR is written to one.

This bit is set when the corresponding bit in IER is written to one.

• NMI: Non-Maskable Interrupt

0: The Non-Maskable Interrupt is disabled.

1: The Non-Maskable Interrupt is enabled.

This bit is cleared when the corresponding bit in IDR is written to one.

This bit is set when the corresponding bit in IER is written to one.

27

-

19

-

10

-

2

INT2

26

-

18

-

9

-

1

INT1

25

-

17

-

8

NMI

0

INT0

24

-

16

-

107

32059L–AVR32–01/2012

AT32UC3B

13.7.4

Interrupt Status Register

Name: ISR

Access Type:

Read-only

Offset: 0x00C

Reset Value: 0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

15

-

14

-

13

-

12

-

11

-

7

INT7

6

INT6

5

INT5

4

INT4

• INTn: External Interrupt n

0: An interrupt event has not occurred

1: An interrupt event has occurred

This bit is cleared by writing a one to the corresponding bit in ICR.

• NMI: Non-Maskable Interrupt

0: An interrupt event has not occurred

1: An interrupt event has occurred

This bit is cleared by writing a one to the corresponding bit in ICR.

3

INT3

27

-

19

-

10

-

2

INT2

26

-

18

-

9

-

1

INT1

25

-

17

-

8

NMI

0

INT0

24

-

16

-

108

32059L–AVR32–01/2012

AT32UC3B

13.7.5

Interrupt Clear Register

Name: ICR

Access Type:

Write-only

Offset: 0x010

Reset Value: 0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

15

-

14

-

13

-

12

-

11

-

7

INT7

6

INT6

5

INT5

4

INT4

• INTn: External Interrupt n

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the corresponding bit in ISR.

• NMI: Non-Maskable Interrupt

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the corresponding bit in ISR.

3

INT3

27

-

19

-

10

-

2

INT2

26

-

18

-

9

-

1

INT1

25

-

17

-

8

NMI

0

INT0

24

-

16

-

109

32059L–AVR32–01/2012

AT32UC3B

13.7.6

Mode Register

Name: MODE

Access Type:

Read/Write

Offset: 0x014

Reset Value: 0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

15

-

14

-

13

-

12

-

7

INT7

6

INT6

5

INT5

• INTn: External Interrupt n

0: The external interrupt is edge triggered.

1: The external interrupt is level triggered.

• NMI: Non-Maskable Interrupt

0: The Non-Maskable Interrupt is edge triggered.

1: The Non-Maskable Interrupt is level triggered.

4

INT4

28

-

20

-

11

-

3

INT3

27

-

19

-

10

-

2

INT2

26

-

18

-

9

-

1

INT1

25

-

17

-

8

NMI

0

INT0

24

-

16

-

110

32059L–AVR32–01/2012

AT32UC3B

13.7.7

Edge Register

Name: EDGE

Access Type:

Read/Write

Offset: 0x018

Reset Value: 0x00000000

31

-

30

-

29

-

28

-

23

-

15

-

22

-

14

-

21

-

13

-

20

-

12

-

7

INT7

6

INT6

5

INT5

4

INT4

• INTn: External Interrupt n

0: The external interrupt triggers on falling edge.

1: The external interrupt triggers on rising edge.

• NMI: Non-Maskable Interrupt

0: The Non-Maskable Interrupt triggers on falling edge.

1: The Non-Maskable Interrupt triggers on rising edge.

27

-

19

-

11

-

3

INT3

26

-

18

-

10

-

2

INT2

25

-

9

-

17

-

1

INT1

24

-

16

-

8

NMI

0

INT0

111

32059L–AVR32–01/2012

AT32UC3B

13.7.8

Level Register

Name: LEVEL

Access Type:

Read/Write

Offset: 0x01C

Reset Value: 0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

15

-

14

-

13

-

12

-

7

INT7

6

INT6

5

INT5

4

INT4

• INTn: External Interrupt n

0: The external interrupt triggers on low level.

1: The external interrupt triggers on high level.

• NMI: Non-Maskable Interrupt

0: The Non-Maskable Interrupt triggers on low level.

1: The Non-Maskable Interrupt triggers on high level.

28

-

20

-

11

-

3

INT3

27

-

19

-

10

-

2

INT2

26

-

18

-

9

-

1

INT1

25

-

17

-

8

NMI

0

INT0

24

-

16

-

112

32059L–AVR32–01/2012

AT32UC3B

13.7.9

Filter Register

Name: FILTER

Access Type:

Read/Write

Offset: 0x020

Reset Value: 0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

15

-

14

-

13

-

12

-

7

INT7

6

INT6

5

INT5

• INTn: External Interrupt n

0: The external interrupt is not filtered.

1: The external interrupt is filtered.

• NMI: Non-Maskable Interrupt

0: The Non-Maskable Interrupt is not filtered.

1: The Non-Maskable Interrupt is filtered.

4

INT4

28

-

20

-

11

-

3

INT3

27

-

19

-

10

-

2

INT2

26

-

18

-

9

-

1

INT1

25

-

17

-

8

NMI

0

INT0

24

-

16

-

113

32059L–AVR32–01/2012

AT32UC3B

13.7.10

Test Register

Name: TEST

Access Type:

Read/Write

Offset: 0x024

Reset Value: 0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

25

-

17

-

24

-

16

-

15

-

14

-

13

-

12

-

11

-

10

-

9

-

8

NMI

7

INT7

6

INT6

5

INT5

4

INT4

3

INT3

2

INT2

1

INT1

0

INT0

• TESTEN: Test Enable

0: This bit disables external interrupt test mode.

1: This bit enables external interrupt test mode.

• INTn: External Interrupt n

If TESTEN is 1, the value written to this bit will be the value to the interrupt detector and the value on the pad will be ignored.

• NMI: Non-Maskable Interrupt

If TESTEN is 1, the value written to this bit will be the value to the interrupt detector and the value on the pad will be ignored.

114

32059L–AVR32–01/2012

AT32UC3B

13.7.11

Asynchronous Register

Name: ASYNC

Access Type:

Read/Write

Offset: 0x028

Reset Value: 0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

15

-

14

-

13

-

12

-

11

-

7

INT7

6

INT6

5

INT5

4

INT4

• INTn: External Interrupt n

0: The external interrupt is synchronized to CLK_SYNC.

1: The external interrupt is asynchronous.

• NMI: Non-Maskable Interrupt

0: The Non-Maskable Interrupt is synchronized to CLK_SYNC

1: The Non-Maskable Interrupt is asynchronous.

3

INT3

27

-

19

-

10

-

2

INT2

26

-

18

-

9

-

1

INT1

25

-

17

-

8

NMI

0

INT0

24

-

16

-

115

32059L–AVR32–01/2012

13.7.12

Scan Register

Name: SCAN

Access Type:

Read/Write

Offset: 0x2C

Reset Value:

0x0000000

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

27

-

19

-

11

26

18

-

10

PRESC[4:0]

7

-

6

-

5

-

4

-

3

-

EN

0: Keypad scanning is disabled

1: Keypad scanning is enabled

PRESC

Prescale select for the keypad scan rate:

Scan rate = 2

(SCAN.PRESC+1)

T

RC

The RC clock period can be found in the Electrical Characteristics section.

PIN

The index of the currently active scan pin. Writing to this bitfield has no effect.

2

-

25

PIN[2:0]

17

-

9

1

-

AT32UC3B

24

16

-

8

0

EN

116

32059L–AVR32–01/2012

AT32UC3B

13.7.13

Enable Register

Name: EN

Access Type:

Write-only

Offset: 0x030

Reset Value: 0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

-

7

INT7

6

INT6

5

INT5

4

INT4

3

INT3

• INTn: External Interrupt n

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the corresponding external interrupt.

• NMI: Non-Maskable Interrupt

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Non-Maskable Interrupt.

10

-

2

INT2

26

-

18

-

9

-

1

INT1

25

-

17

-

8

NMI

0

INT0

24

-

16

-

117

32059L–AVR32–01/2012

AT32UC3B

13.7.14

Disable Register

Name: DIS

Access Type:

Write-only

Offset: 0x034

Reset Value: 0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

-

7

INT7

6

INT6

5

INT5

4

INT4

3

INT3

• INTn: External Interrupt n

Writing a zero to this bit has no effect.

Writing a one to this bit will disable the corresponding external interrupt.

• NMI: Non-Maskable Interrupt

Writing a zero to this bit has no effect.

Writing a one to this bit will disable the Non-Maskable Interrupt.

10

-

2

INT2

26

-

18

-

9

-

1

INT1

25

-

17

-

8

NMI

0

INT0

24

-

16

-

118

32059L–AVR32–01/2012

AT32UC3B

13.7.15

Control Register

Name: CTRL

Access Type:

Read-only

Offset: 0x038

Reset Value: 0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

15

-

14

-

13

-

12

-

7

INT7

6

INT6

5

INT5

4

INT4

• INTn: External Interrupt n

0: The corresponding external interrupt is disabled.

1: The corresponding external interrupt is enabled.

• NMI: Non-Maskable Interrupt

0: The Non-Maskable Interrupt is disabled.

1: The Non-Maskable Interrupt is enabled.

28

-

20

-

11

-

3

INT3

27

-

19

-

10

-

2

INT2

26

-

18

-

9

-

1

INT1

25

-

17

-

8

NMI

0

INT0

24

-

16

-

119

32059L–AVR32–01/2012

AT32UC3B

14. Flash Controller (FLASHC)

Rev: 2.1.2.4

14.1 Features

Controls flash block with dual read ports allowing staggered reads.

Supports 0 and 1 wait state bus access.

Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per clock cycle.

32-bit HSB interface for reads from flash array and writes to page buffer.

32-bit PB interface for issuing commands to and configuration of the controller.

16 lock bits, each protecting a region consisting of (total number of pages in the flash block / 16) pages.

Regions can be individually protected or unprotected.

Additional protection of the Boot Loader pages.

Supports reads and writes of general-purpose NVM bits.

Supports reads and writes of additional NVM pages.

Supports device protection through a security bit.

Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing

flash and clearing security bit.

Interface to Power Manager for power-down of flash-blocks in sleep mode.

14.2 Overview

The flash controller (FLASHC) interfaces a flash block with the 32-bit internal High-Speed Bus

(HSB). Performance for uncached systems with high clock-frequency and one wait state is increased by placing words with sequential addresses in alternating flash subblocks. Having one read interface per subblock allows them to be read in parallel. While data from one flash subblock is being output on the bus, the sequential address is being read from the other flash subblock and will be ready in the next clock cycle.

The controller also manages the programming, erasing, locking and unlocking sequences with dedicated commands.

14.3 Product dependencies

14.3.1

Power Manager

The FLASHC has two bus clocks connected: One High speed bus clock (CLK_FLASHC_HSB) and one Peripheral bus clock (CLK_FLASHC_PB). These clocks are generated by the Power manager. Both clocks are turned on by default, but the user has to ensure that

CLK_FLASHC_HSB is not turned off before reading the flash or writing the pagebuffer and that

CLK_FLASHC_PB is not turned off before accessing the FLASHC configuration and control registers.

14.3.2

Interrupt Controller

The FLASHC interrupt lines are connected to internal sources of the interrupt controller. Using

FLASHC interrupts requires the interrupt controller to be programmed first.

120

32059L–AVR32–01/2012

AT32UC3B

14.4 Functional description

14.4.1

Bus interfaces

The FLASHC has two bus interfaces, one HSB interface for reads from the flash array and writes to the page buffer, and one Peripheral Bus (PB) interface for writing commands and control to and reading status from the controller.

14.4.2

14.4.3

14.4.4

Memory organization

To maximize performance for high clock-frequency systems, FLASHC interfaces to a flash block with two read ports. The flash block has several parameters, given by the design of the flash block. Refer to the “Memories” chapter for the device-specific values of the parameters.

p pages (FLASH_P)

w words in each page and in the page buffer (FLASH_W)

pw words in total (FLASH_PW)

f general-purpose fuse bits (FLASH_F)

• 1 security fuse bit

• 1 User Page

User page

The User page is an additional page, outside the regular flash array, that can be used to store various data, like calibration data and serial numbers. This page is not erased by regular chip erase. The User page can only be written and erased by proprietary commands. Read accesses to the User page is performed just as any other read access to the flash. The address map of the

User page is given in Figure 14-1

.

Read operations

The FLASHC provides two different read modes:

• 0 wait state (0ws) for clock frequencies < (access time of the flash plus the bus delay)

• 1 wait state (1ws) for clock frequencies < (access time of the flash plus the bus delay)/2

Higher clock frequencies that would require more wait states are not supported by the flash controller.

The programmer can select the wait states required by writing to the FWS field in the Flash Control Register (FCR). It is the responsibility of the programmer to select a number of wait states compatible with the clock frequency and timing characteristics of the flash block.

In 0ws mode, only one of the two flash read ports is accessed. The other flash read port is idle.

In 1ws mode, both flash read ports are active. One read port reading the addressed word, and the other reading the next sequential word.

If the clock frequency allows, the user should use 0ws mode, because this gives the lowest power consumption for low-frequency systems as only one flash read port is read. Using 1ws mode has a power/performance ratio approaching 0ws mode as the clock frequency approaches twice the max frequency of 0ws mode. Using two flash read ports use twice the power, but also give twice the performance.

121

32059L–AVR32–01/2012

AT32UC3B

The flash controller supports flash blocks with up to 2^21 word addresses, as displayed in

Figure

14-1 . Reading the memory space between address pw and 2^21-1 returns an undefined result.

The User page is permanently mapped to word address 2^21.

Table 14-1.

User page addresses

Memory type

Main array

User

Start address, byte sized

0

2^23 = 8388608

Size

pw

words = 4pw bytes w words = 4w bytes

Figure 14-1. Memory map for the Flash memories

A ll a d d r e s s e s a r e w o r d a d d r e s s e s

14.4.5

14.4.6

0

F la s h w it h e x t r a p a g e

Quick Page Read

A dedicated command, Quick Page Read (QPR), is provided to read all words in an addressed page. All bits in all words in this page are AND’ed together, returning a 1-bit result. This result is placed in the Quick Page Read Result (QPRR) bit in Flash Status Register (FSR). The QPR command is useful to check that a page is in an erased state. The QPR instruction is much faster than performing the erased-page check using a regular software subroutine.

Write page buffer operations

The internal memory area reserved for the embedded flash can also be written through a writeonly page buffer. The page buffer is addressed only by the address bits required to address w words (since the page buffer is word addressable) and thus wrap around within the internal memory area address space and appear to be repeated within it.

When writing to the page buffer, the PAGEN field in the

Flash Command register (

FCMD) is updated with the page number corresponding to page address of the latest word written into the page buffer.

122

32059L–AVR32–01/2012

AT32UC3B

14.4.7

The page buffer is also used for writes to the User page.

Write operations can be prevented by programming the Memory Protection Unit of the CPU.

Writing 8-bit and 16-bit data to the page buffer is not allowed and may lead to unpredictable data corruption.

Page buffer write operations are performed with 4 wait states.

Writing to the page buffer can only change page buffer bits from one to zero, i.e. writing

0xaaaaaaaa to a page buffer location that has the value 0x00000000, will not change the page buffer value. The only way to change a bit from zero to one, is to reset the entire page buffer with the Clear Page Buffer command.

The page buffer is not automatically reset after a page write. The programmer should do this manually by issuing the Clear Page Buffer flash command. This can be done after a page write, or before the page buffer is loaded with data to be stored to the flash page.

Example: Writing a word into word address 130 of a flash with 128 words in the page buffer.

PAGEN will be updated with the value 1, and the word will be written into word 2 in the page buffer.

Writing words to a page that is not completely erased

This can be used for EEPROM emulation, i.e. writes with granularity of one word instead of an entire page. Only words that are in an completely erased state (0xFFFFFFFF) can be changed.

The procedure is as follows:

1. Clear page buffer

2. Write to the page buffer the result of the logical bitwise AND operation between the contents of the flash page and the new data to write. Only words that were in an erased state can be changed from the original page.

3. Write Page.

14.5 Flash commands

The FLASHC offers a command set to manage programming of the flash memory, locking and

unlocking of regions, and full flash erasing. See chapter 14.8.2 for a complete list of commands.

To run a command, the field FCMD.CMD has to be written with the command number. As soon as FCMD is written, the FRDY bit is automatically cleared. Once the current command is complete, the FRDY bit is automatically set. If an interrupt has been enabled by setting the bit FRDY in FCR, the interrupt line of the flash controller is activated. All flash commands except for Quick

Page Read (QPR) will generate an interrupt request upon completion if FRDY is set.

After a command has been written to FCMD, the programming algorithm should wait until the command has been executed before attempting to read instructions or data from the flash or writing to the page buffer, as the flash will be busy. The waiting can be performed either by polling the Flash Status Register (FSR) or by waiting for the flash ready interrupt. The command written to FCMD is initiated on the first clock cycle where the HSB bus interface in FLASHC is

IDLE. The user must make sure that the access pattern to the FLASHC HSB interface contains an IDLE cycle so that the command is allowed to start. Make sure that no bus masters such as

DMA controllers are performing endless burst transfers from the flash. Also, make sure that the

CPU does not perform endless burst transfers from flash. This is done by letting the CPU enter sleep mode after writing to FCMD, or by polling FSR for command completion. This polling will result in an access pattern with IDLE HSB cycles.

123

32059L–AVR32–01/2012

AT32UC3B

14.5.1

14.5.2

All the commands are protected by the same keyword, which has to be written in the eight highest bits of FCMD. Writing FCMD with data that does not contain the correct key and/or with an invalid command has no effect on the flash memory; however, the PROGE bit is set in FSR. This bit is automatically cleared by a read access to FSR.

Writing a command to FCMD while another command is being executed has no effect on the flash memory; however, the PROGE bit is set in FSR. This bit is automatically cleared by a read access to FSR.

If the current command writes or erases a page in a locked region, or a page protected by the

BOOTPROT fuses, the command has no effect on the flash memory; however, the LOCKE bit is set in FSR . This bit is automatically cleared by a read access to FSR.

Write/erase page operation

Flash technology requires that an erase must be done before programming. The entire flash can be erased by an Erase All command. Alternatively, pages can be individually erased by the

Erase Page command.

The User page can be written and erased using the mechanisms described in this chapter.

After programming, the page can be locked to prevent miscellaneous write or erase sequences.

Locking is performed on a per-region basis, so locking a region locks all pages inside the region.

Additional protection is provided for the lowermost address space of the flash. This address space is allocated for the Boot Loader, and is protected both by the lock bit(s) corresponding to this address space, and the BOOTPROT[2:0] fuses.

Data to be written are stored in an internal buffer called page buffer. The page buffer contains w words. The page buffer wraps around within the internal memory area address space and appears to be repeated by the number of pages in it. Writing of 8-bit and 16-bit data to the page buffer is not allowed and may lead to unpredictable data corruption.

Data must be written to the page buffer before the programming command is written to FCMD.

The sequence is as follows:

• Reset the page buffer with the Clear Page Buffer command.

• Fill the page buffer with the desired contents, using only 32-bit access.

• Programming starts as soon as the programming key and the programming command are written to the Flash Command Register. The FCMD.PAGEN field must contain the address of the page to write. PAGEN is automatically updated when writing to the page buffer, but can also be written to directly. The FRDY bit in FSR is automatically cleared when the page write operation starts.

• When programming is completed, the bit FRDY in FSR is set. If an interrupt was enabled by setting the bit FRDY in FCR, the interrupt line of the flash controller is set.

Two errors can be detected in FSR after a programming sequence:

• Programming Error: A bad keyword and/or an invalid command have been written in FCMD.

• Lock Error: The page to be programmed belongs to a locked region. A command must be executed to unlock the corresponding region before programming can start.

Erase All operation

The entire memory is erased if the Erase All command (EA) is written to FCMD. Erase All erases all bits in the flash array. The User page is not erased. All flash memory locations, the generalpurpose fuse bits, and the security bit are erased (reset to 0xFF) after an Erase All.

124

32059L–AVR32–01/2012

AT32UC3B

14.5.3

The EA command also ensures that all volatile memories, such as register file and RAMs, are erased before the security bit is erased.

Erase All operation is allowed only if no regions are locked, and the BOOTPROT fuses are programmed with a region size of 0. Thus, if at least one region is locked, the bit LOCKE in FSR is set and the command is cancelled. If the bit LOCKE has been written to 1 in FCR, the interrupt line rises.

When the command is complete, the bit FRDY bit in FSR is set. If an interrupt has been enabled by setting the bit FRDY in FCR, the interrupt line of the flash controller is set. Two errors can be detected in FSR after issuing the command:

• Programming Error: A bad keyword and/or an invalid command have been written in FCMD.

• Lock Error: At least one lock region to be erased is protected, or BOOTPROT is different from 0. The erase command has been refused and no page has been erased. A Clear Lock

Bit command must be executed previously to unlock the corresponding lock regions.

Region lock bits

The flash block has p pages, and these pages are grouped into 16 lock regions, each region containing p/16 pages. Each region has a dedicated lock bit preventing writing and erasing pages in the region. After production, the device may have some regions locked. These locked regions are reserved for a boot or default application. Locked regions can be unlocked to be erased and then programmed with another application or other data.

To lock or unlock a region, the commands Lock Region Containing Page (LP) and Unlock

Region Containing Page (UP) are provided. Writing one of these commands, together with the number of the page whose region should be locked/unlocked, performs the desired operation.

One error can be detected in FSR after issuing the command:

• Programming Error: A bad keyword and/or an invalid command have been written in FCMD.

The lock bits are implemented using the lowest 16 general-purpose fuse bits. This means that lock bits can also be set/cleared using the commands for writing/erasing general-purpose fuse

bits, see chapter 14.6. The general-purpose bit being in an erased (1) state means that the

region is unlocked.

The lowermost pages in the Flash can additionally be protected by the BOOTPROT fuses, see

Section 14.6

.

14.6 General-purpose fuse bits

Each flash block has a number of general-purpose fuse bits that the application programmer can use freely. The fuse bits can be written and erased using dedicated commands, and read

125

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

through a dedicated Peripheral Bus address. Some of the general-purpose fuse bits are reserved for special purposes, and should not be used for other functions.:

Table 14-2.

General-purpose fuses with special functions

General-

Purpose fuse number Name Usage

15:0

16

19:17

LOCK

EPFL

BOOTPROT

Region lock bits.

External Privileged Fetch Lock. Used to prevent the CPU from fetching instructions from external memories when in privileged mode. This bit can only be changed when the security bit is cleared. The address range corresponding to external memories is device-specific, and not known to the flash controller. This fuse bit is simply routed out of the CPU or bus system, the flash controller does not treat this fuse in any special way, except that it can not be altered when the security bit is set.

If the security bit is set, only an external JTAG Chip Erase can clear EPFL. No internal commands can alter EPFL if the security bit is set.

When the fuse is erased (i.e. "1"), the CPU can execute instructions fetched from external memories. When the fuse is programmed (i.e. "0"), instructions can not be executed from external memories.

Used to select one of eight different boot loader sizes. Pages included in the bootlegger area can not be erased or programmed except by a JTAG chip erase. BOOTPROT can only be changed when the security bit is cleared.

If the security bit is set, only an external JTAG Chip Erase can clear BOOTPROT, and thereby allow the pages protected by

BOOTPROT to be programmed. No internal commands can alter BOOTPROT or the pages protected by BOOTPROT if the security bit is set.

The BOOTPROT fuses protects the following address space for the Boot Loader:

2

1

0

4

3

6

5

Table 14-3.

Boot Loader area specified by BOOTPROT

BOOTPROT

7

Pages protected by

BOOTPROT

None

Size of protected memory

0

0-1

0-3

0-7

0-15

0-31

0-63

0-127

1kByte

2kByte

4kByte

8kByte

16kByte

32kByte

64kByte

126

AT32UC3B

To erase or write a general-purpose fuse bit, the commands Write General-Purpose Fuse Bit

(WGPB) and Erase General-Purpose Fuse Bit (EGPB) are provided. Writing one of these commands, together with the number of the fuse to write/erase, performs the desired operation.

An entire General-Purpose Fuse byte can be written at a time by using the Program GP Fuse

Byte (PGPFB) instruction. A PGPFB to GP fuse byte 2 is not allowed if the flash is locked by the security bit. The PFB command is issued with a parameter in the PAGEN field:

• PAGEN[2:0] - byte to write

• PAGEN[10:3] - Fuse value to write

All General-Purpose fuses can be erased by the Erase All General-Purpose fuses (EAGP) command. An EAGP command is not allowed if the flash is locked by the security bit.

Two errors can be detected in FSR after issuing these commands:

• Programming Error: A bad keyword and/or an invalid command have been written in FCMD.

• Lock Error: A write or erase of any of the special-function fuse bits in Table 14-3

was attempted while the flash is locked by the security bit.

The lock bits are implemented using the lowest 16 general-purpose fuse bits. This means that the 16 lowest general-purpose fuse bits can also be written/erased using the commands for locking/unlocking regions, see

Section 14.5.3

.

14.7 Security bit

The security bit allows the entire chip to be locked from external JTAG or other debug access for code security. The security bit can be written by a dedicated command, Set Security Bit (SSB).

Once set, the only way to clear the security bit is through the JTAG Chip Erase command.

Once the Security bit is set, the following Flash controller commands will be unavailable and return a lock error if attempted:

• Write General-Purpose Fuse Bit (WGPB) to BOOTPROT or EPFL fuses

• Erase General-Purpose Fuse Bit (EGPB) to BOOTPROT or EPFL fuses

• Program General-Purpose Fuse Byte (PGPFB) of fuse byte 2

• Erase All General-Purpose Fuses (EAGPF)

One error can be detected in FSR after issuing the command:

• Programming Error: A bad keyword and/or an invalid command have been written in FCMD.

127

32059L–AVR32–01/2012

AT32UC3B

14.8 User Interface

Table 14-4.

FLASHC Register Memory Map

Offset

0x0

0x4

0x8

0xc

0x10

Register

Flash Control Register

Flash Command Register

Flash Status Register

Flash General Purpose Fuse Register Hi

Name

FCR

FCMD

FSR

FGPFRHI

Access Reset

R/W 0x00000000

R/W

R/W

0x00000000

0x00000000 (*)

R NA (*)

Flash General Purpose Fuse Register Lo FGPFRLO R NA (*)

(*) The value of the Lock bits is dependent of their programmed state. All other bits in FSR are 0.

All bits in FGPFR and FCFR are dependent on the programmed state of the fuses they map to.

Any bits in these registers not mapped to a fuse read 0.

32059L–AVR32–01/2012

128

14.8.1

Flash Control Register

Name: FCR

Access Type: Read/Write

Offset: 0x00

Reset value: 0x00000000

31

-

30

-

29

-

23

-

15

-

22

-

14

-

21

-

13

-

28

-

20

-

12

-

7

-

6

FWS

5

-

4

-

• FRDY: Flash Ready Interrupt Enable

0: Flash Ready does not generate an interrupt.

1: Flash Ready generates an interrupt.

• LOCKE: Lock Error Interrupt Enable

0: Lock Error does not generate an interrupt.

1: Lock Error generates an interrupt.

• PROGE: Programming Error Interrupt Enable

0: Programming Error does not generate an interrupt.

1: Programming Error generates an interrupt.

• FWS: Flash Wait State

0: The flash is read with 0 wait states.

1: The flash is read with 1 wait state.

11

-

3

PROGE

27

-

19

-

10

-

2

LOCKE

26

-

18

-

9

-

1

-

25

-

17

-

AT32UC3B

8

-

0

FRDY

24

-

16

-

129

32059L–AVR32–01/2012

AT32UC3B

14.8.2

Flash Command Register

Name: FCMD

Access Type: Read/Write

Offset: 0x04

Reset value: 0x00000000

FCMD can not be written if the flash is in the process of performing a flash command. Doing so will cause the FCR write to be ignored, and the PROGE bit to be set.

31 30 29 28 27 26 25 24

KEY

23 22 21 18 17 16

15 14 13

20

PAGEN [15:8]

19

12

PAGEN [7:0]

11 10 9 8

7

-

6

-

5 4 3

CMD

2 1 0

• CMD: Command

This field defines the flash command. Issuing any unused command will cause the Programming Error bit to be set, and the corresponding interrupt to be requested if FCR.PROGE is set.

Table 14-5.

Set of commands

Command

No operation

Write Page

Erase Page

Clear Page Buffer

Lock region containing given Page

Unlock region containing given Page

Erase All

Write General-Purpose Fuse Bit

Erase General-Purpose Fuse Bit

Set Security Bit

Program GP Fuse Byte

Erase All GPFuses

Quick Page Read

10

11

12

8

9

6

7

4

5

2

3

Value

0

1

EA

WGPB

EGPB

SSB

PGPFB

EAGPF

QPR

Mnemonic

NOP

WP

EP

CPB

LP

UP

130

32059L–AVR32–01/2012

AT32UC3B

Table 14-5.

Set of commands

Command

Write User Page

Erase User Page

Quick Page Read User Page

Value

13

14

15

Mnemonic

WUP

EUP

QPRUP

• PAGEN: Page number

The PAGEN field is used to address a page or fuse bit for certain operations. In order to simplify programming, the PAGEN field is automatically updated every time the page buffer is written to. For every page buffer write, the PAGEN field is updated with the page number of the address being written to. Hardware automatically masks writes to the PAGEN field so that only bits representing valid page numbers can be written, all other bits in PAGEN are always 0. As an example, in a flash with 1024 pages (page 0 - page 1023), bits 15:10 will always be 0.

Table 14-6.

Semantic of PAGEN field in different commands

Command

No operation

Write Page

Clear Page Buffer

Lock region containing given Page

Unlock region containing given Page

Erase All

Write General-Purpose Fuse Bit

Erase General-Purpose Fuse Bit

Set Security Bit

Program GP Fuse Byte

Erase All GP Fuses

Quick Page Read

Write User Page

Erase User Page

Quick Page Read User Page

PAGEN description

Not used

The number of the page to write

Not used

Page number whose region should be locked

Page number whose region should be unlocked

Not used

GPFUSE #

GPFUSE #

Not used

WriteData[7:0], ByteAddress[2:0]

Not used

Page number

Not used

Not used

Not used

• KEY: Write protection key

This field should be written with the value 0xA5 to enable the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started.

This field always reads as 0.

131

32059L–AVR32–01/2012

14.8.3

Flash Status Register

Name: FSR

Access Type: Read/Write

Offset: 0x08

Reset value: 0x00000000

31

LOCK15

30

LOCK14

29

LOCK13

23

LOCK7

15

22

LOCK6

14

FSZ

21

LOCK5

13

28

LOCK12

20

LOCK4

27

LOCK11

19

LOCK3

26

LOCK10

18

LOCK2

12

-

11

-

10

-

7

-

6

-

5

QPRR

4

SECURITY

3

PROGE

2

LOCKE

• FRDY: Flash Ready Status

0: The flash controller is busy and the application must wait before running a new command.

1: The flash controller is ready to run a new command.

• LOCKE: Lock Error Status

Automatically cleared when FSR is read.

0: No programming of at least one locked lock region has happened since the last read of FSR.

1: Programming of at least one locked lock region has happened since the last read of FSR.

• PROGE: Programming Error Status

Automatically cleared when FSR is read.

0: No invalid commands and no bad keywords were written in FCMD.

1: An invalid command and/or a bad keyword was/were written in FCMD.

• SECURITY: Security Bit Status

0: The security bit is inactive.

1: The security bit is active.

• QPRR: Quick Page Read Result

0: The result is zero, i.e. the page is not erased.

1: The result is one, i.e. the page is erased.

1

-

9

-

25

LOCK9

17

LOCK1

AT32UC3B

24

LOCK8

16

LOCK0

8

-

0

FRDY

132

32059L–AVR32–01/2012

• FSZ: Flash Size

The size of the flash. Not all device families will provide all flash sizes indicated in the table.

Table 14-7.

Flash size

5

6

3

4

7

1

2

FSZ

0

Flash Size

32 Kbytes

64 Kbytes

128 Kbytes

256 Kbytes

384 Kbytes

512 Kbytes

768 Kbytes

1024 Kbytes

• LOCKx: Lock Region x Lock Status

0: The corresponding lock region is not locked.

1: The corresponding lock region is locked.

AT32UC3B

133

32059L–AVR32–01/2012

AT32UC3B

14.8.4

Flash General Purpose Fuse Register High

Name: FGPFRHI

Access Type: Read

Offset: 0x0C

Reset value: N/A

31

GPF63

30

GPF62

29

GPF61

28

GPF60

23

GPF55

15

GPF47

22

GPF54

14

GPF46

21

GPF53

13

GPF45

20

GPF52

12

GPF44

27

GPF59

19

GPF51

11

GPF43

7

GPF39

6

GPF38

5

GPF37

4

GPF36

This register is only used in systems with more than 32 GP fuses.

• GPFxx: General Purpose Fuse xx

0: The fuse has a written/programmed state.

1: The fuse has an erased state.

3

GPF35

26

GPF58

18

GPF50

10

GPF42

2

GPF34

25

GPF57

17

GPF49

9

GPF41

1

GPF33

24

GPF56

16

GPF48

8

GPF40

0

GPF32

134

32059L–AVR32–01/2012

AT32UC3B

14.8.5

Flash General Purpose Fuse Register Low

Name: FGPFRLO

Access Type: Read

Offset: 0x10

Reset value: N/A

31

GPF31

30

GPF30

29

GPF29

28

GPF28

23

GPF23

15

GPF15

22

GPF22

14

GPF14

21

GPF21

13

GPF13

20

GPF20

12

GPF12

7

GPF07

6

GPF06

5

GPF05

• GPFxx: General Purpose Fuse xx

0: The fuse has a written/programmed state.

1: The fuse has an erased state.

4

GPF04

27

GPF27

19

GPF19

11

GPF11

3

GPF03

26

GPF26

18

GPF18

10

GPF10

2

GPF02

25

GPF25

17

GPF17

9

GPF09

1

GPF01

24

GPF24

16

GPF16

8

GPF08

0

GPF00

135

32059L–AVR32–01/2012

AT32UC3B

14.9 Fuses Settings

The flash block contains a number of general purpose fuses. Some of these fuses have defined meanings outside the flash controller and are described in this section.

The general purpose fuses are erase by a JTAG chip erase.

14.9.1

Flash General Purpose Fuse Register Low (FGPFRLO)

31

GPF31

30

GPF30

29

GPF29

28

BODEN

27 26

BODHYST

25 24

BODLEVEL[5:4]

23

15

7

22 21

BODLEVEL[3:0]

14 13

20 19 18

BOOTPROT

10

17 16

EPFL

8 12

LOCK[15:8]

11 9

6 5 4

LOCK[7:0]

BODEN: Brown Out Detector Enable

3 2 1 0

BODEN

0x0

0x1

0x2

0x3

Description

BOD disabled

BOD enabled, BOD reset enabled

BOD enabled, BOD reset disabled

BOD disabled

BODHYST: Brown Out Detector Hysteresis

0: The Brown out detector hysteresis is disabled

1: The Brown out detector hysteresis is enabled

BODLEVEL: Brown Out Detector Trigger Level

This controls the voltage trigger level for the Brown out detector. Refer to Electrical Characteristics section. If the BODLEVEL is set higher than VDDCORE and enabled byt fuses, the part will be in constant reset. To recover from this situation, apply an external voltage on VDDCORE that is higher than the BOD level and disable the BOD.

LOCK, EPFL, BOOTPROT

These are Flash controller fuses and are described in the FLASHC section.

As no external memories can be connected to AT32UC3B the EPFL bit has no effect.

136

32059L–AVR32–01/2012

AT32UC3B

14.9.2

Default Fuse Value

The devices are shipped with the FGPFRLO register value: 0xFC07FFFF:

• GPF31 fuse set to 1b. This fuse is used by the pre-programmed USB bootloader.

• GPF30 fuse set to 1b. This fuse is used by the pre-programmed USB bootloader.

• GPF29 fuse set to 1b. This fuse is used by the pre-programmed USB bootloader.

• BODEN fuses set to 11b. BOD is disabled.

• BODHYST fuse set to 1b. The BOD hysteresis is enabled.

• BODLEVEL fuses set to 000000b. This is the minimum voltage trigger level. BOD will never trigger as this level is below the POR level.

• BOOTPROT fuses set to 011b. The bootloader protected size is 8 Ko.

• EPFL fuse set to 1b. External privileged fetch is not locked.

• LOCK fuses set to 1111111111111111b. No region locked.

See also the AT32UC3B Bootloader user guide document.

After the JTAG chip erase command, the FGPFRLO register value is 0xFFFFFFFF.

14.10 Bootloader Configuration

The bootloader uses one word in the flash User page to store its configuration. This configuration word is located at address 0x808001FC and its default value is 0x929E0D6B.

Refer to the bootloader documentation for more information.

14.11 Serial Number

Each device has a unique 120 bits serial number readable from address 0x80800204 to

0x80800212.

14.12 Module configuration

Table 14-8.

Flash Memory Parameters

Part Number

AT32UC3B0512

AT32UC3B1512

AT32UC3B0256

AT32UC3B1256

AT32UC3B0128

AT32UC3B1128

AT32UC3B064

AT32UC3B164

Flash Size

(FLASH_PW)

512 Kbytes

512 Kbytes

256 Kbytes

256 Kbytes

128 Kbytes

128 Kbytes

64 Kbytes

64 Kbytes

Number of pages

(FLASH_P)

1024

1024

512

512

256

256

128

128

Page size

(FLASH_W)

128 words

128 words

128 words

128 words

128 words

128 words

128 words

128 words

General Purpose

Fuse bits

(FLASH_L)

32 fuses

32 fuses

32 fuses

32 fuses

32 fuses

32 fuses

32 fuses

32 fuses

137

32059L–AVR32–01/2012

AT32UC3B

15. HSB Bus Matrix (HMATRIX)

Rev: 2.3.0.2

15.1 Features

User Interface on peripheral bus

Configurable Number of Masters (Up to sixteen)

Configurable Number of Slaves (Up to sixteen)

One Decoder for Each Master

Programmable Arbitration for Each Slave

– Round-Robin

– Fixed Priority

Programmable Default Master for Each Slave

– No Default Master

– Last Accessed Default Master

– Fixed Default Master

One Cycle Latency for the First Access of a Burst

Zero Cycle Latency for Default Master

One Special Function Register for Each Slave (Not dedicated)

15.2 Overview

The Bus Matrix implements a multi-layer bus structure, that enables parallel access paths between multiple High Speed Bus (HSB) masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 16 HSB Masters to up to 16 HSB Slaves.

The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). The Bus Matrix provides 16

Special Function Registers (SFR) that allow the Bus Matrix to support application specific features.

15.3 Product Dependencies

In order to use this module, other parts of the system must be configured correctly, as described below.

15.3.1

Clocks

The clock for the HMATRIX bus interface (CLK_HMATRIX) is generated by the Power Manager.

This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the HMATRIX before disabling the clock, to avoid freezing the HMATRIX in an undefined state.

15.4 Functional Description

15.4.1

Special Bus Granting Mechanism

The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. This mechanism reduces latency at first access of a burst or single transfer. This bus granting mechanism sets a different default master for every slave.

138

32059L–AVR32–01/2012

AT32UC3B

15.4.1.1

At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: no default master, last access master and fixed default master.

No Default Master

At the end of the current access, if no other request is pending, the slave is disconnected from all masters. No Default Master suits low-power mode.

15.4.1.2

15.4.1.3

15.4.2

Last Access Master

At the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request.

Fixed Default Master

At the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike last access master, the fixed master does not change unless the user modifies it by a software action (field FIXED_DEFMSTR of the related SCFG).

To change from one kind of default master to another, the Bus Matrix user interface provides the

Slave Configuration Registers, one for each slave, that set a default master for each slave. The

Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The

2-bit DEFMSTR_TYPE field selects the default master type (no default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to the Bus Matrix user interface description.

Arbitration

The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e. when two or more masters try to access the same slave at the same time. One arbiter per HSB slave is provided, thus arbitrating each slave differently.

The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types for each slave:

1. Round-Robin Arbitration (default)

2. Fixed Priority Arbitration

This choice is made via the field ARBT of the Slave Configuration Registers (SCFG).

Each algorithm may be complemented by selecting a default master configuration for each slave.

When a re-arbitration must be done, specific conditions apply. See

Section 15.4.2.1 ”Arbitration

Rules” on page 139

.

15.4.2.1

Arbitration Rules

Each arbiter has the ability to arbitrate between two or more different master requests. In order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following cycles:

1. Idle Cycles: When a slave is not connected to any master or is connected to a master which is not currently accessing it.

2. Single Cycles: When a slave is currently doing a single access.

139

32059L–AVR32–01/2012

AT32UC3B

3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst.

4. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken.

• Undefined Length Burst Arbitration

In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst is used as a defined length burst transfer and can be selected from among the following five possibilities:

1. Infinite: No predicted end of burst is generated and therefore INCR burst transfer will never be broken.

2. One beat bursts: Predicted end of burst is generated at each single transfer inside the

INCP transfer.

3. Four beat bursts: Predicted end of burst is generated at the end of each four beat boundary inside INCR transfer.

4. Eight beat bursts: Predicted end of burst is generated at the end of each eight beat boundary inside INCR transfer.

5. Sixteen beat bursts: Predicted end of burst is generated at the end of each sixteen beat boundary inside INCR transfer.

This selection can be done through the field ULBT of the Master Configuration Registers

(MCFG).

• Slot Cycle Limit Arbitration

The Bus Matrix contains specific logic to break long accesses, such as very long bursts on a very slow slave (e.g., an external low speed memory). At the beginning of the burst access, a counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave

Configuration Register (SCFG) and decreased at each clock cycle. When the counter reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or word transfer.

15.4.2.2

Round-Robin Arbitration

This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave in a round-robin manner. If two or more master requests arise at the same time, the master with the lowest number is first serviced, then the others are serviced in a round-robin manner.

There are three round-robin algorithms implemented:

1. Round-Robin arbitration without default master

2. Round-Robin arbitration with last default master

3. Round-Robin arbitration with fixed default master

• Round-Robin Arbitration without Default Master

This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different masters to the same slave in a pure round-robin manner. At the end of

140

32059L–AVR32–01/2012

AT32UC3B

the current access, if no other request is pending, the slave is disconnected from all masters.

This configuration incurs one latency cycle for the first access of a burst. Arbitration without default master can be used for masters that perform significant bursts.

• Round-Robin Arbitration with Last Default Master

This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. In fact, at the end of the current transfer, if no other master request is pending, the slave remains connected to the last master that performed the access. Other non privileged masters still get one latency cycle if they want to access the same slave. This technique can be used for masters that mainly perform single accesses.

• Round-Robin Arbitration with Fixed Default Master

This is another biased round-robin algorithm. It allows the Bus Matrix arbiters to remove the one latency cycle for the fixed default master per slave. At the end of the current access, the slave remains connected to its fixed default master. Every request attempted by this fixed default master will not cause any latency whereas other non privileged masters will still get one latency cycle. This technique can be used for masters that mainly perform single accesses.

15.4.2.3

15.4.3

Fixed Priority Arbitration

This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user. If two or more master requests are active at the same time, the master with the highest priority number is serviced first. If two or more master requests with the same priority are active at the same time, the master with the highest number is serviced first.

For each slave, the priority of each master may be defined through the Priority Registers for

Slaves (PRAS and PRBS).

Slave and Master assignation

The index number assigned to Bus Matrix slaves and masters are described in Memories chapter.

141

32059L–AVR32–01/2012

15.5 User Interface

Table 15-1.

HMATRIX Register Memory Map

0x005C

0x0060

0x0064

0x0068

0x006C

0x0070

0x0074

0x0078

0x003C

0x0040

0x0044

0x0048

0x004C

0x0050

0x0054

0x0058

0x007C

0x0080

0x0084

0x0088

0x001C

0x0020

0x0024

0x0028

0x002C

0x0030

0x0034

0x0038

Offset

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

Register

Master Configuration Register 0

Master Configuration Register 1

Master Configuration Register 2

Master Configuration Register 3

Master Configuration Register 4

Master Configuration Register 5

Master Configuration Register 6

Master Configuration Register 7

Master Configuration Register 8

Master Configuration Register 9

Master Configuration Register 10

Master Configuration Register 11

Master Configuration Register 12

Master Configuration Register 13

Master Configuration Register 14

Master Configuration Register 15

Slave Configuration Register 0

Slave Configuration Register 1

Slave Configuration Register 2

Slave Configuration Register 3

Slave Configuration Register 4

Slave Configuration Register 5

Slave Configuration Register 6

Slave Configuration Register 7

Slave Configuration Register 8

Slave Configuration Register 9

Slave Configuration Register 10

Slave Configuration Register 11

Slave Configuration Register 12

Slave Configuration Register 13

Slave Configuration Register 14

Slave Configuration Register 15

Priority Register A for Slave 0

Priority Register B for Slave 0

Priority Register A for Slave 1

32059L–AVR32–01/2012

SCFG7

SCFG8

SCFG9

SCFG10

SCFG11

SCFG12

SCFG13

SCFG14

MCFG15

SCFG0

SCFG1

SCFG2

SCFG3

SCFG4

SCFG5

SCFG6

SCFG15

PRAS0

PRBS0

PRAS1

MCFG7

MCFG8

MCFG9

MCFG10

MCFG11

MCFG12

MCFG13

MCFG14

Name

MCFG0

MCFG1

MCFG2

MCFG3

MCFG4

MCFG5

MCFG6

AT32UC3B

0x00000002

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000000

0x00000000

0x00000000

Reset Value

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

142

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Access

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Table 15-1.

HMATRIX Register Memory Map (Continued)

0x00E0

0x00E4

0x00E8

0x00EC

0x00F0

0x00F4

0x00F8

0x00FC

0x00C0

0x00C4

0x00C8

0x00CC

0x00D0

0x00D4

0x00D8

0x00DC

0x0110

0x0114

0x0118

0x011C

0x0120

0x0124

0x0128

Offset

0x008C

0x0090

0x0094

0x0098

0x009C

0x00A0

0x00A4

0x00A8

0x00AC

0x00B0

0x00B4

0x00B8

0x00BC

Register

Priority Register B for Slave 1

Priority Register A for Slave 2

Priority Register B for Slave 2

Priority Register A for Slave 3

Priority Register B for Slave 3

Priority Register A for Slave 4

Priority Register B for Slave 4

Priority Register A for Slave 5

Priority Register B for Slave 5

Priority Register A for Slave 6

Priority Register B for Slave 6

Priority Register A for Slave 7

Priority Register B for Slave 7

Priority Register A for Slave 8

Priority Register B for Slave 8

Priority Register A for Slave 9

Priority Register B for Slave 9

Priority Register A for Slave 10

Priority Register B for Slave 10

Priority Register A for Slave 11

Priority Register B for Slave 11

Priority Register A for Slave 12

Priority Register B for Slave 12

Priority Register A for Slave 13

Priority Register B for Slave 13

Priority Register A for Slave 14

Priority Register B for Slave 14

Priority Register A for Slave 15

Priority Register B for Slave 15

Special Function Register 0

Special Function Register 1

Special Function Register 2

Special Function Register 3

Special Function Register 4

Special Function Register 5

Special Function Register 6

SFR0

SFR1

SFR2

SFR3

SFR4

SFR5

SFR6

PRAS12

PRBS12

PRAS13

PRBS13

PRAS14

PRBS14

PRAS15

PRBS15

PRAS8

PRBS8

PRAS9

PRBS9

PRAS10

PRBS10

PRAS11

PRBS11

Name

PRBS1

PRAS2

PRBS2

PRAS3

PRBS3

PRAS4

PRBS4

PRAS5

PRBS5

PRAS6

PRBS6

PRAS7

PRBS7

32059L–AVR32–01/2012

AT32UC3B

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

Reset Value

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

143

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Access

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Table 15-1.

HMATRIX Register Memory Map (Continued)

Offset

0x012C

0x0130

0x0134

0x0138

0x013C

0x0140

0x0144

0x0148

0x014C

Register

Special Function Register 7

Special Function Register 8

Special Function Register 9

Special Function Register 10

Special Function Register 11

Special Function Register 12

Special Function Register 13

Special Function Register 14

Special Function Register 15

Name

SFR7

SFR8

SFR9

SFR10

SFR11

SFR12

SFR13

SFR14

SFR15

AT32UC3B

Access

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Reset Value

32059L–AVR32–01/2012

144

AT32UC3B

15.5.1

Name:

Master Configuration Registers

MCFG0...MCFG15

Access Type:

Offset:

Reset Value:

Read/Write

0x00 - 0x3C

0x00000002

31

23

15

30

22

14

29

21

13

28

20

12

27

19

11

26

18

10

25

17

9

24

16

8

7

6

5

4

3

2 1

ULBT

0

ULBT: Undefined Length Burst Type

0: Infinite Length Burst

No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.

1: Single Access

The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst.

2: Four Beat Burst

The undefined length burst is split into a four-beat burst, allowing re-arbitration at each four-beat burst end.

3: Eight Beat Burst

The undefined length burst is split into an eight-beat burst, allowing re-arbitration at each eight-beat burst end.

4: Sixteen Beat Burst

The undefined length burst is split into a sixteen-beat burst, allowing re-arbitration at each sixteen-beat burst end.

145

32059L–AVR32–01/2012

AT32UC3B

15.5.2

Name:

Slave Configuration Registers

SCFG0...SCFG15

Access Type:

Offset:

Reset Value:

Read/Write

0x40 - 0x7C

0x00000010

31

23

30

22

29

21

28

27

20 19

FIXED_DEFMSTR

26

18

25

24

ARBT

17 16

DEFMSTR_TYPE

15

14

13

12

11

10

9

8

7 6 5 4

SLOT_CYCLE

3 2 1 0

ARBT: Arbitration Type

0: Round-Robin Arbitration

1: Fixed Priority Arbitration

FIXED_DEFMSTR: Fixed Default Master

This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.

The size of this field depends on the number of masters. This size is log2(number of masters).

DEFMSTR_TYPE: Default Master Type

0: No Default Master

At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.

This results in a one cycle latency for the first access of a burst transfer or for a single access.

1: Last Default Master

At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.

This results in not having one cycle latency when the last master tries to access the slave again.

2: Fixed Default Master

At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.

This results in not having one cycle latency when the fixed master tries to access the slave again.

SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst

When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.

This limit has been placed to avoid locking a very slow slave when very long bursts are used.

This limit must not be very small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.

146

32059L–AVR32–01/2012

AT32UC3B

15.5.3

Name:

Priority Registers A For Slaves

PRAS0...PRAS15

Access Type:

Offset:

Reset Value:

-

Read/Write

0x00000000

31

23

30

22

29

21

M7PR

28

20

27

19

26

18

25

17

M6PR

M5PR M4PR

15

14

13

M3PR

12 11

10

9

M2PR

7

6

5

M1PR

4 3

2

1

MxPR: Master x Priority

Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.

M0PR

24

16

8

0

147

32059L–AVR32–01/2012

AT32UC3B

15.5.4

Name:

Priority Registers B For Slaves

PRBS0...PRBS15

Access Type:

Offset:

Reset Value:

-

Read/Write

0x00000000

31

23

30

22

29

21

M15PR

28

20

27

19

26

18

25

17

M14PR

M13PR M12PR

15

14

13

M11PR

12 11

10

9

M10PR

7

6

5

M9PR

4 3

2

1

MxPR: Master x Priority

Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.

M8PR

24

16

8

0

148

32059L–AVR32–01/2012

AT32UC3B

15.5.5

Name:

Special Function Registers

Access Type:

Offset:

Reset Value:

-

0x110 - 0x115

SFR0...SFR15

Read/Write

31 30 29 28 27 26 25

SFR

23 22 21 20 19 18 17

SFR

15 14 13 12 11 10 9

SFR

7 6 5 4 3 2 1

SFR

SFR: Special Function Register Fields

Those registers are not a HMATRIX specific register. The field of those will be defined where they are used.

24

16

8

0

149

32059L–AVR32–01/2012

AT32UC3B

15.6 Bus Matrix Connections

Accesses to unused areas returns an error result to the master requesting such an access.

The bus matrix has the several masters and slaves. Each master has its own bus and its own decoder, thus allowing a different memory mapping per master. The master number in the table below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0 register is associated with the CPU Data master interface.

Table 15-2.

High Speed Bus masters

Master 0

Master 1

Master 2

Master 3

Master 4

CPU Data

CPU Instruction

CPU SAB

PDCA

USBB DMA

Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number in the table below can be used to index the HMATRIX control registers. For example, SCFG3 is associated with the Internal SRAM Slave Interface.

Table 15-3.

High Speed Bus slaves

Slave 0

Slave 1

Slave 2

Slave 3

Slave 4

Internal Flash

HSB-PB Bridge A

HSB-PB Bridge B

Internal SRAM

USBB DPRAM

150

32059L–AVR32–01/2012

32059L–AVR32–01/2012

Figure 15-1. HMatrix Master / Slave Connections

HMATRIX SLAVES

AT32UC3B

CPU Data 0

CPU

Instruction

1

CPU SAB 2

PDCA 3

USBB DMA 4

0 1 2 3 4

151

AT32UC3B

16. Peripheral DMA Controller (PDCA)

Rev: 1.0.2.1

16.1 Features

Multiple channels

Generates transfers between memories and peripherals such as USART and SPI

Two address pointers/counters per channel allowing double buffering

16.2 Overview

The Peripheral DMA Controller (PDCA) transfers data between on-chip peripheral modules such as USART, SPI and memories (those memories may be on- and off-chip memories). Using the

PDCA avoids CPU intervention for data transfers, improving the performance of the microcontroller. The PDCA can transfer data from memory to a peripheral or from a peripheral to memory.

The PDCA consists of multiple DMA channels. Each channel has:

• A Peripheral Select Register

• A 32-bit memory pointer

• A 16-bit transfer counter

• A 32-bit memory pointer reload value

• A 16-bit transfer counter reload value

The PDCA communicates with the peripheral modules over a set of handshake interfaces. The peripheral signals the PDCA when it is ready to receive or transmit data. The PDCA acknowledges the request when the transmission has started.

When a transmit buffer is empty or a receive buffer is full, an optional interrupt request can be generated.

152

32059L–AVR32–01/2012

AT32UC3B

16.3 Block Diagram

Figure 16-1. PDCA Block Diagram

Memory

HSB

HSB to PB

Bridge

HSB

High Speed

Bus Matrix

Interrupt

Controller

Peripheral

0

Peripheral

1

HSB

IRQ

Peripheral DMA

Controller

(PDCA)

Peripheral

2

Peripheral

(n-1)

Handshake Interfaces

16.4 Product Dependencies

In order to use this module, other parts of the system must be configured correctly, as described below.

16.4.1

16.4.2

16.4.3

Power Management

If the CPU enters a sleep mode that disables the PDCA clocks, the PDCA will stop functioning and resume operation after the system wakes up from sleep mode.

Clocks

The PDCA has two bus clocks connected: One High Speed Bus clock (CLK_PDCA_HSB) and one Peripheral Bus clock (CLK_PDCA_PB). These clocks are generated by the Power Manager. Both clocks are enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the PDCA before disabling the clocks, to avoid freezing the PDCA in an undefined state.

Interrupts

The PDCA interrupt request lines are connected to the interrupt controller. Using the PDCA interrupts requires the interrupt controller to be programmed first.

153

32059L–AVR32–01/2012

AT32UC3B

16.5 Functional Description

16.5.1

Basic Operation

The PDCA consists of multiple independent PDCA channels, each capable of handling DMA requests in parallel. Each PDCA channels contains a set of configuration registers which must be configured to start a DMA transfer.

In this section the steps necessary to configure one PDCA channel is outlined.

The peripheral to transfer data to or from must be configured correctly in the Peripheral Select

Register (PSR). This is performed by writing the Peripheral Identity (PID) value for the corresponding peripheral to the PID field in the PSR register. The PID also encodes the transfer direction, i.e. memory to peripheral or peripheral to memory. See

Section 16.5.5

.

The transfer size must be written to the Transfer Size field in the Mode Register (MR.SIZE). The

size must match the data size produced or consumed by the selected peripheral. See Section

16.5.6

.

The memory address to transfer to or from, depending on the PSR, must be written to the Memory Address Register (MAR). For each transfer the memory address is increased by either a

one, two or four, depending on the size set in MR. See Section 16.5.2

.

The number of data items to transfer is written to the TCR register. If the PDCA channel is enabled, a transfer will start immediately after writing a non-zero value to TCR or the reload version of TCR, TCRR. After each transfer the TCR value is decreased by one. Both MAR and TCR

can be read while the PDCA channel is active to monitor the DMA progress. See Section 16.5.3

.

The channel must be enabled for a transfer to start. A channel is enable by writing a one to the

EN bit in the Control Register (CR).

16.5.2

16.5.3

16.5.4

Memory Pointer

Each channel has a 32-bit Memory Address Register (MAR). This register holds the memory address for the next transfer to be performed. The register is automatically updated after each transfer. The address will be increased by either one, two or four depending on the size of the

DMA transfer (byte, halfword or word). The MAR can be read at any time during transfer.

Transfer Counter

Each channel has a 16-bit Transfer Counter Register (TCR). This register must be written with the number of transfers to be performed. The TCR register should contain the number of data items to be transferred independently of the transfer size. The TCR can be read at any time during transfer to see the number of remaining transfers.

Reload Registers

Both the MAR and the TCR have a reload register, respectively Memory Address Reload Register (MARR) and Transfer Counter Reload Register (TCRR). These registers provide the possibility for the PDCA to work on two memory buffers for each channel. When one buffer has completed, MAR and TCR will be reloaded with the values in MARR and TCRR. The reload logic is always enabled and will trigger if the TCR reaches zero while TCRR holds a non-zero value.

After reload, the MARR and TCRR registers are cleared.

If TCR is zero when writing to TCRR, the TCR and MAR are automatically updated with the value written in TCRR and MARR.

154

32059L–AVR32–01/2012

AT32UC3B

16.5.5

16.5.6

16.5.7

16.5.8

16.5.9

Peripheral Selection

The Peripheral Select Register (PSR) decides which peripheral should be connected to the

PDCA channel. A peripheral is selected by writing the corresponding Peripheral Identity (PID) to the PID field in the PSR register. Writing the PID will both select the direction of the transfer

(memory to peripheral or peripheral to memory), which handshake interface to use, and the address of the peripheral holding register. Refer to the Peripheral Identity (PID) table in the Module Configuration section for the peripheral PID values.

Transfer Size

The transfer size can be set individually for each channel to be either byte, halfword or word (8bit, 16-bit or 32-bit respectively). Transfer size is set by writing the desired value to the Transfer

Size field in the Mode Register (MR.SIZE).

When the PDCA moves data between peripherals and memory, data is automatically sized and aligned. When memory is accessed, the size specified in MR.SIZE and system alignment is used. When a peripheral register is accessed the data to be transferred is converted to a word where bit n in the data corresponds to bit n in the peripheral register. If the transfer size is byte or halfword, bits greater than 8 and16 respectively are set to zero.

Refer to the Module Configuration section for information regarding what peripheral registers are used for the different peripherals and then to the peripheral specific chapter for information about the size option available for the different registers.

Enabling and Disabling

Each DMA channel is enabled by writing a one to the Transfer Enable bit in the Control Register

(CR.TEN) and disabled by writing a one to the Transfer Disable bit (CR.TDIS). The current status can be read from the Status Register (SR).

While the PDCA channel is enabled all DMA request will be handled as long the TCR and TCRR is not zero.

Interrupts

Interrupts can be enabled by writing a one to the corresponding bit in the Interrupt Enable Register (IER) and disabled by writing a one to the corresponding bit in the Interrupt Disable Register

(IDR). The Interrupt Mask Register (IMR) can be read to see whether an interrupt is enabled or not. The current status of an interrupt source can be read through the Interrupt Status Register

(ISR).

The PDCA has three interrupt sources:

• Reload Counter Zero - The TCRR register is zero.

• Transfer Finished - Both the TCR and TCRR registers are zero.

• Transfer Error - An error has occurred in accessing memory.

Priority

If more than one PDCA channel is requesting transfer at a given time, the PDCA channels are prioritized by their channel number. Channels with lower numbers have priority over channels with higher numbers, giving channel zero the highest priority.

16.5.10

Error Handling

If the Memory Address Register (MAR) is set to point to an invalid location in memory, an error will occur when the PDCA tries to perform a transfer. When an error occurs, the Transfer Error

155

32059L–AVR32–01/2012

AT32UC3B

bit in the Interrupt Status Register (ISR.TERR) will be set and the DMA channel that caused the error will be stopped. In order to restart the channel, the user must program the Memory

Address Register to a valid address and then write a one to the Error Clear bit in the Control

Register (CR.ECLR). If the Transfer Error interrupt is enabled, an interrupt request will be generated when a transfer error occurs.

32059L–AVR32–01/2012

156

AT32UC3B

16.6 User Interface

16.6.1

Memory Map Overview

Table 16-1.

PDCA Register Memory Map

Address Range

0x000 - 0x03F

0x040 - 0x07F

...

(0x000 - 0x03F)+m*0x040

Contents

DMA channel 0 configuration registers

DMA channel 1 configuration registers

...

DMA channel m configuration registers

The channels are mapped as shown in

Table 16-1 . Each channel has a set of configuration registers, shown in Table 16-2 , where n is the channel number.

16.6.2

Channel Memory Map

Table 16-2.

PDCA Channel Configuration Registers

Offset

0x000

+ n*0x040

0x004

+ n*0x040

0x008

+ n*0x040

0x00C

+ n*0x040

0x010

+ n*0x040

0x014

+ n*0x040

0x018

+ n*0x040

0x01C

+ n*0x040

0x020

+ n*0x040

0x024

+ n*0x040

0x028

+ n*0x040

0x02C

+ n*0x040

Register

Memory Address Register

Peripheral Select Register

Transfer Counter Register

Memory Address Reload Register

Transfer Counter Reload Register

Control Register

Mode Register

Status Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Interrupt Status Register

Register Name

MAR

PSR

TCR

MARR

TCRR

CR

MR

SR

IER

IDR

IMR

ISR

Access

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Write-only

Read/Write

Read-only

Write-only

Write-only

Read-only

Read-only

Reset

0x00000000

-

(1)

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.

Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.

157

32059L–AVR32–01/2012

AT32UC3B

16.6.3

Name:

Memory Address Register

MAR

Access Type:

Offset:

Reset Value:

Read/Write

0x000 + n*0x040

0x00000000

31

23

30

22

29

21

28

MADDR[31:24]

27

20

MADDR[23:16]

19

26

18

25

17

24

16

15 14 13 12

MADDR[15:8]

11 10 9 8

7 6 5 4

MADDR[7:0]

3 2 1 0

• MADDR: Memory Address

Address of memory buffer. MADDR should be programmed to point to the start of the memory buffer when configuring the

PDCA. During transfer, MADDR will point to the next memory location to be read/written.

158

32059L–AVR32–01/2012

AT32UC3B

16.6.4

Name:

Peripheral Select Register

PSR

Access Type:

Offset:

Reset Value:

-

Read/Write

0x004 + n*0x040

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

25

-

17

-

24

-

16

-

15

-

14

-

13

-

12

-

11

-

10

-

9

-

8

-

7 6 5 4 3 2 1 0

PID

• PID: Peripheral Identifier

The Peripheral Identifier selects which peripheral should be connected to the DMA channel. Writing a PID will select both which handshake interface to use, the direction of the transfer and also the address of the Receive/Transfer Holding Register for the peripheral. See the Module Configuration section of PDCA for details. The width of the PID field is device specific and dependent on the number of peripheral modules in the device.

159

32059L–AVR32–01/2012

AT32UC3B

16.6.5

Name:

Transfer Counter Register

TCR

Access Type:

Offset:

Reset Value:

Read/Write

0x008 + n*0x040

0x00000000

31

-

23

-

15

30

-

22

-

14

29

-

21

-

13

28

-

20

-

27

-

19

-

26

-

18

-

10

25

-

17

-

9

24

-

16

-

8 12

TCV[15:8]

11

7 6 5 4 3 2 1 0

TCV[7:0]

• TCV: Transfer Counter Value

Number of data items to be transferred by the PDCA. TCV must be programmed with the total number of transfers to be made.

During transfer, TCV contains the number of remaining transfers to be done.

160

32059L–AVR32–01/2012

AT32UC3B

16.6.6

Name:

Memory Address Reload Register

MARR

Access Type:

Offset:

Reset Value:

Read/Write

0x00C + n*0x040

0x00000000

31

23

30

22

29

21

28

MARV[31:24]

27

20

MARV[23:16]

19

26

18

25

17

24

16

15 14 13 12

MARV[15:8]

11 10 9 8

7 6 5 4 3 2 1 0

MARV[7:0]

• MARV: Memory Address Reload Value

Reload Value for the MAR register. This value will be loaded into MAR when TCR reaches zero if the TCRR register has a nonzero value.

161

32059L–AVR32–01/2012

AT32UC3B

16.6.7

Name:

Transfer Counter Reload Register

TCRR

Access Type:

Offset:

Reset Value:

Read/Write

0x010 + n*0x040

0x00000000

31

-

23

-

15

30

-

22

-

14

29

-

21

-

13

28

-

20

-

27

-

19

-

26

-

18

-

10

25

-

17

-

9

24

-

16

-

8 12

TCRV[15:8]

11

7 6 5 4 3 2 1 0

TCRV[7:0]

• TCRV: Transfer Counter Reload Value

Reload value for the TCR register. When TCR reaches zero, it will be reloaded with TCRV if TCRV has a positive value. If TCRV is zero, no more transfers will be performed for the channel. When TCR is reloaded, the TCRR register is cleared.

162

32059L–AVR32–01/2012

AT32UC3B

16.6.8

Name:

Control Register

CR

Access Type:

Offset:

Reset Value:

Write-only

0x014 + n*0x040

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

25

-

17

-

24

-

16

-

15

-

14

-

13

-

12

-

11

-

10

-

9

-

8

ECLR

7

-

6

-

5

-

4

-

3

-

2

-

1

TDIS

0

TEN

• ECLR: Transfer Error Clear

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Transfer Error bit in the Status Register (SR.TERR). Clearing the SR.TERR bit will allow the channel to transmit data. The memory address must first be set to point to a valid location.

• TDIS: Transfer Disable

Writing a zero to this bit has no effect.

Writing a one to this bit will disable transfer for the DMA channel.

• TEN: Transfer Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will enable transfer for the DMA channel.

163

32059L–AVR32–01/2012

AT32UC3B

16.6.9

Name:

Mode Register

MR

Access Type:

Offset:

Reset Value:

Read/Write

0x018 + n*0x040

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

7

-

6

-

• SIZE: Size of Transfer

Table 16-3.

Size of Transfer

SIZE

0

1

2

3

Size of Transfer

Byte

Halfword

Word

Reserved

5

-

29

-

21

-

13

-

4

-

12

-

28

-

20

-

3

-

11

-

27

-

19

-

2

-

10

-

26

-

18

-

9

-

1

25

-

17

-

SIZE

8

-

0

24

-

16

-

164

32059L–AVR32–01/2012

AT32UC3B

16.6.10

Status Register

Name:

SR

Access Type:

Offset:

Reset Value:

Read-only

0x01C + n*0x040

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

15

-

14

-

13

-

12

-

7

-

6

-

5

-

4

-

• TEN: Transfer Enabled

This bit is cleared when the TDIS bit in CR is written to one.

This bit is set when the TEN bit in CR is written to one.

0: Transfer is disabled for the DMA channel.

1: Transfer is enabled for the DMA channel.

3

-

11

-

27

-

19

-

2

-

10

-

26

-

18

-

1

-

9

-

25

-

17

-

8

-

0

TEN

24

-

16

-

165

32059L–AVR32–01/2012

16.6.11

Interrupt Enable Register

Name:

IER

Access Type:

Offset:

Reset Value:

Write-only

0x020 + n*0x040

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

-

7

-

6

-

5

-

4

-

3

-

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will set the corresponding bit in IMR.

10

-

2

TERR

26

-

18

-

9

-

1

TRC

25

-

17

-

AT32UC3B

8

-

0

RCZ

24

-

16

-

166

32059L–AVR32–01/2012

16.6.12

Interrupt Disable Register

Name:

IDR

Access Type:

Offset:

Reset Value:

Write-only

0x024 + n*0x040

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

-

10

-

7

-

6

-

5

-

4

-

3

-

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will clear the corresponding bit in IMR.

2

TERR

26

-

18

-

9

-

1

TRC

25

-

17

-

AT32UC3B

8

-

0

RCZ

24

-

16

-

167

32059L–AVR32–01/2012

16.6.13

Interrupt Mask Register

Name:

IMR

Access Type:

Offset:

Reset Value:

Read-only

0x028 + n*0x040

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

-

10

-

7

-

6

-

5

-

4

-

3

-

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

A bit in this register is cleared when the corresponding bit in IDR is written to one.

A bit in this register is set when the corresponding bit in IER is written to one.

2

TERR

26

-

18

-

9

-

1

TRC

25

-

17

-

AT32UC3B

8

-

0

RCZ

24

-

16

-

168

32059L–AVR32–01/2012

16.6.14

Interrupt Status Register

Name:

ISR

Access Type:

Offset:

Reset Value:

Read-only

0x02C + n*0x040

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

26

-

18

-

10

-

7

-

6

-

5

-

4

-

3

-

2

TERR

1

TRC

• TERR: Transfer Error

This bit is cleared when no transfer errors have occurred since the last write to CR.ECLR.

This bit is set when one or more transfer errors has occurred since reset or the last write to CR.ECLR.

• TRC: Transfer Complete

This bit is cleared when the TCR and/or the TCRR holds a non-zero value.

This bit is set when both the TCR and the TCRR are zero.

• RCZ: Reload Counter Zero

This bit is cleared when the TCRR holds a non-zero value.

This bit is set when TCRR is zero.

25

-

17

-

9

-

AT32UC3B

8

-

0

RCZ

24

-

16

-

169

32059L–AVR32–01/2012

AT32UC3B

16.7 Module Configuration

The specific configuration for the PDCA instance is listed in the following tables.

Table 16-4.

PDCA Configuration

Features PDCA

Number of channels 7

Table 16-5.

Register Reset Values

Register

PSRn

Reset Value

n

16.7.1

DMA Handshake Signals

The following table defines the valid settings for the Peripheral Identifier (PID) in the PDCA

Peripheral Select Register (PSR).).

Table 16-6.

PDCA Handshake Signals

PID Value Peripheral module & direction

8

9

10

11

12

13

6

7

4

5

2

3

0

1

ADC

SSC - RX

USART0 - RX

USART1 - RX

USART2 - RX

TWI - RX

SPI0 - RX

SSC - TX

USART0 - TX

USART1 - TX

USART2 - TX

TWI - TX

SPI0 - TX

ABDAC - TX

170

32059L–AVR32–01/2012

AT32UC3B

17. General-Purpose Input/Output Controller (GPIO)

Rev: 1.1.0.4

17.1 Features

Each I/O line of the GPIO features:

Configurable pin-change, rising-edge or falling-edge interrupt on any I/O line

A glitch filter providing rejection of pulses shorter than one clock cycle

Input visibility and output control

Multiplexing of up to four peripheral functions per I/O line

Programmable internal pull-up resistor

17.2 Overview

The General Purpose Input/Output Controller manages the I/O pins of the microcontroller. Each

I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product.

17.3 Block Diagram

Figure 17-1. GPIO Block Diagram

PB Configuration

Interface

Interrupt Controller

GPIO Interrupt Request

General Purpose

Input/Output - GPIO

Power Manager

CLK_GPIO

PIN

PIN

PIN

PIN

PIN

MCU

I/O Pins

Embedded

Peripheral

Pin Control

Signals

17.4 Product Dependencies

In order to use this module, other parts of the system must be configured correctly, as described below.

171

32059L–AVR32–01/2012

AT32UC3B

17.4.1

17.4.2

17.4.3

Module Configuration

Most of the features of the GPIO are configurable for each product. The user must refer to the

Package and Pinout chapter for these settings.

Product specific settings includes:

• Number of I/O pins.

• Functions implemented on each pin

• Peripheral function(s) multiplexed on each I/O pin

• Reset value of registers

Clocks

The clock for the GPIO bus interface (CLK_GPIO) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager.

The CLK_GPIO must be enabled in order to access the configuration registers of the GPIO or to use the GPIO interrupts. After configuring the GPIO, the CLK_GPIO can be disabled if interrupts are not used.

Interrupts

The GPIO interrupt lines are connected to the interrupt controller. Using the GPIO interrupt requires the interrupt controller to be configured first.

17.5 Functional Description

The GPIO controls the I/O lines of the microcontroller. The control logic associated with each pin is represented in the figure below:

172

32059L–AVR32–01/2012

AT32UC3B

Figure 17-2. Overview of the GPIO Pad Connections

ODER

1

Periph. A output enable

Periph. B output enable

Periph. C output enable

Periph. D output enable

0

PMR1

PMR0

Periph. A output data

Periph. B output data

Periph. C output data

Periph. D output data

GPER

0

1

OVR

PUER

PAD

Periph. A input data

Periph. B input data

Periph. C input data

Periph. D input data

PVR

IER

0

Edge Detector

1

1

Glitch Filter

Interrupt Request

0

GFER

IMR1

IMR0

17.5.1

17.5.1.1

Basic Operation

I/O Line or peripheral function selection

When a pin is multiplexed with one or more peripheral functions, the selection is controlled with the GPIO Enable Register (GPER). If a bit in GPER is written to one, the corresponding pin is controlled by the GPIO. If a bit is written to zero, the corresponding pin is controlled by a peripheral function.

17.5.1.2

Peripheral selection

The GPIO provides multiplexing of up to four peripheral functions on a single pin. The selection is performed by accessing Peripheral Mux Register 0 (PMR0) and Peripheral Mux Register 1

(PMR1).

17.5.1.3

Output control

When the I/O line is assigned to a peripheral function, i.e. the corresponding bit in GPER is written to zero, the drive of the I/O line is controlled by the peripheral. The peripheral, depending on the value in PMR0 and PMR1, determines whether the pin is driven or not.

When the I/O line is controlled by the GPIO, the value of the Output Driver Enable Register

(ODER) determines if the pin is driven or not. When a bit in this register is written to one, the cor-

173

32059L–AVR32–01/2012

AT32UC3B

17.5.1.4

17.5.1.5

responding I/O line is driven by the GPIO. When the bit is written to zero, the GPIO does not drive the line.

The level driven on an I/O line can be determined by writing to the Output Value Register (OVR).

Inputs

The level on each I/O line can be read through the Pin Value Register (PVR). This register indicates the level of the I/O lines regardless of whether the lines are driven by the GPIO or by an external component. Note that due to power saving measures, the PVR register can only be read when GPER is written to one for the corresponding pin or if interrupt is enabled for the pin.

Output line timings

The figure below shows the timing of the I/O line when writing a one and a zero to OVR. The same timing applies when performing a ‘set’ or ‘clear’ access, i.e., writing a one to the Output

Value Set Register (OVRS) or the Output Value Clear Register (OVRC). The timing of PVR is also shown.

Figure 17-3. Output Line Timings

CLK_GPIO

Write OVR to 1

Write OVR to 0

OVR / I/O Line

PVR

PB Access

PB Access

17.5.2

17.5.2.1

Advanced Operation

Pull-up resistor control

Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing a one or a zero to the corresponding bit in the Pull-up Enable Register

(PUER). Control of the pull-up resistor is possible whether an I/O line is controlled by a peripheral or the GPIO.

17.5.2.2

Input glitch filter

Optional input glitch filters can be enabled on each I/O line. When the glitch filter is enabled, a glitch with duration of less than 1 clock cycle is automatically rejected, while a pulse with duration of 2 clock cycles or more is accepted. For pulse durations between 1 clock cycle and 2 clock cycles, the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be guaranteed visible it must exceed 2 clock cycles, whereas for a glitch to be reliably filtered out, its duration must not exceed 1 clock cycle. The filter introduces

2 clock cycles of latency.

The glitch filters are controlled by the Glitch Filter Enable Register (GFER). When a bit is written to one in GFER, the glitch filter on the corresponding pin is enabled. The glitch filter affects only interrupt inputs. Inputs to peripherals or the value read through PVR are not affected by the glitch filters.

174

32059L–AVR32–01/2012

AT32UC3B

17.5.3

17.5.4

Interrupts

The GPIO can be configured to generate an interrupt when it detects an input change on an I/O line. The module can be configured to signal an interrupt whenever a pin changes value or only to trigger on rising edges or falling edges. Interrupts are enabled on a pin by writing a one to the corresponding bit in the Interrupt Enable Register (IER). The interrupt mode is set by writing to the Interrupt Mode Register 0 (IMR0) and the Interrupt Mode Register 1(IMR1). Interrupts can be enabled on a pin, regardless of the configuration of the I/O line, i.e. whether it is controlled by the

GPIO or assigned to a peripheral function.

In every port there are four interrupt lines connected to the interrupt controller. Groups of eight interrupts in the port are ORed together to form an interrupt line.

When an interrupt event is detected on an I/O line, and the corresponding bit in IER is written to one, the GPIO interrupt request line is asserted. A number of interrupt signals are ORed-wired together to generate a single interrupt signal to the interrupt controller.

The Interrupt Flag Register (IFR) can by read to determine which pin(s) caused the interrupt.

The interrupt bit must be cleared by writing a one to the Interrupt Flag Clear Register (IFRC). To take effect, the clear operation must be performed when the interrupt line is enabled in IER. Otherwise, it will be ignored.

GPIO interrupts can only be triggered when the CLK_GPIO is enabled.

Interrupt Timings

The figure below shows the timing for rising edge (or pin-change) interrupts when the glitch filter is disabled. For the pulse to be registered, it must be sampled at the rising edge of the clock. In this example, this is not the case for the first pulse. The second pulse is however sampled on a rising edge and will trigger an interrupt request.

Figure 17-4. Interrupt Timing With Glitch Filter Disabled clock

Pin Level

GPIO_IFR

The figure below shows the timing for rising edge (or pin-change) interrupts when the glitch filter is enabled. For the pulse to be registered, it must be sampled on two subsequent rising edges.

In the example, the first pulse is rejected while the second pulse is accepted and causes an interrupt request.

Figure 17-5. Interrupt Timing With Glitch Filter Enabled clock

Pin Level

GPIO_IFR

175

32059L–AVR32–01/2012

AT32UC3B

17.6 User Interface

The GPIO controls all the I/O pins on the AVR32 microcontroller. The pins are managed as 32bit ports that are configurable through a PB interface. Each port has a set of configuration registers. The overall memory map of the GPIO is shown below. The number of pins and hence the number of ports are product specific.

Figure 17-6. Overall Mermory Map

0x0000

Port 0 Configuration Registers

0x0100

Port 1 Configuration Registers

0x0200

Port 2 Configuration Registers

0x0300

Port 3 Configuration Registers

0x0400

Port 4 Configuration Registers

In the GPIO Controller Function Multiplexingtable in the Package and Pinout chapter, each

GPIO line has a unique number. Note that the PA, PB, PC and PX ports do not directly correspond to the GPIO ports. To find the corresponding port and pin the following formula can be used:

GPIO port = floor((GPIO number) / 32), example: floor((36)/32) = 1

GPIO pin = GPIO number mod 32, example: 36 mod 32 = 4

The table below shows the configuration registers for one port. Addresses shown are relative to the port address offset. The specific address of a configuration register is found by adding the

176

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

register offset and the port offset to the GPIO start address. One bit in each of the configuration registers corresponds to an I/O pin.

Table 17-1.

GPIO Register Memory Map

Offset Register Function

0x7C

0x90

0x94

0x98

0x9C

0xA0

0xA4

0xA8

0xAC

0xB0

0x50

0x54

0x58

0x5c

0x60

0x70

0x74

0x78

0x20

0x24

0x28

0x2C

0x40

0x44

0x48

0x4C

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

GPIO Enable Register

GPIO Enable Register

GPIO Enable Register

GPIO Enable Register

Peripheral Mux Register 0

Peripheral Mux Register 0

Peripheral Mux Register 0

Peripheral Mux Register 0

Read/Write

Set

Clear

Toggle

Read/Write

Set

Clear

Toggle

Peripheral Mux Register 1

Peripheral Mux Register 1

Peripheral Mux Register 1

Peripheral Mux Register 1

Read/Write

Set

Clear

Toggle

Output Driver Enable Register Read/Write

Output Driver Enable Register Set

Output Driver Enable Register

Output Driver Enable Register

Clear

Toggle

Output Value Register

Output Value Register

Output Value Register

Output Value Register

Pin Value Register

Pull-up Enable Register

Pull-up Enable Register

Pull-up Enable Register

Pull-up Enable Register

Interrupt Enable Register

Interrupt Enable Register

Interrupt Enable Register

Interrupt Enable Register

Interrupt Mode Register 0

Interrupt Mode Register 0

Interrupt Mode Register 0

Interrupt Mode Register 0

Interrupt Mode Register 1

Read/Write

Set

Clear

Toggle

Read

Read/Write

Set

Clear

Toggle

Read/Write

Set

Clear

Toggle

Read/Write

Set

Clear

Toggle

Read/Write

Reset value

(1)

(1)

(1)

(1)

(1)

(2)

(1)

(1)

(1)

(1)

PUERS

PUERC

PUERT

IER

IERS

IERC

IERT

IMR0

ODERC

ODERT

OVR

OVRS

OVRC

OVRT

PVR

PUER

IMR0S

IMR0C

IMR0T

IMR1

PMR0C

PMR0T

PMR1

PMR1S

PMR1C

PMR1T

ODER

ODERS

Name

GPER

GPERS

GPERC

GPERT

PMR0

PMR0S

Write-Only

Write-Only

Read/Write

Write-Only

Write-Only

Write-Only

Read-Only

Read/Write

Write-Only

Write-Only

Write-Only

Read/Write

Write-Only

Write-Only

Write-Only

Read/Write

Write-Only

Write-Only

Write-Only

Read/Write

Access

Read/Write

Write-Only

Write-Only

Write-Only

Read/Write

Write-Only

Write-Only

Write-Only

Read/Write

Write-Only

Write-Only

Write-Only

Read/Write

Write-Only

177

AT32UC3B

17.6.1

Table 17-1.

GPIO Register Memory Map

0xC8

0xCC

0xD0

0xD4

0xD8

0xDC

Offset

0xB4

0xB8

0xBC

0xC0

0xC4

Register

Interrupt Mode Register 1

Function

Set

Interrupt Mode Register 1

Interrupt Mode Register 1

Clear

Toggle

Glitch Filter Enable Register Read/Write

Glitch Filter Enable Register Set

Glitch Filter Enable Register

Glitch Filter Enable Register

Interrupt Flag Register

Interrupt Flag Register

Interrupt Flag Register

Interrupt Flag Register

Clear

Toggle

Read

-

Clear

-

Name

IMR1S

IMR1C

IMR1T

GFER

GFERS

GFERC

GFERT

IFR

-

IFRC

-

Access

Write-Only

Write-Only

Write-Only

Read/Write

Write-Only

Write-Only

Write-Only

Read-Only

-

Write-Only

-

Reset value

(1)

(1)

1) The reset value for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter.

2) The reset value is undefined depending on the pin states.

Access Types

Each configuration register can be accessed in four different ways. The first address location can be used to write the register directly. This address can also be used to read the register value. The following addresses facilitate three different types of write access to the register. Performing a “set” access, all bits written to one will be set. Bits written to zero will be unchanged by the operation. Performing a “clear” access, all bits written to one will be cleared. Bits written to zero will be unchanged by the operation. Finally, a toggle access will toggle the value of all bits written to one. Again all bits written to zero remain unchanged. Note that for some registers (e.g.

IFR), not all access methods are permitted.

Note that for ports with less than 32 bits, the corresponding control registers will have unused bits. This is also the case for features that are not implemented for a specific pin. Writing to an unused bit will have no effect. Reading unused bits will always return 0.

178

32059L–AVR32–01/2012

17.6.2

Name:

Enable Register

GPER

Access Type:

Offset:

Reset Value: -

Read, Write, Set, Clear, Toggle

0x00, 0x04, 0x08, 0x0C

31

P31

23

P23

15

P15

30

P30

22

P22

14

P14

29

P29

21

P21

13

P13

7

P7

6

P6

5

P5

4

P4

• P0-P31: Pin Enable

0: A peripheral function controls the corresponding pin.

1: The GPIO controls the corresponding pin.

28

P28

20

P20

12

P12

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

AT32UC3B

24

P24

16

P16

8

P8

0

P0

179

32059L–AVR32–01/2012

17.6.3

Name:

Peripheral Mux Register 0

PMR0

Access Type:

Offset:

Reset Value: -

Read, Write, Set, Clear, Toggle

0x10, 0x14, 0x18, 0x1C

31

P31

23

P23

15

P15

30

P30

22

P22

14

P14

7

P7

6

P6

5

P5

• P0-31: Peripheral Multiplexer Select bit 0

29

P29

21

P21

13

P13

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

AT32UC3B

24

P24

16

P16

8

P8

0

P0

180

32059L–AVR32–01/2012

17.6.4

Name:

Peripheral Mux Register 1

PMR1

Access Type:

Offset:

Reset Value: -

Read, Write, Set, Clear, Toggle

0x20, 0x24, 0x28, 0x2C

31

P31

23

P23

15

P15

30

P30

22

P22

14

P14

29

P29

21

P21

13

P13

28

P28

20

P20

12

P12

7

P7

6

P6

5

P5

4

P4

3

P3

• P0-31: Peripheral Multiplexer Select bit 1

{PMR1, PMR0}

00

01

10

11

Selected Peripheral Function

A

B

C

D

27

P27

19

P19

11

P11

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

AT32UC3B

24

P24

16

P16

8

P8

0

P0

181

32059L–AVR32–01/2012

17.6.5

Name:

Output Driver Enable Register

ODER

Access Type:

Offset:

Reset Value: -

Read, Write, Set, Clear, Toggle

0x40, 0x44, 0x48, 0x4C

31

P31

23

P23

15

P15

30

P30

22

P22

14

P14

29

P29

21

P21

13

P13

28

P28

20

P20

12

P12

7

P7

6

P6

5

P5

4

P4

• P0-31: Output Driver Enable

0: The output driver is disabled for the corresponding pin.

1: The output driver is enabled for the corresponding pin.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

AT32UC3B

24

P24

16

P16

8

P8

0

P0

182

32059L–AVR32–01/2012

17.6.6

Name:

Output Value Register

OVR

Access Type:

Offset:

Reset Value: -

Read, Write, Set, Clear, Toggle

0x50, 0x54, 0x58, 0x5C

31

P31

23

P23

15

P15

30

P30

22

P22

14

P14

29

P29

21

P21

13

P13

7

P7

6

P6

5

P5

• P0-31: Output Value

0: The value to be driven on the I/O line is 0.

1: The value to be driven on the I/O line is 1.

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

AT32UC3B

24

P24

16

P16

8

P8

0

P0

183

32059L–AVR32–01/2012

17.6.7

Name:

Pin Value Register

PVR

Access Type:

Offset:

Reset Value: -

Read

0x60, 0x64, 0x68, 0x6C

31

P31

23

P23

15

P15

30

P30

22

P22

14

P14

29

P29

21

P21

13

P13

28

P28

20

P20

12

P12

27

P27

19

P19

11

P11

26

P26

18

P18

10

P10

7

P7

6

P6

5

P5

4

P4

3

P3

2

P2

• P0-31: Pin Value

0: The I/O line is at level ‘0’.

1: The I/O line is at level ‘1’.

Note that the level of a pin can only be read when GPER is set or interrupt is enabled for the pin.

1

P1

25

P25

17

P17

9

P9

AT32UC3B

24

P24

16

P16

8

P8

0

P0

184

32059L–AVR32–01/2012

17.6.8

Name:

Pull-up Enable Register

PUER

Access Type:

Offset:

Reset Value: -

Read, Write, Set, Clear, Toggle

0x70, 0x74, 0x78, 0x7C

31

P31

23

P23

15

P15

30

P30

22

P22

14

P14

29

P29

21

P21

13

P13

28

P28

20

P20

12

P12

7

P7

6

P6

5

P5

4

P4

• P0-31: Pull-up Enable

0: The internal pull-up resistor is disabled for the corresponding pin.

1: The internal pull-up resistor is enabled for the corresponding pin.

3

P3

27

P27

19

P19

11

P11

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

AT32UC3B

24

P24

16

P16

8

P8

0

P0

185

32059L–AVR32–01/2012

17.6.9

Name:

Interrupt Enable Register

IER

Access Type:

Offset:

Reset Value: -

Read, Write, Set, Clear, Toggle

0x90, 0x94, 0x98, 0x9C

31

P31

23

P23

15

P15

30

P30

22

P22

14

P14

29

P29

21

P21

13

P13

7

P7

6

P6

5

P5

• P0-31: Interrupt Enable

0: Interrupt is disabled for the corresponding pin.

1: Interrupt is enabled for the corresponding pin.

4

P4

28

P28

20

P20

12

P12

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

AT32UC3B

24

P24

16

P16

8

P8

0

P0

186

32059L–AVR32–01/2012

17.6.10

Interrupt Mode Register 0

Name:

IMR0

Access Type:

Offset:

Reset Value: -

Read, Write, Set, Clear, Toggle

0xA0, 0xA4, 0xA8, 0xAC

31

P31

23

P23

15

P15

30

P30

22

P22

14

P14

7

P7

6

P6

• P0-31: Interrupt Mode Bit 0

29

P29

21

P21

13

P13

5

P5

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

AT32UC3B

24

P24

16

P16

8

P8

0

P0

187

32059L–AVR32–01/2012

17.6.11

Interrupt Mode Register 1

Name:

IMR1

Access Type:

Offset:

Reset Value: -

Read, Write, Set, Clear, Toggle

0xB0, 0xB4, 0xB8, 0xBC

31

P31

23

P23

15

P15

30

P30

22

P22

14

P14

7

P7

6

P6

• P0-31: Interrupt Mode Bit 1

{IMR1, IMR0}

00

01

10

11

29

P29

21

P21

13

P13

5

P5

28

P28

20

P20

12

P12

4

P4

Interrupt Mode

Pin Change

Rising Edge

Falling Edge

Reserved

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

AT32UC3B

24

P24

16

P16

8

P8

0

P0

188

32059L–AVR32–01/2012

AT32UC3B

17.6.12

Glitch Filter Enable Register

Name:

GFER

Access Type:

Offset:

Reset Value: -

Read, Write, Set, Clear, Toggle

0xC0, 0xC4, 0xC8, 0xCC

31

P31

23

P23

15

P15

30

P30

22

P22

14

P14

29

P29

21

P21

13

P13

28

P28

20

P20

12

P12

27

P27

19

P19

11

P11

26

P26

18

P18

10

P10

25

P25

17

P17

9

P9

24

P24

7

P7

6

P6

5

P5

4

P4

3

P3

2

P2

1

P1

• P0-31: Glitch Filter Enable

0: Glitch filter is disabled for the corresponding pin.

1: Glitch filter is enabled for the corresponding pin.

NOTE! The value of this register should only be changed when IER is ‘0’. Updating this GFER while interrupt on the corresponding pin is enabled can cause an unintentional interrupt to be triggered.

0

P0

16

P16

8

P8

189

32059L–AVR32–01/2012

AT32UC3B

17.6.13

Interrupt Flag Register

Name:

IFR

Access Type:

Offset:

Reset Value: -

Read, Clear

0xD0, 0xD8

31

P31

23

P23

15

P15

30

P30

22

P22

14

P14

29

P29

21

P21

13

P13

28

P28

20

P20

12

P12

27

P27

19

P19

11

P11

26

P26

18

P18

10

P10

25

P25

17

P17

9

P9

7

P7

6

P6

5

P5

4

P4

3

P3

2

P2

1

P1

• P0-31: Interrupt Flag

1: An interrupt condition has been detected on the corresponding pin.

0: No interrupt condition has beedn detected on the corresponding pin since reset or the last time it was cleared.

The number of interrupt request lines is dependant on the number of I/O pins on the MCU. Refer to the product specific data for details. Note also that a bit in the Interrupt Flag register is only valid if the corresponding bit in IER is set.

24

P24

16

P16

8

P8

0

P0

190

32059L–AVR32–01/2012

AT32UC3B

17.7 Programming Examples

17.7.1

8-bit LED-Chaser

// Set R0 to GPIO base address

mov R0, LO(AVR32_GPIO_ADDRESS)

orh R0, HI(AVR32_GPIO_ADDRESS)

// Enable GPIO control of pin 0-8

mov R1, 0xFF

st.w R0[AVR32_GPIO_GPERS], R1

// Set initial value of port

mov R2, 0x01

st.w R0[AVR32_GPIO_OVRS], R2

// Set up toggle value. Two pins are toggled

// in each round. The bit that is currently set,

// and the next bit to be set.

mov R2, 0x0303

orh R2, 0x0303

17.7.2

loop:

// Only change 8 LSB

mov R3, 0x00FF

and R3, R2

st.w R0[AVR32_GPIO_OVRT], R3

rol R2

rcall delay

rjmp loop

It is assumed in this example that a subroutine "delay" exists that returns after a given time.

Configuration of USART pins

The example below shows how to configure a peripheral module to control I/O pins. It assumed in this example that the USART receive pin (RXD) is connected to PC16 and that the USART transmit pin (TXD) is connected to PC17. For both pins, the USART is peripheral B. In this example, the state of the GPIO registers is assumed to be unknown. The two USART pins are therefore first set to be controlled by the GPIO with output drivers disabled. The pins can then be assured to be tri-stated while changing the Peripheral Mux Registers.

// Set up pointer to GPIO, PORTC

mov R0, LO(AVR32_GPIO_ADDRESS + PORTC_OFFSET)

orh R0, HI(AVR32_GPIO_ADDRESS + PORTC_OFFSET)

// Disable output drivers

191

32059L–AVR32–01/2012

mov R1, 0x0000

orh R1, 0x0003

st.w R0[AVR32_GPIO_ODERC], R1

// Make the GPIO control the pins

st.w R0[AVR32_GPIO_GPERS], R1

// Select peripheral B on PC16-PC17

st.w R0[AVR32_GPIO_PMR0S], R1

st.w R0[AVR32_GPIO_PMR1C], R1

// Enable peripheral control

st.w R0[AVR32_GPIO_GPERC], R1

AT32UC3B

32059L–AVR32–01/2012

192

AT32UC3B

17.8 Module Configuration

The specific configuration for each GPIO instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details.

Table 17-2.

Module Configuration

Feature

Number of GPIO ports

Number of peripheral functions

GPIO

2

4

Table 17-3.

Module Clock Name

Module Name Clock Name

GPIO

CLK_GPIO

The reset values for all GPIO registers are zero, with the following exceptions:

IMR1

GFER

IFR

GPER

PMR0

PMR1

ODER

OVR

GPER

PMR0

PMR1

ODER

OVR

PUER

IER

IMR0

PUER

IER

IMR0

IMR1

GFER

IFR

Table 17-4.

Register Reset Values

Port Register Reset Value

1

1

1

1

0

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0xFFFFFFFF

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0xFFFFFFFF

0x00000FFF

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000FFF

193

32059L–AVR32–01/2012

AT32UC3B

18. Serial Peripheral Interface (SPI)

Rev. 1.9.9.2

18.1 Features

Supports Communication with Serial External Devices

– Four Chip Selects with External Decoder Support Allow Communication with Up to 15

Peripherals

– Serial Memories, such as DataFlash and 3-wire EEPROMs

– Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors

– External Co-processors

Master or Slave Serial Peripheral Bus Interface

– 8 - to 16-bit Programmable Data Length Per Chip Select

– Programmable Phase and Polarity Per Chip Select

– Programmable Transfer Delays Between Consecutive Transfers and Between Clock and Data

Per Chip Select

– Programmable Delay Between Consecutive Transfers

– Selectable Mode Fault Detection

Connection to PDCA Channel Capabilities Optimizes Data Transfers

– One Channel for the Receiver, One Channel for the Transmitter

– Next Buffer Support

18.2 Overview

The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system.

The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master.

Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master

Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time.

A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS).

The SPI system consists of two data lines and two control lines:

• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s).

• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer.

• Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted.

• Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.

194

32059L–AVR32–01/2012

18.3 Block Diagram

Figure 18-1. Block Diagram

PDCA

Peripheral Bus

CLK_SPI

DIV

CLK_SPI

32

Spi Interface

Interrupt Control

GPIO

SPI Interrupt

18.4 Application Block Diagram

Figure 18-2. Application Block Diagram: Single Master/Multiple Slave Implementation

Spi Master

SPCK

MISO

MOSI

NPCS0

NPCS1

NPCS2

NPCS3

NC

SPCK

MISO

MOSI

NSS

SPCK

MISO

MOSI

NSS

Slave 0

Slave 1

SPCK

MISO

MOSI

NSS

Slave 2

SPCK

MISO

MOSI

NPCS0/NSS

NPCS1

NPCS2

NPCS3

AT32UC3B

195

32059L–AVR32–01/2012

AT32UC3B

18.5 Signal Description

Table 18-1.

Pin Name

MISO

MOSI

SPCK

NPCS1-NPCS3

NPCS0/NSS

Pin Description

Master In Slave Out

Master Out Slave In

Serial Clock

Peripheral Chip Selects

Peripheral Chip Select/Slave Select

Master

Input

Output

Output

Output

Output

Type

Slave

Output

Input

Input

Unused

Input

18.6 Product Dependencies

18.6.1

18.6.2

I/O Lines

The pins used for interfacing the compliant external devices may be multiplexed with GPIO lines.

The programmer must first program the GPIO controller to assign the SPI pins to their peripheral functions.To use the local loopback function the SPI pins must be controlled by the SPI.

Power Management

The SPI may be clocked through the Power Manager, Before using the SPI, the programmer must ensure that the SPI clock is enabled in the Power Manager.

In the SPI description, CLK_SPI is the clock of the peripheral bus to which the SPI is connected.

18.6.3

Interrupt

The SPI interface has an interrupt line connected to the Interrupt Controller (INTC). Handling the

SPI interrupt requires programming the INTC before configuring the SPI.

18.7 Functional Description

18.7.1

18.7.2

Modes of Operation

The SPI operates in Master Mode or in Slave Mode.

Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register.

The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter.

If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a

Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes.

The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode.

Data Transfer

Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with

196

32059L–AVR32–01/2012

AT32UC3B

the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave.

Table 18-2

shows the four modes and corresponding parameter settings.

Table 18-2.

SPI modes

SPI Mode

0

1

2

3

CPOL

0

0

1

1

NCPHA

1

0

1

0

Figure 18-3 on page 197 and Figure 18-4 on page 197

show examples of data transfers.

Figure 18-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)

SPCK cycle (for reference)

SPCK

(CPOL = 0)

SPCK

(CPOL = 1)

MOSI

(from master)

MISO

(from slave)

MSB

1

MSB

2

6

6

3

5

5

4

4

4

5

3

3

NSS

(to slave)

*** Not Defined, but normaly MSB of previous character received

Figure 18-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)

SPCK cycle (for reference)

1

2

3 4 5 6

SPCK

(CPOL = 0)

6

2

2

7

7

1

1

8

8

LSB

LSB

SPCK

(CPOL = 1)

MOSI

(from master)

MISO

(from slave)

NSS

(to slave)

***

MSB

MSB

6

6

5

5

4

4

3

3

2

2

1

1

LSB

LSB

***

197

32059L–AVR32–01/2012

AT32UC3B

18.7.3

Master Mode Operations

When configured in Master Mode, the SPI uses the internal programmable baud rate generator as clock source. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK).

The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register. The holding registers maintain the data flow at a constant rate.

After enabling the SPI, a data transfer begins when the processor writes to the TDR (Transmit

Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception.

Before writing the TDR, the PCS field must be set in order to select a slave.

If new data is written in TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to RDR, the data in TDR is loaded in the Shift Register and a new transfer starts.

The transfer of a data written in TDR in the Shift Register is indicated by the TDRE bit (Transmit

Data Register Empty) in the Status Register (SR). When new data is written in TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit Peripheral DMA Controller channel.

The end of transfer is indicated by the TXEMPTY flag in the SR register. If a transfer delay (DLY-

BCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay.

The CLK_SPI can be switched off at this time.

The transfer of received data from the Shift Register in RDR is indicated by the RDRF bit

(Receive Data Register Full) in the Status Register (SR). When the received data is read, the

RDRF bit is cleared.

If the RDR (Receive Data Register) has not been read before new data is received, the Overrun

Error bit (OVRES) in SR is set. When this bit is set the SPI will continue to update RDR when data is received, overwriting the previously received data. The user has to read the status register to clear the OVRES bit.

Figure 18-5 on page 199

shows a block diagram of the SPI when operating in Master Mode. Figure 18-6 on page 200 shows a flow chart describing how transfers are handled.

198

32059L–AVR32–01/2012

AT32UC3B

18.7.3.1

Master Mode Block Diagram

Figure 18-5. Master Mode Block Diagram

CSR0..3

SCBR

CLK_SPI

Baud Rate Generator

SPI

Clock

MISO

CSR0..3

BITS

NCPHA

CPOL

LSB

Shift Register

TDR

TD

MSB

RDR

RD

TDRE

SPCK

MOSI

RDRF

OVRES

MR

TDR

PCS

PCS

PS

0

CSR0..3

CSAAT

PCSDEC

Current

Peripheral

1

MSTR

NPCS0

MODFDIS

RDR

MODF

NPCS3

NPCS2

NPCS1

NPCS0

199

32059L–AVR32–01/2012

18.7.3.2

Master Mode Flow Diagram

Figure 18-6. Master Mode Flow Diagram

AT32UC3B

32059L–AVR32–01/2012

200

AT32UC3B

18.7.3.3

18.7.3.4

Clock Generation

The SPI Baud rate clock is generated by dividing the CLK_SPI by a value between 1 and 255.

This allows a maximum operating baud rate at up to CLK_SPI and a minimum operating baud rate of CLK_SPI divided by 255.

Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.

At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.

The divisor can be defined independently for each chip select, as it has to be programmed in the

SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming.

Transfer Delays

Figure 18-7 on page 201 shows a chip select transfer change and consecutive transfers on the

same chip select. Three delays can be programmed to modify the transfer waveforms:

• The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one.

• The delay before SPCK, independently programmable for each chip select by writing the field

DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted.

• The delay between consecutive transfers, independently programmable for each chip select by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select

These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.

Figure 18-7. Programmable Delays

Chip Select 1

Chip Select 2

SPCK

DLYBCS DLYBS DLYBCT DLYBCT

201

32059L–AVR32–01/2012

AT32UC3B

18.7.3.5

18.7.3.6

18.7.3.7

Peripheral Selection

The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer.

The peripheral selection can be performed in two different ways:

• Fixed Peripheral Select: SPI exchanges data with only one peripheral

• Variable Peripheral Select: Data can be exchanged with more than one peripheral

Fixed Peripheral Select is activated by writing the PS bit to zero in MR (Mode Register). In this case, the current peripheral is defined by the PCS field in MR and the PCS field in the TDR has no effect.

Variable Peripheral Select is activated by setting PS bit to one. The PCS field in TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data.

The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the Peripheral DMA Controller is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the

Mode Register to be reprogrammed.

The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the Peripheral DMA Controller in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the

MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor.

Peripheral Chip Select Decoding

The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip

Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCS-

DEC bit at 1 in the Mode Register (MR).

When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low.

When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the Mode Register or the Transmit Data Register (depending on PS).

As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded.

The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the

PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.

Peripheral Deselection

When operating normally, as soon as the transfer of the last data written in TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding

202

32059L–AVR32–01/2012

AT32UC3B

to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers.

To facilitate interfacing with such devices, the Chip Select Register can be programmed with the

CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required.

Figure 18-8 on page 203 shows different peripheral deselection cases and the effect of the

CSAAT bits.

Figure 18-8. Peripheral Deselection

CSAAT = 0 CSAAT = 1

TDRE

NPCS[0..3] A

DLYBCT

A

DLYBCT

DLYBCS

PCS = A

A A

DLYBCS

PCS = A

A

Write SPI_TDR

TDRE

NPCS[0..3] A

DLYBCT

DLYBCS

PCS=A

A

Write SPI_TDR

A

DLYBCT

A

DLYBCS

PCS = A

A

TDRE

NPCS[0..3]

DLYBCT DLYBCT

A B A B

DLYBCS

PCS = B PCS = B

DLYBCS

Write SPI_TDR

18.7.3.8

Mode Fault Detection

A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be configured in open drain through the GPIO controller, so that external pull up resistors are needed to guarantee high level.

When a mode fault is detected, the MODF bit in the SR is set until the SR is read and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the CR (Control Register) at 1.

By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (MR).

203

32059L–AVR32–01/2012

AT32UC3B

18.7.4

SPI Slave Mode

When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK).

The SPI waits for NSS to go active before receiving the serial clock from an external master.

When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI is programmed in Slave Mode.

The bits are shifted out on the MISO line and sampled on the MOSI line.

When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If the RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SR is set. Data is loaded in RDR even if this flag is set. The user has to read the status register to clear the OVRES bit.

When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the Transmit Data Register (TDR), the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0.

When a first data is written in TDR, it is transferred immediately in the Shift Register and the

TDRE bit rises. If new data is written, it remains in TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent updates of critical variables with single transfers.

Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be transmitted, i.e. no character has been written in TDR since the last load from TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted.

Figure 18-9 on page 205 shows a block diagram of the SPI when operating in Slave Mode.

204

32059L–AVR32–01/2012

AT32UC3B

Figure 18-9. Slave Mode Functional Block Diagram

SPCK

NSS

SPIEN

SPIENS

SPIDIS

SPI_CSR0

BITS

NCPHA

CPOL

LSB

MOSI

SPI

Clock

SPI_RDR

RD

Shift Register

MSB

RDRF

OVRES

FLOAD

SPI_TDR

TD

TDRE

MISO

32059L–AVR32–01/2012

205

18.8 User Interface

Table 18-3.

SPI Register Memory Map

Offset

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

Control Register

Mode Register

Receive Data Register

Transmit Data Register

Status Register

Interrupt Enable Register

Interrupt Disable Register

CR

MR

RDR

TDR

SR

IER

IDR

0x1C

0x30

0x34

0x38

Interrupt Mask Register

Chip Select Register 0

Chip Select Register 1

Chip Select Register 2

IMR

CSR0

CSR1

CSR2

0x3C

0x00FC

Chip Select Register 3

Version Register

CSR3

VERSION

Note: 1. Values in the Version Register vary with the version of the IP block implementation.

Write-only

Read/write

Read-only

Write-only

Read-only

Write-only

Write-only

Read-only

Read/write

Read/write

Read/write

Read/write

Read-only

AT32UC3B

Reset

0x00000000

0x00000000

0x00000000

0x00000000

0x000000F0

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x-

(1)

206

32059L–AVR32–01/2012

AT32UC3B

18.8.1

Control Register

Name: CR

Access Type: Write-only

Offset:

0x00

Reset Value:

0x00000000

31

23

15

7

SWRST

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

1

SPIDIS

24

LASTXFER

16

8

-

0

SPIEN

• LASTXFER: Last Transfer

0: No effect.

1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.

• SWRST: SPI Software Reset

0: No effect.

1: Reset the SPI. A software-triggered hardware reset of the SPI interface is performed.

The SPI is in slave mode after software reset.

Peripheral DMA Controller

channels are not affected by software reset.

• SPIDIS: SPI Disable

0: No effect.

1: Disables the SPI.

As soon as SPIDIS is set, SPI finishes its tranfer.

All pins are set in input mode and no data is received or transmitted.

If a transfer is in progress, the transfer is finished before the SPI is disabled.

If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.

• SPIEN: SPI Enable

0: No effect.

1: Enables the SPI to transfer and receive data.

207

32059L–AVR32–01/2012

AT32UC3B

18.8.2

Mode Register

Name: MR

Access Type: Read/Write

Offset:

0x04

Reset Value:

0x00000000

31 30 29

23

15

7

LLB

22

14

6

-

21

13

5

-

28

DLYBCS

20

12

4

MODFDIS

27

19

11

3

26

18

10

2

PCSDEC

PCS

25

17

9

1

PS

• DLYBCS: Delay Between Chip Selects

This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees nonoverlapping chip selects and solves bus contentions in case of peripherals having long data float times.

If DLYBCS is less than or equal to six, six CLK_SPI periods will be inserted by default.

Otherwise, the following equation determines the delay:

24

16

8

0

MSTR

Delay Between Chip Selects

=

CLKSPI

• PCS: Peripheral Chip Select

This field is only used if Fixed Peripheral Select is active (PS = 0).

If PCSDEC = 0:

PCS = xxx0NPCS[3:0] = 1110

PCS = xx01NPCS[3:0] = 1101

PCS = x011NPCS[3:0] = 1011

PCS = 0111NPCS[3:0] = 0111

PCS = 1111forbidden (no peripheral is selected)

(x = don’t care)

If PCSDEC = 1:

NPCS[3:0] output signals = PCS.

• LLB: Local Loopback Enable

0: Local loopback path disabled.

1: Local loopback path enabled (

LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.)

• MODFDIS: Mode Fault Detection

0: Mode fault detection is enabled.

1: Mode fault detection is disabled.

• PCSDEC: Chip Select Decode

0: The chip selects are directly connected to a peripheral device.

1: The four chip select lines are connected to a 4- to 16-bit decoder.

When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules:

CSR0 defines peripheral chip select signals 0 to 3.

CSR1 defines peripheral chip select signals 4 to 7.

CSR2 defines peripheral chip select signals 8 to 11.

208

32059L–AVR32–01/2012

CSR3 defines peripheral chip select signals 12 to 14.

• PS: Peripheral Select

0: Fixed Peripheral Select.

1: Variable Peripheral Select.

• MSTR: Master/Slave Mode

0: SPI is in Slave mode.

1: SPI is in Master mode.

AT32UC3B

32059L–AVR32–01/2012

209

18.8.3

Receive Data Register

Name: RDR

Access Type: Read-only

Offset:

Reset Value:

0x08

0x00000000

31

23

15

30

22

14

29

21

13

28

20

12

27

19

11

26

18

10

RD

7 6 5 4 3 2

RD

• RD: Receive Data

Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.

25

17

9

1

AT32UC3B

24

16

8

0

210

32059L–AVR32–01/2012

AT32UC3B

18.8.4

Transmit Data Register

Name: TDR

Access Type: Write-only

Offset:

0x0C

Reset Value:

0x00000000

31

23

15

30

22

14

29

21

13

28

20

12

27

19

11

26

18

10

PCS

25

17

9

24

LASTXFER

16

8

TD

7 6 5 4 3 2 1 0

TD

• LASTXFER: Last Transfer

0: No effect.

1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.

This field is only used if Variable Peripheral Select is active (PS = 1).

• PCS: Peripheral Chip Select

This field is only used if Variable Peripheral Select is active (PS = 1).

If PCSDEC = 0:

PCS = xxx0NPCS[3:0] = 1110

PCS = xx01NPCS[3:0] = 1101

PCS = x011NPCS[3:0] = 1011

PCS = 0111NPCS[3:0] = 0111

PCS = 1111forbidden (no peripheral is selected)

(x = don’t care)

If PCSDEC = 1:

NPCS[3:0] output signals = PCS

• TD: Transmit Data

Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.

211

32059L–AVR32–01/2012

AT32UC3B

18.8.5

Status Register

Name: SR

Access Type: Read-only

Offset:

Reset Value:

0x10

0x00000000

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

OVRES

26

18

10

-

2

MODF

25

17

9

TXEMPTY

1

TDRE

24

16

SPIENS

8

NSSR

0

RDRF

• SPIENS: SPI Enable Status

0: SPI is disabled.

1: SPI is enabled.

• TXEMPTY: Transmission Registers Empty

0: As soon as data is written in TDR.

1: TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.

• NSSR: NSS Rising

0: No rising edge detected on NSS pin since last read.

1: A rising edge occurred on NSS pin since last read.

• OVRES: Overrun Error Status

0: No overrun has been detected since the last read of SR.

1: An overrun has occurred since the last read of SR.

An overrun occurs when RDR is loaded at least twice from the serializer since the last read of the RDR.

• MODF: Mode Fault Error

0: No Mode Fault has been detected since the last read of SR.

1: A Mode Fault occurred since the last read of the SR.

• TDRE: Transmit Data Register Empty

0: Data has been written to TDR and not yet transferred to the serializer.

1: The last data written in the Transmit Data Register has been transferred to the serializer.

TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.

• RDRF: Receive Data Register Full

0: No data has been received since the last read of RDR

1: Data has been received and the received data has been transferred from the serializer to RDR since the last read of RDR.

212

32059L–AVR32–01/2012

18.8.6

Interrupt Enable Register

Name: IER

Access Type: Write-only

Offset:

Reset Value:

0x14

0x00000000

31

23

15

7

30

22

14

6

29

21

13

5

AT32UC3B

26

18

10

-

2

MODF

25

17

9

TXEMPTY

1

TDRE

24

16

8

NSSR

0

RDRF

32059L–AVR32–01/2012

213

AT32UC3B

18.8.7

Interrupt Disable Register

Name: IDR

Access Type: Write-only

Offset:

Reset Value:

0x18

0x00000000

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

OVRES

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will clear the corresponding bit in IMR.

26

18

10

-

2

MODF

25

17

9

TXEMPTY

1

TDRE

24

16

8

NSSR

0

RDRF

214

32059L–AVR32–01/2012

AT32UC3B

18.8.8

Interrupt Mask Register

Name: IMR

Access Type: Read-only

Offset:

Reset Value:

0x1C

0x00000000

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

OVRES

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

A bit in this register is cleared when the corresponding bit in IDR is written to one.

A bit in this register is set when the corresponding bit in IER is written to one.

26

18

10

-

2

MODF

25

17

9

TXEMPTY

1

TDRE

24

16

8

NSSR

0

RDRF

215

32059L–AVR32–01/2012

AT32UC3B

18.8.9

Chip Select Register n

Name: CSRn

Access Type: Read/Write

Offset:

Reset Value:

0x30 +0x04*n

0x00000000

31 30 29 28 27 26 25 24

DLYBCT

23 22 21 20 19 18 17 16

DLYBS

15 14 13 12 11 10 9 8

SCBR

7 6

BITS

5 4 3

CSAAT

2

CSNAAT

1

NCPHA

0

CPOL

• DLYBCT: Delay Between Consecutive Transfers

This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed.

When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers.

Otherwise, the following equation determines the delay:

Delay Between Consecutive Transfers =

CLKSPI

• DLYBS: Delay Before SPCK

This field defines the delay from NPCS valid to the first valid SPCK transition.

When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.

Otherwise, the following equations determine the delay:

I

Delay Before SPCK

=

CLKSPI

• ISCBR: Serial Clock Baud Rate

In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:

SPCK Baudrate

=

SCBR

Writing 0 to the SCBR field is forbidden. Triggering a transfer while SCBR is 0 can lead to unpredictable results.

At reset, SCBR is 0 and the user has to write it at a valid value before performing the first transfer.

IIf a clock divider (SCBRn) is set to 1 and the other SCBR differ from 1, access on CSn is correct but no correct access will be possible on others CS.

216

32059L–AVR32–01/2012

AT32UC3B

• BITS: Bits Per Transfer

The BITS field determines the number of data bits transferred. Reserved values should not be used.

0111

1000

1001

1010

1011

1100

1101

1110

1111

BITS

0000

0001

0010

0011

0100

0101

0110

Bits Per Transfer

8

9

10

11

12

13

14

15

16

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

• CSAAT: Chip Select Active After Transfer

0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved.

1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select.

• CSNAAT: Chip Select Not Active After Transfer

0 = The Peripheral Chip Select Line rises as soon as the last transfer is acheived

1 = The Peripheral Chip Select Line rises after every transfer

CSNAAT can be used to force the Peripheral Chip Select Line to go inactive after every transfer. This allows successful interfacing to SPI slave devices that require this behavior.

• NCPHA: Clock Phase

0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.

1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.

NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices.

• CPOL: Clock Polarity

0: The inactive state value of SPCK is logic level zero.

1: The inactive state value of SPCK is logic level one.

CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.

217

32059L–AVR32–01/2012

AT32UC3B

19. Two-Wire Interface (TWI)

2.1.1.1

19.1 Features

Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices

(1)

One, Two or Three Bytes for Slave Address

Sequential Read-write Operations

Master, Multi-master and Slave Mode Operation

Bit Rate: Up to 400 Kbits

General Call Supported in Slave mode

Connection to Peripheral DMA Controller Channel Capabilities Optimizes Data Transfers in

Master Mode Only

– One Channel for the Receiver, One Channel for the Transmitter

– Next Buffer Support

Note: 1. See

Table 19-1

below for details on compatibility with I²C Standard.

19.2 Overview

The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial

EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD

Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master or a slave with sequential or single-byte access. Multiple master capability is supported. Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is lost.

A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies.

Below,

Table 19-1

lists the compatibility level of the Atmel Two-wire Interface in Master Mode and

a full I

2

C compatible device.

Table 19-1.

Atmel TWI compatibility with I

2

C Standard

I2C Standard

Standard Mode Speed (100 KHz)

Fast Mode Speed (400 KHz)

7 or 10 bits Slave Addressing

START BYTE

(1)

Repeated Start (Sr) Condition

ACK and NACK Management

Slope control and input filtering (Fast mode)

Clock stretching

Atmel TWI

Supported

Supported

Supported

Not Supported

Supported

Supported

Not Supported

Supported

Note: 1. START + b000000001 + Ack + Sr

218

32059L–AVR32–01/2012

AT32UC3B

19.3 List of Abbreviations

Table 19-2.

Abbreviations

Abbreviation

TWI

A

NA

P

S

Sr

SADR

ADR

R

W

Description

Two-wire Interface

Acknowledge

Non Acknowledge

Stop

Start

Repeated Start

Slave Address

Any address except SADR

Read

Write

19.4 Block Diagram

Figure 19-1. Block Diagram

Peripheral

Bus Bridge

I/O controller

Power

Manager

CLK_TWI

Two-wire

Interface

TWI Interrupt

INTC

TWCK

TWD

219

32059L–AVR32–01/2012

AT32UC3B

19.5 Application Block Diagram

Figure 19-2. Application Block Diagram

VDD

Rp Rp

Host with

TWI

Interface

TWD

TWCK

Atmel TWI

Serial EEPROM

Slave 1

I²C RTC

Slave 2

Rp: Pull up value as given by the I²C Standard

19.6 I/O Lines Description

Table 19-3.

I/O Lines Description

Pin Name

TWD

TWCK

Pin Description

Two-wire Serial Data

Two-wire Serial Clock

I²C LCD

Controller

Slave 3

I²C Temp.

Sensor

Slave 4

Type

Input/Output

Input/Output

19.7 Product Dependencies

19.7.1

I/O Lines

Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see

Figure 19-2 on page 220 ). When the bus is free, both lines are

high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function.

TWD and TWCK pins may be multiplexed with GPIO lines. To enable the TWI, the programmer must perform the following steps:

• Program the GPIO controller to:

– Dedicate TWD and TWCK as peripheral lines.

– Define TWD and TWCK as open-drain.

19.7.2

Power Management

The TWI clock is generated by the Power Manager (PM). Before using the TWI, the programmer must ensure that the TWI clock is enabled in the PM.

In the TWI description, Master Clock (CLK_TWI) is the clock of the peripheral bus to which the

TWI is connected.

220

32059L–AVR32–01/2012

AT32UC3B

19.7.3

Interrupt

The TWI interface has an interrupt line connected to the Interrupt Controller (INTC). In order to handle interrupts, the INTC must be programmed before configuring the TWI.

19.8 Functional Description

19.8.1

Transfer Format

The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must

be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure

19-4

).

Each transfer begins with a START condition and terminates with a STOP condition (see

Figure

19-3

).

• A high-to-low transition on the TWD line while TWCK is high defines the START condition.

• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.

Figure 19-3. START and STOP Conditions

TWD

TWCK

Start Stop

Figure 19-4. Transfer Format

TWD

TWCK

Start Address R/W Ack Data

19.9 Modes of Operation

The TWI has six modes of operations:

• Master transmitter mode

• Master receiver mode

• Multi-master transmitter mode

• Multi-master receiver mode

• Slave transmitter mode

• Slave receiver mode

These modes are described in the following chapters.

Ack Data Ack Stop

221

32059L–AVR32–01/2012

AT32UC3B

19.10 Master Mode

19.10.1

Definition

The Master is the device which starts a transfer, generates a clock and stops it.

19.10.2

Application Block Diagram

Figure 19-5. Master Mode Typical Application Block Diagram

VDD

Rp Rp

Host with

TWI

Interface

TWD

TWCK

Atmel TWI

Serial EEPROM

Slave 1

I²C RTC

Slave 2

Rp: Pull up value as given by the I²C Standard

I²C LCD

Controller

Slave 3

I²C Temp.

Sensor

Slave 4

19.10.3

Programming Master Mode

The following registers have to be programmed before entering Master mode:

1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used to access slave devices in read or write mode.

2. CKDIV + CHDIV + CLDIV: Determines clock waveform T

high

and T

low

.

3. SVDIS: Disable the slave mode.

4. MSEN: Enable the master mode.

19.10.4

Master Mode Clock Timing

The TWI module monitors the state of the TWCK line as required by the I²C specification. The counter that determines the TWCK T

high

or T

low

duration is started whenever a high or low level is detected by the module on TWCK, not when the module begins releasing or driving the TWCK line. Thus, the CWGR.CHDIV and CLDIV fields do not alone determine the overall TWCK period; they merely determine the T

high

(T

rise

and T

fall

and T

low

components, whereas the rise and fall times

) are determined by the external circuitry on the TWCK pin as well as the propagation and synchronization delay of TWCK from the pin back into the TWI module. The TWI module does not attempt to compensate for these delays, so the overall TWI clock period is given by T

high

+T fall

+T low

+T rise

.

19.10.5

Master Transmitter Mode

After the master initiates a Start condition when writing into the Transmit Holding Register, THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in MMR), to notify the slave device. The bit following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in MMR).

222

32059L–AVR32–01/2012

AT32UC3B

The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NACK in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register

(IER). If the slave acknowledges the byte, the data written in the THR, is then shifted in the internal shifter and transferred. When an acknowledge is detected, the TXRDY bit is set until a new write in the THR. When no more data is written into the THR, the master generates a stop condition to end the transfer. The end of the complete transfer is marked by the TXCOMP bit set to one. See

Figure 19-6

,

Figure 19-7

, and

Figure 19-8 on page 223

.

TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.

Figure 19-6. Master Write with One Data Byte

TWD S DADR W A DATA A P

TXCOMP

TXRDY

Write THR (DATA)

Figure 19-7. Master Write with Multiple Data Byte

TWD S DADR W A DATA n A

TXCOMP

STOP sent automaticaly

(ACK received and TXRDY = 1)

DATA n+5 A DATA n+x A P

TXRDY

Write THR (Data n) Write THR (Data n+1) Write THR (Data n+x)

Last data sent

Figure 19-8. Master Write with One Byte Internal Address and Multiple Data Bytes

TWD S DADR W A IADR(7:0) A DATA n A DATA n+5 A

STOP sent automaticaly

(ACK received and TXRDY = 1)

DATA n+x A P

TXCOMP

TXRDY

Write THR (Data n) Write THR (Data n+1) Write THR (Data n+x)

Last data sent

STOP sent automaticaly

(ACK received and TXRDY = 1)

223

32059L–AVR32–01/2012

AT32UC3B

19.10.6

Master Receiver Mode

The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case (MREAD = 1 in MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.

If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the master sends an acknowledge condition to notify the slave that the data

has been received except for the last data, after the stop condition. See Figure 19-9 . When the

RXRDY bit is set in the status register, a character has been received in the receive-holding register (RHR). The RXRDY bit is reset when reading the RHR.

When a single data byte read is performed, with or without internal address (IADR), the START

and STOP bits must be set at the same time. See Figure 19-9

. When a multiple data byte read is performed, with or without IADR, the STOP bit must be set after the next-to-last data received.

See Figure 19-10 . For Internal Address usage see ”Internal Address” on page 224 .

Figure 19-9. Master Read with One Data Byte

TWD S DADR R A DATA N P

TXCOMP

RXRDY

Write START &

STOP Bit

Read RHR

Figure 19-10. Master Read with Multiple Data Bytes

TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m)

N

P

TXCOMP

Write START Bit

RXRDY

Read RHR

DATA n

Read RHR

DATA (n+1)

Read RHR

DATA (n+m)-1

Read RHR

DATA (n+m)

Write STOP Bit after next-to-last data read

RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel.

19.10.7

Internal Address

The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices.

224

32059L–AVR32–01/2012

AT32UC3B

19.10.7.1

7-bit Slave Addressing

When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example. When performing read operations with an internal address, the TWI performs a write operation to set the internal address into the slave device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See

Figure 19-12 . See

Figure 19-11

and

Figure 19-13 for Master Write operation with internal address.

The three internal address bytes are configurable through the Master Mode register (MMR).

If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to

0.

n the figures below the following abbreviations are used:I

• S

• Sr

• P

• W

• R

• A

• N

• DADR

• IADR

Start

Repeated Start

Stop

Write

Read

Acknowledge

Not Acknowledge

Device Address

Internal Address

Figure 19-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte

TWD

Three bytes internal address

S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A

TWD

Two bytes internal address

S DADR W

TWD

One byte internal address

S DADR W

A

A

IADR(15:8)

IADR(7:0)

A

A

IADR(7:0)

DATA

A

A P

DATA A

P

DATA A P

225

32059L–AVR32–01/2012

AT32UC3B

Figure 19-12. Master Read with One, Two or Three Bytes Internal Address and One Data Byte

TWD

Three bytes internal address

S DADR

W

A IADR(23:16) A

IADR(15:8)

A

IADR(7:0) A Sr DADR

DATA

TWD

Two bytes internal address

S DADR W

TWD

One byte internal address

S DADR W

A

A

IADR(15:8) A

IADR(7:0) A

IADR(7:0) A

Sr DADR R

Sr

A

DADR

DATA

R A

N P

DATA

R A

N P

N P

19.10.7.2

10-bit Slave Addressing

For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (IADR). The two remaining Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave

Addressing.

Example: Address a 10-bit device:

(10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)

1. Program IADRSZ = 1,

2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)

3. Program IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address)

Figure 19-13

below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal addresses to access the device.

Figure 19-13. Internal Address Usage

S

T

A

R

T

Device

Address

0

M

S

B

W

R

I

T

E

WORD ADDRESS

L

S

B

R

/

W

A

C

K

M

S

B

FIRST

A

C

K

SECOND

WORD ADDRESS

L

S

B

A

C

K

DATA

A

C

K

S

T

O

P

19.11 Using the Peripheral DMA Controller

The use of the Peripheral DMA Controller significantly reduces the CPU load.

226

32059L–AVR32–01/2012

AT32UC3B

To assure correct implementation, respect the following programming sequences:

19.11.1

Data Transmit with the Peripheral DMA Controller

1. Initialize the Peripheral DMA Controller TX channel (memory pointers, size, etc.).

2. Configure the master mode (DADR, CKDIV, etc.).

3. Start the transfer by setting the Peripheral DMA Controller TXEN bit.

4. Wait for the Peripheral DMA Controller end TX flag.

5. Disable the Peripheral DMA Controller by setting the Peripheral DMA Controller TXDIS bit.

19.11.2

Data Receive with the Peripheral DMA Controller

1. Initialize the Peripheral DMA Controller TX channel (memory pointers, size, etc.).

2. Configure the master mode (DADR, CKDIV, etc.).

3. Start the transfer by setting the Peripheral DMA Controller RXEN bit.

4. Wait for the Peripheral DMA Controller end RX flag.

5. Disable the Peripheral DMA Controller by setting the Peripheral DMA Controller RXDIS bit.

227

32059L–AVR32–01/2012

AT32UC3B

19.11.3

Read-write Flowcharts

The following flowcharts shown in Figure 19-14 to

Figure 19-19 on page 233 give examples for

read and write operations. A polling or interrupt method can be used to check the status bits.

The interrupt method requires that the interrupt enable register (IER) be configured first.

Figure 19-14. TWI Write Operation with Single Data Byte without Internal Address.

BEGIN

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Set the Control register:

- Master enable

TWI_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address (DADR)

- Transfer direction bit

Write ==> bit MREAD = 0

Load Transmit register

TWI_THR = Data to send

Read Status register

TXRDY = 1?

Yes

Read Status register

TXCOMP = 1?

Yes

Transfer finished

No

No

228

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

Figure 19-15. TWI Write Operation with Single Data Byte and Internal Address

BEGIN

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Set the Control register:

- Master enable

TWI_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address (DADR)

- Internal address size (IADRSZ)

- Transfer direction bit

Write ==> bit MREAD = 0

Set the internal address

TWI_IADR = address

Load transmit register

TWI_THR = Data to send

Read Status register

TXRDY = 1?

Yes

Read Status register

TXCOMP = 1?

Yes

Transfer finished

No

No

229

AT32UC3B

Figure 19-16. TWI Write Operation with Multiple Data Bytes with or without Internal Address

BEGIN

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Set the Control register:

- Master enable

TWI_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address

- Internal address size

(if IADR used)

- Transfer direction bit

Write ==> bit MREAD = 0

Internal address size = 0?

Yes

Load Transmit register

TWI_THR = Data to send

No

Set the internal address

TWI_IADR = address

Read Status register

TWI_THR = data to send

No

TXRDY = 1?

Yes

Data to send?

Yes

Read Status register

Yes

TXCOMP = 1?

No

END

230

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

Figure 19-17. TWI Read Operation with Single Data Byte without Internal Address

BEGIN

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Set the Control register:

- Master enable

TWI_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address

- Transfer direction bit

Read ==> bit MREAD = 1

Start the transfer

TWI_CR = START | STOP

Read status register

No

RXRDY = 1?

Yes

Read Receive Holding Register

Read Status register

TXCOMP = 1?

Yes

END

No

231

32059L–AVR32–01/2012

AT32UC3B

Figure 19-18. TWI Read Operation with Single Data Byte and Internal Address

BEGIN

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Set the Control register:

- Master enable

TWI_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address

- Internal address size (IADRSZ)

- Transfer direction bit

Read ==> bit MREAD = 1

Set the internal address

TWI_IADR = address

Start the transfer

TWI_CR = START | STOP

Read Status register

RXRDY = 1?

Yes

Read Receive Holding register

No

Read Status register

TXCOMP = 1?

Yes

END

No

232

32059L–AVR32–01/2012

AT32UC3B

Figure 19-19. TWI Read Operation with Multiple Data Bytes with or without Internal Address

BEGIN

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Set the Control register:

- Master enable

TWI_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address

- Internal address size (if IADR used)

- Transfer direction bit

Read ==> bit MREAD = 1

Internal address size = 0?

Yes

Start the transfer

TWI_CR = START

Read Status register

No

RXRDY = 1?

Yes

Read Receive Holding register (TWI_RHR)

No

Last data to read but one?

Yes

Stop the transfer

TWI_CR = STOP

Read Status register

RXRDY = 1?

Yes

Read Receive Holding register (TWI_RHR)

No

Set the internal address

TWI_IADR = address

Read status register

No

TXCOMP = 1?

Yes

END

233

AT32UC3B

19.12 Multi-master Mode

19.12.1

Definition

More than one master may handle the bus at the same time without data corruption by using arbitration.

Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero.

As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. When the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration.

Arbitration is illustrated in Figure 19-21 on page 235 .

19.12.2

Different Multi-master Modes

Two multi-master modes may be distinguished:

1. TWI is considered as a Master only and will never be addressed.

2. TWI may be either a Master or a Slave and may be addressed.

Note: Arbitration is supported in both Multi-master modes.

19.12.2.1

TWI as Master Only

In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven like a Master with the ARBLST (ARBitration Lost) flag in addition.

If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer.

If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the

TWI automatically waits for a STOP condition on the bus to initiate the transfer (see

Figure 19-

20 on page 235 ).

Note: The state of the bus (busy or free) is not indicated in the user interface.

19.12.2.2

TWI as Master or Slave

The automatic reversal from Master to Slave is not supported in case of a lost arbitration.

Then, in the case where TWI may be either a Master or a Slave, the programmer must manage the pseudo Multi-master mode described in the steps below.

1. Program TWI in Slave mode (SADR + MSDIS + SVEN) and perform Slave Access (if

TWI is addressed).

2. If TWI has to be set in Master mode, wait until TXCOMP flag is at 1.

3. Program Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START +

Write in THR).

4. As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is busy or free. When the bus is considered as free, TWI initiates the transfer.

5. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and the user must monitor the ARBLST flag.

6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave mode in the case where the Master that won the arbitration wanted to access the TWI.

234

32059L–AVR32–01/2012

AT32UC3B

7. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode.

Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat

SADR.

Figure 19-20. Programmer Sends Data While the Bus is Busy

TWCK

TWD

STOP sent by the master

DATA sent by a master

Bus is busy

START sent by the TWI

DATA sent by the TWI

Bus is free

TWI DATA transfer

Transfer is kept

A transfer is programmed

(DADR + W + START + Write THR)

Figure 19-21. Arbitration Cases

TWCK

TWD

Bus is considered as free

Transfer is initiated

TWCK

Data from a Master

Data from TWI

TWD

S

1

0 0

1 1

S

1

0

1

Arbitration is lost

TWI stops sending data

S

1

0

0

1 1 Data from the master

P

P

S

1 0

1

Arbitration is lost

The master stops sending data

S

1

0 0

1

1

S

1 0

0 1

1

Data from the TWI

ARBLST

Bus is busy Bus is free

TWI DATA transfer

Transfer is kept

A transfer is programmed

(DADR + W + START + Write THR)

Transfer is stopped

Transfer is programmed again

(DADR + W + START + Write THR)

Bus is considered as free

Transfer is initiated

The flowchart shown in Figure 19-22 on page 236

gives an example of read and write operations in Multi-master mode.

235

32059L–AVR32–01/2012

AT32UC3B

Figure 19-22. Multi-master Flowchart

START

Programm the SLAVE mode:

SADR + MSDIS + SVEN

Read Status Register

SVACC = 1 ?

Yes

GACC = 1 ?

EOSACC = 1 ?

Yes

TXCOMP = 1 ?

Yes

Need to perform a master access ?

Yes

SVREAD = 0 ?

Program the Master mode

DADR + SVDIS + MSEN + CLK + R / W

Read Status Register

Yes

ARBLST = 1 ?

Read TWI_RHR

Yes

Yes

RXRDY= 0 ?

Yes

Data to read?

MREAD = 1 ?

Yes

RXRDY= 0 ?

Yes

Read TWI_RHR

GENERAL CALL TREATMENT

Decoding of the programming sequence

Prog seq

OK ?

Change SADR

TXRDY= 0 ?

Data to send ?

Yes

Yes

TXRDY= 1 ?

Yes

Write in TWI_THR

Write in TWI_THR

Stop transfer

Read Status Register

Yes

TXCOMP = 0 ?

236

32059L–AVR32–01/2012

AT32UC3B

19.13 Slave Mode

19.13.1

Definition

The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master.

In this mode, the device never initiates and never completes the transmission (START,

REPEATED_START and STOP conditions are always provided by the master).

19.13.2

Application Block Diagram

Figure 19-23. Slave Mode Typical Application Block Diagram

VDD

R R

Master

Host with

TWI

Interface

TWD

TWCK

Host with TWI

Interface

Slave 1

Host with TWI

Interface

Slave 2

LCD Controller

Slave 3

19.13.3

Programming Slave Mode

The following fields must be programmed before entering Slave mode:

1. SADR (SMR): The slave device address is used in order to be accessed by master devices in read or write mode.

2. MSDIS (CR): Disable the master mode.

3. SVEN (CR): Enable the slave mode.

As the device receives the clock, values written in CWGR are not taken into account.

19.13.4

Receiving Data

After a Start or Repeated Start condition is detected and if the address sent by the Master matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave

ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer.

SVACC remains high until a STOP condition or a repeated START is detected. When such a condition is detected, EOSACC (End Of Slave ACCess) flag is set.

19.13.4.1

Read Sequence

In the case of a Read sequence (SVREAD is high), TWI transfers data written in the THR (TWI

Transmit Holding Register) until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmission

Complete) flag is set and SVACC reset.

As soon as data is written in the THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set.

237

32059L–AVR32–01/2012

AT32UC3B

19.13.4.2

Note that a STOP or a repeated START always follows a NACK.

See Figure 19-24 on page 239 .

Write Sequence

In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register

Ready) flag is set as soon as a character has been received in the RHR (TWI Receive Holding

Register). RXRDY is reset when reading the RHR.

TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset.

See Figure 19-25 on page 239 .

19.13.4.3

Clock Synchronization Sequence

In the case where THR or RHR is not written/read in time, TWI performs a clock synchronization.

Clock stretching information is given by the SCLWS (Clock Wait state) bit.

See Figure 19-27 on page 241

and Figure 19-28 on page 242 .

19.13.4.4

General Call

In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set.

After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the new address programming sequence.

See Figure 19-26 on page 240 .

19.13.4.5

Peripheral DMA Controller

As it is impossible to know the exact number of data to receive/send, the use of Peripheral DMA

Controller is NOT recommended in SLAVE mode.

19.13.5

Data Transfer

19.13.5.1

Read Operation

The read mode is defined as a data requirement from the master.

After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer.

Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the THR register.

If a STOP condition or a REPEATED START + an address different from SADR is detected,

SVACC is reset.

Figure 19-24 on page 239

describes the write operation.

238

32059L–AVR32–01/2012

AT32UC3B

Figure 19-24. Read Access Ordered by a MASTER

SADR does not match,

TWI answers with a NACK

SADR matches,

TWI answers with an ACK

ACK/NACK from the Master

A DATA NA S/Sr TWD

TXRDY

NACK

SVACC

SVREAD

EOSVACC

S ADR R NA DATA NA P/S/Sr SADR R A DATA A

Write THR

Read RHR

SVREAD has to be taken into account only while SVACC is active

Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant.

2. TXRDY is reset when data has been transmitted from THR to the shift register and set when this data has been acknowledged or non acknowledged.

19.13.5.2

Write Operation

The write mode is defined as a data transmission from the master.

After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case).

Until a STOP or REPEATED START condition is detected, TWI stores the received data in the

RHR register.

If a STOP condition or a REPEATED START + an address different from SADR is detected,

SVACC is reset.

Figure 19-25 on page 239

describes the Write operation.

Figure 19-25. Write Access Ordered by a Master

SADR does not match,

TWI answers with a NACK

SADR matches,

TWI answers with an ACK

Read RHR

TWD

RXRDY

SVACC

SVREAD

EOSVACC

S ADR W NA DATA NA P/S/Sr SADR W A DATA A A DATA NA S/Sr

SVREAD has to be taken into account only while SVACC is active

Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant.

2. RXRDY is set when data has been transmitted from the shift register to the RHR and reset when this data is read.

239

32059L–AVR32–01/2012

AT32UC3B

19.13.5.3

General Call

The general call is performed in order to change the address of the slave.

If a GENERAL CALL is detected, GACC is set.

After the detection of General Call, it is up to the programmer to decode the commands which come afterwards.

In case of a WRITE command, the programmer has to decode the programming sequence and program a new SADR if the programming sequence matches.

Figure 19-26 on page 240

describes the General Call access.

Figure 19-26. Master Performs a General Call

0000000 + W

RESET command = 00000110X

WRITE command = 00000100X

TXD

S

A

Reset or write DADD

A

DATA1

A DATA2

New SADR

Programming sequence

A New SADR A P

GCACC

SVACC

Reset after read

Note: 1. This method allows the user to create an own programming sequence by choosing the programming bytes and the number of them. The programming sequence has to be provided to the master.

240

32059L–AVR32–01/2012

AT32UC3B

19.13.6

Clock Synchronization

In both read and write modes, it may happen that THR/RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented.

19.13.6.1

Clock Synchronization in Read Mode

The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded.

Figure 19-27 on page 241

describes the clock synchronization in Read mode.

Figure 19-27. Clock Synchronization in Read Mode

TWI_THR 1 DATA1 DATA2

SADR

R A DATA0 A

DATA1

A

XXXXXXX

2

DATA2 NA S

TWCK

CLOCK is tied low by the TWI as long as THR is empty

Write THR

SCLWS

TXRDY

SVACC

SVREAD

TXCOMP

1

2

As soon as a START is detected

TWI_THR is transmitted to the shift register

Ack or Nack from the master

The data is memorized in TWI_THR until a new value is written

The clock is stretched after the ACK, the state of TWD is undefined during clock stretching

Notes: 1. TXRDY is reset when data has been written in the TH to the shift register and set when this data has been acknowledged or non acknowledged.

2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from

SADR.

3. SCLWS is automatically set when the clock synchronization mechanism is started.

241

32059L–AVR32–01/2012

AT32UC3B

19.13.6.2

Clock Synchronization in Write Mode

The clock is tied low if the shift register and the RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until RHR is read.

Figure 19-28 on page 242

describes the clock synchronization in Read mode.

Figure 19-28. Clock Synchronization in Write Mode

TWCK

CLOCK is tied low by the TWI as long as RHR is full

TWD

S SADR W A DATA0 A DATA1 A DATA2

NA

S ADR

TWI_RHR

DATA0 is not read in the RHR

DATA1 DATA2

SCLWS

RXRDY

SCL is stretched on the last bit of DATA1

Rd DATA0

Rd DATA1

Rd DATA2

SVACC

SVREAD

TXCOMP

As soon as a START is detected

Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from

SADR.

2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mechanism is finished.

242

32059L–AVR32–01/2012

AT32UC3B

19.13.7

Reversal after a Repeated Start

19.13.7.1

Reversal of Read to Write

The master initiates the communication by a read command and finishes it by a write command.

Figure 19-29 on page 243

describes the repeated start + reversal from Read to Write mode.

Figure 19-29. Repeated Start + Reversal from Read to Write Mode

TWI_THR

DATA0 DATA1

TWD

S SADR R A DATA0 A DATA1

NA

Sr SADR W A DATA2 A DATA3 A P

TWI_RHR

SVACC

SVREAD

TXRDY

RXRDY

EOSACC

TXCOMP

As soon as a START is detected

Cleared after read

DATA2 DATA3

Note: 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.

19.13.7.2

Reversal of Write to Read

The master initiates the communication by a write command and finishes it by a read command.

Figure 19-30 on page 243

describes the repeated start + reversal from Write to Read mode.

Figure 19-30. Repeated Start + Reversal from Write to Read Mode

TWI_THR

TWD

TWI_RHR

SVACC

SVREAD

TXRDY

RXRDY

EOSACC

TXCOMP

DATA0

DATA2 DATA3

S SADR W A DATA0 A DATA1 A

Sr SADR R A DATA2 A DATA3 NA P

DATA1

Read TWI_RHR

As soon as a START is detected

Cleared after read

Notes: 1. In this case, if THR has not been written at the end of the read command, the clock is automatically stretched before the

ACK.

243

32059L–AVR32–01/2012

AT32UC3B

2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.

19.13.8

Read Write Flowcharts

The flowchart shown in Figure 19-31 on page 244

gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (IER) be configured first.

Figure 19-31. Read Write Flowchart in Slave Mode

Set the SLAVE mode:

SADR + MSDIS + SVEN

Read Status Register

SVACC = 1 ?

EOSACC = 1 ?

TXCOMP = 1 ?

END

GACC = 1 ?

SVREAD = 0 ?

TXRDY= 1 ?

Write in TWI_THR

RXRDY= 0 ?

Read TWI_RHR

Decoding of the programming sequence

Prog seq

OK ?

Change SADR

GENERAL CALL TREATMENT

244

32059L–AVR32–01/2012

19.14 User Interface

Table 19-4.

TWI User Interface

Offset

0x00

0x04

0x08

0x0C

0x10

0x20

0x24

0x28

0x2C

0x30

0x34

Register

Control Register

Master Mode Register

Slave Mode Register

Internal Address Register

Clock Waveform Generator Register

Status Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Receive Holding Register

Transmit Holding Register

AT32UC3B

Register Name

CR

MMR

SMR

IADR

CWGR

SR

IER

IDR

IMR

RHR

THR

Access

Write-only

Read/Write

Read/Write

Read/Write

Read/Write

Read-only

Write-only

Write-only

Read-only

Read-only

Write-only

Reset

N / A

0x00000000

0x00000000

0x00000000

0x00000000

0x0000F009

N / A

N / A

0x00000000

0x00000000

0x00000000

245

32059L–AVR32–01/2012

AT32UC3B

19.14.1

Control Register

Name:

CR

Access:

Offset:

Write-only

0x00

Reset Value: 0x00000000

31

30

23

15

7

SWRST

22

14

6

29

21

13

5

SVDIS

28

20

12

4

SVEN

27

19

11

3

MSDIS

26

18

10

2

MSEN

25

17

9

1

STOP

24

16

8

0

START

• SWRST: Software Reset

0 = No effect.

1 = Equivalent to a system reset.

• SVDIS: TWI Slave Mode Disabled

0 = No effect.

1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation.

In write operation, the character being transferred must be completely received before disabling.

• SVEN: TWI Slave Mode Enabled

0 = No effect.

1 = If SVDIS = 0, the slave mode is enabled.

Switching from Master to Slave mode is only permitted when TXCOMP = 1.

• MSDIS: TWI Master Mode Disabled

0 = No effect.

1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling.

• MSEN: TWI Master Mode Enabled

0 = No effect.

1 = If MSDIS = 0, the master mode is enabled.

Switching from Slave to Master mode is only permitted when TXCOMP = 1.

• STOP: Send a STOP Condition

0 = No effect.

1 = STOP Condition is sent just after completing the current byte transmission in master read mode.

- In single data byte master read, the START and STOP must both be set.

- In multiple data bytes master read, the STOP must be set after the last data received but one.

- In master read mode, if a NACK bit is received, the STOP is automatically performed.

- In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent.

• START: Send a START Condition

0 = No effect.

1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.

246

32059L–AVR32–01/2012

AT32UC3B

This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (THR).

32059L–AVR32–01/2012

247

AT32UC3B

19.14.2

Master Mode Register

Name: MMR

Access:

Offset:

Read-write

0x04

Reset Value: 0x00000000

31

30

29

23

15

7

22

14

6

21

13

5

28

20

12

MREAD

4

27

19

DADR

11

3

26

18

10

2

25

17

9

1

IADRSZ

• DADR: Device Address

The device address is used to access slave devices in read or write mode. Those bits are only used in Master mode.

• MREAD: Master Read Direction

0 = Master write direction.

1 = Master read direction.

• IADRSZ: Internal Device Address Size

24

16

8

0

1

1

0

0

IADRSZ[9:8]

0

1

0

1

Description

No internal device address

One-byte internal device address

Two-byte internal device address

Three-byte internal device address

248

32059L–AVR32–01/2012

AT32UC3B

19.14.3

Slave Mode Register

Name:

SMR

Access:

Offset:

Read-write

0x08

Reset Value: 0x00000000

31

30

23

15

22

14

29

21

13

28

20

12

27

19

SADR

11

26

18

10

25

17

9 8

7

6

5

4

3

2

1

0

• SADR: Slave Address

The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode.

SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect.

24

16

249

32059L–AVR32–01/2012

AT32UC3B

19.14.4

Internal Address Register

Name:

IADR

Access:

Offset:

Read-write

0x0C

Reset Value: 0x00000000

31

30

29

23 22 21

15 14 13

7 6 5

• IADR: Internal Address

0, 1, 2 or 3 bytes depending on IADRSZ.

28

20

IADR

12

IADR

4

IADR

27

19

11

3

26

18

10

2

25

17

9

1

24

16

8

0

250

32059L–AVR32–01/2012

AT32UC3B

19.14.5

Clock Waveform Generator Register

Name:

CWGR

Access:

Offset:

Read-write

0x10

Reset Value: 0x00000000

31

30

29

28

23 22 21 20

15 14 13 12 11

CHDIV

7 6 5 4

CLDIV

CWGR is only used in Master mode.

• CKDIV: Clock Divider

The CKDIV is used to increase both SCL high and low periods.

• CHDIV: Clock High Divider

The SCL high period is defined as follows:

T high

=

( (

CHDIV

×

2

CKDIV

×

T

CLK_TWI

• CLDIV: Clock Low Divider

The SCL low period is defined as follows:

T low

=

( (

CLDIV

×

2

CKDIV

×

T

CLK_TWI

3

27

19

26

18

10

2

25

17

CKDIV

9

1

24

16

8

0

251

32059L–AVR32–01/2012

AT32UC3B

19.14.6

Status Register

Name:

SR

Access:

Offset:

Read-only

0x20

Reset Value: 0x0000F009

31

30

23

15

7

22

14

6

OVRE

29

21

13

5

GACC

28

20

12

4

SVACC

27

19

11

EOSACC

3

SVREAD

26

18

10

SCLWS

2

TXRDY

25

17

9

ARBLST

1

RXRDY

24

16

8

NACK

0

TXCOMP

• EOSACC: End Of Slave Access (clear on read)

This bit is only used in Slave mode.

0 = A slave access is being performing.

1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset.

EOSACC behavior can be seen in

Figure 19-29 on page 243 and Figure 19-30 on page 243

• SCLWS: Clock Wait State (automatically set / reset)

This bit is only used in Slave mode.

0 = The clock is not stretched.

1 = The clock is stretched. THR / RHR buffer is not filled / emptied before the emission / reception of a new character.

SCLWS behavior can be seen in

Figure 19-27 on page 241 and

Figure 19-28 on page 242 .

• ARBLST: Arbitration Lost (clear on read)

This bit is only used in Master mode.

0 = Arbitration won.

1 = Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time.

• NACK: Not Acknowledged (clear on read)

NACK used in Master mode:

0 = Each data byte has been correctly received by the far-end side TWI slave component.

1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP.

NACK used in Slave Read mode:

0 = Each data byte has been correctly received by the Master.

1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it.

Note that in Slave Write mode all data are acknowledged by the TWI.

• OVRE: Overrun Error (clear on read)

This bit is only used in Slave mode.

0 = RHR has not been loaded while RXRDY was set

1 = RHR has been loaded while RXRDY was set. Reset by read in SR when TXCOMP is set.

• GACC: General Call Access (clear on read)

This bit is only used in Slave mode.

0 = No General Call has been detected.

252

32059L–AVR32–01/2012

AT32UC3B

1 = A General Call has been detected. After the detection of General Call, the programmer decoded the commands that follow and the programming sequence.

GACC behavior can be seen in

Figure 19-26 on page 240 .

• SVACC: Slave Access (automatically set / reset)

This bit is only used in Slave mode.

0 = TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected.

1 = Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected.

SVACC behavior can be seen in Figure 19-24 on page 239

,

Figure 19-25 on page 239 ,

Figure 19-29 on page 243 and Figure

19-30 on page 243

.

• SVREAD: Slave Read (automatically set / reset)

This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant.

0 = Indicates that a write access is performed by a Master.

1 = Indicates that a read access is performed by a Master.

SVREAD behavior can be seen in Figure 19-24 on page 239

,

Figure 19-25 on page 239

,

Figure 19-29 on page 243 and Figure

19-30 on page 243

.

• TXRDY: Transmit Holding Register Ready (automatically set / reset)

TXRDY used in Master mode:

0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into THR register.

1 = As soon as a data byte is transferred from THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).

TXRDY behavior in Master mode

can be seen in

Figure 19-8 on page 223 .

TXRDY used in Slave mode:

0 = As soon as data is written in the THR, until this data has been transmitted and acknowledged (ACK or NACK).

1 = It indicates that the THR is empty and that data has been transmitted and acknowledged.

If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill THR to avoid losing it.

TXRDY behavior in Slave mode can be seen in Figure 19-24 on page 239 ,

Figure 19-27 on page 241

,

Figure 19-29 on page

243 and Figure 19-30 on page 243 .

• RXRDY: Receive Holding Register Ready (automatically set / reset)

0 = No character has been received since the last RHR read operation.

1 = A byte has been received in the RHR since the last read.

RXRDY behavior in Master mode can be seen in Figure 19-10 on page 224 .

RXRDY behavior in Slave mode can be seen in Figure 19-25 on page 239

,

Figure 19-28 on page 242 ,

Figure 19-29 on page

243 and Figure 19-30 on page 243 .

• TXCOMP: Transmission Completed (automatically set / reset)

TXCOMP used in Master mode:

0 = During the length of the current frame.

1 = When both holding and shifter registers are empty and STOP condition has been sent.

TXCOMP behavior in Master mode can be seen in

Figure 19-8 on page 223 and in

Figure 19-10 on page 224 .

TXCOMP used in Slave mode:

0 = As soon as a Start is detected.

1 = After a Stop or a Repeated Start + an address different from SADR is detected.

TXCOMP behavior in Slave mode can be seen in Figure 19-27 on page 241 ,

Figure 19-28 on page 242

,

Figure 19-29 on page

243 and Figure 19-30 on page 243 .

253

32059L–AVR32–01/2012

AT32UC3B

19.14.7

Interrupt Enable Register

Name:

IER

Access:

Offset:

Write-only

0x24

Reset Value: 0x00000000

31

30

29

23

15

22

14

21

13

28

20

12

27

19

11

EOSACC

7

6

OVRE

5

GACC

4

SVACC

3

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will set the corresponding bit in IMR.

26

18

10

SCL_WS

2

TXRDY

25

17

9

ARBLST

1

RXRDY

24

16

8

NACK

0

TXCOMP

254

32059L–AVR32–01/2012

AT32UC3B

19.14.8

Interrupt Disable Register

Name:

IDR

Access:

Offset:

Write-only

0x28

Reset Value: 0x00000000

31

30

29

23

15

22

14

21

13

28

20

12

27

19

11

EOSACC

7

6

OVRE

5

GACC

4

SVACC

3

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will clear the corresponding bit in IMR.

26

18

10

SCL_WS

2

TXRDY

25

17

9

ARBLST

1

RXRDY

24

16

8

NACK

0

TXCOMP

255

32059L–AVR32–01/2012

AT32UC3B

19.14.9

Interrupt Mask Register

Name:

IMR

Access:

Offset:

Read-only

0x2C

Reset Value: 0x00000000

31

30

29

23

15

7

22

14

6

OVRE

21

13

5

GACC

28

20

12

4

SVACC

27

19

11

EOSACC

3

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

A bit in this register is cleared when the corresponding bit in IDR is written to one.

A bit in this register is set when the corresponding bit in IER is written to one.

26

18

10

SCL_WS

2

TXRDY

25

17

9

ARBLST

1

RXRDY

24

16

8

NACK

0

TXCOMP

256

32059L–AVR32–01/2012

AT32UC3B

19.14.10 Receive Holding Register

Name:

RHR

Access:

Offset:

Read-only

0x30

Reset Value: 0x00000000

31

30

29

23

15

7

22

14

6

21

13

5

• RXDATA: Master or Slave Receive Holding Data

28

20

12

11

4

RXDATA

3

27

19

10

2

26

18

9

1

25

17

8

0

24

16

257

32059L–AVR32–01/2012

AT32UC3B

19.14.11 Transmit Holding Register

Name:

THR

Access:

Offset:

Read-write

0x34

Reset Value: 0x00000000

31

30

29

23

15

7

22

14

6

21

13

5

28

20

12

11

4

TXDATA

3

27

19

• TXDATA: Master or Slave Transmit Holding Data

10

2

26

18

9

1

25

17

8

0

24

16

258

32059L–AVR32–01/2012

AT32UC3B

20. Synchronous Serial Controller (SSC)

Rev: 3.1.0.2

20.1 Features

Provides serial synchronous communication links used in audio and telecom applications

Independent receiver and transmitter, common clock divider

Interfaced with two Peripheral DMA Controller channels to reduce processor overhead

Configurable frame sync and data length

Receiver and transmitter can be configured to start automatically or on detection of different events on the frame sync signal

Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal

20.2 Overview

The Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc.

The SSC consists of a receiver, a transmitter, and a common clock divider. Both the receiver and the transmitter interface with three signals:

• the TX_DATA/RX_DATA signal for data

• the TX_CLOCK/RX_CLOCK signal for the clock

• the TX_FRAME_SYNC/RX_FRAME_SYNC signal for the frame synchronization

The transfers can be programmed to start automatically or on different events detected on the

Frame Sync signal.

The SSC’s high-level of programmability and its two dedicated Peripheral DMA Controller channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention.

Featuring connection to two Peripheral DMA Controller channels, the SSC permits interfacing with low processor overhead to the following:

• CODEC’s in master or slave mode

• DAC through dedicated serial interface, particularly I2S

• Magnetic card reader

259

32059L–AVR32–01/2012

AT32UC3B

20.3 Block Diagram

Figure 20-1. SSC Block Diagram

High

Speed

Bus

Peripheral Bus

Bridge

Peripheral DMA

Controller

Peripheral

Bus

TX_FRAME_SYNC

TX_CLOCK

TX_DATA

Power

Manager

CLK_SSC

SSC Interface

I/O

Controller

Interrupt Control

RX_FRAME_SYNC

RX_CLOCK

RX_DATA

SSC Interrupt

20.4 Application Block Diagram

Figure 20-2. SSC Application Block Diagram

OS or RTOS Driver

Serial AUDIO Codec

Power

Management

Interrupt

Management

Test

Management

SSC

Time Slot

Management

Frame

Management

Line Interface

260

32059L–AVR32–01/2012

AT32UC3B

20.5 I/O Lines Description

Table 20-1.

I/O Lines Description

Pin Name

RX_FRAME_SYNC

RX_CLOCK

RX_DATA

TX_FRAME_SYNC

TX_CLOCK

TX_DATA

Pin Description

Receiver Frame Synchro

Receiver Clock

Receiver Data

Transmitter Frame Synchro

Transmitter Clock

Transmitter Data

Type

Input/Output

Input/Output

Input

Input/Output

Input/Output

Output

20.6 Product Dependencies

In order to use this module, other parts of the system must be configured correctly, as described below.

20.6.1

I/O Lines

The pins used for interfacing the compliant external devices may be multiplexed with I/O lines.

Before using the SSC receiver, the I/O Controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode.

Before using the SSC transmitter, the I/O Controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode.

20.6.2

Clocks

The clock for the SSC bus interface (CLK_SSC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the

SSC before disabling the clock, to avoid freezing the SSC in an undefined state.

20.6.3

Interrupts

The SSC interrupt request line is connected to the interrupt controller. Using the SSC interrupt requires the interrupt controller to be programmed first.

20.7 Functional Description

This chapter contains the functional description of the following: SSC functional block, clock management, data framing format, start, transmitter, receiver, and frame sync.

The receiver and the transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TX_CLOCK or

RX_CLOCK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TX_CLOCK and RX_CLOCK pins is CLK_SSC divided by two.

261

32059L–AVR32–01/2012

AT32UC3B

Figure 20-3. SSC Functional Block Diagram

CLK_SSC

Clock

Divider

Peripheral

Bus

Transmitter

Clock Output

Controller

TX_CLOCK Input

Transmit Clock

Controller

TX clock

Frame Sync

Controller

RX clock

TX_FRAME_SYNC

RX_FRAME_SYNC

Start

Selector

Transmit Shift Register

TX_DMA

Transmit Holding

Register

Load Shift

Transmit Sync

Holding Register

User

Interface

DMA

Receiver

Clock Output

Controller

RX_CLOCK

Input

TX clock

Receive Clock

Controller

RX clock

Frame Sync

Controller

Interrupt Control

TX_FRAME_SYNC

RX_FRAME_SYNC

Start

Selector

Receive Shift Register

RX_DMA

Receive Holding

Register

Load Shift

Receive Sync

Holding Register

TX_CLOCK

TX_FRAME_SYNC

TX_DATA

RX_CLOCK

RX_FRAME_SYNC

RX_DATA

Interrupt Controller

20.7.1

Clock Management

The transmitter clock can be generated by:

• an external clock received on the TX_CLOCK pin

• the receiver clock

• the internal clock divider

The receiver clock can be generated by:

• an external clock received on the RX_CLOCK pin

• the transmitter clock

• the internal clock divider

Furthermore, the transmitter block can generate an external clock on the TX_CLOCK pin, and the receiver block can generate an external clock on the RX_CLOCK pin.

This allows the SSC to support many Master and Slave Mode data transfers.

262

32059L–AVR32–01/2012

AT32UC3B

20.7.1.1

Clock divider

Figure 20-4. Divided Clock Block Diagram

Clock Divider

CMR

CLK_SSC

/ 2

12-bit Counter

Divided Clock

The peripheral clock divider is determined by the 12-bit Clock Divider field (its maximal value is

4095) in the Clock Mode Register (CMR.DIV), allowing a peripheral clock division by up to 8190.

The divided clock is provided to both the receiver and transmitter. When this field is written to zero, the clock divider is not used and remains inactive.

When CMR.DIV is written to a value equal to or greater than one, the divided clock has a frequency of CLK_SSC divided by two times CMR.DIV. Each level of the divided clock has a duration of the peripheral clock multiplied by CMR.DIV. This ensures a 50% duty cycle for the divided clock regardless of whether the CMR.DIV value is even or odd.

Figure 20-5. Divided Clock Generation

CLK_SSC

Divided Clock

DIV = 1

Divided Clock Frequency = CLK_SSC/2

CLK_SSC

Divided Clock

DIV = 3

Divided Clock Frequency = CLK_SSC/6

Table 20-2.

Range of Clock Divider

Maximum

CLK_SSC / 2

Minimum

CLK_SSC / 8190

20.7.1.2

Transmitter clock management

The transmitter clock is generated from the receiver clock, the divider clock, or an external clock scanned on the TX_CLOCK pin. The transmitter clock is selected by writing to the Transmit

Clock Selection field in the Transmit Clock Mode Register (TCMR.CKS). The transmit clock can

263

32059L–AVR32–01/2012

AT32UC3B

be inverted independently by writing a one to the Transmit Clock Inversion bit in TCMR

(TCMR.CKI).

The transmitter can also drive the TX_CLOCK pin continuously or be limited to the actual data transfer, depending on the Transmit Clock Output Mode Selection field in the TCMR register

(TCMR.CKO). The TCMR.CKI bit has no effect on the clock outputs.

Writing 0b10 to the TCMR.CKS field to select TX_CLOCK pin and 0b001 to the TCMR.CKO field to select Continuous Transmit Clock can lead to unpredictable results.

Figure 20-6. Transmitter Clock Management

TX_CLOCK

MUX

Clock

Output

Receiver

Clock

Tri-state

Controller

Divider

Clock

CKO

Data Transfer

CKS

INV

MUX

Tri-state

Controller

Transmitter

Clock

20.7.1.3

CKI

CKG

Receiver clock management

The receiver clock is generated from the transmitter clock, the divider clock, or an external clock scanned on the RX_CLOCK pin. The receive clock is selected by writing to the Receive Clock

Selection field in the Receive Clock Mode Register (RCMR.CKS). The receive clock can be inverted independently by writing a one to the Receive Clock Inversion bit in RCMR

(RCMR.CKI).

The receiver can also drive the RX_CLOCK pin continuously or be limited to the actual data transfer, depending on the Receive Clock Output Mode Selection field in the RCMR register

(RCMR.CKO). The RCMR.CKI bit has no effect on the clock outputs.

Writing 0b10 to the RCMR.CKS field to select RX_CLOCK pin and 0b001 to the RCMR.CKO

field to select Continuous Receive Clock can lead to unpredictable results.

264

32059L–AVR32–01/2012

AT32UC3B

Figure 20-7. Receiver Clock Management

RX_CLOCK

MUX

Tri-state

Controller

Transmitter

Clock

Divider

Clock

CKO

Data Transfer

CKS

INV

MUX

Clock

Output

Tri-state

Controller

Receiver

Clock

CKI

CKG

20.7.1.4

20.7.2

Serial clock ratio considerations

The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TX_CLOCK or RX_CLOCK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RX_CLOCK pin is:

– CLK_SSC divided by two if RX_FRAME_SYNC is input.

– CLK_SSC divided by three if RX_FRAME_SYNC is output.

In addition, the maximum clock speed allowed on the TX_CLOCK pin is:

– CLK_SSC divided by six if TX_FRAME_SYNC is input.

– CLK_SSC divided by two if TX_FRAME_SYNC is output.

Transmitter Operations

A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission.

The start event is configured by writing to the TCMR register. See

Section 20.7.4

.

The frame synchronization is configured by writing to the Transmit Frame Mode Register

(TFMR). See Section 20.7.5

.

To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the TCMR register. Data is written by the user to the Transmit Holding

Register (THR) then transferred to the shift register according to the data format selected.

When both the THR and the transmit shift registers are empty, the Transmit Empty bit is set in the Status Register (SR.TXEMPTY). When the THR register is transferred in the transmit shift register, the Transmit Ready bit is set in the SR register (SR.TXREADY) and additional data can be loaded in the THR register.

265

32059L–AVR32–01/2012

AT32UC3B

Figure 20-8. Transmitter Block Diagram

TFMR.DATDEF

TX_FRAME_SYNC

RX_FRAME_SYNC

Transmitter Clock

Start

Selector

TFMR.FSDEN

TCMR.STTDLY

TFMR.MSBF

Transmit Shift Register

0 1

1

0

TFMR.DATLEN

THR TSHR

CR.TXEN

SR.TXEN

CR.TXDIS

TCMR.STTDLY

TFMR.FSDEN

TFMR.DATNB

TFMR.FSLEN

TX_DATA

20.7.3

Receiver Operations

A received frame is triggered by a start event and can be followed by synchronization data before data transmission.

The start event is configured by writing to the RCMR register. See Section 20.7.4

.

The frame synchronization is configured by writing to the Receive Frame Mode Register

(RFMR). See Section 20.7.5

.

The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the RCMR register. The data is transferred from the shift register depending on the data format selected.

When the receiver shift register is full, the SSC transfers this data in the Receive Holding Register (RHR), the Receive Ready bit is set in the SR register (SR.RXREADY) and the data can be read in the RHR register. If another transfer occurs before a read of the RHR register

, the

Receive Overrun bit is set in the SR register (SR.OVRUN) and the receiver shift register is transferred to the RHR register.

266

32059L–AVR32–01/2012

AT32UC3B

Figure 20-9. Receiver Block Diagram

R X _C LO C K

M U X

T ransm itter

C lock

D ivider

C lock

C K S

T ri-state

C ontroller

C K O

IN V

M U X

D ata T ransfer

C lock

O utput

T ri-state

C ontroller

R eceiver

C lock

20.7.4

Start

C K I

C K G

The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection field of the TCMR register (TCMR.START) and in the Receive Start Selection field of the RCMR register (RCMR.START).

Under the following conditions the start event is independently programmable:

• Continuous: in this case, the transmission starts as soon as a word is written to the THR register and the reception starts as soon as the receiver is enabled

• Synchronously with the transmitter/receiver

• On detection of a falling/rising edge on TX_FRAME_SYNC/RX_FRAME_SYNC

• On detection of a low/high level on TX_FRAME_SYNC/RX_FRAME_SYNC

• On detection of a level change or an edge on TX_FRAME_SYNC/RX_FRAME_SYNC

A start can be programmed in the same manner on either side of the Transmit/Receive Clock

Mode Register (TCMR/RCMR). Thus, the start could be on TX_FRAME_SYNC (transmit) or

RX_FRAME_SYNC (receive).

Moreover, the receiver can start when data is detected in the bit stream with the compare func-

tions. See Section 20.7.6

for more details on receive compare modes.

Detection on TX_FRAME_SYNC input/output is done by the Transmit Frame Sync Output

Selection field in the TFMR register (TFMR.FSOS). Similarly, detection on RX_FRAME_SYNC input/output is done by the Receive Frame Output Sync Selection field in the RFMR register

(RFMR.FSOS).

267

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

Figure 20-10. Transmit Start Mode

TX_CLOCK (Input)

TX_FRAME_SYNC (Input)

TX_DATA (Output)

Start= Low Level on TX_FRAME_SYNC

TX_DATA (Output)

Start= Falling Edge on TX_FRAME_SYNC

TX_DATA (Output)

Start= High Level on TX_FRAME_SYNC

TX_DATA (Output)

Start= Rising Edge on TX_FRAME_SYNC

TX_DATA (Output)

Start= Level Change on TX_FRAME_SYNC

TX_DATA (Output)

Start= Any Edge on TX_FRAME_SYNC

X

X

X

X

B0

X

B0

X

B0

B1

B0

B1

B1

B0

B1

B0

B0

B1

B0

B1

STTDLY

STTDLY

B1

STTDLY

STTDLY

B1

STTDLY

STTDLY

Figure 20-11. Receive Pulse/Edge Start Modes

RX_CLOCK

RX_FRAME_SYNC (Input)

RX_DATA (Input)

Start = Low Level on RX_FRAME_SYNC

RX_DATA (Input)

Start = Falling Edge on RX_FRAME_SYNC

RX_DATA (Input)

Start = High Level on RX_FRAME_SYNC

RX_DATA (Input)

Start = Rising Edge on RX_FRAME_SYNC

RX_DATA (Input)

Start = Level Change on RX_FRAME_SYNC

RX_DATA (Input)

Start = Any Edge on RX_FRAME_SYNC

X

X

X

X

B0

X

B0

X

B1

B0

B1

B0

B1

B0

B1

B0

STTDLY

STTDLY

B1

STTDLY

STTDLY

B1

STTDLY

B0 B1

STTDLY

268

AT32UC3B

20.7.5

Frame Sync

The transmitter and receiver frame synchro pins, TX_FRAME_SYNC and RX_FRAME_SYNC, can be programmed to generate different kinds of frame synchronization signals. The

RFMR.FSOS and TFMR.FSOS fields are used to select the required waveform.

• Programmable low or high levels during data transfer are supported.

• Programmable high levels before the start of data transfers or toggling are also supported.

If a pulse waveform is selected, in reception, the Receive Frame Sync Length High Part and the

Receive Frame Sync Length fields in the RFMR register (RFMR.FSLENHI and RFMR.FSLEN) define the length of the pulse, from 1 bit time up to 256 bit time.

Reception Pulse Length = ((16 FSLENHI

Similarly, in transmission, the Transmit Frame Sync Length High Part and the Transmit Frame

Sync Length fields in the TFMR register (TFMR.FSLENHI and TFMR.FSLEN) define the length of the pulse, from 1 bit up to 256 bit time.

Transmission Pulse Length = ((16 FSLENHI

20.7.5.1

20.7.5.2

The periodicity of the RX_FRAME_SYNC and TX_FRAME_SYNC pulse outputs can be configured respectively through the Receive Period Divider Selection field in the RCMR register

(RCMR.PERIOD) and the Transmit Period Divider Selection field in the TCMR register

(TCMR.PERIOD).

Frame sync data

Frame Sync Data transmits or receives a specific tag during the Frame Sync signal.

During the Frame Sync signal, the receiver can sample the RX_DATA line and store the data in the Receive Sync Holding Register (RSHR) and the transmitter can transfer the Transmit Sync

Holding Register (TSHR) in the shifter register.

The data length to be sampled in reception during the Frame Sync signal shall be written to the

RFMR.FSLENHI and RFMR.FSLEN fields.

The data length to be shifted out in transmission during the Frame Sync signal shall be written to the TFMR.FSLENHI and TFMR.FSLEN fields.

Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the RSHR through the receive shift register.

The Transmit Frame Sync operation is performed by the transmitter only if the Frame Sync Data

Enable bit in TFMR register (TFMR.FSDEN) is written to one. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the TSHR is transferred in the transmit register, then shifted out.

Frame sync edge detection

The Frame Sync Edge detection is configured by writing to the Frame Sync Edge Detection bit in the RFMR/TFMR registers (RFMR.FSEDGE and TFMR.FSEDGE). This sets the Receive Sync

269

32059L–AVR32–01/2012

AT32UC3B

20.7.6

and Transmit Sync bits in the SR register (SR.RXSYN and SR.TXSYN) on frame synchro edge detection (signals RX_FRAME_SYNC/TX_FRAME_SYNC).

Receive Compare Modes

Figure 20-12. Receive Compare Modes

RX_CLOCK

RX_DATA

(Input)

CMP0

CMP1

CMP2

CMP3

Start

Ignored

B0

B1

B2

{FSLENHI,FSLEN}

Up to 256 Bits

(4 in This Example)

STTDLY DATLEN

20.7.6.1

20.7.7

Compare functions

Compare 0 can be one start event of the receiver. In this case, the receiver compares at each new sample the last {RFMR.FSLENHI, RFMR.FSLEN} bits received to the {RFMR.FSLENHI,

RFMR.FSLEN} lower bits of the data contained in the Receive Compare 0 Register (RC0R).

When this start event is selected, the user can program the receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the Receive Stop Selection bit in the RCMR register (RCMR.STOP).

Data Framing Format

The data framing format of both the transmitter and the receiver are programmable through the

TFMR, TCMR, RFMR, and RCMR registers. In either case, the user can independently select:

• the event that starts the data transfer (RCMR.START and TCMR.START)

• the delay in number of bit periods between the start event and the first data bit

(RCMR.STTDLY and TCMR.STTDLY)

• the length of the data (RFMR.DATLEN and TFMR.DATLEN)

• the number of data to be transferred for each start event (RFMR.DATNB and

TFMR.DATLEN)

• the length of synchronization transferred for each start event (RFMR.FSLENHI,

RFMR.FSLEN, TFMR.FSLENHI, and TFMR.FSLEN)

• the bit sense: most or lowest significant bit first (RFMR.MSBF and TFMR.MSBF)

Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TX_DATA pin while not in data transfer operation. This is done respectively by writing to the Frame Sync Data Enable and the Data Default Value bits in the TFMR register

(TFMR.FSDEN and TFMR.DATDEF).

Table 20-3.

Data Framing Format Registers

Transmitter

TCMR

Receiver

RCMR

Bit/Field

PERIOD

TCMR

TCMR

RCMR

RCMR

START

STTDLY

Length

Up to 512

Up to 255

Frame size

Comment

Start selection

Size of transmit start delay

270

32059L–AVR32–01/2012

AT32UC3B

Table 20-3.

Data Framing Format Registers

Transmitter Receiver Bit/Field

TFMR RFMR DATNB

TFMR

TFMR

TFMR

TFMR

TFMR

RFMR

RFMR

RFMR

DATLEN

{FSLENHI,FSLEN}

MSBF

FSDEN

DATDEF

Length

Up to 16

Up to 32

Up to 256

Figure 20-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes

Start

PERIOD

TX_FRAME_SYNC

/

RX_FRAME_SYNC

(1)

FSLEN

TX_DATA

(If FSDEN = 1)

Sync Data

From TSHR

Default

From DATDEF

Data

From THR

Data

From THR

TX_DATA

(If FSDEN = 0)

RX_DATA

Default

From DATDEF

Sync Data

To RSHR

Ignored

Data

From THR

Data

To RHR

Data

From THR

Data

To RHR

STTDLY DATLEN DATLEN

Comment

Number of words transmitted in frame

Size of word

Size of Synchro data register

Most significant bit first

Enable send TSHR

Data default value ended

Start

Default

From DATDEF

Sync Data

Default

From DATDEF

Ignored

Sync Data

DATNB

Note: Example of input on falling edge of TX_FRAME_SYNC/RX_FRAME_SYNC.

Figure 20-14. Transmit Frame Format in Continuous Mode

Start

32059L–AVR32–01/2012

TX_DATA

Data

From THR

DATLEN

Start: 1. TXEMPTY set to one

2. Write into the THR

Data

From THR

DATLEN

Default

Note: STTDLY is written to zero. In this example, THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode.

271

AT32UC3B

Figure 20-15. Receive Frame Format in Continuous Mode

Start = Enable Receiver

RX_DATA Data

To RHR

DATLEN

Data

To RHR

DATLEN

Note: STTDLY is written to zero.

20.7.8

Loop Mode

The receiver can be programmed to receive transmissions from the transmitter. This is done by writing a one to the Loop Mode bit in RFMR register (RFMR.LOOP). In this case, RX_DATA is connected to TX_DATA, RX_FRAME_SYNC is connected to TX_FRAME_SYNC and

RX_CLOCK is connected to TX_CLOCK.

20.7.9

Interrupt

Most bits in the SR register have a corresponding bit in interrupt management registers.

The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing to the Interrupt Enable Register (IER) and Interrupt Disable Register (IDR).

These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in the Interrupt Mask Register (IMR), which controls the generation of interrupts by asserting the SSC interrupt line connected to the interrupt controller.

Figure 20-16. Interrupt Block Diagram

IM R

IE R

S e t

ID R

C le a r

T ra n s m itte r

T X R D Y

T X E M P T Y

T X S Y N C

In te rru p t

C o n tro l

S S C In te rru p t

R e c e iv e r

R X R D Y

O V R U N

R X S Y N C

272

32059L–AVR32–01/2012

AT32UC3B

20.8 SSC Application Examples

The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here.

Figure 20-17. Audio Application Block Diagram

Clock SCK

TX_CLOCK

Word Select WS

TX_FRAME_SYNC

Data SD

TX_DATA

SSC

RX_DATA

Clock SCK

RX_FRAME_SYNC

Word Select WS

I2S

RECEIVER

RX_CLOCK

Data SD MSB

Left Channel

LSB MSB

Right Channel

Figure 20-18. Codec Application Block Diagram

Serial Data Clock (SCLK)

TX_CLOCK

Frame sync (FSYNC)

TX_FRAME_SYNC

Serial Data Out

TX_DATA

SSC

Serial Data In

RX_DATA

CODEC

RX_FRAME_SYNC

RX_CLOCK

Serial Data Clock (SCLK)

Frame sync (FSYNC)

First Time Slot

Dstart

Dend

Serial Data Out

Serial Data In

273

32059L–AVR32–01/2012

AT32UC3B

Figure 20-19. Time Slot Application Block Diagram

SCLK

TX_CLOCK

FSYNC

TX_FRAME_SYNC

Data Out

TX_DATA

SSC

RX_DATA

Data in

RX_FRAME_SYNC

RX_CLOCK

CODEC

First

Time Slot

CODEC

Second

Time Slot

Serial Data Clock (SCLK)

Frame sync (FSYNC)

Serial Data Out

Serial Data In

First Time Slot

Dstart

Second Time Slot

Dend

274

32059L–AVR32–01/2012

AT32UC3B

20.9 User Interface

Table 20-4.

SSC Register Memory Map

0x24

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x4C

Offset

0x00

0x04

0x10

0x14

0x18

0x1C

0x20

Register

Control Register

Clock Mode Register

Receive Clock Mode Register

Receive Frame Mode Register

Transmit Clock Mode Register

Transmit Frame Mode Register

Receive Holding Register

Transmit Holding Register

Receive Synchronization Holding Register

Transmit Synchronization Holding Register

Receive Compare 0 Register

Receive Compare 1 Register

Status Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Register Name

CR

CMR

RCMR

RFMR

TCMR

TFMR

RHR

THR

RSHR

TSHR

RC0R

RC1R

SR

IER

IDR

IMR

Access

Write-only

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read-only

Write-only

Read-only

Read/Write

Read/Write

Read/Write

Read-only

Write-only

Write-only

Read-only

Reset

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x000000CC

0x00000000

0x00000000

0x00000000

275

32059L–AVR32–01/2012

AT32UC3B

20.9.1

Name:

Control Register

CR

Access Type:

Offset:

Reset value:

Write-only

0x00

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

25

-

17

-

24

-

16

-

15

SWRST

14

-

13

-

12

-

11

-

10

-

9

TXDIS

8

TXEN

7

-

6

-

5

-

4

-

3

-

2

-

1

RXDIS

0

RXEN

• SWRST: Software Reset

1: Writing a one to this bit will perform a software reset. This software reset has priority on any other bit in CR.

0: Writing a zero to this bit has no effect.

• TXDIS: Transmit Disable

1: Writing a one to this bit will disable the transmission. If a character is currently being transmitted, the disable occurs at the end of the current character transmission.

0: Writing a zero to this bit has no effect.

• TXEN: Transmit Enable

1: Writing a one to this bit will enable the transmission if the TXDIS bit is not written to one.

0: Writing a zero to this bit has no effect.

• RXDIS: Receive Disable

1: Writing a one to this bit will disable the reception. If a character is currently being received, the disable occurs at the end of current character reception.

0: Writing a zero to this bit has no effect.

• RXEN: Receive Enable

1: Writing a one to this bit will enables the reception if the RXDIS bit is not written to one.

0: Writing a zero to this bit has no effect.

276

32059L–AVR32–01/2012

AT32UC3B

20.9.2

Name:

Clock Mode Register

CMR

Access Type:

Offset:

Reset value:

Read/Write

0x04

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

11

26

-

18

-

25

-

17

-

24

-

16

-

8 15

-

14

-

13

-

12

-

10

DIV[11:8]

9

7 6 5 4 3 2 1 0

DIV[7:0]

• DIV[11:0]: Clock Divider

The divided clock equals the CLK_SSC divided by two times DIV. The maximum bit rate is CLK_SSC/2. The minimum bit rate is

CLK_SSC/(2 x 4095) = CLK_SSC/8190.

The clock divider is not active when DIV equals zero.

Divided Clock = CLK_SSC (

×

277

32059L–AVR32–01/2012

AT32UC3B

20.9.3

Name:

Receive Clock Mode Register

RCMR

Access Type:

Offset:

Reset value:

Read/Write

0x10

0x00000000

31

23

30

22

29

21

28

PERIOD

27

20

STTDLY

19

26

18

25

17

24

16

15

-

14

-

13

-

12

STOP

11 10

START

9 8

7

CKG

6 5

CKI

4 3

CKO

2 1

CKS

0

• PERIOD: Receive Period Divider Selection

This field selects the divider to apply to the selected receive clock in order to generate a periodic Frame Sync Signal.

If equal to zero, no signal is generated.

If not equal to zero, a signal is generated each 2 x (PERIOD+1) receive clock periods.

• STTDLY: Receive Start Delay

If STTDLY is not zero, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.

When the receiver is programmed to start synchronously with the transmitter, the delay is also applied.

Note: It is very important that STTDLY be written carefully. If STTDLY must be written, it should be done in relation to Receive

Sync Data reception.

• STOP: Receive Stop Selection

1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.

0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new

Compare 0.

278

32059L–AVR32–01/2012

AT32UC3B

• START: Receive Start Selection

START Receive Start

0

1

2

3

4

5

6

7

8

Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.

Transmit start

Detection of a low level on RX_FRAME_SYNC signal

Detection of a high level on RX_FRAME_SYNC signal

Detection of a falling edge on RX_FRAME_SYNC signal

Detection of a rising edge on RX_FRAME_SYNC signal

Detection of any level change on RX_FRAME_SYNC signal

Detection of any edge on RX_FRAME_SYNC signal

Compare 0

Others Reserved

• CKG: Receive Clock Gating Selection

CKG Receive Clock Gating

0 None, continuous clock

1

2

Receive Clock enabled only if RX_FRAME_SYNC is low

Receive Clock enabled only if RX_FRAME_SYNC is high

3 Reserved

• CKI: Receive Clock Inversion

CKI affects only the receive clock and not the output clock signal.

1: The data inputs (Data and Frame Sync signals) are sampled on receive clock rising edge. The Frame Sync signal output is shifted out on receive clock falling edge.

0: The data inputs (Data and Frame Sync signals) are sampled on receive clock falling edge. The Frame Sync signal output is shifted out on receive clock rising edge.

• CKO: Receive Clock Output Mode Selection

CKO Receive Clock Output Mode RX_CLOCK pin

0 None Input-only

Output

Output

1

2

Continuous receive clock

Receive clock only during data transfers

Others Reserved

• CKS: Receive Clock Selection

CKS Selected Receive Clock

0 Divided clock

1

2

3

TX_CLOCK clock signal

RX_CLOCK pin

Reserved

279

32059L–AVR32–01/2012

AT32UC3B

20.9.4

Name:

Receive Frame Mode Register

RFMR

Access Type:

Offset:

Reset value:

Read/Write

0x14

0x00000000

31 30

FSLENHI

29

21

FSOS

13

-

28 27

-

19

26

-

25

-

24

FSEDGE

16 23

-

15

-

22

14

-

20

12

-

11

18

10

FSLEN

DATNB

17

9 8

7

MSBF

6

-

5

LOOP

4 3 2

DATLEN

1 0

• FSLENHI: Receive Frame Sync Length High Part

The four MSB of the FSLEN field.

• FSEDGE: Receive Frame Sync Edge Detection

Determines which edge on Frame Sync will generate the SR.RXSYN interrupt.

FSEDGE Frame Sync Edge Detection

0

1

Positive edge detection

Negative edge detection

• FSOS: Receive Frame Sync Output Selection

FSOS Selected Receive Frame Sync Signal

0

1

None

Negative Pulse

4

5

2

3

Positive Pulse

Driven Low during data transfer

Driven High during data transfer

Toggling at each start of data transfer

RX_FRAME_SYNC Pin

Input-only

Output

Output

Output

Output

Output

Others Reserved Undefined

• FSLEN: Receive Frame Sync Length

This field defines the length of the Receive Frame Sync signal and the number of bits sampled and stored in the RSHR register.

When this mode is selected by the RCMR.START field, it also determines the length of the sampled data to be compared to the

Compare 0 or Compare 1 register.

Note: The four most significant bits for this field are located in the FSLENHI field.

The pulse length is equal to ({FSLENHI,FSLEN} + 1) receive clock periods. Thus, if {FSLENHI,FSLEN} is zero, the Receive

Frame Sync signal is generated during one receive clock period.

280

32059L–AVR32–01/2012

AT32UC3B

• DATNB: Data Number per Frame

This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).

• MSBF: Most Significant Bit First

1: The most significant bit of the data register is sampled first in the bit stream.

0: The lowest significant bit of the data register is sampled first in the bit stream.

• LOOP: Loop Mode

1: RX_DATA is driven by TX_DATA, RX_FRAME_SYNC is driven by TX_FRAME_SYNC and TX_CLOCK drives RX_CLOCK.

0: Normal operating mode.

• DATLEN: Data Length

The bit stream contains (DATLEN + 1) data bits.

This field also defines the transfer size performed by the Peripheral DMA Controller assigned to the receiver.

DATLEN

0

1-7

8-15

Others

Transfer Size

Forbidden value

Data transfer are in bytes

Data transfer are in halfwords

Data transfer are in words

281

32059L–AVR32–01/2012

AT32UC3B

20.9.5

Name:

Transmit Clock Mode Register

TCMR

Access Type:

Offset:

Reset value:

Read/Write

0x18

0x00000000

31

23

30

22

29

21

28

PERIOD

27

20

STTDLY

19

12

-

11

26

18

25

17

24

16

15

-

14

-

13

-

10

START

9 8

7

CKG

6 5

CKI

4 3

CKO

2 1

CKS

0

• PERIOD: Transmit Period Divider Selection

This field selects the divider to apply to the selected transmit clock in order to generate a periodic Frame Sync Signal.

If equal to zero, no signal is generated.

If not equal to zero, a signal is generated each 2 x (PERIOD+1) transmit clock periods.

• STTDLY: Transmit Start Delay

If STTDLY is not zero, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission.

When the transmitter is programmed to start synchronously with the receiver, the delay is also applied.

Note: STTDLY must be written carefully, in relation to Transmit Sync Data transmission.

• START: Transmit Start Selection

START Transmit Start

0

1

Continuous, as soon as a word is written to the THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.

Receive start

4

5

2

3

6

7

Others

Detection of a low level on TX_FRAME_SYNC signal

Detection of a high level on TX_FRAME_SYNC signal

Detection of a falling edge on TX_FRAME_SYNC signal

Detection of a rising edge on TX_FRAME_SYNC signal

Detection of any level change on TX_FRAME_SYNC signal

Detection of any edge on TX_FRAME_SYNC signal

Reserved

282

32059L–AVR32–01/2012

AT32UC3B

• CKG: Transmit Clock Gating Selection

CKG Transmit Clock Gating

2

3

0

1

None, continuous clock

Transmit Clock enabled only if TX_FRAME_SYNC is low

Transmit Clock enabled only if TX_FRAME_SYNC is high

Reserved

• CKI: Transmit Clock Inversion

CKI affects only the Transmit Clock and not the output clock signal.

1: The data outputs (Data and Frame Sync signals) are shifted out on transmit clock rising edge. The Frame sync signal input is sampled on transmit clock falling edge.

0: The data outputs (Data and Frame Sync signals) are shifted out on transmit clock falling edge. The Frame sync signal input is sampled on transmit clock rising edge.

• CKO: Transmit Clock Output Mode Selection

CKO Transmit Clock Output Mode TX_CLOCK pin

0

1

None

Continuous transmit clock

Input-only

Output

Output 2 Transmit clock only during data transfers

Others Reserved

• CKS: Transmit Clock Selection

CKS Selected Transmit Clock

2

3

0

1

Divided Clock

RX_CLOCK clock signal

TX_CLOCK Pin

Reserved

283

32059L–AVR32–01/2012

AT32UC3B

20.9.6

Name:

Transmit Frame Mode Register

TFMR

Access Type:

Offset:

Reset value:

Read/Write

0x1C

0x00000000

31 30

FSLENHI

29

22

14

-

21

FSOS

13

-

28 27

-

19

26

-

25

-

18

FSLEN

17

10

DATNB

9

24

FSEDGE

16 23

FSDEN

15

-

20

12

-

11 8

7

MSBF

6

-

5

DATDEF

4 3 2

DATLEN

1 0

• FSLENHI: Transmit Frame Sync Length High Part

The four MSB of the FSLEN field.

• FSEDGE: Transmit Frame Sync Edge Detection

Determines which edge on Frame Sync will generate the SR.TXSYN interrupt.

FSEDGE Frame Sync Edge Detection

0

1

Positive Edge Detection

Negative Edge Detection

• FSDEN: Transmit Frame Sync Data Enable

1: TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.

0: The TX_DATA line is driven with the default value during the Transmit Frame Sync signal.

• FSOS: Transmit Frame Sync Output Selection

FSOS Selected Transmit Frame Sync Signal TX_FRAME_SYNC Pin

0 None Input-only

3

4

1

2

Negative Pulse

Positive Pulse

Driven Low during data transfer

Driven High during data transfer

Output

Output

Output

Output

5

Others

Toggling at each start of data transfer

Reserved

Output

Undefined

• FSLEN: Transmit Frame Sync Length

This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the TSHR register if

TFMR.FSDEN is equal to one.

Note: The four most significant bits for this field are located in the FSLENHI field.

284

32059L–AVR32–01/2012

AT32UC3B

The pulse length is equal to ({FSLENHI,FSLEN} + 1) transmit clock periods, i.e., the pulse length can range from 1 to 256 transmit clock periods. If {FSLENHI,FSLEN} is zero, the Transmit Frame Sync signal is generated during one transmit clock period.

• DATNB: Data Number per Frame

This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB + 1).

• MSBF: Most Significant Bit First

1: The most significant bit of the data register is shifted out first in the bit stream.

0: The lowest significant bit of the data register is shifted out first in the bit stream.

• DATDEF: Data Default Value

This bit defines the level driven on the TX_DATA pin while out of transmission.

Note that if the pin is defined as multi-drive by the I/O Controller, the pin is enabled only if the TX_DATA output is one.

1: The level driven on the TX_DATA pin while out of transmission is one.

0: The level driven on the TX_DATA pin while out of transmission is zero.

• DATLEN: Data Length

The bit stream contains (DATLEN + 1) data bits.

This field also defines the transfer size performed by the Peripheral DMA Controller assigned to the transmitter.

DATLEN

0

1-7

8-15

Others

Transfer Size

Forbidden value (1-bit data length is not supported)

Data transfer are in bytes

Data transfer are in halfwords

Data transfer are in words

285

32059L–AVR32–01/2012

20.9.7

Name:

Receive Holding Register

RHR

Access Type:

Offset:

Reset value:

Read-only

0x20

0x00000000

31

23

30

22

29

21

28

RDAT[31:24]

27

20

RDAT[23:16]

19

26

18

15 14 13 12

RDAT[15:8]

11 10

7 6 5 4 3 2

RDAT[7:0]

• RDAT: Receive Data

Right aligned regardless of the number of data bits defined by the RFMR.DATLEN field.

9

1

25

17

AT32UC3B

8

0

24

16

286

32059L–AVR32–01/2012

20.9.8

Name:

Transmit Holding Register

THR

Access Type:

Offset:

Reset value:

Write-only

0x24

0x00000000

31

23

30

22

29

21

28

TDAT[31:24]

27

20

TDAT[23:16]

19

26

18

15 14 13 12

TDAT[15:8]

11 10

7 6 5 4 3 2

TDAT[7:0]

• TDAT: Transmit Data

Right aligned regardless of the number of data bits defined by the TFMR.DATLEN field.

9

1

25

17

AT32UC3B

8

0

24

16

287

32059L–AVR32–01/2012

AT32UC3B

20.9.9

Name:

Receive Synchronization Holding Register

RSHR

Access Type:

Offset:

Reset value:

Read-only

0x30

0x00000000

31

-

23

-

15

30

-

22

-

14

29

-

21

-

13

7 6 5

28

-

20

-

12

RSDAT[15:8]

11

4

RSDAT[7:0]

3

27

-

19

-

• RSDAT: Receive Synchronization Data

26

-

18

-

10

2

25

-

17

-

9

1

24

-

16

-

8

0

288

32059L–AVR32–01/2012

AT32UC3B

20.9.10

Transmit Synchronization Holding Register

Name:

TSHR

Access Type:

Offset:

Reset value:

Read/Write

0x34

0x00000000

31

-

23

-

15

30

-

22

-

14

29

-

21

-

13

7 6 5

28

-

20

-

12

TSDAT[15:8]

11

4

TSDAT[7:0]

3

27

-

19

-

• TSDAT: Transmit Synchronization Data

26

-

18

-

10

2

25

-

17

-

9

1

24

-

16

-

8

0

289

32059L–AVR32–01/2012

AT32UC3B

20.9.11

Receive Compare 0 Register

Name:

RC0R

Access Type:

Offset:

Reset value:

Read/Write

0x38

0x00000000

31

-

23

-

15

30

-

22

-

14

29

-

21

-

13

7 6

CP0: Receive Compare Data 0

5

28

-

20

-

12

CP0[15:8]

11

4

CP0[7:0]

3

27

-

19

-

26

-

18

-

10

2

25

-

17

-

9

1

24

-

16

-

8

0

290

32059L–AVR32–01/2012

AT32UC3B

20.9.12

Receive Compare 1 Register

Name:

RC1R

Access Type:

Offset:

Reset value:

Read/Write

0x3C

0x00000000

31

-

23

-

15

30

-

22

-

14

29

-

21

-

13

7 6

• CP1: Receive Compare Data 1

5

28

-

20

-

12

CP1[[15:8]

11

4

CP1[7:0]

3

27

-

19

-

26

-

18

-

10

2

25

-

17

-

9

1

24

-

16

-

8

0

291

32059L–AVR32–01/2012

AT32UC3B

20.9.13

Status Register

Name:

SR

Access Type:

Offset:

Reset value:

Read-only

0x40

0x000000CC

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

RXSYN

26

-

18

-

10

TXSYN

25

-

17

RXEN

9

CP1

24

-

16

TXEN

8

CP0

7

-

6

-

5

OVRUN

4

RXRDY

3

-

2

-

1

TXEMPTY

0

TXRDY

• RXEN: Receive Enable

This bit is set when the CR.RXEN bit is written to one.

This bit is cleared when no data are being processed and the CR.RXDIS bit has been written to one.

• TXEN: Transmit Enable

This bit is set when the CR.TXEN bit is written to one.

This bit is cleared when no data are being processed and the CR.TXDIS bit has been written to one.

• RXSYN: Receive Sync

This bit is set when a Receive Sync has occurred.

This bit is cleared when the SR register is read.

• TXSYN: Transmit Sync

This bit is set when a Transmit Sync has occurred.

This bit is cleared when the SR register is read.

• CP1: Compare 1

This bit is set when compare 1 has occurred.

This bit is cleared when the SR register is read.

• CP0: Compare 0

This bit is set when compare 0 has occurred.

This bit is cleared when the SR register is read.

• OVRUN: Receive Overrun

This bit is set when data has been loaded in the RHR register while previous data has not yet been read.

This bit is cleared when the SR register is read.

• RXRDY: Receive Ready

This bit is set when data has been received and loaded in the RHR register.

This bit is cleared when the RHR register is empty.

• TXEMPTY: Transmit Empty

This bit is set when the last data written in the THR register has been loaded in the TSR register and last data loaded in the TSR register has been transmitted.

This bit is cleared when data remains in the THR register or is currently transmitted from the TSR register.

292

32059L–AVR32–01/2012

AT32UC3B

• TXRDY: Transmit Ready

This bit is set when the THR register is empty.

This bit is cleared when data has been loaded in the THR register and is waiting to be loaded in the TSR register.

32059L–AVR32–01/2012

293

AT32UC3B

20.9.14

Interrupt Enable Register

Name:

IER

Access Type:

Offset:

Reset value:

Write-only

0x44

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

RXSYN

7

6

5

OVRUN

4

RXRDY

3

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will set the corresponding bit in IMR.

10

TXSYN

2

26

-

18

-

25

-

17

-

9

CP1

1

TXEMPTY

8

CP0

0

TXRDY

24

-

16

-

294

32059L–AVR32–01/2012

AT32UC3B

20.9.15

Interrupt Disable Register

Name:

IDR

Access Type:

Offset:

Reset value:

Write-only

0x48

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

RXSYN

7

6

5

OVRUN

4

RXRDY

3

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will clear the corresponding bit in IMR.

10

TXSYN

2

26

-

18

-

25

-

17

-

9

CP1

1

TXEMPTY

8

CP0

0

TXRDY

24

-

16

-

295

32059L–AVR32–01/2012

AT32UC3B

20.9.16

Interrupt Mask Register

Name:

IMR

Access Type:

Offset:

Reset value:

Read-only

0x4C

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

RXSYN

10

TXSYN

7

6

5

OVRUN

4

RXRDY

3

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

A bit in this register is cleared when the corresponding bit in IDR is written to one.

A bit in this register is set when the corresponding bit in IER is written to one.

2

26

-

18

-

25

-

17

-

9

CP1

1

TXEMPTY

8

CP0

0

TXRDY

24

-

16

-

296

32059L–AVR32–01/2012

AT32UC3B

21. Universal Synchronous Asynchronous Receiver Transmitter (USART)

Rev: 4.0.0.6

21.1 Features

Configurable baud rate generator

5- to 9-bit full-duplex, synchronous and asynchronous, serial communication

– 1, 1.5, or 2 stop bits in asynchronous mode, and 1 or 2 in synchronous mode

– Parity generation and error detection

– Framing- and overrun error detection

– MSB- or LSB-first

– Optional break generation and detection

– Receiver frequency over-sampling by 8 or 16 times

– Optional RTS-CTS hardware handshaking

– Optional DTR-DSR-DCD-RI modem signal management

– Receiver Time-out and transmitter Timeguard

– Optional Multidrop mode with address generation and detection

RS485 with line driver control

ISO7816, T=0 and T=1 protocols for Interfacing with smart cards

– , NACK handling, and customizable error counter

IrDA modulation and demodulation

– Communication at up to 115.2Kbit/s

SPI Mode

– Master or slave

– Configurable serial clock phase and polarity

– CLK SPI serial clock frequency up to a quarter of the CLK_USART internal clock frequency

Test Modes

– Automatic echo, remote- and local loopback

Supports two Peripheral DMA Controller channels

– Buffer transfers without processor intervention

21.2 Overview

The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides a full duplex, universal, synchronous/asynchronous serial link. Data frame format is widely configurable, including basic length, parity, and stop bit settings, maximizing standards support. The receiver implements parity-, framing-, and overrun error detection, and can handle un-fixed frame lengths with the time-out feature. The USART supports several operating modes, providing an interface to RS485 and SPI buses, with ISO7816 T=0 and T=1 smart card slots, infrared transceivers, and modem port connections. Communication with slow and remote devices is eased by the timeguard. Duplex multidrop communication is supported by address and data differentiation through the parity bit. The hardware handshaking feature enables an out-of-band flow control, automatically managing RTS and CTS pins. The Peripheral DMA Controller connection enables memory transactions, and the USART supports chained buffer management without processor intervention. Automatic echo, remote-, and local loopback -test modes are also supported.

297

32059L–AVR32–01/2012

AT32UC3B

21.3 Block Diagram

Figure 21-1. USART Block Diagram

USART

Peripheral DMA

Controller

Channel Channel

INTC

USART

Interrupt

Receiver

Transmitter

I/O

Controller

Power

Manager

CLK_USART

DIV

CLK_USART/DIV

Modem

Signals

Control

Peripheral bus

User

Interface

BaudRate

Generator

RXD

RTS

TXD

CTS

DTR

DSR

DCD

RI

CLK

Table 21-1.

SPI Operating Mode

PIN

RXD

USART

RXD

TXD

RTS

CTS

TXD

RTS

CTS

SPI Slave

MOSI

MISO

CS

SPI Master

MISO

MOSI

CS

298

32059L–AVR32–01/2012

AT32UC3B

21.4 I/O Lines Description

Table 21-2.

I/O Lines Description

Name

CLK

TXD

RXD

RI

DSR

DCD

DTR

CTS

RTS

Description

Serial Clock

Transmit Serial Data or Master Out Slave In (MOSI) in SPI master mode or Master In Slave Out (MISO) in SPI slave mode

Receive Serial Data or Master In Slave Out (MISO) in SPI master mode or Master Out Slave In (MOSI) in SPI slave mode

Ring Indicator

Data Set Ready

Data Carrier Detect

Data Terminal Ready

Clear to Send or Slave Select (NSS) in SPI slave mode

Request to Send or Slave Select (NSS) in SPI master mode

Type

I/O

Output

Input

Input

Input

Input

Output

Input

Output

Active Level

Low

Low

Low

Low

Low

Low

21.5 Product Dependencies

21.5.1

I/O Lines

The USART pins may be multiplexed with the I/O Controller lines. The user must first configure the I/O Controller to assign these pins to their peripheral functions. Unused I/O lines may be used for other purposes.

To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is required. If the hardware handshaking feature or modem mode is used, the internal pull up on

TXD must also be enabled.

All the pins of the modems may or may not be implemented on the USART. On USARTs not equipped with the corresponding pins, the associated control bits and statuses have no effect on the behavior of the USART.

21.5.2

Clocks

The clock for the USART bus interface (CLK_USART) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the USART before disabling the clock, to avoid freezing the USART in an undefined state.

21.5.3

Interrupts

The USART interrupt request line is connected to the interrupt controller. Using the USART interrupt requires the interrupt controller to be programmed first.

299

32059L–AVR32–01/2012

AT32UC3B

21.6 Functional Description

21.6.1

Selecting Mode

The USART can operate in several modes. The operating mode is selected by writing to the

Mode field in the

“Mode Register”

(MR.MODE). In addition, Synchronous or Asynchronous mode is selected by writing to the Synchronous Mode Select bit in MR (MR.SYNC).

21.6.2

Baud Rate Generator

The baud rate generator provides the bit period clock named the Baud Rate Clock to both receiver and transmitter. It is based on a 16-bit divider, which is specified in the Clock Divider field in the Baud Rate Generator Register (BRGR.CD). A non-zero value enables the generator, and if CD is one, the divider is bypassed and inactive. The Clock Selection field in the Mode

Register (MR.USCLKS) selects clock source between:

• CLK_USART (internal clock, refer to Power Manager chapter for details)

• CLK_USART/DIV (a divided CLK_USART, refer to Module Configuration section)

• CLK (external clock, available on the CLK pin)

If the external CLK clock is selected, the duration of the low and high levels of the signal provided on the CLK pin must be at least 4.5 times longer than those provided by CLK_USART.

Figure 21-2. Baud Rate Generator

USCLKS

CD

CD

CLK_USART

CLK_USART/DIV

CLK

Reserved

2

3

0

1

16-bit Counter

0

>1

1

0

0

1

OVER

FIDI

Sampling

Divider

0

CLK

SYNC

BaudRate

Clock

1

SYNC

USCLKS= 3

Sampling

Clock

21.6.2.1

Baud Rate in Asynchronous Mode

If the USART is configured to operate in an asynchronous mode, the selected clock is divided by the CD value before it is provided to the receiver as a sampling clock. Depending on the Oversampling Mode bit (MR.OVER) value, the clock is then divided by either 8 (OVER=1), or 16

(OVER=0). The baud rate is calculated with the following formula:

BaudRate

=

(

SelectedClock

8 2 OVER

)CD )

This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is the fastest clock possible, and that OVER is one.

300

32059L–AVR32–01/2012

AT32UC3B

21.6.2.2

Baud Rate Calculation Example

Table 21-3

shows calculations based on the CD field to obtain 38400 baud from different source clock frequencies. This table also shows the actual resulting baud rate and error.

Source Clock (Hz)

3 686 400

4 915 200

5 000 000

7 372 800

8 000 000

12 000 000

12 288 000

14 318 180

14 745 600

18 432 000

24 000 000

24 576 000

25 000 000

32 000 000

32 768 000

33 000 000

40 000 000

50 000 000

60 000 000

Table 21-3.

Baud Rate Example (OVER=0)

Expected Baud

Rate (bit/s)

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

Calculation Result

6.00

8.00

8.14

12.00

13.02

19.53

20.00

23.30

24.00

30.00

39.06

40.00

40.69

52.08

53.33

53.71

65.10

81.38

97.66

39

40

40

52

20

23

24

30

53

54

65

81

98

8

12

13

20

CD

6

8

Actual Baud Rate (bit/s)

38 400.00

38 400.00

39 062.50

38 400.00

38 461.54

37 500.00

38 400.00

38 908.10

38 400.00

38 400.00

38 461.54

38 400.00

38 109.76

38 461.54

38 641.51

38 194.44

38 461.54

38 580.25

38 265.31

0.00%

1.31%

0.00%

0.00%

0.16%

0.00%

0.76%

0.16%

Error

0.00%

0.00%

1.70%

0.00%

0.16%

2.40%

0.63%

0.54%

0.16%

0.47%

0.35%

The baud rate is calculated with the following formula (OVER=0):

BaudRate

=

(

CLKUSART

⁄ ( × )

The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%.

Error

=

1

ActualBaudRate

21.6.2.3

Fractional Baud Rate in Asynchronous Mode

The baud rate generator has a limitation: the source frequency is always a multiple of the baud rate. An approach to this problem is to integrate a high resolution fractional N clock generator, outputting fractional multiples of the reference source clock. This fractional part is selected with the Fractional Part field (BRGR.FP), and is activated by giving it a non-zero value. The resolution is one eighth of CD. The resulting baud rate is calculated using the following formula:

BaudRate

=

8 2 OVER

+ -------

⎞ ⎞

301

32059L–AVR32–01/2012

AT32UC3B

The modified architecture is presented below:

Figure 21-3. Fractional Baud Rate Generator

FP

CD

Modulus

Control

USCLKS

CLK_USART

CLK_USART/DIV

CLK

Reserved

2

3

0

1

16-bit Counter

FP

CD glitch-free logic

0

>1

1

0

0

1

SYNC

USCLKS = 3

OVER

Sampling

Divider

CLK

SYNC

0

BaudRate

Clock

1

Sampling

Clock

21.6.2.4

21.6.2.5

Baud Rate in Synchronous and SPI Mode

If the USART is configured to operate in synchronous mode, the selected clock is divided by the

BRGR.CD field. This does not apply when CLK is selected.

BaudRate

=

CD

When CLK is selected the external frequency must be at least 4.5 times lower than the system clock, and when either CLK or CLK_USART/DIV are selected, CD must be even to ensure a

50/50 duty cycle. If CLK_USART is selected, the generator ensures this regardless of value.

Baud Rate in ISO 7816 Mode

The ISO7816 specification defines the bit rate with the following formula:

B

=

Fi

where:

• B is the bit rate

• Di is the bit-rate adjustment factor

• Fi is the clock frequency division factor

• f is the ISO7816 clock frequency (Hz)

302

32059L–AVR32–01/2012

AT32UC3B

Di is a binary value encoded on a 4-bit field, named DI, as represented in

Table 21-4

.

Table 21-4.

Binary and Decimal Values for Di

DI field

Di (decimal)

0001

1

0010

2

0011

4

0100

8

0101

16

0110

32

1000

12

1001

20

Fi is a binary value encoded on a 4-bit field, named FI, as represented in

Table 21-5

.

Table 21-5.

Binary and Decimal Values for Fi

FI field

Fi (decimal

0000

372

0001

372

0010

558

0011

744

0100

1116

0101

1488

0110

1860

1001

512

1010

768

1011

1024

1100

1536

1101

2048

Table 21-6

shows the resulting Fi/Di ratio, which is the ratio between the ISO7816 clock and the baud rate clock.

Table 21-6.

Possible Values for the Fi/Di Ratio

Fi 372 558 744 1116

Di=2

Di=4

Di=8

Di=16

Di=32

Di=12

Di=20

186

93

46.5

23.25

11.62

31

18.6

279

139.5

69.75

34.87

17.43

46.5

372

186

93

46.5

23.25

62

558

279

139.5

69.75

34.87

93

1488

744

372

186

93

46.5

124

1860

930

465

232.5

116.2

58.13

155

512

256

128

64

32

16

42.66

96

48

24

64

768

384

192

1024

512

256

128

64

32

85.33

1536

768

384

192

96

48

128

27.9

37.2

55.8

74.4

93 25.6

38.4

51.2

76.8

102.4

If the USART is configured to run in ISO7816 mode, the clock selected by the MR.USCLKS field is first divided by the CD value before it can be output on the CLK pin, to feed the smart card clock inputs, by writing a one to the Clock Output Select bit (MR.CLK0). It is then divided by the

FI Over DI Ratio Value field in the FI DI Ratio Register (FIDI.FI_DI_RATIO), which can be up to

2047 in ISO7816 mode. This will be rounded off to an integral so the user has to select a

FI_DI_RATIO value that comes as close as possible to the expected Fi/Di ratio. The

FI_DI_RATIO reset value is 0x174 (372 in decimal) and is the most common divider between the

ISO7816 clock and bit rate (Fi=372, Di=1). Figure 21-4

shows the relationship between the Elementary Time Unit (ETU), corresponding to a bit period, and the ISO 7816 clock.

2048

1024

512

256

128

64

170.6

Figure 21-4. Elementary Time Unit (ETU)

FI_DI_RATIO

ISO7816 Clock Cycles

ISO7816 Clock on CLK

ISO7816 I/O Line on TXD

1 ETU

303

32059L–AVR32–01/2012

AT32UC3B

21.6.3

Receiver and Transmitter Control

After a reset, the transceiver is disabled. The receiver/transmitter is enabled by writing a one to either the Receiver Enable, or Transmitter Enable bit in the Control Register (CR.RXEN, or

CR.TXEN). They may be enabled together and can be configured both before and after they have been enabled. The user can reset the USART receiver/transmitter at any time by writing a one to either the Reset Receiver (CR.RSTRX), or Reset Transmitter (CR.RSTTX) bit. This software reset clears status bits and resets internal state machines, immediately halting any communication. The user interface configuration registers will retain their values.

The user can disable the receiver/transmitter by writing a one to either the Receiver Disable, or

Transmitter Disable bit (CR.RXDIS, or CR.TXDIS). If the receiver is disabled during a character reception, the USART will wait for the current character to be received before disabling. If the transmitter is disabled during transmission, the USART will wait until both the current character and the character stored in the Transmitter Holding Register (THR) are transmitted before disabling. If a timeguard has been implemented it will remain functional during the transaction.

21.6.4

21.6.4.1

Synchronous and Asynchronous Modes

Transmitter Operations

The transmitter performs equally in both synchronous and asynchronous operating modes

(MR.SYNC). One start bit, up to 9 data bits, an optional parity bit, and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the serial clock. The number of data bits is selected by the Character Length field (MR.CHRL) and the MR.MODE9 bit. Nine bits are selected by writing a one to MODE9, overriding any value in CHRL. The parity bit configuration is selected in the MR.PAR field. The Most Significant Bit First bit (MR.MSBF) selects which data bit to send first. The number of stop bits is selected by the MR.NBSTOP field. The 1.5 stop bit configuration is only supported in asynchronous mode.

Figure 21-5. Character Transmit

Example: 8-bit, Parity Enabled One Stop

Baud Rate

Clock

TXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7 Parity

Bit

Stop

Bit

The characters are sent by writing to the Character to be Transmitted field (THR.TXCHR). The transmitter reports status with the Transmitter Ready (TXRDY) and Transmitter Empty

(TXEMPTY) bits in the Channel Status Register (CSR). TXRDY is set when THR is empty.

TXEMPTY is set when both THR and the transmit shift register are empty (transmission complete). Both TXRDY and TXEMPTY are cleared when the transmitter is disabled. Writing a character to THR while TXRDY is zero has no effect and the written character will be lost.

304

32059L–AVR32–01/2012

AT32UC3B

Figure 21-6. Transmitter Status

Baud Rate

Clock

TXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop Start

Bit Bit Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

Write

THR

TXRDY

21.6.4.2

TXEMPTY

Manchester Encoder

When the Manchester endec is used, characters transmitted through the USART are encoded in

Manchester II Biphase format. To enable this mode, write a one to MR.MAN. Depending on polarity configuration, as selected by the Transmission Manchester Polarity bit in the Manchester Configuration Register (MAN.TX_MOPL), a logic level (zero or one), is transmitted as the transition from high -to-low or low-to-high during the middle of each bit period. This consumes twice the bandwidth than the simpler NRZ coding schemes, but the receiver has more error control since the expected input has a transition at every mid-bit period. An example of a

Manchester encoded sequence is the byte 0xB1 or 10110001 being encoded to 10 01 10 10 01

01 01 10, assuming default encoder polarity.

Figure 21-7

illustrates this coding scheme.

Figure 21-7. NRZ to Manchester Encoding

1 0 1 NRZ encoded data

Manchester encoded data

Txd

1 0 0 0 1

A Manchester encoded character can be preceded by both a preamble sequence, and a start frame delimiter. The preamble sequence is a pre-defined pattern with a configurable length from

1 to 15 bit periods. If the preamble length is zero, the preamble waveform is not generated. The length is selected by writing to the Transmitter Preamble Length field (MAN.TX_PL). The available preamble sequence patterns are: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, and are selected by writing to the Transmitter Preamble Pattern field (MAN.TX_PP).

Figure 21-8

illustrates the supported patterns.

305

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

Figure 21-8. Preamble Patterns, Default Polarity Assumed

Manchester encoded data

Txd

8 bit width "ALL_ONE" Preamble

Manchester encoded data

Txd

8 bit width "ALL_ZERO" Preamble

Manchester encoded data

Txd

8 bit width "ZERO_ONE" Preamble

SFD DATA

SFD

DATA

SFD

DATA

Manchester encoded data

Txd

SFD

DATA

8 bit width "ONE_ZERO" Preamble

The Start Frame Delimiter Selector bit (MR.ONEBIT) configures the Manchester start bit pattern following the preamble. If MR.ONEBIT is one, a Manchester encoded zero is transmitted to indicate that a new character is about to be sent. If MR.ONEBIT is zero, a synchronization pattern is sent for the duration of three bit periods to inaugurate the new character. The sync pattern waveform by itself is an invalid Manchester encoding, since the transition only occurs at the middle of the second bit period.

The Manchester Synchronization Mode bit (MR.MODSYNC) selects sync pattern, and this also defines if the character is data (MODSYNC=0) with a zero to one transition, or a command

(MODSYNC=1) with a one to zero transition. When direct memory access is used, the sync pattern can be updated on-the-fly with a modified character located in memory. To enable this mode the Variable Synchronization of Command/Data Sync Start Frame Delimiter bit

(MR.VAR_SYNC) has to be written to one. In this case, MODSYNC is bypassed and

THR.TXSYNH selects the sync type to be included. Figure 21-9 illustrates supported patterns.

306

AT32UC3B

Figure 21-9. Start Frame Delimiter

Preamble Length is set to 0

SFD

Manchester encoded data

Txd

DATA

One bit start frame delimiter

SFD

Manchester encoded data

Txd

DATA

Command Sync start frame delimiter

SFD

Manchester encoded data

Txd

DATA

Data Sync start frame delimiter

Manchester Drift Compensation

The Drift compensation bit (MAN.DRIFT) enables a hardware drift compensation and recovery system that allows for sub-optimal clock drifts without further user intervention. Drift compensation is only available in 16x oversampling mode. If the RXD event is one 16 th

clock cycle from the expected edge, it is considered as normal jitter and no corrective action will be taken. If the event is two to four 16 th

’s early, the current period will be shortened by a 16 th

. If the event is two to three 16 th

’s after the expected edge, the current period will be prolonged by a 16 th

.

Figure 21-10. Bit Resynchronization

Oversampling

16x Clock

RXD

21.6.4.3

Sampling point

Synchro.

Error

Synchro.

Jump

Expected edge

Tolerance

Sync

Jump

Synchro.

Error

Asynchronous Receiver

If the USART is configured in an asynchronous operating mode (MR.SYNC = 0), the receiver will oversample the RXD input line by either 8 or 16 times the baud rate clock, as selected by the

Oversampling Mode bit (MR.OVER). If the line is zero for half a bit period (four or eight consecutive samples, respectively), a start bit will be assumed, and the following 8th or 16th sample will determine the logical value on the line, in effect resulting in bit values being determined at the middle of the bit period.

The number of data bits, endianess, parity mode, and stop bits are selected by the same bits and fields as for the transmitter (MR.CHRL, MODE9, MSBF, PAR, and NBSTOP). The synchro-

307

32059L–AVR32–01/2012

AT32UC3B

21.6.4.4

nization mechanism will only consider one stop bit, regardless of the used protocol, and when the first stop bit has been sampled, the receiver will automatically begin looking for a new start bit, enabling resynchronization even if there is a protocol miss-match.

Figure 21-11 and Figure

21-12 illustrate start bit detection and character reception in asynchronous mode.

Figure 21-11. Asynchronous Start Bit Detection

Baud Rate

Clock

Sampling

Clock (x16)

RXD

Sampling

1 2 3 4 5 6 7 8

Start

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

D0

Sampling

Detection

RXD

Sampling

1 2 3 4 5 6 7 0 1 2 3 4

Start

Rejection

Figure 21-12. Asynchronous Character Reception

Example: 8-bit, Parity Enabled

Baud Rate

Clock

RXD

Start

Detection

16 samples

16 samples

16 samples

16 samples

16 samples

16 samples

16 samples

16 samples

16 samples

16 samples

D0 D1 D2 D3 D4 D5 D6 D7

Parity

Bit

Stop

Bit

Manchester Decoder

When MR.MAN is one, the Manchester endec is enabled. The decoder can detect selectable preamble sequences and start frame delimiters. The Receiver Manchester Polarity bit

(MAN.RX_MPOL) selects input stream polarity. The Receiver Preamble Length field

(MAN.RX_PL) specifies the length characteristics of detectable preambles, and if written to zero the preamble pattern detection will be disabled. The Receiver Preamble Pattern field

(MAN.RX_PP) selects the pattern to be detected. See

Figure 21-8 for available preamble pat-

terns. Figure 21-13

illustrates two types of Manchester preamble pattern mismatches.

The Manchester endec uses the same Start Frame Delimiter Selector (MR.ONEBIT) for both encoder and decoder. If ONEBIT is one, only a Manchester encoded zero will be accepted as a valid start frame delimiter. If ONEBIT is zero, a data or command sync pattern will be expected.

The Received Sync bit in the Receive Holding Register (RHR.RXSYNH) will be zero if it is a data sync, and a one if it is a command sync.

308

32059L–AVR32–01/2012

AT32UC3B

Figure 21-13. Preamble Pattern Mismatch

Preamble Mismatch

Manchester coding error

Preamble Mismatch invalid pattern

Manchester encoded data

Txd

SFD DATA

Preamble Length is set to 8

The receiver samples the RX line in continuos bit period quarters, making the smallest time frame in which to assume a bit value three quarters. A start bit is assumed if RXD is zero during

one of these quarters. See Figure 21-14

.

Figure 21-14. Asynchronous Start Bit Detection

Sampling

Clock

(16 x)

Manchester encoded data

Txd

Start

Detection

1 2 3 4

If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. If the stream does not match a valid preamble pattern or a start frame delimiter, the receiver re-synchronizes at the next valid edge. When a valid start sequence has been detected, the decoded data is passed to the USART and the user will be notified of any incoming Manchester encoding violations by the Manchester Error bit (CSR.MANE). This bit is cleared by writing a one to the Reset Status bits in the Control Register (CR.RSTSTA). A violation occurs when there is no transition in the middle of a bit period. See

Figure 21-15 for an

illustration of a violation causing the Manchester Error bit to be set.

Figure 21-15. Manchester Error

Preamble Length is set to 4

Elementary character bit time

SFD

Manchester encoded data

Txd

Entering USART character area sampling points

21.6.4.5

Preamble subpacket and Start Frame Delimiter were successfully decoded

Manchester

Coding Error detected

Radio Interface: Manchester Endec Application

This section describes low data rate, full duplex, dual frequency, RF systems integrated with a

Manchester endec, that support ASK and/or FSK modulation schemes. See Figure 21-16

.

309

32059L–AVR32–01/2012

AT32UC3B

Figure 21-16. Manchester Encoded Characters RF Transmission

Fup frequency Carrier

Upstream

Emitter

Fdown frequency Carrier

Downstream

Receiver

ASK/FSK

Upstream Receiver

LNA

VCO

RF filter

Demod control bi-dir line

ASK/FSK downstream transmitter

PA

RF filter

Mod

VCO

Serial

Configuration

Interface

Manchester decoder

Manchester encoder

USART

Receiver

USART

Emitter control

To transmit downstream, encoded data is sent serially to the RF modulator and then through space to the RF receiver. To receive, another frequency carrier is used and the RF demodulator does a bit-checking search for valid patterns before it switches to a receiving mode and forwards data to the decoder. Defining preambles to help distinguish between noise and valid data has to be done in conjunction with the RF module, and may sometimes be filtered away from the endec stream. Using the ASK modulation scheme, a one is transmitted as a RF signal at the downstream frequency, while a zero is transmitted as no signal. See

Figure 21-17 The FSK

modulation scheme uses two different frequencies to transmit data. A one is sent as a signal on

one frequency, and a zero on the other. See Figure 21-18 .

Figure 21-17. ASK Modulator Output

1

NRZ stream

Manchester encoded data default polarity unipolar output

ASK Modulator

Output

Uptstream Frequency F0

Txd

0 0 1

310

32059L–AVR32–01/2012

AT32UC3B

Figure 21-18. FSK Modulator Output

1

NRZ stream

Manchester encoded data default polarity unipolar output

FSK Modulator

Output

Uptstream Frequencies

[F0, F0+offset]

Txd

0 0 1

21.6.4.6

Synchronous Receiver

In synchronous mode (SYNC=1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start bit. Configuration bits and fields are the same as in asynchronous mode.

Figure 21-19. Synchronous Mode Character Reception

Example: 8-bit, Parity Enabled 1 Stop

Baud Rate

Clock

21.6.4.7

RXD

Sampling

Start D0 D1 D2 D3 D4 D5 D6 D7

Parity Bit

Stop Bit

Receiver Operations

When a character reception is completed, it is transferred to the Received Character field in the

Receive Holding Register (RHR.RXCHR), and the Receiver Ready bit in the Channel Status

Register (CSR.RXRDY) is set. If RXRDY is already set, RHR will be overwritten and the Overrun

Error bit (CSR.OVRE) is set. Reading RHR will clear CSR.RXRDY, and writing a one to the

Reset Status bit in the Control Register (CR.RSTSTA) will clear CSR.OVRE.

311

32059L–AVR32–01/2012

AT32UC3B

Figure 21-20. Receiver Status

Baud Rate

Clock

RXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

RSTSTA = 1

Write

CR

Read

RHR

21.6.4.8

RXRDY

OVRE

Parity

The USART supports five parity modes selected by MR.PAR. The PAR field also enables the

Multidrop mode, see ”Multidrop Mode” on page 313 . If even parity is selected, the parity bit will

be a zero if there is an even number of ones in the data character, and if there is an odd number it will be a one. For odd parity the reverse applies. If space or mark parity is chosen, the parity bit

will always be a zero or one, respectively. See Table 21-7

.

Table 21-7.

Parity Bit Examples

Alphanum

Character

A

V

R

Hex

0x41

0x56

0x52

Bin

0100 0001

0101 0110

0101 0010

Odd

1

1

0

Even

Parity Mode

Mark

0

0

1

1

1

1

Space

0

0

0

None

-

-

-

The receiver will report parity errors in CSR.PARE, unless parity is disabled. Writing a one to

CR.RSTSTA will clear CSR.PARE. See Figure 21-21

.

Figure 21-21. Parity Error

Baud Rate

Clock

RXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Bad

Parity

Stop

Bit

Bit

RSTSTA = 1

Write

CR

PARE

RXRDY

312

32059L–AVR32–01/2012

AT32UC3B

21.6.4.9

21.6.4.10

Multidrop Mode

If PAR is either 0x6 or 0x7, the USART runs in Multidrop mode. This mode differentiates data and address characters. Data has the parity bit zero and addresses have a one. By writing a one to the Send Address bit (CR.SENDA) the user will cause the next character written to THR to be transmitted as an address. Receiving a character with a one as parity bit will set CSR.PARE.

Transmitter Timeguard

The timeguard feature enables the USART to interface slow devices by inserting an idle state on the TXD line in between two characters. This idle state corresponds to a long stop bit, whose duration is selected by the Timeguard Value field in the Transmitter Timeguard Register

(TTGR.TG). The transmitter will hold the TXD line high for TG bit periods, in addition to the number of stop bits. As illustrated in

Figure 21-22

, the behavior of TXRDY and TXEMPTY is modified when TG has a non-zero value. If a pending character has been written to THR, the TXRDY bit will not be set until this characters start bit has been sent. TXEMPTY will remain low until the timeguard transmission has completed.

Figure 21-22. Timeguard Operation

TG = 4

TG = 4

Baud Rate

Clock

TXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

Write

THR

TXRDY

TXEMPTY

Table 21-8.

Maximum Baud Rate Dependent Timeguard Durations

Baud Rate (bit/sec) Bit time (µs)

1 200

9 600

833

104

14400 69.4

19200 52.1

28800

33400

56000

57600

115200

34.7

29.9

17.9

17.4

8.7

Timeguard (ms)

212.50

26.56

17.71

13.28

8.85

7.63

4.55

4.43

2.21

313

32059L–AVR32–01/2012

AT32UC3B

21.6.4.11

Receiver Time-out

The Time-out Value field in the Receiver Time-out Register (RTOR.TO) enables handling of variable-length frames by detection of selectable idle durations on the RXD line. The value written to

TO is loaded to a decremental counter, and unless it is zero, a time-out will occur when the amount of inactive bit periods match the initial counter value. If a time-out has not occurred, the counter will reload and restart every time a new character arrives. A time-out sets the TIMEOUT bit in CSR. Clearing TIMEOUT can be done in two ways:

• Writing a one to the Start Time-out bit (CR.STTTO). This also aborts count down until the next character has been received.

• Writing a one to the Reload and Start Time-out bit (CR.RETTO). This also reloads the counter and restarts count down immediately.

Figure 21-23. Receiver Time-out Block Diagram

Baud Rate

Clock

TO

16-bit

Value

STTTO

1

D Q

Clock 16-bit Time-out

Counter

= TIMEOUT

Load 0

Clear

Character

Received

RETTO

Table 21-9.

Maximum Time-out Period

Baud Rate (bit/sec)

600

Bit Time (µs)

1 667

1 200

2 400

4 800

9 600

14400

19200

28800

33400

56000

57600

200000

833

417

208

104

69

52

35

30

18

17

5

Time-out (ms)

109 225

54 613

27 306

13 653

6 827

4 551

3 413

2 276

1 962

1 170

1 138

328

314

32059L–AVR32–01/2012

AT32UC3B

21.6.4.12

Framing Error

The receiver is capable of detecting framing errors. A framing error has occurred if a stop bit reads as zero. This can occur if the transmitter and receiver are not synchronized. A framing error is reported by CSR.FRAME as soon as the error is detected, at the middle of the stop bit.

Figure 21-24. Framing Error Status

Baud Rate

Clock

RXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

RSTSTA = 1

Write

CR

FRAME

RXRDY

21.6.4.13

Transmit Break

When CSR.TXRDY is set, the user can request the transmitter to generate a break condition on the TXD line by writing a one to The Start Break bit (CR.STTBRK). The break is treated as a normal 0x00 character transmission, clearing CSR.TXRDY and CSR.TXEMPTY, but with zeroes for preambles, start, parity, stop, and time guard bits. Writing a one to the Stop Break bit

(CR.STBRK) will stop the generation of new break characters, and send ones for TG duration or at least 12 bit periods, ensuring that the receiver detects end of break, before resuming normal

operation. Figure 21-25

illustrates STTBRK and STPBRK effect on the TXD line.

Writing to CR.STTBRK and CR.STPBRK simultaneously can lead to unpredictable results.

Writes to THR before a pending break has started will be ignored.

Figure 21-25. Break Transmission

Baud Rate

Clock

TXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

STTBRK = 1

Break Transmission

STPBRK = 1

End of Break

Write

CR

TXRDY

TXEMPTY

21.6.4.14

Receive Break

A break condition is assumed when incoming data, parity, and stop bits are zero. This corresponds to a framing error, but FRAME will remain zero while the Break Received/End Of Break

315

32059L–AVR32–01/2012

AT32UC3B

bit (CSR.RXBRK) is set. Writing a one to CR.RSTSTA will clear CSR.RXBRK. An end of break will also set CSR.RXBRK, and is assumed when TX is high for at least 2/16 of a bit period in asynchronous mode, or when a high level is sampled in synchronous mode.

21.6.4.15

Hardware Handshaking

The USART features an out-of-band hardware handshaking flow control mechanism, imple-

mentable by connecting the RTS and CTS pins with the remote device, as shown in Figure 21-

26

.

Figure 21-26. Connection with a Remote Device for Hardware Handshaking

USART

TXD

RXD

CTS

RTS

Remote

Device

RXD

TXD

RTS

CTS

Writing 0x2 to the MR.MODE field configures the USART to operate in this mode. The receiver will drive its RTS pin high when disabled or when the Reception Buffer Full bit (CSR.RXBUFF) is set by the Buffer Full signal from the Peripheral DMA controller. If the receivers RTS pin is high, the transmitters CTS pin will also be high and only the active character transactions will be completed. Allocating a new buffer to the DMA controller by clearing RXBUFF, will drive the RTS pin low, allowing the transmitter to resume transmission. Detected level changes on the CTS pin can trigger interrupts, and are reported by the CTS Input Change bit in the Channel Status Register (CSR.CTSIC).

Figure 21-27

illustrates receiver functionality, and

Figure 21-28

illustrates transmitter functionality.

Figure 21-27. Receiver Behavior when Operating with Hardware Handshaking

RXD

Write

CR

RXEN = 1

RXDIS = 1

RTS

RXBUFF

Figure 21-28. Transmitter Behavior when Operating with Hardware Handshaking

CTS

TXD

316

32059L–AVR32–01/2012

AT32UC3B

21.6.5

21.6.5.1

ISO7816 Mode

The USART features an ISO7816-compatible mode, enabling interfacing with smart cards and

Security Access Modules (SAM) through an ISO7816 compliant link. T=0 and T=1 protocols, as defined in the ISO7816 standard, are supported by writing 0x4 and 0x6 respectively to

MR.MODE.

ISO7816 Mode Overview

ISO7816 specifies half duplex communication on one bidirectional line. The baud rate is a fraction of the clock provided by the master on the CLK pin (see

”Baud Rate Generator” on page

300 ). The USART connects to a smart card as shown in

Figure 21-29

. The TXD pin is bidirectional and is routed to the receiver when the transmitter is disabled. Having both receiver and transmitter enabled simultaneously may lead to unpredictable results.

Figure 21-29. USART (master) Connected to a Smart Card

USART

CLK

CLK

I/O

TXD

Smart

Card

21.6.5.2

In both T=0 and T=1 modes, the character format is fixed to eight data bits, and one or two stop bits, regardless of CHRL, MODE9, and CHMODE values. Parity according to specification is even. If the inverse transmission format is used, where payload data bits are transmitted inverted on the I/O line, the user can use odd parity and perform an XOR on data headed to

THR and coming from RHR.

Protocol T=0

In T=0 protocol, a character is made up of one start bit, eight data bits, one parity bit, and a two bit period guard time. During the guard time, the line will be high if the receiver does not signal a

parity error, as shown in Figure 21-30

. The receiver signals a parity error, aka non-acknowledge

(NACK), by pulling the line low for a bit period within the guard time, resulting in the total character length being incremented by one, see

Figure 21-31

. The USART will not load data to RHR if it detects a parity error, and will set PARE if it receives a NACK.

Figure 21-30. T=0 Protocol without Parity Error

Baud Rate

Clock

RXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity

Bit

Guard

Time 1

Guard

Time 2

Next

Start

Bit

317

32059L–AVR32–01/2012

AT32UC3B

Figure 21-31. T=0 Protocol with Parity Error

Baud Rate

Clock

I/O

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Error

Parity

Bit

Guard

Time 1

Guard

Time 2

Start

Bit

D0

Repetition

D1

21.6.5.3

21.6.5.4

Protocol T=1

In T=1 protocol, the character resembles an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity errors set PARE.

Receive Error Counter

The USART receiver keeps count of up to 255 errors in the Number Of Errors field in the Number of Error Register (NER.NB_ERRORS). Reading NER automatically clears NB_ERRORS.

21.6.5.5

21.6.5.6

Receive NACK Inhibit

The USART can be configured to ignore parity errors by writing a one to the Inhibit Non

Acknowledge bit (MR.INACK). Erroneous characters will be treated as if they were ok, not generating a NACK, loaded to RHR, and raising RXRDY.

Transmit Character Repetition

The USART can be configured to automatically re-send a character if it receives a NACK. Writing a value other than zero to MR.MAX_ITERATION will enable and determine the number of consecutive re-transmissions. If the number of unsuccessful re-transmissions equal

MAX_ITERATION, the iteration bit (CSR.ITER) is set. Writing a one to the Reset Iteration bit

(CR.RSTIT) will clear ITER.

21.6.5.7

21.6.6

Disable Successive Receive NACK

The receiver can limit the number of consecutive NACK’s to the value in MAX_ITERATION. This is enabled by writing a one to the Disable Successive NACK bit (MR.DSNACK). If the number of

NACK’s is about to surpass MAX_ITERATION, the character will instead be accepted as valid and ITER is set.

IrDA Mode

The USART features an IrDA mode, supporting asynchronous, half-duplex, point-to-point wireless communication. It embeds the modulator and demodulator, allowing for a glueless

connection to the infrared transceivers, as shown in Figure 21-32 . Writing 0x8 to MR.MODE

enables this mode, and activates the IrDA specification v1.1 compliant modem. Data transfer speeds ranging from 2.4Kbit/s to 115.2Kbit/s are supported and the character format is fixed to one start bit, eight data bits, and one stop bit.

318

32059L–AVR32–01/2012

AT32UC3B

Figure 21-32. Connection to IrDA Transceivers

Receiver

USART

Demodulator

RXD

Transmitter

Modulator

TXD

RX

IrDA

Transceivers

TX

21.6.6.1

The receiver and the transmitter must be exclusively enabled or disabled, according to the direction of the transmission. To receive IrDA signals, the following needs to be done:

• Disable TX and enable RX.

• Configure the TXD pin as an I/O, outputting zero to avoid LED activation. Disable the internal pull-up for improved power consumption.

• Receive data.

IrDA Modulation

The RZI modulation scheme is used, where a zero is represented by a light pulse one 3/16 th

of a bit period, and no pulse to represent a one. Some examples of signal pulse duration are shown in

Table 21-10 .

Table 21-10. IrDA Pulse Duration

Baud Rate

2.4 Kbit/s

9.6 Kbit/s

19.2 Kbit/s

38.4 Kbit/s

57.6 Kbit/s

115.2 Kbit/s

Pulse Duration (3/16)

78.13 µs

19.53 µs

9.77 µs

4.88 µs

3.26 µs

1.63 µs

Figure 21-33

shows an example of character transmission.

319

32059L–AVR32–01/2012

AT32UC3B

Figure 21-33. IrDA Modulation

Transmitter

Output

Start

Bit

0 1 0

1

Data Bits

0

0

1 1 0

Stop

Bit

1

TXD

21.6.6.2

Bit Period

3

16

Bit Period

IrDA Baud Rate

As the IrDA mode shares some logic with the ISO7816 mode, the FIDI.FI_DI_RATIO field needs

to be configured correctly. See Section “21.6.2.5” on page 302.

Table 21-11 gives some exam-

ples of BRGR.CD values, baud rate error, and pulse duration. Note that the maximal acceptable error rate of ±1.87% must be met.

Table 21-11. IrDA Baud Rate Error

Peripheral Clock Baud Rate

3 686 400

20 000 000

32 768 000

40 000 000

3 686 400

20 000 000

32 768 000

40 000 000

3 686 400

20 000 000

32 768 000

40 000 000

3 686 400

20 000 000

32 768 000

40 000 000

3 686 400

20 000 000

32 768 000

40 000 000

38 400

38 400

38 400

38 400

19 200

19 200

19 200

19 200

115 200

115 200

115 200

115 200

57 600

57 600

57 600

57 600

9 600

9 600

9 600

9 600

53

65

12

65

36

43

6

33

18

22

4

22

CD

2

11

107

130

24

130

213

260

Baud Rate Error

0.00%

1.38%

1.25%

1.38%

0.00%

1.38%

1.25%

0.93%

0.00%

1.38%

0.63%

0.16%

0.00%

0.16%

0.31%

0.16%

0.00%

0.16%

0.16%

0.16%

4.88

4.88

9.77

9.77

3.26

3.26

4.88

4.88

Pulse Time

1.63

1.63

1.63

1.63

3.26

3.26

9.77

9.77

19.53

19.53

19.53

19.53

320

32059L–AVR32–01/2012

AT32UC3B

Table 21-11. IrDA Baud Rate Error (Continued)

Peripheral Clock

3 686 400

20 000 000

32 768 000

Baud Rate

2 400

2 400

2 400

CD

96

521

853

Baud Rate Error

0.00%

0.03%

0.04%

Pulse Time

78.13

78.13

78.13

21.6.6.3

IrDA Demodulator

The demodulator depends on an 8-bit down counter loaded with the value in IRDA_Filter field in the IrDA Filter Register (IFR.IRDA_FILTER). When a falling edge on RXD is detected, the counter starts decrementing at CLK_USART speed. If a rising edge is detected on RXD, the counter stops and is reloaded with the IFR value. If no rising edge has been detected when the counter reaches zero, the receiver input is pulled low during one bit period. See

Figure 21-34 . Writing a

one to the Infrared Receive Line Filter bit (MR.FILTER), enables a noise filter that, instead of using just one sample, will choose the majority value from three consecutive samples.

Figure 21-34. IrDA Demodulator Operations

CLK_USART

RXD

Counter

Value

6 5 4 3 2

Pulse

Rejected

6 6 5 4 3 2 1 0

Pulse

Accepted

21.6.7

Receiver

Input

Driven Low During 16 Baud Rate Clock Cycles

RS485 Mode

The USART features an RS485 mode, supporting line driver control. This supplements normal synchronous and asynchronous mode by driving the RTS pin high when the transmitter is operating. The RTS pin level is the inverse of the CSR.TXEMPTY value. Writing 0x1 to MR.MODE

enables this mode. A typical connection to a RS485 bus is shown in

Figure 21-35 .

Figure 21-35. Typical Connection to a RS485 Bus

USART

RXD

TXD

RTS

Differential

Bus

If a timeguard has been configured the RTS pin will remain high for the duration specified in TG, as shown in

Figure 21-36 .

321

32059L–AVR32–01/2012

AT32UC3B

Figure 21-36. Example of RTS Drive with Timeguard Enabled

Baud Rate

Clock

TXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

Write

THR

TXRDY

TXEMPTY

RTS

TG = 4

21.6.8

Modem Mode

The USART features a modem mode, supporting asynchronous communication with the following signal pins: Data Terminal Ready (DTR), Data Set Ready (DSR), Request to Send (RTS),

Clear to Send (CTS), Data Carrier Detect (DCD), and Ring Indicator (RI). Writing 0x3 to

MR.MODE enables this mode, and the USART will behave as a Data Terminal Equipment

(DTE), controlling DTR and RTS, whilst detecting level changes on DSR, DCD, CTS, and RI.

Table 21-12

shows USART signal pins with the corresponding standardized modem connections.

Table 21-12. Circuit References

USART Pin V.24

TXD

RTS

DTR

RXD

CTS

DSR

DCD

RI

5

6

8

22

2

4

20

3

CCITT

103

105

108.2

104

106

107

109

125

Direction

From terminal to modem

From terminal to modem

From terminal to modem

From modem to terminal

From terminal to modem

From terminal to modem

From terminal to modem

From terminal to modem

The DTR pin is controlled by writing a one to the DTR enable and disable bits (DTREN,

DTRDIS) in CR. It is low when enabled, and high when disabled. The RTS pin is controlled automatically.

Detected level changes can trigger interrupts, and are reported by the respective Input Change bits (RIIC, DSRIC, DCDIC, and CTSIC) in CSR. These status bit are automatically cleared when

CSR is read. When the CTS pin goes high, the USART will wait for the transmitter to complete any ongoing character transmission before automatically disabling it.

322

32059L–AVR32–01/2012

AT32UC3B

21.6.9

21.6.9.1

SPI Mode

The USART features a Serial Peripheral Interface (SPI) link compliant mode, supporting synchronous, full-duplex communication, in both master and slave mode. Writing 0xE (master) or

0xF (slave) to MR.MODE will enable this mode. A SPI in master mode controls the data flow to and from the other SPI devices, who are in slave mode. It is possible to let devices take turns being masters (aka multi-master protocol), and one master may shift data simultaneously into several slaves, but only one slave may respond at a time. A slave is selected when its slave select (NSS) signal has been raised by the master. The USART can only generate one NSS signal, and it is possible to use standard I/O lines to address more than one slave.

Modes of Operation

The SPI system consists of two data lines and two control lines:

• Master Out Slave In (MOSI): This line supplies the data shifted from master to slave. In master mode this is connected to TXD, and in slave mode to RXD.

• Master In Slave Out (MISO): This line supplies the data shifted from slave to master. In master mode this is connected to RXD, and in slave mode to TXD.

• Serial Clock (CLK): This is controlled by the master. One period per bit transmission. In both modes this is connected to CLK.

• Slave Select (NSS): This control line allows the master to select or deselect a slave. In master mode this is connected to RTS, and in slave mode to CTS.

Changing SPI mode after initial configuration has to be followed by a transceiver software reset in order to avoid unpredictable behavior.

21.6.9.2

Baud Rate

The baud rate generator operates as described in

”Baud Rate in Synchronous and SPI Mode” on page 302 , with the following requirements:

In SPI Master Mode:

• The Clock Selection field (MR.USCLKS) must not equal 0x3 (external clock, CLK).

• The Clock Output Select bit (MR.CLKO) must be one.

• The BRGR.CD field must be at least 0x4.

• If USCLKS is one (internal divided clock, CLK_USART/DIV), the value in CD has to be even, ensuring a 50:50 duty cycle. CD can be odd if USCLKS is zero (internal clock, CLK_USART).

In SPI Slave Mode:

• CLK frequency must be at least four times lower than the system clock.

21.6.9.3

Data Transfer

Up to nine data bits are successively shifted out on the TXD pin at each edge. There are no start, parity, or stop bits, and MSB is always sent first. The SPI Clock Polarity (MR.CPOL), and

SPI Clock Phase (MR.CPHA) bits configure CLK by selecting the edges upon which bits are shifted and sampled, resulting in four non-interoperable protocol modes, see

Table 21-13 . If

MR.CPOL is zero, the inactive state value of CLK is logic level zero, and if MR.CPOL is one, the inactive state value of CLK is logic level one. If MR.CPHA is zero, data is changed on the leading edge of CLK, and captured on the following edge of CLK. If MR.CPHA is one, data is captured on the leading edge of CLK, and changed on the following edge of CLK. A master/slave pair must use the same configuration, and the master must be reconfigured if it is to

communicate with slaves using different configurations. See Figures 21-37 and 21-38

.

323

32059L–AVR32–01/2012

AT32UC3B

Table 21-13. SPI Bus Protocol Modes

SPI Bus Protocol Mode

0

1

2

3

Figure 21-37. SPI Transfer Format (CPHA=1, 8 bits per transfer)

CLK cycle (for reference)

1

2

3

4

CLK

(CPOL= 0)

CLK

(CPOL= 1)

MOSI

SPI Master ->TXD

SPI Slave ->RXD

MISO

SPI Master ->RXD

SPI Slave ->TXD

NSS

SPI Master ->RTS

SPI Slave ->CTS

MSB

MSB

6

6

5

5

4

4

Figure 21-38. SPI Transfer Format (CPHA=0, 8 bits per transfer)

CLK cycle (for reference)

1 2 3 4

CLK

(CPOL= 0)

5

3

3

5

CPOL

0

0

1

1

6

2

2

6

7

1

1

7

8

LSB

LSB

8

CPHA

1

0

1

0

CLK

(CPOL= 1)

MOSI

SPI Master -> TXD

SPI Slave -> RXD

MISO

SPI Master -> RXD

SPI Slave -> TXD

NSS

SPI Master -> RTS

SPI Slave -> CTS

MSB 6

MSB 6

5

5

4

4

3

3

2

2

1

1

LSB

LSB

324

32059L–AVR32–01/2012

AT32UC3B

21.6.9.4

Receiver and Transmitter Control

See ”Transmitter Operations” on page 304

, and

”Receiver Operations” on page 311 .

21.6.9.5

21.6.9.6

Character Transmission and Reception

In SPI master mode, the slave select line (NSS) is asserted low one bit period before the start of transmission, and released high one bit period after every character transmission. A delay for at least three bit periods is always inserted in between characters. In order to address slave devices supporting the Chip Select Active After Transfer (CSAAT) mode, NSS can be forced low by writing a one to the Force SPI Chip Select bit (CR.RTSEN/FCS). Releasing NSS when FCS is one, is only possible by writing a one to the Release SPI Chip Select bit (CR.RTSDIS/RCS).

In SPI slave mode, a low level on NSS for at least one bit period will allow the slave to initiate a transmission or reception. The Underrun Error bit (CSR.UNRE) is set if a character must be sent while THR is empty, and TXD will be high during character transmission, as if 0xFF was being sent. If a new character is written to THR it will be sent correctly during the next transmission slot. Writing a one to CR.RSTSTA will clear CSR.UNRE. To ensure correct behavior of the receiver in SPI slave mode, the master device sending the frame must ensure a minimum delay of one bit period in between each character transmission.

Receiver Time-out

Receiver Time-out’s are not possible in SPI mode as the baud rate clock is only active during data transfers.

21.6.10

21.6.11

Test Modes

21.6.11.1

The internal loopback feature enables on-board diagnostics, and allows the USART to operate in three different test modes, with reconfigured pin functionality, as shown below.

Normal Mode

During normal operation, a receivers RXD pin is connected to a transmitters TXD pin.

Figure 21-39. Normal Mode Configuration

RXD

Receiver

TXD

Transmitter

21.6.11.2

Automatic Echo Mode

Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it

is also sent to the TXD pin, as shown in Figure 21-40

. Transmitter configuration has no effect.

325

32059L–AVR32–01/2012

AT32UC3B

Figure 21-40. Automatic Echo Mode Configuration

Receiver

RXD

TXD

Transmitter

21.6.11.3

Local Loopback Mode

Local loopback mode connects the output of the transmitter directly to the input of the receiver,

as shown in Figure 21-41 . The TXD and RXD pins are not used. The RXD pin has no effect on

the receiver and the TXD pin is continuously driven high, as in idle state.

Figure 21-41. Local Loopback Mode Configuration

RXD

Receiver

TXD

Transmitter

1

21.6.11.4

Remote Loopback Mode

Remote loopback mode connects the RXD pin to the TXD pin, as shown in

Figure 21-42 . The

transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission.

Figure 21-42. Remote Loopback Mode Configuration

RXD

Receiver

1

TXD

Transmitter

326

32059L–AVR32–01/2012

AT32UC3B

21.7 User Interface

Table 21-14. USART Register Memory Map

0x001C

0x0020

0x0024

0x0028

0x0040

0x0044

0x004C

0x0050

0x00FC

Offset

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

Register

Control Register

Mode Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Channel Status Register

Receiver Holding Register

Name

CR

MR

IER

IDR

IMR

CSR

RHR

Access Reset

Write-only 0x00000000

Read-write

Write-only

0x00000000

0x00000000

Write-only

Read-only

Read-only

Read-only

0x00000000

0x00000000

0x00000000

0x00000000

Transmitter Holding Register

Baud Rate Generator Register

Receiver Time-out Register

Transmitter Timeguard Register

THR

BRGR

RTOR

TTGR

Write-only

Read-write

Read-write

Read-write

0x00000000

0x00000000

0x00000000

0x00000000

FI DI Ratio Register

Number of Errors Register

FIDI

NER

Read-write

Read-only

0x00000174

0x00000000

IrDA Filter Register IFR Read-write 0x00000000

Manchester Configuration Register MAN Read-write 0x30011004

Version Register VERSION Read-only

0x–

Note: 1. Values in the Version Register vary with the version of the IP block implementation.

(1)

327

32059L–AVR32–01/2012

AT32UC3B

21.7.1

Name:

Control Register

CR

Access Type:

Offset:

Reset Value:

Write-only

0x0

0x00000000

31

23

15

RETTO

30

22

14

RSTNACK

29

21

13

RSTIT

28

20

12

SENDA

27

26

19 18

RTSDIS/RCS RTSEN/FCS

11

STTTO

10

STPBRK

25

17

DTRDIS

9

STTBRK

24

16

DTREN

8

RSTSTA

7

TXDIS

6

TXEN

5

RXDIS

4

RXEN

3

RSTTX

2

RSTRX

1

0

• RTSDIS/RCS: Request to Send Disable/Release SPI Chip Select

Writing a zero to this bit has no effect.

Writing a one to this bit when USART is not in SPI master mode drives RTS pin high.

Writing a one to this bit when USART is in SPI master mode releases NSS (RTS pin).

• RTSEN/FCS: Request to Send Enable/Force SPI Chip Select

Writing a zero to this bit has no effect.

Writing a one to this bit when USART is not in SPI master mode drives RTS low.

Writing a one to this bit when USART is in SPI master mode when;

FCS=0: has no effect.

FCS=1: forces NSS (RTS pin) low, even if USART is not transmitting, in order to address SPI slave devices supporting the

CSAAT Mode (Chip Select Active After Transfer).

• DTRDIS: Data Terminal Ready Disable

Writing a zero to this bit has no effect.

Writing a one to this bit drives DTR pin high.

• DTREN: Data Terminal Ready Enable

Writing a zero to this bit has no effect.

Writing a one to this bit drives DTR pin low.

• RETTO: Rearm Time-out

Writing a zero to this bit has no effect.

Writing a one to this bit reloads the time-out counter and clears CSR.TIMEOUT.

• RSTNACK: Reset Non Acknowledge

Writing a zero to this bit has no effect.

Writing a one to this bit clears CSR.NACK.

• RSTIT: Reset Iterations

Writing a zero to this bit has no effect.

Writing a one to this bit clears CSR.ITER if ISO7816 is enabled in MR.MODE

• SENDA: Send Address

Writing a zero to this bit has no effect.

Writing a one to this bit will in multidrop mode send the next character written to THR as an address.

328

32059L–AVR32–01/2012

AT32UC3B

• STTTO: Start Time-out

Writing a zero to this bit has no effect.

Writing a one to this bit will abort any current time-out count down, and trigger a new count down when the next character has been received. CSR.TIMEOUT is also cleared.

• STPBRK: Stop Break

Writing a zero to this bit has no effect.

Writing a one to this bit will stop the generation of break signal characters, and then send ones for TTGR.TG duration, or at least

12 bit periods. No effect if no break is being transmitted.

• STTBRK: Start Break

Writing a zero to this bit has no effect.

Writing a one to this bit will start transmission of break characters when current characters present in THR and the transmit shift register have been sent. No effect if a break signal is already being generated. CSR.TXRDY and CSR.TXEMPTY will be cleared.

• RSTSTA: Reset Status Bits

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the following bits in CSR: PARE, FRAME, OVRE, MANERR, UNRE, and RXBRK.

TXDIS: Transmitter Disable

Writing a zero to this bit has no effect.

Writing a one to this bit disables the transmitter.

TXEN: Transmitter Enable

Writing a zero to this bit has no effect.

Writing a one to this bit enables the transmitter if TXDIS is zero.

RXDIS: Receiver Disable

Writing a zero to this bit has no effect.

Writing a one to this bit disables the receiver.

RXEN: Receiver Enable

Writing a zero to this bit has no effect.

Writing a one to this bit enables the receiver if RXDIS is zero.

RSTTX: Reset Transmitter

Writing a zero to this bit has no effect.

Writing a one to this bit will reset the transmitter.

RSTRX: Reset Receiver

Writing a zero to this bit has no effect.

Writing a one to this bit will reset the receiver.

329

32059L–AVR32–01/2012

AT32UC3B

21.7.2

Name:

Mode Register

MR

Access Type:

Offset:

Reset Value:

Read-write

0x4

0x00000000

31

ONEBIT

23

15

7

30

MODSYNC

22

VAR_SYNC

CHMODE

14

6

29

MAN

21

DSNACK

13

5

NBSTOP

28

FILTER

20

INACK

12

4

27

19

OVER

11

3

26

18

CLKO

10

PAR

2

MODE

25

MAX_ITERATION

17

MODE9

9

1

24

16

MSBF/CPOL

8

SYNC/CPHA

0

CHRL USCLKS

• ONEBIT: Start Frame Delimiter Selector

0: The start frame delimiter is a command or data sync, as defined by MODSYNC.

1: The start frame delimiter is a normal start bit, as defined by MODSYNC.

• MODSYNC: Manchester Synchronization Mode

0: The manchester start bit is either a 0-to-1 transition, or a data sync.

1: The manchester start bit is either a 1-to-0 transition, or a command sync.

• MAN: Manchester Encoder/Decoder Enable

0: Manchester endec is disabled.

1: Manchester endec is enabled.

• FILTER: Infrared Receive Line Filter

0: The USART does not filter the receive line.

1: The USART filters the receive line by doing three consecutive samples and uses the majority value.

• MAX_ITERATION

This field determines the number of acceptable consecutive NACK’s when in protocol T=0.

• VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter

0: Sync pattern according to MODSYNC.

1: Sync pattern according to THR.TXSYNH.

• DSNACK: Disable Successive NACK

0: NACK’s are handled as normal, unless disabled by INACK.

1: The receiver restricts the amount of consecutive NACK’s by MAX_ITERATION value. If MAX_ITERATION=0 no NACK will be issued and the first erroneous message is accepted as a valid character, setting CSR.ITER.

• INACK: Inhibit Non Acknowledge

0: The NACK is generated.

1: The NACK is not generated.

• OVER: Oversampling Mode

0: Oversampling at 16 times the baud rate.

1: Oversampling at 8 times the baud rate.

• CLKO: Clock Output Select

0: The USART does not drive the CLK pin.

1: The USART drives the CLK pin unless USCLKS selects the external clock.

• MODE9: 9-bit Character Length

0: CHRL defines character length.

330

32059L–AVR32–01/2012

AT32UC3B

1: 9-bit character length.

• MSBF/CPOL: Bit Order or SPI Clock Polarity

If USART does not operate in SPI Mode:

MSBF=0: Least Significant Bit is sent/received first.

MSBF=1: Most Significant Bit is sent/received first.

If USART operates in SPI Mode, CPOL is used with CPHA to produce the required clock/data relationship between devices.

CPOL=0: The inactive state value of CLK is logic level zero.

CPOL=1: The inactive state value of CLK is logic level one.

• CHMODE: Channel Mode

Table 21-15.

CHMODE

1

1

0

0

0

1

0

1

Mode Description

Normal Mode

Automatic Echo. Receiver input is connected to the TXD pin.

Local Loopback. Transmitter output is connected to the Receiver input.

Remote Loopback. RXD pin is internally connected to the TXD pin.

• NBSTOP: Number of Stop Bits

Table 21-16.

NBSTOP

1

1

0

0

0

1

0

1

Asynchronous (SYNC=0)

1 stop bit

1.5 stop bits

2 stop bits

Reserved

Synchronous (SYNC=1)

1 stop bit

Reserved

2 stop bits

Reserved

• PAR: Parity Type

Table 21-17.

0

1

1

0

0

0

1

0

1

PAR

0

0

1

1 x x

0

1

0

Parity Type

Even parity

Odd parity

Parity forced to 0 (Space)

Parity forced to 1 (Mark)

No parity

Multidrop mode

• SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase

If USART does not operate in SPI Mode (MODE is

… 0xE and 0xF):

SYNC = 0: USART operates in Asynchronous Mode.

SYNC = 1: USART operates in Synchronous Mode.

If USART operates in SPI Mode, CPHA determines which edge of CLK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between master and slave devices.

CPHA = 0: Data is changed on the leading edge of CLK and captured on the following edge of CLK.

CPHA = 1: Data is captured on the leading edge of CLK and changed on the following edge of CLK.

331

32059L–AVR32–01/2012

AT32UC3B

1

1

0

0

1

0

0

0

0

• CHRL: Character Length.

Table 21-18.

CHRL

1

1

0

0

0

1

0

1

Character Length

5 bits

6 bits

7 bits

8 bits

• USCLKS: Clock Selection

Table 21-19.

USCLKS

1

1

0

0

0

1

0

1

Selected Clock

CLK_USART

CLK_USART/DIV

(1)

Reserved

CLK

Note: 1. The value of DIV is device dependent. Please refer to the Module Configuration section at the end of this chapter.

• MODE

Table 21-20.

0

1

1

1

1

0

0

0

0

MODE

Others

0

1

0

1

1

1

1

0

0

0

0

0

0

1

0

1

0

1

Mode of the USART

Normal

RS485

Hardware Handshaking

Modem

IS07816 Protocol: T = 0

IS07816 Protocol: T = 1

IrDA

SPI Master

SPI Slave

Reserved

332

32059L–AVR32–01/2012

AT32UC3B

21.7.3

Name:

Interrupt Enable Register

IER

Access Type:

Offset:

Reset Value:

Write-only

0x8

0x00000000

31

23

15

30

22

14

29

21

13

NACK

28

20

MANE

12

RXBUFF

27

19

CTSIC

11

7

PARE

6

FRAME

5

OVRE

4

3

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will set the corresponding bit in IMR.

26

18

DCDIC

10

ITER/UNRE

2

RXBRK

25

17

DSRIC

9

TXEMPTY

1

TXRDY

24

MANEA

16

RIIC

8

TIMEOUT

0

RXRDY

For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Writing either one or the other has the same effect.

333

32059L–AVR32–01/2012

AT32UC3B

21.7.4

Name:

Interrupt Disable Register

IDR

Access Type:

Offset:

Reset Value:

Write-only

0xC

0x00000000

31

23

15

30

22

14

29

21

13

NACK

28

20

MANE

12

RXBUFF

27

19

CTSIC

11

7

PARE

6

FRAME

5

OVRE

4

3

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will clear the corresponding bit in IMR.

26

18

DCDIC

10

ITER/UNRE

2

RXBRK

25

17

DSRIC

9

TXEMPTY

1

TXRDY

24

MANEA

16

RIIC

8

TIMEOUT

0

RXRDY

For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Writing either one or the other has the same effect.

334

32059L–AVR32–01/2012

AT32UC3B

21.7.5

Name:

Interrupt Mask Register

IMR

Access Type:

Offset:

Reset Value:

Read-only

0x10

0x00000000

31

23

15

30

22

14

29

21

13

NACK

28

20

MANE

12

RXBUFF

27

19

CTSIC

11

26

18

DCDIC

10

ITER/UNRE

7

PARE

6

FRAME

5

OVRE

4

3

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

A bit in this register is cleared when the corresponding bit in IDR is written to one.

A bit in this register is set when the corresponding bit in IER is written to one.

2

RXBRK

25

17

DSRIC

9

TXEMPTY

1

TXRDY

24

MANEA

16

RIIC

8

TIMEOUT

0

RXRDY

For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Reading either one or the other has the same effect.

335

32059L–AVR32–01/2012

AT32UC3B

21.7.6

Name:

Channel Status Register

CSR

Access Type:

Offset:

Reset Value:

Read-only

0x14

0x00000000

31

23

CTS

15

7

PARE

30

22

DCD

14

6

FRAME

29

21

DSR

13

NACK

5

OVRE

28

20

RI

12

RXBUFF

4

27

19

CTSIC

11

3

26

18

DCDIC

10

ITER/UNRE

2

RXBRK

25

17

DSRIC

9

TXEMPTY

1

TXRDY

24

MANERR

16

RIIC

8

TIMEOUT

0

RXRDY

• MANERR: Manchester Error

0: No Manchester error has been detected since the last RSTSTA.

1: At least one Manchester error has been detected since the last RSTSTA.

• CTS: Image of CTS Input

0: CTS is low.

1: CTS is high.

• DCD: Image of DCD Input

0: DCD is low.

1: DCD is high.

• DSR: Image of DSR Input

0: DSR is low.

1: DSR is high.

• RI: Image of RI Input

0: RI is low.

1: RI is high.

• CTSIC: Clear to Send Input Change Flag

0: No change has been detected on the CTS pin since the last CSR read.

1: At least one change has been detected on the CTS pin since the last CSR read.

• DCDIC: Data Carrier Detect Input Change Flag

0: No change has been detected on the DCD pin since the last CSR read.

1: At least one change has been detected on the DCD pin since the last CSR read.

• DSRIC: Data Set Ready Input Change Flag

0: No change has been detected on the DSR pin since the last CSR read.

1: At least one change has been detected on the DSR pin since the last CSR read.

32059L–AVR32–01/2012

336

AT32UC3B

• RIIC: Ring Indicator Input Change Flag

0: No change has been detected on the RI pin since the last CSR read.

1: At least one change has been detected on the RI pin since the last CSR read.

• NACK: Non Acknowledge

0: No Non Acknowledge has been detected since the last RSTNACK.

1: At least one Non Acknowledge has been detected since the last RSTNACK.

This bit is cleared by writing a one to CR.RSTNACK.

• RXBUFF: Reception Buffer Full

0: The Buffer Full signal from the Peripheral DMA Controller channel is inactive.

1: The Buffer Full signal from the Peripheral DMA Controller channel is active.

• ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error

If USART does not operate in SPI Slave Mode:

ITER=0: Maximum number of repetitions has not been reached since the last RSTSTA.

ITER=1: Maximum number of repetitions has been reached since the last RSTSTA.

If USART operates in SPI Slave Mode:

UNRE=0: No SPI underrun error has occurred since the last RSTSTA.

UNRE=1: At least one SPI underrun error has occurred since the last RSTSTA.

This bit is cleared by writing a one to CR.RSTSTA.

• TXEMPTY: Transmitter Empty

0: The transmitter is either disabled or there are characters in THR, or in the transmit shift register.

1: There are no characters in neither THR, nor in the transmit shift register.

This bit is cleared by writing a one to CR.STTBRK.

• TIMEOUT: Receiver Time-out

0: There has not been a time-out since the last Start Time-out command (CR.STTTO), or RTOR.TO is zero.

1: There has been a time-out since the last Start Time-out command.

This bit is cleared by writing a one to CR.STTTO or CR.RETTO.

• PARE: Parity Error

0: Either no parity error has been detected, or the parity bit is a zero in multidrop mode, since the last RSTSTA.

1: Either at least one parity error has been detected, or the parity bit is a one in multidrop mode, since the last RSTSTA.

This bit is cleared by writing a one to CR.RSTSTA.

• FRAME: Framing Error

0: No stop bit has been found as low since the last RSTSTA.

1: At least one stop bit has been found as low since the last RSTSTA.

This bit is cleared by writing a one to CR.RSTSTA.

• OVRE: Overrun Error

0: No overrun error has occurred since the last RSTSTA.

1: At least one overrun error has occurred since the last RSTSTA.

This bit is cleared by writing a one to CR.RSTSTA.

• RXBRK: Break Received/End of Break

0: No Break received or End of Break detected since the last RSTSTA.

1: Break received or End of Break detected since the last RSTSTA.

This bit is cleared by writing a one to CR.RSTSTA.

• TXRDY: Transmitter Ready

0: The transmitter is either disabled, or a character in THR is waiting to be transferred to the transmit shift register, or an

STTBRK command has been requested. As soon as the transmitter is enabled, TXRDY is set.

1: There is no character in the THR.

This bit is cleared by writing a one to CR.STTBRK.

• RXRDY: Receiver Ready

0: The receiver is either disabled, or no complete character has been received since the last read of RHR. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.

1: At least one complete character has been received and RHR has not yet been read.

337

32059L–AVR32–01/2012

This bit is cleared when the Receive Holding Register (RHR) is read.

AT32UC3B

32059L–AVR32–01/2012

338

AT32UC3B

21.7.7

Name:

Receiver Holding Register

RHR

Access Type:

Offset:

Reset Value:

Read-only

0x18

0x00000000

31

23

15

RXSYNH

7

30

22

14

6

29

21

13

5

Reading this register will clear the CSR.RXRDY bit.

• RXSYNH: Received Sync

0: Last character received is a data sync.

1: Last character received is a command sync.

• RXCHR: Received Character

Last received character.

28

20

12

4

RXCHR[7:0]

3

27

19

11

26

18

10

2

25

17

9

1

24

16

8

RXCHR[8]

0

339

32059L–AVR32–01/2012

AT32UC3B

21.7.8

Name:

Transmitter Holding Register

THR

Access Type:

Offset:

Reset Value:

Write-only

0x1C

0x00000000

31

23

30

22

29

21

28

20

12

27

19

11

26

18

25

17

24

16

15

TXSYNH

7

14

6

13

5

10

2

9

1

8

TXCHR[8]

0 4

TXCHR[7:0]

3

• TXSYNH: Sync Field to be transmitted

0: If MR.VARSYNC is a one, the next character sent is encoded as data, and the start frame delimiter is a data sync.

1: If MR.VARSYNC is a one, the next character sent is encoded as a command, and the start frame delimiter is a command sync.

• TXCHR: Character to be Transmitted

If TXRDY is zero this field contains the next character to be transmitted.

340

32059L–AVR32–01/2012

AT32UC3B

21.7.9

Name:

Baud Rate Generator Register

BRGR

Access Type:

Offset:

Reset Value:

Read-write

0x20

0x00000000

31

23

15

7

30

22

14

6

29

21

13

5

• FP: Fractional Part

0: Fractional divider is disabled.

1 - 7: Baud rate resolution, defined by FP x 1/8.

CD: Clock Divider

28

20

12

CD[15:8]

11

4 3

CD[7:0]

27

19

26

18

10

2

25

17

FP

9

1

Table 21-21. Baud Rate in Asynchronous Mode (MR.SYNC is 0)

CD

0

OVER = 0

Baud Rate Clock Disabled

OVER = 1

1 to 65535

Baud Rate

=

Baud Rate

=

24

16

8

0

Table 21-22. Baud Rate in Synchronous Mode (MR.SYNC is 1) and SPI Mode

CD Baud Rate

0 Baud Rate Clock Disabled

1 to 65535

Baud Rate =

CD

341

32059L–AVR32–01/2012

Table 21-23. Baud Rate in ISO7816 Mode

CD

0

1 to 65535

Baud Rate

Baud Rate Clock Disabled

Baud Rate

=

AT32UC3B

32059L–AVR32–01/2012

342

21.7.10

Receiver Time-out Register

Name:

RTOR

Access Type:

Offset:

Reset Value:

Read-write

0x24

0x00000000

31

23

15

30

22

14

29

21

13

28

20

12

TO[15:8]

11

27

19

26

18

10

7 6 5 4 3 2

TO[7:0]

• TO: Time-out Value

0: The receiver Time-out is disabled.

1 - 65535: The receiver Time-out is enabled and the time-out delay is TO x bit period.

Note that the size of the TO counter is device dependent, see the Module Configuration section.

25

17

9

1

AT32UC3B

24

16

8

0

343

32059L–AVR32–01/2012

21.7.11

Transmitter Timeguard Register

Name:

TTGR

Access Type:

Offset:

Reset Value:

Read-write

0x28

0x00000000

31

23

30

22

29

21

28

20

27

19

26

18

15

7

14

6

13

5

12

4

11

3

10

2

TG

• TG: Timeguard Value

0: The transmitter Timeguard is disabled.

1 - 255: The transmitter timeguard is enabled and the timeguard delay is TG x bit period.

25

17

9

1

AT32UC3B

24

16

8

0

344

32059L–AVR32–01/2012

AT32UC3B

21.7.12

FI DI Ratio Register

Name:

FIDI

Access Type:

Offset:

Reset Value:

Read-write

0x40

0x00000174

31

23

30

22

29

21

28

20

12

27

19

11

26

18

10

25

17

15

7

14

6

13

5

9

FI_DI_RATIO[10:8]

1 4 3

FI_DI_RATIO[7:0]

2

• FI_DI_RATIO: FI Over DI Ratio Value

0: If ISO7816 mode is selected, the baud rate generator does not generate a signal.

1 - 2047: If ISO7816 mode is selected, the baud rate is the clock provided on CLK divided by FI_DI_RATIO.

24

16

8

0

345

32059L–AVR32–01/2012

AT32UC3B

21.7.13

Number of Errors Register

Name:

NER

Access Type:

Offset:

Reset Value:

Read-only

0x44

0x00000000

31

23

30

22

29

21

28

20

12

27

19

11

26

18

25

17

15

7

14

6

13

5

10

2

9

1 4

NB_ERRORS

3

• NB_ERRORS: Number of Errors

Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.

24

16

8

0

346

32059L–AVR32–01/2012

AT32UC3B

21.7.14

IrDA Filter Register

Name:

IFR

Access Type:

Offset:

Reset Value:

Read-write

0x4C

0x00000000

31

23

15

7

30

22

14

6

29

21

13

5

• IRDA_FILTER: IrDA Filter

Configures the IrDA demodulator filter.

28

20

12

4

IRDA_FILTER

3

27

19

11

26

18

10

2

25

17

9

1

24

16

8

0

347

32059L–AVR32–01/2012

AT32UC3B

21.7.15

Manchester Configuration Register

Name:

MAN

Access Type:

Offset:

Reset Value:

Read-write

0x50

0x30011004

31

23

15

7

30

DRIFT

22

14

6

29

1

21

13

5

28

RX_MPOL

20

12

TX_MPOL

4

11

3

27

19

10

2

26

18

RX_PL

25

17

9

1

TX_PL

• DRIFT: Drift compensation

0: The USART can not recover from a clock drift.

1: The USART can recover from clock drift (only available in 16x oversampling mode).

• RX_MPOL: Receiver Manchester Polarity

0: Zeroes are encoded as zero-to-one transitions, and ones are encoded as a one-to-zero transitions.

1: Zeroes are encoded as one-to-zero transitions, and ones are encoded as a zero-to-one transitions.

• RX_PP: Receiver Preamble Pattern detected

Table 21-24.

1

1

0

0

RX_PP

0

1

0

1

Preamble Pattern default polarity assumed (RX_MPOL field not set)

ALL_ONE

ALL_ZERO

ZERO_ONE

ONE_ZERO

• RX_PL: Receiver Preamble Length

0: The receiver preamble pattern detection is disabled.

1 - 15: The detected preamble length is RX_PL x bit period

• TX_MPOL: Transmitter Manchester Polarity

0: Zeroes are encoded as zero-to-one transitions, and ones are encoded as a one-to-zero transitions.

1: Zeroes are encoded as one-to-zero transitions, and ones are encoded as a zero-to-one transitions.

RX_PP

TX_PP

24

16

8

0

348

32059L–AVR32–01/2012

• TX_PP: Transmitter Preamble Pattern

Table 21-25.

1

1

0

0

TX_PP

0

1

0

1

Preamble Pattern default polarity assumed (TX_MPOL field not set)

ALL_ONE

ALL_ZERO

ZERO_ONE

ONE_ZERO

• TX_PL: Transmitter Preamble Length

0: The transmitter preamble pattern generation is disabled

1 - 15: The preamble length is TX_PL x bit period

AT32UC3B

32059L–AVR32–01/2012

349

AT32UC3B

21.7.16

Version Register

Name:

Access Type:

Offset:

Reset Value:

VERSION

Read-only

0xFC

-

31

23

30

22

29

21

28

20

12

15

7

14

6

13

5

11

• MFN

Reserved. No functionality associated.

• VERSION

Version of the module. No functionality associated.

4

VERSION[7:0]

3

27

19

26

18

MFN

10

VERSION[11:8]

9

2 1

25

17

8

0

24

16

350

32059L–AVR32–01/2012

AT32UC3B

21.8 Module Configuration

The specific configuration for each USART instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section.

Table 21-26. Module Configuration

Feature

SPI Logic

USART0

Implemented

RS485 Logic Not Implemented

Manchester Logic Not Implemented

Modem Logic

IRDA Logic

Fractional

Baudrate

Not Implemented

Not Implemented

Implemented

ISO7816

DIV

Receiver Time-out

Counter Size

Not Implemented

8

8-bits

USART1

Implemented

Implemented

Implemented

Implemented

Implemented

Implemented

Implemented

8

17-bits

USART2

Implemented

Not Implemented

Not Implemented

Not Implemented

Not Implemented

Implemented

Not Implemented

8

8-bits

Table 21-27. Module Clock Name

Module name Clock name

USART0

USART1

USART2

CLK_USART0

CLK_USART1

CLK_USART2

351

32059L–AVR32–01/2012

AT32UC3B

22. USB Interface (USBB)

Rev: 3.1.0.1.18

22.1 Features

Compatible with the USB 2.0 specification

Supports Full (12Mbit/s) and Low (1.5 Mbit/s) speed Device and Embedded Host

seven pipes/endpoints

960 of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints

Up to 2 memory banks per Pipe/Endpoint (Not for Control Pipe/Endpoint)

Flexible Pipe/Endpoint configuration and management with dedicated DMA channels

On-Chip transceivers including Pull-Ups/Pull-downs

On-Chip pad including VBUS analog comparator

22.2 Overview

The Universal Serial Bus (USB) MCU device complies with the Universal Serial Bus (USB) 2.0

specification, but it does NOT feature Hi-Speed USB (480 Mbit/s).

Each pipe/endpoint can be configured in one of several transfer types. It can be associated with one or more banks of a dual-port RAM (DPRAM) used to store the current data payload. If several banks are used (“ping-pong” mode), then one DPRAM bank is read or written by the CPU or the DMA while the other is read or written by the USBB core. This feature is mandatory for isochronous pipes/endpoints.

Table 22-1 on page 352 describes the hardware configuration of the USB MCU device.

Table 22-1.

Description of USB Pipes/Endpoints

Pipe/Endpoint Mnemonic Max. Size

4

5

6

2

3

0

1

PEP0

PEP1

PEP2

PEP3

PEP4

PEP5

PEP6

64 bytes

64 bytes

64 bytes

64 bytes

64 bytes

256 bytes

256 bytes

Max. Nb. Banks

1

2

2

2

2

2

2

DMA

N

Y

Y

Y

Y

Y

Y

Type

Control

Isochronous/Bulk/Interrupt/Control

Isochronous/Bulk/Interrupt/Control

Isochronous/Bulk/Interrupt/Control

Isochronous/Bulk/Interrupt/Control

Isochronous/Bulk/Interrupt/Control

Isochronous/Bulk/Interrupt/Control

The theoretical maximal pipe/endpoint configuration (1600) exceeds the real DPRAM size (960).

The user needs to be aware of this when configuring pipes/endpoints. To fully use the 960 of

DPRAM, the user could for example use the configuration described in

Table 22-2 on page 352

.

Table 22-2.

Example of Configuration of Pipes/Endpoints Using the Whole DPRAM

Pipe/Endpoint Mnemonic Size Nb. Banks

2

3

0

1

PEP0

PEP1

PEP2

PEP3

64 bytes

64 bytes

64 bytes

64 bytes

1

2

1

1

352

32059L–AVR32–01/2012

AT32UC3B

Table 22-2.

Example of Configuration of Pipes/Endpoints Using the Whole DPRAM

Pipe/Endpoint

4

5

6

Mnemonic

PEP4

PEP5

PEP6

Size

64 bytes

256 bytes

256 bytes

Nb. Banks

2

1

1

22.3 Block Diagram

The USBB provides a hardware device to interface a USB link to a data flow stored in a dual-port

RAM (DPRAM).

The USBB requires a 48MHz ± 0.25% reference clock, which is the USB generic clock generated from one of the power manager oscillators, optionally through one of the power manager

PLLs.

The 48MHz clock is used to generate a 12MHz full-speed (or 1.5 MHz low-speed) bit clock from the received USB differential data and to transmit data according to full- or low-speed USB device tolerance. Clock recovery is achieved by a digital phase-locked loop (a DPLL, not represented), which complies with the USB jitter specifications.

353

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

Figure 22-1. USBB Block Diagram

USB

32 bits

DPRAM

HSB

PB

Local

HSB

Slave Interface

PEP

Allocation

Slave

HSB MUX

Master

HSB0

DMA

HSB1

User Interface

USB Interrupts

USB 2.0

Core

Interrupt

Controller

Power

Manager

USB GCLK @ 48 MHz

System Clock

Domain

USB Clock

Domain

I/O

Controller

VBUS

D-

D+

USB_ID

USB_VBOF

354

AT32UC3B

22.4 Application Block Diagram

Depending on the USB operating mode (device-only, reduced-host modes) and the power source (bus-powered or self-powered), there are different typical hardware implementations.

22.4.1

22.4.1.1

Device Mode

Bus-Powered device

Figure 22-2. Bus-Powered Device Application Block Diagram

VDD

3.3 V

Regulator

USB

USB_VBOF

VBUS

D-

D+

USB_ID

39

Ω

± 1%

39

Ω

± 1%

USB

Connector

VBUS

D-

D+

ID

GND

22.4.1.2

Self-Powered device

Figure 22-3. Self-Powered Device Application Block Diagram

USB

USB_VBOF

VBUS

D-

D+

39

Ω

± 1%

39

Ω

± 1%

USB

Connector

VBUS

D-

D+

USB_ID ID

GND

355

32059L–AVR32–01/2012

22.4.2

Host Mode

Figure 22-4. Host Application Block Diagram

VDD

5 V DC/DC

Generator

USB

USB_VBOF

VBUS

D-

D+

USB_ID

39

Ω

± 1%

39

Ω

± 1%

USB

Connector

VBUS

D-

D+

ID

GND

AT32UC3B

356

32059L–AVR32–01/2012

AT32UC3B

22.5 I/O Lines Description

Table 22-3.

I/O Lines Description

PIn Name

USB_VBOF

USB_VBUS

D-

D+

Pin Description

USB VBus On/Off: Bus Power Control Port

VBus: Bus Power Measurement Port

Data -: Differential Data Line - Port

Data +: Differential Data Line + Port

USB_ID USB Identification: Mini Connector Identification Port

Type

Output

Input

Input/Output

Input/Output

Input

Active Level

VBUSPO

Low: Mini-A plug

High Z: Mini-B plug

32059L–AVR32–01/2012

357

AT32UC3B

22.6 Product Dependencies

In order to use this module, other parts of the system must be configured correctly, as described below.

22.6.1

I/O Lines

The USB_VBOF and USB_ID pins are multiplexed with I/O Controller lines and may also be multiplexed with lines of other peripherals. In order to use them with the USB, the user must first configure the I/O Controller to assign them to their USB peripheral functions.

If USB_ID is used, the I/O Controller must be configured to enable the internal pull-up resistor of its pin.

If USB_VBOF or USB_ID is not used by the application, the corresponding pin can be used for other purposes by the I/O Controller or by other peripherals.

22.6.2

Clocks

The clock for the USBB bus interface (CLK_USBB) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the USBB before disabling the clock, to avoid freezing the USBB in an undefined state.

The 48MHz USB clock is generated by a dedicated generic clock from the Power Manager.

Before using the USB, the user must ensure that the USB generic clock (GCLK_USBB) is enabled at 48MHz in the Power Manager.

22.6.3

Interrupts

The USBB interrupt request line is connected to the interrupt controller. Using the USBB interrupt requires the interrupt controller to be programmed first.

358

32059L–AVR32–01/2012

AT32UC3B

22.7 Functional Description

22.7.1

22.7.1.1

USB General Operation

Introduction

After a hardware reset, the USBB is disabled. When enabled, the USBB runs either in device mode or in host mode according to the ID detection.

If the USB_ID pin is not connected to ground, the USB_ID Pin State bit in the General Status register (USBSTA.ID) is set (the internal pull-up resistor of the USB_ID pin must be enabled by the I/O Controller) and device mode is engaged.

The USBSTA.ID bit is cleared when a low level has been detected on the USB_ID pin. Host mode is then engaged.

22.7.1.2

Power-On and reset

Figure 22-5 on page 359 describes the USBB main states.

Figure 22-5. General States

Macro off:

USBE = 0

Clock stopped:

FRZCLK = 1

USBE = 0

Reset HW

RESET

USBE = 1

ID = 1

USBE = 0

USBE = 1

ID = 0

Device

USBE = 0

<any other state>

Host

After a hardware reset, the USBB is in the Reset state. In this state:

• The macro is disabled. The USBB Enable bit in the General Control register

(USBCON.USBE) is zero.

• The macro clock is stopped in order to minimize power consumption. The Freeze USB Clock bit in USBCON (USBON.FRZCLK) is set.

• The pad is in suspend mode.

• The internal states and registers of the device and host modes are reset.

• The DPRAM is not cleared and is accessible.

• The USBSTA.ID bit and the VBus Level bit in the UBSTA (UBSTA.VBUS) reflect the states of the USB_ID and USB_VBUS input pins.

• The OTG Pad Enable (OTGPADE) bit, the VBus Polarity (VBUSPO) bit, the FRZCLK bit, the

USBE bit, the USB_ID Pin Enable (UIDE) bit, the USBB Mode (UIMOD) bit in USBCON, and the Low-Speed Mode Force bit in the Device General Control (UDCON.LS) register can be written by software, so that the user can program pads and speed before enabling the macro, but their value is only taken into account once the macro is enabled and unfrozen.

359

32059L–AVR32–01/2012

AT32UC3B

22.7.1.3

After writing a one to USBCON.USBE, the USBB enters the Device or the Host mode (according to the ID detection) in idle state.

The USBB can be disabled at any time by writing a zero to USBCON.USBE. In fact, writing a zero to USBCON.USBE acts as a hardware reset, except that the OTGPADE, VBUSPO,

FRZCLK, UIDE, UIMOD and, LS bits are not reset.

Interrupts

One interrupt vector is assigned to the USB interface. Figure 22-6 on page 361 shows the struc-

ture of the USB interrupt system.

32059L–AVR32–01/2012

360

AT32UC3B

Figure 22-6. Interrupt System

USBSTA.IDTI

USBSTA.VBUSTI

USBSTA.SRPI

USBSTA.VBERRI

USBSTA.BCERRI

USBSTA.ROLEEXI

USBSTA.HNPERRI

USBSTA.STOI

USBCON.IDTE

USBCON.VBUSTE

USBCON.SRPE

USBCON.VBERRE

USBCON.BCERRE

USBCON.ROLEEXE

USBCON.HNPERRE

USBCON.STOE

USB General

Interrupt

UESTAX.TXINI

UESTAX.RXOUTI

UESTAX.RXSTPI

UESTAX.UNDERFI

UESTAX.NAKOUTI

UESTAX.NAKINI

UESTAX.OVERFI

UESTAX.STALLEDI

UESTAX.CRCERRI

UESTAX.SHORTPACKET

UESTAX.NBUSYBK

UECONX.TXINE

UECONX.RXOUTE

UECONX.RXSTPE

UECONX.UNDERFE

UECONX.NAKOUTE

UECONX.NAKINE

UECONX.OVERFE

UECONX.STALLEDE

UECONX.CRCERRE

UECONX.SHORTPACKETE

UECONX.NBUSYBKE

USB Device

Endpoint X

Interrupt

UDINT.SUSP

UDINT.SOF

UDINT.EORST

UDINT.WAKEUP

UDINT.EORSM

UDINT.UPRSM

UDINT.EPXINT

USB Device

DMA Channel X

Interrupt

UDINT.DMAXINT

UDINTE.SUSPE

UDINTE.SOFE

UDINTE.EORSTE

UDINTE.WAKEUPE

UDINTE.EORSME

UDINTE.UPRSME

UDINTE.EPXINTE

UDINTE.DMAXINTE

USB Device

Interrupt

USB

Interrupt

UDDMAX_STATUS.EOT_STA

UDDMAX_STATUS.EOCH_BUFF_STA

UDDMAX_STATUS.DESC_LD_STA

UDDMAX_CONTROL.EOT_IRQ_EN

UDDMAX_CONTROL.EOBUFF_IRQ_EN

UDDMAX_CONTROL.DESC_LD_IRQ_EN

UPSTAX.RXINI

UPSTAX.TXOUTI

UPSTAX.TXSTPI

UPSTAX.UNDERFI

UPSTAX.PERRI

UPSTAX.NAKEDI

UPSTAX.OVERFI

UPSTAX.RXSTALLDI

UPSTAX.CRCERRI

UPSTAX.SHORTPACKETI

UPSTAX.NBUSYBK

UHDMAX_STATUS.EOT_STA

UHDMAX_STATUS.EOCH_BUFF_STA

UHDMAX_STATUS.DESC_LD_STA

UPCONX.RXINE

UPCONX.TXOUTE

UPCONX.TXSTPE

UPCONX.UNDERFIE

UPCONX.PERRE

UPCONX.NAKEDE

UPCONX.OVERFIE

UPCONX.RXSTALLDE

UPCONX.CRCERRE

UPCONX.SHORTPACKETIE

UPCONX.NBUSYBKE

UHINT.DCONNI

UHINT.DDISCI

UHINT.RSTI

UHINT.RSMEDI

USB Host

Pipe X

Interrupt

UHINT.RXRSMI

UHINT.HSOFI

UHINT.HWUPI

UHINT.PXINT

USB Host

DMA Channel X

Interrupt

UHINT.DMAXINT

UHINTE.DCONNIE

UHINTE.DDISCIE

UHINTE.RSTIE

UHINTE.RSMEDIE

UHINTE.RXRSMIE

UHINTE.HSOFIE

UHINTE.HWUPIE

UHINTE.PXINTE

UHINTE.DMAXINTE

USB Host

Interrupt

UHDMAX_CONTROL.EOT_IRQ_EN

UHDMAX_CONTROL.EOBUFF_IRQ_EN

UHDMAX_CONTROL.DESC_LD_IRQ_EN

Asynchronous interrupt source

See Section 22.7.2.17

and

Section 22.7.3.13

for further details about device and host interrupts.

There are two kinds of general interrupts: processing, i.e. their generation is part of the normal processing, and exception, i.e. errors (not related to CPU exceptions).

The processing general interrupts are:

361

32059L–AVR32–01/2012

AT32UC3B

22.7.1.4

• The ID Transition Interrupt (IDTI)

• The VBus Transition Interrupt (VBUSTI)

• The Role Exchange Interrupt (ROLEEXI)

The exception general interrupts are:

• The VBus Error Interrupt (VBERRI)

• The B-Connection Error Interrupt (BCERRI)

• The Suspend Time-Out Interrupt (STOI)

MCU Power modes

•Run mode

In this mode, all MCU clocks can run, including the USB clock.

•Idle mode

In this mode, the CPU is halted, i.e. the CPU clock is stopped. The Idle mode is entered whatever the state of the USBB. The MCU wakes up on any USB interrupt.

•Frozen mode

Same as the Idle mode, except that the HSB module is stopped, so the USB DMA, which is an

HSB master, can not be used. Moreover, the USB DMA must be stopped before entering this sleep mode in order to avoid erratic behavior. The MCU wakes up on any USB interrupt.

•Standby, Stop, DeepStop and Static modes

Same as the Frozen mode, except that the USB generic clock and other clocks are stopped, so the USB macro is frozen. Only the asynchronous USB interrupt sources can wake up the MCU in these modes

(1)

. The Power Manager (PM) may have to be configured to enable asynchro-

nous wake up from USB. The USB module must be frozen by writing a one to the FRZCLK bit.

Note: 1. When entering a sleep mode deeper or equal to DeepStop, the VBus asynchronous interrupt can not be triggered because the bandgap voltage reference is off. Thus this interrupt should be disabled (USBCON.VBUSTE = 0).

•USB clock frozen

In the run, idle and frozen MCU modes, the USBB can be frozen when the USB line is in the suspend mode, by writing a one to the FRZCLK bit, what reduces power consumption.

In deeper MCU power modes (from StandBy mode), the USBC must be frozen.

In this case, it is still possible to access the following elements, but only in Run mode:

• The OTGPADE, VBUSPO, FRZCLK, USBE, UIDE, UIMOD and LS bits in the USBCON register

• The DPRAM (through the USB Pipe/Endpoint n FIFO Data (USBFIFOnDATA) registers, but not through USB bus transfers which are frozen)

362

32059L–AVR32–01/2012

AT32UC3B

22.7.1.5

Moreover, when FRZCLK is written to one, only the asynchronous interrupt sources may trigger the USB interrupt:

• The ID Transition Interrupt (IDTI)

• The VBus Transition Interrupt (VBUSTI)

• The Wake-up Interrupt (WAKEUP)

• The Host Wake-up Interrupt (HWUPI)

•USB Suspend mode

In peripheral mode, the Suspend Interrupt bit in the Device Global Interrupt register

(UDINT.SUSP)indicates that the USB line is in the suspend mode. In this case, the USB Data

UTMI transceiver is automatically set in suspend mode to reduce the consumption.

Speed control

•Device mode

When the USBB interface is in device mode, the speed selection (full-/low-speed) depends on which of D+ and D- is pulled up. The LS bit allows to connect an internal pull-up resistor either on D+ (full-speed mode) or on D- (low-speed mode). The LS bit shall be written before attaching the device, what can be done by clearing the DETACH bit in UDCON.

Figure 22-7. Speed Selection in Device Mode

VBUS

UDCON.DETACH

UDCON.LS

D+

D-

22.7.1.6

•Host mode

When the USB interface is in host mode, internal pull-down resistors are connected on both D+ and D- and the interface detects the speed of the connected device, which is reflected by the

Speed Status (SPEED) field in USBSTA.

DPRAM management

Pipes and endpoints can only be allocated in ascending order (from the pipe/endpoint 0 to the last pipe/endpoint to be allocated). The user shall therefore configure them in the same order.

The allocation of a pipe/endpoint n starts when the Endpoint Memory Allocate bit in the Endpoint n Configuration register (UECFGn.ALLOC) is written to one. Then, the hardware allocates a

363

32059L–AVR32–01/2012

AT32UC3B

memory area in the DPRAM and inserts it between the n-1 and n+1 pipes/endpoints. The n+1 pipe/endpoint memory window slides up and its data is lost. Note that the following pipe/endpoint memory windows (from n+2) do not slide.

Disabling a pipe, by writing a zero to the Pipe n Enable bit in the Pipe Enable/Reset register

(UPRST.PENn), or disabling an endpoint, by writing a zero to the Endpoint n Enable bit in the

Endpoint Enable/Reset register (UERST.EPENn), resets neither the UECFGn.ALLOC bit nor its configuration (the Pipe Banks (PBK) field, the Pipe Size (PSIZE) field, the Pipe Token (PTO-

KEN) field, the Pipe Type (PTYPE) field, the Pipe Endpoint Number (PEPNUM) field, and the

Pipe Interrupt Request Frequency (INTFRQ) field in the Pipe n Configuration (UPCFGn) register/the Endpoint Banks (EPBK) field, the Endpoint Size (EPSIZE) field, the Endpoint Direction

(EPDIR) field, and the Endpoint Type (EPTYPE) field in UECFGn).

To free its memory, the user shall write a zero to the UECFGn.ALLOC bit. The n+1 pipe/endpoint memory window then slides down and its data is lost. Note that the following pipe/endpoint memory windows (from n+2) does not slide.

Figure 22-8 on page 364 illustrates the allocation and reorganization of the DPRAM in a typical

example.

Figure 22-8. Allocation and Reorganization of the DPRAM

Free Memory

PEP5

PEP4

PEP3

PEP2

Free Memory

PEP5

PEP4

PEP3

(ALLOC stays at 1)

PEP2

Free Memory

PEP5

PEP4 Lost Memory

PEP4

PEP2

Free Memory

PEP5

PEP4

PEP3 (larger size)

PEP2

Conflict

PEP1

PEP0

PEP1

PEP0

PEP1

PEP0

PEP1

PEP0

U(P/E)RST.(E)PENn = 1

U(P/E)CFGn.ALLOC = 1

U(P/E)RST.(E)PEN3 = 0 U(P/E)CFG3.ALLOC = 0 U(P/E)RST.(E)PEN3 = 1

U(P/E)CFG3.ALLOC = 1

Pipes/Endpoints 0..5

Activated

Pipe/Endpoint 3

Disabled

Pipe/Endpoint 3

Memory Freed

Pipe/Endpoint 3

Activated

1. The pipes/endpoints 0 to 5 are enabled, configured and allocated in ascending order.

Each pipe/endpoint then owns a memory area in the DPRAM.

2. The pipe/endpoint 3 is disabled, but its memory is kept allocated by the controller.

3. In order to free its memory, its ALLOC bit is written to zero. The pipe/endpoint 4 memory window slides down, but the pipe/endpoint 5 does not move.

4. If the user chooses to reconfigure the pipe/endpoint 3 with a larger size, the controller allocates a memory area after the pipe/endpoint 2 memory area and automatically slides up the pipe/endpoint 4 memory window. The pipe/endpoint 5 does not move and a memory conflict appears as the memory windows of the pipes/endpoints 4 and 5 overlap. The data of these pipes/endpoints is potentially lost.

Note that:

364

32059L–AVR32–01/2012

AT32UC3B

22.7.1.7

• There is no way the data of the pipe/endpoint 0 can be lost (except if it is de-allocated) as memory allocation and de-allocation may affect only higher pipes/endpoints.

• Deactivating then reactivating a same pipe/endpoint with the same configuration only modifies temporarily the controller DPRAM pointer and size for this pipe/endpoint, but nothing changes in the DPRAM, so higher endpoints seem to not have been moved and their data is preserved as far as nothing has been written or received into them while changing the allocation state of the first pipe/endpoint.

• When the user write a one to the ALLOC bit, the Configuration OK Status bit in the Endpoint n Status register (UESTAn.CFGOK) is set only if the configured size and number of banks are correct compared to their maximal allowed values for the endpoint and to the maximal

FIFO size (i.e. the DPRAM size), so the value of CFGOK does not consider memory allocation conflicts.

Pad Suspend

Figure 22-9 on page 365 shows the pad behavior.

Figure 22-9. Pad Behavior

USBE = 1

& DETACH = 0

& Suspend

Idle

USBE = 0

| DETACH = 1

| Suspend

Active

• In the Idle state, the pad is put in low power consumption mode, i.e., the differential receiver of the USB pad is off, and internal pull-down with strong value(15K) are set in both DP/DM to avoid floating lines.

• In the Active state, the pad is working.

Figure 22-10 on page 366

illustrates the pad events leading to a PAD state change.

365

32059L–AVR32–01/2012

AT32UC3B

Figure 22-10. Pad Events

SUSP

Suspend detected

WAKEUP

PAD State

Active

Idle

Cleared on wake-up

Wake-up detected Cleared by software to acknowledge the interrupt

Active

22.7.1.8

The SUSP bit is set and the Wake-Up Interrupt (WAKEUP) bit in UDINT is cleared when a USB

“Suspend” state has been detected on the USB bus. This event automatically puts the USB pad in the Idle state. The detection of a non-idle event sets WAKEUP, clears SUSP and wakes up the USB pad.

Moreover, the pad goes to the Idle state if the macro is disabled or if the DETACH bit is written to one. It returns to the Active state when USBE is written to one and DETACH is written to zero.

Plug-In detection

The USB connection is detected from the USB_VBUS pad.

Figure 22-11 on page 366 shows the

architecture of the plug-in detector.

Figure 22-11. Plug-In Detection Input Block Diagram

VDD

VBus_pulsing

USB_VBUS

Session_valid

Va_Vbus_valid

Logic

VBUS

USBSTA

VBUSTI

USBSTA

VBus_discharge

GND

Pad Logic

The control logic of the USB_VBUS pad outputs two signals:

• The Session_valid signal is high when the voltage on the USB_VBUS pad is higher than or equal to 1.4V.

• The Va_Vbus_valid signal is high when the voltage on the USB_VBUS pad is higher than or equal to 4.4V.

In device mode, the USBSTA.VBUS bit follows the Session_valid comparator output:

• It is set when the voltage on the USB_VBUS pad is higher than or equal to 1.4V.

366

32059L–AVR32–01/2012

AT32UC3B

22.7.1.9

• It is cleared when the voltage on the VBUS pad is lower than 1.4V.

In host mode, the USBSTA.VBUS bit follows an hysteresis based on Session_valid and

Va_Vbus_valid:

• It is set when the voltage on the USB_VBUS pad is higher than or equal to 4.4V.

• It is cleared when the voltage on the USB_VBUS pad is lower than 1.4V.

The VBus Transition interrupt (VBUSTI) bit in USBSTA is set on each transition of the USB-

STA.VBUS bit.

The USBSTA.VBUS bit is effective whether the USBB is enabled or not.

ID detection

Figure 22-12 on page 367

shows how the ID transitions are detected.

Figure 22-12. ID Detection Input Block Diagram

VDD

USB_ID

1

UIMOD

USBCON

0

UIDE

USBCON

ID

USBSTA

IDTI

USBSTA

I/O Controller

The USB mode (device or host) can be either detected from the USB_ID pin or software selected by writing to the UIMOD bit, according to the UIDE bit. This allows the USB_ID pin to be used as a general purpose I/O pin even when the USB interface is enabled.

By default, the USB_ID pin is selected (UIDE is written to one) and the USBB is in device mode

(UBSTA.ID is one), what corresponds to the case where no Mini-A plug is connected, i.e. no plug or a Mini-B plug is connected and the USB_ID pin is kept high by the internal pull-up resistor from the I/O Controller (which must be enabled if USB_ID is used).

The ID Transition Interrupt (IDTI) bit in USBSTA is set on each transition of the ID bit, i.e. when a

Mini-A plug (host mode) is connected or disconnected. This does not occur when a Mini-B plug

(device mode) is connected or disconnected.

The USBSTA.ID bit is effective whether the USBB is enabled or not.

367

32059L–AVR32–01/2012

AT32UC3B

22.7.2

22.7.2.1

USB Device Operation

Introduction

In device mode, the USBB supports full- and low-speed data transfers.

In addition to the default control endpoint, six endpoints are provided, which can be configured

with the types isochronous, bulk or interrupt, as described in Table 22-1 on page 352

.

The device mode starts in the Idle state, so the pad consumption is reduced to the minimum.

22.7.2.2

Power-On and reset

Figure 22-13 on page 368

describes the USBB device mode main states.

Figure 22-13. Device Mode States

USBE = 0

| ID = 0

<any other state>

HW

RESET

Reset

USBE = 0

| ID = 0

USBE = 1

& ID = 1

Idle

22.7.2.3

After a hardware reset, the USBB device mode is in the Reset state. In this state:

• The macro clock is stopped in order to minimize power consumption (FRZCLK is written to one).

• The internal registers of the device mode are reset.

• The endpoint banks are de-allocated.

• Neither D+ nor D- is pulled up (DETACH is written to one).

D+ or D- will be pulled up according to the selected speed as soon as the DETACH bit is written to zero and VBus is present. See

“Device mode”

for further details.

When the USBB is enabled (USBE is written to one) in device mode (ID is one), its device mode state goes to the Idle state with minimal power consumption. This does not require the USB clock to be activated.

The USBB device mode can be disabled and reset at any time by disabling the USBB (by writing a zero to USBE) or when host mode is engaged (ID is zero).

USB reset

The USB bus reset is managed by hardware. It is initiated by a connected host.

When a USB reset is detected on the USB line, the following operations are performed by the controller:

• All the endpoints are disabled, except the default control endpoint.

368

32059L–AVR32–01/2012

AT32UC3B

22.7.2.4

22.7.2.5

• The default control endpoint is reset (see

Section 22.7.2.4

for more details).

• The data toggle sequence of the default control endpoint is cleared.

• At the end of the reset process, the End of Reset (EORST) bit in UDINT interrupt is set.

Endpoint reset

An endpoint can be reset at any time by writing a one to the Endpoint n Reset (EPRSTn) bit in the UERST register. This is recommended before using an endpoint upon hardware reset or when a USB bus reset has been received. This resets:

• The internal state machine of this endpoint.

• The receive and transmit bank FIFO counters.

• All the registers of this endpoint (UECFGn, UESTAn, the Endpoint n Control (UECONn) register), except its configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE) and the Data

Toggle Sequence (DTSEQ) field of the UESTAn register.

Note that the interrupt sources located in the UESTAn register are not cleared when a USB bus reset has been received.

The endpoint configuration remains active and the endpoint is still enabled.

The endpoint reset may be associated with a clear of the data toggle sequence as an answer to the CLEAR_FEATURE USB request. This can be achieved by writing a one to the Reset Data

Toggle Set bit in the Endpoint n Control Set register (UECONnSET.RSTDTS).(This will set the

Reset Data Toggle (RSTD) bit in UECONn).

In the end, the user has to write a zero to the EPRSTn bit to complete the reset operation and to start using the FIFO.

Endpoint activation

The endpoint is maintained inactive and reset (see

Section 22.7.2.4

for more details) as long as it is disabled (EPENn is written to zero). DTSEQ is also reset.

The algorithm represented on Figure 22-14 on page 370 must be followed in order to activate an

endpoint.

369

32059L–AVR32–01/2012

AT32UC3B

Figure 22-14. Endpoint Activation Algorithm

Endpoint

Activation

EPENn = 1

UECFGn

EPTYPE

EPDIR

EPSIZE

EPBK

ALLOC

CFGOK ==

1?

Yes

Endpoint

Activated

No

ERROR

Enable the endpoint.

Configure the endpoint:

- type

- direction

- size

- number of banks

Allocate the configured DPRAM banks.

Test if the endpoint configuration is correct.

22.7.2.6

As long as the endpoint is not correctly configured (CFGOK is zero), the controller does not acknowledge the packets sent by the host to this endpoint.

The CFGOK bit is set only if the configured size and number of banks are correct compared to their maximal allowed values for the endpoint (see

Table 22-1 on page 352 ) and to the maximal

FIFO size (i.e. the DPRAM size).

See Section 22.7.1.6

for more details about DPRAM management.

Address setup

The USB device address is set up according to the USB protocol.

• After all kinds of resets, the USB device address is 0.

• The host starts a SETUP transaction with a SET_ADDRESS(addr) request.

• The user write this address to the USB Address (UADD) field in UDCON, and write a zero to the Address Enable (ADDEN) bit in UDCON, so the actual address is still 0.

• The user sends a zero-length IN packet from the control endpoint.

• The user enables the recorded USB device address by writing a one to ADDEN.

Once the USB device address is configured, the controller filters the packets to only accept those targeting the address stored in UADD.

UADD and ADDEN shall not be written all at once.

UADD and ADDEN are cleared:

• On a hardware reset.

• When the USBB is disabled (USBE written to zero).

• When a USB reset is detected.

When UADD or ADDEN is cleared, the default device address 0 is used.

370

32059L–AVR32–01/2012

AT32UC3B

22.7.2.7

22.7.2.8

22.7.2.9

22.7.2.10

Suspend and wake-up

When an idle USB bus state has been detected for 3 ms, the controller set the Suspend (SUSP) interrupt bit in UDINT. The user may then write a one to the FRZCLK bit to reduce power consumption. The MCU can also enter the Idle or Frozen sleep mode to lower again power consumption.

To recover from the Suspend mode, the user shall wait for the Wake-Up (WAKEUP) interrupt bit, which is set when a non-idle event is detected, then write a zero to FRZCLK.

As the WAKEUP interrupt bit in UDINT is set when a non-idle event is detected, it can occur whether the controller is in the Suspend mode or not. The SUSP and WAKEUP interrupts are thus independent of each other except that one bit is cleared when the other is set.

Detach

The reset value of the DETACH bit is one.

It is possible to initiate a device re-enumeration simply by writing a one then a zero to DETACH.

DETACH acts on the pull-up connections of the D+ and D- pads. See “Device mode” for further

details.

Remote wake-up

The Remote Wake-Up request (also known as Upstream Resume) is the only one the device may send on its own initiative, but the device should have beforehand been allowed to by a

DEVICE_REMOTE_WAKEUP request from the host.

• First, the USBB must have detected a “Suspend” state on the bus, i.e. the Remote Wake-Up request can only be sent after a SUSP interrupt has been set.

• The user may then write a one to the Remote Wake-Up (RMWKUP) bit in UDCON to send an upstream resume to the host for a remote wake-up. This will automatically be done by the controller after 5ms of inactivity on the USB bus.

• When the controller sends the upstream resume, the Upstream Resume (UPRSM) interrupt is set and SUSP is cleared.

• RMWKUP is cleared at the end of the upstream resume.

• If the controller detects a valid “End of Resume” signal from the host, the End of Resume

(EORSM) interrupt is set.

STALL request

For each endpoint, the STALL management is performed using:

• The STALL Request (STALLRQ) bit in UECONn to initiate a STALL request.

• The STALLed Interrupt (STALLEDI) bit in UESTAn is set when a STALL handshake has been sent.

To answer the next request with a STALL handshake, STALLRQ has to be set by writing a one to the STALL Request Set (STALLRQS) bit. All following requests will be discarded (RXOUTI, etc. will not be set) and handshaked with a STALL until the STALLRQ bit is cleared, what is done when a new SETUP packet is received (for control endpoints) or when the STALL Request

Clear (STALLRQC) bit is written to one.

Each time a STALL handshake is sent, the STALLEDI bit is set by the USBB and the EPnINT interrupt is set.

371

32059L–AVR32–01/2012

AT32UC3B

22.7.2.11

•Special considerations for control endpoints

If a SETUP packet is received into a control endpoint for which a STALL is requested, the

Received SETUP Interrupt (RXSTPI) bit in UESTAn is set and STALLRQ and STALLEDI are cleared. The SETUP has to be ACKed.

This management simplifies the enumeration process management. If a command is not supported or contains an error, the user requests a STALL and can return to the main task, waiting for the next SETUP request.

•STALL handshake and retry mechanism

The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the

STALLRQ bit is set and if there is no retry required.

Management of control endpoints

•Overview

A SETUP request is always ACKed. When a new SETUP packet is received, the RXSTPI is set, but not the Received OUT Data Interrupt (RXOUTI) bit.

The FIFO Control (FIFOCON) bit in UECONn and the Read/Write Allowed (RWALL) bit in

UESTAn are irrelevant for control endpoints. The user shall therefore never use them on these endpoints. When read, their value are always zero.

Control endpoints are managed using:

• The RXSTPI bit which is set when a new SETUP packet is received and which shall be cleared by firmware to acknowledge the packet and to free the bank.

• The RXOUTI bit which is set when a new OUT packet is received and which shall be cleared by firmware to acknowledge the packet and to free the bank.

• The Transmitted IN Data Interrupt (TXINI) bit which is set when the current bank is ready to accept a new IN packet and which shall be cleared by firmware to send the packet.

•Control write

Figure 22-15 on page 373 shows a control write transaction. During the status stage, the control-

ler will not necessarily send a NAK on the first IN token:

• If the user knows the exact number of descriptor bytes that must be read, it can then anticipate the status stage and send a zero-length packet after the next IN token.

• Or it can read the bytes and wait for the NAKed IN Interrupt (NAKINI) which tells that all the bytes have been sent by the host and that the transaction is now in the status stage.

372

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

Figure 22-15. Control Write

SETUP

USB Bus SETUP

RXSTPI

RXOUTI

TXINI

HW SW

OUT

HW

DATA

SW

OUT

HW SW

IN

NAK

STATUS

IN

SW

•Control read

Figure 22-16 on page 373 shows a control read transaction. The USBB has to manage the

simultaneous write requests from the CPU and the USB host.

Figure 22-16. Control Read

USB Bus

RXSTPI

RXOUTI

TXINI

Wr Enable

HOST

Wr Enable

CPU

SETUP

SETUP

HW SW

SW

IN

HW

DATA

SW

IN OUT

NAK

STATUS

OUT

HW SW

A NAK handshake is always generated on the first status stage command.

When the controller detects the status stage, all the data written by the CPU are lost and clearing TXINI has no effect.

The user checks if the transmission or the reception is complete.

The OUT retry is always ACKed. This reception sets RXOUTI and TXINI. Handle this with the following software algorithm: set TXINI wait for RXOUTI OR TXINI if RXOUTI, then clear bit and return if TXINI, then continue

Once the OUT status stage has been received, the USBB waits for a SETUP request. The

SETUP request has priority over any other request and has to be ACKed. This means that any other bit should be cleared and the FIFO reset when a SETUP is received.

The user has to take care of the fact that the byte counter is reset when a zero-length OUT packet is received.

373

AT32UC3B

22.7.2.12

Management of IN endpoints

•Overview

IN packets are sent by the USB device controller upon IN requests from the host. All the data can be written which acknowledges or not the bank when it is full.

The endpoint must be configured first.

The TXINI bit is set at the same time as FIFOCON when the current bank is free. This triggers an EPnINT interrupt if the Transmitted IN Data Interrupt Enable (TXINE) bit in UECONn is one.

TXINI shall be cleared by software (by writing a one to the Transmitted IN Data Interrupt Enable

Clear bit in the Endpoint n Control Clear register (UECONnCLR.TXINIC)) to acknowledge the interrupt, what has no effect on the endpoint FIFO.

The user then writes into the FIFO (see

”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-

DATA)” on page 471

) and write a one to the FIFO Control Clear (FIFOCONC) bit in

UECONnCLR to clear the FIFOCON bit. This allows the USBB to send the data. If the IN endpoint is composed of multiple banks, this also switches to the next bank. The TXINI and

FIFOCON bits are updated in accordance with the status of the next bank.

TXINI shall always be cleared before clearing FIFOCON.

The RWALL bit is set when the current bank is not full, i.e. the software can write further data into the FIFO.

Figure 22-17. Example of an IN Endpoint with 1 Data Bank

NAK

IN

DATA

(bank 0)

ACK IN

HW

TXINI SW SW

FIFOCON write data to CPU

BANK 0

SW write data to CPU

BANK 0

SW

374

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

TXINI

Figure 22-18. Example of an IN Endpoint with 2 Data Banks

IN

DATA

(bank 0)

ACK IN

HW

SW SW SW

DATA

(bank 1)

ACK

FIFOCON write data to CPU

BANK 0

SW write data to CPU

BANK 1

SW write data to CPU

BANK0

•Detailed description

The data is written, following the next flow:

• When the bank is empty, TXINI and FIFOCON are set, what triggers an EPnINT interrupt if

TXINE is one.

• The user acknowledges the interrupt by clearing TXINI.

• The user writes the data into the current bank by using the USB Pipe/Endpoint nFIFO Data

virtual segment (see ”USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)” on page

471

), until all the data frame is written or the bank is full (in which case RWALL is cleared and the Byte Count (BYCT) field in UESTAn reaches the endpoint size).

• The user allows the controller to send the bank and switches to the next bank (if any) by clearing FIFOCON.

If the endpoint uses several banks, the current one can be written while the previous one is being read by the host. Then, when the user clears FIFOCON, the following bank may already be free and TXINI is set immediately.

An “Abort” stage can be produced when a zero-length OUT packet is received during an IN stage of a control or isochronous IN transaction. The Kill IN Bank (KILLBK) bit in UECONn is used to kill the last written bank. The best way to manage this abort is to apply the algorithm rep-

resented on Figure 22-19 on page 376

. See

”Endpoint n Control Register” on page 432

to have more details about the KILLBK bit.

375

AT32UC3B

Figure 22-19. Abort Algorithm

Endpoint

Abort

TXINEC = 1

NBUSYBK

== 0?

Yes

EPRSTn = 1

No

KILLBKS = 1

Yes

KILLBK

== 1?

No

Abort Done

Disable the TXINI interrupt.

Abort is based on the fact that no bank is busy, i.e., that nothing has to be sent

Kill the last written bank.

Wait for the end of the procedure

22.7.2.13

Management of OUT endpoints

•Overview

OUT packets are sent by the host. All the data can be read which acknowledges or not the bank when it is empty.

The endpoint must be configured first.

The RXOUTI bit is set at the same time as FIFOCON when the current bank is full. This triggers an EPnINT interrupt if the Received OUT Data Interrupt Enable (RXOUTE) bit in UECONn is one.

RXOUTI shall be cleared by software (by writing a one to the Received OUT Data Interrupt Clear

(RXOUTIC) bit) to acknowledge the interrupt, what has no effect on the endpoint FIFO.

The user then reads from the FIFO (see ”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-

DATA)” on page 471 ) and clears the FIFOCON bit to free the bank. If the OUT endpoint is

composed of multiple banks, this also switches to the next bank. The RXOUTI and FIFOCON bits are updated in accordance with the status of the next bank.

RXOUTI shall always be cleared before clearing FIFOCON.

The RWALL bit is set when the current bank is not empty, i.e. the software can read further data from the FIFO.

376

32059L–AVR32–01/2012

OUT

RXOUTI

FIFOCON

OUT

AT32UC3B

Figure 22-20. Example of an OUT Endpoint with one Data Bank

DATA

(bank 0)

ACK

NAK

OUT

DATA

(bank 0)

HW

SW

ACK

HW

SW read data from CPU

BANK 0

SW

Figure 22-21. Example of an OUT Endpoint with two Data Banks

DATA

(bank 0)

ACK OUT

DATA

(bank 1)

ACK

HW

HW

SW read data from CPU

BANK 0

SW RXOUTI

FIFOCON read data from CPU

BANK 0

SW read data from CPU

BANK 1

•Detailed description

The data is read, following the next flow:

• When the bank is full, RXOUTI and FIFOCON are set, what triggers an EPnINT interrupt if

RXOUTE is one.

• The user acknowledges the interrupt by writing a one to RXOUTIC in order to clear RXOUTI.

• The user can read the byte count of the current bank from BYCT to know how many bytes to read, rather than polling RWALL.

• The user reads the data from the current bank by using the USBFIFOnDATA register (see

”USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)” on page 471

), until all the expected data frame is read or the bank is empty (in which case RWALL is cleared and

BYCT reaches zero).

• The user frees the bank and switches to the next bank (if any) by clearing FIFOCON.

If the endpoint uses several banks, the current one can be read while the following one is being written by the host. Then, when the user clears FIFOCON, the following bank may already be ready and RXOUTI is set immediately.

377

32059L–AVR32–01/2012

AT32UC3B

22.7.2.14

22.7.2.15

Underflow

This error exists only for isochronous IN/OUT endpoints. It set the Underflow Interrupt

(UNDERFI) bit in UESTAn, what triggers an EPnINT interrupt if the Underflow Interrupt Enable

(UNDERFE) bit is one.

An underflow can occur during IN stage if the host attempts to read from an empty bank. A zerolength packet is then automatically sent by the USBB.

An underflow can not occur during OUT stage on a CPU action, since the user may read only if the bank is not empty (RXOUTI is one or RWALL is one).

An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not fast enough. The packet is lost.

An underflow can not occur during IN stage on a CPU action, since the user may write only if the bank is not full (TXINI is one or RWALL is one).

Overflow

This error exists for all endpoint types. It set the Overflow interrupt (OVERFI) bit in UESTAn, what triggers an EPnINT interrupt if the Overflow Interrupt Enable (OVERFE) bit is one.

An overflow can occur during OUT stage if the host attempts to write into a bank that is too small for the packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first bytes of the packet that fit in.

An overflow can not occur during IN stage on a CPU action, since the user may write only if the bank is not full (TXINI is one or RWALL is one).

22.7.2.16

CRC error

This error exists only for isochronous OUT endpoints. It set the CRC Error Interrupt (CRCERRI) bit in UESTAn, what triggers an EPnINT interrupt if the CRC Error Interrupt Enable (CRCERRE) bit is one.

A CRC error can occur during OUT stage if the USBB detects a corrupted received packet. The

OUT packet is stored in the bank as if no CRC error had occurred (RXOUTI is set).

22.7.2.17

Interrupts

See the structure of the USB device interrupt system on

Figure 22-6 on page 361 .

There are two kinds of device interrupts: processing, i.e. their generation is part of the normal processing, and exception, i.e. errors (not related to CPU exceptions).

•Global interrupts

The processing device global interrupts are:

• The Suspend (SUSP) interrupt

• The Start of Frame (SOF) interrupt with no frame number CRC error (the Frame Number

CRC Error (FNCERR) bit in the Device Frame Number (UDFNUM) register is zero)

• The End of Reset (EORST) interrupt

• The Wake-Up (WAKEUP) interrupt

• The End of Resume (EORSM) interrupt

378

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

• The Upstream Resume (UPRSM) interrupt

• The Endpoint n (EPnINT) interrupt

• The DMA Channel n (DMAnINT) interrupt

The exception device global interrupts are:

• The Start of Frame (SOF) interrupt with a frame number CRC error (FNCERR is one)

•Endpoint interrupts

The processing device endpoint interrupts are:

• The Transmitted IN Data Interrupt (TXINI)

• The Received OUT Data Interrupt (RXOUTI)

• The Received SETUP Interrupt (RXSTPI)

• The Short Packet (SHORTPACKET) interrupt

• The Number of Busy Banks (NBUSYBK) interrupt

The exception device endpoint interrupts are:

• The Underflow Interrupt (UNDERFI)

• The NAKed OUT Interrupt (NAKOUTI)

• The NAKed IN Interrupt (NAKINI)

• The Overflow Interrupt (OVERFI)

• The STALLed Interrupt (STALLEDI)

• The CRC Error Interrupt (CRCERRI)

•DMA interrupts

The processing device DMA interrupts are:

• The End of USB Transfer Status (EOTSTA) interrupt

• The End of Channel Buffer Status (EOCHBUFFSTA) interrupt

• The Descriptor Loaded Status (DESCLDSTA) interrupt

There is no exception device DMA interrupt.

379

AT32UC3B

22.7.3

22.7.3.1

USB Host Operation

Description of pipes

For the USBB in host mode, the term “pipe” is used instead of “endpoint” (used in device mode).

A host pipe corresponds to a device endpoint, as described by the Figure 22-22 on page 380

from the USB specification.

Figure 22-22. USB Communication Flow

22.7.3.2

In host mode, the USBB associates a pipe to a device endpoint, considering the device configuration descriptors.

Power-On and reset

Figure 22-23 on page 380

describes the USBB host mode main states.

Figure 22-23. Host Mode States

Macro off

Clock stopped

Device

Disconnection

<any other state>

Idle

Device

Connection

Device

Disconnection

Ready

SOFE = 0

SOFE = 1

Suspend

After a hardware reset, the USBB host mode is in the Reset state.

When the USBB is enabled (USBE is one) in host mode (ID is zero), its host mode state goes to the Idle state. In this state, the controller waits for device connection with minimal power con-

380

32059L–AVR32–01/2012

AT32UC3B

22.7.3.3

22.7.3.4

22.7.3.5

22.7.3.6

Device detection

A device is detected by the USBB host mode when D+ or D- is no longer tied low, i.e., when the device D+ or D- pull-up resistor is connected. To enable this detection, the host controller has to provide the VBus power supply to the device by setting the VBUSRQ bit (by writing a one to the

VBUSRQS bit).

The device disconnection is detected by the host controller when both D+ and D- are pulled down.

USB reset

sumption. The USB pad should be in the Idle state. Once a device is connected, the macro enters the Ready state, what does not require the USB clock to be activated.

The controller enters the Suspend state when the USB bus is in a “Suspend” state, i.e., when the host mode does not generate the “Start of Frame (SOF)”. In this state, the USB consumption is minimal. The host mode exits the Suspend state when starting to generate the SOF over the

USB line.

The USBB sends a USB bus reset when the user write a one to the Send USB Reset bit in the

Host General Control register (UHCON.RESET). The USB Reset Sent Interrupt bit in the Host

Global Interrupt register (UHINT.RSTI) is set when the USB reset has been sent. In this case, all the pipes are disabled and de-allocated.

If the bus was previously in a “Suspend” state (the Start of Frame Generation Enable (SOFE) bit in UHCON is zero), the USBB automatically switches it to the “Resume” state, the Host Wake-

Up Interrupt (HWUPI) bit in UHINT is set and the SOFE bit is set in order to generate SOFs immediately after the USB reset.

Pipe reset

A pipe can be reset at any time by writing a one to the Pipe n Reset (PRSTn) bit in the UPRST register. This is recommended before using a pipe upon hardware reset or when a USB bus reset has been sent. This resets:

• The internal state machine of this pipe

• The receive and transmit bank FIFO counters

• All the registers of this pipe (UPCFGn, UPSTAn, UPCONn), except its configuration (ALLOC,

PBK, PSIZE, PTOKEN, PTYPE, PEPNUM, INTFRQ in UPCFGn) and its Data Toggle

Sequence field in the Pipe n Status register (UPSTAn.DTSEQ).

The pipe configuration remains active and the pipe is still enabled.

The pipe reset may be associated with a clear of the data toggle sequence. This can be achieved by setting the Reset Data Toggle bit in the Pipe n Control register (UPCONn.RSTDT)

(by writing a one to the Reset Data Toggle Set bit in the Pipe n Control Set register

(UPCONnSET.RSTDTS)).

In the end, the user has to write a zero to the PRSTn bit to complete the reset operation and to start using the FIFO.

Pipe activation

The pipe is maintained inactive and reset (see

Section 22.7.3.5

for more details) as long as it is disabled (PENn is zero). The Data Toggle Sequence field (DTSEQ) is also reset.

381

32059L–AVR32–01/2012

AT32UC3B

The algorithm represented on Figure 22-24 on page 382

must be followed in order to activate a pipe.

Figure 22-24. Pipe Activation Algorithm

Pipe

Activation

PENn = 1

UPCFGn

INTFRQ

PEPNUM

PTYPE

PTOKEN

PSIZE

PBK

ALLOC

Enable the pipe.

Configure the pipe:

- interrupt request frequency

- endpoint number

- type

- size

- number of banks

Allocate the configured DPRAM banks.

CFGOK ==

1?

Yes

Pipe Activated

No

ERROR

Test if the pipe configuration is correct.

22.7.3.7

As long as the pipe is not correctly configured (UPSTAn.CFGOK is zero), the controller can not send packets to the device through this pipe.

The UPSTAn.CFGOK bit is set only if the configured size and number of banks are correct compared to their maximal allowed values for the pipe (see

Table 22-1 on page 352 ) and to the

maximal FIFO size (i.e. the DPRAM size).

See Section 22.7.1.6

for more details about DPRAM management.

Once the pipe is correctly configured (UPSTAn.CFGOK is zero), only the PTOKEN and INTFRQ fields can be written by software. INTFRQ is meaningless for non-interrupt pipes.

When starting an enumeration, the user gets the device descriptor by sending a

GET_DESCRIPTOR USB request. This descriptor contains the maximal packet size of the device default control endpoint (bMaxPacketSize0) and the user re-configures the size of the default control pipe with this size parameter.

Address setup

Once the device has answered the first host requests with the default device address 0, the host assigns a new address to the device. The host controller has to send an USB reset to the device and to send a SET_ADDRESS(addr) SETUP request with the new address to be used by the device. Once this SETUP transaction is over, the user writes the new address into the USB Host

Address for Pipe n field in the USB Host Device Address register (UHADDR.UHADDRPn). All following requests, on all pipes, will be performed using this new address.

When the host controller sends an USB reset, the UHADDRPn field is reset by hardware and the following host requests will be performed using the default device address 0.

382

32059L–AVR32–01/2012

AT32UC3B

22.7.3.8

Remote wake-up

The controller host mode enters the Suspend state when the UHCON.SOFE bit is written to zero. No more “Start of Frame” is sent on the USB bus and the USB device enters the Suspend state 3ms later.

The device awakes the host by sending an Upstream Resume (Remote Wake-Up feature).

When the host controller detects a non-idle state on the USB bus, it set the Host Wake-Up interrupt (HWUPI) bit in UHINT. If the non-idle bus state corresponds to an Upstream Resume (K state), the Upstream Resume Received Interrupt (RXRSMI) bit in UHINT is set. The user has to generate a Downstream Resume within 1ms and for at least 20ms by writing a one to the Send

USB Resume (RESUME) bit in UHCON. It is mandatory to write a one to UHCON.SOFE before writing a one to UHCON.RESUME to enter the Ready state, else UHCON.RESUME will have no effect.

22.7.3.9

Management of control pipes

A control transaction is composed of three stages:

• SETUP

• Data (IN or OUT)

• Status (OUT or IN)

The user has to change the pipe token according to each stage.

For the control pipe, and only for it, each token is assigned a specific initial data toggle sequence:

• SETUP: Data0

• IN: Data1

• OUT: Data1

22.7.3.10

Management of IN pipes

IN packets are sent by the USB device controller upon IN requests from the host. All the data can be read which acknowledges or not the bank when it is empty.

The pipe must be configured first.

When the host requires data from the device, the user has to select beforehand the IN request mode with the IN Request Mode bit in the Pipe n IN Request register (UPINRQn.INMODE):

• When INMODE is written to zero, the USBB will perform (INRQ + 1) IN requests before freezing the pipe.

• When INMODE is written to one, the USBB will perform IN requests endlessly when the pipe is not frozen by the user.

The generation of IN requests starts when the pipe is unfrozen (the Pipe Freeze (PFREEZE) field in UPCONn is zero).

The Received IN Data Interrupt (RXINI) bit in UPSTAn is set at the same time as the FIFO Control (FIFOCON) bit in UPCONn when the current bank is full. This triggers a PnINT interrupt if the

Received IN Data Interrupt Enable (RXINE) bit in UPCONn is one.

RXINI shall be cleared by software (by writing a one to the Received IN Data Interrupt Clear bit in the Pipe n Control Clear register(UPCONnCLR.RXINIC)) to acknowledge the interrupt, what has no effect on the pipe FIFO.

383

32059L–AVR32–01/2012

IN

DATA

(bank 0)

AT32UC3B

The user then reads from the FIFO (see ”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-

DATA)” on page 471 ) and clears the FIFOCON bit (by writing a one to the FIFO Control Clear

(FIFOCONC) bit in UPCONnCLR) to free the bank. If the IN pipe is composed of multiple banks, this also switches to the next bank. The RXINI and FIFOCON bits are updated in accordance with the status of the next bank.

RXINI shall always be cleared before clearing FIFOCON.

The Read/Write Allowed (RWALL) bit in UPSTAn is set when the current bank is not empty, i.e., the software can read further data from the FIFO.

Figure 22-25. Example of an IN Pipe with 1 Data Bank

ACK IN

DATA

(bank 0)

ACK

HW HW

SW SW RXINI

FIFOCON

RXINI read data from CPU

BANK 0

SW

Figure 22-26. Example of an IN Pipe with 2 Data Banks

IN

DATA

(bank 0)

ACK IN

DATA

(bank 1)

HW

SW

ACK

HW read data from CPU

BANK 0

SW

FIFOCON read data from CPU

BANK 0

SW read data from CPU

BANK 1

22.7.3.11

Management of OUT pipes

OUT packets are sent by the host. All the data can be written which acknowledges or not the bank when it is full.

The pipe must be configured and unfrozen first.

The Transmitted OUT Data Interrupt (TXOUTI) bit in UPSTAn is set at the same time as FIFO-

CON when the current bank is free. This triggers a PnINT interrupt if the Transmitted OUT Data

Interrupt Enable (TXOUTE) bit in UPCONn is one.

384

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

TXOUTI shall be cleared by software (by writing a one to the Transmitted OUT Data Interrupt

Clear (TXOUTIC) bit in UPCONnCLR) to acknowledge the interrupt, what has no effect on the pipe FIFO.

The user then writes into the FIFO (see

”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-

DATA)” on page 471 ) and clears the FIFOCON bit to allow the USBB to send the data. If the

OUT pipe is composed of multiple banks, this also switches to the next bank. The TXOUTI and

FIFOCON bits are updated in accordance with the status of the next bank.

TXOUTI shall always be cleared before clearing FIFOCON.

The UPSTAn.RWALL bit is set when the current bank is not full, i.e., the software can write further data into the FIFO.

Note that if the user decides to switch to the Suspend state (by writing a zero to the

UHCON.SOFE bit) while a bank is ready to be sent, the USBB automatically exits this state and the bank is sent.

Figure 22-27. Example of an OUT Pipe with one Data Bank

OUT

DATA

(bank 0)

ACK OUT

HW

TXOUTI SW SW

FIFOCON write data to CPU

BANK 0

SW write data to CPU

BANK 0

SW

Figure 22-28. Example of an OUT Pipe with two Data Banks and no Bank Switching Delay

TXOUTI SW

OUT

DATA

(bank 0)

ACK

HW

SW

OUT

DATA

(bank 1)

ACK

SW

FIFOCON write data to CPU

BANK 0

SW write data to CPU

BANK 1

SW write data to CPU

BANK0

385

AT32UC3B

Figure 22-29. Example of an OUT Pipe with two Data Banks and a Bank Switching Delay

OUT

DATA

(bank 0)

ACK OUT

DATA

(bank 1)

ACK

TXOUTI SW SW

HW

SW

FIFOCON write data to CPU

BANK 0

SW write data to CPU

BANK 1

SW write data to CPU

BANK0

22.7.3.12

CRC error

This error exists only for isochronous IN pipes. It set the CRC Error Interrupt (CRCERRI) bit, what triggers a PnINT interrupt if then the CRC Error Interrupt Enable (CRCERRE) bit in

UPCONn is one.

A CRC error can occur during IN stage if the USBB detects a corrupted received packet. The IN packet is stored in the bank as if no CRC error had occurred (RXINI is set).

22.7.3.13

Interrupts

See the structure of the USB host interrupt system on

Figure 22-6 on page 361 .

There are two kinds of host interrupts: processing, i.e. their generation is part of the normal processing, and exception, i.e. errors (not related to CPU exceptions).

•Global interrupts

The processing host global interrupts are:

• The Device Connection Interrupt (DCONNI)

• The Device Disconnection Interrupt (DDISCI)

• The USB Reset Sent Interrupt (RSTI)

• The Downstream Resume Sent Interrupt (RSMEDI)

• The Upstream Resume Received Interrupt (RXRSMI)

• The Host Start of Frame Interrupt (HSOFI)

• The Host Wake-Up Interrupt (HWUPI)

• The Pipe n Interrupt (PnINT)

• The DMA Channel n Interrupt (DMAnINT)

There is no exception host global interrupt.

•Pipe interrupts

The processing host pipe interrupts are:

• The Received IN Data Interrupt (RXINI)

386

32059L–AVR32–01/2012

32059L–AVR32–01/2012

• The Transmitted OUT Data Interrupt (TXOUTI)

• The Transmitted SETUP Interrupt (TXSTPI)

• The Short Packet Interrupt (SHORTPACKETI)

• The Number of Busy Banks (NBUSYBK) interrupt

The exception host pipe interrupts are:

• The Underflow Interrupt (UNDERFI)

• The Pipe Error Interrupt (PERRI)

• The NAKed Interrupt (NAKEDI)

• The Overflow Interrupt (OVERFI)

• The Received STALLed Interrupt (RXSTALLDI)

• The CRC Error Interrupt (CRCERRI)

•DMA interrupts

The processing host DMA interrupts are:

• The End of USB Transfer Status (EOTSTA) interrupt

• The End of Channel Buffer Status (EOCHBUFFSTA) interrupt

• The Descriptor Loaded Status (DESCLDSTA) interrupt

There is no exception host DMA interrupt.

AT32UC3B

387

AT32UC3B

22.7.4

22.7.4.1

USB DMA Operation

Introduction

USB packets of any length may be transferred when required by the USBB. These transfers always feature sequential addressing. These two characteristics mean that in case of high

USBB throughput, both HSB ports will benefit from “incrementing burst of unspecified length” since the average access latency of HSB slaves can then be reduced.

The DMA uses word “incrementing burst of unspecified length” of up to 256 beats for both data transfers and channel descriptor loading. A burst may last on the HSB busses for the duration of a whole USB packet transfer, unless otherwise broken by the HSB arbitration or the HSB 1kbyte boundary crossing.

Packet data HSB bursts may be locked on a DMA buffer basis for drastic overall HSB bus bandwidth performance boost with paged memories. This is because these memories row (or bank) changes, which are very clock-cycle consuming, will then likely not occur or occur once instead of dozens of times during a single big USB packet DMA transfer in case other HSB masters address the memory. This means up to 128 words single cycle unbroken HSB bursts for bulk pipes/endpoints and 256 words single cycle unbroken bursts for isochronous pipes/endpoints.

This maximal burst length is then controlled by the lowest programmed USB pipe/endpoint size

(PSIZE/EPSIZE) and the Channel Byte Length (CHBYTELENGTH) field in the Device DMA

Channel n Control (UDDMAnCONTROL) register.

The USBB average throughput may be up to nearly 12 Mbit/s. Its average access latency decreases as burst length increases due to the zero wait-state side effect of unchanged pipe/endpoint. Word access allows reducing the HSB bandwidth required for the USB by four compared to native byte access. If at least 0 wait-state word burst capability is also provided by the other DMA HSB bus slaves, each of both DMA HSB busses need less than 1.1% bandwidth allocation for full USB bandwidth usage at 33MHz, and less than 0.6% at 66MHz.

388

32059L–AVR32–01/2012

AT32UC3B

USB DMA Channel X Registers

(Current Transfer Descriptor)

Next Descriptor Address

HSB Address

Control

Status

Figure 22-30. Example of DMA Chained List

Transfer Descriptor

Next Descriptor Address

HSB Address

Control

Transfer Descriptor

Next Descriptor Address

HSB Address

Control

Transfer Descriptor

Next Descriptor Address

HSB Address

Control

NULL

Memory Area

Data Buffer 1

Data Buffer 2

Data Buffer 3

22.7.4.2

22.7.4.3

DMA Channel descriptor

The DMA channel transfer descriptor is loaded from the memory.

Be careful with the alignment of this buffer.

The structure of the DMA channel transfer descriptor is defined by three parameters as described below:

• Offset 0:

– The address must be aligned: 0xXXXX0

– DMA Channel n Next Descriptor Address Register: DMAnNXTDESCADDR

• Offset 4:

– The address must be aligned: 0xXXXX4

– DMA Channel n HSB Address Register: DMAnADDR

• Offset 8:

– The address must be aligned: 0xXXXX8

– DMA Channel n Control Register: DMAnCONTROL

Programming a chanel:

Each DMA transfer is unidirectionnal. Direction depends on the type of the associated endpoint

(IN or OUT).

Three registers, the UDDMAnNEXTDESC, the UDDMAnADDR and UDDMAnCONTROL need to be programmed to set up wether single or multiple transfer is used.

The following example refers to OUT endpoint. For IN endpoint, the programming is symmetric.

389

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

•Single-block transfer programming example for OUT transfer :

The following sequence may be used:

• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching for this endpoint in the UECFGn register to handle multiple OUT packet.

• Write the starting destination address in the UDDMAnADDR register.

• There is no need to program the UDDMAnNEXTDESC register.

• Program the channel byte length in the UDDMAnCONTROL register.

• Program the UDDMAnCONTROL according to Row 2 as shown in Figure 22-6 on page 439

to set up a single block transfer.

The UDDMAnSTATUS.CHEN bit is set indicating that the dma channel is enable.

As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit is set to one, indicating that the DMA channel is transfering data from the endpoint to the destination address until the endpoint is empty or the channel byte length is reached. Once the endpoint is empty, the UDDMAnSTATUS.CHACTIVE bit is cleared.

Once the DMA channel is completed (i.e : the channel byte length is reached), after one or multiple processed OUT packet, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence, the UDDMAnSTATUS.CHEN bit is also cleared, and the UDDMAnSTATUS.EOCHBUFFSTA bit is set indicating a end of dma channel. If the UDDMAnCONTROL.DMAENDEN bit was set, the last endpoint bank will be properly released even if there are some residual datas inside, i.e:

OUT packet truncation at the end of DMA buffer when the dma channel byte lenght is not an integral multiple of the endpoint size.

•Programming example for single-block dma transfer with automatic closure for OUT transfer :

The idea is to automatically close the DMA transfer at the end of the OUT transaction (received short packet). The following sequence may be used:

• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching for this endpoint in the UECFGn register to handle multiple OUT packet.

• Write the starting destination address in the UDDMAnADDR register.

• There is no need to program the UDDMAnNEXTDESC register.

• Program the channel byte length in the UDDMAnCONTROL register.

• Set the BUFFCLOSEINEN bit in the UDDMAnCONTROL register.

• Program the UDDMAnCONTROL according to Row 2 as shown in Figure 22-6 on page 439

to set up a single block transfer.

As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit is set to one, indicating that the DMA channel is transfering data from the endpoint to the destin a t i o n a d d r e s s u n t i l t h e e n d p o i n t i s e m p t y . O n c e t h e e n d p o i n t i s e m p t y , t h e

UDDMAnSTATUS.CHACTIVE bit is cleared.

After one or multiple processed OUT packet, the DMA channel is completed after sourcing a short packet. Then, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared, and the UDDMAnSTA-

TUS.EOTSTA bit is set indicating that the DMA was closed by a end of USB transaction.

390

32059L–AVR32–01/2012

AT32UC3B

•Programming example for multi-block dma transfer : run and link at end of buffer

The idea is to run first a single block transfer followed automatically by a linked list of DMA. The following sequence may be used:

• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching for this endpoint in the UECFGn register to handle multiple OUT packet.

• Set up the chain of linked list of descripor in memory. Each descriptor is composed of 3 items

: channel next descriptor address, channel destination address and channel control. The last

descriptor should be programmed according to row 2 as shown in Figure 22-6 on page 439 .

• Write the starting destination address in the UDDMAnADDR register.

• Program the UDDMAnNEXTDESC register.

• Program the channel byte length in the UDDMAnCONTROL register.

• Optionnaly set the BUFFCLOSEINEN bit in the UDDMAnCONTROL register.

• Program the UDDMAnCONTROL according to Row 4 as shown in Figure 22-6 on page 439 .

The UDDMAnSTATUS.CHEN bit is set indicating that the dma channel is enable.

As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit is set to one, indicating that the DMA channel is transfering data from the endpoint to the destination address until the endpoint is empty or the channel byte length is reached. Once the endpoint is empty, the UDDMAnSTATUS.CHACTIVE bit is cleared.

Once the first DMA channel is completed (i.e : the channel byte length is reached), after one or multiple processed OUT packet, the UDDMAnCONTROL.CHEN bit is cleared. As a conseq u e n c e , t h e U D D M A n S T A T U S . C H E N b i t i s a l s o c l e a r e d , a n d t h e

UDDMAnSTATUS.EOCHBUFFSTA bit is set indicating a end of dma channel. If the UDDMAn-

CONTROL.DMAENDEN bit was set, the last endpoint bank will be properly released even if there are some residual datas inside, i.e: OUT packet truncation at the end of DMA buffer when the dma channel byte lenght is not an integral multiple of the endpoint size. Note that the

UDDMAnCONTROL.LDNXTCH bit remains to one indicating that a linked descriptor will be loaded.

Once the new descriptor is loaded from the UDDMAnNEXTDESC memory address, the UDDM-

AnSTATUS.DESCLDSTA bit is set, and the UDDMAnCONTROL register is updated from the memory. As a consequence, the UDDMAnSTATUS.CHEN bit is set, and the UDDMAnSTA-

TUS.CHACTIVE is set as soon as the endpoint is ready to be sourced by the DMA (received

OUT data packet).

This sequence is repeated until a last linked descriptor is processed. The last descriptor is

detected according to row 2 as shown in Figure 22-6 on page 439

.

At the end of the last descriptor, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared.

•Programming example for multi-block dma transfer : load next descriptor now

The idea is to directly run first a linked list of DMA. The following sequence may be used: The following sequence may be used:

• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching for this endpoint in the UECFGn register to handle multiple OUT packet.

391

32059L–AVR32–01/2012

AT32UC3B

• Set up the chain of linked list of descripor in memory. Each descriptor is composed of 3 items

: channel next descriptor address, channel destination address and channel control. The last

descriptor should be programmed according to row 2 as shown in Figure 22-6 on page 439 .

• Program the UDDMAnNEXTDESC register.

• Program the UDDMAnCONTROL according to Row 3 as shown in Figure 22-6 on page 439 .

The UDDMAnSTATUS.CHEN bit is 0 and the UDDMAnSTATUS.LDNXTCHDESCEN is set indicating that the DMA channel is pending until the endpoint is ready (received OUT packet).

As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit is set to one. Then after a few cycle latency, the new descriptor is loaded from the memory and the UDDMAnSTATUS.DESCLDSTA is set.

At the end of this DMA (for instance when the channel byte length has reached 0), the

UDDMAnCONTROL.CHEN bit is cleared, and then the UDDMAnSTATUS.CHEN bit is also cleared. If the UDDMAnCONTROL.LDNXTCH value is one, a new descriptor is loaded.

This sequence is repeated until a last linked descriptor is processed. The last descriptor is

detected according to row 2 as shown in Figure 22-6 on page 439

.

At the end of the last descriptor, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared.

392

22.8 User Interface

Table 22-4.

USBB Register Memory Map

0x0160

0x0164

0x0168

0x016C

0x0170

0x0174

0x0178

0x017C

0x0118

0x0130

0x0134

0x0138

0x013C

0x0140

0x0144

0x0148

0x0190

0x0194

0x0198

0x019C

0x001C

0x0020

0x0100

0x0104

0x0108

0x010C

0x0110

0x0114

Offset

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

Register

Device General Control Register

Device Global Interrupt Register

Device Global Interrupt Clear Register

Device Global Interrupt Set Register

Device Global Interrupt Enable Register

Device Global Interrupt Enable Clear Register

Device Global Interrupt Enable Set Register

Endpoint Enable/Reset Register

Device Frame Number Register

Endpoint 0 Configuration Register

Endpoint 1 Configuration Register

Endpoint 2 Configuration Register

Endpoint 3 Configuration Register

Endpoint 4 Configuration Register

Endpoint 5 Configuration Register

Endpoint 6 Configuration Register

Endpoint 0 Status Register

Endpoint 1 Status Register

Endpoint 2 Status Register

Endpoint 3 Status Register

Endpoint 4 Status Register

Endpoint 5 Status Register

Endpoint 6 Status Register

Endpoint 0 Status Clear Register

Endpoint 1 Status Clear Register

Endpoint 2 Status Clear Register

Endpoint 3 Status Clear Register

Endpoint 4 Status Clear Register

Endpoint 5 Status Clear Register

Endpoint 6 Status Clear Register

Endpoint 7 Status Clear Register

Endpoint 0 Status Set Register

Endpoint 1 Status Set Register

Endpoint 2 Status Set Register

Endpoint 3 Status Set Register

UECFG6

UESTA0

UESTA1

UESTA2

UESTA3

UESTA4

UESTA5

UESTA6

UESTA0CLR

UESTA1CLR

UESTA2CLR

UESTA3CLR

UESTA4CLR

UESTA5CLR

UESTA6CLR

UESTA7CLR

UESTA0SET

UESTA1SET

UESTA2SET

UESTA3SET

Name

UDCON

UDINT

UDINTCLR

UDINTSET

UDINTE

UDINTECLR

UDINTESET

UERST

UDFNUM

UECFG0

UECFG1

UECFG2

UECFG3

UECFG4

UECFG5

32059L–AVR32–01/2012

Read/Write

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Access

Read/Write

Read-Only

Write-Only

Write-Only

Read-Only

Write-Only

Write-Only

Read/Write

Read-Only

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

AT32UC3B

0x00002000

0x00000100

0x00000100

0x00000100

0x00000100

0x00000100

0x00000100

0x00000100

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

Reset Value

0x00000100

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00002000

0x00002000

0x00002000

0x00002000

0x00002000

0x00002000

393

Table 22-4.

USBB Register Memory Map

0x0224

0x0228

0x022C

0x0230

0x0234

0x0238

0x023C

0x01F4

0x01F8

0x01FC

0x0200

0x0204

0x0208

0x020C

0x0220

Offset

0x01A0

0x01A4

0x01A8

0x01AC

0x01C0

0x01C4

0x01C8

0x01CC

0x01D0

0x01D4

0x01D8

0x01DC

0x01F0

0x0310

Register

Endpoint 4 Status Set Register

Endpoint 5 Status Set Register

Endpoint 6 Status Set Register

Endpoint 7 Status Set Register

Endpoint 0 Control Register

Endpoint 1 Control Register

Endpoint 2 Control Register

Endpoint 3 Control Register

Endpoint 4 Control Register

Endpoint 5 Control Register

Endpoint 6 Control Register

Endpoint 7 Control Register

Endpoint 0 Control Set Register

Endpoint 1 Control Set Register

Endpoint 2 Control Set Register

Endpoint 3 Control Set Register

Endpoint 4 Control Set Register

Endpoint 5 Control Set Register

Endpoint 6 Control Set Register

Endpoint 7 Control Set Register

Endpoint 0 Control Clear Register

Endpoint 1 Control Clear Register

Endpoint 2 Control Clear Register

Endpoint 3 Control Clear Register

Endpoint 4 Control Clear Register

Endpoint 5 Control Clear Register

Endpoint 6 Control Clear Register

Endpoint 7 Control Clear Register

Device DMA Channel 1 Next Descriptor

Address Register

0x0314 Device DMA Channel 1 HSB Address Register

0x0318

0x031C

0x0320

Device DMA Channel 1 Control Register

Device DMA Channel 1 Status Register

Device DMA Channel 2 Next Descriptor

Address Register

UECON1SET

UECON2SET

UECON3SET

UECON4SET

UECON5SET

UECON6SET

UECON7SET

UECON0CLR

UECON1CLR

UECON2CLR

UECON3CLR

UECON4CLR

UECON5CLR

UECON6CLR

UECON7CLR

UDDMA1

NEXTDESC

UDDMA1

ADDR

UDDMA1

CONTROL

UDDMA1

STATUS

UDDMA2

NEXTDESC

Name

UESTA4SET

UESTA5SET

UESTA6SET

UESTA7SET

UECON0

UECON1

UECON2

UECON3

UECON4

UECON5

UECON6

UECON7

UECON0SET

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Access

Write-Only

Write-Only

Write-Only

Write-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Write-Only

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

AT32UC3B

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

Reset Value

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

394

32059L–AVR32–01/2012

AT32UC3B

0x034C

0x0350

0x0354

0x0358

0x035C

0x0360

0x0364

0x0368

0x036C

0x0400

0x0404

0x0408

0x040C

0x0410

Table 22-4.

USBB Register Memory Map

Offset Register

0x0324 Device DMA Channel 2 HSB Address Register

0x0328

0x032C

0x0330

0x0334

0x0338

0x033C

0x0340

0x0344

0x0348

Device DMA Channel 2 Control Register

Device DMA Channel 2 Status Register

Device DMA Channel 3 Next Descriptor

Address Register

Device DMA Channel 3 HSB Address Register

Device DMA Channel 3 Control Register

Device DMA Channel 3 Status Register

Device DMA Channel 4 Next Descriptor

Address Register

Device DMA Channel 4 HSB Address Register

Device DMA Channel 4 Control Register

Device DMA Channel 4 Status Register

Device DMA Channel 5 Next Descriptor

Address Register

Device DMA Channel 5 HSB Address Register

Device DMA Channel 5 Control Register

Device DMA Channel 5 Status Register

Device DMA Channel 6 Next Descriptor

Address Register

Device DMA Channel 6 HSB Address Register

Device DMA Channel 6 Control Register

Device DMA Channel 6 Status Register

Host General Control Register

Host Global Interrupt Register

Host Global Interrupt Clear Register

Host Global Interrupt Set Register

Host Global Interrupt Enable Register

UDDMA4

NEXTDESC

UDDMA4

ADDR

UDDMA4

CONTROL

UDDMA4

STATUS

UDDMA5

NEXTDESC

UDDMA5

ADDR

UDDMA5

CONTROL

UDDMA5

STATUS

Name

UDDMA2

ADDR

UDDMA2

CONTROL

UDDMA2

STATUS

UDDMA3

NEXTDESC

UDDMA3

ADDR

UDDMA3

CONTROL

UDDMA3

STATUS

UDDMA6

NEXTDESC

UDDMA6

ADDR

UDDMA6

CONTROL

UDDMA6

STATUS

UHCON

UHINT

UHINTCLR

UHINTSET

UHINTE

32059L–AVR32–01/2012

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

Reset Value

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

395

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read-Only

Write-Only

Write-Only

Read-Only

Access

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Table 22-4.

USBB Register Memory Map

0x0564

0x0568

0x056C

0x0570

0x0574

0x0578

0x0590

0x0594

0x0530

0x0534

0x0538

0x053C

0x0540

0x0544

0x0548

0x0560

0x0598

0x059C

0x05A0

0x05A4

0x05A8

0x05C0

0x05C4

Offset

0x0414

0x0418

0x0041C

0x0420

0x0424

0x0428

0x0500

0x0504

0x0508

0x050C

0x0510

0x0514

0x0518

Register

Host Global Interrupt Enable Clear Register

Host Global Interrupt Enable Set Register

Pipe Enable/Reset Register

Host Frame Number Register

Host Address 1 Register

Host Address 2 Register

Pipe 0 Configuration Register

Pipe 1 Configuration Register

Pipe 2 Configuration Register

Pipe 3 Configuration Register

Pipe 4 Configuration Register

Pipe 5 Configuration Register

Pipe 6 Configuration Register

Pipe 0 Status Register

Pipe 1 Status Register

Pipe 2 Status Register

Pipe 3 Status Register

Pipe 4 Status Register

Pipe 5 Status Register

Pipe 6 Status Register

Pipe 0 Status Clear Register

Pipe 1 Status Clear Register

Pipe 2 Status Clear Register

Pipe 3 Status Clear Register

Pipe 4 Status Clear Register

Pipe 5 Status Clear Register

Pipe 6 Status Clear Register

Pipe 0 Status Set Register

Pipe 1 Status Set Register

Pipe 2 Status Set Register

Pipe 3 Status Set Register

Pipe 4 Status Set Register

Pipe 5 Status Set Register

Pipe 6 Status Set Register

Pipe 0 Control Register

Pipe 1 Control Register

UPSTA0

UPSTA1

UPSTA2

UPSTA3

UPSTA4

UPSTA5

UPSTA6

UPSTA0CLR

UPSTA1CLR

UPSTA2CLR

UPSTA3CLR

UPSTA4CLR

UPSTA5CLR

UPSTA6CLR

UPSTA0SET

UPSTA1SET

Name

UHINTECLR

UHINTESET

UPRST

UHFNUM

UHADDR1

UHADDR2

UPCFG0

UPCFG1

UPCFG2

UPCFG3

UPCFG4

UPCFG5

UPCFG6

UPSTA2SET

UPSTA3SET

UPSTA4SET

UPSTA5SET

UPSTA6SET

UPCON0

UPCON1

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Access

Write-Only

Write-Only

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Read-Only

Read-Only

AT32UC3B

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

Reset Value

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

396

32059L–AVR32–01/2012

Table 22-4.

USBB Register Memory Map

0x0654

0x0658

0x065C

0x0660

0x0664

0x0668

0x0680

0x0684

0x0620

0x0624

0x0628

0x062C

0x0630

0x0634

0x0638

0x0650

0x0688

0x068C

0x0690

0x0694

0x0698

Offset

0x05C8

0x05CC

0x05D0

0x05D4

0x05D8

0x05DC

0x05F0

0x05F4

0x05F8

0x05FC

0x0600

0x0604

0x0608

0x0710

Register

Pipe 2 Control Register

Pipe 3 Control Register

Pipe 4 Control Register

Pipe 5 Control Register

Pipe 6 Control Register

Pipe 7 Control Register

Pipe 0 Control Set Register

Pipe 1 Control Set Register

Pipe 2 Control Set Register

Pipe 3 Control Set Register

Pipe 4 Control Set Register

Pipe 5 Control Set Register

Pipe 6 Control Set Register

Pipe 0 Control Clear Register

Pipe 1 Control Clear Register

Pipe 2 Control Clear Register

Pipe 3 Control Clear Register

Pipe 4 Control Clear Register

Pipe 5 Control Clear Register

Pipe 6 Control Clear Register

Pipe 0 IN Request Register

Pipe 1 IN Request Register

Pipe 2 IN Request Register

Pipe 3 IN Request Register

Pipe 4 IN Request Register

Pipe 5 IN Request Register

Pipe 6 IN Request Register

Pipe 0 Error Register

Pipe 1 Error Register

Pipe 2 Error Register

Pipe 3 Error Register

Pipe 4 Error Register

Pipe 5 Error Register

Pipe 6 Error Register

Host DMA Channel 1 Next Descriptor Address

Register

UPCON0CLR

UPCON1CLR

UPCON2CLR

UPCON3CLR

UPCON4CLR

UPCON5CLR

UPCON6CLR

UPINRQ0

UPINRQ1

UPINRQ2

UPINRQ3

UPINRQ4

UPINRQ5

UPINRQ6

UPERR0

UPERR1

Name

UPCON2

UPCON3

UPCON4

UPCON5

UPCON6

UPCON7

UPCON0SET

UPCON1SET

UPCON2SET

UPCON3SET

UPCON4SET

UPCON5SET

UPCON6SET

UPERR2

UPERR3

UPERR4

UPERR5

UPERR6

UHDMA1

NEXTDESC

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Access

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Write-Only

Read/Write

AT32UC3B

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

Reset Value

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

397

32059L–AVR32–01/2012

0x0754

0x0758

0x075C

0x0760

0x0764

0x0768

0x073C

0x0740

0x0744

0x0748

0x074C

0x0750

Table 22-4.

USBB Register Memory Map

Offset Register

0x0714 Host DMA Channel 1 HSB Address Register

0x0718

0x071C

0x0720

0x0724

0x0728

0x072C

0x0730

0x0734

0x0738

Host DMA Channel 1 Control Register

Host DMA Channel 1 Status Register

Host DMA Channel 2 Next Descriptor Address

Register

Host DMA Channel 2 HSB Address Register

Host DMA Channel 2 Control Register

Host DMA Channel 2 Status Register

Host DMA Channel 3 Next Descriptor Address

Register

Host DMA Channel 3 HSB Address Register

Host DMA Channel 3 Control Register

Host DMA Channel 3Status Register

Host DMA Channel 4 Next Descriptor Address

Register

Host DMA Channel 4 HSB Address Register

Host DMA Channel 4 Control Register

Host DMA Channel 4 Status Register

Host DMA Channel 5 Next Descriptor Address

Register

Host DMA Channel 5 HSB Address Register

Host DMA Channel 5 Control Register

Host DMA Channel 5 Status Register

Host DMA Channel 6 Next Descriptor Address

Register

Host DMA Channel 6 HSB Address Register

Host DMA Channel 6 Control Register

UHDMA3

NEXTDESC

UHDMA3

ADDR

UHDMA3

CONTROL

UHDMA3

STATUS

UHDMA4

NEXTDESC

UHDMA4

ADDR

UHDMA4

CONTROL

UHDMA4

STATUS

Name

UHDMA1

ADDR

UHDMA1

CONTROL

UHDMA1

STATUS

UHDMA2

NEXTDESC

UHDMA2

ADDR

UHDMA2

CONTROL

UHDMA2

STATUS

UHDMA5

NEXTDESC

UHDMA5

ADDR

UHDMA5

CONTROL

UHDMA5

STATUS

UHDMA6

NEXTDESC

UHDMA6

ADDR

UHDMA6

CONTROL

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Access

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

AT32UC3B

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

Reset Value

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

398

32059L–AVR32–01/2012

AT32UC3B

Table 22-4.

USBB Register Memory Map

Offset Register

0x076C Host DMA Channel 6 Status Register

0x0800

0x0804

0x0808

0x080C

0x0818

0x081C

0x0820

0x0824

0x0828

0x082C

Offset

0x00000 -

0x0FFFC

0x10000 -

0x1FFFC

0x20000 -

0x2FFFC

0x30000 -

0x3FFFC

0x40000 -

0x4FFFC

0x50000 -

0x5FFFC

0x60000 -

0x6FFFC

General Control Register

General Status Register

General Status Clear Register

General Status Set Register

IP Version Register

IP Features Register

IP PB Address Size Register

IP Name Register 1

IP Name Register 2

USB Finite State Machine Status Register

Table 22-5.

USB HSB Memory Map

Register

Pipe/Endpoint 0 FIFO Data Register

Pipe/Endpoint 1 FIFO Data Register

Pipe/Endpoint 2 FIFO Data Register

Pipe/Endpoint 3 FIFO Data Register

Pipe/Endpoint 4 FIFO Data Register

Pipe/Endpoint 5 FIFO Data Register

Pipe/Endpoint 6 FIFO Data Register

Name

UHDMA6

STATUS

USBCON

USBSTA

USBSTACLR

USBSTASET

UVERS

UFEATURES

UADDRSIZE

UNAME1

UNAME2

USBFSM

Name

USB

FIFO0DATA

USB

FIFO1DATA

USB

FIFO2DATA

USB

FIFO3DATA

USB

FIFO4DATA

USB

FIFO5DATA

USB

FIFO6DATA

Access

Read/Write

Read/Write

Read-Only

Write-Only

Write-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Access

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Reset Value

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.

Reset Value

0x00000000

0x03004000

0x00000400

0x00000000

0x00000000

-

(1)

-

(1)

-

(1)

-

(1)

-

(1)

0x00000009

399

32059L–AVR32–01/2012

AT32UC3B

22.8.1

USB General Registers

22.8.1.1

Name:

Access Type:

Offset:

Reset Value:

General Control Register

USBCON

Read/Write

0x0800

0x03004000

31

-

23

-

30

-

22

UNLOCK

29

-

28

-

21

TIMPAGE

20

13

VBUSPO

12

OTGPADE

27

-

19

-

11

26

-

18

-

10

25

UIMOD

17

TIMVALUE

16

9

24

UIDE

8

VBUSHWC

15

USBE

14

FRZCLK

7

STOE

6 5

ROLEEXE

4

BCERRE

3

VBERRE

2 1

VBUSTE

0

IDTE

• UIMOD: USBB Mode

This bit has no effect when UIDE is one (USB_ID input pin activated).

0: The module is in USB host mode.

1: The module is in USB device mode.

This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit.

• UIDE: USB_ID Pin Enable

0: The USB mode (device/host) is selected from the UIMOD bit.

1: The USB mode (device/host) is selected from the USB_ID input pin.

This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit.

• UNLOCK: Timer Access Unlock

1: The TIMPAGE and TIMVALUE fields are unlocked.

0: The TIMPAGE and TIMVALUE fields are locked.

The TIMPAGE and TIMVALUE fields can always be read, whatever the value of UNLOCK.

• TIMPAGE: Timer Page

This field contains the page value to access a special timer register.

• TIMVALUE: Timer Value

This field selects the timer value that is written to the special time register selected by TIMPAGE. See

Section 22.7.1.8

for

details.

• USBE: USBB Enable

Writing a zero to this bit will reset the USBB, disable the USB transceiver and, disable the USBB clock inputs. Unless explicitly stated, all registers then will become read-only and will be reset.

1: The USBB is enabled.

0: The USBB is disabled.

400

32059L–AVR32–01/2012

AT32UC3B

This bit can be written even if FRZCLK is one.

• FRZCLK: Freeze USB Clock

1: The clock input are disabled (the resume detection is still active).This reduces power consumption. Unless explicitly stated, all registers then become read-only.

0: The clock inputs are enabled.

This bit can be written even if USBE is zero. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit, but this freezes the clock inputs whatever its value.

• VBUSPO: VBus Polarity

1: The USB_VBOF output signal is inverted (active low).

0: The USB_VBOF output signal is in its default mode (active high).

To be generic. May be useful to control an external VBus power module.

This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit.

• OTGPADE: OTG Pad Enable

1: The OTG pad is enabled.

0: The OTG pad is disabled.

This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit.

• VBUSHWC: VBus Hardware Control

1: The hardware control over the USB_VBOF output pin is disabled.

0: The hardware control over the USB_VBOF output pin is enabled. The USBB resets the USB_VBOF output pin when a VBUS problem occurs.

• STOE: Suspend Time-Out Interrupt Enable

1: The Suspend Time-Out Interrupt (STOI) is enabled.

0: The Suspend Time-Out Interrupt (STOI) is disabled.

• ROLEEXE: Role Exchange Interrupt Enable

1: The Role Exchange Interrupt (ROLEEXI) is enabled.

0: The Role Exchange Interrupt (ROLEEXI) is disabled.

• BCERRE: B-Connection Error Interrupt Enable

1: The B-Connection Error Interrupt (BCERRI) is enabled.

0: The B-Connection Error Interrupt (BCERRI) is disabled.

• VBERRE: VBus Error Interrupt Enable

1: The VBus Error Interrupt (VBERRI) is enabled.

0: The VBus Error Interrupt (VBERRI) is disabled.

• VBUSTE: VBus Transition Interrupt Enable

1: The VBus Transition Interrupt (VBUSTI) is enabled.

0: The VBus Transition Interrupt (VBUSTI) is disabled.

• IDTE: ID Transition Interrupt Enable

1: The ID Transition interrupt (IDTI) is enabled.

0: The ID Transition interrupt (IDTI) is disabled.

401

32059L–AVR32–01/2012

AT32UC3B

22.8.1.2

General Status Register

Register Name:

USBSTA

Access Type:

Offset:

Reset Value:

Read-Only

0x0804

0x00000400

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

25

-

17

-

24

-

16

-

15

-

14

-

13

SPEED

12 11

VBUS

10

ID

9

VBUSRQ

8

-

7

STOI

6 5

ROLEEXI

4

BCERRI

• SPEED: Speed Status

This field is set according to the controller speed mode..

3

VBERRI

2 1

VBUSTI

0

IDTI

0

1

X

SPEED

0

0

1

Speed Status

Full-Speed mode

Low-Speed mode

Reserved

• VBUS: VBus Level

This bit is set when the VBus line level is high.

This bit is cleared when the VBus line level is low.

This bit can be used in either device or host mode to monitor the USB bus connection state of the application.

• ID: USB_ID Pin State

This bit is cleared when the USB_ID level is low, even if USBE is zero.

This bit is set when the USB_ID level is high, event if USBE is zero.

• VBUSRQ: VBus Request

This bit is set when the USBSTASET.VBUSRQS bit is written to one.

This bit is cleared when the USBSTACLR.VBUSRQC bit is written to one or when a VBus error occurs and VBUSHWC is zero.

1: The USB_VBOF output pin is driven high to enable the VBUS power supply generation.

0: The USB_VBOF output pin is driven low to disable the VBUS power supply generation.

This bit shall only be used in host mode.

• STOI: Suspend Time-Out Interrupt

This bit is set when a time-out error (more than 200ms) has been detected after a suspend. This triggers a USB interrupt if

STOE is one.

This bit is cleared when the UBSTACLR.STOIC bit is written to one.

This bit shall only be used in host mode.

402

32059L–AVR32–01/2012

AT32UC3B

• ROLEEXI: Role Exchange Interrupt

This bit is set when the USBB has successfully switched its mode because of an negotiation (host to device or device to host).

This triggers a USB interrupt if ROLEEXE is one.

This bit is cleared when the UBSTACLR.ROLEEXIC bit is written to one.

• BCERRI: B-Connection Error Interrupt

This bit is set when an error occurs during the B-connection. This triggers a USB interrupt if BCERRE is one.

This bit is cleared when the UBSTACLR.BCERRIC bit is written to one.

This bit shall only be used in host mode.

• VBERRI: VBus Error Interrupt

This bit is set when a VBus drop has been detected. This triggers a USB interrupt if VBERRE is one.

This bit is cleared when the UBSTACLR.VBERRIC bit is written to one.

This bit shall only be used in host mode.

If a VBus problem occurs, then the VBERRI interrupt is generated even if the USBB does not go to an error state because of

VBUSHWC is one.

• VBUSTI: VBus Transition Interrupt

This bit is set when a transition (high to low, low to high) has been detected on the USB_VBUS pad. This triggers an USB interrupt if VBUSTE is one.

This bit is cleared when the UBSTACLR.VBUSTIC bit is written to one.

This interrupt is generated even if the clock is frozen by the FRZCLK bit.

• IDTI: ID Transition Interrupt

This bit is set when a transition (high to low, low to high) has been detected on the USB_ID input pin. This triggers an USB interrupt if IDTE is one.

This bit is cleared when the UBSTACLR.IDTIC bit is written to one.

This interrupt is generated even if the clock is frozen by the FRZCLK bit or pad is disable by USBCON.OTGPADE or the USBB module is disabled by USBCON.USBE.

403

32059L–AVR32–01/2012

AT32UC3B

22.8.1.3

General Status Clear Register

Register Name:

USBSTACLR

Access Type:

Offset:

Read Value:

Write-Only

0x0808

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

-

7

STOIC

6 5

ROLEEXIC

4

BCERRIC

3

VBERRIC

Writing a one to a bit in this register will clear the corresponding bit in UBSTA.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

2

10

-

26

-

18

-

25

-

17

-

9

VBUSRQC

1

VBUSTIC

8

-

0

IDTIC

24

-

16

-

404

32059L–AVR32–01/2012

AT32UC3B

22.8.1.4

General Status Set Register

Register Name:

USBSTASET

Access Type:

Offset:

Read Value:

Write-Only

0x080C

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

25

-

17

-

24

-

16

-

15

-

14

-

13

-

12

-

11

-

10

-

9

VBUSRQS

8

-

7

STOIS

6 5

ROLEEXIS

4

BCERRIS

3

VBERRIS

2 1

VBUSTIS

0

IDTIS

Writing a one to a bit in this register will set the corresponding bit in UBSTA, what may be useful for test or debug purposes.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

405

32059L–AVR32–01/2012

AT32UC3B

22.8.1.5

Version Register

Register Name:

UVERS

Access Type:

Offset:

Read Value:

-

Read-Only

0x0818

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

15

-

14

-

13

-

12

-

11

7 6 5 4

VERSION[7:0]

3

• VARIANT: Variant Number

Reserved. No functionality associated.

• VERSION: Version Number

Version number of the module. No functionality associated.

27

-

19

26

-

25

-

18

VARIANT

17

10

VERSION[11:8]

9

2 1

8

0

24

-

16

406

32059L–AVR32–01/2012

22.8.1.6

Features Register

Register Name:

UFEATURES

Access Type:

Offset:

Read Value:

-

Read-Only

0x081C

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

15

BYTEWRITE

DPRAM

14 13

FIFOMAXSIZE

12 11 10 9

DMAFIFOWORDDEPTH

1

1

0

1

1

0

0

0

7

DMABUFFE

RSIZE

6 5

DMACHANNELNBR

4 3 2

EPTNBRMAX

• BYTEWRITEDPRAM: DPRAM Byte-Write Capability

1: The DPRAM is natively byte-write capable.

0: The DPRAM byte write lanes have shadow logic implemented in the USBB IP interface.

• FIFOMAXSIZE: Maximal FIFO Size

This field indicates the maximal FIFO size, i.e., the DPRAM size:

1

FIFOMAXSIZE

0

0

1

0

1

1

0

1

0

1

0

1

0

1

0

1

Maximal FIFO Size

< 256 bytes

< 512 bytes

< 1024 bytes

< 2048 bytes

< 4096 bytes

< 8192 bytes

< 16384 bytes

>= 16384 bytes

25

-

17

-

AT32UC3B

24

-

16

-

8

0

407

32059L–AVR32–01/2012

• DMAFIFOWORDDEPTH: DMA FIFO Depth in Words

This field indicates the DMA FIFO depth controller in words:

0

0

0

1

DMAFIFOWORDDEPTH

0

0

0

1

0

0

1

1

0

1

0

1

1

2

DMA FIFO Depth in Words

16

...

15

• DMABUFFERSIZE: DMA Buffer Size

1: The DMA buffer size is 24bits.

0: The DMA buffer size is 16bits.

• DMACHANNELNBR: Number of DMA Channels

This field indicates the number of hardware-implemented DMA channels:

0

0

0

DMACHANNELNBR

0

0

1

0

1

0 2

...

7

Number of DMA Channels

Reserved

1

1 1 1

• EPTNBRMAX: Maximal Number of Pipes/Endpoints

This field indicates the number of hardware-implemented pipes/endpoints:

0

0

0

1

EPTNBRMAX

0

0

0

0

0

1

1 1

0

1

0

1

2

...

15

Maximal Number of Pipes/Endpoints

16

1

AT32UC3B

408

32059L–AVR32–01/2012

22.8.1.7

Address Size Register

Register Name:

UADDRSIZE

Access Type:

Offset:

Read Value:

-

Read-Only

0x0820

31

23

30

22

29

21

28 27

UADDRSIZE[31:24]

20 19

UADDRSIZE[23:16]

26

18

15 14 13 12 11

UADDRSIZE[15:8]

10

7 6 5 4 3

UADDRSIZE[7:0]

2

• UADDRSIZE: IP PB Address Size

This field indicates the size of the PB address space reserved for the USBB IP interface.

25

17

9

1

AT32UC3B

24

16

8

0

409

32059L–AVR32–01/2012

AT32UC3B

22.8.1.8

Name Register 1

Register Name:

UNAME1

Access Type:

Offset:

Read Value:

-

Read-Only

0x0824

31

23

30

22

29

21

28 27

UNAME1[31:24]

20 19

UNAME1[23:16]

15 14 13 12

UNAME1[15:8]

11

7 6 5 4

UNAME1[7:0]

3

• UNAME1: IP Name Part One

This field indicates the first part of the ASCII-encoded name of the USBB IP.

26

18

10

2

9

1

25

17

8

0

24

16

410

32059L–AVR32–01/2012

AT32UC3B

22.8.1.9

Name Register 2

Register Name:

UNAME2

Access Type:

Offset:

Read Value:

Read-Only

0x0828

31

23

30

22

29

21

28 27

UNAME2[31:24]

20 19

UNAME2[23:16]

26

18

15 14 13 12

UNAME2[15:8]

11 10

7 6 5 4

UNAME2[7:0]

3

• UNAME2: IP Name Part Two

This field indicates the second part of the ASCII-encoded name of the USBB IP.

2

9

1

25

17

8

0

24

16

411

32059L–AVR32–01/2012

22.8.1.10

Finite State Machine Status Register

Register Name:

USBFSM

Access Type:

Offset:

Read Value:

Read-Only

0x082C

0x00000009

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

15

-

14

-

13

-

12

-

11

-

10

-

9

-

7

-

6

-

5

-

• DRDSTATE

This field indicates the state of the USBB.

4

-

3 2

DRDSTATE

1

DRDSTATE Description

0

1

2 a_idle state: this is the start state for A-devices (when the ID pin is 0) a_wait_vrise: In this state, the A-device waits for the voltage on VBus to rise above the Adevice VBus Valid threshold (4.4 V).

a_wait_bcon: In this state, the A-device waits for the B-device to signal a connection.

3

4

5

6

7

8

9

10 a_host: In this state, the A-device that operates in Host mode is operational.

a_suspend: The A-device operating as a host is in the suspend mode.

a_peripheral: The A-device operates as a peripheral.

a_wait_vfall: In this state, the A-device waits for the voltage on VBus to drop below the Adevice Session Valid threshold (1.4 V).

a_vbus_err: In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state.

a_wait_discharge: In this state, the A-device waits for the data usb line to discharge (100 us).

b_idle: this is the start state for B-device (when the ID pin is 1).

11

12 b_peripheral: In this state, the B-device acts as the peripheral.

b_wait_begin_hnp: In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested.

b_wait_discharge: In this state, the B-device waits for the data usb line to discharge (100 us) before becoming Host.

25

-

17

-

AT32UC3B

8

-

0

24

-

16

-

412

32059L–AVR32–01/2012

DRDSTATE Description

13

14 b_wait_acon: In this state, the B-device waits for the A-device to signal a connect before becoming B-Host.

b_host: In this state, the B-device acts as the Host.

15 b_srp_init: In this state, the B-device attempts to start a session using the SRP protocol.

AT32UC3B

32059L–AVR32–01/2012

413

AT32UC3B

22.8.2

USB Device Registers

22.8.2.1

Device General Control Register

Register Name:

UDCON

Access Type:

Offset:

Reset Value:

Read/Write

0x0000

0x00000100

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

25

-

17

-

24

-

16

-

15

-

14

-

13

-

12

LS

11

-

10

-

9

RMWKUP

8

DETACH

7

ADDEN

6 5 4 3

UADD

2 1 0

• LS: Low-Speed Mode Force

1: The low-speed mode is active.

0: The full-speed mode is active.

This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit.

• RMWKUP: Remote Wake-Up

Writing a one to this bit will send an upstream resume to the host for a remote wake-up.

Writing a zero to this bit has no effect.

This bit is cleared when the USBB receive a USB reset or once the upstream resume has been sent.

• DETACH: Detach

Writing a one to this bit will physically detach the device (disconnect internal pull-up resistor from D+ and D-).

Writing a zero to this bit will reconnect the device.

• ADDEN: Address Enable

Writing a one to this bit will activate the UADD field (USB address).

Writing a zero to this bit has no effect.

This bit is cleared when a USB reset is received.

• UADD: USB Address

This field contains the device address.

This field is cleared when a USB reset is received.

414

32059L–AVR32–01/2012

AT32UC3B

22.8.2.2

Device Global Interrupt Register

Register Name:

UDINT

Access Type:

Offset:

Reset Value:

Read-Only

0x0004

0x00000000

31

-

23

-

30

DMA6INT

22

-

29

DMA5INT

21

-

28

DMA4INT

20

-

27

DMA3INT

19

-

26

DMA2INT

18

EP6INT

25

DMA1INT

17

EP5INT

24

-

16

EP4INT

15

EP3INT

14

EP2INT

13

EP1INT

12

EP0INT

11

-

10

-

9

-

8

-

7

-

6

UPRSM

5

EORSM

4

WAKEUP

3

EORST

2

SOF

1

-

0

SUSP

• DMAnINT: DMA Channel n Interrupt

This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if DMAnINTE is one.

This bit is cleared when the UDDMAnSTATUS interrupt source is cleared.

• EPnINT: Endpoint n Interrupt

This bit is set when an interrupt is triggered by the endpoint n (UESTAn, UECONn). This triggers a USB interrupt if EPnINTE is one.

This bit is cleared when the interrupt source is serviced.

• UPRSM: Upstream Resume Interrupt

This bit is set when the USBB sends a resume signal called “Upstream Resume”. This triggers a USB interrupt if UPRSME is one.

This bit is cleared when the UDINTCLR.UPRSMC bit is written to one to acknowledge the interrupt (USB clock inputs must be enabled before).

• EORSM: End of Resume Interrupt

This bit is set when the USBB detects a valid “End of Resume” signal initiated by the host. This triggers a USB interrupt if

EORSME is one.

This bit is cleared when the UDINTCLR.EORSMC bit is written to one to acknowledge the interrupt.

• WAKEUP: Wake-Up Interrupt

This bit is set when the USBB is reactivated by a filtered non-idle signal from the lines (not by an upstream resume). This triggers an interrupt if WAKEUPE is one.

This bit is cleared when the UDINTCLR.WAKEUPC bit is written to one to acknowledge the interrupt (USB clock inputs must be enabled before).

This bit is cleared when the Suspend (SUSP) interrupt bit is set.

This interrupt is generated even if the clock is frozen by the FRZCLK bit.

• EORST: End of Reset Interrupt

This bit is set when a USB “End of Reset” has been detected. This triggers a USB interrupt if EORSTE is one.

This bit is cleared when the UDINTCLR.EORSTC bit is written to one to acknowledge the interrupt.

415

32059L–AVR32–01/2012

AT32UC3B

• SOF: Start of Frame Interrupt

This bit is set when a USB “Start of Frame” PID (SOF) has been detected (every 1 ms). This triggers a USB interrupt if SOFE is one. The FNUM field is updated.

This bit is cleared when the UDINTCLR.SOFC bit is written to one to acknowledge the interrupt.

• SUSP: Suspend Interrupt

This bit is set when a USB “Suspend” idle bus state has been detected for 3 frame periods (J state for 3 ms). This triggers a

USB interrupt if SUSPE is one.

This bit is cleared when the UDINTCLR.SUSPC bit is written to one to acknowledge the interrupt.

This bit is cleared when the Wake-Up (WAKEUP) interrupt bit is set.

32059L–AVR32–01/2012

416

AT32UC3B

22.8.2.3

Device Global Interrupt Clear Register

Register Name:

UDINTCLR

Access Type:

Offset:

Read Value:

Write-Only

0x0008

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

-

10

-

7

-

6

UPRSMC

5

EORSMC

4

WAKEUPC

3

EORSTC

Writing a one to a bit in this register will clear the corresponding bit in UDINT.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

2

SOFC

26

-

18

-

1

-

9

-

25

-

17

-

8

-

0

SUSPC

24

-

16

-

417

32059L–AVR32–01/2012

AT32UC3B

22.8.2.4

Device Global Interrupt Set Register

Register Name:

UDINTSET

Access Type:

Offset:

Read Value:

Write-Only

0x000C

0x00000000

31

-

23

-

15

-

30

DMA6INTS

22

-

14

-

29

DMA5INTS

21

-

13

-

28

DMA4INTS

20

-

12

-

27

DMA3INTS

19

-

11

-

26

DMA2INTS

18

-

10

-

25

DMA1INTS

17

-

9

-

24

-

16

-

8

-

7

-

6

UPRSMS

5

EORSMS

4

WAKEUPS

3

EORSTS

2

SOFS

1

-

0

SUSPS

Writing a one to a bit in this register will set the corresponding bit in UDINT, what may be useful for test or debug purposes.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

418

32059L–AVR32–01/2012

AT32UC3B

22.8.2.5

Device Global Interrupt Enable Register

Register Name:

UDINTE

Access Type:

Offset:

Reset Value:

Read-Only

0x0010

0x00000000

31

-

23

-

15

EP3INTE

30

DMA6INTE

22

-

14

EP2INTE

29

DMA5INTE

21

-

13

EP1INTE

28

DMA4INTE

20

-

12

EP0INTE

27

DMA3INTE

19

-

11

-

26

DMA2INTE

18

EP6INTE

10

-

7

-

6

UPRSME

5

EORSME

4

WAKEUPE

3

EORSTE

2

SOFE

1: The corresponding interrupt is enabled.

0: The corresponding interrupt is disabled.

A bit in this register is set when the corresponding bit in UDINTESET is written to one.

A bit in this register is cleared when the corresponding bit in UDINTECLR is written to one.

25

DMA1INTE

17

EP5INTE

9

-

1

-

24

-

16

EP4INTE

8

-

0

SUSPE

419

32059L–AVR32–01/2012

AT32UC3B

22.8.2.6

Device Global Interrupt Enable Clear Register

Register Name:

UDINTECLR

Access Type:

Offset:

Read Value:

Write-Only

0x0014

0x00000000

31

-

23

-

15

EP3INTEC

7

-

30 29 28 27 26 25

DMA6INTEC DMA5INTEC DMA4INTEC DMA3INTEC DMA2INTEC DMA1INTEC

22

-

21

-

20

-

19

-

18

EP6INTEC

17

EP5INTEC

24

-

16

EP4INTEC

14

EP2INTEC

6

UPRSMEC

13

EP1INTEC

5

EORSMEC

12

EP0INTEC

4

WAKEUPEC

11

-

3

EORSTEC

Writing a one to a bit in this register will clear the corresponding bit in UDINTE.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

10

-

2

SOFEC

1

-

9

-

8

-

0

SUSPEC

420

32059L–AVR32–01/2012

AT32UC3B

22.8.2.7

Device Global Interrupt Enable Set Register

Register Name:

UDINTESET

Access Type:

Offset:

Read Value:

Write-Only

0x0018

0x00000000

31

-

23

-

15

EP3INTES

7

-

30 29 28 27 26 25

DMA6INTES DMA5INTES DMA4INTES DMA3INTES DMA2INTES DMA1INTES

22

-

21

-

20

-

19

-

18

EP6INTES

17

EP5INTES

24

-

16

EP4INTES

14

EP2INTES

6

UPRSMES

13

EP1INTES

5

EORSMES

12

EP0INTES

4

WAKEUPES

11

-

3

EORSTES

Writing a one to a bit in this register will set the corresponding bit in UDINTE.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

10

-

2

SOFES

1

-

9

-

8

-

0

SUSPES

421

32059L–AVR32–01/2012

AT32UC3B

22.8.2.8

Endpoint Enable/Reset Register

Register Name:

UERST

Access Type:

Offset:

Reset Value:

Read/Write

0x001C

0x00000000

31

-

23

-

30

-

22

EPRST6

29

-

21

EPRST5

28

-

20

EPRST4

27

-

19

EPRST3

26

-

18

EPRST2

25

-

17

EPRST1

24

-

16

EPRST0

15

-

14

-

13

-

12

-

11

-

10

-

9

-

8

-

7

-

6

EPEN6

5

EPEN5

4

EPEN4

3

EPEN3

2

EPEN2

1

EPEN1

0

EPEN0

• EPRSTn: Endpoint n Reset

Writing a one to this bit will reset the endpoint n FIFO prior to any other operation, upon hardware reset or when a USB bus reset has been received. This resets the endpoint n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration

(ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).

All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence field

(DTSEQ) which can be cleared by setting the RSTDT bit (by writing a one to the RSTDTS bit).

The endpoint configuration remains active and the endpoint is still enabled.

Writing a zero to this bit will complete the reset operation and start using the FIFO.

This bit is cleared upon receiving a USB reset.

• EPENn: Endpoint n Enable

1: The endpoint n is enabled.

0: The endpoint n is disabled, what forces the endpoint n state to inactive (no answer to USB requests) and resets the endpoint n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).

422

32059L–AVR32–01/2012

AT32UC3B

22.8.2.9

Device Frame Number Register

Register Name:

UDFNUM

Access Type:

Offset:

Reset Value:

Read-Only

0x0020

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

13

28

-

20

-

12

27

-

19

-

26

-

18

-

25

-

17

-

9

24

-

16

-

8 15

FNCERR

14

-

11

FNUM[10:5]

10

7 6 5

FNUM[4:0]

4 3 2

-

1

-

0

-

• FNCERR: Frame Number CRC Error

This bit is set when a corrupted frame number is received. This bit and the SOF interrupt bit are updated at the same time.

This bit is cleared upon receiving a USB reset.

• FNUM: Frame Number

This field contains the 11-bit frame number information. It is provided in the last received SOF packet.

This field is cleared upon receiving a USB reset.

FNUM is updated even if a corrupted SOF is received.

423

32059L–AVR32–01/2012

AT32UC3B

22.8.2.10

Endpoint n Configuration Register

Register Name:

UECFGn, n in [0..6]

Access Type:

Offset:

Reset Value:

Read/Write

0x0100 + (n * 0x04)

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

EPTYPE

7

-

6 5

EPSIZE

4

• EPTYPE: Endpoint Type

This field shall be written to select the endpoint type:

0

0

1

1

EPTYPE

0

1

0

1

Endpoint Type

Control

Isochronous

Bulk

Interrupt

This field is cleared upon receiving a USB reset.

• AUTOSW: Automatic Switch

This bit is cleared upon receiving a USB reset.

1: The automatic bank switching is enabled.

0: The automatic bank switching is disabled.

• EPDIR: Endpoint Direction

This bit is cleared upon receiving a USB reset.

1: The endpoint direction is IN (nor for control endpoints).

0: The endpoint direction is OUT.

11

3

EPBK

10

-

2

26

-

18

-

25

-

17

-

9

AUTOSW

1

ALLOC

8

EPDIR

0

-

24

-

16

-

424

32059L–AVR32–01/2012

AT32UC3B

• EPSIZE: Endpoint Size

This field shall be written to select the size of each endpoint bank. The maximum size of each endpoint is specified in

Table 22-

1 on page 352

.

1

1

1

0

0

0

0

EPSIZE

0

0

1

1

0

0

1

0

1

0

1

0

1

0

Endpoint Size

8 bytes

16 bytes

32 bytes

64 bytes

128 bytes

256 bytes

512 bytes

This field is cleared upon receiving a USB reset (except for the endpoint 0).

• EPBK: Endpoint Banks

This field shall be written to select the number of banks for the endpoint:

0

0

1

1

EPBK

0

1

0

1

Endpoint Banks

1 (single-bank endpoint)

2 (double-bank endpoint)

3 (triple-bank endpoint) if supported

(see

Table 22-1 on page 352

).

Reserved

For control endpoints, a single-bank endpoint (0b00) shall be selected.

This field is cleared upon receiving a USB reset (except for the endpoint 0).

• ALLOC: Endpoint Memory Allocate

Writing a one to this bit will allocate the endpoint memory. The user should check the CFGOK bit to know whether the allocation of this endpoint is correct.

Writing a zero to this bit will free the endpoint memory.

This bit is cleared upon receiving a USB reset (except for the endpoint 0).

425

32059L–AVR32–01/2012

AT32UC3B

22.8.2.11

Endpoint n Status Register

Register Name:

UESTAn, n in [0..6]

Access Type:

Offset:

Reset Value:

Read-Only 0x0100

0x0130 + (n * 0x04)

0x00000100

31

-

23

15

CURRBK

30

22

14

BYCT

29

21

28

20

13

NBUSYBK

12

27

BYCT

19

-

11

-

26

18

CFGOK

10

-

25

17

CTRLDIR

9

DTSEQ

24

16

RWALL

8

7

SHORT

PACKET

6

STALLEDI/

CRCERRI

5

OVERFI

4

NAKINI

3

NAKOUTI

2

RXSTPI/

UNDERFI

1

RXOUTI

0

TXINI

• BYCT: Byte Count

This field is set with the byte count of the FIFO.

For IN endpoints, incremented after each byte written by the software into the endpoint and decremented after each byte sent to the host.

For OUT endpoints, incremented after each byte received from the host and decremented after each byte read by the software from the endpoint.

This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.

• CFGOK: Configuration OK Status

This bit is updated when the ALLOC bit is written to one.

This bit is set if the endpoint n number of banks (EPBK) and size (EPSIZE) are correct compared to the maximal allowed number of banks and size for this endpoint and to the maximal FIFO size (i.e. the DPRAM size).

If this bit is cleared, the user shall rewrite correct values to the EPBK and EPSIZE fields in the UECFGn register.

• CTRLDIR: Control Direction

This bit is set after a SETUP packet to indicate that the following packet is an IN packet.

This bit is cleared after a SETUP packet to indicate that the following packet is an OUT packet.

Writing a zero or a one to this bit has no effect.

• RWALL: Read/Write Allowed

This bit is set for IN endpoints when the current bank is not full, i.e., the user can write further data into the FIFO.

This bit is set for OUT endpoints when the current bank is not empty, i.e., the user can read further data from the FIFO.

This bit is never set if STALLRQ is one or in case of error.

This bit is cleared otherwise.

This bit shall not be used for control endpoints.

426

32059L–AVR32–01/2012

AT32UC3B

• CURRBK: Current Bank

This bit is set for non-control endpoints, to indicate the current bank:

0

0

1

1

CURRBK

0

1

0

1

Current Bank

Bank0

Bank1

Bank2 if supported

(see

Table 22-1 on page 352 ).

Reserved

This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.

• NBUSYBK: Number of Busy Banks

This field is set to indicate the number of busy banks:

0

0

1

1

NBUSYBK

0

1

0

1

Number of Busy Banks

0 (all banks free)

1

2

3 if supported

(see

Table 22-1 on page 352

).

For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are free, this triggers an EPnINT interrupt if NBUSYBKE is one.

For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are busy, this triggers an EPnINT interrupt if NBUSYBKE is one.

When the FIFOCON bit is cleared (by writing a one to the FIFOCONC bit) to validate a new bank, this field is updated two or three clock cycles later to calculate the address of the next bank.

An EPnINT interrupt is triggered if:

- for IN endpoint, NBUSYBKE is one and all the banks are free.

- for OUT endpoint, NBUSYBKE is one and all the banks are busy.

• DTSEQ: Data Toggle Sequence

This field is set to indicate the PID of the current bank:

0

0

1

DTSEQ

0

1

X

Data Toggle Sequence

Data0

Data1

Reserved

For IN transfers, it indicates the data toggle sequence that will be used for the next packet to be sent. This is not relative to the current bank.

For OUT transfers, this value indicates the last data toggle sequence received on the current bank.

By default DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle sequence should be Data0.

• SHORTPACKET: Short Packet Interrupt

This bit is set for non-control OUT endpoints, when a short packet has been received.

427

32059L–AVR32–01/2012

AT32UC3B

This bit is set for non-control IN endpoints, a short packet is transmitted upon ending a DMA transfer, thus signaling an end of isochronous frame or a bulk or interrupt end of transfer, this only if the End of DMA Buffer Output Enable (DMAENDEN) bit and the Automatic Switch (AUTOSW) bit are written to one.

This triggers an EPnINT interrupt if SHORTPACKETE is one.

This bit is cleared when the SHORTPACKETC bit is written to one. This will acknowledge the interrupt.

• STALLEDI: STALLed Interrupt

This bit is set to signal that a STALL handshake has been sent. To do that, the software has to set the STALLRQ bit (by writing a one to the STALLRQS bit). This triggers an EPnINT interrupt if STALLEDE is one.

This bit is cleared when the STALLEDIC bit is written to one. This will acknowledge the interrupt.

• CRCERRI: CRC Error Interrupt

This bit is set to signal that a CRC error has been detected in an isochronous OUT endpoint. The OUT packet is stored in the bank as if no CRC error had occurred. This triggers an EPnINT interrupt if CRCERRE is one.

This bit is cleared when the CRCERRIC bit is written to one. This will acknowledge the interrupt.

• OVERFI: Overflow Interrupt

This bit is set when an overflow error occurs. This triggers an EPnINT interrupt if OVERFE is one.

For all endpoint types, an overflow can occur during OUT stage if the host attempts to write into a bank that is too small for the packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first bytes of the packet that fit in.

This bit is cleared when the OVERFIC bit is written to one. This will acknowledge the interrupt.

• NAKINI: NAKed IN Interrupt

This bit is set when a NAK handshake has been sent in response to an IN request from the host. This triggers an EPnINT interrupt if NAKINE is one.

This bit is cleared when the NAKINIC bit is written to one. This will acknowledge the interrupt.

• NAKOUTI: NAKed OUT Interrupt

This bit is set when a NAK handshake has been sent in response to an OUT request from the host. This triggers an EPnINT interrupt if NAKOUTE is one.

This bit is cleared when the NAKOUTIC bit is written to one. This will acknowledge the interrupt.

• UNDERFI: Underflow Interrupt

This bit is set, for isochronous IN/OUT endpoints, when an underflow error occurs. This triggers an EPnINT interrupt if

UNDERFE is one.

An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then automatically sent by the USBB.

An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not fast enough. The packet is lost.

Shall be cleared by writing a one to the UNDERFIC bit. This will acknowledge the interrupt.

This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means RXSTPI for control endpoints.

• RXSTPI: Received SETUP Interrupt

This bit is set, for control endpoints, to signal that the current bank contains a new valid SETUP packet. This triggers an EPnINT interrupt if RXSTPE is one.

Shall be cleared by writing a one to the RXSTPIC bit. This will acknowledge the interrupt and free the bank.

This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means UNDERFI for isochronous IN/OUT endpoints.

• RXOUTI: Received OUT Data Interrupt

This bit is set, for control endpoints, when the current bank contains a bulk OUT packet (data or status stage). This triggers an

EPnINT interrupt if RXOUTE is one.

Shall be cleared for control end points, by writing a one to the RXOUTIC bit. This will acknowledge the interrupt and free the bank.

This bit is set for isochronous, bulk and, interrupt OUT endpoints, at the same time as FIFOCON when the current bank is full.

This triggers an EPnINT interrupt if RXOUTE is one.

428

32059L–AVR32–01/2012

AT32UC3B

Shall be cleared for isochronous, bulk and, interrupt OUT endpoints, by writing a one to the RXOUTIC bit. This will acknowledge the interrupt, what has no effect on the endpoint FIFO.

The user then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT endpoint is composed of multiple banks, this also switches to the next bank. The RXOUTI and FIFOCON bits are set/cleared in accordance with the status of the next bank.

RXOUTI shall always be cleared before clearing FIFOCON.

This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints.

• TXINI: Transmitted IN Data Interrupt

This bit is set for control endpoints, when the current bank is ready to accept a new IN packet. This triggers an EPnINT interrupt if TXINE is one.

This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt and send the packet.

This bit is set for isochronous, bulk and interrupt IN endpoints, at the same time as FIFOCON when the current bank is free.

This triggers an EPnINT interrupt if TXINE is one.

This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt, what has no effect on the endpoint

FIFO.

The user then writes into the FIFO and clears the FIFOCON bit to allow the USBB to send the data. If the IN endpoint is composed of multiple banks, this also switches to the next bank. The TXINI and FIFOCON bits are set/cleared in accordance with the status of the next bank.

TXINI shall always be cleared before clearing FIFOCON.

This bit is inactive (cleared) for isochronous, bulk and interrupt OUT endpoints.

429

32059L–AVR32–01/2012

AT32UC3B

22.8.2.12

Endpoint n Status Clear Register

Register Name:

UESTAnCLR, n in [0..6]

Access Type:

Offset:

Read Value:

Write-Only

0x0160 + (n * 0x04)

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

15

-

14

-

13

-

12

-

11

-

10

-

7

SHORT

PACKETC

6

STALLEDIC/

CRCERRIC

5

OVERFIC

4

NAKINIC

3

NAKOUTIC

Writing a one to a bit in this register will clear the corresponding bit in UESTA.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

2

RXSTPIC/

UNDERFIC

25

-

17

-

9

-

1

RXOUTIC

8

-

0

TXINIC

24

-

16

-

430

32059L–AVR32–01/2012

AT32UC3B

22.8.2.13

Endpoint n Status Set Register

Register Name:

UESTAnSET, n in [0..6]

Access Type:

Offset:

Read Value:

Write-Only

0x0190 + (n * 0x04)

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

25

-

17

-

9

24

-

16

-

15

-

14

-

13

-

12

NBUSYBKS

11

-

10

-

8

-

7

SHORT

PACKETS

6

STALLEDIS/

CRCERRIS

5

OVERFIS

4

NAKINIS

3

NAKOUTIS

2

RXSTPIS/

UNDERFIS

1

RXOUTIS

0

TXINIS

Writing a one to a bit in this register will set the corresponding bit in UESTA, what may be useful for test or debug purposes.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

431

32059L–AVR32–01/2012

AT32UC3B

22.8.2.14

Endpoint n Control Register

Register Name:

UECONn, n in [0..6]

Access Type:

Offset:

Reset Value:

Read-Only

0x01C0 + (n * 0x04)

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

STALLRQ

26

-

18

RSTDT

25

-

17

-

24

-

16

EPDISHDMA

15

-

14

FIFOCON

13

KILLBK

12

NBUSYBKE

11

-

10

-

9

-

8

-

7

SHORT

PACKETE

6

STALLEDE/

CRCERRE

5

OVERFE

4

NAKINE

3

NAKOUTE

2

RXSTPE/

UNDERFE

1

RXOUTE

0

TXINE

• STALLRQ: STALL Request

This bit is set when the STALLRQS bit is written to one. This will request to send a STALL handshake to the host.

This bit is cleared when a new SETUP packet is received or when the STALLRQC bit is written to zero.

• RSTDT: Reset Data Toggle

This bit is set when the RSTDTS bit is written to one. This will clear the data toggle sequence, i.e., set to Data0 the data toggle sequence of the next sent (IN endpoints) or received (OUT endpoints) packet.

This bit is cleared instantaneously.

The user does not have to wait for this bit to be cleared.

• EPDISHDMA: Endpoint Interrupts Disable HDMA Request Enable

This bit is set when the EPDISHDMAS is written to one. This will pause the on-going DMA channel n transfer on any Endpoint n interrupt (EPnINT), whatever the state of the Endpoint n Interrupt Enable bit (EPnINTE).

The user then has to acknowledge or to disable the interrupt source (e.g. RXOUTI) or to clear the EPDISHDMA bit (by writing a one to the EPDISHDMAC bit) in order to complete the DMA transfer.

In ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA transfer is running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but the new-packet DMA transfer will not start (not requested).

If the interrupt is not associated to a new system-bank packet (NAKINI, NAKOUTI, etc.), then the request cancellation may occur at any time and may immediately pause the current DMA transfer.

This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to complete a

DMA transfer by software after reception of a short packet, etc.

• FIFOCON: FIFO Control

For control endpoints:

The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them on these endpoints. When read, their value is always 0.

For IN endpoints:

This bit is set when the current bank is free, at the same time as TXINI.

432

32059L–AVR32–01/2012

AT32UC3B

This bit is cleared (by writing a one to the FIFOCONC bit) to send the FIFO data and to switch to the next bank.

For OUT endpoints:

This bit is set when the current bank is full, at the same time as RXOUTI.

This bit is cleared (by writing a one to the FIFOCONC bit) to free the current bank and to switch to the next bank.

• KILLBK: Kill IN Bank

This bit is set when the KILLBKS bit is written to one. This will kill the last written bank.

This bit is cleared by hardware after the completion of the “kill packet procedure”.

The user shall wait for this bit to be cleared before trying to process another IN packet.

Caution: The bank is cleared when the “kill packet” procedure is completed by the USBB core :

If the bank is really killed, the NBUSYBK field is decremented.

If the bank is not “killed” but sent (IN transfer), the NBUSYBK field is decremented and the TXINI flag is set. This specific case can occur if at the same time an IN token is coming and the user wants to kill this bank.

Note : If two banks are ready to be sent, the above specific case can not occur, because the first bank is sent (IN transfer) while the last bank is killed.

• NBUSYBKE: Number of Busy Banks Interrupt Enable

This bit is set when the NBUSYBKES bit is written to one. This will enable the Number of Busy Banks interrupt (NBUSYBK).

This bit is cleared when the NBUSYBKEC bit is written to zero. This will disable the Number of Busy Banks interrupt

(NBUSYBK).

• SHORTPACKETE: Short Packet Interrupt Enable

This bit is set when the SHORTPACKETES bit is written to one. This will enable the Short Packet interrupt (SHORTPACKET).

This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Short Packet interrupt

(SHORTPACKET).

• STALLEDE: STALLed Interrupt Enable

This bit is set when the STALLEDES bit is written to one. This will enable the STALLed interrupt (STALLEDI).

This bit is cleared when the STALLEDEC bit is written to one. This will disable the STALLed interrupt (STALLEDI).

• CRCERRE: CRC Error Interrupt Enable

This bit is set when the CRCERRES bit is written to one. This will enable the CRC Error interrupt (CRCERRI).

This bit is cleared when the CRCERREC bit is written to one. This will disable the CRC Error interrupt (CRCERRI).

• OVERFE: Overflow Interrupt Enable

This bit is set when the OVERFES bit is written to one. This will enable the Overflow interrupt (OVERFI).

This bit is cleared when the OVERFEC bit is written to one. This will disable the Overflow interrupt (OVERFI).

• NAKINE: NAKed IN Interrupt Enable

This bit is set when the NAKINES bit is written to one. This will enable the NAKed IN interrupt (NAKINI).

This bit is cleared when the NAKINEC bit is written to one. This will disable the NAKed IN interrupt (NAKINI).

• NAKOUTE: NAKed OUT Interrupt Enable

This bit is set when the NAKOUTES bit is written to one. This will enable the NAKed OUT interrupt (NAKOUTI).

This bit is cleared when the NAKOUTEC bit is written to one. This will disable the NAKed OUT interrupt (NAKOUTI).

• RXSTPE: Received SETUP Interrupt Enable

This bit is set when the RXSTPES bit is written to one. This will enable the Received SETUP interrupt (RXSTPI).

This bit is cleared when the RXSTPEC bit is written to one. This will disable the Received SETUP interrupt (RXSTPI).

• UNDERFE: Underflow Interrupt Enable

This bit is set when the UNDERFES bit is written to one. This will enable the Underflow interrupt (UNDERFI).

This bit is cleared when the UNDERFEC bit is written to one. This will disable the Underflow interrupt (UNDERFI).

• RXOUTE: Received OUT Data Interrupt Enable

This bit is set when the RXOUTES bit is written to one. This will enable the Received OUT Data interrupt (RXOUT).

This bit is cleared when the RXOUTEC bit is written to one. This will disable the Received OUT Data interrupt (RXOUT).

• TXINE: Transmitted IN Data Interrupt Enable

This bit is set when the TXINES bit is written to one. This will enable the Transmitted IN Data interrupt (TXINI).

This bit is cleared when the TXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXINI).

433

32059L–AVR32–01/2012

AT32UC3B

22.8.2.15

Endpoint n Control Clear Register

Register Name:

UECONnCLR, n in [0..6]

Access Type:

Offset:

Read Value:

Write-Only

0x0220 + (n * 0x04)

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

STALLRQC

26

-

18

-

25

-

17

-

15

-

14

FIFOCONC

13

-

12

NBUSYBKEC

11

-

10

-

9

-

7

SHORT

PACKETEC

6

STALLEDEC

/CRCERREC

5

OVERFEC

4

NAKINEC

3

NAKOUTEC

2

RXSTPEC/

UNDERFEC

Writing a one to a bit in this register will clear the corresponding bit in UECONn.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

1

RXOUTEC

24

-

16

EPDISHDMAC

8

-

0

TXINEC

434

32059L–AVR32–01/2012

AT32UC3B

22.8.2.16

Endpoint n Control Set Register

Register Name:

UECONnSET, n in [0..6]

Access Type:

Offset:

Read Value:

Write-Only

0x01F0 + (n * 0x04)

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

STALLRQS

26

-

18

RSTDTS

25

-

17

-

15

-

14

-

13

KILLBKS

12

NBUSYBKES

11

-

10

-

9

-

7

SHORT

PACKETES

6

STALLEDES/

CRCERRES

5

OVERFES

4

NAKINES

3

NAKOUTES

Writing a one to a bit in this register will set the corresponding bit in UECONn.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

2

RXSTPES/

UNDERFES

1

RXOUTES

24

-

16

EPDISHDMAS

8

-

0

TXINES

435

32059L–AVR32–01/2012

AT32UC3B

22.8.2.17

Device DMA Channel n Next Descriptor Address Register

Register Name:

UDDMAnNEXTDESC, n in [1..6]

Access Type:

Offset:

Reset Value:

Read/Write

0x0310 + (n - 1) * 0x10

0x00000000

31

23

30

22

29

21

28 27

NXTDESCADDR[31:24]

20 19

NXTDESCADDR[23:16]

26

18

25

17

24

16

15 14 13 12 11

NXTDESCADDR[15:8]

10 9

7 6 5

NXTDESCADDR[7:4]

4 3

-

2

-

1

-

• NXTDESCADDR: Next Descriptor Address

This field contains the bits 31:4 of the 16-byte aligned address of the next channel descriptor to be processed.

This field is written either or by descriptor loading.

8

0

-

436

32059L–AVR32–01/2012

AT32UC3B

22.8.2.18

Device DMA Channel n HSB Address Register

Register Name:

UDDMAnADDR, n in [1..6]

Access Type:

Offset:

Reset Value:

Read/Write

0x0314 + (n - 1) * 0x10

0x00000000

31

23

30

22

29

21

28 27

HSBADDR[31:24]

20 19

HSBADDR[23:16]

26

18

25

17

24

16

15 14 13 12 11

HSBADDR[15:8]

10 9 8

7 6 5 4

HSBADDR[7:0]

3 2 1 0

• HSBADDR: HSB Address

This field determines the HSB bus current address of a channel transfer.

The address written to the HSB address bus is HSBADDR rounded down to the nearest word-aligned address, i.e.,

HSBADDR[1:0] is considered as 0b00 since only word accesses are performed.

Channel HSB start and end addresses may be aligned on any byte boundary.

The user may write this field only when the Channel Enabled bit (CHEN) of the UDDMAnSTATUS register is cleared.

This field is updated at the end of the address phase of the current access to the HSB bus. It is incremented of the HSB access byte-width.

The HSB access width is 4 bytes, or less at packet start or end if the start or end address is not aligned on a word boundary.

The packet start address is either the channel start address or the next channel address to be accessed in the channel buffer.

The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.

The channel start address is written or loaded from the descriptor, whereas the channel end address is either determined by the end of buffer or the end of USB transfer if the Buffer Close Input Enable bit (BUFFCLOSEINEN) is set.

437

32059L–AVR32–01/2012

AT32UC3B

22.8.2.19

Device DMA Channel n Control Register

Register Name:

UDDMAnCONTROL, n in [1..6]

Access Type:

Offset:

Reset Value:

Read/Write

0x0318 + (n - 1) * 0x10

0x00000000

31

23

30

22

29

21

28 27

CHBYTELENGTH[15:8]

20 19

CHBYTELENGTH[7:0]

26

18

25

17

24

16

15

-

14

-

13

-

12

-

11

-

10

-

9

-

8

-

7 6 5

BURSTLOCKEN DESCLDIRQEN EOBUFFIRQEN

4

EOTIRQEN

3

DMAENDEN

2

BUFFCLOSE

INEN

1

LDNXTCH

DESCEN

0

CHEN

• CHBYTELENGTH: Channel Byte Length

This field determines the total number of bytes to be transferred for this buffer.

The maximum channel transfer size 64kB is reached when this field is zero (default value).

If the transfer size is unknown, the transfer end is controlled by the peripheral and this field should be written to zero.

This field can be written or descriptor loading only after the UDDMAnSTATUS.CHEN bit has been cleared, otherwise this field is ignored.

• BURSTLOCKEN: Burst Lock Enable

1: The USB data burst is locked for maximum optimization of HSB busses bandwidth usage and maximization of fly-by duration.

0: The DMA never locks the HSB access.

• DESCLDIRQEN: Descriptor Loaded Interrupt Enable

1: The Descriptor Loaded interrupt is enabled.This interrupt is generated when a Descriptor has been loaded from the system bus.

0: The Descriptor Loaded interrupt is disabled.

• EOBUFFIRQEN: End of Buffer Interrupt Enable

1: The end of buffer interrupt is enabled.This interrupt is generated when the channel byte count reaches zero.

0: The end of buffer interrupt is disabled.

• EOTIRQEN: End of USB Transfer Interrupt Enable

1: The end of usb OUT data transfer interrupt is enabled. This interrupt is generated only if the BUFFCLOSEINEN bit is set.

0: The end of usb OUT data transfer interrupt is disabled.

• DMAENDEN: End of DMA Buffer Output Enable

Writing a one to this bit will properly complete the usb transfer at the end of the dma transfer.

For IN endpoint, it means that a short packet (but not a Zero Length Packet) will be sent to the USB line to properly closed the usb transfer at the end of the dma transfer.

For OUT endpoint, it means that all the banks will be properly released. (NBUSYBK=0) at the end of the dma transfer.

438

32059L–AVR32–01/2012

AT32UC3B

• BUFFCLOSEINEN: Buffer Close Input Enable

For Bulk and Interrupt endpoint, writing a one to this bit will automatically close the current DMA transfer at the end of the USB

OUT data transfer (received short packet).

For Full-speed Isochronous, it does not make sense, so BUFFCLOSEINEN should be left to zero.

Writing a zero to this bit to disable this feature.

• LDNXTCHDESCEN: Load Next Channel Descriptor Enable

1: the channel controller loads the next descriptor after the end of the current transfer, i.e. when the UDDMAnSTATUS.CHEN bit is reset.

0: no channel register is loaded after the end of the channel transfer.

If the CHEN bit is written to zero, the next descriptor is immediately loaded upon transfer request (endpoint is free for IN endpoint, or endpoint is full for OUT endpoint).

Table 22-6.

DMA Channel Control Command Summary

LDNXTCHDES

CEN

1

1

0

0

CHEN

0

1

0

1

Current Bank

stop now

Run and stop at end of buffer

Load next descriptor now

Run and link at end of buffer

• CHEN: Channel Enable

Writing this bit to zero will disabled the DMA channel and no transfer will occur upon request. If the LDNXTCHDESCEN bit is written to zero, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both

UDDMAnSTATUS.CHEN and CHACTIVE bits are zero.

Writing this bit to one will set the UDDMAnSTATUS.CHEN bit and enable DMA channel data transfer. Then any pending request will start the transfer. This may be used to start or resume any requested transfer.

This bit is cleared when the channel source bus is disabled at end of buffer. If the LDNXTCHDESCEN bit has been cleared by descriptor loading, the user will have to write to one the corresponding CHEN bit to start the described transfer, if needed.

If a channel request is currently serviced when this bit is zero, the DMA FIFO buffer is drained until it is empty, then the

UDDMAnSTATUS.CHEN bit is cleared.

If the LDNXTCHDESCEN bit is set or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer occurs) and the next descriptor is immediately loaded.

439

32059L–AVR32–01/2012

AT32UC3B

22.8.2.20

Device DMA Channel n Status Register

Register Name:

UDDMAnSTATUS, n in [1..6]

Access Type:

Offset:

Reset Value:

Read/Write

0x031C + (n - 1) * 0x10

0x00000000

31

23

30

22

29

21

28 27

CHBYTECNT[15:8]

20 19

CHBYTECNT[7:0]

26

18

25

17

24

16

15

-

14

-

13

-

12

-

11

-

10

-

9

-

8

-

7

-

6

DESCLD

STA

5

EOCHBUFF

STA

4

EOTSTA

3

-

2

-

1

CHACTIVE

0

CHEN

• CHBYTECNT: Channel Byte Count

This field contains the current number of bytes still to be transferred for this buffer.

This field is decremented at each dma access.

This field is reliable (stable) only if the CHEN bit is zero.

• DESCLDSTA: Descriptor Loaded Status

This bit is set when a Descriptor has been loaded from the HSB bus.

This bit is cleared when read by the user.

• EOCHBUFFSTA: End of Channel Buffer Status

This bit is set when the Channel Byte Count counts down to zero.

This bit is automatically cleared when read by software.

• EOTSTA: End of USB Transfer Status

This bit is set when the completion of the usb data transfer has closed the dma transfer. It is valid only if

UDDMAnCONTROL.BUFFCLOSEINEN is one. Note that for OUT endpoint, if the UECFGn.AUTOSW is set, any received zerolength-packet will be cancelled by the DMA, and the EOTSTA will be set whatever the UDDMAnCONTROL.CHEN bit is.

This bit is automatically cleared when read by software.

• CHACTIVE: Channel Active

0: the DMA channel is no longer trying to source the packet data.

1: the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. When a packet transfer cannot be completed due to an EOCHBUFFSTA, this bit stays set during the next channel descriptor load (if any) and potentially until USB packet transfer completion, if allowed by the new descriptor.

When programming a DMA by descriptor (Load next descriptor now), the CHACTIVE bit is set only once the DMA is running

(the endpoint is free for IN transaction, the endpoint is full for OUT transaction).

• CHEN: Channel Enabled

This bit is set (after one cycle latency) when the L.CHEN is written to one or when the descriptor is loaded.

This bit is cleared when any transfer is ended either due to an elapsed byte count or a USB device initiated transfer end.

440

32059L–AVR32–01/2012

AT32UC3B

0: the DMA channel no longer transfers data, and may load the next descriptor if the UDDMAnCONTROL.LDNXTCHDESCEN bit is zero.

1: the DMA channel is currently enabled and transfers data upon request.

If a channel request is currently serviced when the UDDMAnCONTROL.CHEN bit is written to zero, the DMA FIFO buffer is drained until it is empty, then this status bit is cleared.

32059L–AVR32–01/2012

441

AT32UC3B

22.8.3

USB Host Registers

22.8.3.1

Host General Control Register

Register Name:

UHCON

Access Type:

Offset:

Reset Value:

Read/Write

0x0400

0x00000000

7

-

15

-

31

-

23

-

30

-

22

-

14

-

6

-

29

-

21

-

13

-

5

-

28

-

20

-

12

-

4

-

27

-

19

-

11

-

3

-

26

-

18

-

10

RESUME

2

-

25

-

17

-

9

RESET

1

-

24

-

16

-

8

SOFE

0

-

• RESUME: Send USB Resume

Writing a one to this bit will generate a USB Resume on the USB bus.

This bit is cleared when the USB Resume has been sent or when a USB reset is requested.

Writing a zero to this bit has no effect.

This bit should be written to one only when the start of frame generation is enable. (SOFE bit is one).

• RESET: Send USB Reset

Writing a one to this bit will generate a USB Reset on the USB bus.

This bit is cleared when the USB Reset has been sent.

It may be useful to write a zero to this bit when a device disconnection is detected (UHINT.DDISCI is one) whereas a USB Reset is being sent.

• SOFE: Start of Frame Generation Enable

Writing a one to this bit will generate SOF on the USB bus in full speed mode and keep alive in low speed mode.

Writing a zero to this bit will disable the SOF generation and to leave the USB bus in idle state.

This bit is set when a USB reset is requested or an upstream resume interrupt is detected (UHINT.RXRSMI).

442

32059L–AVR32–01/2012

AT32UC3B

22.8.3.2

Host Global Interrupt Register

Register Name:

UHINT

Access Type:

Offset:

Reset Value:

Read-Only

0x0404

0x00000000

31

-

23

-

30

DMA6INT

22

-

29

DMA5INT

21

-

28

DMA4INT

20

-

27

DMA3INT

19

-

26

DMA2INT

18

-

25

DMA1INT

17

-

24

-

16

15

-

14

P6INT

13

P5INT

12

P4INT

11

P3INT

10

P2INT

9

P1INT

8

P0INT

7

-

6

HWUPI

5

HSOFI

4

RXRSMI

3

RSMEDI

2

RSTI

1

DDISCI

0

DCONNI

• DMAnINT: DMA Channel n Interrupt

This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if the corresponding

DMAnINTE is one (UHINTE register).

This bit is cleared when the UHDMAnSTATUS interrupt source is cleared.

• PnINT: Pipe n Interrupt

This bit is set when an interrupt is triggered by the endpoint n (UPSTAn). This triggers a USB interrupt if the corresponding pipe interrupt enable bit is one (UHINTE register).

This bit is cleared when the interrupt source is served.

• HWUPI: Host Wake-Up Interrupt

This bit is set when the host controller is in the suspend mode (SOFE is zero) and an upstream resume from the peripheral is detected.

This bit is set when the host controller is in the suspend mode (SOFE is zero) and a peripheral disconnection is detected.

This bit is set when the host controller is in the Idle state (USBSTA.VBUSRQ is zero, no VBus is generated).

This interrupt is generated even if the clock is frozen by the FRZCLK bit.

• HSOFI: Host Start of Frame Interrupt

This bit is set when a SOF is issued by the Host controller. This triggers a USB interrupt when HSOFE is one. When using the host controller in low speed mode, this bit is also set when a keep-alive is sent.

This bit is cleared when the HSOFIC bit is written to one.

• RXRSMI: Upstream Resume Received Interrupt

This bit is set when an Upstream Resume has been received from the Device.

This bit is cleared when the RXRSMIC is written to one.

• RSMEDI: Downstream Resume Sent Interrupt

This bit set when a Downstream Resume has been sent to the Device.

This bit is cleared when the RSMEDIC bit is written to one.

• RSTI: USB Reset Sent Interrupt

This bit is set when a USB Reset has been sent to the device.

This bit is cleared when the RSTIC bit is written to one.

443

32059L–AVR32–01/2012

• DDISCI: Device Disconnection Interrupt

This bit is set when the device has been removed from the USB bus.

This bit is cleared when the DDISCIC bit is written to one.

• DCONNI: Device Connection Interrupt

This bit is set when a new device has been connected to the USB bus.

This bit is cleared when the DCONNIC bit is written to one.

AT32UC3B

32059L–AVR32–01/2012

444

AT32UC3B

22.8.3.3

Host Global Interrupt Clear Register

Register Name:

UHINTCLR

Access Type:

Offset:

Read Value:

Write-Only

0x0408

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

-

10

-

7

-

6

HWUPIC

5

HSOFIC

4

RXRSMIC

3

RSMEDIC

Writing a one to a bit in this register will clear the corresponding bit in UHINT.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

2

RSTIC

26

-

18

-

25

-

17

-

9

-

1

DDISCIC

24

-

16

-

8

-

0

DCONNIC

445

32059L–AVR32–01/2012

AT32UC3B

22.8.3.4

Host Global Interrupt Set Register

Register Name:

UHINTSET

Access Type:

Offset:

Read Value:

Write-Only

0x040C

0x00000000

31

-

23

-

15

-

30

DMA6INTS

22

-

14

-

29

DMA5INTS

21

-

13

-

28

DMA4INTS

20

-

12

-

27

DMA3INTS

19

-

11

-

26

DMA2INTS

18

-

10

-

25

DMA1INTS

17

-

9

-

24

-

16

-

8

-

7

-

6

HWUPIS

5

HSOFIS

4

RXRSMIS

3

RSMEDIS

2

RSTIS

1

DDISCIS

0

DCONNIS

Writing a one to a bit in this register will set the corresponding bit in UHINT, what may be useful for test or debug purposes.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

446

32059L–AVR32–01/2012

AT32UC3B

22.8.3.5

Host Global Interrupt Enable Register

Register Name:

UHINTE

Access Type:

Offset:

Reset Value:

Read-Only

0x0410

0x00000000

31

-

23

-

15

-

30

DMA6INTE

22

-

14

P6INTE

29

DMA5INTE

21

-

13

P5INTE

28

DMA4INTE

20

-

12

P4INTE

27

DMA3INTE

19

-

11

P3INTE

26

DMA2INTE

18

-

10

P2INTE

25

DMA1INTE

17

-

9

P1INTE

24

-

16

-

8

P0INTE

7

-

6

HWUPIE

5

HSOFIE

4

RXRSMIE

3

RSMEDIE

2

RSTIE

1

DDISCIE

0

DCONNIE

• DMAnINTE: DMA Channel n Interrupt Enable

This bit is set when the DMAnINTES bit is written to one. This will enable the DMA Channel n Interrupt (DMAnINT).

This bit is cleared when the DMAnINTEC bit is written to one. This will disable the DMA Channel n Interrupt (DMAnINT).

• PnINTE: Pipe n Interrupt Enable

This bit is set when the PnINTES bit is written to one. This will enable the Pipe n Interrupt (PnINT).

This bit is cleared when the PnINTEC bit is written to one. This will disable the Pipe n Interrupt (PnINT).

• HWUPIE: Host Wake-Up Interrupt Enable

This bit is set when the HWUPIES bit is written to one. This will enable the Host Wake-up Interrupt (HWUPI).

This bit is cleared when the HWUPIEC bit is written to one. This will disable the Host Wake-up Interrupt (HWUPI).

• HSOFIE: Host Start of Frame Interrupt Enable

This bit is set when the HSOFIES bit is written to one. This will enable the Host Start of Frame interrupt (HSOFI).

This bit is cleared when the HSOFIEC bit is written to one. This will disable the Host Start of Frame interrupt (HSOFI).

• RXRSMIE: Upstream Resume Received Interrupt Enable

This bit is set when the RXRSMIES bit is written to one. This will enable the Upstream Resume Received interrupt (RXRSMI).

This bit is cleared when the RXRSMIEC bit is written to one. This will disable the Downstream Resume interrupt (RXRSMI).

• RSMEDIE: Downstream Resume Sent Interrupt Enable

This bit is set when the RSMEDIES bit is written to one. This will enable the Downstream Resume interrupt (RSMEDI).

This bit is cleared when the RSMEDIEC bit is written to one. This will disable the Downstream Resume interrupt (RSMEDI).

• RSTIE: USB Reset Sent Interrupt Enable

This bit is set when the RSTIES bit is written to one. This will enable the USB Reset Sent interrupt (RSTI).

This bit is cleared when the RSTIEC bit is written to one. This will disable the USB Reset Sent interrupt (RSTI).

• DDISCIE: Device Disconnection Interrupt Enable

This bit is set when the DDISCIES bit is written to one. This will enable the Device Disconnection interrupt (DDISCI).

This bit is cleared when the DDISCIEC bit is written to one. This will disable the Device Disconnection interrupt (DDISCI).

• DCONNIE: Device Connection Interrupt Enable

This bit is set when the DCONNIES bit is written to one. This will enable the Device Connection interrupt (DCONNI).

This bit is cleared when the DCONNIEC bit is written to one. This will disable the Device Connection interrupt (DCONNI).

447

32059L–AVR32–01/2012

AT32UC3B

22.8.3.6

Host Global Interrupt Enable Clear Register

Register Name:

UHINTECLR

Access Type:

Offset:

Read Value:

Write-Only

0x0414

0x00000000

31

-

23

-

30 29 28 27 26 25

DMA6INTEC DMA5INTEC DMA4INTEC DMA3INTEC DMA2INTEC DMA1INTEC

22

-

21

-

20

-

19

-

18

-

17

-

15

-

14

P6INTEC

13

P5INTEC

12

P4INTEC

11

P3INTEC

10

P2INTEC

7

-

6

HWUPIEC

5

HSOFIEC

4

RXRSMIEC

3

RSMEDIEC

Writing a one to a bit in this register will clear the corresponding bit in UHINTE.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

2

RSTIEC

9

P1INTEC

24

-

16

-

8

P0INTEC

1

DDISCIEC

0

DCONNIEC

448

32059L–AVR32–01/2012

AT32UC3B

22.8.3.7

Host Global Interrupt Enable Set Register

Register Name:

UHINTESET

Access Type:

Offset:

Read Value:

Write-Only

0x0418

0x00000000

31

-

23

-

30 29 28 27 26 25

DMA6INTES DMA5INTES DMA4INTES DMA3INTES DMA2INTES DMA1INTES

22

-

21

-

20

-

19

-

18

-

17

-

15

-

14

P6INTES

13

P5INTES

12

P4INTES

11

P3INTES

10

P2INTES

7

-

6

HWUPIES

5

HSOFIES

4

RXRSMIES

3

RSMEDIES

Writing a one to a bit in this register will set the corresponding bit in UHINT.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

2

RSTIES

9

P1INTES

24

-

16

-

8

P0INTES

1

DDISCIES

0

DCONNIES

449

32059L–AVR32–01/2012

AT32UC3B

22.8.3.8

Host Frame Number Register

Register Name:

UHFNUM

Access Type:

Offset:

Reset Value:

Read/Write

0x0420

0x00000000

31

-

23

30

-

22

29

-

21

28

-

20

FLENHIGH

19

12

27

-

11

FNUM[10:5]

10

26

-

18

25

-

17

24

-

16

15

-

14

-

13 9 8

7 6 5

FNUM[4:0]

4 3 2

-

1

-

0

-

• FLENHIGH: Frame Length

This field contains the 8 high-order bits of the 14-bits internal frame counter (frame counter at 12MHz, counter length is 12000 to ensure a SOF generation every 1 ms).

• FNUM: Frame Number

This field contains the current SOF number.

This field can be written.

450

32059L–AVR32–01/2012

AT32UC3B

22.8.3.9

Host Address 1 Register

Register Name:

UHADDR1

Access Type:

Offset:

Reset Value:

Read/Write

0x0424

0x00000000

31

-

23

-

30

22

29

21

28

20

27

UHADDRP3

19

UHADDRP2

15

-

14 13 12 11

UHADDRP1

7

-

6 5 4

• UHADDRP3: USB Host Address

This field contains the address of the Pipe3 of the USB Device.

This field is cleared when a USB reset is requested.

• UHADDRP2: USB Host Address

This field contains the address of the Pipe2 of the USB Device.

This field is cleared when a USB reset is requested.

• UHADDRP1: USB Host Address

This field contains the address of the Pipe1 of the USB Device.

This field is cleared when a USB reset is requested.

• UHADDRP0: USB Host Address

This field contains the address of the Pipe0 of the USB Device.

This field is cleared when a USB reset is requested.

3

UHADDRP0

26

18

10

2

9

1

25

17

8

0

24

16

451

32059L–AVR32–01/2012

AT32UC3B

22.8.3.10

Host Address 2 Register

Register Name:

UHADDR2

Access Type:

Offset:

Reset Value:

Read/Write

0x0428

0x00000000

31

-

23

-

30

-

22

29

-

21

28

-

20

27

-

19

UHADDRP6

15

-

14 13 12 11

UHADDRP5

7

-

6 5 4

• UHADDRP6: USB Host Address

This field contains the address of the Pipe6 of the USB Device.

This field is cleared when a USB reset is requested.

• UHADDRP5: USB Host Address

This field contains the address of the Pipe5 of the USB Device.

This field is cleared when a USB reset is requested.

• UHADDRP4: USB Host Address

This field contains the address of the Pipe4 of the USB Device.

This field is cleared when a USB reset is requested.

3

UHADDRP4

26

-

18

10

2

9

1

25

-

17

8

0

24

-

16

452

32059L–AVR32–01/2012

AT32UC3B

22.8.3.11

Pipe Enable/Reset Register

Register Name:

UPRST

Access Type:

Offset:

Reset Value:

Read/Write

0x0041C

0x00000000

31

-

23

-

30

-

22

PRST6

29

-

21

PRST5

28

-

20

PRST4

27

-

19

PRST3

26

-

18

PRST2

25

-

17

PRST1

24

-

16

PRST0

15

-

14

-

13

-

12

-

11

-

10

-

9

-

8

-

7

-

6

PEN6

5

PEN5

4

PEN4

3

PEN3

2

PEN2

1

PEN1

0

PEN0

• PRSTn: Pipe n Reset

Writing a one to this bit will reset the Pipe n FIFO.

This resets the endpoint n registers (UPCFGn, UPSTAn, UPCONn) but not the endpoint configuration (ALLOC, PBK, PSIZE,

PTOKEN, PTYPE, PEPNUM, INTFRQ).

All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle management.

The endpoint configuration remains active and the endpoint is still enabled.

Writing a zero to this bit will complete the reset operation and allow to start using the FIFO.

• PENn: Pipe n Enable

Writing a one to this bit will enable the Pipe n.

Writing a zero to this bit will disable the Pipe n, what forces the Pipe n state to inactive and resets the pipe n registers (UPCFGn,

UPSTAn, UPCONn) but not the pipe configuration (ALLOC, PBK, PSIZE).

453

32059L–AVR32–01/2012

AT32UC3B

22.8.3.12

Pipe n Configuration Register

Register Name:

UPCFGn, n in [0..6]

Access Type:

Offset:

Reset Value:

Read/Write

0x0500 + (n * 0x04)

0x00000000

31 30 29 28

INTFRQ

27 26 25 24

23

-

15

-

22

-

14

-

21

-

13

PTYPE

20

-

12

19

11

-

18

10

PEPNUM

AUTOSW

17 16

9

PTOKEN

8

7

-

6 5

PSIZE

4 3

PBK

2

• INTFRQ: Pipe Interrupt Request Frequency

This field contains the maximum value in millisecond of the polling period for an Interrupt Pipe.

This value has no effect for a non-Interrupt Pipe.

This field is cleared upon sending a USB reset.

• PEPNUM: Pipe Endpoint Number

This field contains the number of the endpoint targeted by the pipe. This value is from 0 to 15.

This field is cleared upon sending a USB reset.

• PTYPE: Pipe Type

This field contains the pipe type.

1

ALLOC

0

0

1

1

PTYPE

0

1

0

1

Pipe Type

Control

Isochronous

Bulk

Interrupt

This field is cleared upon sending a USB reset.

• AUTOSW: Automatic Switch

This bit is cleared upon sending a USB reset.

1: The automatic bank switching is enabled.

0: The automatic bank switching is disabled.

0

-

454

32059L–AVR32–01/2012

• PTOKEN: Pipe Token

This field contains the endpoint token.

1

1

1

1

0

0

0

0

PTOKEN

00

01

10

11

Endpoint Direction

SETUP

IN

OUT reserved

• PSIZE: Pipe Size

This field contains the size of each pipe bank.

PSIZE

0

0

0

0

1

1

1

1

0

1

0

1

0

1

0

1

Endpoint Size

8 bytes

16 bytes

32 bytes

64 bytes

128 bytes

256 bytes

512 bytes

1024 bytes

This field is cleared upon sending a USB reset.

• PBK: Pipe Banks

This field contains the number of banks for the pipe.

PBK

1

1

0

0

0

1

0

1

Endpoint Banks

1 (single-bank pipe)

2 (double-bank pipe)

3 (triple-bank pipe) if supported

(see

Table 22-1 on page 352 ).

Reserved

For control endpoints, a single-bank pipe (0b00) should be selected.

This field is cleared upon sending a USB reset.

• ALLOC: Pipe Memory Allocate

Writing a one to this bit will allocate the pipe memory.

Writing a zero to this bit will free the pipe memory.

This bit is cleared when a USB Reset is requested.

Refer to the DPRAM Management chapter for more details.

AT32UC3B

455

32059L–AVR32–01/2012

AT32UC3B

22.8.3.13

Pipe n Status Register

Register Name:

UPSTAn, n in [0..6]

Access Type:

Offset:

Reset Value:

Read-Only

0x0530 + (n * 0x04)

0x00000000

31

-

23

30 29 28

15

CURRBK

22

PBYCT[3:0]

21

14

20

13

NBUSYBK

12

27

PBYCT[10:4]

19

-

11

-

26

18

CFGOK

10

-

25

17

-

9

DTSEQ

24

16

RWALL

8

7

SHORT

PACKETI

6

RXSTALLDI/

CRCERRI

5

OVERFI

4

NAKEDI

3

PERRI

2

TXSTPI/

UNDERFI

1

TXOUTI

0

RXINI

• PBYCT: Pipe Byte Count

This field contains the byte count of the FIFO.

For OUT pipe, incremented after each byte written by the user into the pipe and decremented after each byte sent to the peripheral.

For IN pipe, incremented after each byte received from the peripheral and decremented after each byte read by the user from the pipe.

This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.

• CFGOK: Configuration OK Status

This bit is set/cleared when the UPCFGn.ALLOC bit is set.

This bit is set if the pipe n number of banks (UPCFGn.PBK) and size (UPCFGn.PSIZE) are correct compared to the maximal allowed number of banks and size for this pipe and to the maximal FIFO size (i.e., the DPRAM size).

If this bit is cleared, the user should rewrite correct values ot the PBK and PSIZE field in the UPCFGn register.

• RWALL: Read/Write Allowed

For OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO.

For IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the FIFO.

This bit is cleared otherwise.

This bit is also cleared when the RXSTALL or the PERR bit is one.

• CURRBK: Current Bank

For non-control pipe, this field indicates the number of the current bank.

0

CURRBK

0

Current Bank

Bank0

456

32059L–AVR32–01/2012

AT32UC3B

0

1

1

CURRBK

1

0

1

Current Bank

Bank1

Bank2 if supported

(see

Table 22-1 on page 352 ).

Reserved

This field may be updated 1 clock cycle after the RWALL bit changes, so the user shall not poll this field as an interrupt bit.

• NBUSYBK: Number of Busy Banks

This field indicates the number of busy bank.

For OUT pipe, this field indicates the number of busy bank(s), filled by the user, ready for OUT transfer. When all banks are busy, this triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.

For IN pipe, this field indicates the number of busy bank(s) filled by IN transaction from the Device. When all banks are free, this triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.

1

1

0

0

NBUSYBK

0

1

0

1

Number of busy bank

All banks are free.

1 busy bank

2 busy banks if supported

(see

Table 22-1 on page 352 ).

reserved

• DTSEQ: Data Toggle Sequence

This field indicates the data PID of the current bank.

0

0

1

1

DTSEQ

0

1

0

1

Data toggle sequence

Data0

Data1 reserved reserved

For OUT pipe, this field indicates the data toggle of the next packet that will be sent.

For IN pipe, this field indicates the data toggle of the received packet stored in the current bank.

• SHORTPACKETI: Short Packet Interrupt

This bit is set when a short packet is received by the host controller (packet length inferior to the PSIZE programmed field).

This bit is cleared when the SHORTPACKETIC bit is written to one.

• RXSTALLDI: Received STALLed Interrupt

This bit is set, for all endpoints but isochronous, when a STALL handshake has been received on the current bank of the pipe.

The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is one.

This bit is cleared when the RXSTALLDIC bit is written to one.

• CRCERRI: CRC Error Interrupt

This bit is set, for isochronous endpoint, when a CRC error occurs on the current bank of the Pipe. This triggers an interrupt if the TXSTPE bit is one.

This bit is cleared when the CRCERRIC bit is written to one.

• OVERFI: Overflow Interrupt

This bit is set when the current pipe has received more data than the maximum length of the current pipe. An interrupt is triggered if the OVERFIE bit is one.

This bit is cleared when the OVERFIC bit is written to one.

• NAKEDI: NAKed Interrupt

This bit is set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if the NAKEDE bit is one.

457

32059L–AVR32–01/2012

AT32UC3B

This bit is cleared when the NAKEDIC bit written to one.

• PERRI: Pipe Error Interrupt

This bit is set when an error occurs on the current bank of the pipe. This triggers an interrupt if the PERRE bit is set. Refers to the UPERRn register to determine the source of the error.

This bit is cleared when the error source bit is cleared.

• TXSTPI: Transmitted SETUP Interrupt

This bit is set, for Control endpoints, when the current SETUP bank is free and can be filled. This triggers an interrupt if the

TXSTPE bit is one.

This bit is cleared when the TXSTPIC bit is written to one.

• UNDERFI: Underflow Interrupt

This bit is set, for isochronous and Interrupt IN/OUT pipe, when an error flow occurs. This triggers an interrupt if the UNDERFIE bit is one.

This bit is set, for Isochronous or interrupt OUT pipe, when a transaction underflow occurs in the current pipe. (the pipe can’t send the OUT data packet in time because the current bank is not ready). A zero-length-packet (ZLP) will be sent instead of.

This bit is set, for Isochronous or interrupt IN pipe, when a transaction flow error occurs in the current pipe. i.e, the current bank of the pipe is not free whereas a new IN USB packet is received. This packet is not stored in the bank. For Interrupt pipe, the overflowed packet is ACKed to respect the USB standard.

This bit is cleared when the UNDERFIEC bit is written to one.

• TXOUTI: Transmitted OUT Data Interrupt

This bit is set when the current OUT bank is free and can be filled. This triggers an interrupt if the TXOUTE bit is one.

This bit is cleared when the TXOUTIC bit is written to one.

• RXINI: Received IN Data Interrupt

This bit is set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if the RXINE bit is one.

This bit is cleared when the RXINIC bit is written to one.

458

32059L–AVR32–01/2012

AT32UC3B

22.8.3.14

Pipe n Status Clear Register

Register Name:

UPSTAnCLR, n in [0..6]

Access Type:

Offset:

Read Value:

Write-Only

0x0560 + (n * 0x04)

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

15

-

14

-

13

-

12

-

11

-

10

-

7

SHORT

PACKETIC

6

RXSTALLDI

C/

CRCERRIC

5

OVERFIC

4

NAKEDIC

3

-

Writing a one to a bit in this register will clear the corresponding bit in UPSTAn.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

2

TXSTPIC/

UNDERFIC

25

-

17

-

9

-

1

TXOUTIC

8

-

0

RXINIC

24

-

16

-

459

32059L–AVR32–01/2012

AT32UC3B

22.8.3.15

Pipe n Status Set Register

Register Name:

UPSTAnSET, n in [0..6]

Access Type:

Offset:

Read Value:

Write-Only

0x0590 + (n * 0x04)

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

25

-

17

-

24

-

16

-

15

-

14

-

13

-

12

NBUSYBKS

11

-

10

-

9

-

8

-

7

SHORT

PACKETIS

6

RXSTALLDIS

/

CRCERRIS

5

OVERFIS

4

NAKEDIS

3

PERRIS

2

TXSTPIS/

UNDERFIS

1

TXOUTIS

0

RXINIS

Writing a one to a bit in this register will set the corresponding bit in UPSTAn, what may be useful for test or debug purposes.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

460

32059L–AVR32–01/2012

AT32UC3B

22.8.3.16

Pipe n Control Register

Register Name:

UPCONn, n in [0..6]

Access Type:

Offset:

Reset Value:

Read-Only

0x05C0 + (n * 0x04)

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

RSTDT

25

-

17

PFREEZE

24

-

16

PDISHDMA

15

-

14

FIFOCON

13

-

12

NBUSYBKE

11

-

10

-

9

-

8

-

7

SHORT

PACKETIE

6

RXSTALLDE

/CRCERRE

5

OVERFIE

4

NAKEDE

3

PERRE

2

TXSTPE/

UNDERFIE

1

TXOUTE

0

RXINE

• RSTDT: Reset Data Toggle

This bit is set when the RSTDTS bit is written to one. This will reset the Data Toggle to its initial value for the current Pipe.

This bit is cleared when proceed.

• PFREEZE: Pipe Freeze

This bit is set when the PFREEZES bit is written to one or when the pipe is not configured or when a STALL handshake has been received on this Pipe or when an error occurs on the Pipe (PERR is one) or when (INRQ+1) In requests have been processed or when after a Pipe reset (UPRST.PRSTn rising) or a Pipe Enable (UPRST.PEN rising). This will Freeze the Pipe requests generation.

This bit is cleared when the PFREEZEC bit is written to one. This will enable the Pipe request generation.

• PDISHDMA: Pipe Interrupts Disable HDMA Request Enable

See the UECONn.EPDISHDMA bit description.

• FIFOCON: FIFO Control

For OUT and SETUP Pipe:

This bit is set when the current bank is free, at the same time than TXOUTI or TXSTPI.

This bit is cleared when the FIFOCONC bit is written to one. This will send the FIFO data and switch the bank.

For IN Pipe:

This bit is set when a new IN message is stored in the current bank, at the same time than RXINI.

This bit is cleared when the FIFOCONC bit is written to one. This will free the current bank and switch to the next bank.

• NBUSYBKE: Number of Busy Banks Interrupt Enable

This bit is set when the NBUSYBKES bit is written to one.This will enable the Transmitted IN Data interrupt (NBUSYBKE).

This bit is cleared when the NBUSYBKEC bit is written to one. This will disable the Transmitted IN Data interrupt (NBUSYBKE).

• SHORTPACKETIE: Short Packet Interrupt Enable

This bit is set when the SHORTPACKETES bit is written to one. This will enable the Transmitted IN Data IT

(SHORTPACKETIE).

This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Transmitted IN Data IT

(SHORTPACKETE).

461

32059L–AVR32–01/2012

AT32UC3B

• RXSTALLDE: Received STALLed Interrupt Enable

This bit is set when the RXSTALLDES bit is written to one. This will enable the Transmitted IN Data interrupt (RXSTALLDE).

This bit is cleared when the RXSTALLDEC bit is written to one. This will disable the Transmitted IN Data interrupt

(RXSTALLDE).

• CRCERRE: CRC Error Interrupt Enable

This bit is set when the CRCERRES bit is written to one. This will enable the Transmitted IN Data interrupt (CRCERRE).

This bit is cleared when the CRCERREC bit is written to one. This will disable the Transmitted IN Data interrupt (CRCERRE).

• OVERFIE: Overflow Interrupt Enable

This bit is set when the OVERFIES bit is written to one. This will enable the Transmitted IN Data interrupt (OVERFIE).

This bit is cleared when the OVERFIEC bit is written to one. This will disable the Transmitted IN Data interrupt (OVERFIE).

• NAKEDE: NAKed Interrupt Enable

This bit is set when the NAKEDES bit is written to one. This will enable the Transmitted IN Data interrupt (NAKEDE).

This bit is cleared when the NAKEDEC bit is written to one. This will disable the Transmitted IN Data interrupt (NAKEDE).

• PERRE: Pipe Error Interrupt Enable

This bit is set when the PERRES bit is written to one. This will enable the Transmitted IN Data interrupt (PERRE).

This bit is cleared when the PERREC bit is written to one. This will disable the Transmitted IN Data interrupt (PERRE).

• TXSTPE: Transmitted SETUP Interrupt Enable

This bit is set when the TXSTPES bit is written to one. This will enable the Transmitted IN Data interrupt (TXSTPE).

This bit is cleared when the TXSTPEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXSTPE).

• UNDERFIE: Underflow Interrupt Enable

This bit is set when the UNDERFIES bit is written to one. This will enable the Transmitted IN Data interrupt (UNDERFIE).

This bit is cleared when the UNDERFIEC bit is written to one. This will disable the Transmitted IN Data interrupt (UNDERFIE).

• TXOUTE: Transmitted OUT Data Interrupt Enable

This bit is set when the TXOUTES bit is written to one. This will enable the Transmitted IN Data interrupt (TXOUTE).

This bit is cleared when the TXOUTEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXOUTE).

• RXINE: Received IN Data Interrupt Enable

This bit is set when the RXINES bit is written to one. This will enable the Transmitted IN Data interrupt (RXINE).

This bit is cleared when the RXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (RXINE).

462

32059L–AVR32–01/2012

AT32UC3B

22.8.3.17

Pipe n Control Clear Register

Register Name:

UPCONnCLR, n in [0..6]

Access Type:

Offset:

Read Value:

Write-Only

0x0620 + (n * 0x04)

0x00000000

31

-

23

-

15

-

30

-

22

-

14

FIFOCONC

29

-

21

-

13

-

28

-

20

-

12

NBUSYBKEC

27

-

19

-

11

-

26

-

18

-

10

-

7

SHORT

PACKETIEC

6

RXSTALLDEC

/CRCERREC

5

OVERFIEC

4

NAKEDEC

3

PERREC

2

TXSTPEC/

UNDERFIEC

Writing a one to a bit in this register will clear the corresponding bit in UPCONn.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

25

-

24

-

17 16

PFREEZEC PDISHDMAC

9

-

1

TXOUTEC

8

-

0

RXINEC

463

32059L–AVR32–01/2012

AT32UC3B

22.8.3.18

Pipe n Control Set Register

Register Name:

UPCONnSET, n in [0..6]

Access Type:

Offset:

Read Value:

Write-Only

0x05F0 + (n * 0x04)

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

NBUSYBKES

27

-

19

-

11

-

26

-

18

RSTDTS

10

-

7

SHORT

PACKETIES

6

RXSTALLDES

/

CRCERRES

5

OVERFIES

4

NAKEDES

3

PERRES

Writing a one to a bit in this register will set the corresponding bit in UPCONn.

Writing a zero to a bit in this register has no effect.

This bit always reads as zero.

2

TXSTPES/

UNDERFIES

25

-

24

-

17 16

PFREEZES PDISHDMAS

9

-

1

TXOUTES

8

-

0

RXINES

464

32059L–AVR32–01/2012

AT32UC3B

22.8.3.19

Pipe n IN Request Register

Register Name:

UPINRQn, n in [0..6]

Access Type:

Offset:

Reset Value:

Read/Write

0x0650 + (n * 0x04)

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

25

-

17

-

24

-

16

-

15

-

14

-

13

-

12

-

11

-

10

-

9

-

8

INMODE

7 6 5 4 3 2 1 0

INRQ

• INMODE: IN Request Mode

Writing a one to this bit will allow the USBB to perform infinite IN requests when the Pipe is not frozen.

Writing a zero to this bit will perform a pre-defined number of IN requests. This number is the INRQ field.

• INRQ: IN Request Number before Freeze

This field contains the number of IN transactions before the USBB freezes the pipe. The USBB will perform (INRQ+1) IN requests before to freeze the Pipe. This counter is automatically decreased by 1 each time a IN request has been successfully performed.

This register has no effect when the INMODE bit is one (infinite IN requests generation till the pipe is not frozen).

465

32059L–AVR32–01/2012

AT32UC3B

22.8.3.20

Pipe n Error Register

Register Name:

UPERRn, n in [0..6]

Access Type:

Offset:

Reset Value:

Read/Write

0x0680 + (n * 0x04)

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

25

-

17

-

24

-

16

-

15

-

14

-

13

-

12

-

11

-

10

-

9

-

8

-

7

-

6

COUNTER

5 4

CRC16

3

TIMEOUT

2

PID

1

DATAPID

0

DATATGL

• COUNTER: Error Counter

This field is incremented each time an error occurs (CRC16, TIMEOUT, PID, DATAPID or DATATGL).

This field is cleared when receiving a good usb packet without any error.

When this field reaches 3 (i.e., 3 consecutive errors), this pipe is automatically frozen (UPCONn.PFREEZE is set).

Writing 0b00 to this field will clear the counter.

• CRC16: CRC16 Error

This bit is set when a CRC16 error has been detected.

Writing a zero to this bit will clear the bit.

Writing a one to this bit has no effect.

• TIMEOUT: Time-Out Error

This bit is set when a Time-Out error has been detected.

Writing a zero to this bit will clear the bit.

Writing a one to this bit has no effect.

• PID: PID Error

This bit is set when a PID error has been detected.

Writing a zero to this bit will clear the bit.

Writing a one to this bit has no effect.

• DATAPID: Data PID Error

This bit is set when a Data PID error has been detected.

Writing a zero to this bit will clear the bit.

Writing a one to this bit has no effect.

• DATATGL: Data Toggle Error

This bit is set when a Data Toggle error has been detected.

Writing a zero to this bit will clear the bit.

Writing a one to this bit has no effect.

466

32059L–AVR32–01/2012

AT32UC3B

22.8.3.21

Host DMA Channel n Next Descriptor Address Register

Register Name:

UHDMAnNEXTDESC, n in [1..6]

Access Type:

Offset:

Reset Value:

Read/Write

0x0710 + (n - 1) * 0x10

0x00000000

31 30 29

23

15

7

22

14

6 5

NXTDESCADDR[7:4]

Same as Section 22.8.2.17

.

21

13

28 27

NXTDESCADDR[31:24]

20 19

NXTDESCADDR[23:16]

12 11

NXTDESCADDR[15:8]

4 3

-

10

2

-

26

18

9

1

-

25

17

8

0

-

24

16

467

32059L–AVR32–01/2012

AT32UC3B

22.8.3.22

Host DMA Channel n HSB Address Register

Register Name:

UHDMAnADDR, n in [1..6]

Access Type:

Offset:

Reset Value:

Read/Write

0x0714 + (n - 1) * 0x10

0x00000000

31 30 29

23

15

7

22

14

6

21

13

5

28 27

HSBADDR[31:24]

20 19

HSBADDR[23:16]

12 11

HSBADDR[15:8]

4

HSBADDR[7:0]

3

Same as Section 22.8.2.18

.

10

2

26

18

9

1

25

17

8

0

24

16

468

32059L–AVR32–01/2012

AT32UC3B

22.8.3.23

USB Host DMA Channel n Control Register

Register Name:

UHDMAnCONTROL, n in [1..6]

Access Type:

Offset:

Reset Value:

Read/Write

0x0718 + (n - 1) * 0x10

0x00000000

31

23

30

22

29

21

28 27

CHBYTELENGTH[15:8]

20 19

CHBYTELENGTH[7:0]

12

-

11

-

26

18

25

17

15

-

14

-

13

-

10

-

9

-

7

BURSTLOC

KEN

6

DESCLD

IRQEN

5

EOBUFF

IRQEN

4

EOTIRQEN

3

DMAENDEN

2

BUFFCLOSE

INEN

1

LDNXTCHD

ESCEN

Same as Section 22.8.2.19

.

(just replace the IN endpoint term by OUT endpoint, and vice-versa)

24

16

8

-

0

CHEN

469

32059L–AVR32–01/2012

AT32UC3B

22.8.3.24

USB Host DMA Channel n Status Register

Register Name:

UHDMAnSTATUS, n in [1..6]

Access Type:

Offset:

Reset Value:

Read/Write

0x071C + (n - 1) * 0x10

0x00000000

31

23

30

22

29

21

15

-

14

-

13

-

7

-

6

DESCLD

STA

Same as Section 22.8.2.20

.

5

EOCHBUFFS

TA

12

-

4

EOTSTA

28 27

CHBYTECNT[15:8]

20 19

CHBYTECNT[7:0]

3

-

11

-

26

18

2

-

10

-

25

17

9

-

1

CHACTIVE

8

-

0

CHEN

24

16

470

32059L–AVR32–01/2012

AT32UC3B

22.8.4

USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)

The application has access to the physical DPRAM reserved for the Endpoint/Pipe through a

64KB virtual address space. The application can access anywhere in the virtual 64KB segment

(linearly or fixedly) as the DPRAM Fifo address increment is fully handled by hardware. Byte, half-word and word access are supported. Data should be access in a big-endian way.

For instance, if the application wants to write into the Endpoint/Pipe3, it can access anywhere in the USBFIFO3DATA HSB segment address. i.e : an access to the 0x30000 offset, is strictly equivalent to an access to the 0x3FFFC offset.

Note that the virtual address space size (64KB) has nothing to do with the Endpoint/Pipe size.

Disabling the USBB (by writing a zero to the USBE bit) does not reset the DPRAM.

32059L–AVR32–01/2012

471

AT32UC3B

23. Timer/Counter (TC)

Rev: 2.2.2.3

23.1 Features

Three 16-bit Timer Counter channels

A wide range of functions including:

– Frequency measurement

– Event counting

– Interval measurement

– Pulse generation

– Delay timing

– Pulse width modulation

– Up/down capabilities

Each channel is user-configurable and contains:

– Three external clock inputs

– Five internal clock inputs

– Two multi-purpose input/output signals

Internal interrupt signal

Two global registers that act on all three TC channels

23.2 Overview

The Timer Counter (TC) includes three identical 16-bit Timer Counter channels.

Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation.

Each channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts.

The TC block has two global registers which act upon all three TC channels.

The Block Control Register (BCR) allows the three channels to be started simultaneously with the same instruction.

The Block Mode Register (BMR) defines the external clock inputs for each channel, allowing them to be chained.

472

32059L–AVR32–01/2012

AT32UC3B

23.3 Block Diagram

Figure 23-1. TC Block Diagram

TIMER_CLOCK1

TIMER_CLOCK2

TIMER_CLOCK3

TIMER_CLOCK4

TIMER_CLOCK5

TCLK0

TCLK1

TCLK2

TIOA1

TIOA2

TCLK0

TCLK1

TIOA0

TIOA2

TCLK2

TCLK0

TCLK1

TCLK2

TIOA0

TIOA1

TC0XC0S

XC0

XC1

XC2

Timer/Counter

Channel 0

TIOA

TIOB

SYNC

INT0

TIOA0

TIOB0

TC1XC1S

XC0

XC1

XC2

Timer/Counter

Channel 1

TIOA

TIOB

SYNC

INT1

TIOA1

TIOB1

XC0

XC1

XC2

TC2XC2S

Timer/Counter

Channel 2

TIOA

TIOB

SYNC

INT2

TIOA2

TIOB2

Timer Count er

Interrupt

Controller

I/O

Contr oller

CLK0

CLK1

CLK2

A0

B0

A1

B1

A2

B2

23.4 I/O Lines Description

Table 23-1.

I/O Lines Description

Pin Name

CLK0-CLK2

Description

External Clock Input

A0-A2

B0-B2

I/O Line A

I/O Line B

Type

Input

Input/Output

Input/Output

23.5 Product Dependencies

In order to use this module, other parts of the system must be configured correctly, as described below.

23.5.1

I/O Lines

The pins used for interfacing the compliant external devices may be multiplexed with I/O lines.

The user must first program the I/O Controller to assign the TC pins to their peripheral functions.

473

32059L–AVR32–01/2012

AT32UC3B

23.5.2

23.5.3

23.5.4

Power Management

If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning and resume operation after the system wakes up from sleep mode.

Clocks

The clock for the TC bus interface (CLK_TC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the

TC before disabling the clock, to avoid freezing the TC in an undefined state.

Interrupts

The TC interrupt request line is connected to the interrupt controller. Using the TC interrupt requires the interrupt controller to be programmed first.

23.5.5

23.6 Functional Description

23.6.1

TC Description

The three channels of the Timer Counter are independent and identical in operation. The regis-

ters for channel programming are listed in Figure 23-3 on page 489

.

23.6.1.1

Channel I/O Signals

As described in Figure 23-1 on page 473

, each Channel has the following I/O signals.

Table 23-2.

Channel I/O Signals Description

Block/Channel Signal Name

XC0, XC1, XC2

Channel Signal

TIOA

TIOB

INT

SYNC

Description

External Clock Inputs

Capture mode: Timer Counter Input

Waveform mode: Timer Counter Output

Capture mode: Timer Counter Input

Waveform mode: Timer Counter Input/Output

Interrupt Signal Output

Synchronization Input Signal

23.6.1.2

Debug Operation

The Timer Counter clocks are frozen during debug operation, unless the OCD system keeps peripherals running in debug operation.

16-bit counter

Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the Counter Overflow Status bit in the Channel n Status Register (SRn.COVFS) is set.

The current value of the counter is accessible in real time by reading the Channel n Counter

Value Register (CVn). The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock.

474

32059L–AVR32–01/2012

AT32UC3B

23.6.1.3

Clock selection

At block level, input clock signals of each channel can either be connected to the external inputs

TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals A0, A1 or A2 for

chaining by writing to the BMR register. See Figure 23-2 on page 475

.

Each channel can independently select an internal or external clock source for its counter:

• Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3,

TIMER_CLOCK4, TIMER_CLOCK5. See the Module Configuration Chapter for details about the connection of these clock sources.

• External clock signals: XC0, XC1 or XC2. See the Module Configuration Chapter for details about the connection of these clock sources.

This selection is made by the Clock Selection field in the Channel n Mode Register

(CMRn.TCCLKS).

The selected clock can be inverted with the Clock Invert bit in CMRn (CMRn.CLKI). This allows counting on the opposite edges of the clock.

The burst function allows the clock to be validated when an external signal is high. The Burst

Signal Selection field in the CMRn register (CMRn.BURST) defines this signal.

Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the

CLK_TC period. The external clock frequency must be at least 2.5 times lower than the CLK_TC.

Figure 23-2. Clock Selection

TCCLKS

TIMER_CLOCK1

TIMER_CLOCK2

TIMER_CLOCK3

TIMER_CLOCK4

TIMER_CLOCK5

XC0

XC1

XC2

CLKI

Selected

Clock

BURST

1

23.6.1.4

Clock control

The clock of each counter can be controlled in two different ways: it can be enabled/disabled

and started/stopped. See Figure 23-3 on page 476

.

475

32059L–AVR32–01/2012

AT32UC3B

• The clock can be enabled or disabled by the user by writing to the Counter Clock

Enable/Disable Command bits in the Channel n Clock Control Register (CCRn.CLKEN and

CCRn.CLKDIS). In Capture mode it can be disabled by an RB load event if the Counter

Clock Disable with RB Loading bit in CMRn is written to one (CMRn.LDBDIS). In Waveform mode, it can be disabled by an RC Compare event if the Counter Clock Disable with RC

Compare bit in CMRn is written to one (CMRn.CPCDIS). When disabled, the start or the stop actions have no effect: only a CLKEN command in CCRn can re-enable the clock. When the clock is enabled, the Clock Enabling Status bit is set in SRn (SRn.CLKSTA).

• The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. In Capture mode the clock can be stopped by an RB load event if the

Counter Clock Stopped with RB Loading bit in CMRn is written to one (CMRn.LDBSTOP). In

Waveform mode it can be stopped by an RC compare event if the Counter Clock Stopped with RC Compare bit in CMRn is written to one (CMRn.CPCSTOP). The start and the stop commands have effect only if the clock is enabled.

Figure 23-3. Clock Control

Selected

Clock

Trigger

CLKSTA CLKEN CLKDIS

Q S

R

Q S

R

23.6.1.5

Stop

Event

Disable

Event

Counter

Clock

TC operating modes

Each channel can independently operate in two different modes:

• Capture mode provides measurement on signals.

• Waveform mode provides wave generation.

The TC operating mode selection is done by writing to the Wave bit in the CCRn register

(CCRn.WAVE).

In Capture mode, TIOA and TIOB are configured as inputs.

In Waveform mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger.

476

32059L–AVR32–01/2012

AT32UC3B

23.6.1.6

Trigger

A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode.

The following triggers are common to both modes:

• Software Trigger: each channel has a software trigger, available by writing a one to the

Software Trigger Command bit in CCRn (CCRn.SWTRG).

• SYNC: each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing a one to the Synchro Command bit in the BCR register

(BCR.SYNC).

• Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if the RC Compare Trigger Enable bit in CMRn

(CMRn.CPCTRG) is written to one.

The channel can also be configured to have an external trigger. In Capture mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform mode, an external event can be programmed to be one of the following signals: TIOB, XC0, XC1, or XC2. This external event can then be programmed to perform a trigger by writing a one to the External Event Trigger Enable bit in CMRn (CMRn.ENETRG).

If an external trigger is used, the duration of the pulses must be longer than the CLK_TC period in order to be detected.

Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock.

23.6.2

23.6.2.1

Capture Operating Mode

This mode is entered by writing a zero to the CMRn.WAVE bit.

Capture mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs.

Figure 23-4 on page 479 shows the configuration of the TC channel when programmed in Cap-

ture mode.

Capture registers A and B

Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA.

The RA Loading Selection field in CMRn (CMRn.LDRA) defines the TIOA edge for the loading of the RA register, and the RB Loading Selection field in CMRn (CMRn.LDRB) defines the TIOA edge for the loading of the RB register.

RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA.

RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.

Loading RA or RB before the read of the last value loaded sets the Load Overrun Status bit in

SRn (SRn.LOVRS). In this case, the old value is overwritten.

477

32059L–AVR32–01/2012

AT32UC3B

23.6.2.2

Trigger conditions

In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined.

The TIOA or TIOB External Trigger Selection bit in CMRn (CMRn.ABETRG) selects TIOA or

TIOB input signal as an external trigger. The External Trigger Edge Selection bit in CMRn

(CMRn.ETREDG) defines the edge (rising, falling or both) detected to generate an external trigger. If CMRn.ETRGEDG is zero (none), the external trigger is disabled.

32059L–AVR32–01/2012

478

Figure 23-4. Capture Mode

CPCS

LOVRS

COVFS

LDRBS

LDRAS

ETRGS

SR

IMR

AT32UC3B

32059L–AVR32–01/2012

479

AT32UC3B

23.6.3

23.6.3.1

Waveform Operating Mode

Waveform operating mode is entered by writing a one to the CMRn.WAVE bit.

In Waveform operating mode the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of oneshot or repetitive pulses.

In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event.

Figure 23-5 on page 481 shows the configuration of the TC channel when programmed in

Waveform operating mode.

Waveform selection

Depending on the Waveform Selection field in CMRn (CMRn.WAVSEL), the behavior of CVn varies.

With any selection, RA, RB and RC can all be used as compare registers.

RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output

(if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs.

480

32059L–AVR32–01/2012

32059L–AVR32–01/2012

Figure 23-5. Waveform Mode ller ro ont utC tp Ou oller tr on utC tp Ou

AT32UC3B

CPCS

CPBS

CPAS

COVFS

ETRGS

SR

IMR

481

AT32UC3B

23.6.3.2

WAVSEL = 0

When CMRn.WAVSEL is zero, the value of CVn is incremented from 0 to 0xFFFF. Once

0xFFFF has been reached, the value of CVn is reset. Incrementation of CVn starts again and

the cycle continues. See Figure 23-6 on page 482

.

An external event trigger or a software trigger can reset the value of CVn. It is important to note

that the trigger may occur at any time. See Figure 23-7 on page 483

.

RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1).

Figure 23-6. WAVSEL= 0 Without Trigger

Counter Value

0xFFFF

Counter cleared by compare match with

0xFFFF

RC

RB

RA

Time

Waveform Examples

TIOB

TIOA

482

32059L–AVR32–01/2012

AT32UC3B

Figure 23-7. WAVSEL= 0 With Trigger

Counter Value

0xFFFF

RC

RB

RA

Counter cleared by compare match with 0xFFFF

Counter cleared by trigger

Waveform Examples

TIOB

Time

TIOA

23.6.3.3

WAVSEL = 2

When CMRn.WAVSEL is two, the value of CVn is incremented from zero to the value of RC, then automatically reset on a RC Compare. Once the value of CVn has been reset, it is then

incremented and so on. See Figure 23-8 on page 484

.

It is important to note that CVn can be reset at any time by an external event or a software trig-

ger if both are programmed correctly. See Figure 23-9 on page 484

.

In addition, RC Compare can stop the counter clock (CMRn.CPCSTOP) and/or disable the counter clock (CMRn.CPCDIS = 1).

483

32059L–AVR32–01/2012

Figure 23-8. WAVSEL = 2 Without Trigger

Counter Value

0xFFFF

Counter cleared by compare match with RC

RC

RB

RA

AT32UC3B

Waveform Examples

TIOB

Time

TIOA

Figure 23-9. WAVSEL = 2 With Trigger

Counter Value

0xFFFF

Counter cleared by compare match with RC

R

C

Counter cleared by trigger

R

B

R

A

Time

Waveform Examples

TIOB

TIOA

23.6.3.4

WAVSEL = 1

When CMRn.WAVSEL is one, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of CVn is decremented to 0, then re-incremented to 0xFFFF and so on.

See Figure 23-10 on page 485 .

484

32059L–AVR32–01/2012

AT32UC3B

A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See

Figure 23-11 on page 485

.

RC Compare cannot be programmed to generate a trigger in this configuration.

At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1).

Figure 23-10. WAVSEL = 1 Without Trigger

Counter Value

0xFFFF

Counter decremented by compare match with 0xFFFF

RC

RB

RA

Time

Waveform Examples

TIOB

TIOA

Figure 23-11. WAVSEL = 1 With Trigger

Counter Value

Counter decremented by compare match with 0xFFFF

0xFFFF

Counter decremented by trigger

RC

RB

RA

Counter incremented by trigger

Time

Waveform Examples

TIOB

TIOA

485

32059L–AVR32–01/2012

AT32UC3B

23.6.3.5

WAVSEL = 3

When CMRn.WAVSEL is three, the value of CVn is incremented from zero to RC. Once RC is reached, the value of CVn is decremented to zero, then re-incremented to RC and so on. See

Figure 23-12 on page 486

.

A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See

Figure 23-13 on page 487

.

RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock

(CMRn.CPCDIS = 1).

Figure 23-12. WAVSEL = 3 Without Trigger

Counter Value

0xFFFF

Counter cleared by compare match with RC

RC

RB

RA

Time

Waveform Examples

TIOB

TIOA

486

32059L–AVR32–01/2012

AT32UC3B

Figure 23-13. WAVSEL = 3 With Trigger

Counter Value

0xFFFF

RC

RB

RA

Counter decremented by compare match with RC

Counter decremented by trigger

Counter incremented by trigger

Time

Waveform Examples

TIOB

TIOA

23.6.3.6

23.6.3.7

External event/trigger conditions

An external event can be programmed to be detected on one of the clock sources (XC0, XC1,

XC2) or TIOB. The external event selected can then be used as a trigger.

The External Event Selection field in CMRn (CMRn.EEVT) selects the external trigger. The

External Event Edge Selection field in CMRn (CMRn.EEVTEDG) defines the trigger edge for each of the possible external triggers (rising, falling or both). If CMRn.EEVTEDG is written to zero, no external event is defined.

If TIOB is defined as an external event signal (CMRn.EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no

IRQs. In this case the TC channel can only generate a waveform on TIOA.

When an external event is defined, it can be used as a trigger by writing a one to the

CMRn.ENETRG bit.

As in Capture mode, the SYNC signal and the software trigger are also available as triggers. RC

Compare can also be used as a trigger depending on the CMRn.WAVSEL field.

Output controller

The output controller defines the output level changes on TIOA and TIOB following an event.

TIOB control is used only if TIOB is defined as output (not as an external event).

The following events control TIOA and TIOB:

• software trigger

• external event

• RC compare

RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the following fields in CMRn:

• RC Compare Effect on TIOB (CMRn.BCPC)

487

32059L–AVR32–01/2012

• RB Compare Effect on TIOB (CMRn.BCPB)

• RC Compare Effect on TIOA (CMRn.ACPC)

• RA Compare Effect on TIOA (CMRn.ACPA)

AT32UC3B

32059L–AVR32–01/2012

488

AT32UC3B

23.7 User Interface

Table 23-3.

TC Register Memory Map

0x94

0x98

0x9C

0xA0

0xA4

0xA8

0xAC

0xC0

0x5C

0x60

0x64

0x68

0x6C

0x80

0x84

0x90

0xC4

0xF8

0xFC

0x24

0x28

0x2C

0x40

0x44

0x50

0x54

0x58

Offset

0x00

0x04

0x10

0x14

0x18

0x1C

0x20

Register

Channel 0 Control Register

Channel 0 Mode Register

Channel 0 Counter Value

Channel 0 Register A

Channel 0 Register B

Channel 0 Register C

Channel 0 Status Register

Interrupt Enable Register

Channel 0 Interrupt Disable Register

Channel 0 Interrupt Mask Register

Channel 1 Control Register

Channel 1 Mode Register

Channel 1 Counter Value

Channel 1 Register A

Channel 1 Register B

Channel 1 Register C

Channel 1 Status Register

Channel 1 Interrupt Enable Register

Channel 1 Interrupt Disable Register

Channel 1 Interrupt Mask Register

Channel 2 Control Register

Channel 2 Mode Register

Channel 2 Counter Value

Channel 2 Register A

Channel 2 Register B

Channel 2 Register C

Channel 2 Status Register

Channel 2 Interrupt Enable Register

Channel 2 Interrupt Disable Register

Channel 2 Interrupt Mask Register

Block Control Register

Block Mode Register

Features Register

Version Register

RA2

RB2

RC2

SR2

IER2

IDR2

IMR2

BCR

RC1

SR1

IER1

IDR1

IMR1

CCR2

CMR2

CV2

BMR

FEATURES

VERSION

Register Name

CCR0

CMR0

CV0

RA0

RB0

RC0

SR0

IER0

IDR0

IMR0

CCR1

CMR1

CV1

RA1

RB1

Access

Write-only

Read/Write

Read-only

Read/Write

(1)

Read/Write

(1)

Read/Write

Read-only

Write-only

Write-only

Read-only

Write-only

Read/Write

Read-only

Read/Write

(1)

Read/Write

(1)

Read/Write

Read-only

Write-only

Write-only

Read-only

Write-only

Read/Write

Read-only

Read/Write

(1)

Read/Write

(1)

Read/Write

Read-only

Write-only

Write-only

Read-only

Write-only

Read/Write

Read-only

Read-only

32059L–AVR32–01/2012

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

-

(2)

-

(2)

Reset

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

489

AT32UC3B

Notes: 1. Read-only if CMRn.WAVE is zero.

2. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.

32059L–AVR32–01/2012

490

23.7.1

Name:

Channel Control Register

CCR

Access Type:

Offset:

Reset Value:

Write-only

0x00 + n * 0x40

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

15

-

14

-

13

-

12

-

11

-

10

-

9

-

7

-

6

-

5

-

4

-

3

-

2

SWTRG

1

CLKDIS

• SWTRG: Software Trigger Command

1: Writing a one to this bit will perform a software trigger: the counter is reset and the clock is started.

0: Writing a zero to this bit has no effect.

• CLKDIS: Counter Clock Disable Command

1: Writing a one to this bit will disable the clock.

0: Writing a zero to this bit has no effect.

• CLKEN: Counter Clock Enable Command

1: Writing a one to this bit will enable the clock if CLKDIS is not one.

0: Writing a zero to this bit has no effect.

25

-

17

-

AT32UC3B

8

-

0

CLKEN

24

-

16

-

491

32059L–AVR32–01/2012

AT32UC3B

23.7.2

Name:

Channel Mode Register: Capture Mode

CMR

Access Type:

Offset:

Reset Value:

Read/Write

0x04 + n * 0x40

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

15

WAVE

14

CPCTRG

13

-

12

-

11

-

7

LDBDIS

6

LDBSTOP

• LDRB: RB Loading Selection

5

BURST

4

LDRB

0

1

2

3

Edge

none rising edge of TIOA falling edge of TIOA each edge of TIOA

• LDRA: RA Loading Selection

LDRA

0

1

2

3

Edge

none rising edge of TIOA falling edge of TIOA each edge of TIOA

• WAVE

1: Capture mode is disabled (Waveform mode is enabled).

0: Capture mode is enabled.

• CPCTRG: RC Compare Trigger Enable

1: RC Compare resets the counter and starts the counter clock.

0: RC Compare has no effect on the counter and its clock.

• ABETRG: TIOA or TIOB External Trigger Selection

1: TIOA is used as an external trigger.

3

CLKI

27

-

19

LDRB

26

-

18

10

ABETRG

2

25

-

17

1

TCCLKS

LDRA

9

ETRGEDG

8

0

24

-

16

492

32059L–AVR32–01/2012

0: TIOB is used as an external trigger.

• ETRGEDG: External Trigger Edge Selection

ETRGEDG

0

1

2

3

Edge

none rising edge falling edge each edge

• LDBDIS: Counter Clock Disable with RB Loading

1: Counter clock is disabled when RB loading occurs.

0: Counter clock is not disabled when RB loading occurs.

• LDBSTOP: Counter Clock Stopped with RB Loading

1: Counter clock is stopped when RB loading occurs.

0: Counter clock is not stopped when RB loading occurs.

• BURST: Burst Signal Selection

BURST

0

1

2

3

Burst Signal Selection

The clock is not gated by an external signal

XC0 is ANDed with the selected clock

XC1 is ANDed with the selected clock

XC2 is ANDed with the selected clock

• CLKI: Clock Invert

1: The counter is incremented on falling edge of the clock.

0: The counter is incremented on rising edge of the clock.

• TCCLKS: Clock Selection

6

7

4

5

2

3

0

1

TIMER_CLOCK1

TIMER_CLOCK2

TIMER_CLOCK3

TIMER_CLOCK4

TIMER_CLOCK5

XC0

XC1

XC2

32059L–AVR32–01/2012

AT32UC3B

493

AT32UC3B

23.7.3

Name:

Channel Mode Register: Waveform Mode

CMR

Access Type:

Offset:

Reset Value:

Read/Write

0x04 + n * 0x40

0x00000000

31

BSWTRG

30

23

ASWTRG

22

15

WAVE

14

29

21

WAVSEL

13

BEEVT

AEEVT

28

20

12

ENETRG

7

CPCDIS

6

CPCSTOP

5

BURST

• BSWTRG: Software Trigger Effect on TIOB

4

BSWTRG

0

1

2

3

Effect

none set clear toggle

• BEEVT: External Event Effect on TIOB

BEEVT

0

1

2

3

Effect

none set clear toggle

27

BCPC

26

19 18

ACPC

11 10

EEVT

3

CLKI

2

25 24

BCPB

17 16

1

TCCLKS

ACPA

9

EEVTEDG

8

0

494

32059L–AVR32–01/2012

• BCPC: RC Compare Effect on TIOB

BCPC

0

1

2

3

Effect

none set clear toggle

• BCPB: RB Compare Effect on TIOB

BCPB

0

1

2

3

Effect

none set clear toggle

• ASWTRG: Software Trigger Effect on TIOA

ASWTRG

0

1

2

3

Effect

none set clear toggle

• AEEVT: External Event Effect on TIOA

AEEVT

0

1

2

3

Effect

none set clear toggle

• ACPC: RC Compare Effect on TIOA

ACPC

0

1

2

3

Effect

none set clear toggle

32059L–AVR32–01/2012

AT32UC3B

495

AT32UC3B

• ACPA: RA Compare Effect on TIOA

ACPA

0

1

2

3

Effect

none set clear toggle

• WAVE

1: Waveform mode is enabled.

0: Waveform mode is disabled (Capture mode is enabled).

• WAVSEL: Waveform Selection

WAVSEL

0

1

2

3

Effect

UP mode without automatic trigger on RC Compare

UPDOWN mode without automatic trigger on RC Compare

UP mode with automatic trigger on RC Compare

UPDOWN mode with automatic trigger on RC Compare

• ENETRG: External Event Trigger Enable

1: The external event resets the counter and starts the counter clock.

0: The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output.

• EEVT: External Event Selection

EEVT

0

1

2

Signal selected as external event

TIOB

XC0

XC1

TIOB Direction

input

(1) output output

3 XC2 output

Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subse-

quently no IRQs

.

• EEVTEDG: External Event Edge Selection

EEVTEDG

0

1

2

3

Edge

none rising edge falling edge each edge

• CPCDIS: Counter Clock Disable with RC Compare

1: Counter clock is disabled when counter reaches RC.

0: Counter clock is not disabled when counter reaches RC.

496

32059L–AVR32–01/2012

• CPCSTOP: Counter Clock Stopped with RC Compare

1: Counter clock is stopped when counter reaches RC.

0: Counter clock is not stopped when counter reaches RC.

• BURST: Burst Signal Selection

BURST

0

1

2

3

Burst Signal Selection

The clock is not gated by an external signal.

XC0 is ANDed with the selected clock.

XC1 is ANDed with the selected clock.

XC2 is ANDed with the selected clock.

• CLKI: Clock Invert

1: Counter is incremented on falling edge of the clock.

0: Counter is incremented on rising edge of the clock.

• TCCLKS: Clock Selection

TCCLKS

0

1

4

5

2

3

6

7

Clock Selected

TIMER_CLOCK1

TIMER_CLOCK2

TIMER_CLOCK3

TIMER_CLOCK4

TIMER_CLOCK5

XC0

XC1

XC2

AT32UC3B

497

32059L–AVR32–01/2012

AT32UC3B

23.7.4

Name:

Channel Counter Value Register

CV

Access Type:

Offset:

Reset Value:

Read-only

0x10 + n * 0x40

0x00000000

31

-

23

-

15

30

-

22

-

14

29

-

21

-

13

7 6 5

28

-

20

-

12

CV[15:8]

11

4 3

CV[7:0]

27

-

19

-

• CV: Counter Value

CV contains the counter value in real time.

26

-

18

-

10

2

25

-

17

-

9

1

24

-

16

-

8

0

498

32059L–AVR32–01/2012

23.7.5

Name:

Channel Register A

RA

Access Type:

Offset:

Reset Value:

Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1

0x14 + n * 0X40

0x00000000

31

-

23

-

15

7

30

-

22

-

14

6

29

-

21

-

13

5

• RA: Register A

RA contains the Register A value in real time.

28

-

20

-

12

RA[15:8]

11

4 3

RA[7:0]

27

-

19

-

26

-

18

-

10

2

25

-

17

-

9

1

AT32UC3B

24

-

16

-

8

0

499

32059L–AVR32–01/2012

23.7.6

Name:

Channel Register B

RB

Access Type:

Offset:

Reset Value:

Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1

0x18 + n * 0x40

0x00000000

31

-

23

-

15

7

30

-

22

-

14

6

29

-

21

-

13

5

• RB: Register B

RB contains the Register B value in real time.

28

-

20

-

12

RB[15:8]

11

4 3

RB[7:0]

27

-

19

-

26

-

18

-

10

2

25

-

17

-

9

1

AT32UC3B

24

-

16

-

8

0

500

32059L–AVR32–01/2012

AT32UC3B

23.7.7

Name:

Channel Register C

RC

Access Type:

Offset:

Reset Value:

Read/Write

0x1C + n * 0x40

0x00000000

31

-

23

-

15

7

30

-

22

-

14

6

29

-

21

-

13

5

• RC: Register C

RC contains the Register C value in real time.

28

-

20

-

12

RC[15:8]

11

4 3

RC[7:0]

27

-

19

-

26

-

18

-

10

2

25

-

17

-

9

1

24

-

16

-

8

0

501

32059L–AVR32–01/2012

AT32UC3B

23.7.8

Name:

Channel Status Register

SR

Access Type:

Offset:

Reset Value:

Read-only

0x20 + n * 0x40

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

26

-

18

MTIOB

10

-

25

-

17

MTIOA

9

-

24

-

16

CLKSTA

8

-

7

ETRGS

6

LDRBS

5

LDRAS

4

CPCS

3

CPBS

2

CPAS

1

LOVRS

0

COVFS

Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts.

• MTIOB: TIOB Mirror

1: TIOB is high. If CMRn.WAVE is zero, this means that TIOB pin is high. If CMRn.WAVE is one, this means that TIOB is driven high.

0: TIOB is low. If CMRn.WAVE is zero, this means that TIOB pin is low. If CMRn.WAVE is one, this means that TIOB is driven low.

• MTIOA: TIOA Mirror

1: TIOA is high. If CMRn.WAVE is zero, this means that TIOA pin is high. If CMRn.WAVE is one, this means that TIOA is driven high.

0: TIOA is low. If CMRn.WAVE is zero, this means that TIOA pin is low. If CMRn.WAVE is one, this means that TIOA is driven low.

• CLKSTA: Clock Enabling Status

1: This bit is set when the clock is enabled.

0: This bit is cleared when the clock is disabled.

• ETRGS: External Trigger Status

1: This bit is set when an external trigger has occurred.

0: This bit is cleared when the SR register is read.

• LDRBS: RB Loading Status

1: This bit is set when an RB Load has occurred and CMRn.WAVE is zero.

0: This bit is cleared when the SR register is read.

• LDRAS: RA Loading Status

1: This bit is set when an RA Load has occurred and CMRn.WAVE is zero.

0: This bit is cleared when the SR register is read.

• CPCS: RC Compare Status

1: This bit is set when an RC Compare has occurred.

0: This bit is cleared when the SR register is read.

502

32059L–AVR32–01/2012

AT32UC3B

• CPBS: RB Compare Status

1: This bit is set when an RB Compare has occurred and CMRn.WAVE is one.

0: This bit is cleared when the SR register is read.

• CPAS: RA Compare Status

1: This bit is set when an RA Compare has occurred and CMRn.WAVE is one.

0: This bit is cleared when the SR register is read.

• LOVRS: Load Overrun Status

1: This bit is set when RA or RB have been loaded at least twice without any read of the corresponding register and

CMRn.WAVE is zero.

0: This bit is cleared when the SR register is read.

• COVFS: Counter Overflow Status

1: This bit is set when a counter overflow has occurred.

0: This bit is cleared when the SR register is read.

32059L–AVR32–01/2012

503

AT32UC3B

23.7.9

Name:

Channel Interrupt Enable Register

IER

Access Type:

Offset:

Reset Value:

Write-only

0x24 + n * 0x40

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

-

7

ETRGS

6

LDRBS

5

LDRAS

4

CPCS

3

CPBS

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will set the corresponding bit in IMR.

10

-

2

CPAS

26

-

18

-

9

-

1

LOVRS

25

-

17

-

8

-

0

COVFS

24

-

16

-

504

32059L–AVR32–01/2012

AT32UC3B

23.7.10

Channel Interrupt Disable Register

Name:

IDR

Access Type:

Offset:

Reset Value:

Write-only

0x28 + n * 0x40

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

-

10

-

7

ETRGS

6

LDRBS

5

LDRAS

4

CPCS

3

CPBS

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will clear the corresponding bit in IMR.

2

CPAS

26

-

18

-

9

-

1

LOVRS

25

-

17

-

8

-

0

COVFS

24

-

16

-

505

32059L–AVR32–01/2012

AT32UC3B

23.7.11

Channel Interrupt Mask Register

Name:

IMR

Access Type:

Offset:

Reset Value:

Read-only

0x2C + n * 0x40

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

15

-

14

-

13

-

12

-

11

-

10

-

7

ETRGS

6

LDRBS

5

LDRAS

4

CPCS

3

CPBS

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

A bit in this register is cleared when the corresponding bit in IDR is written to one.

A bit in this register is set when the corresponding bit in IER is written to one.

2

CPAS

26

-

18

-

9

-

1

LOVRS

25

-

17

-

8

-

0

COVFS

24

-

16

-

506

32059L–AVR32–01/2012

AT32UC3B

23.7.12

Block Control Register

Name:

BCR

Access Type:

Offset:

Reset Value:

Write-only

0xC0

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

28

-

20

-

27

-

19

-

26

-

18

-

25

-

17

-

24

-

16

-

15

-

14

-

13

-

12

-

11

-

10

-

9

-

8

-

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

SYNC

• SYNC: Synchro Command

1: Writing a one to this bit asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.

0: Writing a zero to this bit has no effect.

507

32059L–AVR32–01/2012

AT32UC3B

23.7.13

Block Mode Register

Name:

BMR

Access Type:

Offset:

Reset Value:

Read/Write

0xC4

0x00000000

31

-

23

-

30

-

22

-

29

-

21

-

15

-

14

-

13

-

7

-

6

-

5

TC2XC2S

• TC2XC2S: External Clock Signal 2 Selection

4

TC2XC2S

0

1

2

3

Signal Connected to XC2

TCLK2 none

TIOA0

TIOA1

• TC1XC1S: External Clock Signal 1 Selection

TC1XC1S

0

1

2

3

Signal Connected to XC1

TCLK1 none

TIOA0

TIOA2

12

-

28

-

20

-

27

-

19

-

11

-

3

TC1XC1S

2

10

-

26

-

18

-

25

-

17

-

9

-

1

TC0XC0S

0

8

-

24

-

16

-

508

32059L–AVR32–01/2012

• TC0XC0S: External Clock Signal 0 Selection

TC0XC0S

0

1

2

3

Signal Connected to XC0

TCLK0 none

TIOA1

TIOA2

AT32UC3B

32059L–AVR32–01/2012

509

AT32UC3B

23.7.14

Features Register

Name:

FEATURES

Access Type:

Offset:

Reset Value:

-

Read-only

0xF8

15

-

7

31

-

23

-

14

-

6

30

-

22

-

13

-

5

29

-

21

-

• BRPBHSB: Bridge type is PB to HSB

1: Bridge type is PB to HSB.

0: Bridge type is not PB to HSB.

• UPDNIMPL: Up/down is implemented

1: Up/down counter capability is implemented.

0: Up/down counter capability is not implemented.

• CTRSIZE: Counter size

This field indicates the size of the counter in bits.

28

-

20

-

12

-

4

CTRSIZE

3

11

-

27

-

19

-

10

-

2

26

-

18

-

25

-

17

-

9

BRPBHSB

1

24

-

16

8

UPDNIMPL

0

510

32059L–AVR32–01/2012

AT32UC3B

23.7.15

Version Register

Name:

VERSION

Access Type:

Offset:

Reset Value:

-

Read-only

0xFC

15

-

7

31

-

23

-

14

-

6

30

-

22

-

13

-

5

29

-

21

-

28

-

20

-

12

-

11

4

VERSION[7:0]

3

27

-

19

• VARIANT: Variant number

Reserved. No functionality associated.

• VERSION: Version number

Version number of the module. No functionality associated.

26

-

25

-

18

VARIANT

17

10

VERSION[11:8]

9

2 1

8

0

24

-

16

511

32059L–AVR32–01/2012

AT32UC3B

23.8 Module Configuration

The specific configuration for each TC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power

Manager section.

Table 23-4.

Module Clock Name

Module name Clock name

TC0 CLK_TC0

23.8.1

Clock Connections

Each Timer/Counter channel can independently select an internal or external clock source for its counter:

Table 23-5.

Timer/Counter clock connections

Source Name Connection

Internal TIMER_CLOCK1

TIMER_CLOCK2

TIMER_CLOCK3

TIMER_CLOCK4

TIMER_CLOCK5

32 KHz Oscillator

PBA Clock / 2

PBA Clock / 8

PBA Clock / 32

PBA Clock / 128

512

32059L–AVR32–01/2012

AT32UC3B

24. Pulse Width Modulation Controller (PWM)

Rev: 1.3.0.1

24.1 Features

7 Channels

One 20-bit Counter Per Channel

Common Clock Generator Providing Thirteen Different Clocks

– A Modulo n Counter Providing Eleven Clocks

– Two Independent Linear Dividers Working on Modulo n Counter Outputs

Independent Channels

– Independent Enable Disable Command for Each Channel

– Independent Clock Selection for Each Channel

– Independent Period and Duty Cycle for Each Channel

– Double Buffering of Period or Duty Cycle for Each Channel

– Programmable Selection of The Output Waveform Polarity for Each Channel

– Programmable Center or Left Aligned Output Waveform for Each Channel

24.2 Description

The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock.

All PWM macrocell accesses are made through registers mapped on the peripheral bus.

Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle.

513

32059L–AVR32–01/2012

AT32UC3B

24.3 Block Diagram

Figure 24-1. Pulse Width Modulation Controller Block Diagram

PWMx

Channel

Clock

Selector

PWM

Controller

Period

Update

Duty Cycle

Counter

PWMx

I/O

Controller

PWM0

Channel

Clock

Selector

Power

Manager

CLK_PWM

ClockGenerator

Period

Update

Duty Cycle

Counter

PB Interface

Peripheral

Bus

Interrupt Generator

24.4 I/O Lines Description

Each channel outputs one waveform on one external I/O line.

Table 24-1.

I/O Line Description

Name

PWMx

Description

PWM Waveform Output for channel x

Interrupt

Controller

Type

Output

PWM0

514

32059L–AVR32–01/2012

AT32UC3B

24.5 Product Dependencies

24.5.1

I/O Lines

The pins used for interfacing the PWM may be multiplexed with I/O controller lines. The programmer must first program the I/O controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the I/O controller.

Not all PWM outputs may be enabled. If an application requires only four channels, then only four I/O lines will be assigned to PWM outputs.

24.5.2

24.5.3

24.5.4

Debug operation

The PWM clock is running during debug operation.

Power Manager

The PWM clock is generated by the Power Manager. Before using the PWM, the user must ensure that the PWM clock is enabled in the Power Manager. However, if the application does not require PWM operations, the PWM clock can be stopped when not needed and be restarted later. In this case, the PWM will resume its operations where it left off.

In the PWM description, CLK_PWM is the clock of the peripheral bus to which the PWM is connected.

Interrupts

The PWM interrupt line is connected to the interrupt controller. Using the PWM interrupt requires the interrupt controller to be programmed first.

515

32059L–AVR32–01/2012

AT32UC3B

24.6 Functional Description

The PWM macrocell is primarily composed of a clock generator module and 7 channels.

– Clocked by the system clock, CLK_PWM, the clock generator module provides 13 clocks.

– Each channel can independently choose one of the clock generator outputs.

– Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers.

24.6.1

PWM Clock Generator

Figure 24-2. Functional View of the Clock Generator Block Diagram

CLK_PWM modulo n

Counter

CLK_PWM

CLK_PWM/2

CLK_PWM/4

CLK_PWM/8

CLK_PWM/16

CLK_PWM/32

CLK_PWM/64

CLK_PWM/128

CLK_PWM/256

CLK_PWM/512

CLK_PWM/1024

Divider A clk A

PREA

MR

DIVA

Divider B clk B

32059L–AVR32–01/2012

PREB

MR

DIVB

Caution: Before using the PWM macrocell, the programmer must ensure that the PWM clock in the Power Manager is enabled.

The PWM macrocell master clock, CLK_PWM, is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the

516

AT32UC3B

divided clocks.

The clock generator is divided in three blocks:

– a modulo n counter which provides 11 clocks: F

F

F

CLK_PWM

CLK_PWM

/8, F

CLK_PWM

/512, F

/16, F

CLK_PWM

CLK_PWM

/1024

CLK_PWM

/32, F

CLK_PWM

, F

CLK_PWM

/2, F

CLK_PWM

/4,

/64, F

CLK_PWM

/128, F

CLK_PWM

/256,

– two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB

Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made according to the PREA (PREB) field of the Mode register (MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value in the Mode register (MR).

After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the Mode register are cleared. This implies that after reset clkA (clkB) are turned off.

At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true when the PWM master clock is turned off through the Power Manager .

24.6.2

24.6.2.1

PWM Channel

Block Diagram

Figure 24-3. Functional View of the Channel Block Diagram

Inputs from

clock generator

Channel

Clock

Selector

Internal

Counter

Comparator

PWMx output waveform

Inputs from

Peripheral

Bus

24.6.2.2

Each of the 7 channels is composed of three blocks:

• A clock selector which selects one of the clocks provided by the clock generator described in

Section 24.6.1

.

• An internal counter clocked by the output of the clock selector. This internal counter is incremented or decremented according to the channel configuration and comparators events. The size of the internal counter is 20 bits.

• A comparator used to generate events according to the internal counter value. It also computes the PWMx output waveform according to the configuration.

Waveform Properties

The different properties of output waveforms are:

• the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the CMRx register. This field is reset at 0.

517

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

• the waveform period. This channel parameter is defined in the CPRD field of the CPRDx register.

- If the waveform is left aligned, then the output waveform period depends on the counter source clock and can be calculated:

By using the Master Clock (CLK_PWM) divided by an X given prescaler value

(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:

(

CLK_PWM

)

By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:

(

CLK_PWM

)

or

( )

CLK_PWM

If the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated:

By using the Master Clock (CLK_PWM) divided by an X given prescaler value

(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:

(

CLK_PWM

)

By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:

(

CLK_PWM

)

or

( ×

DIVB

CLK_PWM

)

• the waveform duty cycle. This channel parameter is defined in the CDTY field of the CDTYx register.

If the waveform is left aligned then: duty cycle =

(

period 1 fchannel_x_clock CDTY

period

)

If the waveform is center aligned, then: duty cycle =

( ) 1 fchannel_x_clock CDTY

(

period 2

)

) )

• the waveform polarity. At the beginning of the period, the signal can be at high or low level.

This property is defined in the CPOL field of the CMRx register. By default the signal starts by a low level.

• the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the CALG field of the CMRx register. The default mode is left aligned.

518

32059L–AVR32–01/2012

AT32UC3B

Figure 24-4. Non Overlapped Center Aligned Waveforms

No overlap

PWM0

PWM1

Period

Note: 1. See

Figure 24-5 on page 520

for a detailed description of center aligned waveforms.

When center aligned, the internal channel counter increases up to CPRD and.decreases down to 0. This ends the period.

When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period.

Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel.

Waveforms are fixed at 0 when:

• CDTY = CPRD and CPOL = 0

• CDTY = 0 and CPOL = 1

Waveforms are fixed at 1 (once the channel is enabled) when:

• CDTY = 0 and CPOL = 0

• CDTY = CPRD and CPOL = 1

The waveform polarity must be set before enabling the channel. This immediately affects the channel output level. Changes on channel polarity are not taken into account while the channel is enabled.

519

Figure 24-5. Waveform Properties

CLK_PWM

CHIDx (SR)

CHIDx (ENA)

CCNTx

CPRD(CPRDx)

CDTY(CDTYx)

Period

Output Waveform PWMx

CPOL(CMRx) = 0

Output Waveform PWMx

CPOL(CMRx) = 1

CHIDx (ISR)

CCNTx

CPRD(CPRDx)

CDTY(CDTYx)

Period

Output Waveform PWMx

CPOL(CMRx) = 0

Output Waveform PWMx

CPOL(CMRx) = 1

CHIDx (ISR)

32059L–AVR32–01/2012

Center Aligned

CALG (CMRx) = 1

Left Aligned

CALG (CMRx) = 0

AT32UC3B

520

AT32UC3B

24.6.3

24.6.3.1

PWM Controller Operations

Initialization

Before enabling the output channel, this channel must have been configured by the software application:

• Configuration of the clock generator if DIVA and DIVB are required

• Selection of the clock for each channel (CPRE field in the CMRx register)

• Configuration of the waveform alignment for each channel (CALG field in the CMRx register)

• Configuration of the period for each channel (CPRD in the CPRDx register). Writing in

CPRDx Register is possible while the channel is disabled. After validation of the channel, the user must use CUPDx Register to update CPRDx as explained below.

• Configuration of the duty cycle for each channel (CDTY in the CDTYx register). Writing in

CDTYx Register is possible while the channel is disabled. After validation of the channel, the user must use CUPDx Register to update CDTYx as explained below.

• Configuration of the output waveform polarity for each channel (CPOL in the CMRx register)

• Enable Interrupts (Writing CHIDx in the IER register)

• Enable the PWM channel (Writing CHIDx in the ENA register)

It is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several CHIDx bits in the ENA register.

In such a situation, all channels may have the same clock selector configuration and the same period specified.

24.6.3.2

24.6.3.3

Source Clock Selection Criteria

The large number of source clocks can make selection difficult. The relationship between the value in the Period Register (CPRDx) and the Duty Cycle Register (CDTYx) can help the user in choosing. The event number written in the Period Register gives the PWM accuracy. The Duty

Cycle quantum cannot be lower than 1/CPRDx value. The higher the value of CPRDx, the greater the PWM accuracy.

For example, if the user sets 15 (in decimal) in CPRDx, the user is able to set a value between 1 up to 14 in CDTYx Register. The resulting duty cycle quantum cannot be lower than 1/15 of the

PWM period.

Changing the Duty Cycle or the Period

It is possible to modulate the output waveform duty cycle or period.

To prevent unexpected output waveform, the user must use the update register (PWM_CUPDx) to change waveform parameters while the channel is still enabled. The user can write a new period value or duty cycle value in the update register (CUPDx). This register holds the new value until the end of the current cycle and updates the value for the next cycle. Depending on the CPD field in the CMRx register, CUPDx either updates CPRDx or CDTYx. Note that even if the update register is used, the period must not be smaller than the duty cycle.

521

32059L–AVR32–01/2012

32059L–AVR32–01/2012

AT32UC3B

Figure 24-6. Synchronized Period or Duty Cycle Update

User’s Writing

CUPDx Value

1 0

CMRx.CPD

CPRDx CDTYx

End of Cycle

To prevent overwriting the CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in IER at PWM Controller level.

The first method (polling method) consists of reading the relevant status bit in ISR Register

according to the enabled channel(s). See Figure 24-7 .

The second method uses an Interrupt Service Routine associated with the PWM channel.

Note: Reading the ISR register automatically clears CHIDx flags.

Figure 24-7. Polling Method

ISR Read

Acknoledgement and clear previous register state

Writing in CPD field

Update of the Period or Duty Cycle

CHIDx = 1

Writing in CUPDx

The last write has been taken into account

Note: Polarity and alignment can be modified only when the channel is disabled.

522

AT32UC3B

24.6.3.4

Interrupts

Depending on the interrupt mask in the IMR register, an interrupt is generated at the end of the corresponding channel period. The interrupt remains active until a read operation in the ISR register occurs.

A channel interrupt is enabled by setting the corresponding bit in the IER register. A channel interrupt is disabled by setting the corresponding bit in the IDR register.

32059L–AVR32–01/2012

523

AT32UC3B

24.7 User Interface

Table 24-2.

PWM Controller Memory Map

0x01C

0x200

0x204

0x208

0x20C

0x210

0x220

0x224

Offset

0x000

0x004

0x008

0x00C

0x010

0x014

0x018

0x228

0x22C

0x230

Register Name

Mode Register MR

Enable Register

Disable Register

ENA

DIS

Status Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

SR

IER

IDR

IMR

Interrupt Status Register

Channel 0 Mode Register

Channel 0 Duty Cycle Register

Channel 0 Period Register

Channel 0 Counter Register

Channel 0 Update Register

Channel 1 Mode Register

Channel 1 Duty Cycle Register

Channel 1 Period Register

Channel 1 Counter Register

Channel 1 Update Register

CPRD1

CCNT1

CUPD1

ISR

CMR0

CDTY0

CPRD0

CCNT0

CUPD0

CMR1

CDTY1

Access

Read/Write

Write-only

Write-only

Read-only

Write-only

Write-only

Read-only

Read-only

Read/Write

Read/Write

Read/Write

Read-only

Write-only

Read/Write

Read/Write

Read/Write

Read-only

Write-only

Peripheral

Reset Value

0x00000000

-

-

0x00000000

-

-

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

-

0x00000000

0x00000000

0x00000000

0x00000000

-

524

32059L–AVR32–01/2012

AT32UC3B

0

0

0

0

0

0

0

0

1

1

1

24.7.1

Name:

Mode Register

MR

Access Type: Read/Write

Offset:

Reset Value:

31

30

0x000

0x00000000

29

23 22 21

28

20

27

19

26

18

PREB

25

17

24

16

DIVB

15

7

14

6

13

5

12

4

11

3

10

2

PREA

9

1

8

0

DIVA

• DIVA, DIVB: CLKA, CLKB Divide Factor

DIVA, DIVB

0

1

2-255

• PREA, PREB

CLKA, CLKB

CLKA, CLKB clock is turned off

CLKA, CLKB clock is clock selected by PREA, PREB

CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.

0

0

1

1

0

1

1

0

0

PREA, PREB

0

0

0

0

0

0

1

1

0

0

1

1

1

Other

0

1

0

1

0

1

0

1

0

1

0

CLK_PWM.

CLK_PWM/2

CLK_PWM/4

CLK_PWM/8

CLK_PWM/16

CLK_PWM/32

CLK_PWM/64

CLK_PWM/128

CLK_PWM/256

CLK_PWM/512

CLK_PWM/1024

Reserved

Divider Input Clock

525

32059L–AVR32–01/2012

AT32UC3B

24.7.2

Name:

Enable Register

Access Type:

Offset:

Reset Value:

31

30

ENA

Write-only

-

0x004

29

23

15

22

14

21

13

28

20

12

7

6

CHID6

5

CHID5

4

CHID4

• CHIDx: Channel ID

1: Writing a one to this bit will enable PWM output for channel x.

0: Writing a zero to this bit has no effect.

3

CHID3

27

19

11

26

18

10

2

CHID2

25

17

9

1

CHID1

24

16

8

0

CHID0

526

32059L–AVR32–01/2012

AT32UC3B

24.7.3

Name:

Disable Register

Access Type:

DIS

Write-only

Offset:

Reset Value:

31

30

-

0x008

29

23

15

22

14

21

13

28

20

12

7

6

CHID6

5

CHID5

4

CHID4

• CHIDx: Channel ID

1: Writing a one to this bit will disable PWM output for channel x.

0: Writing a zero to this bit has no effect.

3

CHID3

27

19

11

26

18

10

2

CHID2

25

17

9

1

CHID1

24

16

8

0

CHID0

527

32059L–AVR32–01/2012

AT32UC3B

24.7.4

Name:

Status Register

Access Type:

SR

Read-only

Offset:

Reset Value:

31

30

0x00C

0x00000000

29

23

15

22

14

21

13

7

6

CHID6

5

CHID5

• CHIDx: Channel ID

0: PWM output for channel x is disabled.

1: PWM output for channel x is enabled.

28

20

12

4

CHID4

27

19

11

3

CHID3

26

18

10

2

CHID2

25

17

9

1

CHID1

24

16

8

0

CHID0

528

32059L–AVR32–01/2012

AT32UC3B

24.7.5

Name:

Interrupt Enable Register

Access Type:

IER

Write-only

Offset:

Reset Value:

31

30

0x010

-

29

23

15

22

14

21

13

28

20

12

27

19

11

7

6

CHID6

5

CHID5

4

CHID4

3

CHID3

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will set the corresponding bit in IMR.

26

18

10

2

CHID2

25

17

9

1

CHID1

24

16

8

0

CHID0

529

32059L–AVR32–01/2012

AT32UC3B

24.7.6

Name:

Interrupt Disable Register

Access Type:

IDR

Write-only

Offset:

Reset Value:

31

30

0x014

-

29

23

15

22

14

21

13

28

20

12

27

19

11

7

6

CHID6

5

CHID5

4

CHID4

3

CHID3

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will clear the corresponding bit in IMR.

26

18

10

2

CHID2

25

17

9

1

CHID1

24

16

8

0

CHID0

530

32059L–AVR32–01/2012

AT32UC3B

24.7.7

Name:

Interrupt Mask Register

Access Type:

IMR

Read-only

Offset:

Reset Value:

31

30

0x018

0x00000000

29

23

15

22

14

21

13

28

20

12

27

19

11

7

6

CHID6

5

CHID5

4

CHID4

3

CHID3

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

A bit in this register is cleared when the corresponding bit in IDR is written to one.

A bit in this register is set when the corresponding bit in IER is written to one.

2

CHID2

26

18

10

25

17

9

1

CHID1

24

16

8

0

CHID0

531

32059L–AVR32–01/2012

AT32UC3B

24.7.8

Name:

Interrupt Status Register

Access Type:

ISR

Read-only

Offset:

Reset Value:

31

30

0x01C

0x00000000

29

23

15

22

14

21

13

28

20

12

27

19

11

7

6

CHID6

5

CHID5

4

CHID4

3

CHID3

• CHIDx: Channel ID

0 = No new channel period since the last read of the ISR register.

1 = At least one new channel period since the last read of the ISR register.

Note: Reading ISR automatically clears CHIDx flags.

26

18

10

2

CHID2

25

17

9

1

CHID1

24

16

8

0

CHID0

532

32059L–AVR32–01/2012

AT32UC3B

24.7.9

Name:

Channel Mode Register

Access Type:

CMRx

Read/Write

Offset:

Reset Value:

31

30

0x200

0x00000000

29

23

15

22

14

21

13

28

20

12

27

19

11

3

26

18

7

6

5

4

• CPD: Channel Update Period

0 = Writing a zero to this bit will modify the duty cycle at the next period start event.

1 = Writing a one to this bit will modify the period at the next period start event.

• CPOL: Channel Polarity

0 = Writing a zero to this bit with configure the output waveform to start at a low level.

1 = Writing a zero to this bit with configure the output waveform to start at a high level.

• CALG: Channel Alignment

0 = Writing a zero to this bit with configure the period to be left aligned.

1 = Writing a zero to this bit with configure the period to be center aligned.

10

CPD

2

CPRE

9

CPOL

1

25

17

24

16

8

CALG

0

533

32059L–AVR32–01/2012

0

0

0

0

0

0

0

0

1

1

1

1

1

• CPRE: Channel Pre-scaler

1

1

1

1

0

0

0

0

0

0

0

0

1

CPRE

Other

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

0

1

0

1

0

1

0

1

0

1

0

CLK_PWM

CLK_PWM/2

CLK_PWM/4

CLK_PWM/8

CLK_PWM/16

CLK_PWM/32

CLK_PWM/64

CLK_PWM/128

CLK_PWM/256

CLK_PWM/512

CLK_PWM/1024

CLKA

CLKB

Reserved

Channel Pre-scaler

AT32UC3B

534

32059L–AVR32–01/2012

24.7.10

Channel Duty Cycle Register

Name:

CDTY x

Access Type:

Read/Write

Offset:

Reset Value:

31 30

0x204

0x00000000

29 28 27 26

CDTY

23 22 21 20 19 18

CDTY

15 14 13 12 11 10

CDTY

7 6 5 4 3 2

CDTY

Only the first 20 bits (internal channel counter size) are significant.

• CDTY: Channel Duty Cycle

Defines the waveform duty cycle. This value must be defined between 0 and CPRD (CPRx).

9

1

25

17

AT32UC3B

8

0

24

16

535

32059L–AVR32–01/2012

AT32UC3B

24.7.11

Channel Period Register

Name:

CPRDx

Access Type:

Read/Write

Offset:

Reset Value:

31 30

0x208

0x00000000

29 28 27 26 25 24

CPRD

23 22 21 20 19 18 17 16

CPRD

15 14 13 12 11 10 9 8

CPRD

7 6 5 4 3 2 1 0

CPRD

Only the first 20 bits (internal channel counter size) are significant.

• CPRD: Channel Period

If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated:

– By using the Master Clock (CLK_PWM) divided by an X given prescaler value (with

X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:

(

CLK_PWM

)

– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:

(

CLK_PWM

)

or

(

CLK_PWM

)

If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated:

– By using the Master Clock (CLK_PWM) divided by an X given prescaler value (with

X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:

(

CLK_PWM

)

– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:

(

2 CPRD DIVA

CLK_PWM

)

or

( ×

DIVB

CLK_PWM

)

536

32059L–AVR32–01/2012

AT32UC3B

24.7.12

Channel Counter Register

Name:

CCNTx

Access Type:

Read-only

Offset:

Reset Value:

31 30

0x20C

0x00000000

29 28 27 26 25 24

CNT

23 22 21 20 19 18 17 16

CNT

15 14 13 12 11 10 9 8

CNT

7 6 5 4 3 2 1 0

CNT

• CNT: Channel Counter Register

Internal counter value. This register is reset when the counter reaches the CPRD value defined in the CPRDx register if the waveform is left aligned.

537

32059L–AVR32–01/2012

AT32UC3B

24.7.13

Channel Update Register

Name:

CUPDx

Access Type:

Write-only

Offset:

Reset Value:

31 30

0x210

0x00000000

29 28 27 26 25 24

CUPD

23 22 21 20 19 18 17 16

CUPD

15 14 13 12 11 10 9 8

CUPD

7 6 5 4 3 2 1 0

CUPD

This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle.

Only the first 20 bits (internal channel counter size) are significant.

• CPD (CMRx Register)

0

1

The duty-cycle (CDTY in the CDTYx register) is updated with the CUPD value at the beginning of the next period.

The period (CPRD in the CPRDx register) is updated with the CUPD value at the beginning of the next period.

538

32059L–AVR32–01/2012

AT32UC3B

25. Analog-to-Digital Converter (ADC)

Rev: 2.0.0.1

25.1 Features

Integrated multiplexer offering up to eight independent analog inputs

Individual enable and disable of each channel

Hardware or software trigger

– External trigger pin

– Timer counter outputs (corresponding TIOA trigger)

Peripheral DMA Controller support

Possibility of ADC timings configuration

Sleep mode and conversion sequencer

– Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels

25.2 Overview

The Analog-to-Digital Converter (ADC) is based on a Successive Approximation Register (SAR)

10-bit ADC. It also integrates an 8-to-1 analog multiplexer, making possible the analog-to-digital conversions of 8 analog lines. The conversions extend from 0V to ADVREF.

The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. Software trigger, external trigger on rising edge of the TRIGGER pin, or internal triggers from timer counter output(s) are configurable.

The ADC also integrates a sleep mode and a conversion sequencer and connects with a Peripheral DMA Controller channel. These features reduce both power consumption and processor intervention.

Finally, the user can configure ADC timings, such as startup time and sample & hold time.

539

32059L–AVR32–01/2012

AT32UC3B

25.3 Block Diagram

Figure 25-1. ADC Block Diagram

Timer

Counter

Channels

ADC

TRIGGER

VDDANA

ADVREF

Dedicated

Analog

Inputs

AD-

AD-

AD-

Analog Inputs

Multiplexed

With I/O lines

AD-

AD-

AD-

GND

I/O

Controller

Trigger

Selection

Successive

Approximation

Register

Analog-to-Digital

Converter

Control

Logic

ADC Interrupt

Interrupt

Controller

User

Interface

Peripheral

DMA

Controller

High Speed

Bus (HSB)

Peripheral Bridge

Peripheral Bus

(PB)

25.4 I/O Lines Description

Table 25-1.

ADC Pins Description

Pin Name

VDDANA

ADVREF

AD[0] - AD[

7]

TRIGGER

Description

Analog power supply

Reference voltage

Analog input channels

External trigger

25.5 Product Dependencies

In order to use this module, other parts of the system must be configured correctly, as described below.

25.5.1

I/O Lines

The TRIGGER pin may be shared with other peripheral functions through the I/O Controller.

540

32059L–AVR32–01/2012

AT32UC3B

25.5.2

25.5.3

25.5.4

25.5.5

25.5.6

Power Management

In sleep mode, the ADC clock is automatically stopped after each conversion. As the logic is small and the ADC cell can be put into sleep mode, the Power Manager has no effect on the

ADC behavior.

Clocks

The clock for the ADC bus interface (CLK_ADC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the

ADC before disabling the clock, to avoid freezing the ADC in an undefined state.

The CLK_ADC clock frequency must be in line with the ADC characteritics. Refer to Electrical

Characteristics section for details.

Interrupts

The ADC interrupt request line is connected to the interrupt controller. Using the ADC interrupt requires the interrupt controller to be programmed first.

Analog Inputs

The analog input pins can be multiplexed with I/O lines. In this case, the assignment of the ADC input is automatically done as soon as the corresponding I/O is configured through the I/O contoller. By default, after reset, the I/O line is configured as a logic input.

Timer Triggers

Timer Counters may or may not be used as hardware triggers depending on user requirements.

Thus, some or all of the timer counters may be non-connected.

25.6 Functional Description

25.6.1

Analog-to-digital Conversion

The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10bit digital data requires sample and hold clock cycles as defined in the Sample and Hold Time field of the Mode Register (MR.SHTIM) and 10 ADC Clock cycles. The ADC Clock frequency is selected in the Prescaler Rate Selection field of the MR register (MR.PRESCAL).

The ADC Clock range is between CLK_ADC/2, if the PRESCAL field is 0, and CLK_ADC/128, if the PRESCAL field is 63 (0x3F). The PRESCAL field must be written in order to provide an ADC

Clock frequency according to the parameters given in the Electrical Characteristics chapter.

25.6.2

25.6.3

Conversion Reference

The conversion is performed on a full range between 0V and the reference voltage pin ADVREF.

Analog input values between these voltages are converted to digital values based on a linear conversion.

Conversion Resolution

The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by writing a one to the Resolution bit in the MR register (MR.LOWRES). By default, after a reset, the resolution is the highest and the Converted Data field in the Channel Data Registers (CDRn.DATA) is fully used. By writing a one to the LOWRES bit, the ADC switches in the lowest resolution and the conversion results can be read in the eight lowest significant bits of the Channel Data Registers

(CDRn). The two highest bits of the DATA field in the corresponding CDRn register will be read

541

32059L–AVR32–01/2012

AT32UC3B

as zero. The two highest bits of the Last Data Converted field in the Last Converted Data Register (LCDR.LDATA) will be read as zero too.

Moreover, when a Peripheral DMA channel is connected to the ADC, a 10-bit resolution sets the transfer request size to 16-bit. Writing a one to the LOWRES bit automatically switches to 8-bit data transfers. In this case, the destination buffers are optimized.

25.6.4

Conversion Results

When a conversion is completed, the resulting 10-bit digital value is stored in the CDR register of the current channel and in the LCDR register. Channels are enabled by writing a one to the

Channel n Enable bit (CHn) in the CHER register.

The corresponding channel End of Conversion bit in the Status Register (SR.EOCn) and the

Data Ready bit in the SR register (SR.DRDY) are set. In the case of a connected Peripheral

DMA channel, DRDY rising triggers a data transfer request. In any case, either EOC or DRDY can trigger an interrupt.

Reading one of the CDRn registers clears the corresponding EOC bit. Reading LCDR clears the

DRDY bit and the EOC bit corresponding to the last converted channel.

Figure 25-2. EOCn and DRDY Flag Behavior

Write CR

With START=1

Read CDRn

Write CR

With START=1

Read LCDR

CHn(CHSR)

EOCn(SR)

Conversion Time

Conversion Time

DRDY(SR)

542

32059L–AVR32–01/2012

AT32UC3B

If the CDR register is not read before further incoming data is converted, the corresponding

Overrun Error bit in the SR register (SR.OVREn) is set.

In the same way, new data converted when DRDY is high sets the General Overrun Error bit in the SR register (SR.GOVRE).

The OVREn and GOVRE bits are automatically cleared when the SR register is read.

Figure 25-3. GOVRE and OVREn Flag Behavior

Read SR

TRIGGER

CH0(CHSR)

CH1(CHSR)

LCDR

CRD0

CRD1

EOC0(SR)

Undefined Data

Undefined Data

Undefined Data

Conversion

Data A

Data A

Data B

Conversion

Data B

Data C

Data C

Read CDR0

EOC1(SR)

Conversion

Read CDR1

GOVRE(SR)

DRDY(ASR)

OVRE0(SR)

Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in SR are unpredictable.

543

32059L–AVR32–01/2012

AT32UC3B

25.6.5

25.6.6

Conversion Triggers

Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing a one to the START bit in the Control Register

(CR.START).

The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (TRIGGER). The hardware trigger is selected with the Trigger

Selection field in the Mode Register (MR.TRIGSEL). The selected hardware trigger is enabled by writing a one to the Trigger Enable bit in the Mode Register (MR.TRGEN).

If a hardware trigger is selected, the start of a conversion is detected at each rising edge of the selected signal. If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in Waveform Mode.

Only one start command is necessary to initiate a conversion sequence on all the channels. The

ADC hardware logic automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable (CHER) and Channel Disable (CHDR) Registers enable the analog channels to be enabled or disabled independently.

If the ADC is used with a Peripheral DMA Controller, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly.

Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or the software trigger.

Sleep Mode and Conversion Sequencer

The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not being used for conversions. Sleep Mode is selected by writing a one to the Sleep Mode bit in the Mode Register (MR.SLEEP).

The SLEEP mode is automatically managed by a conversion sequencer, which can automatically process the conversions of all channels at lowest power consumption.

When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into account.

The conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. Conversion sequences can be performed periodically using a Timer/Counter output. The periodic acquisition of several samples can be processed automatically without any intervention of the processor thanks to the Peripheral DMA Controller.

Note: The reference voltage pins always remain connected in normal mode as in sleep mode.

544

32059L–AVR32–01/2012

AT32UC3B

25.6.7

25.6.8

ADC Timings

Each ADC has its own minimal startup time that is defined through the Start Up Time field in the

Mode Register (MR.STARTUP). This startup time is given in the Electrical Characteristics chapter.

In the same way, a minimal sample and hold time is necessary for the ADC to guarantee the best converted final value between two channels selection. This time has to be defined through the Sample and Hold Time field in the Mode Register (MR.SHTIM). This time depends on the input impedance of the analog input, but also on the output impedance of the driver providing the signal to the analog input, as there is no input buffer amplifier.

Conversion Performances

For performance and electrical characteristics of the ADC, see the Electrical Characteristics chapter.

32059L–AVR32–01/2012

545

AT32UC3B

25.7 User Interface

Table 25-2.

ADC Register Memory Map

Offset

0x00

0x04

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

Register

Control Register

Mode Register

Channel Enable Register

Channel Disable Register

Channel Status Register

Status Register

Last Converted Data Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Channel Data Register 0

Name

CR

MR

CHER

CHDR

CHSR

SR

LCDR

IER

IDR

IMR

CDR0

Write-only

Read/Write

Write-only

Write-only

Read-only

Read-only

Read-only

Write-only

Write-only

Read-only

Read-only

...

0x4C

0xFC

...(if implemented)

Channel Data Register 7(if implemented)

Version Register

...

CDR

7

VERSION

...

Read-only

Read-only

...

0x00000000

-

Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.

(1)

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x000C0000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

546

32059L–AVR32–01/2012

AT32UC3B

25.7.1

Name:

Control Register

CR

Access Type:

Offset:

Reset Value:

Write-only

0x00

0x00000000

31

23

15

30

22

14

29

21

13

28

20

12

7

6

5

4

• START: Start Conversion

Writing a one to this bit will begin an analog-to-digital conversion.

Writing a zero to this bit has no effect.

This bit always reads zero.

• SWRST: Software Reset

Writing a one to this bit will reset the ADC.

Writing a zero to this bit has no effect.

This bit always reads zero.

3

27

19

11

26

18

10

2

25

17

9

1

START

24

16

8

0

SWRST

547

32059L–AVR32–01/2012

25.7.2

Name:

Mode Register

MR

Access Type:

Offset:

Reset Value:

Read/Write

0x04

0x00000000

31

23

15

30

22

14

29

21

13

28

20

27

19

STARTUP

12

PRESCAL

11

26

18

10

SHTIM

7

6

5

SLEEP

4

LOWRES

3 2

TRGSEL

• SHTIM: Sample & Hold Time

Sample & Hold Time = (SHTIM+3) / ADCClock

• STARTUP: Start Up Time

Startup Time = (STARTUP+1) * 8 / ADCClock

This Time should respect a minimal value. Refer to Electrical Characteristics section for details.

• PRESCAL: Prescaler Rate Selection

ADCClock = CLK_ADC / ( (PRESCAL+1) * 2 )

• SLEEP: Sleep Mode

1: Sleep Mode is selected.

0: Normal Mode is selected.

• LOWRES: Resolution

1: 8-bit resolution is selected.

0: 10-bit resolution is selected.

• TRGSEL: Trigger Selection

25

17

9

1

1

1

0

1

0

0

0

TRGSEL

0

0

1

1

0

0

1

0

1

0

1

0

1

0

Selected TRGSEL

Internal Trigger 0, depending of chip integration

Internal Trigger 1, depending of chip integration

Internal Trigger 2, depending of chip integration

Internal Trigger 3, depending of chip integration

Internal Trigger 4, depending of chip integration

Internal Trigger 5, depending of chip integration

External trigger

• TRGEN: Trigger Enable

1: The hardware trigger selected by the TRGSEL field is enabled.

0: The hardware triggers are disabled. Starting a conversion is only possible by software.

AT32UC3B

24

16

8

0

TRGEN

548

32059L–AVR32–01/2012

AT32UC3B

25.7.3

Name:

Channel Enable Register

CHER

Access Type:

Offset:

Reset Value:

Write-only

0x10

0x00000000

31

23

15

30

22

14

29

21

13

28

20

12

7

CH7

6

CH6

5

CH5

4

CH4

• CHn: Channel n Enable

Writing a one to these bits will set the corresponding bit in CHSR.

Writing a zero to these bits has no effect.

These bits always read a zero.

3

CH3

27

19

11

26

18

10

2

CH2

25

17

9

1

CH1

24

16

8

0

CH0

549

32059L–AVR32–01/2012

AT32UC3B

25.7.4

Name:

Channel Disable Register

CHDR

Access Type:

Offset:

Reset Value:

Write-only

0x14

0x00000000

31

23

15

30

22

14

29

21

13

28

20

12

27

19

11

26

18

10

25

17

9

24

16

8

7

CH7

6

CH6

5

CH5

4

CH4

3

CH3

• CHn: Channel n Disable

Writing a one to these bits will clear the corresponding bit in CHSR.

Writing a zero to these bits has no effect.

These bits always read a zero.

2

CH2

1

CH1

0

CH0

Warning:

If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in SR are unpredictable.

550

32059L–AVR32–01/2012

AT32UC3B

25.7.5

Name:

Channel Status Register

CHSR

Access Type:

Offset:

Reset Value:

Read-only

0x18

0x00000000

31

23

15

30

22

14

29

21

13

28

20

12

27

19

11

7

CH7

6

CH6

5

CH5

4

CH4

3

CH3

• CHn: Channel n Status

These bits are set when the corresponding bits in CHER is written to one.

These bits are cleared when the corresponding bits in CHDR is written to one.

1: The corresponding channel is enabled.

0: The corresponding channel is disabled.

26

18

10

2

CH2

25

17

9

1

CH1

24

16

8

0

CH0

551

32059L–AVR32–01/2012

AT32UC3B

25.7.6

Name:

Status Register

SR

Access Type:

Offset:

Reset Value:

Read-only

0x1C

0x000C0000

31

23

15

OVRE7

30

22

14

OVRE6

29

21

13

OVRE5

28

20

12

OVRE4

27

19

RXBUFF

11

OVRE3

26

18

ENDRX

10

OVRE2

25

17

GOVRE

9

OVRE1

7

EOC7

6

EOC6

5

EOC5

4

EOC4

3

EOC3

2

EOC2

1

EOC1

• RXBUFF: RX Buffer Full

This bit is set when the Buffer Full signal from the Peripheral DMA is active.

This bit is cleared when the Buffer Full signal from the Receive Peripheral DMA is inactive.

• ENDRX: End of RX Buffer

This bit is set when the End Receive signal from the Peripheral DMA is active.

This bit is cleared when the End Receive signal from the Peripheral DMA is inactive.

• GOVRE: General Overrun Error

This bit is set when a General Overrun Error has occurred.

This bit is cleared when the SR register is read.

1: At least one General Overrun Error has occurred since the last read of the SR register.

0: No General Overrun Error occurred since the last read of the SR register.

• DRDY: Data Ready

This bit is set when a data has been converted and is available in the LCDR register.

This bit is cleared when the LCDR register is read.

0: No data has been converted since the last read of the LCDR register.

1: At least one data has been converted and is available in the LCDR register.

• OVREn: Overrun Error n

These bits are set when an overrun error on the corresponding channel has occurred (if implemented).

These bits are cleared when the SR register is read.

0: No overrun error on the corresponding channel (if implemented) since the last read of SR.

1: There has been an overrun error on the corresponding channel (if implemented) since the last read of SR.

• EOCn: End of Conversion n

These bits are set when the corresponding conversion is complete.

These bits are cleared when the corresponding CDR or LCDR registers are read.

0: Corresponding analog channel (if implemented) is disabled, or the conversion is not finished.

1: Corresponding analog channel (if implemented) is enabled and conversion is complete.

24

16

DRDY

8

OVRE0

0

EOC0

552

32059L–AVR32–01/2012

AT32UC3B

25.7.7

Name:

Last Converted Data Register

LCDR

Access Type:

Offset:

Reset Value:

Read-only

0x20

0x00000000

31

23

30

22

29

21

28

20

12

27

19

11

26

18

25

17

24

16

15

7

14

6

13

5

10

2

9

LDATA[9:8]

8

1 0 4

LDATA[7:0]

3

• LDATA: Last Data Converted

The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.

553

32059L–AVR32–01/2012

AT32UC3B

25.7.8

Name:

Interrupt Enable Register

IER

Access Type:

Offset:

Reset Value:

Write-only

0x24

0x00000000

31

23

15

OVRE7

30

22

14

OVRE6

29

21

13

OVRE5

28

20

12

OVRE4

27

19

RXBUFF

11

OVRE3

7

EOC7

6

EOC6

5

EOC5

4

EOC4

3

EOC3

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will set the corresponding bit in IMR.

26

18

ENDRX

10

OVRE2

2

EOC2

25

17

GOVRE

9

OVRE1

1

EOC1

24

16

DRDY

8

OVRE0

0

EOC0

554

32059L–AVR32–01/2012

AT32UC3B

25.7.9

Name:

Interrupt Disable Register

IDR

Access Type:

Offset:

Reset Value:

Write-only

0x28

0x00000000

31

23

15

OVRE7

30

22

14

OVRE6

29

21

13

OVRE5

28

20

12

OVRE4

27

19

RXBUFF

11

OVRE3

7

EOC7

6

EOC6

5

EOC5

4

EOC4

3

EOC3

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will clear the corresponding bit in IMR.

26

18

ENDRX

10

OVRE2

2

EOC2

25

17

GOVRE

9

OVRE1

1

EOC1

24

16

DRDY

8

OVRE0

0

EOC0

555

32059L–AVR32–01/2012

AT32UC3B

25.7.10

Interrupt Mask Register

Name:

IMR

Access Type:

Offset:

Reset Value:

Read-only

0x2C

0x00000000

31

23

15

OVRE7

30

22

14

OVRE6

29

21

13

OVRE5

28

20

12

OVRE4

27

19

RXBUFF

11

OVRE3

26

18

ENDRX

10

OVRE2

7

EOC7

6

EOC6

5

EOC5

4

EOC4

3

EOC3

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

A bit in this register is cleared when the corresponding bit in IDR is written to one.

A bit in this register is cleared when the corresponding bit in IER is written to one.

2

EOC2

25

17

GOVRE

9

OVRE1

1

EOC1

24

16

DRDY

8

OVRE0

0

EOC0

556

32059L–AVR32–01/2012

AT32UC3B

25.7.11

Channel Data Register

Name:

CDRx

Access Type:

Offset:

Reset Value:

Read-only

0x2C-0x4C

0x00000000

31

23

30

22

29

21

28

20

12

27

19

11

26

18

25

17

24

16

15

7

14

6

13

5

10

2

9

DATA[9:8]

8

1 0 4

DATA[7:0]

3

• DATA: Converted Data

The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

557

32059L–AVR32–01/2012

AT32UC3B

25.7.12

Version Register

Name:

VERSION

Access Type:

Offset:

Reset Value:

Read-only

0xFC

31

23

30

22

29

21

28

20

12

15

7

14

6

13

5

11

4

VERSION[7:0]

3

• VARIANT: Variant Number

Reserved. No functionality associated.

• VERSION: Version Number

Version number of the module. No functionality associated.

27

19

26

25

18

VARIANT

17

10

VERSION[11:8]

9

2 1

8

0

24

16

558

32059L–AVR32–01/2012

AT32UC3B

25.8 Module Configuration

The specific configuration for the ADC instance is listed in the following tables.

Table 25-3.

Module configuration

Feature

Number of Channels

Internal Trigger 0

Internal Trigger 1

Internal Trigger 2

Internal Trigger 3

Internal Trigger 4

Internal Trigger 5

ADC

8

TIOA Ouput A of the Timer Counter Channel 0

TIOB Ouput B of the Timer Counter Channel 0

TIOA Ouput A of the Timer Counter Channel 1

TIOB Ouput B of the Timer Counter Channel 1

TIOA Ouput A of the Timer Counter Channel 2

TIOB Ouput B of the Timer Counter Channel 2

Table 25-4.

Module Clock Name

Module name Clock name

ADC CLK_ADC

Table 25-5.

Register Reset Values

Module name Reset Value

VERSION 0x00000200

559

32059L–AVR32–01/2012

AT32UC3B

26. Audio Bitstream DAC (ABDAC)

Rev: 1.0.1.1

26.1 Features

Digital Stereo DAC

Oversampled D/A conversion architecture

– Oversampling ratio fixed 128x

– FIR equalization filter

– Digital interpolation filter: Comb4

– 3rd Order Sigma-Delta D/A converters

Digital bitstream outputs

Parallel interface

Connected to DMA Controller for background transfer without CPU intervention

26.2 Overview

The Audio Bitstream DAC converts a 16-bit sample value to a digital bitstream with an average value proportional to the sample value. Two channels are supported, making the Audio Bitstream DAC particularly suitable for stereo audio. Each channel has a pair of complementary digital outputs, DATAn and DATANn, which can be connected to an external high input impedance amplifier.

The output DATAn and DATANn should be as ideal as possible before filtering, to achieve the best SNR and THD quality. The outputs can be connected to a class D amplifier output stage to drive a speaker directly, or it can be low pass filtered and connected to a high input impedance amplifier. A simple 1st order low pass filter that filters all the frequencies above 50kHz should be adequate when applying the signal to a speaker or a bandlimited amplifier, as the speaker or amplifier will act as a filter and remove high frequency components from the signal. In some cases high frequency components might be folded down into the audible range, and in that case a higher order filter is required. For performance measurements on digital equipment a minimum of 4th order low pass filter should be used. This is to prevent aliasing in the measurements.

For the best performance when not using a class D amplifier approach, the two outputs DATAn and DATANn, should be applied to a differential stage amplifier, as this will increase the SNR and THD.

560

32059L–AVR32–01/2012

AT32UC3B

26.3 Block Diagram

Figure 26-1. ABDAC Block Diagram

PM

GCLK_ABDAC sample_clk

Audio Bitstream DAC

Clock Generator bit_clk

CHANNEL0[15:0]

User Interface

CHANNEL1[15:0]

Equalization FIR

Equalization FIR

COMB

(INT=128)

COMB

(INT=128)

Sigma-Delta

DA-MOD

Sigma-Delta

DA-MOD

DATA0

DATA1

26.4 I/O Lines Description

Table 26-1.

I/O Lines Description

Pin Name

DATA0

Pin Description

Output from Audio Bitstream DAC Channel 0

DATA1

DATAN0

DATAN1

Output from Audio Bitstream DAC Channel 1

Inverted output from Audio Bitstream DAC Channel 0

Inverted output from Audio Bitstream DAC Channel 1

Type

Output

Output

Output

Output

26.5 Product Dependencies

In order to use this module, other parts of the system must be configured correctly, as described below.

26.5.1

I/O Lines

The output pins used for the output bitstream from the Audio Bitstream DAC may be multiplexed with IO lines.

Before using the Audio Bitstream DAC, the I/O Controller must be configured in order for the

Audio Bitstream DAC I/O lines to be in Audio Bitstream DAC peripheral mode.

561

32059L–AVR32–01/2012

AT32UC3B

26.5.2

Clocks

The CLK_ABDAC to the Audio Bitstream DAC is generated by the Power Manager (PM). Before using the Audio Bitstream DAC, the user must ensure that the Audio Bitstream DAC clock is enabled in the Power Manager.

The ABDAC needs a separate clock for the D/A conversion operation. This clock,

GCLK_ABDAC should be set up in the Generic Clock register in the Power Manager and its frequency must be as follow:

f

GCLK

=

S

where f s

is the samping rate of the data stream to convert. For f

GCLK_ABDAC clock must have a frequency of 12.288MHz.

s

= 48kHz this means that the

The two clocks, CLK_ABDAC and GCLK_ABDAC, must be in phase with each other.

26.5.3

Interrupts

The ABDAC interrupt request line is connected to the interrupt controller. Using the ABDAC interrupt requires the interrupt controller to be programmed first.

26.6 Functional Description

26.6.1

How to Initialize the Module

In order to use the Audio Bitstream DAC the product dependencies given in

Section 26.5 on page 561

must be resolved. Particular attention should be given to the configuration of clocks and I/O lines in order to ensure correct operation of the Audio Bitstream DAC.

The Audio Bitstream DAC is enabled by writing a one to the enable bit in the Audio Bitstream

DAC Control Register (CR.EN).

The Transmit Ready Interrupt Status bit in the Interrupt Status Register (ISR.TXREADY) will be set whenever the ABDAC is ready to receive a new sample. A new sample value should be written to SDR before 256 ABDAC clock cycles, or an underrun will occur, as indicated by the

Underrun Interrupt Status bit in ISR (ISR.UNDERRUN). ISR is cleared when read, or when writing one to the corresponding bits in the Interrupt Clear Register (ICR).

26.6.2

Data Format

The input data format is two’s complement. Two 16-bit sample values for channel 0 and 1 can be written to the least and most significant halfword of the Sample Data Register (SDR), respectively.

An input value of 0x7FFF will result in an output voltage of approximately:

V

OUT

(

0x7FFF

) ≈

128

=

128

0

,

98V

An Input value of 0x8000 will result in an output value of approximately:

V

OUT

(

0x8000

) ≈

128

=

128

2

,

32V

562

32059L–AVR32–01/2012

AT32UC3B

26.6.3

26.6.4

26.6.5

26.6.6

26.6.7

26.6.8

If one want to get coherence between the sign of the input data and the output voltage one can use the DATAN signal or invert the sign of the input data by software.

Data Swapping

When the SWAP bit in the ABDAC Control Register (CR.SWAP) is written to one, writing to the

Sample Data Register (SDR) will cause the values written to the CHANNEL0 and CHANNEL1 fields to be swapped.

Peripheral DMA Controller

The Audio Bitstream DAC is connected to the Peripheral DMA Controller. The Peripheral DMA

Controller can be programmed to automatically transfer samples to the Audio Bitstream DAC

Sample Data Register (SDR) when the Audio Bitstream DAC is ready for new samples. In this case only the CR.EN bit needs to be set in the Audio Bitstream DAC module. This enables the

Audio Bitstream DAC to operate without any CPU intervention such as polling the Interrupt Status Register (ISR) or using interrupts. See the Peripheral DMA Controller documentation for details on how to setup Peripheral DMA transfers.

Construction

The Audio Bitstream DAC is constructed of two 3rd order Sigma-Delta D/A converter with an oversampling ratio of 128. The samples are upsampled with a 4th order Sinc interpolation filter

(Comb4) before being applied to the Sigma-Delta Modulator. In order to compensate for the pass band frequency response of the interpolation filter and flatten the overall frequency response, the input to the interpolation filter is first filtered with a simple 3-tap FIR filter.The total frequency response of the Equalization FIR filter and the interpolation filter is given in

Figure 26-

2 on page 564

. The digital output bitstreams from the Sigma-Delta Modulators should be lowpass filtered to remove high frequency noise inserted by the modulation process.

Equalization Filter

The equalization filter is a simple 3-tap FIR filter. The purpose of this filter is to compensate for the pass band frequency response of the sinc interpolation filter. The equalization filter makes the pass band response more flat and moves the -3dB corner a little higher.

Interpolation Filter

The interpolation filter interpolates from f s

to 128f s

. This filter is a 4thorder Cascaded Integrator-

Comb filter, and the basic building blocks of this filter is a comb part and an integrator part.

Sigma-Delta Modulator

This part is a 3rdorder Sigma-Delta Modulator consisting of three differentiators (delta blocks), three integrators (sigma blocks) and a one bit quantizer. The purpose of the integrators is to shape the noise, so that the noise is reduced in the band of interest and increased at the higher frequencies, where it can be filtered.

563

32059L–AVR32–01/2012

AT32UC3B

26.6.9

Frequency Response

Figure 26-2. Frequency Response, EQ-FIR+COMB

4

1 0

0

- 1 0

- 2 0

- 3 0

- 4 0

- 5 0

- 6 0

0 1 2 3 4 5

F r e q u e n c y [ F s ]

6 7 8 9 1 0 x 1 0

4

564

32059L–AVR32–01/2012

26.7 User Interface

Table 26-2.

ABDAC Register Memory Map

Offset

0x00

0x08

0x0C

0x10

0x14

0x18

0x1C

Register

Sample Data Register

Control Register

Interrupt Mask Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Clear Register

Interrupt Status Register

AT32UC3B

Register Name

SDR

CR

IMR

IER

IDR

ICR

ISR

Access

Read/Write

Read/Write

Read-only

Write-only

Write-only

Write-only

Read-only

Reset

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

32059L–AVR32–01/2012

565

AT32UC3B

26.7.1

Name:

Sample Data Register

SDR

Access Type:

Offset:

Reset Value:

Read/Write

0x00

0x00000000

31

23

15

30

22

14

29

21

13

28 27

CHANNEL1[15:8]

20 19

CHANNEL1[7:0]

12 11

CHANNEL0[15:8]

7 6 5

• CHANNEL1: Sample Data for Channel 1

signed 16-bit Sample Data for channel 1.

• CHANNEL0: Signed 16-bit Sample Data for Channel 0

signed 16-bit Sample Data for channel 0.

4

CHANNEL0[7:0]

3

10

2

26

18

9

1

25

17

8

0

24

16

566

32059L–AVR32–01/2012

AT32UC3B

26.7.2

Name:

Control Register

CR

Access Type:

Offset:

Reset Value:

Read/Write

0x08

0x00000000

31

EN

23

-

15

-

30

SWAP

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

7

-

6

-

5

-

4

-

EN: Enable Audio Bitstream DAC

1: The module is enabled.

0: The module is disabled.

SWAP: Swap Channels

1: The swap of CHANNEL0 and CHANNEL1 samples is enabled.

0: The swap of CHANNEL0 and CHANNEL1 samples is disabled.

3

-

27

-

19

-

11

-

26

-

18

-

10

-

2

-

25

-

17

-

9

-

1

-

24

-

16

-

8

-

0

-

567

32059L–AVR32–01/2012

AT32UC3B

26.7.3

Name:

Interrupt Mask Register

IMR

Access Type:

Offset:

Reset Value:

Read-only

0x0C

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

29

TXREADY

21

-

13

-

28

UNDERRUN

20

-

12

-

27

-

19

-

11

-

7

-

6

-

5

-

4

-

3

-

1: The corresponding interrupt is enabled.

0: The corresponding interrupt is disabled.

A bit in this register is set when the corresponding bit in IER is written to one.

A bit in this register is cleared when the corresponding bit in IDR is written to one.

2

-

26

-

18

-

10

-

25

-

17

-

9

-

1

-

24

-

16

-

8

-

0

-

568

32059L–AVR32–01/2012

AT32UC3B

26.7.4

Name:

Interrupt Enable Register

IER

Access Type:

Offset:

Reset Value:

Write-only

0x10

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

29

TXREADY

21

-

13

-

28

UNDERRUN

20

-

12

-

7

-

6

-

5

-

4

-

3

-

Writing a one to a bit in this register will set the corresponding bit in IMR.

Writing a zero to a bit in this register has no effect.

27

-

19

-

11

-

26

-

18

-

10

-

2

-

25

-

17

-

9

-

1

-

24

-

16

-

8

-

0

-

569

32059L–AVR32–01/2012

AT32UC3B

26.7.5

Name:

Interrupt Disable Register

IDR

Access Type:

Offset:

Reset Value:

Write-only

0x14

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

29

TXREADY

21

-

13

-

28

UNDERRUN

20

-

12

-

27

-

19

-

11

-

7

-

6

-

5

-

4

-

3

-

Writing a one to a bit in this register will clear the corresponding bit in IMR.

Writing a zero to a bit in this register has no effect.

26

-

18

-

10

-

2

-

25

-

17

-

9

-

1

-

24

-

16

-

8

-

0

-

570

32059L–AVR32–01/2012

AT32UC3B

26.7.6

Name:

Interrupt Clear Register

ICR

Access Type:

Offset:

Reset Value:

Write-only

0x18

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

29

TXREADY

21

-

13

-

28

UNDERRUN

20

-

12

-

27

-

19

-

11

-

26

-

18

-

10

-

25

-

17

-

9

-

7

-

6

-

5

-

4

-

3

-

2

-

1

-

Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request.

Writing a zero to a bit in this register has no effect.

0

-

24

-

16

-

8

-

571

32059L–AVR32–01/2012

AT32UC3B

26.7.7

Name:

Interrupt Status Register

ISR

Access Type:

Offset:

Reset Value:

Read-only

0x1C

0x00000000

31

-

23

-

15

-

30

-

22

-

14

-

29

TXREADY

21

-

13

-

28

UNDERRUN

20

-

12

-

27

-

19

-

11

-

26

-

18

-

10

-

25

-

17

-

9

-

24

-

16

-

8

-

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

TXREADY: TX Ready Interrupt Status

This bit is set when the Audio Bitstream DAC is ready to receive a new data in SDR.

This bit is cleared when the Audio Bitstream DAC is not ready to receive a new data in SDR.

UNDERRUN: Underrun Interrupt Status

This bit is set when at least one Audio Bitstream DAC Underrun has occurred since the last time this bit was cleared (by reset or by writing in ICR).

This bit is cleared when no Audio Bitstream DAC Underrun has occurred since the last time this bit was cleared (by reset or by writing in ICR).

572

32059L–AVR32–01/2012

AT32UC3B

27. Programming and Debugging

27.1 Overview

General description of programming and debug features, block diagram and introduction of main concepts.

27.2 Service Access Bus

The AVR32 architecture offers a common interface for access to On-Chip Debug, programming, and test functions. These are mapped on a common bus called the Service Access Bus (SAB), which is linked to the JTAG port through a bus master module, which also handles synchronization between the debugger and SAB clocks.

When accessing the SAB through the debugger there are no limitations on debugger frequency compared to chip frequency, although there must be an active system clock in order for the SAB accesses to complete. If the system clock is switched off in sleep mode, activity on the debugger will restart the system clock automatically, without waking the device from sleep. Debuggers may optimize the transfer rate by adjusting the frequency in relation to the system clock. This ratio can be measured with debug protocol specific instructions.

The Service Access Bus uses 36 address bits to address memory or registers in any of the slaves on the bus. The bus supports sized accesses of bytes (8 bits), halfwords (16 bits), or words (32 bits). All accesses must be aligned to the size of the access, i.e. halfword accesses must have the lowest address bit cleared, and word accesses must have the two lowest address bits cleared.

27.2.1

SAB address map

The Service Access Bus (SAB) gives the user access to the internal address space and other features through a 36 bits address space. The 4 MSBs identify the slave number, while the 32

LSBs are decoded within the slave’s address space. The SAB slaves are shown in Table 27-1 on page 573 .

Table 27-1.

SAB Slaves, addresses and descriptions.

Slave Address [35:32] Description

Unallocated

OCD

HSB

HSB

0x0

0x1

0x4

0x5

Intentionally unallocated

OCD registers

HSB memory space, as seen by the CPU

Alternative mapping for HSB space, for compatibility with other 32-bit AVR devices.

Memory Service

Unit

Reserved

0x6

Other

Memory Service Unit registers

Unused

27.2.2

SAB security restrictions

The Service Access bus can be restricted by internal security measures. A short description of the security measures are found in the table below.

573

32059L–AVR32–01/2012

AT32UC3B

27.2.2.1

Security measure and control location

A security measure is a mechanism to either block or allow SAB access to a certain address or address range. A security measure is enabled or disabled by one or several control signals. This is called the control location for the security measure.

These security measures can be used to prevent an end user from reading out the code programmed in the flash, for instance.

Table 27-2.

SAB Security measures.

Security measure Control Location Description

Security bit

FLASHC security bit set

Programming and debugging not possible, very restricted access.

User code programming

FLASHC UPROT

+ security bit set

Restricts all access except parts of the flash and the flash controller for programming user code. Debugging is not possible unless an OS running from the secure part of the flash supports it.

Below follows a more in depth description of what locations are accessible when the security measures are active.

Table 27-3.

Security bit SAB restrictions

Name

OCD DCCPU,

OCD DCEMU,

OCD DCSR

User page

Other accesses

Address start

0x100000110

0x580800000

-

Address end

0x100000118 Read/Write

0x581000000

-

Access

Read

Blocked

Table 27-4.

User code programming SAB restrictions

Name

OCD DCCPU,

OCD DCEMU,

OCD DCSR

User page

FLASHC PB interface

FLASH pages outside

BOOTPROT

Other accesses

Address start

0x100000110

0x580800000

0x5FFFE0000

0x580000000 +

BOOTPROT size

-

Address end

0x100000118 Read/Write

0x581000000

0x5FFFE0400

0x580000000 + Flash size Read/Write

-

Access

Read

Read/Write

Blocked

574

32059L–AVR32–01/2012

AT32UC3B

27.3 On-Chip Debug (OCD)

Rev: 1.4.3.1

27.3.1

Features

Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+

JTAG access to all on-chip debug functions

Advanced program, data, ownership, and watchpoint trace supported

NanoTrace JTAG-based trace access

Auxiliary port for high-speed trace information

Hardware support for 6 program and 2 data breakpoints

Unlimited number of software breakpoints supported

Automatic CRC check of memory regions

27.3.2

Overview

Debugging on the AT32UC3B is facilitated by a powerful On-Chip Debug (OCD) system. The user accesses this through an external debug tool which connects to the JTAG port and the Auxiliary (AUX) port. The AUX port is primarily used for trace functions, and a JTAG-based debugger is sufficient for basic debugging.

The debug system is based on the Nexus 2.0 standard, class 2+, which includes:

• Basic run-time control

• Program breakpoints

• Data breakpoints

• Program trace

• Ownership trace

• Data trace

In addition to the mandatory Nexus debug features, the AT32UC3B implements several useful

OCD features, such as:

• Debug Communication Channel between CPU and JTAG

• Run-time PC monitoring

• CRC checking

• NanoTrace

• Software Quality Assurance (SQA) support

The OCD features are controlled by OCD registers, which can be accessed by JTAG when the

NEXUS_ACCESS JTAG instruction is loaded. The CPU can also access OCD registers directly using mtdr/mfdr instructions in any privileged mode. The OCD registers are implemented based on the recommendations in the Nexus 2.0 standard, and are detailed in the AVR32UC Technical

Reference Manual.

575

32059L–AVR32–01/2012

AT32UC3B

27.3.3

Block Diagram

Figure 27-1. On-Chip Debug Block Diagram

JTAG

JTAG

On-Chip Debug

Service Access Bus

Debug PC

Debug

Instruction

Breakpoints

AUX

Memory

Service

Unit

Transmit Queue Watchpoints

Program

Trace

Data Trace

Ownership

Trace

CPU

Internal

SRAM

HSB Bus Matrix

Memories and peripherals

27.3.4

JTAG-based Debug Features

A debugger can control all OCD features by writing OCD registers over the JTAG interface.

Many of these do not depend on output on the AUX port, allowing a JTAG-based debugger to be used.

A JTAG-based debugger should connect to the device through a standard 10-pin IDC connector as described in the AVR32UC Technical Reference Manual.

576

32059L–AVR32–01/2012

AT32UC3B

Figure 27-2. JTAG-based Debugger

PC

JTAG-based debug tool

10-pin IDC

JTAG

AVR32

27.3.4.1

27.3.4.2

Debug Communication Channel

The Debug Communication Channel (DCC) consists of a pair OCD registers with associated handshake logic, accessible to both CPU and JTAG. The registers can be used to exchange data between the CPU and the JTAG master, both runtime as well as in debug mode.

breakpoints

One of the most fundamental debug features is the ability to halt the CPU, to examine registers and the state of the system. This is accomplished by breakpoints, of which many types are available:

• Unconditional breakpoints are set by writing OCD registers by JTAG, halting the CPU immediately.

• Program breakpoints halt the CPU when a specific address in the program is executed.

• Data breakpoints halt the CPU when a specific memory address is read or written, allowing variables to be watched.

• Software breakpoints halt the CPU when the breakpoint instruction is executed.

When a breakpoint triggers, the CPU enters debug mode, and the D bit in the Status Register is set. This is a privileged mode with dedicated return address and return status registers. All privileged instructions are permitted. Debug mode can be entered as either OCD mode, running instructions from JTAG, or monitor mode, running instructions from program memory.

577

32059L–AVR32–01/2012

AT32UC3B

27.3.4.3

27.3.4.4

27.3.4.5

OCD mode

When a breakpoint triggers, the CPU enters OCD mode, and instructions are fetched from the

Debug Instruction OCD register. Each time this register is written by JTAG, the instruction is executed, allowing the JTAG to execute CPU instructions directly. The JTAG master can e.g.

read out the register file by issuing mtdr instructions to the CPU, writing each register to the

Debug Communication Channel OCD registers.

monitor mode

Since the OCD registers are directly accessible by the CPU, it is possible to build a softwarebased debugger that runs on the CPU itself. Setting the Monitor Mode bit in the Development

Control register causes the CPU to enter monitor mode instead of OCD mode when a breakpoint triggers. Monitor mode is similar to OCD mode, except that instructions are fetched from the debug exception vector in regular program memory, instead of issued by JTAG.

program counter monitoring

Normally, the CPU would need to be halted for a JTAG-based debugger to examine the current

PC value. However, the AT32UC3B provides a Debug Program Counter OCD register, where the debugger can continuously read the current PC without affecting the CPU. This allows the debugger to generate a simple statistic of the time spent in various areas of the code, easing code optimization.

27.3.5

27.3.5.1

Memory Service Unit

The Memory Service Unit (MSU) is a block dedicated to test and debug functionality. It is controlled through a dedicated set of registers addressed through the MEMORY_SERVICE JTAG command.

Cyclic Redundancy Check (CRC)

The MSU can be used to automatically calculate the CRC of a block of data in memory. The

OCD will then read out each word in the specified memory block and report the CRC32-value in an OCD register.

27.3.5.2

27.3.6

NanoTrace

The MSU additionally supports NanoTrace. This is an AVR32-specific feature, in which trace data is output to memory instead of the AUX port. This allows the trace data to be extracted by

JTAG MEMORY_ACCESS, enabling trace features for JTAG-based debuggers. The user must write MSU registers to configure the address and size of the memory block to be used for Nano-

Trace. The NanoTrace buffer can be anywhere in the physical address range, including internal and external RAM, through an EBI, if present. This area may not be used by the application running on the CPU.

AUX-based Debug Features

Utilizing the Auxiliary (AUX) port gives access to a wide range of advanced debug features. Of prime importance are the trace features, which allow an external debugger to receive continuous information on the program execution in the CPU. Additionally, Event In and Event Out pins allow external events to be correlated with the program flow.

The AUX port contains a number of pins, as shown in Table 27-5 on page 579

. These are multiplexed with I/O Controller lines, and must explicitly be enabled by writing OCD registers before the debug session starts. The AUX port is mapped to two different locations, selectable by OCD

Registers, minimizing the chance that the AUX port will need to be shared with an application.

578

32059L–AVR32–01/2012

AT32UC3B

Debug tools utilizing the AUX port should connect to the device through a Nexus-compliant Mictor-38 connector, as described in the AVR32UC Technical Reference manual. This connector includes the JTAG signals and the RESET_N pin, giving full access to the programming and debug features in the device.

Table 27-5.

Auxiliary Port Signals

Signal Direction Description

MCKO

MDO[5:0]

MSEO[1:0]

EVTI_N

EVTO_N

Output

Output

Output

Input

Output

Trace data output clock

Trace data output

Trace frame control

Event In

Event Out

Figure 27-3. AUX+JTAG based Debugger

P C

T r a c e b u f f e r

A U X + J T A G d e b u g t o o l

M ic t o r 3 8

A U X h ig h s p e e d

J T A G

A V R 3 2

27.3.6.1

trace operation

Trace features are enabled by writing OCD registers by JTAG. The OCD extracts the trace information from the CPU, compresses this information and formats it into variable-length messages according to the Nexus standard. The messages are buffered in a 16-frame transmit queue, and are output on the AUX port one frame at a time.

579

32059L–AVR32–01/2012

AT32UC3B

27.3.6.2

27.3.6.3

27.3.6.4

27.3.6.5

27.3.6.6

program trace

Program trace allows the debugger to continuously monitor the program execution in the CPU.

Program trace messages are generated for every branch in the program, and contains compressed information, which allows the debugger to correlate the message with the source code to identify the branch instruction and target address.

data trace

The trace features can be configured to be very selective, to reduce the bandwidth on the AUX port. In case the transmit queue overflows, error messages are produced to indicate loss of data. The transmit queue module can optionally be configured to halt the CPU when an overflow occurs, to prevent the loss of messages, at the expense of longer run-time for the program.

Data trace outputs a message every time a specific location is read or written. The message