Constant-Frequency, Current-Mode Step-Up DC-to-DC Controller ADP1621 Data Sheet

Constant-Frequency, Current-Mode Step-Up DC-to-DC Controller ADP1621 Data Sheet
Constant-Frequency, Current-Mode
Step-Up DC-to-DC Controller
ADP1621
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUIT
APD bias
Portable electronic equipment
Isolated dc-to-dc converter
Step-up/step-down dc-to-dc converter
LED driver for laptop computer and navigation system
LCD backlighting
GENERAL DESCRIPTION
The ADP1621 is a fixed-frequency, pulse-width modulation
(PWM), current-mode, step-up converter controller. It drives an
external n-channel MOSFET to convert the input voltage to a
higher output voltage. The ADP1621 can also be used to drive
flyback, SEPIC, and forward converter topologies, either isolated
or nonisolated.
The ADP1621 eliminates the use of a current-sense power
resistor by measuring the voltage drop across the on resistance of
the n-channel MOSFET. This technique, allowed up to a
maximum voltage of 30 V at the switch node, maximizes
efficiency and reduces cost. For switch-node voltages higher than
30 V or for more accurate current limiting, the CS pin can be
connected to a current-sense resistor in the source of the MOSFET.
The slope compensation is implemented by an external resistor,
allowing a wide range of external components (inductors and
MOSFETs), and can be chosen for various switching frequencies
and input and output voltages.
Rev. D
L1
4.7µH
VOUT = 5V
1A
D1
C3
1µF
10V
C4
0.1µF
10V
PIN
IN
R1
35.7kΩ
1%
RS
80Ω
CS
ADP1621
SDSN
GATE
COMP
C2
120pF
RCOMP
9.09kΩ
CCOMP
1.8nF
M1
COUT1
1µF
10V
COUT3
150µF
6.3V
×2
COUT2
10µF
10V
R2
11.5kΩ
1%
PGND
FREQ
FB
GND
C1
47µF
6.3V
RFREQ
31.6kΩ
1%
C1 = MURATA GRM31CR60J476M
COUT3 = SANYO POSCAP 6TPE150M
L1 = TOKO FDV0630-4R7M
06090-001
AGND
fOSC = 600kHz
M1 = VISHAY Si7882DP
D1 = VISHAY SSA33L
Figure 1. High Efficiency Output Boost Converter in Lossless Mode,
3.3 V Input, 5 V Output (Bootstrapped)
The ADP1621 supply input voltage range is 2.9 V to 5.5 V,
although higher input voltages are possible with the use of a
small signal NPN pass transistor or a single resistor. The voltage
of the power input can be as low as 1 V for fuel cell applications.
The switching frequency is set by an external resistor over a range
of 100 kHz to 1.5 MHz and can be synchronized to an external
clock by using the SDSN pin. The shutdown quiescent current is
less than 10 μA. The ADP1621 has a thermal shutdown feature
that shuts down the gate driver when the junction temperature
reaches approximately 150°C. The internal soft start circuit limits
inrush current at startup. The ADP1621 is available in the 10-lead
MSOP lead-free package and is specified over the −40°C to +125°C
junction temperature range.
100
90
80
70
60
50
40
30
0.01
0.1
1
LOAD CURRENT (A)
10
06090-042
APPLICATIONS
VIN = 3.3V
EFFICIENCY (%)
92% efficiency (no sense resistor required)
±1.0% initial accuracy
IC supply voltage range: 2.9 V to 5.5 V
Power-input voltage as low as 1.0 V
Capable of high supply input voltage (>5.5 V)
with an external NPN or a resistor
VIN UVLO and 35 mA shunt regulator
External slope compensation with 1 resistor
Programmable operating frequency
(100 kHz to 1.5 MHz) with 1 resistor
Lossless current sensing for switch-node voltage <30 V
Resistor current sensing for switch-node voltage >30 V
Synchronizable to external clock
Current-mode operation for excellent line and load transient
responses
10 μA shutdown current
Current limit and thermal overload protection
Soft start in 2048 clock cycles
Supported by ADIsimPower™ design tool
Figure 2. Efficiency of Circuit Shown in Figure 1
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ADP1621
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Duty Cycle ................................................................................... 14
Applications ....................................................................................... 1
Setting the Output Voltage ........................................................ 14
General Description ......................................................................... 1
Inductor Current Ripple ............................................................ 14
Typical Application Circuit ............................................................. 1
Inductor Selection ...................................................................... 14
Revision History ............................................................................... 2
Input Capacitor Selection .......................................................... 15
Simplified Block Diagram ............................................................... 3
Output Capacitor Selection....................................................... 15
Specifications..................................................................................... 4
Diode Selection........................................................................... 16
Absolute Maximum Ratings............................................................ 6
MOSFET Selection ..................................................................... 16
Thermal Resistance ...................................................................... 6
Loop Compensation .................................................................. 17
ESD Caution .................................................................................. 6
Slope Compensation .................................................................. 18
Pin Configuration and Function Descriptions ............................. 7
Current Limit .............................................................................. 18
Typical Performance Characteristics ............................................. 8
Light Load Operation ................................................................ 19
Theory of Operation ...................................................................... 12
Recommended Component Manufacturers ........................... 19
Control Loop ............................................................................... 12
Layout Considerations ................................................................... 20
Current-Sense Configurations.................................................. 12
Efficiency Considerations ............................................................. 21
Current Limit .............................................................................. 13
Examples of Application Circuits ................................................. 22
Undervoltage Lockout ............................................................... 13
Standard Boost Converter—Design Example ........................ 22
Shutdown ..................................................................................... 13
Bootstrapped Boost Converter ................................................. 23
Soft Start ...................................................................................... 13
SEPIC Converter Circuit ........................................................... 27
Internal Shunt Regulators.......................................................... 13
Low Voltage Power-Input Circuit ............................................ 27
Setting the Oscillator Frequency and Synchronization
Frequency .................................................................................... 13
LED Driver Application Circuits ............................................. 28
Related Devices ............................................................................... 30
Application Information: Boost Converter ................................. 14
Outline Dimensions ....................................................................... 31
ADIsimPower Design Tool ....................................................... 14
Ordering Guide .......................................................................... 31
REVISION HISTORY
2/16— Rev. C to Rev. D
Changes to Figure 39 and Figure 40 ............................................. 27
10/15—Rev. B to Rev. C
Moved Figure 3 ................................................................................. 3
Changes to Shunt Regulation Voltage Parameter, Table 1 .......... 4
6/12—Rev. A to Rev. B
Change to Features Section ............................................................. 1
Added ADIsimPower Design Tool Section ................................. 14
Change to Table 6 ........................................................................... 30
Updated Outline Dimensions ....................................................... 31
Changes to Ordering Guide .......................................................... 31
12/06—Rev. 0 to Rev. A
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................5
Added Table 3 ....................................................................................5
Changes to Table 5.......................................................................... 19
Changes to Ordering Guide .......................................................... 31
7/06—Revision 0: Initial Version
Rev. D | Page 2 of 32
Data Sheet
ADP1621
SIMPLIFIED BLOCK DIAGRAM
VREF
1.215V
ERROR
AMPLIFIER
SOFT START
(2048 CYCLES)
gm
FB
PIN
5.5V
COMP
VOSC
1.4V
SET
FREQ
S
GATE
R
SLOPE
COMP
GATE
DRIVER
PWM
COMPARATOR
CS
+
+
IN
UVLO
n
SDSN
100kΩ
PGND
5.5V
GND
ADP1621
Figure 3. ADP1621 Simplified Block Diagram
Rev. D | Page 3 of 32
06090-002
OSC
ADP1621
Data Sheet
SPECIFICATIONS
VIN = 5 V, RFREQ = 100 kΩ, fOSC = 200 kHz, TJ = −40°C to 125°C, unless otherwise noted.
Table 1.
Parameter
MAIN CONTROL LOOP
Internal Soft Start Time
PIN Supply Voltage 1
IN Supply Voltage1
Shunt Regulation Voltage
Symbol
tSS
VPIN
VIN
VSHUNT
Shunt Resistance
RSHUNT
IN Quiescent Current
IN Shutdown Current
PIN Supply Current
Static Mode, No Switching
Shutdown Mode
Undervoltage Lockout Threshold at
IN Pin
IIN
Test Conditions/Comments
Typ
Max
2048
IIN = 3 mA, IPIN = 3 mA, TA = 25°C
IIN = 3 mA, IPIN = 3 mA
Current into IN = 8 mA to 12 mA
Current into PIN = 8 mA to 12 mA
VIN = 2.9 V to 5.5 V, VFB = 1.215 V
VIN = 2.9 V to 5.5 V, SDSN = GND
2.9
2.9
5.2
5.0
5.4
5.4
13
7
1.8
1
Unit
3
10
Cycles
V
V
V
V
Ω
Ω
mA
µA
10
10
2.8
µA
µA
V
VSHUNT
VSHUNT
5.7
6.0
IPIN
VUVLO
VFB = 1.3 V, VCOMP < VCOMP,ZCT, GATE = 0 V
SDSN = GND
VUVLO rising
FB Regulation Voltage
VFB
VUVLO hysteresis
TA = 25°C
FB Input Current
Line Regulation 2
IFB
∆VFB/∆VIN
Load Regulation 3
Error Amplifier Transconductance
COMP Zero-Current Threshold
COMP Clamp High Voltage
∆VFB/∆VCOMP
gm
VCOMP,ZCT
VCOMP,CLAMP
Current-Sense Amplifier Gain
Peak Slope-Compensation Current at
CS Pin 4
CS Pin Leakage Current
Shutdown Time
Thermal Shutdown Threshold 5
Thermal Shutdown Hysteresis5
OSCILLATOR
Oscillator Frequency Range 6
Oscillator Frequency
Oscillator Frequency Tempco
SDSN Input Level Threshold
SDSN Threshold Hysteresis
SDSN Internal Pull-Down Resistor
Synchronization Minimum Pulse Width
Synchronization Maximum Pulse Width
Synchronization Frequency
GATE Minimum On Time
GATE Minimum Off Time
Maximum Duty Cycle6, 7
Recommended Maximum
Synchronized Frequency Ratio6, 8
Min
n
ISC,PK
ICS,LEAK
tSD
TTMSD
fOSC
fOSC
fOSC,TC
VSDSN,THRESH
RSDSN
tSYNC,MIN
tSYNC,MAX
fSYNC
tON,MIN
tOFF,MIN
DMAX
fSYNC/fOSC
VFB = 1.215 V, TA = 25°C
2.9 V ≤ VIN ≤ 5 V, TJ = −40°C to +85°C
2.9 V ≤ VIN ≤ 5 V, TJ = −40°C to +125°C
VCOMP = 1.4 V to 1.5 V
TJ = −40°C to +85°C
TJ = −40°C to +125°C
VCS = 0 V to 100 mV maximum across RS
(GATE high)
VCS = 30 V (GATE low)
SDSN pin from high to low or left floating
2.2
1.203
1.197
−75
−1
0.85
1.9
1.9
7.5
55
1
1
2.5
−80
1.215
1.215
+25
0.02
0.02
−0.1
300
1.0
2.0
2.0
9.5
70
100
255
VIN = VPIN = 5 V
1.5
VSDSN = 0 V to VIN
VSDSN = 0 V to VIN
325
±0.06
1.7
−0.19
100
45
0.8/fSYNC
110
Rev. D | Page 4 of 32
1.15
2.1
2.2
11.5
85
180
190
93
1.1
1.2
mV
V
V
nA
%/V
%/V
%
µS
V
V
V
V/V
µA
5
µA
µs
°C
°C
1500
395
kHz
kHz
%/°C
V
V
kΩ
ns
ns
kHz
ns
ns
%
50
150
−10
RFREQ = 65 kΩ, TA = 25°C
VFB = 1.215 V, VCOMP = 1.0 V
VFB = 1.215 V, VCOMP = 2.0 V
fSW = 200 kHz, RFREQ = 100 kΩ
fOSC = 200 kHz, RFREQ = 100 kΩ, fSYNC = fSW
1.227
1.233
+75
0.06
0.072
1.9
100
1800
215
230
97
1.4
Data Sheet
Parameter
GATE DRIVER
GATE Rise Time 9
GATE Fall Time9
ADP1621
Symbol
Test Conditions/Comments
tR
tF
CGATE = 3.3 nF
CGATE = 3.3 nF
Min
Typ
17
13
Max
Unit
ns
ns
The maximum input voltage is the shunt regulation voltage, which is typically 5.5 V and can range from 5.3 V to 6.0 V over the specified temperature range.
The ADP1621 is tested in a feedback servo loop, which servos VFB to the internal reference voltage. The voltage change in FB is measured while VIN is changed from
2.9 V to 5 V. The line regulation is calculated by (∆VFB/VFB) × 100%/∆VIN.
3
The ADP1621 is tested in a feedback servo loop, which servos VFB to the internal reference voltage, and VCOMP is forced from 1.4 V to 1.5 V. The VCOMP range is
(1.0 V ≤ VCOMP ≤ 2.0 V).
4
The peak slope-compensation current at the CS pin is typically 70 µA, and effectively clamped at 116 mV. Thus, RS should not exceed 1.6 kΩ (116 mV/70 µA).
5
Guaranteed by design for thermal shutdown. When the thermal junction temperature of the ADP1621 reaches approximately 150°C, the ADP1621 goes into thermal
shutdown and the GATE voltage is pulled low. When the junction temperature drops below about 140°C, the soft start sequence is initiated and the ADP1621 resumes
normal operation.
6
fOSC is the natural oscillation frequency, fSYNC is the synchronization frequency, and fSW is the switching frequency. If synchronization is used, then fSW = fSYNC; otherwise, fSW = fOSC.
7
Guaranteed by design and bench characterization.
8
To ensure proper synchronization operation, set the synchronization frequency, fSYNC, to 1.2× of the free-running frequency, fOSC. Although the switching frequency can
be synchronized to as high as 1.8 MHz, the peak slope-compensation current decreases at higher synchronization frequencies. It is recommended that the maximum
fSYNC be less than 1.4× of fOSC and should not exceed 1.8 MHz. Choose the slope-compensation resistor, RS, for the synchronization frequency (see the Slope
Compensation section in the Application Information: Boost Converter section).
9
GATE rise and fall times are measured from 10% to 90% levels.
1
2
Rev. D | Page 5 of 32
ADP1621
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
IN to GND
FB, COMP, SDSN, FREQ, GATE to GND
CS to GND
PIN to PGND
Supply Current into IN
Supply Current into PIN
Storage Temperature Range
Junction Operating Temperature Range1
Junction Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Package Power Dissipation1
1
Rating
−0.3 V to VSHUNT
−0.3 V to (VIN + 0.3 V)
−5 V to +33 V
−0.3 V to VSHUNT
25 mA
35 mA
−55°C to +150°C
−55°C to +150°C
−55°C to +150°C
300°C
(TJ,MAX − TA)/θJA
In applications where high power dissipation and poor package thermal
resistance are present, the maximum ambient temperature may need to be
derated. Maximum ambient temperature (TA,MAX) is dependent on the maximum
operating junction temperature (TJ,MAX = 150oC), the maximum power dissipation
of the device in the application (PD,MAX), and the junction-to-ambient thermal
resistance of the package in the application (θJA), is given by the following
equation: TA,MAX = TJ,MAX – (θJA x PD,MAX).
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to GND.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
θJA
10-Lead MSOP on a 2-Layer Printed Circuit Board (PCB) 200
10-Lead MSOP on a 4-Layer PCB
172
Unit
°C/W
°C/W
Junction-to-ambient thermal resistance of the package is based
on modeling and calculation using 2-layer and 4-layer boards, and
natural convection. The junction-to-ambient thermal resistance is
application- and board-layout dependent. In applications where
high maximum power dissipation exists, attention to thermal
dissipation issues in board design is required.
ESD CAUTION
Rev. D | Page 6 of 32
Data Sheet
ADP1621
SDSN
1
10
IN
GND 2
ADP1621
9
CS
TOP VIEW
(Not to Scale)
8
PIN
7
GATE
6
PGND
COMP 3
FB 4
FREQ 5
06090-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
SDSN
2
3
GND
COMP
4
FB
5
FREQ
6
PGND
7
GATE
8
PIN
9
CS
10
IN
Description
Shutdown and Synchronization Input. Turn the ADP1621 on by driving SDSN high; turn it off by driving SDSN low.
If SDSN is left floating or when the SDSN is pulled low, the ADP1621 goes into shutdown after 50 μs. If synchronization is
needed, synchronize the switching frequency to an external clock by connecting the external clock to the SDSN pin. An
internal 100 kΩ pull-down resistor is connected from SDSN to GND.
Ground.
Regulation Control Compensation Node. COMP is the output of the internal transconductance error amplifier.
Connect a series RC from COMP to GND to compensate the regulator. The nominal voltage range for this pin is
1.0 V to 2.0 V.
Feedback Input. FB is the input to the internal transconductance error amplifier. Drive FB from the output voltage
through a resistive voltage divider. The ratio of the voltage divider sets the output voltage. The regulation voltage
at FB is nominally 1.215 V.
Frequency Control Input. Connect a resistor from FREQ to GND to set the free-running switching frequency
between 100 kHz and 1.5 MHz. The nominal voltage of this pin is 1.4 V.
Power Ground Input. PGND is the ground return for the internal gate driver and the negative input of the internal
current-sense amplifier. Connect PGND to GND as close to the ADP1621 as possible.
Gate Driver Output. The maximum gate driver output is equal to the PIN voltage. GATE drives the gate of the
external n-channel power MOSFET. Connect GATE to the gate of the MOSFET.
Power Input. PIN powers the gate driver output. An internal 5.5 V shunt regulator is connected to this pin. Bypass
PIN to PGND with a 0.1 μF or greater capacitor.
Current-Sense Input. CS is the positive input of the current-sense amplifier. When GATE is turned on, the voltage at
the CS pin increases linearly from 0 V to a maximum of 116 mV, and the nominal peak slope-compensation output
current is 70 μA. When GATE is off, the CS function is disabled. For current sensing in lossless mode, connect CS to
the drain of the power MOSFET. The absolute maximum voltage at CS is 33 V. For higher accuracy current sensing
or higher switch-node voltages, connect CS to a current-sense power resistor in the source of the power MOSFET.
In both sensing methods, it is required to add a slope-compensation resistor, RS, to the CS pin to achieve stability
in the inductor current for duty cycles greater than 50%. However, it is recommended to add RS for all duty cycles
because load transients can momentarily cause the duty cycle to be greater than 50%, even when the steadystate duty cycle is less than 50%.
Input Voltage. IN powers the ADP1621 internal circuitry. An internal 5.5 V shunt regulator is connected to this pin.
Bypass IN to GND with a 0.1 μF or greater capacitor.
Rev. D | Page 7 of 32
ADP1621
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
100
92
90
91
80
90
EFFICIENCY (%)
EFFICIENCY (%)
LOAD = 0.5A
70
60
89
LOAD = 1A
88
87
50
86
0.1
10
1
LOAD CURRENT (A)
84
100
06090-004
30
0.01
TA = 25°C
VIN = 3.3V
VOUT = 5V
85
300
500
700
900
1100
1300
1500
SWITCHING FREQUENCY (kHz)
Figure 5. Efficiency vs. Load Current
06090-007
TA = 25°C
fSW = 220kHz
VIN = 3.3V
VOUT = 5V
40
Figure 8. Efficiency vs. Switching Frequency
100
VOUT RIPPLES @ 5V
AC-COUPLED
10
1
0.1
IPIN
0.01
0.001
0.0001
TA = 25°C
NO SWITCHING
2
CH1 20mV
CH2 2V
M2µs
A CH2
2.6V
0.00001
06090-005
CH2 = GATE
0
1
2
3
4
5
6
7
06090-008
SUPPLY CURRENT (mA)
IIN
1
1.29
06090-009
TA = 25°C
VIN = 3.3V
VOUT = 5V
LOAD = 1A
SUPPLY VOLTAGE (V)
Figure 6. Output Voltage Ripple of the Circuit Shown in Figure 1
Figure 9. Supply Current vs. Supply Voltage
1.21605
2.5
TA = 25°C
VIN = 5V
TA = 25°C
1.21600
2.0
VCOMP (V)
1.21590
1.5
1.0
1.21585
0.5
1.21580
1.21575
2.5
3.0
3.5
4.0
4.5
VIN (V)
5.0
5.5
6.0
06090-006
VFB (V)
1.21595
Figure 7. VFB vs. VIN
0
1.17
1.19
1.21
1.23
1.25
VFB (V)
Figure 10. VCOMP vs. VFB
Rev. D | Page 8 of 32
1.27
Data Sheet
ADP1621
45
35
MOSFET QG = 25nC
GATE RISE AND FALL TIMES (ns)
35
30
25
20
MOSFET QG = 15nC
10
25
tF
20
15
10
5
MOSFET QG = 7nC
5
0
0
200
400
600
800
1000
1200
1400
1600
1800
SWITCHING FREQUENCY (kHz)
0
0
5
15
20
25
30
35
45
50
180
200
40
Figure 14. GATE Rise and Fall Times vs. CGATE
2.60
1600
1500
1400
1300
1200
SDSN = 5V
2.55
1100
1000
900
2.50
2.45
0
50
100
150
TEMPERATURE (°C)
700
600
500
400
300
200
100
0
06090-011
2.40
–50
800
0
20
40
60
80
100
120
140
160
RFREQ (kΩ)
Figure 12. VUVLO Threshold vs. Temperature
06090-014
fOSC (kHz)
Figure 15. Oscillator Frequency vs. Resistance
198
1.03
VIN = 5V
TA = 25°C
RFREQ = 100kΩ
197
1.02
196
fOSC (kHz)
1.01
1.00
0.99
195
194
193
192
0.98
191
0
50
100
TEMPERATURE (°C)
150
2
06090-012
0.97
–50
3
4
VIN (V)
Figure 16. Oscillator Frequency vs. VIN
Figure 13. Frequency vs. Temperature
Rev. D | Page 9 of 32
5
06090-015
VUVLO (V)
10
GATE CAPACITANCE (nF)
Figure 11. PIN Supply Current vs. Switching Frequency
NORMALIZED FREQUENCY (fOSC/fOSC,25°C)
tR
06090-013
15
TA = 25°C
VIN = VPIN = 5V
tR OR tF IS FROM
10% TO 90% OF
THE GATE VOLTAGE
30
06090-010
PIN SUPPLY CURRENT (mA)
40
ADP1621
Data Sheet
1.6
250
VIN = 5V
CS = 30V
1.4
SHUTDOWN IN CURRENT (µA)
TEMPERATURE (°C)
200
150
100
50
VIN = 5V
SDSN = 0V
1.2
1.0
0.8
0.6
0.4
10
60
160
110
CS LEAKAGE (nA)
0
–50
06090-016
0
–40
0
50
100
150
TEMPERATURE (°C)
Figure 17. Temperature vs. CS Leakage
06090-019
0.2
Figure 20. Shutdown IN Current vs. Temperature
1.2165
VFB = 1.2113V AT 25°C
FB BIAS CURRENT IS MEASURED
BY FORCING A CONSTANT 1.2113V
OVER THE TEMPERATURE RANGE.
8
VIN = 5V
SDSN = 0V
1.2155
1.2150
0
VFB (V)
FB BIAS CURRENT (nA)
4
1.2160
–4
1.2145
1.2140
1.2135
–8
1.2130
–12
0
50
100
150
TEMPERATURE (°C)
1.2120
–50
0
50
100
150
TEMPERATURE (°C)
Figure 21. FB Voltage vs. Temperature
Figure 18. FB Bias Current vs. Temperature
TA = 25°C
VIN = 3.3V
VOUT = 5V
LOAD = 0.1A
DCM OPERATION
80
70
60
4
50
CH4 = INDUCTOR CURRENT
fOSC = 200kHz
40
fOSC = 550kHz
30
2
CH2 = DRAIN VOLTAGE
20
10
1
CH1 = GATE
1.2
1.4
1.6
1.8
2.0
fSYNC /fOSC
2.2
CH1 5V
CH2 5V
CH4 500mAΩ
M2µs
A CH1
Figure 22. DCM Switching Waveform
Figure 19. Slope-Compensation Current vs. fSYNC/fOSC
Rev. D | Page 10 of 32
2.9V
06090-021
0
1.0
06090-018
PEAK SLOPE COMPENSATION CURRENT (µA)
90
06090-020
–16
–50
06090-017
1.2125
Data Sheet
ADP1621
TA = 25°C
VIN = 3.3V
VOUT = 5V
LOAD = 0.3A
CCM OPERATION
LOAD CURRENT
FROM 0.2A TO 1.2A
4
4
CH4 = INDUCTOR CURRENT
1
2
CH2 = DRAIN VOLTAGE
OUTPUT, AC-COUPLED
CH1 5V
CH2 5V
CH4 500mAΩ
M2µs
A CH1
2.9V
06090-022
CH1 = GATE
CH1 50mV
Figure 23. CCM Switching Waveform
TA = 25°C
VIN = 3.3V
VOUT = 5V
fSW = 220kHz
SOFT-START = 9.3ms
CH4 1AΩ
M200µs
A CH4
700V
06090-025
TA = 25°C
VIN = 3.3V
VOUT = 5V
1
Figure 26. Load Transient Response of the Circuit Shown in Figure 1
TA = 25°C
VOUT = 5V
NO LOAD AT VOUT
CH1 = VOUT
CH1 = VOUT, AC-COUPLED
1
CH2 = SDSN
2
1
CH2 = VIN FROM 3V TO 4V
3
CH3 = GATE
M2ms
A CH1
4.5V
CH1 50mV
Figure 24. Soft Start Waveform
CH1 = VOUT, AC-COUPLED
1
CH2 = VIN FROM 3V TO 4V
M400µs
A CH2
3.8V
06090-024
2
CH2 2V
M400µs
A CH2
3.8V
Figure 27. Line Transient Response of the Configuration Shown in Figure 1
with No Load
TA = 25°C
VOUT = 5V
LOAD AT VOUT = 1A
CH1 50mV
CH2 2V
06090-026
CH2 5V
06090-023
CH1 1V
CH3 5V
2
Figure 25. Line Transient Response of the Configuration Shown in Figure 1
with a 1 A Load
Rev. D | Page 11 of 32
ADP1621
Data Sheet
THEORY OF OPERATION
CONTROL LOOP
The ADP1621 uses a current-mode architecture to regulate the
output voltage. The output voltage is monitored at FB through
a resistive voltage divider. The voltage at FB is compared to the
internal 1.215 V reference voltage by the internal transconductance
error amplifier to create an error current at COMP. A resistorcapacitor compensation impedance connected from COMP to
GND converts the error current to an error voltage.
The ADP1621 can sense the current across the on resistance of
the MOSFET to minimize external component count and improve
efficiency by eliminating the power that would be lost in a currentsense resistor. This lossless technique eliminates the need for an
expensive current-sense resistor. In the lossless mode configuration,
the voltage at the CS pin (or the switch-node voltage at the drain of
the MOSFET) must not exceed 30 V (see Figure 28). This technique
maximizes efficiency and reduces cost. In practice, when the
calculated VSW approaches 30 V, build the board and measure
the actual VSW before committing to the lossless mode design.
Because of the parasitic inductance in the diode, output capacitor,
and PCB traces, VSW typically has narrow peaks that exceed the
theoretical maximum voltage at VSW—the sum of VOUT and the
forward-voltage drop of Diode D1. If the measured peak voltage
exceeds 30 V, or if a more accurate current limit is desired, then
the CS pin can be connected to an external current-sense resistor
in the source of the MOSFET (Figure 29). The maximum power
output is limited by the selection of the external components.
At the beginning of the switching cycle, the MOSFET is turned
on and the inductor current ramps up. The MOSFET current is
measured and converted to a voltage using RCS or RDSON and is
added to the stabilizing slope-compensation ramp. The resulting
voltage sum passes through the current-sense amplifier to generate
the current-sense voltage. When the current-sense voltage is
greater than the COMP error voltage, the MOSFET is turned off
and the inductor current ramps down until the internal clock
initiates the next switching cycle. The duty-cycle of the PWM
modulator is thus adjusted to provide the necessary load current
at the desired output voltage. Because the output voltage ultimately
controls the peak inductor current through the COMP error
voltage, this scheme is referred to as peak current-mode control.
With light loads, the converter can also operate under discontinuous conduction mode and pulse-skipping modulation to
maintain output-voltage regulation. These two forms of operation
are discussed in detail in the Light Load Operation section.
Note that the converter can also be designed to operate in
discontinuous conduction mode at full load if desired.
Overall, the current-mode regulation system of the ADP1621
allows fast transient responses while maintaining a stable output
voltage. By selecting the proper resistor-capacitor network from
COMP to GND, the regulator response can be optimized for a
wide range of input voltages, output voltages, and load currents.
Rev. D | Page 12 of 32
L
VIN
PIN
IN
CS
ADP1621
D1
VOUT
VSW
RS
CO
SDSN
GATE
PGND
GND
06090-027
The input supply current to the ADP1621 is less than 3 mA
during normal operation and less than 10 μA during shutdown.
The ADP1621 can drive large external MOSFETs, allowing it to
support load currents in excess of 10 A.
CURRENT-SENSE CONFIGURATIONS
Figure 28. CS Pin Connection for VSW < 30 V, Lossless Mode
(No Current-Sense Resistor Needed)
L VSW D1
VIN
PIN
VOUT
IN
GATE
ADP1621
CO
SDSN
CS
PGND
GND
RS
RCS
06090-028
The ADP1621 is a fixed-frequency, current-mode, step-up dc-todc converter controller. It drives an external n-channel MOSFET
to step the input voltage up to a higher output voltage. It can be
used for SEPIC, flyback, boost, buck-boost, forward, and other
converter topologies. It operates at a fixed switching frequency that
is set by an external resistor over a range of 100 kHz to 1.5 MHz,
and it can be synchronized to an external clock by connecting
the SDSN pin to the clock.
Figure 29. CS Pin Connection for VSW > 30 V, Resistor Sense Mode
with a Current-Sense Resistor, RCS
Data Sheet
ADP1621
The current limit is achieved by the COMP voltage clamp, owing
to the current-mode operation of the ADP1621. A detailed
explanation of how the current limit is determined can be found
in the Current Limit section of the Application Information:
Boost Converter section.
UNDERVOLTAGE LOCKOUT
SETTING THE OSCILLATOR FREQUENCY AND
SYNCHRONIZATION FREQUENCY
The free-running oscillator frequency, fOSC, is set by a resistor
from FREQ to GND. A 100 kΩ resistor sets the typical oscillator
frequency to 200 kHz, a 65 kΩ resistor sets it to 325 kHz, a 32 kΩ
resistor sets it to 600 kHz, and a 10 kΩ resistor sets it to 1.5 MHz.
Figure 30 shows a typical relationship between fOSC and RFREQ.
1600
1500
1400
1300
1200
1100
1000
900
An internal undervoltage lockout (UVLO) circuit at the IN pin
holds the GATE voltage low when the IN voltage is below the
UVLO voltage, which is typically 2.5 V.
fOSC (kHz)
SHUTDOWN
The ADP1621 goes into shutdown approximately 50 µs after the
SDSN pin is pulled low or left floating. There is an internal 100 kΩ
resistor connected between SDSN and GND.
When the junction temperature of the ADP1621 reaches about
150°C, the ADP1621 goes into thermal shutdown and the
GATE voltage is pulled low. When the junction temperature drops
below about 140°C, the ADP1621 resumes normal operation after
the soft start sequence.
SOFT START
The ADP1621 has an internal soft start circuit that ramps
the FB regulation voltage from 0 V to 1.215 V in 64 steps over
2048 clock oscillator cycles. This soft start ramp allows the
output voltage to slowly rise to the steady-state output voltage,
preventing input inrush current at startup.
INTERNAL SHUNT REGULATORS
The IN and PIN pins each have an internal shunt regulator that
allows the ADP1621 to operate over a wide input voltage range.
The shunt regulators limit the voltages at IN and PIN to about
5.5 V, allowing the use of logic-level MOSFETs independent of
the input and/or output voltage. The shunt regulator voltage can
reach 5.7 V at 10 mA. See Figure 9 for the I-V characteristics of
these shunt regulators.
The internal power is derived from the IN pin, whereas the
MOSFET gate driver (GATE) current comes from the power
input, PIN. By separating the two inputs, PIN can be driven
with an external small-signal NPN transistor to limit the power
loss in the PIN shunt regulator when the input voltage is higher
than 5.5 V. See Figure 37 for an example. The maximum currents
going into PIN and IN must not exceed 35 mA and 25 mA,
respectively.
800
700
600
500
400
300
200
100
0
0
20
40
60
80
100
120
140
RFREQ (kΩ)
160
180
200
06090-029
CURRENT LIMIT
Figure 30. fOSC vs. RFREQ
The switching frequency can be synchronized to an external clock
by driving the SDSN pin with that clock signal. The SDSN pin
serves the two functions of shutdown control and frequency
synchronization input. If the SDSN input detects a low-to-high
transition within 10 µs of a high-to-low transition, it resets the
oscillator to synchronize to the frequency of the signal at SDSN.
The ADP1621 only synchronizes to frequencies greater than the
free-running switching frequency. To ensure proper synchronization
operation, set the synchronization frequency, fSYNC, to 1.2× the freerunning frequency, fOSC. The switching frequency, fSW, is equal to
fSYNC. Although the switching frequency can be synchronized to as
high as 1.8 MHz, the peak slope-compensation current decreases at
higher fSYNC. It is recommended that the maximum fSYNC be less
than 1.4× of fOSC. Choose the slope-compensation resistor, RS, for
the synchronization frequency (see the Slope Compensation
section). For SDSN to detect a high input, the high state must
remain high for at least 100 ns.
Rev. D | Page 13 of 32
ADP1621
Data Sheet
APPLICATION INFORMATION: BOOST CONVERTER
In this section, an analysis of a boost converter is presented,
along with guidelines for component selection. A typical boostconverter application circuit is shown in Figure 1.
ADIsimPower DESIGN TOOL
The ADP1621 is supported by ADIsimPower design tool set.
ADIsimPower is a collection of tools that produce complete
power designs optimized for a specific design goal. The tools
enable the user to generate a full schematic, bill of materials,
and calculate performance in minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and device count
while taking into consideration the operating conditions and
limitations of the IC and all real external components. For
more information about ADIsimPower design tools, refer to
www.analog.com/ADIsimPower. The tool set is available from
this website, and users can also request an unpopulated board
through the tool.
DUTY CYCLE
To determine the worst-case inductor current ripple, output
voltage ripple, and slope-compensation factor, it is first
necessary to determine the system duty cycle. The duty cycle in
continuous conduction mode (CCM) is calculated by the following
equation:
V
+ VD − VIN
D = OUT
VOUT + VD
(1)
where:
VOUT is the desired output voltage.
VIN is the input voltage.
VD is the forward-voltage drop of the diode. A typical Schottky
diode has a forward-voltage drop of 0.5 V.
The GATE minimum on and off times determine the minimum
and maximum duty cycles, respectively. The minimum on and off
times are typically 180 ns and 190 ns, respectively. The minimum
and maximum duty cycles are given by the following equations:
D MIN =
t ON , MIN
t SW
D MAX = 1 −
(2)
= t ON , MIN × f SW
t OFF , MIN
t SW
(3)
= 1 − (t OFF , MIN × f SW )
SETTING THE OUTPUT VOLTAGE
The output voltage is set through a voltage divider from the output
voltage to the FB input. The feedback resistor ratio sets the output
voltage of the system. The regulation voltage at FB is 1.215 V. The
output voltage is given by the following equation (see Figure 1):
R1 
VOUT = 1.215 V × 1 +

 R2 
(4)
The input bias current into FB is 25 nA typical, 70 nA maximum.
For a 0.1% degradation in regulation voltage and with 70 nA
bias current, R2 must be less than 18 kΩ, which results in 68 µA
of divider current. Choose the value of R1 to set the output
voltage. Using higher values for R2 results in reduced output
voltage accuracy due to the input bias current at the FB pin,
whereas lower values cause increased quiescent current
consumption.
INDUCTOR CURRENT RIPPLE
Choose a peak-to-peak inductor ripple current between 20%
and 40% of the average inductor current. A good starting point
for a design is to choose the peak-to-peak ripple current to be
30% of 1/(1 − D) times the maximum load current:
∆I L = 0.3 ×
I LOAD , MAX
1− D
(5)
where:
ΔIL is the peak-to-peak inductor ripple current.
ILOAD,MAX is the maximum load current required by the application.
INDUCTOR SELECTION
The inductor value choice is important because it dictates the
inductor current ripple and therefore the voltage ripple at the
output.
The average inductor current, IL,AVE, is given by the following
equation:
I L , AVE =
I LOAD
1− D
(6)
and the peak-to-peak inductor ripple current is inversely
proportional to the inductor value:
∆I L =
where:
VIN × D
f SW × L
(7)
where:
DMIN is the minimum duty cycle.
DMAX is the maximum duty cycle.
tON,MIN is the minimum on time.
tOFF,MIN is the minimum off time.
tSW is the switching period.
fSW is the switching frequency.
fSW is the switching frequency.
L is the inductor value.
Assuming continuous conduction mode (CCM) operation, the
peak inductor current is given by the following equation:
Note that when the converter tries to operate at a duty cycle
lower than DMIN, pulse-skipping modulation occurs to maintain
the output voltage regulation (see the Light Load Operation
section).
Rev. D | Page 14 of 32
I L ,PK =
I LOAD ∆I L I LOAD
V ×D
+
=
+ IN
1− D
2
1 − D 2 × f SW × L
(8)
Data Sheet
ADP1621
Smaller inductor values are typically smaller in size and usually
less expensive, but increase the ripple current. Larger ripple current
also increases the power loss in the inductor core. Too large an
inductor value results in added expense and may impede load
transient responses because it reduces the effect of slope
compensation.
Assuming the ripple current is 30% of 1/(1 − D) times the maximum load current, a reasonable choice for the inductor value is
L=
VIN × D × (1 − D )
0.3 × f SW × I LOAD , MAX
(9)
From this starting point, modify the inductance to obtain the
right balance of size, cost, and output voltage ripple while
maintaining the inductor ripple current between 20% and 40%
of 1/(1 − D) times the maximum load current. Keep in mind
that the inductor saturation current must be greater than the
peak inductor current. Magnetically shielded inductors are
generally recommended, although they cost slightly more than
unshielded inductors.
Also, losses due to the inductor winding resistance reduce the
efficiency of the boost converter. This power loss is given by
Regardless of the type of capacitor used, make sure the ripple
current rating of the bulk input capacitor, ICIN,RMS, is greater than
I CIN ,RMS =
In addition to the bulk input capacitor, a bypass input capacitor is
required. The function of the bypass capacitor is to locally filter the
input voltage to the ADP1621 and maintain the input voltage at a
steady value during switching transitions. The bypass capacitor is
typically a 0.1 µF or greater ceramic capacitor and should be placed
as close as possible to the IN and PIN pins of the ADP1621.
Capacitors C3 and C4 in Figure 1 represent the bypass capacitors.
OUTPUT CAPACITOR SELECTION
The output capacitor maintains the output voltage and supplies
current to the load while the external MOSFET is on.
The value and characteristics of the output capacitor greatly
affect the output voltage ripple and stability of the converter.
The amount of peak-to-peak output voltage ripple, ΔVOUT, can
be approximated by
∆I 
I
∆VOUT ≈  LOAD + L  ×
2 
 1− D
(10)

1

 2π × f × C
SW
OUT

where:
PL,W is the power dissipation in the winding of the inductor.
RW is the winding resistance.
(11)
where ΔIL is the peak-to-peak inductor ripple current.
2
I

PL ,W =  LOAD  × RW
 1− D 
1 ∆I L
×
3 2
2

 + ESR 2 + (2π × f SW × ESL )2


(12)
where:
INPUT CAPACITOR SELECTION
The bulk input capacitor provides a low impedance path for the
inductor ripple current. Capacitor C1 in Figure 1 represents a
bulk input capacitor. Choose a bulk input capacitor whose
impedance at the switching frequency is lower than the
impedance of the voltage source VIN.
The preferred bulk input capacitor is a 10 µF to 100 µF ceramic
capacitor because it has low equivalent series resistance (ESR) and
low impedance. Aluminum electrolytic and aluminum polymer
capacitors can also be used as the bulk input capacitors. The bulk
input capacitor does not need to be placed very close to the IN
and PIN pins. Aluminum electrolytic capacitors are the cheapest
and generally have high ESR values, which increase dramatically at
temperatures less than 0°C. Some aluminum electrolytic capacitors
have ESR less than 20 mΩ, but their capacitances are generally
greater than 800 µF. Aluminum polymer capacitors are more
expensive than the aluminum electrolytic ones, but are generally
cheaper than the ceramic capacitors for the same amount of
capacitance. Polymer capacitors have relatively low ESR, with
some models having less than 10 mΩ.
ΔIL is the peak-to-peak inductor ripple current.
fSW is the switching frequency.
COUT is the output capacitance.
ESR is the effective ESR of COUT.
ESL is the effective equivalent series inductance of COUT.
Because the output capacitor is typically greater than 40 µF, the
ESR dominates the output capacitance impedance and thus the
output voltage ripple. The use of low ESR, ceramic dielectric
capacitors is preferred, although aluminum electrolytic,
tantalum, OS-CON™ (from Sanyo), and aluminum polymer
capacitors can be used. At higher switching frequencies, the ESL
of the output capacitor may also be a factor in determining the
output voltage ripple. Multiple capacitors can be connected in
parallel to reduce the effective ESR and ESL. Keep in mind that
the capacitance of a given capacitor typically degrades with
increased temperature and bias voltage. Consult the capacitor
manufacturer’s data sheet when determining the actual
capacitance of a capacitor under certain conditions.
Ensure that the output capacitor ripple current rating, ICOUT,RMS,
is greater than
I COUT ,RMS = I LOAD ×
Rev. D | Page 15 of 32
D
1− D
(13)
ADP1621
Data Sheet
DIODE SELECTION
The diode conducts the inductor current to the output capacitor
and load while the MOSFET is off. The average diode current is
the load current:
I DIODE , AVE = I LOAD
(14)
The rms diode current in continuous conduction mode is given by
I DIODE ,RMS =
I LOAD
× 1− D
1− D
(15)
Estimate the rms current in the MOSFET under continuous
conduction mode by
where D is the duty cycle.
The power dissipated in the diode is
PDIODE = VD × I LOAD
I MOSFET , RMS =
(16)
I LOAD
× D
1− D
(18)
where D is the duty cycle. Derate the MOSFET current at least
20% to account for inductor ripple and changes in the forwardvoltage drop of the diode.
where VD is the forward-voltage drop of the diode.
The total power dissipation determines the diode junction
temperature, which is given by
TJ , DIODE = TA + PDIODE × θ JA
The minimum operating voltage of the ADP1621 is 2.9 V.
Choose a MOSFET with a VT that is at least 0.3 V less than the
minimum input supply voltage at PIN used in the application.
Ensure that the maximum VGS rating of the MOSFET is at least
a few volts greater than the maximum voltage that is applied to
PIN. Ensure that the maximum VDS rating of the MOSFET
exceeds the maximum VOUT by at least 5 V to 10 V. Depending
on parasitics, the MOSFET may be exposed to voltage spikes that
exceed the sum of VOUT and the forward-voltage drop of the diode.
(17)
The MOSFET power dissipation due to conduction is thus
2
I
PC =  LOAD  × D × RDSON × (1 + K )
 1− D 
where:
TJ,DIODE is the junction temperature.
TA is the ambient temperature.
θJA is the junction-to-ambient thermal resistance of the diode
package. The diode junction temperature must not exceed its
maximum rating at the given power dissipation level.
For high efficiency, Schottky diodes are recommended. The low
forward-voltage drop of a Schottky diode reduces the power losses
during the MOSFET off time, and the fast switching speed reduces
the switching losses during the MOSFET transitions. However,
for high voltage, high temperature applications where the reverse
leakage current of the Schottky diode can become significant
and degrade efficiency, use an ultrafast-recovery junction diode.
Make sure that the diode is rated to handle the average output
load current. Many diode manufacturers derate the current
capability of the diode as a function of the duty cycle. Verify
that the diode is rated to handle the average output load current
with the minimum duty cycle. Also, ensure that the peak inductor
current is less than the maximum rated current of the diode.
MOSFET SELECTION
When turned on, the external n-channel MOSFET allows
energy to be stored in the magnetic field of the inductor. When
the MOSFET is turned off, this energy is delivered to the load to
boost the output voltage.
The choice of the external power MOSFET directly affects the
boost converter performance. Choose the MOSFET based on
the following: threshold voltage (VT), on resistance (RDSON),
maximum voltage and current ratings, and gate charge.
(19)
where:
PC is the conduction power loss.
RDSON is the MOSFET on resistance. The variable K is a factor
that models the increase of RDSON with temperature:
(
K = 0.005 / C × TJ,MOSFET
− 25 C
)
(20)
where TJ,MOSFET is the MOSFET junction temperature. Note that
multiple n-channel MOSFETs can be placed in parallel to reduce
the effective RDSON.
The power dissipation due to switching transition loss is
approximated by
PSW =
(VOUT + VD )× I LOAD × (t R + t F )× f SW
1− D
2
(21)
where:
PSW is the switching power loss.
tR is the MOSFET rise time.
tF is the MOSFET fall time. The MOSFET rise and fall times are
functions of both the gate drive circuitry and the MOSFET used
in the application.
The total power dissipation of the MOSFET is the sum of the
conduction and transition losses:
PMOSFET = PC + PSW
(22)
where PMOSFET is the total MOSFET power dissipation. Ensure
that the maximum power dissipation is significantly less than
the maximum power rating of the MOSFET.
Rev. D | Page 16 of 32
Data Sheet
ADP1621
The regulator loop gain is
The total power dissipation also determines the MOSFET
junction temperature, which is given by
TJ , MOSFET = TA + PMOSFET × θ JA
(23)
AVL =
V FB
1
× (1 − D ) × g m × | Z COMP | ×
× | Z OUT |
VOUT
n × R CS
(28)
where:
where:
TJ,MOSFET is the junction temperature.
TA is the ambient temperature.
θJA is the junction-to-ambient thermal resistance of the
MOSFET package. The MOSFET junction temperature must not
exceed its maximum rating at the given power dissipation level.
AVL is the loop gain.
VFB is the feedback regulation voltage (typically 1.215 V).
VOUT is the regulated output voltage.
D is the duty cycle.
gm is the error amplifier transconductance gain (typically 300 µs).
ZCOMP is the impedance of the RC network from COMP to GND.
n is the current-sense amplifier gain (typically 9.5).
RCS is the current-sense resistance.
ZOUT is the impedance of the load and output capacitor. In the case
of lossless current sensing, as shown in Figure 28, RCS is equal to the
on resistance, RDSON, of the external power MOSFET. Otherwise,
RCS represents the external current-sense resistor, as shown in
Figure 29.
If lossless current sensing is not used, there is also power
dissipation in the external current-sense resistor, RCS. The power
dissipation, PCS, in the external resistor due to conduction losses
is given by
2
I

PCS =  LOAD  × D × RCS
1
−
D


(24)
LOOP COMPENSATION
The ADP1621 uses external components to compensate the
regulator loop, allowing optimization of the loop dynamics for
a given application.
The step-up converter produces an undesirable right-half plane
(RHP) zero in the regulation feedback loop. This RHP zero
requires compensating the regulator such that the crossover
frequency occurs well below the frequency of the RHP zero. The
location of the RHP zero is determined by the following equation:
f Z ,RHP = (1 − D )2 ×
RLOAD
2π × L
(25)
To determine the crossover frequency, it is important to note
that at that frequency the compensation impedance, ZCOMP, is
dominated by Resistor RCOMP, and the output impedance, ZOUT,
is dominated by the impedance of the output capacitor, COUT.
When solving for the crossover frequency, the equation is
simplified to
| AVL | =
VFB
1
1
× (1 − D ) × g m × RCOMP ×
×
=1
VOUT
n × RCS 2π × f C × C OUT
(29)
where:
where:
fZ,RHP is the RHP zero frequency.
RLOAD is the equivalent load resistance or the output voltage divided
by the load current.
fC is the crossover frequency.
RCOMP is the compensation resistor.
COUT is the output capacitance.
To stabilize the regulator, ensure that the regulator crossover
frequency is less than or equal to one-fifth of the RHP zero
frequency and less than or equal to one-fifteenth of the switching
frequency. For an initial practical design, choose the crossover
frequency fC to be the lower of
Solving for RCOMP gives
fC =
f SW
15
(26)
R COMP =
CCOMP =
f Z ,RHP
5
where:
fC is the crossover frequency.
fSW is the switching frequency.
(27)
V FB × (1 − D ) × g m
(30)
After the compensation resistor, RCOMP, is known, set the zero
formed by the resistor and compensation capacitor, CCOMP, to
one-fourth of the crossover frequency, or
and
fC =
2π × f C × C OUT × n × R CS × VOUT
2
π × f C × RCOMP
(31)
Capacitor C2 is chosen to cancel the zero introduced by the output
capacitance ESR. Thus, set C2 to (see Figure 31)
C2 =
ESR × COUT
RCOMP
where ESR represents the ESR of COUT.
Rev. D | Page 17 of 32
(32)
ADP1621
Data Sheet
For low ESR output capacitors, such as ceramic capacitors, C2
is small, generally in the range of 10 pF to 400 pF. Because of the
parasitic inductance, resistance, and capacitance of the PCB layout,
the RCOMP, CCOMP, and C2 values might need to be adjusted by
observing the load transient response of the ADP1621 to establish
a stable operating system and achieve optimal transient
performance. For most applications, RCOMP is in the range of
5 kΩ to 100 kΩ, and CCOMP is in the range of 100 pF to 30 nF.
COMP
gm
3
2
RCOMP
CCOMP
C2
06090-030
REF
Figure 31. Compensation Components
SLOPE COMPENSATION
CURRENT LIMIT
The current limit in the ADP1621 limits the peak inductor
current and is achieved by the COMP voltage clamp. The peak
inductor current, IL,PK, is given by
Slope compensation is achieved by internally forcing a ramping
current source out of the CS current-sense pin. By placing a
resistor between the CS pin and the current sensing device (the
drain of the external MOSFET in the case of lossless current
sensing or the source of the MOSFET if a current-sense resistor
is used), a voltage is developed across the resistor that is
proportional to the slope-compensation current.
To ensure stability of the current-mode control loop, use a
compensation voltage slope that is equal to or greater than onehalf of the current-sense representation of the inductor current
downslope. Therefore, it follows that
I SC,PK × f SW
V
+ VD − VIN
> RCS × OUT
L
1 − t OFF,MIN × f SW
(33)
where:
RS is the slope-compensation resistor.
ISC,PK is the peak slope-compensation current.
fSW is the switching frequency.
RCS is the current-sense resistor.
VOUT is the regulated output voltage.
VD is the forward-voltage drop of the diode.
VIN is the input voltage.
tOFF,MIN is the minimum off time.
L is the power-stage inductor. In the case of lossless current
sensing, RCS is equal to the on resistance, RDSON, of the external
power MOSFET. Otherwise, RCS represents the external currentsense resistor.
Solving for RS gives the following slope-compensation criterion:
RS >
RCS × (VOUT + VD − VIN ) × (1 − t OFF , MIN × f SW )
2 × I SC , PK × f SW × L
After accounting for parameter variations, use values of RS that
are as close to the calculated limit as possible because excessive
slope compensation reduces the benefits of current-mode control
and increases the “softness” of the current limit, as discussed in the
Current Limit section. Given a typical peak slope-compensation
current of 70 µA, RS must not exceed 1.6 kΩ because the voltage at
the CS pin is typically clamped at 116 mV. It is also recommended
that RS be greater than 20 Ω. If the calculated RS is greater than
1.6 kΩ, the parameters in Equation 34, such as RCS, fSW, and L,
can be adjusted such that RS is less than 1.6 kΩ.
In conclusion, the value of RS should be 20 Ω ≤ RS ≤ 1.6 kΩ.
The ADP1621 includes a circuit that allows adjustable slope
compensation. Slope compensation is required by currentmode regulators to stabilize the current-control loop when
operating in continuous conduction and the switching duty
cycle is greater than 50%.
2 × RS ×
Keep in mind that the above inequality is a function of both
ADP1621 parameters and off-chip components, the values of
which vary from device to device and with temperature. Select
RS to ensure current-loop stability for all possible variations.
VCOMP ,CLAMP − VCOMP , ZCT
I L , PK =
n
−
I SC , PK × R S × D
1 − t OFF , MIN × f SW
(35)
RCS
where:
VCOMP,CLAMP is the COMP clamp voltage (typically 2.0 V).
VCOMP,ZCT is the COMP zero-current threshold (typically 1.0 V).
n is the current-sense amplifier gain (typically 9.5).
ISC,PK is the peak slope-compensation current (typically 70 µA).
RS is the slope-compensation resistor.
D is the duty cycle.
fSW is the switching frequency.
tOFF,MIN is the minimum off time (typically 190 ns).
RCS is the current-sense resistor. In the case of lossless current
sensing, RCS is equal to the on resistance, RDSON, of the external
power MOSFET. Otherwise, RCS represents the external currentsense resistor.
The current limit in the ADP1621 is a soft current limit. When
the inductor current reaches the IL,PK limit given in Equation 35,
the duty cycle decreases, and the output voltage drops below the
desired voltage. The IL,PK limit in Equation 35 then increases in
response to the smaller duty cycle, D. The larger the slopecompensation resistor, RS, the larger the effect on IL,PK for an
incremental decrease in D. This behavior results in a soft current
limit for the ADP1621. Use values of RS that are as close as possible
to the calculated limit derived from Equation 34. If high-precision
current limiting is required, consider inserting a fuse in series
with the inductor.
(34)
Rev. D | Page 18 of 32
Data Sheet
ADP1621
Also, keep in mind that the current limit is a function of both
ADP1621 parameters and off-chip components, the values of
which vary from device to device and with temperature. If
lossless current sensing is used, consider that the on resistance
of a MOSFET typically increases with increasing junction
temperature.
resonant frequency of the inductor and the total capacitance
from the SW node to GND, which includes the capacitances of
the MOSFET and diode, and any parasitic capacitances from
the PCB. While adding a resistive element, such as a snubber, to
the system further dampens the resonance, it also decreases the
efficiency of the regulator.
The peak inductor current limit also limits the maximum load
current at a given output voltage. The maximum load current,
assuming CCM operation, is given by
Pulse-Skipping Modulation
I LOAD , MAX = (1 − D ) ×
I
× RS × D
 VCOMP ,CLAMP − VCOMP , ZCT



− SC , PK
n
1
−
t
×
f
V
×
D


OFF , MIN
SW
IN
−

RCS
2 × f SW × L 




(36)
If the load current exceeds ILOAD,MAX, the output voltage drops
below the desired voltage.
With light loads, the COMP voltage hovers around 1.0 V, and
short periods of switching are followed by long periods of the
MOSFET being powered off. This pulse-skipping modulation
operation improves converter efficiency by reducing the number of
switching cycles and therefore reducing the gate drive current and
the switching transition power loss.
LIGHT LOAD OPERATION
Discontinuous Conduction Mode
With light loads, the average inductor current is small, and,
depending on the converter design, the instantaneous inductor
current may reach 0 during the time when the MOSFET is off.
This mode of operation is termed discontinuous conduction
mode. The condition for entering discontinuous conduction
mode in a boost converter is
I LOAD <
VIN × D × (1 − D )
2 × L × f SW
(37)
When the instantaneous inductor current reaches 0 during the
cycle, the inductor ceases to be a current source, and ringing
can be observed in the waveforms of the MOSFET drain voltage
and the inductor current. The frequency of the ringing is the
The ADP1621 features circuitry that improves the converter
efficiency and minimizes power consumption with no load or
very light loads. When the COMP voltage drops below VCOMP,ZCT
(typically 1.0 V), which can occur at sufficiently light loads, the
MOSFET is powered off until the FB voltage drops below 1.215 V.
Then, the error amplifier drives the COMP voltage higher, and
the converter resumes switching when the COMP voltage rises
above the VCOMP,ZCT voltage. While the MOSFET is powered off,
the output capacitor supplies current to the load.
Given the minimum on time of the ADP1621, pulse-skipping
modulation is also a requirement to maintain output voltage
regulation with light loads. During the short switching periods
of pulse-skipping modulation, the MOSFET is turned on for the
minimum on time each cycle, storing just enough energy in the
inductor to charge the output capacitor. During the long period
when the MOSFET is off, no current flows through the inductor,
and the light load current is supplied by the output capacitor.
RECOMMENDED COMPONENT MANUFACTURERS
Table 5. Recommended Component Manufacturers
Vendor
AVX Corporation
Central Semiconductor Corp.
Coilcraft, Inc.
Diodes, Inc.
International Rectifier
Murata Manufacturing Co., Ltd.
ON Semiconductor
Rubycon Corporation
Sanyo
Sumida
Taiyo Yuden, Inc.
Toko America, Inc.
United Chemi-Con, Inc.
Vishay Siliconix
Components
Capacitors
Diodes
Inductors
Diodes
Diodes, MOSFETs
Capacitors, inductors
Diodes, MOSFETs
Capacitors
Capacitors
Inductors
Capacitors, inductors
Inductors
Capacitors
Diodes, MOSFETs, resistors, capacitors
Rev. D | Page 19 of 32
ADP1621
Data Sheet
LAYOUT CONSIDERATIONS
Layout is important for all switching regulators, but is particularly important for regulators with high switching frequencies.
To achieve high efficiency, good regulation, and stability, a welldesigned printed circuit board layout is required. A sample PCB
layout for the standard boost converter circuit shown in Figure 33
is given in Figure 32.

Follow these guidelines when designing printed circuit boards:





VIN
C1
L1
GND
D1
COUT1
M1
COUT2
VOUT
GATE
COUT3
GND
REMOTE OUTPUT
SENSING
06090-031
R1
RFREQ
R2
VIAS TO GND PLANE
VIAS TO 2ND LAYER
ADP1621
CCOMP
SDSN
C4

C2

RCOMP


RS


Keep the low ESR bypass input capacitor of 0.1 μF or
higher close to IN/PIN and GND.
Keep the high current path from Bulk Input Capacitor C1
through Inductor L1 and MOSFET M1 to PGND as short
as possible.
Keep the high current path from Bulk Input Capacitor C1
through Inductor L1, Diode D1, and Output Capacitor COUT
to PGND as short as possible. Place COUT as close to PGND
as possible to reduce ground bouncing.
Keep high current traces as short and wide as possible to
minimize parasitic series inductance, which causes spiking
and electromagnetic interference (EMI).
To minimize switching noise, place the drain of the power
MOSFET very close to the inductor, and connect the source
of the MOSFET (or the bottom side of the sense resistor)
directly to the power GND plane. Use wide copper traces on
the drain and on the source of the MOSFET to minimize
parasitic inductance and resistance. Parasitic inductance
can lead to excessive ringing during switching transitions,
and parasitic resistance reduces the converter efficiency.
Make sure that the MOSFET selected is capable of handling
the total power loss (conduction plus transition losses) in
the application circuit.
C3

Avoid routing high impedance traces near any node connected to the switch node (the MOSFET drain) or near
Inductor L1 to prevent radiated switching-noise injection.
Add an extra copper plane at the connection of the MOSFET
drain and the anode of the diode to help dissipate the heat
generated by losses in those components.
Avoid ground loops by having one central ground node on the
PCB. If this is impractical, place the power ground with
high current levels physically closer to the PCB ground
terminal. Place the analog, low current-level ground farther
from the PCB ground terminal.
Minimize the length of the PCB trace between the GATE
pin and the MOSFET gate. The parasitic inductance in this
PCB trace can give rise to excessive voltage ringing at the
MOSFET gate and drain, as well as the regulator output. It
is recommended to add 5 Ω of resistance for every inch of
PCB trace. This helps to reduce the overshoot and ringing at
the drain and the output. However, this added resistance
increases the rise and fall times of the MOSFET; thus, the
switching loss in the MOSFET is increased.
Place the feedback resistors as close to FB as possible to
prevent high frequency switching-noise injection.
Place the top of the upper feedback resistor, R1, as close
as possible to the top of COUT for optimum output voltage
sensing.
If a current-sense resistor is connected between the source
of the MOSFET and PGND, ensure that the capacitance from
CS to PGND is minimized.
Place the compensation components as close as possible
to COMP.
Figure 32. PCB Layout of the Circuit Shown in Figure 33 (2-layer PCB)
Rev. D | Page 20 of 32
Data Sheet
ADP1621
EFFICIENCY CONSIDERATIONS
The efficiency, η, of a dc-to-dc converter is given by
P
η = OUT × 100%
PIN
•
(38)
2
I

PL , W =  LOAD  × RW
 1− D 
where:
POUT is the output power.
PIN is the input power to the converter. While switching regulators
are ideally lossless converters of power, the nonideal characteristics
of regulator components degrade the efficiency of the regulator.
•
•
(39)
PIC = PG + (VIN × I Q )





(
= (VPIN × QG × f SW ) + VIN × I Q
PIC is the total power dissipated in the IC.
IQ is the quiescent current.
VIN is the voltage at the IN pin.
2
•
(40)
The power dissipation in the external diode.
PDIODE = VD × I LOAD
)
(44)
where:
The power dissipation in the external current-sense
resistor if lossless current sensing is not used.
I

PCS =  LOAD  × D × RCS
−
1
D


(43)
PG is the gate charging power loss.
VPIN is the voltage at the PIN pin.
QG is the MOSFET total gate charge.
fSW is the converter switching frequency. Therefore, the total
power dissipation in the IC itself is given by

 I

=  LOAD  × D × R DSON × (1 + K ) +

 1 − D 
I LOAD

 (VOUT + V D ) × 1 − D × (t R + t F ) × f SW

2


The supply current to the ADP1621 IC, which includes the
quiescent current and the gate driver charging current. The
power dissipation due to gate charging loss is approximated by
where:
The power dissipation in the external power MOSFET due
to conduction and switching losses.
PMOSFET = PC + PSW
(42)
PG = VPIN × QG × f SW
The primary sources of power dissipation in the regulator include
•
The power dissipation in the winding resistance of the
power stage inductor.
The secondary sources of power dissipation in the regulator
include
•
(41)
•
Rev. D | Page 21 of 32
The power dissipation in the ESR of the input and output
capacitors.
Inductor core losses due to hysteresis and eddy currents.
ADP1621
Data Sheet
EXAMPLES OF APPLICATION CIRCUITS
The next step is to choose a Schottky diode. The average
and rms diode currents are calculated to be 1.0 A and 1.3 A,
respectively, using Equations 14 and 15. A Vishay SSA33L
Schottky diode meets the current and thermal requirements
and is an excellent choice.
STANDARD BOOST CONVERTER—DESIGN
EXAMPLE
The example covered here is for the ADP1621 configured as a
standard boost converter, as shown in Figure 33, where lossless
current sensing is employed. The design parameters are VIN =
3.3 V, VOUT = 5 V, and a maximum load current of 1 A.
The power MOSFET must be chosen based on threshold voltage
(VT), on resistance (RDSON), maximum voltage and current ratings,
and gate charge. The rms current through the MOSFET is given
by Equation 18 as 1.1 A. The Vishay Si7882DP is a 20 V n-channel
power MOSFET that meets the current and thermal requirements.
It comes in a PowerPAK® package and offers low RDSON and gate
charge. At VGS = 2.5 V, the on resistance, RDSON, is 8 mΩ.
To begin this design, a switching frequency of 600 kHz is chosen
(by setting RFREQ to 32 kΩ, see Figure 30) so that a small inductor
and small output capacitors can be used. The duty cycle is calculated from Equation 1 to be 0.4, given a forward-voltage drop of
0.5 V for the Schottky diode. The feedback resistors are calculated
to be R1 = 35.7 kΩ and R2 = 11.5 kΩ from Equation 4.
The loop-compensation components are chosen to be RCOMP =
9.1 kΩ and CCOMP = 1.7 nF from Equations 30 and 31, respectively.
A roll-off capacitor of C2 = 120 pF is also added. The slopecompensation resistor is set to be RS = 80 Ω from Equation 34.
Assuming that the inductor ripple is 30% of 1/(1 − D) times
the maximum load current, the inductor size is calculated to be
about 4.4 µH, according to Equation 9. The small, magnetically
shielded 4.7 µH Toko FDV0630-4R7M inductor is selected.
Because ceramic capacitors have very low ESR (a few milliohms),
a 47 µF/6.3 V Murata GRM31CR60J476M ceramic capacitor is
chosen for the input capacitor. The output voltage ripple for a
given COUT, ESR, and ESL can be found by solving Equation 12.
By choosing an output voltage ripple equal to 1% of the output
voltage, Equation 12 yields that the minimum COUT required is
100 µF and the maximum ESR required is 25 mΩ. Other combinations of capacitance and ESR are possible by choosing a
much larger COUT and a larger ESR. In this case, a small 1 µF
ceramic capacitor and two 150 µF Sanyo POSCAP™ capacitors
are selected. The low ESR ceramic capacitor helps to suppress
the high frequency overshoot at the output. POSCAP has low
ESR and high capacitance in a relatively small package. Ceramic
capacitors can also be used. Generally, bigger ceramic capacitors
are more expensive.
Lastly, given the chosen components, the peak inductor current
as set by the current limit circuitry is given by Equation 35 as
IL,PK = 12 A. Thus, the maximum load current, assuming CCM
operation, is given by Equation 36 as ILOAD,MAX = 8 A, which is
safely above the 1.0 A load current requirement for this design
example. Note that the current limit is a strong function of RCS,
which can vary device to device and with temperature. In addition,
note that RCS can be implemented with an external current-sense
resistor or with the RDSON of a MOSFET. Variations in RCS and the
other parameters in Equations 35 and 36 must be taken into
account if precise current limiting is necessary. Due to the parasitic
resistance of PCB traces, RS might need to be adjusted on the
actual circuit board to achieve the desired current limit. Keep in
mind that RS must be less than 1.6 kΩ. Using a MOSFET with a
different RDSON or adjusting RCS can also set the current limit to
the desired level.
VIN = 3.3V
L1
4.7µH
C3
1µF
10V
PIN
IN
CS
R1
35.7kΩ
1%
RS
80Ω
ADP1621
SDSN
GATE
COMP
RCOMP
9.09kΩ
C2
120pF
CCOMP
1.8nF
VOUT = 5V
1A
D1
C4
0.1µF
10V
M1
COUT1
1µF
10V
COUT2
10µF
10V
COUT3
150µF
6.3V
×2
R2
11.5kΩ
1%
PGND
FREQ
FB
GND
RFREQ
31.6kΩ
1%
C1
47µF
6.3V
AGND
C1 = MURATA GRM31CR60J476M
COUT3 = SANYO POSCAP 6TPE150M
L1 = TOKO FDV0630-4R7M
M1 = VISHAY Si7882DP
D1 = VISHAY SSA33L
Figure 33. Typical Boost Converter Application Circuit
Rev. D | Page 22 of 32
06090-032
fOSC = 600kHz
Data Sheet
ADP1621
BOOTSTRAPPED BOOST CONVERTER
The inputs of the ADP1621 can be driven from the step-up
converter output voltage to improve efficiency for low input
voltages. For low input voltages, bootstrapped operation improves
efficiency with heavy loads by increasing the available gate drive
voltage, thus reducing the on resistance of the MOSFET. However,
because the internal circuitry is driven from IN, the ADP1621
quiescent current and gate drive current supplied from the input
increases due to the step-up ratio and the conversion efficiency
loss.
The circuit shown in Figure 1 shows a bootstrapped boost converter, where VIN = 3.3 V and VOUT = 5 V. To ensure that the circuit
starts, make sure that the input voltage minus the forward-voltage
drop of the diode is greater than the UVLO voltage and the gate
threshold voltage of the MOFSET. In this example, the MOSFET
has a gate threshold voltage of 2.5 V. The regulator shown in
Figure 1 is very similar to that shown in Figure 33, which is a
standard boost without bootstrapping. Because the same MOSFET
and inductor are used in both circuits and the input and output
conditions are the same, the compensation components remain
unchanged.
Figure 34 shows a bootstrapped application circuit for output
voltages greater than 5.5 V. In this case, the output is 12 V.
Notice that a resistor, R3, of 700 Ω is placed between VOUT and
the IN and PIN pins to limit the input currents because the IN
and PIN pins are regulated to 5.5 V. A diode, D2, is placed between
VIN and the IN/PIN pins to supply the necessary quiescent current
to start the ADP1621. After the ADP1621 starts and the output
voltage reaches 12 V, the quiescent current stops flowing through
D2 and is supplied by the output. Keep in mind that the dynamic
supply current to PIN increases as the switching frequency
increases because more gate drive is needed for a higher
switching frequency. Therefore, R3 needs to be set appropriately.
The PIN supply current can be approximated by
IPIN = fSW × QG
(45)
where:
IPIN is the PIN supply current.
fSW is the switching frequency.
QG is the gate charge of a particular MOSFET.
An alternative implementation to Figure 34 is shown in Figure 35,
where an NPN transistor is used to supply the necessary current
to the input PIN at various loads, but the gate drive voltage is
limited to approximately 4.8 V (one diode drop below the voltage
at IN). Signal Diodes D2 and D3 help to provide the necessary
quiescent current to start the ADP1621. After the ADP1621
starts, the current stops flowing through these two diodes because
the voltages at PIN and IN are approximately 4.8 V and 5.5 V,
respectively. One advantage of this technique is that Q1 provides
enough current to the gate driver at any switching frequency
with a wide range of MOSFETs that have different gate charge
specifications.
Notice that the output capacitor, COUT2 in Figure 34 and Figure 35,
is a large aluminum electrolytic capacitor, both in physical size
and capacitance. Such capacitors are very cheap relative to
ceramic capacitors (such as Sanyo POSCAP) or aluminum
polymer capacitors. The ADP1621 can work with a wide range
of capacitor types.
Rev. D | Page 23 of 32
ADP1621
Data Sheet
VIN = 3.3V
D2
C3
1µF
10V
R3
700Ω
L1
10µH
IN
PIN
CS
R1
88.7kΩ
1%
RS
200Ω
ADP1621
SDSN
C2
220pF
CCOMP
330pF
COUT1
10µF
16V
×2
COUT2
330µF
25V
×2
R2
10kΩ
1%
M1
GATE
COMP
RCOMP
51.5kΩ
VOUT = 12V
1A
D1
C4
0.1µF
10V
PGND
FREQ
GND
FB
RFREQ
31.6kΩ
1%
C1
47µF
6.3V
AGND
fOSC = 600kHz
C1 = MURATA GRM31CR60J476M
COUT2 = RUBYCON 25ZL330M8x16
L1 = COILCRAFT MSS1260-103ML
06090-033
M1 = IRF7470
D1 = VISHAY SSC53L
D2 = SIGNAL DIODE
Figure 34. Bootstrapped Application Circuit for VOUT > 5.5 V
VIN = 3.3V
L1
10µH
D2
D3
Q1
R3
1.5kΩ
C3
1µF
10V
PIN
IN
CS
R1
88.7kΩ
1%
RS
200Ω
ADP1621
SDSN
GATE
COMP
RCOMP
51.5kΩ
C2
220pF
CCOMP
330pF
VOUT = 12V
1A
D1
C4
0.1µF
10V
M1
COUT1
10µF
16V
×2
COUT2
330µF
25V
×2
R2
10kΩ
1%
PGND
FREQ
GND
FB
C1
47µF
6.3V
RFREQ
31.6kΩ
1%
C1 = MURATA GRM31CR60J476M
COUT2 = RUBYCON 25ZL330M8x16
L1 = COILCRAFT MSS1260-103ML
Q1 = SIGNAL NPN TRANSISTOR
M1 = IRF7470
D1 = VISHAY SSC53L
D2, D3 = SIGNAL DIODE
Figure 35. Bootstrapped Application Circuit for VOUT > 5.5 V
Rev. D | Page 24 of 32
06090-034
AGND
fOSC = 600kHz
Data Sheet
ADP1621
Low Input and High Output Boost Converter
with a single resistor, as shown in Figure 38. When there is a
wide input voltage range, it is sometimes desirable to use the
pass NPN transistor, as shown in Figure 37. If the input voltage
range is narrow, a single resistor connecting to the IN and PIN
pins is sufficient, as shown in Figure 38. In Figure 37, Resistor R3
limits the current going into IN, and there is power loss in this
resistor. The voltages at IN and PIN are both clamped to about
5.5 V, which can rise to as high as 5.9 V when the shunt current
is 30 mA. Refer to Figure 9 for the I-V characteristics of the shunt
regulators. Ensure that Resistor R3 is physically large enough to
handle the power dissipation. For switch-node voltages higher
than 30 V, a current-sense resistor is needed and the CS pin
senses the voltage across the sense resistor.
Figure 36 shows a typical application boost converter circuit
that operates at a switching frequency of 200 kHz with VIN = 5 V
and VOUT = 30 V with a 1 A load. The duty cycle for this circuit
is about 83%. A higher switching frequency can be selected, but
the switching power loss in the MOSFET increases and a bigger
MOSFET is needed. For switch-node voltages greater than 30 V,
a sense resistor, RCS, is needed because the absolute maximum
voltage at CS is 33 V.
High Input Voltage Boost Converter Circuit
Input voltages higher than 5.5 V are possible with the addition
of a resistor and an NPN transistor, as shown in Figure 37, or just
VIN = 5V
L1
7.8µH
C3
1µF
10V
R1
115kΩ
1%
PIN
IN
FB
ADP1621
SDSN
C2
120pF
CCOMP
20pF
FREQ
M1
GATE
COMP
RCOMP
1.6MΩ
VOUT = 30V
1A
D1
C4
0.1µF
10V
CS
PGND
GND
RS
909Ω
COUT1
1µF
100V
COUT2
4.7µF
50V
COUT3
330µF
50V
×2
R2
4.87kΩ
1%
RCS
3mΩ
C1
47µF
6.3V
×2
RFREQ
100kΩ
1%
AGND
fOSC = 200kHz
06090-035
M1 = VISHAY SUD50N06-07L
C1 = MURATA GRM31CR60J476M
COUT1 = MURATA GRM31CR72A10
COUT2 = MURATA GRM55ER71H475K
COUT3 = RUBYCON 50ZL330M10x23
D1 = IRF 15TQ060
L1 = COILCRAFT DO501DH-782ML
Figure 36. Low Input, High Output Boost Converter
VIN = 8V TO 15V
R3
700Ω
Q1
C4
0.1µF
10V
C3
1µF
10V
L1
8.2µH
R1
115kΩ
1%
PIN
IN
FB
RCOMP
2MΩ
C2
120pF
CCOMP
220pF
FREQ
CS
PGND
GND
COUT2
4.7µF
50V
COUT3
330µF
50V
×2
M1
GATE
COMP
COUT1
1µF
100V
R2
4.87kΩ
1%
ADP1621
SDSN
VOUT = 30V
1A
D1
RS
402Ω
RCS
3mΩ
C1
22µF
16V
×2
RFREQ
34.8kΩ
AGND
C1 = MURATA GRM32ER61C226K
COUT1 = MURATA GRM31CR72A105K
COUT2 = MURATA GRM55ER71H475K
COUT3 = RUBYCON 50ZL220M10x23
M1 = IRF7470
Q1 = SIGNAL NPN TRANSISTOR
D1 = MBRB7H50
L1 = COILCRAFT MSS1260-822ML
Figure 37. High Input Voltage and High Output Voltage Converter
Rev. D | Page 25 of 32
06090-036
fOSC = 560kHz
ADP1621
Data Sheet
VIN = 12V
R3
649Ω
C3
1µF
10V
L1
15µH
R1
324kΩ
1%
PIN
IN
FB
ADP1621
SDSN
C2
120pF
CCOMP
18pF
FREQ
M1
GATE
COMP
RCOMP
2MΩ
VOUT = 40V
1A
D1
C4
0.1µF
10V
CS
PGND
GND
RS
442Ω
COUT1
1µF
100V
COUT2
4.7µF
50V
COUT3
220µF
63V
×2
R2
10.2kΩ
1%
RCS
0.01Ω
C1
22µF
16V
×2
RFREQ
34.8Ω
AGND
fOSC = 560kHz
M1 = VISHAY Si7478DP
D1 = MBRB7H50
L1 = COILCRAFT MSS1278-153ML
Figure 38. High Input Voltage and High Output Voltage Converter
Rev. D | Page 26 of 32
06090-037
C1 = MURATA GRM32ER61C226K
COUT1 = MURATA GRM31CR72A105K
COUT2 = MURATA GRM55ER71H475K
COUT3 = RUBYCON 63ZL220M10x23
Data Sheet
ADP1621
SEPIC CONVERTER CIRCUIT
load current during this time. When the MOSFET turns off and
the diode turns on, the energy in L1 and L2 is released to charge
the output capacitor, COUT, and the coupling capacitor, C5, as
well as to supply current to the load.
A single-ended primary inductance converter (SEPIC) topology
is shown in Figure 39. This topology is useful for an unregulated
input voltage, where the regulated output voltage falls within the
input voltage range.
LOW VOLTAGE POWER-INPUT CIRCUIT
The input and output are dc-isolated by a coupling capacitor,
C5. L1 and L2 are coupled inductors with a 1:1 turn ratio, which
saves space on the PCB. In steady state, the average voltage across
C5 is the input voltage. When the MOSFET turns on and the
diode turns off, the input voltage provides energy to L1, and C5
provides energy to L2. The output capacitor, COUT, supplies the
The ADP1621 can be configured to run from a low voltage
(as low as 1 V) power input. The power source generally needs
to have a high current capability, such as a fuel cell. Figure 40
illustrates such an application, where the voltage of the power
input is 1 V and the voltage of the chip supply to the IN and
PIN pins is provided by an auxiliary low power source.
VIN = 3V TO 5V
L2
2.4µH
C3
1µF
10V
L1
2.4µH
C4
0.1µF
10V
IN
PIN
CS
COUT1
1µF
10V
RS
80Ω
ADP1621
SDSN
RCOMP
26kΩ
CCOMP
1.2nF
M1
GATE
COMP
C2
33pF
VOUT = 3.3V
2A
D1
C5
10µF
10V
X5R
R1
17.4kΩ
1%
PGND
FREQ
COUT2
150µF
6.3V
×3
FB
GND
R2
10kΩ
1%
RFREQ
65kΩ
C1
22µF
10V
×2
AGND
fOSC = 325kHz
06090-038
C1 = MURATA GRM332ER61A226K
M1 = VISHAY Si7882DP
COUT2 = SANYO POSCAP 6TPE150MI D1 = VISHAY SSC53L
C5 = MURATA GRM21BR61A106K
L1, L2 = COUPLED INDUCTORS, 1:1 RATIO, BH ELECTRONICS BH510-1006
Figure 39. A SEPIC DC-to-DC Converter
VIN = 1V
L1
2.2µH
VCC = 2.9V TO 5V
C3
1µF
10V
IN
PIN
CS
R1
35.7kΩ
1%
RS
249Ω
ADP1621
SDSN
GATE
COMP
RCOMP
9.4kΩ
C2
260pF
CCOMP
56nF
VOUT = 5V
1A
D1
C4
0.1µF
10V
M1
COUT1
1µF
10V
COUT2
10µF
6.3V
COUT3
150µF
6.3V
×2
R2
11.5kΩ
1%
PGND
FREQ
FB
GND
C1
100µF
X5R
6.3V
RFREQ
31.6kΩ
1%
AGND
C1 = MURATA GRM32ER60J107ME20 M1 = VISHAY Si7882DP
COUT2 = MURATA GRM21BR60J106K D1 = MBRD835L
COUT3 = SANYO POSCAP 6TPE150MI L1 = TOKO FDV0630-2R2M
Figure 40. Low Voltage Power-Input Application Circuit
Rev. D | Page 27 of 32
06090-039
fOSC = 600kHz
ADP1621
Data Sheet
LED DRIVER APPLICATION CIRCUITS
The ADP1621 can be used as an LED driver. Two LED application
circuits are shown in Figure 41 and Figure 42, where each circuit
is driving 20 white LEDs in series. Each white LED has a typical
current of 150 mA at a typical forward voltage of 4.0 V, with a
maximum voltage of 4.5 V over the temperature range of −40°C
to +125°C.
Two methods for dimming the brightness of the LEDs are
shown in Figure 41 and Figure 42. In Figure 41, a PWM signal
is fed to the SDSN pin to turn the ADP1621 controller on and
off. As a result, the LED current is turned on and off, and the
average LED current is dependent on the PWM duty cycle. The
advantage of this method is that no current flows through the
LEDs during the PWM off cycle. In addition, when the ADP1621
is on, the forward current through the LEDs is constant, which
guarantees constant color emission across the entire dimming
range. Because the soft start period is fixed at 2048 oscillator
cycles, the PWM frequency range is limited.
As shown in Figure 41, because the natural switching frequency
chosen is 400 kHz, the useful PWM frequency range is 90 Hz to
195 Hz. However, when driving fewer LEDs, the ADP1621 can
be set to run at a faster frequency, increasing the maximum
PWM frequency. The PWM duty cycle can be between 5% and
95%. A higher PWM duty cycle produces a higher average LED
current.
Another method for driving the LEDs is shown in Figure 42,
where the PWM signal is filtered by an RC low-pass filter and is
fed to the FB node. The effective FB voltage at the bottom of the
LED string is modulated in an analog manner by the PWM
duty cycle. Thus, the average current through the LEDs is
modulated accordingly. Unlike the case depicted in Figure 41, a
higher duty cycle produces a lower average LED current using
the filtered PWM scheme in Figure 42. The advantage of this
circuit is that the PWM frequency can be in the range between
90 Hz and 100 kHz, and the duty cycle can be between 5% and
95%. The disadvantage of this method is that the forward current
through the LEDs is directly modified to control the brightness
of the LEDs. Because the wavelength of the light emitted from
an LED is a weak function of its forward current, perfect color
purity across the entire dimming range cannot be guaranteed.
If PCB space is a constraint, smaller inductors can be selected
for the circuits shown in Figure 41 and Figure 42. For example,
a 4.7 µH inductor can be used, and a 200 kHz switching frequency
can be selected. However, with this small inductor, the system
operates in DCM, which is slightly less efficient than operating
in CCM.
Rev. D | Page 28 of 32
Data Sheet
ADP1621
VIN = 10V TO 16V
RB
800Ω
L1
33µH
D1
100V
C4
0.1µF
C3
0.1µF
IN
PIN
M1
100V
GATE
SDSN
CS
COMP
RCOMP
101kΩ
C2
18pF
CCOMP
390nF
FREQ
COUT
1µF
100V
×3
150mA
ADP1621
PWM
VOUT
RS
800Ω
20
LEDS
FB
PGND
GND
RCS
3mΩ
RFREQ
50kΩ
1%
R1
8Ω
1/4W
C1
2.2µF
25V
AGND
C1 = MURATA GRM31MR71E225K
COUT = MURATA GRM31CR72A105K
L1 = COILCRAFT MSS1038-333NL
M1 = VISHAY Si4482DY
D1 = IRF 10MQ100
06090-040
fOSC = 400kHz
Figure 41. 20-Series LED Driver with PWM at SDSN
VIN = 10V TO 16V
RB
800Ω
C4
0.1µF
C3
0.1µF
PIN
IN
ADP1621
SDSN
CS
COMP
RCOMP
101kΩ
C2
10pF
CCOMP
390nF
FREQ
RS
800Ω
RFREQ
50kΩ
1%
20
LEDS
R2
10kΩ
FB
PGND
GND
VOUT
COUT
1µF
100V
×3
150mA
M1
100V
GATE
R5
18kΩ
L1
33µH
D1
100V
RCS
3m
R1
8Ω
1/4W
R3
R4
22.9kΩ 10kΩ
C5
0.1µF
6.3V
PWM =
0V TO 4V
C1
2.2µF
25V
C1 = MURATA GRM31MR71E225K
COUT = MURATA GRM31CR72A105K
L1 = COILCRAFT MSS1038-333NL
M1 = VISHAY Si4482DY
D1 = IRF 10MQ100
Figure 42. 20-Series LED Driver with Filtered PWM
Rev. D | Page 29 of 32
06090-041
AGND
fOSC = 400kHz
ADP1621
Data Sheet
RELATED DEVICES
Table 6. Related Devices
Device
Number
ADP1612
ADP1613
ADP1614
Description
Current-mode PWM step-up controller
Current-mode PWM step-up controller
Current-mode PWM step-up controller
Comments
1.4 A, internal FET RDSON is 130 m Ω nominal, VIN = 1.8 V to 5.5 V, VOUTMAX is 20 V
2.0 A, internal FET RDSON is 130 m Ω nominal, VIN = 2.5 V to 5.5 V, VOUTMAX is 20 V
4.0 A, internal FET RDSON is 50 m Ω nominal, VIN = 2.5 V to 5.5 V, VOUTMAX is 20 V
Rev. D | Page 30 of 32
Data Sheet
ADP1621
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
6°
0°
0.23
0.13
0.70
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
0.15
0.05
COPLANARITY
0.10
Figure 43. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP1621ARMZ-R7
ADP1621-EVAL
1
Temperature Range
−40°C to +125°C
Package Description
10-Lead Mini Small Outline Package [MSOP]
Evaluation Board
Z = RoHS Compliant Part.
Rev. D | Page 31 of 32
Package
Option
RM-10
Ordering
Quantity
1,000
1
Branding
L3M
ADP1621
Data Sheet
NOTES
©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06090-0-2/16(D)
Rev. D | Page 32 of 32
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