Constant-Frequency, Current-Mode Step-Up DC-to-DC Controller ADP1621 Data Sheet

Constant-Frequency, Current-Mode Step-Up DC-to-DC Controller ADP1621 Data Sheet

Data Sheet

FEATURES

92% efficiency (no sense resistor required)

±1.0% initial accuracy

IC supply voltage range: 2.9 V to 5.5 V

Power-input voltage as low as 1.0 V

Capable of high supply input voltage (>5.5 V) with an external NPN or a resistor

V

IN

UVLO and 35 mA shunt regulator

External slope compensation with 1 resistor

Programmable operating frequency

(100 kHz to 1.5 MHz) with 1 resistor

Lossless current sensing for switch-node voltage <30 V

Resistor current sensing for switch-node voltage >30 V

Synchronizable to external clock

Current-mode operation for excellent line and load transient responses

10 μA shutdown current

Current limit and thermal overload protection

Soft start in 2048 clock cycles

Supported by ADIsimPower ™ design tool

APPLICATIONS

APD bias

Portable electronic equipment

Isolated dc-to-dc converter

Step-up/step-down dc-to-dc converter

LED driver for laptop computer and navigation system

LCD backlighting

GENERAL DESCRIPTION

The ADP1621 is a fixed-frequency, pulse-width modulation

(PWM), current-mode, step-up converter controller. It drives an external n-channel MOSFET to convert the input voltage to a higher output voltage. The ADP1621 can also be used to drive flyback, SEPIC, and forward converter topologies, either isolated or nonisolated.

The ADP1621 eliminates the use of a current-sense power resistor by measuring the voltage drop across the on resistance of the n-channel MOSFET. This technique, allowed up to a maximum voltage of 30 V at the switch node, maximizes efficiency and reduces cost. For switch-node voltages higher than

30 V or for more accurate current limiting, the CS pin can be connected to a current-sense resistor in the source of the MOSFET.

The slope compensation is implemented by an external resistor, allowing a wide range of external components (inductors and

MOSFETs), and can be chosen for various switching frequencies and input and output voltages.

Constant-Frequency, Current-Mode

Step-Up DC-to-DC Controller

ADP1621

TYPICAL APPLICATION CIRCUIT

V

IN

= 3.3V

L1

4.7µH

D1

C3

1µF

10V

C2

120pF

C4

0.1µF

10V

PIN IN

CS

ADP1621

SDSN

GATE

COMP

PGND

R

COMP

9.09kΩ

C

COMP

1.8nF

FREQ

GND

FB

R

FREQ

31.6kΩ

1%

R

S

80Ω

R1

35.7kΩ

1%

M1

R2

11.5kΩ

1%

C1

47µF

6.3V

C

OUT1

1µF

10V

C

OUT2

10µF

10V

C

OUT3

150µF

6.3V

×2

AGND f

OSC

= 600kHz

C1 = MURATA GRM31CR60J476M

C

OUT3

= SANYO POSCAP 6TPE150M

L1 = TOKO FDV0630-4R7M

M1 = VISHAY Si7882DP

D1 = VISHAY SSA33L

Figure 1. High Efficiency Output Boost Converter in Lossless Mode,

3.3 V Input, 5 V Output (Bootstrapped)

The ADP1621 supply input voltage range is 2.9 V to 5.5 V, although higher input voltages are possible with the use of a small signal NPN pass transistor or a single resistor. The voltage of the power input can be as low as 1 V for fuel cell applications.

The switching frequency is set by an external resistor over a range of 100 kHz to 1.5 MHz and can be synchronized to an external clock by using the SDSN pin. The shutdown quiescent current is less than 10 μA. The ADP1621 has a thermal shutdown feature that shuts down the gate driver when the junction temperature reaches approximately 150°C. The internal soft start circuit limits inrush current at startup. The ADP1621 is available in the 10-lead

MSOP lead-free package and is specified over the −40°C to +125°C junction temperature range.

100

90

80

70

60

50

40

30

0.01

0.1

1

LOAD CURRENT (A)

Figure 2. Efficiency of Circuit Shown in Figure 1

10

V

OUT

= 5V

1A

Rev. D Document Feedback

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Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved.

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ADP1621

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Typical Application Circuit ............................................................. 1

Revision History ............................................................................... 2

Simplified Block Diagram ............................................................... 3

Specifications ..................................................................................... 4

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 12

Control Loop ............................................................................... 12

Current-Sense Configurations .................................................. 12

Current Limit .............................................................................. 13

Undervoltage Lockout ............................................................... 13

Shutdown ..................................................................................... 13

Soft Start ...................................................................................... 13

Internal Shunt Regulators .......................................................... 13

Setting the Oscillator Frequency and Synchronization

Frequency .................................................................................... 13

Application Information: Boost Converter ................................. 14

ADIsimPower Design Tool ....................................................... 14

REVISION HISTORY

2/16— Rev. C to Rev. D

Changes to Figure 39 and Figure 40 ............................................. 27

10/15—Rev. B to Rev. C

Moved Figure 3 ................................................................................. 3

Changes to Shunt Regulation Voltage Parameter, Table 1 .......... 4

6/12—Rev. A to Rev. B

Change to Features Section ............................................................. 1

Added ADIsimPower Design Tool Section ................................. 14

Change to Table 6 ........................................................................... 30

Updated Outline Dimensions ....................................................... 31

Changes to Ordering Guide .......................................................... 31

Data Sheet

Duty Cycle ................................................................................... 14

Setting the Output Voltage ........................................................ 14

Inductor Current Ripple ............................................................ 14

Inductor Selection ...................................................................... 14

Input Capacitor Selection .......................................................... 15

Output Capacitor Selection ....................................................... 15

Diode Selection ........................................................................... 16

MOSFET Selection ..................................................................... 16

Loop Compensation .................................................................. 17

Slope Compensation .................................................................. 18

Current Limit .............................................................................. 18

Light Load Operation ................................................................ 19

Recommended Component Manufacturers ........................... 19

Layout Considerations ................................................................... 20

Efficiency Considerations ............................................................. 21

Examples of Application Circuits ................................................. 22

Standard Boost Converter—Design Example ........................ 22

Bootstrapped Boost Converter ................................................. 23

SEPIC Converter Circuit ........................................................... 27

Low Voltage Power-Input Circuit ............................................ 27

LED Driver Application Circuits ............................................. 28

Related Devices ............................................................................... 30

Outline Dimensions ....................................................................... 31

Ordering Guide .......................................................................... 31

12/06—Rev. 0 to Rev. A

Changes to Table 1 ............................................................................. 3

Changes to Table 2 ............................................................................. 5

Added Table 3 .................................................................................... 5

Changes to Table 5 .......................................................................... 19

Changes to Ordering Guide .......................................................... 31

7/06—Revision 0: Initial Version

Rev. D | Page 2 of 32

Data Sheet

SIMPLIFIED BLOCK DIAGRAM

FB

COMP

V

OSC

1.4V

V

REF

1.215V

FREQ

CS

PGND

GND

+

+

g m

ERROR

AMPLIFIER

SOFT START

(2048 CYCLES)

5.5V

PIN n

OSC

SET

SLOPE

COMP

PWM

COMPARATOR

S

R

UVLO

100kΩ

GATE

DRIVER

5.5V

GATE

IN

SDSN

ADP1621

Figure 3. ADP1621 Simplified Block Diagram

ADP1621

Rev. D | Page 3 of 32

ADP1621

SPECIFICATIONS

V

IN

= 5 V, R

FREQ

= 100 kΩ, f

OSC

= 200 kHz, T

J

= −40°C to 125°C, unless otherwise noted.

Data Sheet

Table 1.

Parameter

MAIN CONTROL LOOP

Internal Soft Start Time

PIN Supply Voltage 1

IN Supply Voltage

Shunt Resistance

FB Input Current

Line Regulation

Load Regulation

2

3

1

Shunt Regulation Voltage

IN Quiescent Current

IN Shutdown Current

PIN Supply Current

Static Mode, No Switching

Shutdown Mode

Undervoltage Lockout Threshold at

IN Pin

FB Regulation Voltage

Error Amplifier Transconductance

COMP Zero-Current Threshold

COMP Clamp High Voltage

Current-Sense Amplifier Gain

Peak Slope-Compensation Current at

CS Pin 4

t

I

I

Symbol

V

SS

PIN

V

IN

V

SHUNT

R

SHUNT

V

IN

PIN

UVLO

CS Pin Leakage Current

Shutdown Time

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis 5

5

I

CS,LEAK t

SD

T

TMSD

OSCILLATOR

Oscillator Frequency Range

Oscillator Frequency

6

Oscillator Frequency Tempco

SDSN Input Level Threshold f

OSC f

OSC f

OSC,TC

V

SDSN,THRESH

SDSN Threshold Hysteresis

SDSN Internal Pull-Down Resistor R

SDSN

Synchronization Minimum Pulse Width t

SYNC,MIN

Synchronization Maximum Pulse Width t

SYNC,MAX

Test Conditions/Comments

I

IN

= 3 mA, I

PIN

= 3 mA, T

A

= 25°C

I

IN

= 3 mA, I

PIN

= 3 mA

Current into IN = 8 mA to 12 mA

Current into PIN = 8 mA to 12 mA

V

IN

= 2.9 V to 5.5 V, V

FB

= 1.215 V

V

IN

= 2.9 V to 5.5 V, SDSN = GND

V

FB

= 1.3 V, V

COMP

< V

COMP,ZCT

, GATE = 0 V

SDSN = GND

V

UVLO

R

FREQ

V

IN

= V

PIN

= 5 V

V

SDSN

V

SDSN

rising

= 65 kΩ, T

A

= 0 V to V

IN

= 25°C

= 0 V to V

IN

Min Typ

2.9

2.9

5.2

5.0

2.2

1.5

2048

7

1.8

1

5.4

5.4

13

1

1

2.5

I

V

FB

I

FB

∆V

FB

/∆V

IN

∆V g

V

V n m

COMP,ZCT

SC,PK

COMP,CLAMP

V

T

V

UVLO

A

FB

FB

/∆V

COMP

V

COMP

hysteresis

= 25°C

= 1.215 V, T

2.9 V ≤ V

2.9 V ≤ V

IN

IN

A

= 25°C

≤ 5 V, T

≤ 5 V, T

J

J

= −40°C to +85°C

= −40°C to +125°C

= 1.4 V to 1.5 V

−80

1.203 1.215

1.197 1.215

−75 +25

0.02

−1

0.02

−0.1

T

T

J

J

= −40°C to +85°C

= −40°C to +125°C

V

CS

= 0 V to 100 mV maximum across R

S

(GATE high)

V

CS

= 30 V (GATE low)

SDSN pin from high to low or left floating

300

0.85 1.0

1.9

1.9

2.0

2.0

7.5

55

9.5

70

50

150

−10

100

255 325

±0.06

1.7

−0.19

100

Max Unit

Cycles

V

SHUNT

V

3

10

V

SHUNT

V

5.7 V

6.0 V

Ω mA

µA

10

10

2.8

µA

µA

V mV

1.227 V

1.233 V

+75 nA

0.06 %/V

0.072 %/V

%

µS

1.15 V

2.1

2.2

V

V

11.5 V/V

85 µA

5

1500

395

1.9

45

0.8/f

SYNC

100

µA

µs

°C

°C kHz kHz

%/°C

V

V kΩ ns ns

Synchronization Frequency

GATE Minimum On Time

GATE Minimum Off Time

Maximum Duty Cycle 6, 7

Recommended Maximum

Synchronized Frequency Ratio 6, 8

f

SYNC t

ON,MIN t

OFF,MIN

D

MAX f

SYNC

/f

OSC

V

FB

= 1.215 V, V

COMP

= 1.0 V

V

FB

= 1.215 V, V

COMP

= 2.0 V

110 f

SW

= 200 kHz, R

FREQ

= 100 kΩ 93 f

OSC

= 200 kHz, R

FREQ

= 100 kΩ, f

SYNC

= f

SW

1.1

180

190

1.2

1800 kHz

215 ns

230 ns

97

1.4

%

Rev. D | Page 4 of 32

Data Sheet ADP1621

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

GATE DRIVER

GATE Rise Time 9

GATE Fall Time 9 t

R t

F

C

GATE

= 3.3 nF

C

GATE

= 3.3 nF

17

13 ns ns

1

2

The maximum input voltage is the shunt regulation voltage, which is typically 5.5 V and can range from 5.3 V to 6.0 V over the specified temperature range.

The ADP1621 is tested in a feedback servo loop, which servos V

2.9 V to 5 V. The line regulation is calculated by (∆V

FB

/V

FB

to the internal reference voltage. The voltage change in FB is measured while V

FB

) × 100%/∆V

IN

.

IN

is changed from

4

3 The ADP1621 is tested in a feedback servo loop, which servos V

(1.0 V ≤ V

COMP

≤ 2.0 V).

The peak

FB

to the internal reference voltage, and V

COMP

is forced from 1.4 V to 1.5 V. The V slope-compensation current at the CS pin is typically 70 µA, and effectively clamped at 116 mV. Thus, R

COMP

range is

S

should not exceed 1.6 kΩ (116 mV/70 µA).

5 Guaranteed by design for thermal shutdown. When the thermal junction temperature of the ADP1621 reaches approximately 150°C, the ADP1621 goes into thermal

6 f shutdown and the GATE voltage is pulled low. When the junction temperature drops below about 140°C, the soft start sequence is initiated and the ADP1621 resumes normal operation.

OSC

is the natural oscillation frequency, f

SYNC

is the synchronization frequency, and f

SW

is the switching frequency. If synchronization is used, then f

SW

= f

SYNC

; otherwise, f

SW

= f

OSC

.

7 Guaranteed by design and bench characterization.

8 To ensure proper synchronization operation, set the synchronization frequency, f

SYNC

, to 1.2× of the free-running frequency, f

OSC

. Although the switching frequency can f be synchronized to as high as 1.8 MHz, the peak slope-compensation current decreases at higher synchronization frequencies. It is recommended that the maximum

SYNC

be less than 1.4× of f

OSC

and should not exceed 1.8 MHz. Choose the slope-compensation resistor, R

S

Compensation section in the Application Information: Boost Converter section).

9 GATE rise and fall times are measured from 10% to 90% levels.

, for the synchronization frequency (see the Slope

Rev. D | Page 5 of 32

ADP1621

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

IN to GND

FB, COMP, SDSN, FREQ, GATE to GND

CS to GND

PIN to PGND

−0.3 V to V

SHUNT

−0.3 V to (V

IN

+ 0.3 V)

−5 V to +33 V

−0.3 V to V

SHUNT

Supply Current into IN

Supply Current into PIN

25 mA

35 mA

Storage Temperature Range −55°C to +150°C

Junction Operating Temperature Range

1

−55°C to +150°C

Junction Storage Temperature Range

Lead Temperature (Soldering, 10 sec)

Package Power Dissipation 1

−55°C to +150°C

300°C

(T

J,MAX

− T

A

)/θ

JA

1

In applications where high power dissipation and poor package thermal resistance are present, the maximum ambient temperature may need to be derated. Maximum ambient temperature (T

A,MAX

) is dependent on the maximum operating junction temperature (T

J,MAX

= 150 o C), the maximum power dissipation of the device in the application (P

D,MAX

), and the junction-to-ambient thermal resistance of the package in the application (θ

JA

), is given by the following equation: T

A,MAX

= T

J,MAX

– (θ

JA x P

D,MAX

).

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

Data Sheet

Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND.

THERMAL RESISTANCE

θ

JA

is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θ

JA

Unit

10-Lead MSOP on a 2-Layer Printed Circuit Board (PCB) 200 °C/W

10-Lead MSOP on a 4-Layer PCB 172 °C/W

Junction-to-ambient thermal resistance of the package is based on modeling and calculation using 2-layer and 4-layer boards, and natural convection. The junction-to-ambient thermal resistance is application- and board-layout dependent. In applications where high maximum power dissipation exists, attention to thermal dissipation issues in board design is required.

ESD CAUTION

Rev. D | Page 6 of 32

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SDSN

1

GND

2

COMP

3

FB

4

FREQ

5

ADP1621

TOP VIEW

(Not to Scale)

10

IN

9

8

7

6

CS

PIN

GATE

PGND

Figure 4. Pin Configuration

ADP1621

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 SDSN ADP1621 on by driving SDSN high; turn it off by driving SDSN low.

If SDSN is left floating or when the SDSN is pulled low, the ADP1621 goes into shutdown after 50 μs. If synchronization is needed, synchronize the switching frequency to an external clock by connecting the external clock to the SDSN pin. An internal 100 kΩ pull-down resistor is connected from SDSN to GND.

2 GND Ground.

Connect a series RC from COMP to GND to compensate the regulator. The nominal voltage range for this pin is

1.0 V to 2.0 V.

4 FB Feedback Input. FB is the input to the internal transconductance error amplifier. Drive FB from the output voltage through a resistive voltage divider. The ratio of the voltage divider sets the output voltage. The regulation voltage at FB is nominally 1.215 V. between 100 kHz and 1.5 MHz. The nominal voltage of this pin is 1.4 V. current-sense amplifier. Connect PGND to GND as close to the ADP1621 as possible. external n-channel power MOSFET. Connect GATE to the gate of the MOSFET.

8 PIN Power Input. PIN powers the gate driver output. An internal 5.5 V shunt regulator is connected to this pin. Bypass

PIN to PGND with a 0.1 μF or greater capacitor.

9 CS Current-Sense Input. CS is the positive input of the current-sense amplifier. When GATE is turned on, the voltage at the CS pin increases linearly from 0 V to a maximum of 116 mV, and the nominal peak slope-compensation output current is 70 μA. When GATE is off, the CS function is disabled. For current sensing in lossless mode, connect CS to the drain of the power MOSFET. The absolute maximum voltage at CS is 33 V. For higher accuracy current sensing or higher switch-node voltages, connect CS to a current-sense power resistor in the source of the power MOSFET.

In both sensing methods, it is required to add a slope-compensation resistor, R

S

, to the CS pin to achieve stability in the inductor current for duty cycles greater than 50%. However, it is recommended to add R

S

for all duty cycles because load transients can momentarily cause the duty cycle to be greater than 50%, even when the steadystate duty cycle is less than 50%.

10 IN Input Voltage. IN powers the ADP1621 internal circuitry. An internal 5.5 V shunt regulator is connected to this pin.

Bypass IN to GND with a 0.1 μF or greater capacitor.

Rev. D | Page 7 of 32

ADP1621

TYPICAL PERFORMANCE CHARACTERISTICS

100

90

80

70

60

50

40

30

0.01

f

T

A

= 25°C

SW

= 220kHz

V

V

IN

= 3.3V

OUT

= 5V

0.1

LOAD CURRENT (A)

1

Figure 5. Efficiency vs. Load Current

10

T

A

= 25°C

V

V

IN

= 3.3V

OUT

= 5V

LOAD = 1A

V

OUT

RIPPLES @ 5V

AC-COUPLED

1

2

CH2 = GATE

CH1 20mV CH2 2V M2µs A CH2 2.6V

Figure 6. Output Voltage Ripple of the Circuit Shown in Figure 1

1.21605

T

A

= 25°C

1.21600

1.21595

1.21590

1.21585

1.21580

1.21575

2.5

3.0

3.5

4.0

V

IN

(V)

4.5

Figure 7. V

FB

vs. V

IN

5.0

5.5

6.0

Data Sheet

90

89

88

87

92

91

LOAD = 0.5A

LOAD = 1A

86

85

T

A

= 25°C

V

IN

V

= 3.3V

OUT

= 5V

84

100 300 500 700 900 1100

SWITCHING FREQUENCY (kHz)

1300

Figure 8. Efficiency vs. Switching Frequency

1500

100

0.1

0.01

0.001

10

1

0.0001

0.00001

0

I

IN

I

PIN

T

A

= 25°C

NO SWITCHING

1 2 3 4

SUPPLY VOLTAGE (V)

5

Figure 9. Supply Current vs. Supply Voltage

6 7

2.5

T

A

V

IN

= 25°C

= 5V

2.0

1.5

1.0

0.5

0

1.17

1.19

1.21

1.23

V

FB

(V)

1.25

Figure 10. V

COMP

vs. V

FB

1.27

1.29

Rev. D | Page 8 of 32

Data Sheet

45

40

35

30

25

MOSFET Q

G

= 25nC

20

15

MOSFET Q

G

= 15nC

10

5

MOSFET Q

G

= 7nC

0

0 200 400 600 800 1000 1200

SWITCHING FREQUENCY (kHz)

1400 1600

Figure 11. PIN Supply Current vs. Switching Frequency

1800

2.60

SDSN = 5V

2.55

2.50

2.45

1.01

1.00

0.99

0.98

0.97

–50

2.40

–50 0 50

TEMPERATURE (°C)

100

Figure 12. V

UVLO

Threshold vs. Temperature

1.03

V

IN

= 5V

1.02

0 50

TEMPERATURE (°C)

100

Figure 13. Frequency vs. Temperature

150

150

ADP1621

35

30

25 t

T

A

= 25°C

V

IN

R

= V

PIN

OR t

F

= 5V

IS FROM

10% TO 90% OF

THE GATE VOLTAGE

20 t

R t

F

196

195

194

193

192

191

2

15

10

5

0

0

198

5 10 15 20 25 30 35

GATE CAPACITANCE (nF)

40

Figure 14. GATE Rise and Fall Times vs. C

GATE

45 50

1600

1500

1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

0 20 40 60 80 100 120 140 160 180

R

FREQ

(k

Ω)

Figure 15. Oscillator Frequency vs. Resistance

200

197

T

A

= 25°C

R

FREQ

= 100k

3 4

V

IN

(V)

Figure 16. Oscillator Frequency vs. V

IN

5

Rev. D | Page 9 of 32

ADP1621

250

V

IN

= 5V

CS = 30V

200

150

100

50

0

–40 10 60

CS LEAKAGE (nA)

110

Figure 17. Temperature vs. CS Leakage

160

8

4

0

V

FB

= 1.2113V AT 25°C

FB BIAS CURRENT IS MEASURED

BY FORCING A CONSTANT 1.2113V

OVER THE TEMPERATURE RANGE.

–4

–8

–12

–16

–50 0 50

TEMPERATURE (°C)

100

Figure 18. FB Bias Current vs. Temperature

150

90

80

30

20

10

50

40

70

60 f

OSC

= 550kHz f

OSC

= 200kHz

0

1.0

1.2

1.4

1.6

f

SYNC

/ f

OSC

1.8

2.0

Figure 19. Slope-Compensation Current vs. f

SYNC

/f

OSC

2.2

4

Data Sheet

1.0

0.8

0.6

0.4

1.6

1.4

V

IN

= 5V

SDSN = 0V

1.2

0.2

0

–50 0 50

TEMPERATURE (°C)

100

Figure 20. Shutdown IN Current vs. Temperature

1.2165

1.2160

1.2155

1.2150

1.2145

1.2140

1.2135

1.2130

1.2125

1.2120

–50

V

IN

= 5V

SDSN = 0V

0 50

TEMPERATURE (°C)

100

Figure 21. FB Voltage vs. Temperature

150

150

T

A

V

IN

V

= 25°C

= 3.3V

OUT

= 5V

LOAD = 0.1A

DCM OPERATION

CH4 = INDUCTOR CURRENT

2

CH2 = DRAIN VOLTAGE

1

CH1 = GATE

CH1 5V CH2 5V

CH4 500mAΩ

M2µs A CH1 2.9V

Figure 22. DCM Switching Waveform

Rev. D | Page 10 of 32

Data Sheet

T

A

= 25°C

V

V

IN

= 3.3V

OUT

= 5V

LOAD = 0.3A

CCM OPERATION

4

CH4 = INDUCTOR CURRENT

2

CH2 = DRAIN VOLTAGE

1

CH1 5V

CH1 = GATE

CH2 5V

CH4 500mAΩ

M2µs A CH1 2.9V

Figure 23. CCM Switching Waveform

T

A

= 25°C

V

IN f

= 3.3V

V

OUT

= 5V

SW

= 220kHz

SOFT-START = 9.3ms

CH1 = V

OUT

CH2 = SDSN

2

1

3

CH1 1V

CH3 5V

CH3 = GATE

A CH1 4.5V

CH2 5V M2ms

Figure 24. Soft Start Waveform

T

A

= 25°C

V

OUT

= 5V

LOAD AT V

OUT

= 1A

CH1 = V

OUT

, AC-COUPLED

1

CH2 = V

IN

FROM 3V TO 4V

2

CH1 50mV CH2 2V M400µs A CH2 3.8V

Figure 25. Line Transient Response of the Configuration Shown in Figure 1

with a 1 A Load

4

ADP1621

LOAD CURRENT

FROM 0.2A TO 1.2A

1

OUTPUT, AC-COUPLED

T

A

V

IN

= 25°C

= 3.3V

V

OUT

= 5V

CH1 50mV M200µs A CH4 700V

CH4 1AΩ

Figure 26. Load Transient Response of the Circuit Shown in Figure 1

T

A

= 25°C

V

OUT

= 5V

NO LOAD AT V

OUT

CH1 = V

OUT

, AC-COUPLED

1

CH2 = V

IN

FROM 3V TO 4V

2

CH1 50mV CH2 2V M400µs A CH2 3.8V

Figure 27. Line Transient Response of the Configuration Shown in Figure 1

with No Load

Rev. D | Page 11 of 32

ADP1621

THEORY OF OPERATION

The ADP1621 is a fixed-frequency, current-mode, step-up dc-todc converter controller. It drives an external n-channel MOSFET to step the input voltage up to a higher output voltage. It can be used for SEPIC, flyback, boost, buck-boost, forward, and other converter topologies. It operates at a fixed switching frequency that is set by an external resistor over a range of 100 kHz to 1.5 MHz, and it can be synchronized to an external clock by connecting the SDSN pin to the clock.

The input supply current to the ADP1621 is less than 3 mA during normal operation and less than 10 μA during shutdown.

The ADP1621 can drive large external MOSFETs, allowing it to support load currents in excess of 10 A.

CONTROL LOOP

The ADP1621 uses a current-mode architecture to regulate the output voltage. The output voltage is monitored at FB through a resistive voltage divider. The voltage at FB is compared to the internal 1.215 V reference voltage by the internal transconductance error amplifier to create an error current at COMP. A resistorcapacitor compensation impedance connected from COMP to

GND converts the error current to an error voltage.

At the beginning of the switching cycle, the MOSFET is turned on and the inductor current ramps up. The MOSFET current is measured and converted to a voltage using R

CS

or R

DSON

and is added to the stabilizing slope-compensation ramp. The resulting voltage sum passes through the current-sense amplifier to generate the current-sense voltage. When the current-sense voltage is greater than the COMP error voltage, the MOSFET is turned off and the inductor current ramps down until the internal clock initiates the next switching cycle. The duty-cycle of the PWM modulator is thus adjusted to provide the necessary load current at the desired output voltage. Because the output voltage ultimately controls the peak inductor current through the COMP error voltage, this scheme is referred to as peak current-mode control.

With light loads, the converter can also operate under discontinuous conduction mode and pulse-skipping modulation to maintain output-voltage regulation. These two forms of operation

are discussed in detail in the Light Load Operation section.

Note that the converter can also be designed to operate in discontinuous conduction mode at full load if desired.

Overall, the current-mode regulation system of the ADP1621 allows fast transient responses while maintaining a stable output voltage. By selecting the proper resistor-capacitor network from

COMP to GND, the regulator response can be optimized for a wide range of input voltages, output voltages, and load currents.

Data Sheet

CURRENT-SENSE CONFIGURATIONS

The ADP1621 can sense the current across the on resistance of the MOSFET to minimize external component count and improve efficiency by eliminating the power that would be lost in a currentsense resistor. This lossless technique eliminates the need for an expensive current-sense resistor. In the lossless mode configuration, the voltage at the CS pin (or the switch-node voltage at the drain of

the MOSFET) must not exceed 30 V (see Figure 28). This technique

maximizes efficiency and reduces cost. In practice, when the calculated V

SW

approaches 30 V, build the board and measure the actual V

SW

before committing to the lossless mode design.

Because of the parasitic inductance in the diode, output capacitor, and PCB traces, V

SW

typically has narrow peaks that exceed the theoretical maximum voltage at V

SW

—the sum of V

OUT

and the forward-voltage drop of Diode D1. If the measured peak voltage exceeds 30 V, or if a more accurate current limit is desired, then the CS pin can be connected to an external current-sense resistor

in the source of the MOSFET (Figure 29). The maximum power

output is limited by the selection of the external components.

V

IN

L D1

V

OUT

PIN IN

ADP1621

SDSN

CS

GATE

PGND GND

R

S

V

SW

C

O

Figure 28. CS Pin Connection for V

SW

< 30 V, Lossless Mode

(No Current-Sense Resistor Needed)

V

IN

L

V

SW

D1

V

OUT

PIN IN

GATE

ADP1621

SDSN

CS

PGND GND

R

S

R

CS

C

O

Figure 29. CS Pin Connection for V

SW

> 30 V, Resistor Sense Mode with a Current-Sense Resistor, R

CS

Rev. D | Page 12 of 32

Data Sheet

CURRENT LIMIT

The current limit is achieved by the COMP voltage clamp, owing to the current-mode operation of the ADP1621 . A detailed explanation of how the current limit is determined can be found

in the Current Limit section of the Application Information:

Boost Converter section.

UNDERVOLTAGE LOCKOUT

An internal undervoltage lockout (UVLO) circuit at the IN pin holds the GATE voltage low when the IN voltage is below the

UVLO voltage, which is typically 2.5 V.

SHUTDOWN

The ADP1621 goes into shutdown approximately 50 µs after the

SDSN pin is pulled low or left floating. There is an internal 100 kΩ resistor connected between SDSN and GND.

When the junction temperature of the ADP1621 reaches about

150°C, the ADP1621 goes into thermal shutdown and the

GATE voltage is pulled low. When the junction temperature drops below about 140°C, the ADP1621 resumes normal operation after the soft start sequence.

SOFT START

The ADP1621 has an internal soft start circuit that ramps the FB regulation voltage from 0 V to 1.215 V in 64 steps over

2048 clock oscillator cycles. This soft start ramp allows the output voltage to slowly rise to the steady-state output voltage, preventing input inrush current at startup.

INTERNAL SHUNT REGULATORS

The IN and PIN pins each have an internal shunt regulator that allows the ADP1621 to operate over a wide input voltage range.

The shunt regulators limit the voltages at IN and PIN to about

5.5 V, allowing the use of logic-level MOSFETs independent of the input and/or output voltage. The shunt regulator voltage can

reach 5.7 V at 10 mA. See Figure 9 for the I-V characteristics of

these shunt regulators.

The internal power is derived from the IN pin, whereas the

MOSFET gate driver (GATE) current comes from the power input, PIN. By separating the two inputs, PIN can be driven with an external small-signal NPN transistor to limit the power loss in the PIN shunt regulator when the input voltage is higher

than 5.5 V. See Figure 37 for an example. The maximum currents

going into PIN and IN must not exceed 35 mA and 25 mA, respectively.

ADP1621

SETTING THE OSCILLATOR FREQUENCY AND

SYNCHRONIZATION FREQUENCY

The free-running oscillator frequency, f

OSC

, is set by a resistor from FREQ to GND. A 100 kΩ resistor sets the typical oscillator frequency to 200 kHz, a 65 kΩ resistor sets it to 325 kHz, a 32 kΩ resistor sets it to 600 kHz, and a 10 kΩ resistor sets it to 1.5 MHz.

Figure 30 shows a typical relationship between f

OSC

and R

FREQ

.

1600

1500

1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

0 20 40 60 80 100 120 140 160 180

R

FREQ

(k

Ω)

200

Figure 30. f

OSC

vs. R

FREQ

The switching frequency can be synchronized to an external clock by driving the SDSN pin with that clock signal. The SDSN pin serves the two functions of shutdown control and frequency synchronization input. If the SDSN input detects a low-to-high transition within 10 µs of a high-to-low transition, it resets the oscillator to synchronize to the frequency of the signal at SDSN.

The ADP1621 only synchronizes to frequencies greater than the free-running switching frequency. To ensure proper synchronization operation, set the synchronization frequency, f

SYNC

, to 1.2× the freerunning frequency, f

OSC

. The switching frequency, f

SW

, is equal to f

SYNC

. Although the switching frequency can be synchronized to as high as 1.8 MHz, the peak slope-compensation current decreases at higher f

SYNC

. It is recommended that the maximum f

SYNC

be less than 1.4× of f

OSC

. Choose the slope-compensation resistor, R

S

, for

the synchronization frequency (see the Slope Compensation

section). For SDSN to detect a high input, the high state must remain high for at least 100 ns.

Rev. D | Page 13 of 32

ADP1621 Data Sheet

APPLICATION INFORMATION: BOOST CONVERTER

In this section, an analysis of a boost converter is presented, along with guidelines for component selection. A typical boost-

converter application circuit is shown in Figure 1.

ADIsimPower DESIGN TOOL

The ADP1621 is supported by ADIsimPower design tool set.

SETTING THE OUTPUT VOLTAGE

The output voltage is set through a voltage divider from the output voltage to the FB input. The feedback resistor ratio sets the output voltage of the system. The regulation voltage at FB is 1.215 V. The

output voltage is given by the following equation (see Figure 1):

ADIsimPower is a collection of tools that produce complete power designs optimized for a specific design goal. The tools enable the user to generate a full schematic, bill of materials, and calculate performance in minutes. ADIsimPower can optimize designs for cost, area, efficiency, and device count while taking into consideration the operating conditions and limitations of the IC and all real external components. For more information about ADIsimPower design tools, refer to www.analog.com/ADIsimPower . The tool set is available from this website, and users can also request an unpopulated board through the tool.

DUTY CYCLE

To determine the worst-case inductor current ripple, output voltage ripple, and slope-compensation factor, it is first necessary to determine the system duty cycle. The duty cycle in continuous conduction mode (CCM) is calculated by the following equation:

D

=

V

OUT

+

V

OUT

V

D

+

V

D

V

IN

(1)

V

OUT

=

1 .

215

The input bias current into FB is 25 nA typical, 70 nA maximum.

For a 0.1% degradation in regulation voltage and with 70 nA bias current, R2 must be less than 18 kΩ, which results in 68 µA of divider current. Choose the value of R1 to set the output voltage. Using higher values for R2 results in reduced output voltage accuracy due to the input bias current at the FB pin, whereas lower values cause increased quiescent current consumption.

INDUCTOR CURRENT RIPPLE

Choose a peak-to-peak inductor ripple current between 20% and 40% of the average inductor current. A good starting point for a design is to choose the peak-to-peak ripple current to be

30% of 1/(1 − D) times the maximum load current:

I

L

where:

=

0 .

3

×

I

V

×

LOAD

,

1

MAX

D

R1

R2

(4)

(5) where:

V

OUT

is the desired output voltage.

V

IN

is the input voltage.

V

D

is the forward-voltage drop of the diode. A typical Schottky diode has a forward-voltage drop of 0.5 V.

The GATE minimum on and off times determine the minimum and maximum duty cycles, respectively. The minimum on and off times are typically 180 ns and 190 ns, respectively. The minimum and maximum duty cycles are given by the following equations:

D

MIN

=

t

ON

,

MIN t

SW

=

t

ON

,

MIN

×

f

SW

D

MAX

=

1

t

OFF

,

MIN t

SW

=

1

(

t

OFF

,

MIN

×

f

SW

)

(2)

ΔI

L

is the peak-to-peak inductor ripple current.

I

LOAD,MAX

is the maximum load current required by the application.

INDUCTOR SELECTION

The inductor value choice is important because it dictates the inductor current ripple and therefore the voltage ripple at the output.

The average inductor current, I equation:

L,AVE

, is given by the following

I

L

,

AVE

=

I

1

LOAD

D

and the peak-to-peak inductor ripple current is inversely proportional to the inductor value:

(6)

(3)

I

L

=

V

IN f

SW

×

×

D

L

(7) where:

t f t

D

MIN

is the minimum duty cycle.

D

MAX

is the maximum duty cycle.

t

ON,MIN

is the minimum on time.

OFF,MIN

is the minimum off time.

SW

SW

is the switching period.

is the switching frequency.

Note that when the converter tries to operate at a duty cycle lower than D

MIN

, pulse-skipping modulation occurs to maintain

the output voltage regulation (see the Light Load Operation

section).

f

where:

SW

is the switching frequency.

L is the inductor value.

Assuming continuous conduction mode (CCM) operation, the peak inductor current is given by the following equation:

=

I

1

LOAD

D

+

I

L

2

=

I

1

LOAD

D

+

2

V

IN

×

f

×

SW

D

×

L

(8)

Rev. D | Page 14 of 32

I

L

,

PK

Data Sheet

Smaller inductor values are typically smaller in size and usually less expensive, but increase the ripple current. Larger ripple current also increases the power loss in the inductor core. Too large an inductor value results in added expense and may impede load transient responses because it reduces the effect of slope compensation.

Assuming the ripple current is 30% of 1/(1 − D) times the maximum load current, a reasonable choice for the inductor value is

L

=

0 .

V

3

×

IN f

×

SW

D

×

×

(

1

I

LOAD

D

)

,

MAX

(9)

From this starting point, modify the inductance to obtain the right balance of size, cost, and output voltage ripple while maintaining the inductor ripple current between 20% and 40% of 1/(1 − D) times the maximum load current. Keep in mind that the inductor saturation current must be greater than the peak inductor current. Magnetically shielded inductors are generally recommended, although they cost slightly more than unshielded inductors.

Also, losses due to the inductor winding resistance reduce the efficiency of the boost converter. This power loss is given by

P

L

,

W

=

I

1

LOAD

D

2

×

R

W

where:

P

L,W

is the power dissipation in the winding of the inductor.

R

W

is the winding resistance.

(10)

INPUT CAPACITOR SELECTION

The bulk input capacitor provides a low impedance path for the

inductor ripple current. Capacitor C1 in Figure 1 represents a

bulk input capacitor. Choose a bulk input capacitor whose impedance at the switching frequency is lower than the impedance of the voltage source V

IN

.

The preferred bulk input capacitor is a 10 µF to 100 µF ceramic capacitor because it has low equivalent series resistance (ESR) and low impedance. Aluminum electrolytic and aluminum polymer capacitors can also be used as the bulk input capacitors. The bulk input capacitor does not need to be placed very close to the IN and PIN pins. Aluminum electrolytic capacitors are the cheapest and generally have high ESR values, which increase dramatically at temperatures less than 0°C. Some aluminum electrolytic capacitors have ESR less than 20 mΩ, but their capacitances are generally greater than 800 µF. Aluminum polymer capacitors are more expensive than the aluminum electrolytic ones, but are generally cheaper than the ceramic capacitors for the same amount of capacitance. Polymer capacitors have relatively low ESR, with some models having less than 10 mΩ.

Rev. D | Page 15 of 32

ADP1621

Regardless of the type of capacitor used, make sure the ripple current rating of the bulk input capacitor, I

CIN,RMS

, is greater than

I

CIN

,

RMS

=

1

3

×

I

L

2

(11) where ΔI

L

is the peak-to-peak inductor ripple current.

In addition to the bulk input capacitor, a bypass input capacitor is required. The function of the bypass capacitor is to locally filter the input voltage to the ADP1621 and maintain the input voltage at a steady value during switching transitions. The bypass capacitor is typically a 0.1 µF or greater ceramic capacitor and should be placed as close as possible to the IN and PIN pins of the ADP1621 .

Capacitors C3 and C4 in Figure 1 represent the bypass capacitors.

OUTPUT CAPACITOR SELECTION

The output capacitor maintains the output voltage and supplies current to the load while the external MOSFET is on.

The value and characteristics of the output capacitor greatly affect the output voltage ripple and stability of the converter.

The amount of peak-to-peak output voltage ripple, ΔV

OUT

, can be approximated by

V

OUT

I

LOAD

1

D

+

I

L

2 

×



2

π ×

f

SW

1

×

C

OUT



2

+

ESR

2 +

(

2

π ×

f

SW

×

ESL

)

2

(12) where:

ΔI

L

is the peak-to-peak inductor ripple current.

f

SW

is the switching frequency.

C

OUT

is the output capacitance.

ESR is the effective ESR of C

OUT

.

ESL is the effective equivalent series inductance of C

OUT

.

Because the output capacitor is typically greater than 40 µF, the

ESR dominates the output capacitance impedance and thus the output voltage ripple. The use of low ESR, ceramic dielectric capacitors is preferred, although aluminum electrolytic, tantalum, OS-CON™ (from Sanyo), and aluminum polymer capacitors can be used. At higher switching frequencies, the ESL of the output capacitor may also be a factor in determining the output voltage ripple. Multiple capacitors can be connected in parallel to reduce the effective ESR and ESL. Keep in mind that the capacitance of a given capacitor typically degrades with increased temperature and bias voltage. Consult the capacitor manufacturer’s data sheet when determining the actual capacitance of a capacitor under certain conditions.

Ensure that the output capacitor ripple current rating, I

COUT,RMS

, is greater than

I

COUT

,

RMS

=

I

LOAD

×

1

D

D

(13)

ADP1621

DIODE SELECTION

The diode conducts the inductor current to the output capacitor and load while the MOSFET is off. The average diode current is the load current:

I

DIODE

,

AVE

=

I

LOAD

(14)

The rms diode current in continuous conduction mode is given by

I

DIODE

,

RMS

=

I

1

LOAD

D

× where D is the duty cycle.

1

D

The power dissipated in the diode is

P

DIODE

=

V

D

×

I

LOAD

(15)

(16) where V

D

is the forward-voltage drop of the diode.

The total power dissipation determines the diode junction temperature, which is given by

T

J

,

DIODE

=

T

A

+

P

DIODE

×

θ

JA

(17) where:

T

J,DIODE

is the junction temperature.

T

A

is the ambient temperature.

θ

JA

is the junction-to-ambient thermal resistance of the diode package. The diode junction temperature must not exceed its maximum rating at the given power dissipation level.

For high efficiency, Schottky diodes are recommended. The low forward-voltage drop of a Schottky diode reduces the power losses during the MOSFET off time, and the fast switching speed reduces the switching losses during the MOSFET transitions. However, for high voltage, high temperature applications where the reverse leakage current of the Schottky diode can become significant and degrade efficiency, use an ultrafast-recovery junction diode.

Make sure that the diode is rated to handle the average output load current. Many diode manufacturers derate the current capability of the diode as a function of the duty cycle. Verify that the diode is rated to handle the average output load current with the minimum duty cycle. Also, ensure that the peak inductor current is less than the maximum rated current of the diode.

MOSFET SELECTION

When turned on, the external n-channel MOSFET allows energy to be stored in the magnetic field of the inductor. When the MOSFET is turned off, this energy is delivered to the load to boost the output voltage.

The choice of the external power MOSFET directly affects the boost converter performance. Choose the MOSFET based on the following: threshold voltage (V

T

), on resistance (R

DSON

), maximum voltage and current ratings, and gate charge.

Rev. D | Page 16 of 32

Data Sheet

The minimum operating voltage of the ADP1621 is 2.9 V.

Choose a MOSFET with a V

T

that is at least 0.3 V less than the minimum input supply voltage at PIN used in the application.

Ensure that the maximum V

GS

rating of the MOSFET is at least a few volts greater than the maximum voltage that is applied to

PIN. Ensure that the maximum V

DS

rating of the MOSFET exceeds the maximum V

OUT

by at least 5 V to 10 V. Depending on parasitics, the MOSFET may be exposed to voltage spikes that exceed the sum of V

OUT

and the forward-voltage drop of the diode.

Estimate the rms current in the MOSFET under continuous conduction mode by

I

MOSFET

,

RMS

=

I

1

LOAD

D

×

D

(18) where D is the duty cycle. Derate the MOSFET current at least

20% to account for inductor ripple and changes in the forwardvoltage drop of the diode.

The MOSFET power dissipation due to conduction is thus

P

C

=

I

1

LOAD

D

2

×

D

×

R

DSON

×

(

1

+

K

)

(19) where:

P

C

is the conduction power loss.

R

DSON

is the MOSFET on resistance. The variable K is a factor that models the increase of R

DSON

with temperature:

K

=

0 .

005 /  C

×

(

T

J,MOSFET

25  C

)

(20) where T

J,MOSFET

is the MOSFET junction temperature. Note that multiple n-channel MOSFETs can be placed in parallel to reduce the effective R

DSON

.

The power dissipation due to switching transition loss is approximated by

P

SW

=

(

V

OUT

+

V

D

)

×

I

1

LOAD

D

2

×

t

(

R

+

t

F

)

×

f

SW

(21) where:

t

P

SW

is the switching power loss.

t

R

is the MOSFET rise time.

F

is the MOSFET fall time. The MOSFET rise and fall times are functions of both the gate drive circuitry and the MOSFET used in the application.

The total power dissipation of the MOSFET is the sum of the conduction and transition losses:

P

MOSFET

=

P

C

+

P

SW

(22) where P

MOSFET

is the total MOSFET power dissipation. Ensure that the maximum power dissipation is significantly less than the maximum power rating of the MOSFET.

Data Sheet

The total power dissipation also determines the MOSFET junction temperature, which is given by

T

J

,

MOSFET

=

T

A

+

P

MOSFET

×

θ

JA

(23) where:

T

J,MOSFET

is the junction temperature.

T

A

is the ambient temperature.

θ

JA

is the junction-to-ambient thermal resistance of the

MOSFET package. The MOSFET junction temperature must not exceed its maximum rating at the given power dissipation level.

If lossless current sensing is not used, there is also power dissipation in the external current-sense resistor, R

CS

. The power dissipation, P

CS

, in the external resistor due to conduction losses is given by

P

CS

=

I

1

LOAD

D

2

×

D

×

R

CS

(24)

LOOP COMPENSATION

The ADP1621 uses external components to compensate the regulator loop, allowing optimization of the loop dynamics for a given application.

The step-up converter produces an undesirable right-half plane

(RHP) zero in the regulation feedback loop. This RHP zero requires compensating the regulator such that the crossover frequency occurs well below the frequency of the RHP zero. The location of the RHP zero is determined by the following equation:

f

Z

,

RHP

=

(

1

D

)

2 ×

R

LOAD

2

π ×

L

where:

(25)

f

Z,RHP

is the RHP zero frequency.

R

LOAD

is the equivalent load resistance or the output voltage divided by the load current.

To stabilize the regulator, ensure that the regulator crossover frequency is less than or equal to one-fifth of the RHP zero frequency and less than or equal to one-fifteenth of the switching frequency. For an initial practical design, choose the crossover frequency f

C

to be the lower of

f

SW

15

(26) and

f

Z

,RHP

5 where:

f f

C

is the crossover frequency.

SW

is the switching frequency.

(27)

Rev. D | Page 17 of 32

ADP1621

The regulator loop gain is

A

VL

=

V

FB

V

OUT

×

(

1

D

)

×

g m

×

|

Z

COMP

|

×

n

×

1

R

CS

×

|

Z

OUT

| (28) where:

A

VL

is the loop gain.

V

FB

is the feedback regulation voltage (typically 1.215 V).

V

OUT

is the regulated output voltage.

D is the duty cycle.

g m

is the error amplifier transconductance gain (typically 300 µs).

Z

COMP

is the impedance of the RC network from COMP to GND.

n is the current-sense amplifier gain (typically 9.5).

R

CS

is the current-sense resistance.

Z

OUT

is the impedance of the load and output capacitor. In the case

of lossless current sensing, as shown in Figure 28, R

CS

is equal to the on resistance, R

DSON

, of the external power MOSFET. Otherwise,

R

CS

represents the external current-sense resistor, as shown in

Figure 29.

To determine the crossover frequency, it is important to note that at that frequency the compensation impedance, Z

COMP

, is dominated by Resistor R

COMP

, and the output impedance, Z

OUT

, is dominated by the impedance of the output capacitor, C

OUT

.

When solving for the crossover frequency, the equation is simplified to

|

A

VL

V

FB

V

OUT

|

=

×

(

1

D

)

×

g m

×

R

COMP

×

n

×

1

R

CS

×

2

π ×

f

C

1

×

C

OUT

=

1

(29) where:

f

C

is the crossover frequency.

R

COMP

is the compensation resistor.

C

OUT

is the output capacitance.

Solving for R

COMP

gives

R

COMP

=

2

π ×

f

C

×

V

FB

C

OUT

×

(

1

×

n

D

×

)

×

R

CS g m

×

V

OUT

(30)

After the compensation resistor, R

COMP

, is known, set the zero formed by the resistor and compensation capacitor, C one-fourth of the crossover frequency, or

COMP

, to

C

COMP

=

π ×

f

C

2

×

R

COMP

(31)

Capacitor C2 is chosen to cancel the zero introduced by the output

capacitance ESR. Thus, set C2 to (see Figure 31)

C

2

=

ESR

×

C

OUT

R

COMP

(32) where ESR represents the ESR of C

OUT

.

ADP1621

For low ESR output capacitors, such as ceramic capacitors, C2 is small, generally in the range of 10 pF to 400 pF. Because of the parasitic inductance, resistance, and capacitance of the PCB layout, the R

COMP

, C

COMP

, and C2 values might need to be adjusted by observing the load transient response of the ADP1621 to establish a stable operating system and achieve optimal transient performance. For most applications, R

COMP

is in the range of

5 kΩ to 100 kΩ, and C

COMP

is in the range of 100 pF to 30 nF.

REF

g m

COMP

3

2

R

COMP

C

COMP

C2

Figure 31. Compensation Components

SLOPE COMPENSATION

The ADP1621 includes a circuit that allows adjustable slope compensation. Slope compensation is required by currentmode regulators to stabilize the current-control loop when operating in continuous conduction and the switching duty cycle is greater than 50%.

Slope compensation is achieved by internally forcing a ramping current source out of the CS current-sense pin. By placing a resistor between the CS pin and the current sensing device (the drain of the external MOSFET in the case of lossless current sensing or the source of the MOSFET if a current-sense resistor is used), a voltage is developed across the resistor that is proportional to the slope-compensation current.

To ensure stability of the current-mode control loop, use a compensation voltage slope that is equal to or greater than onehalf of the current-sense representation of the inductor current downslope. Therefore, it follows that

2

×

R

S

×

1

I

SC,PK t

×

OFF, MIN f

SW

×

f

SW

>

R

CS

×

V

OUT

+

V

D

L

V

IN

(33) where:

R

S

is the slope-compensation resistor.

I

SC,PK

is the peak slope-compensation current.

f

SW

is the switching frequency.

R

CS

is the current-sense resistor.

V

OUT

is the regulated output voltage.

V

D

is the forward-voltage drop of the diode.

V

IN

is the input voltage.

t

OFF,MIN

is the minimum off time.

L is the power-stage inductor. In the case of lossless current sensing, R

CS

is equal to the on resistance, R

DSON

, of the external power MOSFET. Otherwise, R

CS

represents the external currentsense resistor.

Solving for R

S

gives the following slope-compensation criterion:

R

S

>

R

CS

×

(

V

OUT

+

2

V

×

D

I

SC

,

V

PK

IN

×

)

×

f

SW

(

1

×

t

OFF

L

,

MIN

×

f

SW

)

(34)

Rev. D | Page 18 of 32

Data Sheet

Keep in mind that the above inequality is a function of both

ADP1621 parameters and off-chip components, the values of which vary from device to device and with temperature. Select

R

S

to ensure current-loop stability for all possible variations.

After accounting for parameter variations, use values of R

S

that are as close to the calculated limit as possible because excessive slope compensation reduces the benefits of current-mode control and increases the “softness” of the current limit, as discussed in the

Current Limit section. Given a typical peak slope-compensation

current of 70 µA, R

S

must not exceed 1.6 kΩ because the voltage at the CS pin is typically clamped at 116 mV. It is also recommended that R

S

be greater than 20 Ω. If the calculated R

S

is greater than

1.6 kΩ, the parameters in Equation 34, such as R

CS

, f

SW

, and L, can be adjusted such that R

S

is less than 1.6 kΩ.

In conclusion, the value of R

S

should be 20 Ω ≤ R

S

≤ 1.6 kΩ.

CURRENT LIMIT

The current limit in the ADP1621 limits the peak inductor current and is achieved by the COMP voltage clamp. The peak inductor current, I

L,PK

, is given by

I

L

,

PK

=

V

COMP

,

CLAMP n

V

COMP

,

ZCT

R

CS

1

I

SC

,

PK t

×

R

S

OFF

,

MIN

×

×

D f

SW

(35) where:

I

V

COMP,CLAMP

is the COMP clamp voltage (typically 2.0 V).

V

COMP,ZCT

is the COMP zero-current threshold (typically 1.0 V).

n is the current-sense amplifier gain (typically 9.5).

SC,PK

is the peak slope-compensation current (typically 70 µA).

t

R

S

is the slope-compensation resistor.

D is the duty cycle.

f

SW

is the switching frequency.

OFF,MIN

is the minimum off time (typically 190 ns).

R

CS

is the current-sense resistor. In the case of lossless current sensing, R

CS

is equal to the on resistance, R

DSON

, of the external power MOSFET. Otherwise, R

CS

represents the external currentsense resistor.

The current limit in the ADP1621 is a soft current limit. When the inductor current reaches the I

L,PK

limit given in Equation 35, the duty cycle decreases, and the output voltage drops below the desired voltage. The I

L,PK

limit in Equation 35 then increases in response to the smaller duty cycle, D. The larger the slopecompensation resistor, R

S

, the larger the effect on I

L,PK

for an incremental decrease in D. This behavior results in a soft current limit for the ADP1621 . Use values of R

S

that are as close as possible to the calculated limit derived from Equation 34. If high-precision current limiting is required, consider inserting a fuse in series with the inductor.

Data Sheet ADP1621

Also, keep in mind that the current limit is a function of both

ADP1621 parameters and off-chip components, the values of which vary from device to device and with temperature. If lossless current sensing is used, consider that the on resistance of a MOSFET typically increases with increasing junction temperature. resonant frequency of the inductor and the total capacitance from the SW node to GND, which includes the capacitances of the MOSFET and diode, and any parasitic capacitances from the PCB. While adding a resistive element, such as a snubber, to the system further dampens the resonance, it also decreases the efficiency of the regulator.

The peak inductor current limit also limits the maximum load current at a given output voltage. The maximum load current, assuming CCM operation, is given by



I

LOAD

,

MAX

V

COMP

=

,

CLAMP

(

n

1

V

D

)

×

COMP

,

ZCT

R

CS

1

I

SC

,

PK t

OFF

,

×

R

S

MIN

×

×

D f

SW

2

V

×

IN

×

f

SW

D

×

L



(36)

If the load current exceeds I

LOAD,MAX

, the output voltage drops below the desired voltage.

Pulse-Skipping Modulation

The ADP1621 features circuitry that improves the converter efficiency and minimizes power consumption with no load or very light loads. When the COMP voltage drops below V

COMP,ZCT

(typically 1.0 V), which can occur at sufficiently light loads, the

MOSFET is powered off until the FB voltage drops below 1.215 V.

Then, the error amplifier drives the COMP voltage higher, and the converter resumes switching when the COMP voltage rises above the V

COMP,ZCT

voltage. While the MOSFET is powered off, the output capacitor supplies current to the load.

With light loads, the COMP voltage hovers around 1.0 V, and short periods of switching are followed by long periods of the

MOSFET being powered off. This pulse-skipping modulation operation improves converter efficiency by reducing the number of switching cycles and therefore reducing the gate drive current and the switching transition power loss.

LIGHT LOAD OPERATION

Discontinuous Conduction Mode

With light loads, the average inductor current is small, and, depending on the converter design, the instantaneous inductor current may reach 0 during the time when the MOSFET is off.

This mode of operation is termed discontinuous conduction mode. The condition for entering discontinuous conduction mode in a boost converter is

I

LOAD

<

V

IN

2

×

×

D

L

×

×

(

1

D

)

f

SW

(37)

Given the minimum on time of the ADP1621 , pulse-skipping modulation is also a requirement to maintain output voltage regulation with light loads. During the short switching periods of pulse-skipping modulation, the MOSFET is turned on for the minimum on time each cycle, storing just enough energy in the inductor to charge the output capacitor. During the long period when the MOSFET is off, no current flows through the inductor, and the light load current is supplied by the output capacitor.

When the instantaneous inductor current reaches 0 during the cycle, the inductor ceases to be a current source, and ringing can be observed in the waveforms of the MOSFET drain voltage and the inductor current. The frequency of the ringing is the

RECOMMENDED COMPONENT MANUFACTURERS

Table 5. Recommended Component Manufacturers

Vendor

AVX Corporation

Central Semiconductor Corp.

Coilcraft, Inc.

Diodes, Inc.

International Rectifier

Murata Manufacturing Co., Ltd.

ON Semiconductor

Rubycon Corporation

Sanyo

Sumida

Taiyo Yuden, Inc.

Toko America, Inc.

United Chemi-Con, Inc.

Vishay Siliconix

Components

Capacitors

Diodes

Inductors

Diodes

Diodes, MOSFETs

Capacitors, inductors

Diodes, MOSFETs

Capacitors

Capacitors

Inductors

Capacitors, inductors

Inductors

Capacitors

Diodes, MOSFETs, resistors, capacitors

Rev. D | Page 19 of 32

ADP1621

LAYOUT CONSIDERATIONS

Layout is important for all switching regulators, but is particularly important for regulators with high switching frequencies.

To achieve high efficiency, good regulation, and stability, a welldesigned printed circuit board layout is required. A sample PCB

layout for the standard boost converter circuit shown in Figure 33

is given in Figure 32.

Follow these guidelines when designing printed circuit boards:

 Keep the low ESR bypass input capacitor of 0.1 μF or higher close to IN/PIN and GND.

 Keep the high current path from Bulk Input Capacitor C1 through Inductor L1 and MOSFET M1 to PGND as short as possible.

 Keep the high current path from Bulk Input Capacitor C1 through Inductor L1, Diode D1, and Output Capacitor C

OUT to PGND as short as possible. Place C

OUT

as close to PGND as possible to reduce ground bouncing.

 Keep high current traces as short and wide as possible to minimize parasitic series inductance, which causes spiking and electromagnetic interference (EMI).

 To minimize switching noise, place the drain of the power

MOSFET very close to the inductor, and connect the source of the MOSFET (or the bottom side of the sense resistor) directly to the power GND plane. Use wide copper traces on the drain and on the source of the MOSFET to minimize parasitic inductance and resistance. Parasitic inductance can lead to excessive ringing during switching transitions, and parasitic resistance reduces the converter efficiency.

Make sure that the MOSFET selected is capable of handling the total power loss (conduction plus transition losses) in the application circuit.

V

IN

L1

C1

GND

D1

Data Sheet

 Avoid routing high impedance traces near any node connected to the switch node (the MOSFET drain) or near

Inductor L1 to prevent radiated switching-noise injection.

 Add an extra copper plane at the connection of the MOSFET drain and the anode of the diode to help dissipate the heat generated by losses in those components.

 Avoid ground loops by having one central ground node on the

PCB. If this is impractical, place the power ground with high current levels physically closer to the PCB ground terminal. Place the analog, low current-level ground farther from the PCB ground terminal.

 Minimize the length of the PCB trace between the GATE pin and the MOSFET gate. The parasitic inductance in this

PCB trace can give rise to excessive voltage ringing at the

MOSFET gate and drain, as well as the regulator output. It is recommended to add 5 Ω of resistance for every inch of

PCB trace. This helps to reduce the overshoot and ringing at the drain and the output. However, this added resistance increases the rise and fall times of the MOSFET; thus, the switching loss in the MOSFET is increased.

 Place the feedback resistors as close to FB as possible to prevent high frequency switching-noise injection.

 Place the top of the upper feedback resistor, R1, as close as possible to the top of C

OUT

for optimum output voltage sensing.

 If a current-sense resistor is connected between the source of the MOSFET and PGND, ensure that the capacitance from

CS to PGND is minimized.

 Place the compensation components as close as possible to COMP.

M1

GND

GATE

C

OUT1

C

OUT2

C

OUT3

V

OUT

ADP1621

SDSN

R

FREQ

REMOTE OUTPUT

SENSING

VIAS TO GND PLANE

VIAS TO 2ND LAYER

Figure 32. PCB Layout of the Circuit Shown in Figure 33 (2-layer PCB)

Rev. D | Page 20 of 32

Data Sheet

EFFICIENCY CONSIDERATIONS

The efficiency, η, of a dc-to-dc converter is given by

η

=

P

OUT

P

IN

×

100 % where:

(38)

P

OUT

is the output power.

P

IN

is the input power to the converter. While switching regulators are ideally lossless converters of power, the nonideal characteristics of regulator components degrade the efficiency of the regulator.

The primary sources of power dissipation in the regulator include

• The power dissipation in the external power MOSFET due to conduction and switching losses.

P

MOSFET

=

P

C

+

P

SW

(39)

=

I

1

LOAD

D

(

V

OUT

×

D

×

R

DSON

+

V

D

)

×

I

LOAD

1

D

2

×

( 1

+

K

)

+

×

(

t

R

+

t

F

)

×

f

SW

• The power dissipation in the external current-sense resistor if lossless current sensing is not used.

P

CS

=

I

1

LOAD

D

2

×

D

×

R

CS

• The power dissipation in the external diode.

P

DIODE

=

V

D

×

I

LOAD

(40)

(41)

ADP1621

• The power dissipation in the winding resistance of the power stage inductor.

P

L

,

W

=

I

1

LOAD

D

2

×

R

W

(42)

• The supply current to the

ADP1621 IC, which includes the quiescent current and the gate driver charging current. The power dissipation due to gate charging loss is approximated by

P

G

=

V

PIN

×

Q

G

×

f

SW

(43) where:

P

G

is the gate charging power loss.

V

PIN

is the voltage at the PIN pin.

Q

G

is the MOSFET total gate charge.

f

SW

is the converter switching frequency. Therefore, the total power dissipation in the IC itself is given by

P

IC

=

(

V

=

PIN

P

G

×

+

Q

(

G

V

IN

×

×

f

SW

I

)

Q

+

)

(

V

IN

×

I

Q

)

(44) where:

P

IC

is the total power dissipated in the IC.

I

Q

is the quiescent current.

V

IN

is the voltage at the IN pin.

The secondary sources of power dissipation in the regulator include

• The power dissipation in the ESR of the input and output capacitors.

• Inductor core losses due to hysteresis and eddy currents.

Rev. D | Page 21 of 32

ADP1621

EXAMPLES OF APPLICATION CIRCUITS

STANDARD BOOST CONVERTER—DESIGN

EXAMPLE

The example covered here is for the ADP1621 configured as a

standard boost converter, as shown in Figure 33, where lossless

current sensing is employed. The design parameters are V

3.3 V, V

OUT

= 5 V, and a maximum load current of 1 A. to be R1 = 35.7 kΩ and R2 = 11.5 kΩ from Equation 4.

IN

=

To begin this design, a switching frequency of 600 kHz is chosen

(by setting R

FREQ

to 32 kΩ, see Figure 30) so that a small inductor

and small output capacitors can be used. The duty cycle is calculated from Equation 1 to be 0.4, given a forward-voltage drop of

0.5 V for the Schottky diode. The feedback resistors are calculated

Assuming that the inductor ripple is 30% of 1/(1 − D) times the maximum load current, the inductor size is calculated to be about 4.4 µH, according to Equation 9. The small, magnetically shielded 4.7 µH Toko FDV0630-4R7M inductor is selected.

Because ceramic capacitors have very low ESR (a few milliohms), a 47 µF/6.3 V Murata GRM31CR60J476M ceramic capacitor is chosen for the input capacitor. The output voltage ripple for a given C

OUT

, ESR, and ESL can be found by solving Equation 12.

By choosing an output voltage ripple equal to 1% of the output voltage, Equation 12 yields that the minimum C

OUT

required is

100 µF and the maximum ESR required is 25 mΩ. Other combinations of capacitance and ESR are possible by choosing a much larger C

OUT

and a larger ESR. In this case, a small 1 µF ceramic capacitor and two 150 µF Sanyo POSCAP™ capacitors are selected. The low ESR ceramic capacitor helps to suppress the high frequency overshoot at the output. POSCAP has low

ESR and high capacitance in a relatively small package. Ceramic capacitors can also be used. Generally, bigger ceramic capacitors are more expensive.

Data Sheet

The next step is to choose a Schottky diode. The average and rms diode currents are calculated to be 1.0 A and 1.3 A, respectively, using Equations 14 and 15. A Vishay SSA33L

Schottky diode meets the current and thermal requirements and is an excellent choice.

The power MOSFET must be chosen based on threshold voltage

(V

T

), on resistance (R

DSON

), maximum voltage and current ratings, and gate charge. The rms current through the MOSFET is given by Equation 18 as 1.1 A. The Vishay Si7882DP is a 20 V n-channel power MOSFET that meets the current and thermal requirements.

It comes in a PowerPAK® package and offers low R

DSON

and gate charge. At V

GS

= 2.5 V, the on resistance, R

DSON

, is 8 mΩ.

The loop-compensation components are chosen to be R

COMP

=

9.1 kΩ and C

COMP

= 1.7 nF from Equations 30 and 31, respectively.

A roll-off capacitor of C2 = 120 pF is also added. The slopecompensation resistor is set to be R

S

= 80 Ω from Equation 34.

Lastly, given the chosen components, the peak inductor current as set by the current limit circuitry is given by Equation 35 as

I

L,PK

= 12 A. Thus, the maximum load current, assuming CCM operation, is given by Equation 36 as I

LOAD,MAX

= 8 A, which is safely above the 1.0 A load current requirement for this design example. Note that the current limit is a strong function of R

CS

, which can vary device to device and with temperature. In addition, note that R

CS

can be implemented with an external current-sense resistor or with the R

DSON

of a MOSFET. Variations in R

CS

and the other parameters in Equations 35 and 36 must be taken into account if precise current limiting is necessary. Due to the parasitic resistance of PCB traces, R

S

might need to be adjusted on the actual circuit board to achieve the desired current limit. Keep in mind that R

S

must be less than 1.6 kΩ. Using a MOSFET with a different R

DSON

or adjusting R

CS

can also set the current limit to the desired level.

V

IN

= 3.3V

L1

4.7µH

D1

C3

1µF

10V

C2

120pF

C4

0.1µF

10V

PIN IN

R

COMP

9.09kΩ

C

COMP

1.8nF

R

FREQ

31.6kΩ

1%

ADP1621

CS

SDSN

GATE

COMP

PGND

FREQ

GND

FB

R

S

80Ω

R1

35.7kΩ

1%

M1

R2

11.5kΩ

1%

C1

47µF

6.3V

AGND f

OSC

= 600kHz

C1 = MURATA GRM31CR60J476M

C

OUT3

= SANYO POSCAP 6TPE150M

L1 = TOKO FDV0630-4R7M

M1 = VISHAY Si7882DP

D1 = VISHAY SSA33L

Figure 33. Typical Boost Converter Application Circuit

C

OUT1

1µF

10V

C

OUT2

10µF

10V

V

OUT

= 5V

1A

C

OUT3

150µF

6.3V

×2

Rev. D | Page 22 of 32

Data Sheet

BOOTSTRAPPED BOOST CONVERTER

The inputs of the ADP1621 can be driven from the step-up converter output voltage to improve efficiency for low input voltages. For low input voltages, bootstrapped operation improves efficiency with heavy loads by increasing the available gate drive voltage, thus reducing the on resistance of the MOSFET. However, because the internal circuitry is driven from IN, the ADP1621 quiescent current and gate drive current supplied from the input increases due to the step-up ratio and the conversion efficiency loss.

The circuit shown in Figure 1 shows a bootstrapped boost con-

verter, where V

IN

= 3.3 V and V

OUT

= 5 V. To ensure that the circuit starts, make sure that the input voltage minus the forward-voltage drop of the diode is greater than the UVLO voltage and the gate threshold voltage of the MOFSET. In this example, the MOSFET has a gate threshold voltage of 2.5 V. The regulator shown in

Figure 1 is very similar to that shown in Figure 33, which is a

standard boost without bootstrapping. Because the same MOSFET and inductor are used in both circuits and the input and output conditions are the same, the compensation components remain unchanged.

Figure 34 shows a bootstrapped application circuit for output

voltages greater than 5.5 V. In this case, the output is 12 V.

Notice that a resistor, R3, of 700 Ω is placed between V

OUT

and the IN and PIN pins to limit the input currents because the IN and PIN pins are regulated to 5.5 V. A diode, D2, is placed between

V

IN

and the IN/PIN pins to supply the necessary quiescent current to start the ADP1621 . After the ADP1621 starts and the output voltage reaches 12 V, the quiescent current stops flowing through

D2 and is supplied by the output. Keep in mind that the dynamic

ADP1621

supply current to PIN increases as the switching frequency increases because more gate drive is needed for a higher switching frequency. Therefore, R3 needs to be set appropriately.

The PIN supply current can be approximated by

I

PIN

where:

= f

SW

× Q

G

(45)

I

PIN

is the PIN supply current.

f

SW

is the switching frequency.

Q

G

is the gate charge of a particular MOSFET.

An alternative implementation to Figure 34 is shown in Figure 35,

where an NPN transistor is used to supply the necessary current to the input PIN at various loads, but the gate drive voltage is limited to approximately 4.8 V (one diode drop below the voltage at IN). Signal Diodes D2 and D3 help to provide the necessary quiescent current to start the ADP1621 . After the ADP1621 starts, the current stops flowing through these two diodes because the voltages at PIN and IN are approximately 4.8 V and 5.5 V, respectively. One advantage of this technique is that Q1 provides enough current to the gate driver at any switching frequency with a wide range of MOSFETs that have different gate charge specifications.

Notice that the output capacitor, C

OUT2

in Figure 34 and Figure 35,

is a large aluminum electrolytic capacitor, both in physical size and capacitance. Such capacitors are very cheap relative to ceramic capacitors (such as Sanyo POSCAP) or aluminum polymer capacitors. The ADP1621 can work with a wide range of capacitor types.

Rev. D | Page 23 of 32

ADP1621

C3

1µF

10V

C2

220pF

C4

0.1µF

10V

R

COMP

51.5kΩ

C

COMP

330pF

D2

R3

700Ω

V

IN

= 3.3V

L1

10µH

D1

PIN IN

CS

ADP1621

SDSN

GATE

COMP

PGND

R

FREQ

31.6kΩ

1%

FREQ

GND

FB

R

S

200Ω

M1

R1

88.7kΩ

1%

R2

10kΩ

1%

C1

47µF

6.3V

V

OUT

= 12V

1A

C

OUT1

10µF

16V

×2

C

OUT2

330µF

25V

×2

AGND f

OSC

C1 = MURATA GRM31CR60J476M

C

= 600kHz

OUT2

= RUBYCON 25ZL330M8x16

L1 = COILCRAFT MSS1260-103ML

M1 = IRF7470

D1 = VISHAY SSC53L

D2 = SIGNAL DIODE

Figure 34. Bootstrapped Application Circuit for V

OUT

> 5.5 V

V

IN

= 3.3V

D3 D2

L1

10µH

Q1

R3

1.5kΩ

C3

1µF

10V

C2

220pF

C4

0.1µF

10V

R

COMP

51.5kΩ

C

COMP

330pF

PIN IN

ADP1621

CS

SDSN

GATE

COMP

PGND

R

FREQ

31.6kΩ

1%

FREQ

GND

FB

R

S

200Ω

M1

D1

R1

88.7kΩ

1%

R2

10kΩ

1%

C1

47µF

6.3V

AGND f

OSC

= 600kHz

C1 = MURATA GRM31CR60J476M

C

OUT2

= RUBYCON 25ZL330M8x16

L1 = COILCRAFT MSS1260-103ML

Q1 = SIGNAL NPN TRANSISTOR

M1 = IRF7470

D1 = VISHAY SSC53L

D2, D3 = SIGNAL DIODE

Figure 35. Bootstrapped Application Circuit for V

OUT

> 5.5 V

V

OUT

= 12V

1A

C

OUT1

10µF

16V

×2

C

OUT2

330µF

25V

×2

Data Sheet

Rev. D | Page 24 of 32

Data Sheet

Low Input and High Output Boost Converter

Figure 36 shows a typical application boost converter circuit

that operates at a switching frequency of 200 kHz with V

IN

= 5 V and V

OUT

= 30 V with a 1 A load. The duty cycle for this circuit is about 83%. A higher switching frequency can be selected, but the switching power loss in the MOSFET increases and a bigger

MOSFET is needed. For switch-node voltages greater than 30 V, a sense resistor, R

CS

, is needed because the absolute maximum voltage at CS is 33 V.

High Input Voltage Boost Converter Circuit

Input voltages higher than 5.5 V are possible with the addition

of a resistor and an NPN transistor, as shown in Figure 37, or just

ADP1621

with a single resistor, as shown in Figure 38. When there is a

wide input voltage range, it is sometimes desirable to use the

pass NPN transistor, as shown in Figure 37. If the input voltage

range is narrow, a single resistor connecting to the IN and PIN

pins is sufficient, as shown in Figure 38. In Figure 37, Resistor R3

limits the current going into IN, and there is power loss in this resistor. The voltages at IN and PIN are both clamped to about

5.5 V, which can rise to as high as 5.9 V when the shunt current

is 30 mA. Refer to Figure 9 for the I-V characteristics of the shunt

regulators. Ensure that Resistor R3 is physically large enough to handle the power dissipation. For switch-node voltages higher than 30 V, a current-sense resistor is needed and the CS pin senses the voltage across the sense resistor.

V

IN

= 5V

C3

1µF

10V

L1

7.8µH

D1

C4

0.1µF

10V

R

COMP

1.6MΩ

C

COMP

20pF

IN PIN

R1

115kΩ

1%

FB

ADP1621

SDSN

GATE

COMP

CS

R

FREQ

100kΩ

1%

FREQ

PGND

GND

M1

R2

4.87kΩ

1%

R

S

909Ω

R

3mΩ

C

OUT1

1µF

100V

C2

120pF

C1

47µF

6.3V

×2

AGND f

OSC

= 200kHz

C1 = MURATA GRM31CR60J476M

C

OUT1

C

OUT2

C

OUT3

= MURATA GRM31CR72A10

= MURATA GRM55ER71H475K

= RUBYCON 50ZL330M10x23

M1 = VISHAY SUD50N06-07L

D1 = IRF 15TQ060

L1 = COILCRAFT DO501DH-782ML

Figure 36. Low Input, High Output Boost Converter

V

IN

= 8V TO 15V

R3

700Ω

L1

8.2µH

C4

0.1µF

10V

Q1

C3

1µF

10V

D1

IN PIN

R1

115kΩ

1%

C

OUT1

1µF

100V

ADP1621

FB

SDSN

GATE

COMP

CS

M1

R2

4.87kΩ

1%

C2

120pF

R

COMP

2MΩ

C

COMP

220pF

R

FREQ

34.8kΩ

FREQ

PGND

GND

R

S

402Ω

R

CS

3mΩ

C1

22µF

16V

×2

AGND f

OSC

= 560kHz

C1 = MURATA GRM32ER61C226K

C

OUT1

C

OUT2

C

OUT3

= MURATA GRM31CR72A105K

= MURATA GRM55ER71H475K

= RUBYCON 50ZL220M10x23

M1 = IRF7470

Q1 = SIGNAL NPN TRANSISTOR

D1 = MBRB7H50

L1 = COILCRAFT MSS1260-822ML

Figure 37. High Input Voltage and High Output Voltage Converter

C

OUT2

4.7µF

50V

V

OUT

= 30V

1A

C

OUT3

330µF

50V

×2

C

OUT2

4.7µF

50V

V

OUT

= 30V

1A

C

OUT3

330µF

50V

×2

Rev. D | Page 25 of 32

ADP1621

V

IN

= 12V

C3

1µF

10V

R3

649Ω

L1

15µH

D1

C4

0.1µF

10V

R

COMP

2MΩ

C

COMP

18pF

IN PIN

R1

324kΩ

1%

ADP1621

FB

SDSN

GATE

COMP

CS

R

FREQ

34.8Ω

FREQ

PGND

GND

M1

R2

10.2kΩ

1%

R

S

442Ω

R

CS

0.01Ω

C

OUT1

1µF

100V

C2

120pF

C1

22µF

16V

×2

AGND f

OSC

= 560kHz

C1 = MURATA GRM32ER61C226K

C

OUT1

C

OUT2

C

OUT3

= MURATA GRM31CR72A105K

= MURATA GRM55ER71H475K

= RUBYCON 63ZL220M10x23

M1 = VISHAY Si7478DP

D1 = MBRB7H50

L1 = COILCRAFT MSS1278-153ML

Figure 38. High Input Voltage and High Output Voltage Converter

C

OUT2

4.7µF

50V

V

OUT

= 40V

1A

C

OUT3

220µF

63V

×2

Data Sheet

Rev. D | Page 26 of 32

Data Sheet

SEPIC CONVERTER CIRCUIT

A single-ended primary inductance converter (SEPIC) topology

is shown in Figure 39. This topology is useful for an unregulated

input voltage, where the regulated output voltage falls within the input voltage range.

The input and output are dc-isolated by a coupling capacitor,

C5. L1 and L2 are coupled inductors with a 1:1 turn ratio, which saves space on the PCB. In steady state, the average voltage across

C5 is the input voltage. When the MOSFET turns on and the diode turns off, the input voltage provides energy to L1, and C5 provides energy to L2. The output capacitor, C

OUT

, supplies the

C3

1µF

10V

C2

33pF

C

OUT1

1µF

10V

C1

22µF

10V

×2

V

OUT

= 3.3V

2A

C

OUT2

150µF

6.3V

×3

ADP1621

load current during this time. When the MOSFET turns off and the diode turns on, the energy in L1 and L2 is released to charge the output capacitor, C

OUT

, and the coupling capacitor, C5, as well as to supply current to the load.

LOW VOLTAGE POWER-INPUT CIRCUIT

The ADP1621 can be configured to run from a low voltage

(as low as 1 V) power input. The power source generally needs

to have a high current capability, such as a fuel cell. Figure 40

illustrates such an application, where the voltage of the power input is 1 V and the voltage of the chip supply to the IN and

PIN pins is provided by an auxiliary low power source.

V

IN

= 3V TO 5V

L2

2.4µH

D1

C4

0.1µF

10V

L1

2.4µH

PIN IN

R

COMP

26kΩ

C

COMP

1.2nF

CS

ADP1621

SDSN

GATE

COMP

PGND

R

65kΩ

FREQ

GND

FB

R

80Ω

M1

C5

10µF

10V

X5R

R1

17.4kΩ

1%

R2

10kΩ

1%

AGND f

OSC

= 325kHz

C1 = MURATA GRM332ER61A226K

C

OUT2

= SANYO POSCAP 6TPE150MI

C5 = MURATA GRM21BR61A106K

M1 = VISHAY Si7882DP

D1 = VISHAY SSC53L

L1, L2 = COUPLED INDUCTORS, 1:1 RATIO, BH ELECTRONICS BH510-1006

Figure 39. A SEPIC DC-to-DC Converter

V

IN

= 1V

C3

1µF

10V

V

CC

= 2.9V TO 5V

L1

2.2µH

D1

C4

0.1µF

10V

PIN IN

R

COMP

9.4kΩ

C

COMP

56nF

CS

ADP1621

SDSN

GATE

COMP

PGND

R

FREQ

31.6kΩ

1%

FREQ

GND

FB

R

S

249Ω

R1

35.7kΩ

1%

M1

R2

1

1.5kΩ

1%

C

OUT1

1µF

10V

C

OUT2

10µF

6.3V

V

OUT

= 5V

1A

C

OUT3

150µF

6.3V

×2

C2

260pF

C1

100µF

X5R

6.3V

AGND f

OSC

= 600kHz

C1 = MURATA GRM32ER60J107ME20

C

OUT2

C

OUT3

= MURATA GRM21BR60J106K

= SANYO POSCAP 6TPE150MI

M1 = VISHAY Si7882DP

D1 = MBRD835L

L1 = TOKO FDV0630-2R2M

Figure 40. Low Voltage Power-Input Application Circuit

Rev. D | Page 27 of 32

ADP1621

LED DRIVER APPLICATION CIRCUITS

The ADP1621 can be used as an LED driver. Two LED application

circuits are shown in Figure 41 and Figure 42, where each circuit

is driving 20 white LEDs in series. Each white LED has a typical current of 150 mA at a typical forward voltage of 4.0 V, with a maximum voltage of 4.5 V over the temperature range of −40°C to +125°C.

Two methods for dimming the brightness of the LEDs are

shown in Figure 41 and Figure 42. In Figure 41, a PWM signal

is fed to the SDSN pin to turn the ADP1621 controller on and off. As a result, the LED current is turned on and off, and the average LED current is dependent on the PWM duty cycle. The advantage of this method is that no current flows through the

LEDs during the PWM off cycle. In addition, when the ADP1621 is on, the forward current through the LEDs is constant, which guarantees constant color emission across the entire dimming range. Because the soft start period is fixed at 2048 oscillator cycles, the PWM frequency range is limited.

As shown in Figure 41, because the natural switching frequency

chosen is 400 kHz, the useful PWM frequency range is 90 Hz to

195 Hz. However, when driving fewer LEDs, the ADP1621 can be set to run at a faster frequency, increasing the maximum

PWM frequency. The PWM duty cycle can be between 5% and

95%. A higher PWM duty cycle produces a higher average LED current.

Data Sheet

Another method for driving the LEDs is shown in Figure 42,

where the PWM signal is filtered by an RC low-pass filter and is fed to the FB node. The effective FB voltage at the bottom of the

LED string is modulated in an analog manner by the PWM duty cycle. Thus, the average current through the LEDs is

modulated accordingly. Unlike the case depicted in Figure 41, a

higher duty cycle produces a lower average LED current using

the filtered PWM scheme in Figure 42. The advantage of this

circuit is that the PWM frequency can be in the range between

90 Hz and 100 kHz, and the duty cycle can be between 5% and

95%. The disadvantage of this method is that the forward current through the LEDs is directly modified to control the brightness of the LEDs. Because the wavelength of the light emitted from an LED is a weak function of its forward current, perfect color purity across the entire dimming range cannot be guaranteed.

If PCB space is a constraint, smaller inductors can be selected

for the circuits shown in Figure 41 and Figure 42. For example,

a 4.7 µH inductor can be used, and a 200 kHz switching frequency can be selected. However, with this small inductor, the system operates in DCM, which is slightly less efficient than operating in CCM.

Rev. D | Page 28 of 32

Data Sheet

V

IN

= 10V TO 16V

C3

0.1µF

PIN

R

B

800Ω

IN

C4

0.1µF

L1

33µH

D1

100V

R

S

800Ω

150mA

M1

100V

20

LEDS

V

OUT

C

OUT

1µF

100V

×3

C2

18pF

PWM

R

COMP

101kΩ

C

COMP

390nF

GATE

ADP1621

SDSN

CS

COMP

FB

R

FREQ

50kΩ

1%

FREQ

PGND

GND

R

CS

3mΩ

R1

8Ω

1/4W

C1

2.2µF

25V

C2

10pF

AGND f

OSC

= 400kHz

C1 = MURATA GRM31MR71E225K

C

OUT

= MURATA GRM31CR72A105K

L1 = COILCRAFT MSS1038-333NL

M1 = VISHAY Si4482DY

D1 = IRF 10MQ100

Figure 41. 20-Series LED Driver with PWM at SDSN

V

IN

= 10V TO 16V

C3

0.1µF

R

B

800Ω

C4

0.1µF

L1

33µH

D1

100V

V

OUT

PIN IN

R5

18kΩ

R

COMP

101kΩ

C

COMP

390nF

GATE

ADP1621

SDSN

COMP

CS

FB

R

FREQ

50kΩ

1%

FREQ

PGND

GND

R

S

800Ω

150mA

M1

100V

20

LEDS

R2

10kΩ

C

OUT

1µF

100V

×3

R3

22.9kΩ

R4

10kΩ

R

CS

3m

R1

8Ω

1/4W

C5

0.1µF

6.3V

PWM =

0V TO 4V

C1

2.2µF

25V

AGND f

OSC

= 400kHz

C1 = MURATA GRM31MR71E225K

C

OUT

= MURATA GRM31CR72A105K

L1 = COILCRAFT MSS1038-333NL

M1 = VISHAY Si4482DY

D1 = IRF 10MQ100

Figure 42. 20-Series LED Driver with Filtered PWM

Rev. D | Page 29 of 32

ADP1621

ADP1621

RELATED DEVICES

Data Sheet

Table 6. Related Devices

Device

Number Description

ADP1612

ADP1613

ADP1614

Comments

Current-mode PWM step-up controller 1.4 A, internal FET R

DSON

is 130 m Ω nominal, V

IN

= 1.8 V to 5.5 V, V

OUTMAX

is 20 V

Current-mode PWM step-up controller 2.0 A, internal FET R

DSON

is 130 m Ω nominal, V

IN

= 2.5 V to 5.5 V, V

OUTMAX

is 20 V

Current-mode PWM step-up controller 4.0 A, internal FET R

DSON

is 50 m Ω nominal, V

IN

= 2.5 V to 5.5 V, V

OUTMAX

is 20 V

Rev. D | Page 30 of 32

Data Sheet

OUTLINE DIMENSIONS

3.10

3.00

2.90

ORDERING GUIDE

Model 1

ADP1621ARMZ-R7

ADP1621-EVAL

1 Z = RoHS Compliant Part.

Temperature Range

−40°C to +125°C

3.10

3.00

2.90

10

1

6 5.15

4.90

4.65

5

PIN 1

IDENTIFIER

0.50 BSC

0.95

0.85

0.75

0.15

0.05

COPLANARITY

0.10

0.30

0.15

1.10 MAX

15° MAX

0.23

0.13

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 43. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

0.70

0.55

0.40

Package Description

10-Lead Mini Small Outline Package [MSOP]

Evaluation Board

ADP1621

Package

Option

RM-10

Ordering

Quantity Branding

1,000

1

L3M

Rev. D | Page 31 of 32

ADP1621

NOTES

©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D06090-0-2/16(D)

Rev. D | Page 32 of 32

Data Sheet

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