datasheet for VL31B5263A

datasheet for VL31B5263A

Product Specifications

PART NO.:

VL31B5263A-K0/K9/F8/E7S REV: 1.0

General Information

4GB 512Mx72 DDR3 SDRAM ECC UNBUFFERED DIMM 240-PIN

Description

The VL31B5263A is a 512Mx72 DDR3 SDRAM high density UDIMM. This memory module is dual rank, consists of eighteen CMOS 256Mx8 bits with 8 banks DDR3 synchronous DRAMs in BGA packages, and a 2K EEPROM in an 8pin MLF package. This module is a 240-pin dual in-line memory module and is intended for mounting into an edge connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR3 SDRAM.

240-pin, unbuffered dual in-line memory module (UDIMM)

Supports ECC error detection and correction

Fast data transfer rates: PC3-12800, PC3-10600, PC3-8500, PC3-6400

VDD = VDDQ = 1.5V +/-0.075V

JEDEC standard 1.5V +/-0.075V I/O (SSTL_15 )

VDDSPD = 3.0V to 3.6V

Eight internal component banks for concurrent operation

8-bit

Bi-directional differential data-strobe

Nominal and dynamic on-die termination (ODT)

ZQ calibration support

Programmable CAS# latency:

11 (DDR3-1600), 9 (DDR3-1333), 7 (DDR3-1066), 6 (DDR3-800)

Programmable burst; length (8)

Average refresh period 7.8 us

Asynchronous

Fly-by

On board terminated command, address, and control bus

Serial presence detect (SPD) with EEPROM

Gold edge contacts

Lead-free, RoHS compliant

PCB:

Operating temperature (T

OPER

): - Commercial (0 o

- Industrial (-40 o

C <= Tc <= 95

C <= Tc <= 95 o o

C)

C)

Notes: Double refresh rate is required when 85 o

C < T

OPER

<= 95 o

C.

T

OPER

is DRAM case temperature (Tc).

Pin Name

A12/BC#

DQS0#~DQS8#

CB0~CB7

CK0, CK0#, CK1, CK1#

ODT0, ODT1

CKE0, CKE1

CS0#, CS1#

RAS#

CAS#

Data Check Bits I/O

Clock Input

On-die Termination Control

Clock Enables

Chip Selects

Row Address Strobes

Column Address Strobes

RESET#

Function

Address Input/ Burst Chop

Data Strobes Complement

Register and SDRAM Control

VSS Ground

Order Information:

VL31B5263A K0 S X -

X

OPERATING TEMPERATURE

None: Commercial

S1: Industrial screening

DRAM DIE (Option)

DRAM MANUFACTURER

S - SAMSUNG

MODULE SPEED

K0: PC3-12800 @ CL11

K9: PC3-10600 @ CL9

F8: PC3-8500 @ CL7

E7: PC3-6400 @ CL6

VL: Lead-free/RoHS

DRAM component: Samsung K4B2G0846D-HCK0 (Lead-free/RoHS)

SDA

SCL

VREFCA

VREFDQ

VDDSPD

SPD Data Input/Output

SPD Clock Input

Reference Voltage for CA

Reference Voltage for DQ

SPD Voltage Supply

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Product Specifications

PART NO.:

VL31B5263A-K0/K9/F8/E7S REV: 1.0

240-PIN DDR3 UDIMM FRONT SIDE

Pin Configuration

240-PIN DDR3 UDIMM BACK SIDE

Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name

2

3

4

VSS 32

DQ0

DQ1

33

34

VSS

DQS3#

DQS3

62 VSS 122 DQ4 152 DM3 182 VDD 212 DM5

123 DQ5 153 NC 183 VDD 213 NC 63 CK1

64 CK1#

93 DQS5#

94 DQS5 124 VSS

VDD 125

154 VSS 184 CK0 214 VSS

6 DQS0#

7 DQS0

36

37

DQ26

DQ27

66 VDD 96

67 VREFCA 97

DQ42

DQ43

126

127

NC

VSS

156

157

DQ31 186

VSS

VDD

187 EVENT#*

216

217

DQ47

VSS

PAR_IN 128 DQ6 158

9 DQ2 39 CB0 69 VDD 99 DQ48

130 VSS 160 VSS 190 BA1 220 VSS

11 VSS 41 VSS 71 BA0 101 VSS

12 DQ8 42 DQS8# 72 VDD 102 DQS6#

13 DQ9 43 DQS8 73 WE# 103 DQS6

131 DQ12 161 DM8 191 VDD 221 DM6

132 DQ13 162 NC 192 RAS# 222 NC

133 VSS 163 VSS 193 CS0# 223 VSS

15 DQS1#

16 DQS1

45

46

CB2

CB3

75

76

VDD

CS1#

105

106

DQ50

DQ51

135

136

NC

VSS

165

166

CB7

VSS

195 ODT0

196 A13

225

226

DQ55

VSS

18 DQ10 48 VTT 78 VDD 108 DQ56

19 DQ11 49 VTT 79 NC 109 DQ57

20 VSS 50 CKE0 80 VSS 110 VSS

21 DQ16 51 VDD 81 DQ32 111 DQS7#

22 DQ17 52 BA2 82 DQ33 112 DQS7

83 VSS 113 VSS

24 DQS2# 54 VDD 84 DQS4# 114 DQ58

25 DQS2 55 A11 85 DQS4 115 DQ59

141

142

DQ21

VSS

171 A15 *

172 A14

201 DQ37 231 NC

202 VSS 232 VSS

143 DM2 173 VDD 203 DM4 233 DQ62

144 NC 174 A12/ BC# 204 NC 234 DQ63

145 VSS 175 A9 205 VSS 235 VSS

*: These pins are not used in this module.

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PART NO.:

Function Block Diagram

Product Specifications

VL31B5263A-K0/K9/F8/E7S REV: 1.0

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

Vss

DQS2

DQS2#

DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

Vss

DQS3

DQS3#

DM3

CS1#

CS0#

DQS0

DQS0#

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Vss

DQS1

DQS1#

DM1

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

Vss

DQS8

DQS8#

DM8

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D0

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS

D9

DQS#

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D1

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D10

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D2

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D11

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D3

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D12

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D8

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D17

ZQ

Vss

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

Vss

DQS7

DQS7#

DM7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

Vss

DQS6

DQS6#

DM6

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

Vss

DQS4

DQS4#

DM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

Vss

DQS5

DQS5#

DM5

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D4

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D13

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS

D5

DQS# DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D14

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS

D6

DQS# DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D15

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS

D7

DQS# DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D16

ZQ

Vss

Command, address, control, and clock line terminations

A0-A14, BA0-BA2

RAS#, CAS#, WE#,

CS0#, CKE0, ODT0

CS1#, CKE1, ODT1

CK0, CK1

CK0#, CK1#

DDR3

SDRAM

DDR3

SDRAM

39 ohm +/-5%

VTT

36 ohm +/-5%

0.1uF

VDD

A0-A14

BA0-BA2

RAS#

CAS#

WE#

CKE0

ODT0

CKE1

ODT1

RESET#

CK0

CK0#

3.3pF

A0-A14: SDRAMs D0-D17

BA0-BA2: SDRAMs D0-D17

RAS#: SDRAMs D0-D17

CAS#: SDRAMs D0-D17

WE#: SDRAMs D0-D17

CKE0: SDRAMs D0-D8

ODT0: SDRAMs D0-D8

CKE1: SDRAMs D9-D17

ODT1: SDRAMs D9-D17

RESET#: SDRAMs D0-D17

D0-D8

CK1

CK1#

3.3pF

D9-D17

Serial PD

SCL

Vss

WP

A0 A1 A2

SA0 SA1 SA2

SDA

VDDSPD

VDD

VTT

VREFCA

VREFDQ

VSS

Notes:

1. Unless otherw ise noted, resistor values are 15 ohms +/-5%

2. ZQ resistors are 240 ohms +/-1%

Serial PD

D0-D17

D0-D17

D0-D17

D0-D17

D0-D17

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Product Specifications

PART NO.:

VL31B5263A-K0/K9/F8/E7S

Absolute Maximum Ratings

Symbol Parameter

VDD Voltage on VDD pin relative to VSS

VDDQ Voltage on VDDQ pin relative to VSS

VIN, VOUT Voltage on any pin relative to VSS

-0.4

-0.4

-0.4

-55

IL

Input leakage current; Any input 0V<VIN<VDD;

VREF input 0V<VIN<0.95V;

Other pins not under test = 0V

Address, RAS#,

CAS#, WE#, BA

CS#, CKE, ODT

CK, CK#

-18

-18

REV: 1.0

1.975

1.975

1.975

100

18

18 uA uA

V

V

V

0

C

IOZ

IVREF

Output leakage current;

0V<VOUT<VDDQ; DQs and ODT are disabled

DQ, DQS, DQS#

VREF supply leakage current; VREF = Valid VREF level

-10

-18

10

18 uA uA

DC Operating Conditions

Symbol Parameter Min Max

1.425 1.5 1.575 V 1,2

VDDQ I/O Supply Voltage

VREFDQ (DC) I/O reference voltage DQ bus

1.425

0.49 x VDD

1.5

0.5 x VDD

1.575

0.51 x VDD

V

V

1,2

3,4

VREFCA (DC) Input reference voltage CMD/ADD bus 0.49 x VDD 0.5 x VDD 0.51 x VDD V 3,4

VTT Termination Reference Voltage -0.483 x VDDQ 0.5 x VDDQ +0.517 x VDDQ V

Notes:

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than +/-1% VDD

4. For reference: approximate VDD/2 +/-15mV.

5. VTT termination voltage in excess of stated limit will adversely affect the command and address signals’ voltage margin and will reduce timing margins.

5

Operating Temperature Condition

Symbol Parameter

T

OPER

Operating

Commercial

Industrial

Rating Units Notes

0 to 95

-40 to +95

0

C 1,2

Notes:

1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51-2.

2. At -40 to +85 o

C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when

85 o

C < TOPER <= 95 o

C.

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Product Specifications

PART NO.:

VL31B5263A-K0/K9/F8/E7S REV: 1.0

Input DC Logic Level

All voltages referenced to VSS

Symbol Parameter Min Unit

Command and Address

VIHCA(DC)

VILCA(DC)

Input High (Logic 1) Voltage (

DDR3-800/1066/1333/1600)

Input Low (Logic 0) Voltage ( DDR3-800/1066/1333/1600)

DQ and DM

VREF + 0.100

VSS

VDD

VREF - 0.100

V

V

VIHDQ(DC)

VILDQ(DC)

Input High (Logic 1) Voltage ( DDR3-800/1066/1333/1600)

Input Low (Logic 0) Voltage ( DDR3-800/1066/1333/1600)

VREF + 0.100

VSS

VDD

VREF - 0.100

V

V

Input AC Logic Level

All voltages referenced to VSS

Symbol Parameter Min Unit

Command and Address

VIHCA(AC)

VILCA(AC)

DQ and DM

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage (

(

DDR3-800/1066/1333/1600)

DDR3-800/1066/1333/1600)

VREF + 0.175

-

-

VREF - 0.175

V

V

VIHDQ(AC)

VILDQ(AC)

Input High (Logic 1) Voltage (

DDR3-800/1066)

Input Low (Logic 0) Voltage

(DDR3-800/1066)

VREF + 0.175

-

-

VREF - 0.175

V

V

VIHDQ(AC) VREF + 0.150 - V Input High (Logic 1) Voltage (DDR3-1333/1600)

VILDQ(AC) - VREF - 0.150 V Input Low (Logic 0) Voltage (DDR3-1333/1600)

Input/Output Capacitance

TA=25

0

C, f=100MHz

Parameter Symbol

K0

(DDR3-1600)

K9

(DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Min Max Min Max Min Max Min Max

Unit

Input capacitance (A0~A14, BA0~BA2, RAS#,

CAS#, WE#)

Input capacitance (CKE0, CKE1), (ODT0, ODT1),

(CS0#, CS1#)

CIN1 17.5 27.4 17.5 27.4 17.5 31 17.5 31 pF

CIN2 10.75 15.7 10.75 15.7 10.75 17.5 10.75 17.5 pF

Input capacitance (CK0, CK0#), (CK1, CK1#) CIN3 11.2 16.6 11.2 16.6 11.2 18.4 11.2 18.4 pF

Input/Output capacitance (DQ, DQS, DQS#, CB, DM) CIO 7 8.6 7 9 7 9.4 7 10

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5 pF

Product Specifications

PART NO.:

VL31B5263A-K0/K9/F8/E7S REV: 1.0

IDD Specification

Condition Symbol

(DDR3-1600) (DDR3-1333) (DDR3-1066)

E7

(DDR3-800)

Operating one bank active-precharge current;

tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); tRCD= tRCD(IDD);

CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W.

Precharge power-down current;

All device banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING.

Precharge standby current;

All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is

HIGH; Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING.

Precharge quiet standby current;

All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is

HIGH; Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING.

Active power-down current;

All device banks open; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING.

Active standby current;

All device banks open; tCK= tCK(IDD); tRP= tRP(IDD); tRAS= tRAS MAX(IDD)); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING.

Operating burst read current;

All device banks open; Continuous burst reads; IOUT = 0mA;

BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS

MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data pattern is same as IDD4W.

Operating burst write current;

All device banks open; Continuous burst writes; BL = 8; CL =

CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

Burst refresh current;

tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH; CS# is HIGH between valid commands;

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

Self refresh current;

Unit

IDD5** 2160 2070 1980 1980 mA

CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING.

Operating bank interleave read current;

All bank interleaving reads; IOUT = 0mA; BL = 8; CL =

CL(IDD); AL = tRCD(IDD) - 1*tCK(IDD); tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is

HIGH; CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R.

Notes: IDD specification is based on Samsung D-die components.

*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.

**: Value calculated reflects all module ranks in this operating condition.

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Product Specifications

PART NO.:

VL31B5263A-K0/K9/F8/E7S REV: 1.0

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9

(DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Unit

MIN MAX MIN MAX MIN MAX MIN MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode) tCK(DLL_OFF) 8 - 8 - 8 - 8 - ns

Average Clock Period tCK(avg)

Clock Period

Average high pulse width

Average low pulse width

Clock Period Jitter tCK(abs) tCH(avg) tCL(avg) tJIT(per)

1.25 <1.50 1.5 <1.875 1.875 <2.5 2.5 3.3 tCK(avg)min

+

tJIT(per)min tCK(avg)max

+ tJIT(per)max tCK(avg)min

+ tJIT(per)min tCK(avg)max

+ tJIT(per)max tCK(avg)min

+ tJIT(per)min tCK(avg)max

+ tCK(avg)min

+

tJIT(per)max tJIT(per)min tCK(avg)max

+

tJIT(per)max

0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 ns ns tCK(avg)

0.47

-70

0.53

70

0.47

-80

0.53

80

0.47

-90

0.53

90

0.47

-100

0.53

100 tCK(avg) ps

Clock Period Jitter during DLL locking period tJIT(per, lck)

Cycle to Cycle Period Jitter

Cycle to Cycle Period Jitter during DLL locking period

Cumulative error across 2 cycles tJIT(cc) tJIT(cc, lck) tERR(2per) tERR(3per) Cumulative error across 3 cycles

Cumulative error across 4 cycles tERR(4per) tERR(5per) Cumulative error across 5 cycles

Cumulative error across 6 cycles tERR(6per) tERR(7per) Cumulative error across 7 cycles

Cumulative error across 8 cycles tERR(8per) tERR(9per) Cumulative error across 9 cycles

Cumulative error across 10 cycles tERR(10per) tERR(11per) Cumulative error across 11 cycles

Cumulative error across 12 cycles

Cumulative error across n = 13, 14 ... 49, 50 cycles

Absolute clock HIGH pulse width tERR(12per) tERR(nper) tCH(abs) tCL(abs) Absolute clock Low pulse width

Data Timing

DQS,DQS# to DQ skew, per group, per access

DQ output hold time from DQS, DQS#

DQ low-impedance time from CK, CK#

DQ high-impedance time from CK, CK#

Data setup time to DQS, DQS# referenced to Vih(ac)Vil(ac) levels

Data hold time to DQS, DQS# referenced to

Vih(ac)Vil(ac) levels

DQ and DM Input pulse width for each input tQH tLZ(DQ) tHZ(DQ) tDIPW

-60

-155

-163

-169

-175

-103

-122

-136

-147

-180

-184

-188

0.43

0.43

0.38

-450

-

360

140

120

60

155

163

169

175

103

122

136

147

180

184

188

-

-

-

225

225

-

-70 70 -80 80

160

140

180

160

-177

-186

-193

-200

-118

-140

-155

-168

118

140

155

168

177

186

193

200

-132

-157

-175

-188

-200

-209

-217

-224

-205

-210

205

210

-231

-237

231

237

-215 215 -242 242 tERR(nper)min =(1+ 0.68ln(n))*tJIT(per)min

tERR(nper)max=(1+ 0.68ln(n))*tJIT(per)max

0.43 - 0.43 -

0.43 - 0.43 -

200

209

217

224

132

157

175

188

0.38

-500

-

400

-

250

250

-

0.38

-600

-

490

-

300

300

-

-90

-222

-232

-241

-249

-147

-175

-194

-209

-257

-263

-269

0.43

0.43

0.38

-800

-

600

200

180

90

222

232

241

249

147

175

194

209

257

263

269

-

-

-

400

400

- tCK(avg) ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps tCK(avg) tCK(avg)

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PART NO.:

Product Specifications

VL31B5263A-K0/K9/F8/E7S REV: 1.0

Data Strobe Timing

DQS, DQS# differential READ Postamble

DQS, DQS# output high time

DQS, DQS# output low time

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9

(DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Unit

MIN MAX MIN MAX MIN MAX MIN MAX

tRPST tQSH tQSL

0.3

0.4

0.4

-

-

-

0.3

0.4

0.4

-

-

-

0.3

0.38

0.38

-

-

-

0.3

0.38

0.38

-

-

- tCK tCK(avg) tCK(avg)

DQS, DQS# rising edge output access time from rising CK, CK#

DQS, DQS# low-impedance time

(Referenced from

DQS, DQS# high-impedance time

(Referenced from RL+BL/ 2)

DQS, DQS# differential input low pulse width

DQS, DQS# differential input high pulse width

DQS, DQS# rising edge to CK, CK# rising edge

DQS,DQS# failing edge setup time to CK,

CK# rising edge

DQS,DQS# failing edge hold time to CK,

CK# rising edge

Command and Address Timing

tDQSCK -225 225 -255 255 -300 300 -400 400 ps tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Internal READ Command to PRECHARGE

Command delay

Delay from start of internal write transaction to internal read command tRTP tWTR max

(4tCK,7.5ns) max

(4tCK,7.5ns)

-

- max

(4tCK,7.5ns) max

(4tCK,7.5ns)

-

- max

(4tCK,7.5ns) max

(4tCK,7.5ns)

-

- max

(4tCK,7.5ns) max

(4tCK,7.5ns)

-

-

Mode Register Set command cycle time

Mode Register Set command update delay

CAS# to CAS# command delay

Auto precharge write recovery + precharge time

Multi-Purpose Register Recovery Time

ACTIVE to PRECHARGE command period

ACTIVE to ACTIVE command period for

1KB page size

ACTIVE to ACTIVE command period for

2KB page size

Four activate window for 1KB page size

Four activate window for 2KB page size

Command and Address setup time to CK,

CK# referenced to Vih(ac) / Vil(ac) levels

Command and Address hold time from CK,

CK# referenced to Vih(ac) / Vil(ac) levels

Control & Address Input pulse width for each input tMRD tMOD tCCD tDAL(min) tMPRR tRAS tRRD tRRD tFAW tFAW

4 max

(12tCK,15ns)

4

1

35 max

(4tCK,6ns) max

(4tCK,7.5ns)

30

40

-

-

-

4 max

(12tCK,15ns)

4

-

-

-

4 max

(12tCK,15ns)

4

-

-

-

4 max

(12tCK,15ns)

4

- nCK

-

- nCK

WR + roundup (tRP / tCK(AVG))

- 1 nCK nCK - 1 - 1 -

9*tREFI 36 9*tREFI 37.5 9*tREFI 37.5 9*tREFI ns

-

-

- max

(4tCK,6ns) max

(4tCK,7.5ns)

30

-

-

- max

(4tCK,7.5ns) max

(4tCK,10ns)

37.5

-

-

- max

(4tCK,10ns) max

(4tCK,10ns)

40

-

-

- ns

- 45 - 50 - 50 - ns tIPW 560 - 620 - 780 - 900 - ps

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Product Specifications

PART NO.:

VL31B5263A-K0/K9/F8/E7S REV: 1.0

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9

(DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Unit

MIN MAX MIN MAX MIN MAX MIN MAX

Refresh Timing

2Gb REFRESH to REFRESH or REFRESH to ACTIVE command interval

Average periodic refresh interval

(0°C<= TCASE <= 85 °C)

Average periodic refresh interval

(85°C<= TCASE <= 95 °C)

Calibration Timing

tRFC 160 - 160 - 160 - 160 - ns

Power-up and RESET calibration time tZQinitI 512 - 512 - 512 - 512 - tCK

Normal operation Full calibration time tZQoper 256 - 256 - 256 - 256 - tCK

Reset Timing

Exit Reset from CKE HIGH to a valid command

Self Refresh Timing

Exit Self Refresh to commands not requiring a locked DLL

Exit Self Refresh to commands requiring a locked DLL

Minimum CKE low width for Self refresh entry to exit timing

Valid Clock Requirement after Self Refresh

Entry (SRE)

Valid Clock Requirement before Self

Refresh Exit (SRX)

Power Down Timing

Exit Power Down with DLL to any valid command; Exit Precharge Power Down with

DLL frozen to commands not requiring a locked DLL

Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL

CKE minimum pulse width

Command pass disable delay

Power Down Entry to Exit Timing

Timing of ACT command to Power Down entry

Timing of PRE command to Power Down entry

Timing of RD/RDA command to Power

Down entry

Timing of WR command to Power Down entry BL8 (OTF, MRS), BL4OTF

Timing of WRA command to Power Down entry BL8 (OTF, MRS), BL4OTF

Timing of WR command to Power Down entry (BL4MRS)

Timing of WRA command to Power Down entry (BL4MRS)

Timing of REF command to Power Down entry

Timing of MRS command to Power Down entry tXPR tXS tCKESR tCKSRE tCKSRX max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC+10ns) tCKE(min) +

1tCK max(5tC,

10ns) max(5tC,

10ns)

-

-

-

-

-

-

-

- tXP tXPDLL tCKE tCPDED tPD max

(3tCK,6ns) max

(10tCK,24ns) max (3tCK,

5.625ns)

1 tCKE(min)

-

-

-

-

9*tREFI max

(3tCK,6ns) max

(10tCK,24ns) max (3tCK,

5.625ns)

1 tCKE(min)

-

-

-

-

9*tREFI max

(3tCK,7.5ns) max

(10tCK,24ns) max (3tCK,

5.625ns)

1 tCKE(min)

-

-

-

-

9*tREFI max

(3tCK,7.5ns) max

(10tCK,24ns) max (3tCK,

7.5ns)

1 tCKE(min)

-

-

-

-

9*tREFI tRDPDEN tWRPDEN tWRAPDEN tWRPDEN tWRAPDEN

RL + 4 +1

WL + 4

+(tWR/ tCK)

WL+4+WR+

1

WL + 2

+(tWR/ tCK)

WL+2+WR+

1

-

-

- max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC+10ns) tCKE(min) +

1tCK max(5tCK,

10ns) max(5tCK,

10ns)

-

-

- max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC +10ns) tCKE(min) +

1tCK max(5tCK,

10ns) max(5tCK,

10ns)

-

-

- max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC +10ns) tCKE(min) +

1tCK max(5tCK,

10ns) max(5tCK,

10ns)

-

-

- nCK tCK

-

-

RL + 4 +1

WL + 4

+(tWR/ tCK)

-

-

RL + 4 +1

WL + 4

+(tWR/ tCK)

-

-

RL + 4 +1

WL + 4

+(tWR/ tCK)

-

- nCK

- WL+4+WR+1 - WL+4+WR+1 - WL+4+WR+1 - nCK

-

WL + 2

+(tWR/ tCK)

-

WL + 2

+(tWR/ tCK)

-

WL + 2

+(tWR/ tCK)

- nCK

- WL+2+WR+1 - WL+2+WR+1 - WL+2+WR+1 - nCK

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9

Product Specifications

PART NO.:

VL31B5263A-K0/K9/F8/E7S REV: 1.0

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9

(DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Unit

MIN MAX MIN MAX MIN MAX MIN MAX

ODT Timing

ODT high time without write command or with write command and BC4

ODT high time with Write command and BL8

Asynchronous RTT turn-on delay (Power-

Down with DLL frozen)

Asynchronous RTT turn-off delay (Power-

Down with DLL frozen)

ODT turn-on

RTT_NOM and RTT_WR turn-off time from

ODTL off reference

ODTH8 tAON

6

-225

-

225

6

-250

-

250

6

-300

-

300

6

-400

-

400 nCK ps

Write Leveling Timing

First DQS pulse rising edge after tDQSS margining mode is programmed

DQS/DQS delay after tDQS margining mode is programmed

Hold time for tDQSS latch

Write leveling output delay tWLH tWLO

165

0

-

7.5

195

0

-

9

245

0

-

9

325

0

-

9 ps ns

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PART NO.:

Package Dimensions

Product Specifications

VL31B5263A-K0/K9/F8/E7S

FRONT VIEW

133.35

REV: 1.0

3.67

MAX

0.70 R MAX

(8X)

2.50 D

(2X)

2.30 TYP

2.20 TYP

1.50 TYP

PIN 1

0.75 R

54.68

TYP

1.50 +/-0.10

123.00

TYP

BACK VIEW

1.00

TYP

0.80

TYP

9.50

PIN 120

17.30

30.00

1.27 +/-0.10

3.05 TYP

5.175 (2X)

PIN 240

71.00

TYP

5.00

TYP

47.00

TYP

3.00 TYP

(4X)

PIN 121

Note: 1. All dimensions are in millimeters with tolerance +/- 0.15mm unless otherwise specified.

2. The dimensional diagram is for reference only.

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Revision History:

PART NO.:

Product Specifications

VL31B5263A-K0/K9/F8/E7S REV: 1.0

05/21/2011 1.0 All Spec

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