L2_slides

Transmission techniques and multiplexing hierarchies

Switching Technology

S38.165

http://www.netlab.hut.fi/opetus/s38165

© P. Raatikainen Switching Technology / 2005

L2 - 1

Transmission techniques and multiplexing hierarchies

• Transmission of data signals

• Timing and synchronization

• Transmission techniques and multiplexing

– PDH

– ATM

– IP/Ethernet

– SDH/SONET

– OTN

– GFP

© P. Raatikainen Switching Technology / 2005

L2 - 2

Transmission of data signals

• Encapsulation of user data into layered protocol structure

• Physical and link layers implement functionality that have relevance to switching

– multiplexing of transport signals (channels/connections)

– medium access and flow control

– error indication and recovery

– bit, octet and frame level timing/synchronization

– line coding (for spectrum manipulation and timing extraction)

© P. Raatikainen Switching Technology / 2005

L2 - 3

Encapsulation of user data

PLH

LLH

NLH

User data

TLH Transport layer payload

Network layer payload

Link layer payload

Physical layer

© P. Raatikainen Switching Technology / 2005

error coding/indication

octet & frame synchronization

addressing

medium access & flow control

line coding

bit level timing

physical signal generation/

recovery

L2 - 4

Synchronization of transmitted data

• Successful transmission of data requires bit, octet, frame and packet level synchronism

• Synchronous systems (e.g. PDH and SDH) carry additional information (embedded into transmitted line signal) for accurate recovery of clock signals

• Asynchronous systems (e.g. Ethernet) carry additional bit patterns to synchronize receiver logic

© P. Raatikainen Switching Technology / 2005

L2 - 5

Timing accuracy

• Inaccuracy of frequency classified in telecom networks to

– jitter (short term changes in frequency > 10 Hz)

– wander (< 10 Hz fluctuation)

– long term frequency shift (drift or skew)

• To maintain required timing accuracy, network nodes are connected to a hierarchical synchronization network

– Universal Time Coordinated (UTC): error in the order of 10

-13

– Error of Primary Reference Clock (PRC) of the telecom network in the order of 10

-11

© P. Raatikainen Switching Technology / 2005

L2 - 6

Timing accuracy (cont.)

• Inaccuracy of clock frequency causes

– degraded quality of received signal

– bit errors in regeneration

– slips: in PDH networks a frame is duplicated or lost due to timing difference between the sender and receiver

• Based on applied synchronization method, networks are divided into

– fully synchronous networks (e.g. SDH)

– plesiochronous networks (e.g. PDH), sub-networks have nominally the same clock frequency but are not synchronized to each other

– mixed networks

© P. Raatikainen Switching Technology / 2005

L2 - 7

Methods for bit level timing

• To obtain bit level synchronism receiver clocks must be synchronized to incoming signal

• Incoming signal must include transitions to keep receiver’s clock recovery circuitry in synchronism

• Methods to introduce line signal transitions

– Line coding

– Block coding

– Scrambling

© P. Raatikainen Switching Technology / 2005

L2 - 8

Line coding

Uncoded

+V

1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1

+V

ADI

ADI RZ

+V

AMI RZ

+V

-V

© P. Raatikainen

ADI - Alternate Digit Inversion

ADI RZ - Alternate Digit Inversion Return to Zero

AMI RZ - Alternate Mark Inversion Return to Zero

Switching Technology / 2005

L2 - 9

Line coding (cont.)

• ADI, ADI RZ and codes alike introduce DC balance shift

=> clock recovery becomes difficult

• AMI and AMI RZ introduces DC balance, but lacks effective ability to introduce signal transitions

• HDB3 (

High Density Bipolar 3

) code, used in PDH systems, guarantees a signal transition at least every fourth bit

• 0000 coded by 000V when there is an odd number of pulses since the last violation (V) pulse

• 0000 coded by B00V when there is an even number of pulses since the last violation pulse

HDB3

+V

1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1

V

B V

-V

© P. Raatikainen Switching Technology / 2005

L2 - 10

Line coding (cont.)

• When bit rates increase (> 100 Mbit/s) jitter requirements become tighter and signal transitions should occur more frequently than in HDB3 coding

• CMI (Coded Mark Inversion) coding was introduced for electronic differential links and for optical links

• CMI doubles bit rate on transmission link => higher bit rate implies larger bandwidth and shortened transmission distance

CMI

+V

1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1

-V

© P. Raatikainen Switching Technology / 2005

L2 - 11

Block coding

• Entire blocks of n bits are replaced by other blocks of m bits (m > n)

nBmB block codes are usually applied on optical links by using on-off keying

• Block coding adds variety of “1”s and “0”s to obtain better clock synchronism and reduced jitter

• Redundancy in block codes (in the form of extra combinations) enables error recovery to a certain extent

• When m>n the coded line signal requires larger bandwidth than the original signal

• Examples: 4B5B (FDDI), 5B6B (E3 optical links) and 8B10B (GbE)

© P. Raatikainen Switching Technology / 2005

L2 - 12

Coding examples

4B5B coding

Input word

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Output word

1 1 1 1 0

0 1 0 0 1

1 0 1 0 0

1 0 1 0 1

0 1 0 1 0

0 1 0 1 1

0 1 1 1 0

0 1 1 1 1

1 0 0 1 0

1 0 0 1 1

1 0 1 1 0

1 0 1 1 1

1 1 0 1 0

1 1 0 1 1

1 1 1 0 0

1 1 1 0 1

Other output words

0 0 0 0 0 Quiet line symbol

1 1 1 1 1 Idle symbol

0 0 1 0 0 Halt line symbol

1 1 0 0 0 Start symbol

1 0 0 0 1 Start symbol

0 1 1 0 1 End symbol

0 0 1 1 1 Reset symbol

1 1 0 0 1 Set Symbol

0 0 0 0 1 Invalid

0 0 0 1 0 Invalid

0 0 0 1 1 Invalid

0 0 1 0 1 Invalid

0 0 1 1 0 Invalid

0 1 0 0 0 Invalid

0 1 1 0 0 Invalid

1 0 0 0 0 Invalid

© P. Raatikainen Switching Technology / 2005

5B6B coding

Input word

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

...

1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

Output word

1 0 1 0 1 1

1 0 1 0 1 0

1 0 1 0 0 1

1 1 1 0 0 0

...

0 1 0 0 1 1

0 1 0 1 1 1

0 1 1 0 1 1

0 1 1 1 0 0

L2 - 13

Scrambling

• Data signal is changed bit by bit according to a separate repetitive sequence (to avoid long sequences of “1”s or “0”s)

• Steps of the sequence give information on how to handle bits in the signal being coded

• A scrambler consists of a feedback shift register described by a polynomial (x

N

+ … + x m

+ … + x k

+ … + x + 1)

• Polynomial specifies from where in the shift register feedback is taken

• Output bit rate is the same as the input bit rate

• Scrambling is not as effective as line coding

© P. Raatikainen Switching Technology / 2005

L2 - 14

Scrambler example

SDH/STM-1 uses x 7 +x 6 +1 polynomial

Scrambler

Preset x

0

D x

1

D x

2

D x

3

D x

4

D x

5

D x

6

D

+ x

7

D

S i

D i

+

X i

Descrambler

Preset x

0

D x

1

D x

2

D x

3

D x

4

D x

5

D x

6

D

+ x

7

D

S i

X i

+

R i

=D i

X i

= S i

D i

R i

= S

= S i i

X

(S i i

D i

) = D i

© P. Raatikainen Switching Technology / 2005

L2 - 15

Methods for octet and frame level timing

• Frame alignment bit pattern

• Start of frame signal

• Use of frame check sequence

© P. Raatikainen Switching Technology / 2005

L2 - 16

Frame alignment sequence

• Data frames carry special frame alignment bit patterns to obtain octet and frame level synchronism

• Data bits scrambled to avoid misalignment

• Used in networks that utilize synchronous transmission, e.g. in PDH, SDH and OTN

• Examples

– PDH E1 frames carry bit sequence 0011011 in every other frame

(even frames)

– SDH and OTN frames carry a six octet alignment sequence

(hexadecimal form: F6 F6 F6 28 28 28) in every frame

© P. Raatikainen Switching Technology / 2005

L2 - 17

Start of frame signal

• Data frames carry special bit patterns to synchronize receiver logic

• False synchronism avoided for example by inserting additional bits into data streams

• Used in synchronous and asynchronous networks, e.g.,

Ethernet and HDLC

• Examples

– Ethernet frames are preceded by a 7-octet preamble field

(10101010) followed by a start-of-frame delimiter octet (10101011)

– HDLC frames are preceded by a flag byte (0111 1110)

© P. Raatikainen Switching Technology / 2005

L2 - 18

Frame check sequence

• Data frames carry no special bit patterns for synchronization

• Synchronization is based on the use of error indication and correction fields

– CRC (Cyclic Redundancy Check) calculation

• Used in bit synchronous networks such as ATM and GFP

(Generic Framing Procedures)

• Example

– ATM cells streams can be synchronized to HEC (Header Error

Control) field, which is calculated across ATM cell header

© P. Raatikainen Switching Technology / 2005

L2 - 19

Transmission techniques

• PDH (Plesiochronous Digital Hierarchy)

• ATM (Asynchronous Transfer Mode)

• IP/Ethernet

• SDH (Synchronous Digital Hierarchy)

• OTN (Optical Transport network)

• GFP (Generic Framing Procedure)

© P. Raatikainen Switching Technology / 2005

L2 - 20

Plesiochronous Digital Hierarchy

(PDH)

Transmission technology of the

digitized telecom network

Basic channel capacity 64 kbit/s

Voice information PCM coded

8 bits per sample

A or

µµµµ

law

sample rate 8 kHz (125

µµµµ

s)

Channel associated signaling (SS7)

Higher order frames obtained by

multiplexing four lower order frames bit by bit and adding some synchr. and management info

The most common switching and

transmission format in the telecommunication network is PCM 30

(E1)

E0

E1

E2

64 kbit/s

E3

E4

8.448 Mbit/s

139.264 Mbit/s

34.368 Mbit/s x 4

1 channel x 4 x 4

1920 channels

480 channels

120 channels

2.048 Mbit/s

...

x 32

30 channels

© P. Raatikainen Switching Technology / 2005

L2 - 21

PDH E1-frame structure

(even frames)

Multi- frame

F0 F1 . . . F14 F15

Voice channels 1 - 15

T0 T1 T2 T0

. . .

T15 T16 T17

Voice channels 16 - 30

. . .

T28 T29 T30 T31

Frame alignment time-slot

C 0 0 1 1 0 1 1

Frame alignment signal (FAS)

Error indicator bit (CRC-4)

© P. Raatikainen

Signaling time-slot

0 0 0 0 1 A 1 1

Multi-frame alignment bit sequence in F0 Multi-frame alarm

Switching Technology / 2005

Voice channel 28

B1 B2 B3 B4 B5 B6 B7 B8

Polarity

Voice sample amplitude

L2 - 22

PDH E1-frame structure

(odd frames)

Multi- frame

F0 F1 . . . F14 F15

Voice channels 1 - 15

T0 T1 T2 T0

. . .

T15 T16 T17

Voice channels 16 - 30

. . .

T28 T29 T30 T31

Frame alignment time-slot

C 1 A D D D D D

Error indicator bit (CRC-4)

Data bits for management

Far end alarm indication

© P. Raatikainen

Signaling time-slot a b c d a b c c

Channel 1 signaling bits

Channel 16 signaling bits

Switching Technology / 2005

Nowadays, time slot 1 used for signaling and time slot 16 for voice

L2 - 23

PDH-multiplexing

• Tributaries have the same nominal bit rate, but with a specified, permitted deviation (100 bit/s for 2.048 Mbit/s)

• Plesiochronous = tributaries have almost the same bit rate

• Justification and control bits are used in multiplexed flows

• First order (E1) is octet-interleaved, but higher orders (E2,

…) are bit-interleaved

© P. Raatikainen Switching Technology / 2005

L2 - 24

PDH network elements

concentrator

n channels are multiplexed to a higher capacity link that carries m channels (n > m)

multiplexer

n channels are multiplexed to a higher capacity link that carries n channels

cross-connect

– static multiplexing/switching of user channels

switch

– switches incoming TDM/SDM channels to outgoing ones

© P. Raatikainen Switching Technology / 2005

L2 - 25

Example PDH network elements

Concentrator

n > m

m output channels

Cross-connect

DXC

Multiplexer

4

4

4

3

3

3

2

2

2

1

1

1

© P. Raatikainen

n = m

m output channels

Switching Technology / 2005

Switch

4

4

4

3

3

3

2

2

2

1

1

1

L2 - 26

Synchronous digital hierarchy

STM-256

40 Gbit/s

Major ITU-T SDH standards:

- G.707

- G.783

STM-64

10 Gbit/s x 4

Notice that each frame transmitted in 125

µ s !

STM-16

2.48 Gbit/s x 4

STM-4

622 Mbit/s x 4

STM-1

155 Mbit/s x 4

© P. Raatikainen Switching Technology / 2005

L2 - 27

SDH reference model

MPX

STM-n

DXC

STM-n

R

STM-n

R

STM-n

MPX

Multiplexing section

Regeneration section

Regeneration section

Regeneration section

Multiplexing section

Path layer connection

- DXC Digital gross-connect

- MPX Multiplexer

- R Repeater

© P. Raatikainen Switching Technology / 2005

L2 - 28

SDH-multiplexing

• Multiplexing hierarchy for plesiochronous and synchronous tributaries

(e.g. E1 and E3)

• Octet-interleaving, no justification bits - tributaries visible and available in the multiplexed SDH flow

• SDH hierarchy divided into two groups:

– multiplexing level (virtual containers, VCs)

– line signal level (synchronous transport level, STM)

• Tributaries from E1 (2.048 Mbit/s) to E4 (139.264 Mbit/s) are synchronized (using justification bits if needed) and packed in containers of standardized size

• Control and supervisory information (POH, path overhead) added to containers => virtual container (VC)

© P. Raatikainen Switching Technology / 2005

L2 - 29

SDH-multiplexing (cont.)

Different sized VCs for different tributaries (e.g. VC-12/E1, VC-3/E3,

VC-4/E4)

• Smaller VCs can be packed into a larger VC (+ new POH)

Section overhead (SOH) added to larger VC

=> transport module

• Transport module corresponds to line signal (bit flow transferred on the medium)

– bit rate is 155.52 Mbit/s or its multiples

– transport modules called STM-N (N = 1, 4, 16, 64, ...)

– bit rate of STM-N is Nx155.52 Mbit/s

– duration of a module is 125

µ s (= duration of a PDH frame)

© P. Raatikainen Switching Technology / 2005

L2 - 30

SDH network elements

• regenerator (intermediate repeater, IR)

– regenerates line signal and may send or receive data via communication channels in RSOH header fields

• multiplexer

– terminal multiplexer multiplexes/demultiplexes PDH and SDH tributaries to/from a common STM-n

– add-drop multiplexer adds or drops tributaries to/from a common STMn

• digital cross-connect

– used for rearrangement of connections to meet variations of capacity or for protection switching

– connections set up and released by operator

© P. Raatikainen Switching Technology / 2005

L2 - 31

Example SDH network elements

STM-n

STM-n

STM-n

Add-drop multiplexer

STM-n STM-n

ADM

Cross-connect

DXC

STM-n

STM-n

STM-n

Terminal multiplexer

STM-n

ADM

2 - 140 Mbit/s

© P. Raatikainen Switching Technology / 2005

2 - 140 Mbit/s

L2 - 32

Generation of STM-1 frame

PDH/E1

Justification

VC-12

+ POH

MUX

+ POH

VC-4

+ SOH

STM-1

© P. Raatikainen Switching Technology / 2005

L2 - 33

STM-n frame

Three main fields:

– Regeneration and multiplexer section overhead (RSOH and MSOH)

Payload and path overhead (POH)

– AU (administrative) pointer specifies where payload (VC-4 or VC-3) starts

nx9 octets nx261 octets

3

1

5

RSOH

AU-4 PTR

P

O

H

MSOH

© P. Raatikainen Switching Technology / 2005

L2 - 34

Synchronization of payload

Position of each octet in a STM frame (or VC frame) has a number

• AU pointer contains position number of the octet in which VC starts

• Lower order VC included as part of a higher order VC (e.g. VC-12 as part of VC-4)

STM-1 no. k

STM-1 no. k+1

RSOH

AU-4 PTR

MSOH

RSOH

AU-4 PTR

MSOH

VC-4 no. 0

VC-4 no. 1

VC-4 no. 2

© P. Raatikainen Switching Technology / 2005

L2 - 35

ATM concept in summary

cell

– 53 octets

routing/switching

– based on VPI and VCI

adaptation

– processing of user data into ATM cells

error control

– cell header checking and discarding

flow control

– no flow control

– input rate control

congestion control

– cell discarded (two priorities)

© P. Raatikainen Switching Technology / 2005

L2 - 36

ATM protocol reference model

© P. Raatikainen

AAL

ATM

Phys

Convergence sublayer (CS)

Segmentation and reassembly (SAR)

Generic flow control

VPI/VCI translation

Multiplexing and demultiplexing of cells

Cell rate decoupling

HEC header sequence generation/verification

Cell delineation

Transmission frame adaptation

Transmission frame generation/recovery

Timing

Physical medium

Switching Technology / 2005

L2 - 37

Reference interfaces

© P. Raatikainen

ATM network

NNI

EX

UNI

TE

NNI - Network-to-Network Interface

UNI - User Network Interface

EX

TE

- Exchange Equipment

- Terminal Equipment

Switching Technology / 2005

L2 - 38

ATM cell structure

5 octets

ATM header

48 octets

VPI

VPI

VCI

VCI

ATM header for UNI

PTI

PTI

VCI

VCI

CPL

CPL

UNI - User Network Interface

NNI - Network-to-Network Interface

VPI - Virtual Path Identifier

VCI - Virtual Channel Identifier

GFC - Generic Flow Control

PTI - Payload Type Identifier

CPL - Cell Loss Priority

HEC - Header Error Control

VPI

VPI

VCI

VCI

ATM header for NNI

PTI

PTI

VCI

VCI

CPL

CPL

© P. Raatikainen

HEC = 8 x (header octets 1 to 4) / (x

8

+ x

2

+ x + 1)

Switching Technology / 2005

L2 - 39

ATM connection types

VCI 1

VCI 2

VCI 1

VCI 2

VPI 1

VPI 2

© P. Raatikainen

Physical channel

VPI 1

VPI 2

VCI 1

VCI 2

VCI 1

VCI 2

VCI k - Virtual Channel Identifier k

VPI k - Virtual Path Identifier k

Switching Technology / 2005

L2 - 40

Physical layers for ATM

SDH

(Synchronous Digital Hierarchy)

STM-1 155 Mbit/s

STM-4 622 Mbit/s

STM-16 2.4 Gbit/s

PDH

(Plesiochronous Digital Hierarchy)

E1 2 Mbit/s

E3 34 Mbit/s

E4 140 Mbit/s

TAXI 100 Mbit/s and IBM 25 Mbit/s

Cell based interface

uses standard bit rates and physical level interfaces

(e.g. E1, STM-1 or STM-4)

HEC used for framing

© P. Raatikainen Switching Technology / 2005

L2 - 41

Transport of data in ATM cells

Network layer

ATM adaptation layer (AAL)

ATM layer

IP packet

≤≤≤≤

65 535

AAL 5 payload

Pad 0 - 47 octets

(1+1+ 2) octets

4 octets

P

UU/

CPI/

LEN

CRC

5

H

48

Cell payload H Cell payload H Cell payload H Cell payload

Physical layer

© P. Raatikainen

P - Padding octets

UU - AAL layer user-to-user indicator

CPI - Common part indicator

LEN - Length indicator

Switching Technology / 2005

L2 - 42

9 octets

3

1

5

SOH

AU-4 PTR

SOH

© P. Raatikainen

ATM cell encapsulation / SDH

261 octets

...

STM-1 frame

VC-4 frame

G1

F2

H4

Z3

J1

B3

C2

Z4

Z5

...

...

VC-4 POH

Switching Technology / 2005

...

ATM cell

L2 - 43

ATM cell encapsulation / PDH (E1)

TS0

TS0

TS0

TS0

TS0

Header

Header

32 octets

TS16

TS16

TS16

TS16

TS16

Header

Head.

TS0

frame alignment

F3 OAM functions

loss of frame alignment

performance monitoring

transmission of FERF and LOC

performance reporting

© P. Raatikainen Switching Technology / 2005

TS16

reserved for signaling

L2 - 44

Cell based interface

P

L

Frame structure for cell base interfaces:

27 1 2

IDLE or

PL-OAM

H ATM layer H ATM layer

...

26

H ATM layer

P

L

27

IDLE or

PL-OAM

PL cells processed on physical layer (not on ATM layer)

IDLE cell for cell rate adaptation

PL-OAM cells carry physical level OAM information

(regenerator (F1) and transmission path (F3) level messages)

PL cell identified by a pre-defined header

00000000 00000000 0000000 00000001 (IDLE cell)

00000000 00000000 0000000 00001001 (phys. layer OAM)

xxxx0000 00000000 0000000 0000xxxx (reserved for phys. layer)

H = ATM cell Header, PL = Physical Layer, OAM = Operation Administration and Maintenance

© P. Raatikainen Switching Technology / 2005

L2 - 45

ATM network elements

Gross-connect

– switching of virtual paths (VPs)

– VP paths are statically connected

Switch

– switching of virtual channel (VCs)

VC paths are dynamically or statically connected

DSLAM (Digital Subscriber Line Access Multiplexer)

– concentrates a larger number of sub-scriber lines to a common higher capacity link

– aggregated capacity of subscriber lines surpasses that of the common link

© P. Raatikainen Switching Technology / 2005

L2 - 46

Ethernet

• Originally a link layer protocol for LANs

(10 and 100 MbE)

• Upgrade of link speeds

=> optical versions 1GbE and 10 GbE

=> suggested for long haul transmission

• No connections - each data terminal (DTE) sends data when ready - MAC is based on CSMA/CD

• Synchronization

– line coding, preamble pattern and start-of-frame delimiter

– Manchester code for 10 MbE, 8B6T for 100 MbE,

8B10B for GbE

© P. Raatikainen Switching Technology / 2005

L2 - 47

Ethernet frame

64 - 1518 octets

Preamble

7

S

F

D

1

DA

6

SA T/L

6 2

Payload

46 - 1500

CRC

4

Preamble - AA AA AA AA AA AA AA (Hex)

SFD - Start of Frame Delimiter AB (Hex)

DA - Destination Address

SA - Source Address

T/L - Type (RFC894, Ethernet) or Length (RFC1042, IEEE 802.3) indicator

CRC - Cyclic Redundance Check

Inter-frame gap 12 octets (9,6

µµµµ

s /10 MbE)

© P. Raatikainen Switching Technology / 2005

L2 - 48

1GbE frame

512 - 1518 octets

Preamble

7

S

F

D

1

DA

6

SA

6

L

2

Payload

46 - 1500

Preamble - AA AA AA AA AA AA AA (Hex)

SFD - Start of Frame Delimiter AB (Hex)

DA - Destination Address

SA - Source Address

T/L - Type (RFC894, Ethernet) or Length (RFC1042, IEEE 802.3) indicator

CRC - Cyclic Redundancy Check

Inter-frame gap 12 octets (96 ns /1 GbE)

Extension - for padding short frames to be 512 octets long

© P. Raatikainen Switching Technology / 2005

CRC Extension

4

L2 - 49

Ethernet network elements

Repeater

– interconnects LAN segments on physical layer

– regenerates all signals received from one segment and forwards them onto the next

Bridge

– interconnects LAN segments on link layer (MAC)

– all received frames are buffered and error free ones are forwarded to another segment (if they are addressed to it)

Hub and switch

– hub connects DTEs with two twisted pair links in a star topology and repeats received signal from any input to all output links

– switch is an intelligent hub, which learns MAC addresses of DTEs and is capable of directing received frames only to addressed ports

© P. Raatikainen Switching Technology / 2005

L2 - 50

Optical transport network

• Optical Transport Network (OTN), being developed by ITU-T

(G.709), specifies interfaces for optical networks

• Goal to gather for the transmission needs of today’s wide range of digital services and to assist network evolution to higher bandwidths and improved network performance

• OTN builds on SDH and introduces some refinements:

– management of optical channels in optical domain

– FEC to improve error performance and allow longer link spans

– provides means to manage optical channels end-to-end in optical domain (i.e. no O/E/O conversions)

– interconnections scale from a single wavelength to multiple ones

© P. Raatikainen Switching Technology / 2005

L2 - 51

OTN reference model

OMPX

OA OA

OTS OTS

OMS

OCh

- OCh

- OA

Optical Channel

Optical Amplifier

- OMS Optical Multiplexing Section

- OMPX Optical Multiplexer

- OTS Optical Transport Section

© P. Raatikainen Switching Technology / 2005

OTS

OMPX

L2 - 52

OTN layers and OCh sub-layers

SONET/

SDH

ATM Ethernet

Optical channel

Optical multiplexing section

(OMSn)

Optical transport section

(OTSn)

IP

© P. Raatikainen Switching Technology / 2005

OPU

Optical channel payload unit

ODU

Optical channel data unit

OTU

Optical channel transport unit

L2 - 53

OTN frame structure

Three main fields

– Optical channel overhead

– Payload

– Forward error indication field

GbE

ATM/FR

IP

SONET/SDH

DWDM

© P. Raatikainen

FR SONET/SDH ATM GbE IP

Och Payload

Client

Digital wrapper

Switching Technology / 2005

FEC

L2 - 54

OTN frame structure (cont.)

1 ..... 16

Och overhead

4080 bytes

17 ...................................

Payload

3824 3825 ... 4080

FEC

1

2

3

4

1 ..... 7 8 ..... 14

Frame alignmt.

OTU overhead

15 ... 16

ODU overhead

OPU overh.

OTU - Optical transport unit

ODU - Optical data unit

OPU - Optical payload unit

FEC - Forward error correction

© P. Raatikainen

Frame size remains the same (4x4080)

regardless of line rate

=> frame rate increases as line rate increases

Three line rates defined:

• OTU1 2.666 Gbit/s

• OTU2 10.709 Gbit/s

• OTU3 43.014 Gbit/s

Switching Technology / 2005

L2 - 55

Generation of OTN frame and signal

Client signal

OTN frame generation

OPU ODU OTU

+ OPU-OH + OTU-OH

+ FEC

Client signal

Client signal

OCh

OCh

OTN signal generation

OMUX OMS

© P. Raatikainen Switching Technology / 2005

OTS

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OTN network elements

optical amplifier

– amplifies optical line signal

optical multiplexer

– multiplexes optical wavelengths to OMS signal

– add-drop multiplexer adds or drops wavelengths to/from a common OMS

optical cross-connect

– used to direct optical wavelengths (channels) from an OMS to another

– connections set up and released by operator

optical switches ?

– when technology becomes available optical switches will be used for switching of data packets in the optical domain

© P. Raatikainen Switching Technology / 2005

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Generic Framing Procedure (GFP)

• Recently standardized traffic adaptation mechanism especially for transporting block-coded and packet-oriented data

• Standardized by ITU-T (G.7041) and ANSI (T1.105.02) (the only standard supported by both organizations)

• Developed to overcome data transport inefficiencies of existing ATM,

POS, etc. technologies

• Operates over byte-synchronous communications channels (e.g.

SDH/SONET and OTN)

• Supports both fixed and variable length data frames

• Generalizes error-control-based frame delineation scheme ( successfully employed in ATM

)

– relies on payload length and error control check for frame boundary delineation

© P. Raatikainen Switching Technology / 2005

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GFP (cont.)

• Two frame types: client and control frames

– client frames include client data frames and client management frames

– control frames used for OAM purposes

• Multiple transport modes (coexistent in the same channel) possible

– Frame-mapped GFP for packet data, e.g. PPP, IP, MPLS and Ethernet)

– Transparent-mapped GFP for delay sensitive traffic (storage area networks), e.g. Fiber Channel, FICON and ESCON

© P. Raatikainen Switching Technology / 2005

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GFP frame types

GFP frames

Client frames Control frames

Client data frames

Client management frames

Idle frames OA&M frames

© P. Raatikainen Switching Technology / 2005

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GFP client data frame

• Composed of a frame header and payload

• Core header intended for data link management

– payload length indicator (PLI, 2 octets), HEC (CRC-16, 2 octets)

• Payload field divided into payload header, payload and optional FCS

(CRC-32) sub-fields

• Payload header includes:

– payload type (2 octets) and type HEC (2 octets) sub-fields

– optional 0 - 60 octets of extension header

• Payload:

– variable length (0 - 65 535 octets, including payload header and FCS) for frame mapping mode (GFP-F) - frame multiplexing

– fixed size Nx[536, 520] for transparent mapping mode (GFP-T) - no frame multiplexing

© P. Raatikainen Switching Technology / 2005

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GFP frame structure

Payload length indicator

Core HEC

PTI PFI

UPI

EXI

Core header

Payload header

Payload type

Type HEC

0 – 60 bytes extension header

(optional)

CID

Spare

Extension HEC MSB

Extension HEC LSB

Payload area

Payload

[N x 536, 520 bytes or variable length packet]

Payload FCS

CID - Channel identifier

FCS - Frame Check Sequence

EXI - Extension Header Identifier

HEC - Header Error Check

PFI - Payload FCS Indicator

PTI - Payload Type Indicator

UPI - User payload Identifier

Source: IEEE Communications Magazine, May 2002

© P. Raatikainen Switching Technology / 2005

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GFP relationship to client signals and transport paths

Frame mapped

GFP client-dependent

GFP client-independent

SDH/SONET path

Transparent mapped

OTN ODUk path

ESCON - Enterprise System CONnection

FICON - Fiber CONnection

IP/PPP - IP over Point-to-Point Protocol

MAPOS - Multiple Access Protocol over SONET/SDH

RPR - Resilient Packet Ring

Source: IEEE Communications Magazine, May 2002

© P. Raatikainen Switching Technology / 2005

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Adapting traffic via GFP-F and GFP-T

PLI

2 bytes cHEC

2 bytes

Payload header

4 bytes

GFP-F frame

Client PDU

(PPP, IP, Ethernet, RPR, etc.)

FCS

(optional)

4 bytes

PLI

2 bytes cHEC

2 bytes

Payload header

4 bytes

GFP-T frame

8x64B/65B superblock #1

FCS - Frame Check Sequence cHEC - Core Header Error Control

PDU

PLI

- Packet Data Unit

- Payload Length Indicator

© P. Raatikainen Switching Technology / 2005

#2

...

#N-1 #N

FCS

(optional)

4 bytes

L2 - 64

GFP-T frame mapping

8B 8B

64B/65B code block

8B 8B 8B 8B 8B 8B

8 x 64B/65B code blocks

Superblock (8 x 64B/65B code blocks + CRC-16)

CRC-16

GFP-T frame with five superblocks

Core header and payload header

© P. Raatikainen Switching Technology / 2005

FCS (optional)

L2 - 65

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