DG508A

DG508A
DG508AxWE
Rev. A
RELIABILITY REPORT
FOR
DG508AxWE
PLASTIC ENCAPSULATED DEVICES
December 17, 2002
MAXIM INTEGRATED PRODUCTS
120 SAN GABRIEL DR.
SUNNYVALE, CA 94086
Written by
Reviewed by
Jim Pedicord
Quality Assurance
Reliability Lab Manager
Bryan J. Preeshl
Quality Assurance
Executive Director
Conclusion
The DG508A successfully meets the quality and reliability standards required of all Maxim products. In addition,
Maxim’s continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim’s quality
and reliability standards.
Table of Contents
I. ........Device Description
II. ........Manufacturing Information
III. .......Packaging Information
IV. .......Die Information
V. ........Quality Assurance Information
VI. .......Reliability Evaluation
......Attachments
I. Device Description
A. General
Maxim’s DG508A is a monolithic CMOS analog
multiplexer.
multiplexer.
The DG508A is a single 8 channel (1 of 8)
This device features break-before-make switching. Maxim guarantees that this multiplexer will not latch-up if the
power supplies are turned off with the input signals still present. Maxim also guarantees continuous operation
when this device is powered by supplies ranging from ±4.5V to ±18V. The multiplexer operates over a wide range
of power supplies from ±4.5V to ±18V.
The DG508A is a plug-in upgrade for the industry-standard DG508A. Maxim’s parts have lower on resistance,
faster enable switching times, and significantly lower leakage currents. The DG508A also consumes significantly
lower power, making it ideal for portable equipment.
B. Absolute Maximum Ratings
Item
Voltage Referenced to VV+
GND
Digital Inputs VS, VD (Note 1)
Current (Any Terminal Except S or D)
Continuous Current, S or D
Peak Current, S or D (Pulse at 1msec, 10% duty cycle max)
Storage Temp.
Storage Temp.
Lead Temp. (10 sec.)
Power Dissipation
Derates above +70°C
Rating
+44V
+25V
-2V to (V+ + 2V) or 20mA, whichever occurs first
30mA
20mA
40mA
-65°C to +150°C
-65°C to +150°C
+300°C
762mW
9.52mW/°C
Note 1:
Signals on S_, D_, or IN_ exceeding V+ or V- will be clamped by internal diodes. Limit forward
diode current to maximum current ratings.
II. Manufacturing Information
A. Description/Function:
Monolithic CMOS Analog Multiplexer
B. Process:
MV6 (Medium voltage 6 micron metal gate CMOS)
C. Number of Device Transistors:
152
D. Fabrication Location:
California, USA
E. Assembly Location:
Philippines or Malaysia
F. Date of Initial Production:
December, 1990
III. Packaging Information
A. Package Type:
16 Lead Wide SO
B. Lead Frame:
Copper
C. Lead Finish:
Solder Plate
D. Die Attach:
Silver-filled Epoxy
E. Bondwire:
Gold (1.3 mil dia.)
F. Mold Material:
Epoxy with silica filler
G. Assembly Diagram:
Buildsheet # 05-0301-0311
H. Flammability Rating:
Class UL94-V0
I.
Classification of Moisture Sensitivity
per JEDEC standard JESD22-A112: Level 1
IV. Die Information
A. Dimensions:
93 x 119 mils
B. Passivation:
Si3N4/SiO2 (Silicon nitride/ Silicon dioxide)
C. Interconnect:
Aluminum/Si (Si = 1%)
D. Backside Metallization:
None
E. Minimum Metal Width:
6 microns (as drawn)
F. Minimum Metal Spacing:
6 microns (as drawn)
G. Bondpad Dimensions:
5 mil. Sq.
H. Isolation Dielectric:
SiO2
I. Die Separation Method:
Wafer Saw
V. Quality Assurance Information
A. Quality Assurance Contacts: Jim Pedicord (Manager, Rel Operations)
Bryan Preeshl (Executive Director of QA)
Kenneth Huening (Vice President)
B. Outgoing Inspection Level: 0.1% for all electrical parameters guaranteed by the Datasheet.
0.1% For all Visual Defects.
C. Observed Outgoing Defect Rate: < 50 ppm
D. Sampling Plan: Mil-Std-105D
VI. Reliability Evaluation
A. Accelerated Life Test
The results of the 135°C biased (static) life test are shown in Table 1. Using these results, the Failure Rate
(λ) is calculated as follows:
λ=
1
=
MTTF
1.83
(Chi square value for MTTF upper limit)
192 x 4389 x 400 x 2
Temperature Acceleration factor assuming an activation energy of 0.8eV
λ = 2.71 x 10-9
λ = 2.71 F.I.T. (60% confidence level @ 25°C)
This low failure rate represents data collected from Maxim’s reliability monitor program. In addition to
routine production Burn-In, Maxim pulls a sample from every fabrication process three times per week and subjects
it to an extended Burn-In prior to shipment to ensure its reliability. The reliability control level for each lot to be
shipped as standard product si 59 F.I.T. at a 60% confidence level, which equates to 3 failures in an 80 piece
sample. Maxim performs failure analysis on any lot that exceeds this reliability control level. Attached Burn-In
Schematic (Spec. # 06-4529) shows the static Burn-In circuit. Maxim also performs quarterly 1000 hour life test
monitors. This data is published in the Product Reliability Report (RR-1M).
B. Moisture Resistance Tests
Maxim pulls pressure pot samples from every assembly process three times per week. Each lot sample
must meet an LTPD = 20 or less before shipment as standard product. Additionally, the industry standard
85°C/85%RH testing is done per generic device/package family once a quarter.
C. E.S.D. and Latch-Up Testing
The AG41-1 die type has been found to have all pins able to withstand a transient pulse of ± 600V, per MilStd-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device
withstands a current of ±250mA.
Table 1
Reliability Evaluation Test Results
DG508AxWE
TEST ITEM
TEST CONDITION
Static Life Test (Note 1)
Ta = 135°C
Biased
Time = 192 hrs.
FAILURE
IDENTIFICATION
SAMPLE
SIZE
NUMBER OF
FAILURES
DC Parameters
& functionality
400
0
Moisture Testing
Pressure Pot
Ta = 121°C
P = 15 psi.
RH= 100%
Time = 96hrs.
DC Parameters
& functionality
77
0
85/85
Ta = 85°C
RH = 85%
Biased
Time = 1000hrs.
DC Parameters
& functionality
(generic test vehicle)
77
0
-65°C/150°C
1000 Cycles
Method 1010
DC Parameters
(generic test vehicle)
77
Mechanical Stress
Temperature
Cycle
0
Note 1: Life Test Data may represent plastic D.I.P. qualification lots for the Small Outline package.
Attachment #1
TABLE II. Pin combination to be tested. 1/ 2/
Terminal A
(Each pin individually
connected to terminal A
with the other floating)
Terminal B
(The common combination
of all like-named pins
connected to terminal B)
1.
All pins except VPS1 3/
All VPS1 pins
2.
All input and output pins
All other input-output pins
1/ Table II is restated in narrative form in 3.4 below.
2/ No connects are not to be tested.
3/ Repeat pin combination I for each named Power supply and for ground
(e.g., where VPS1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc).
3.4
Pin combinations to be tested.
a.
Each pin individually connected to terminal A with respect to the device ground pin(s) connected to terminal
B. All pins except the one being tested and the ground pin(s) shall be open.
b.
Each pin individually connected to terminal A with respect to each different set of a combination of all
named power supply pins (e.g., VSS1, or VSS2 or VSS3 or VCC1, or VCC2) connected to terminal B. All pins
except the one being tested and the power supply pin or set of pins shall be open.
c.
Each input and each output individually connected to terminal A with respect to a
combination of all the other input and output pins connected to terminal B. All pins except the input or
output pin being tested and the combination of all the other input and output pins shall be open.
TERMINAL C
R1
R2
S1
TERMINAL A
REGULATED
HIGH VOLTAGE
SUPPLY
S2
C1
DUT
SOCKET
SHORT
TERMINAL B
TERMINAL D
Mil Std 883D
Method 3015.7
Notice 8
R = 1.5kΩ
C = 100pf
CURRENT
PROBE
(NOTE 6)
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