Cyclone IV Schematic Review Worksheet

Cyclone IV Schematic Review Worksheet
<Project Name> <Date>
Cyclone® IV Device Schematic Review Worksheet
This document is intended to help you review your schematic and compare the pin usage against the Cyclone IV Device Family Pin Connection
Guidelines (PDF) version 1.5 and other referenced literature for this device family. The technical content is divided into focus areas such as FPGA
power supplies, configuration, transceivers, FPGA I/O, and external memory interfaces.
Within each focus area, there is a table that contains the voltage or pin name for all of the dedicated and dual purpose pins for the device family.
In some cases, the device density and package combination may not include some of the pins shown in this worksheet, you should cross
reference with the pin-out file for your specific device. Links to the device pin-out files are provided at the top of each section.
Before you begin using this worksheet to review your schematic and commit to board layout, Altera highly recommends:
1) Review the latest version of the Cyclone IV Device Errata Sheet (no errata exists at the time this document was published) and the Knowledge
Database for Cyclone IV Device Known Issues and Cyclone IV Device Handbook Known Issues.
2) Compile your design in the Quartus® II software to completion.
For example, there are many I/O related placement restrictions and VCCIO requirements for the I/O standards used in the device. If you do not
have a complete project, then at a minimum a top level project should be used with all I/O pins defined, placed, and apply all of the configurable
options that you plan to use. All I/O related megafunctions should also be included in the minimal project, including, but not limited to, external
memory interfaces, PLLs, altlvds, altgx, and altddio. The I/O Analysis tool in the Pin Planner can then be used on the minimal project to validate
the pinout in the Quartus II software to assure there are no conflicts with the device rules and guidelines.
When using the I/O Analysis tool you must ensure there are no errors with your pinout. Additionally, you should check all warning and critical
warning messages to evaluate their impact on your design. You can right click your mouse over any warning or critical warning message and
select “Help”. This will bring open a new Help window with further information on the cause of the warning, and the action that is required.
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For example, the following warning is generated when a PLL is driven by a global network where the source is a valid dedicated clock input pin,
but the pin is not one dedicated to the particular PLL:
Warning: PLL "<PLL Instance Name>" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by
a non-dedicated input
Info: Input port INCLK[0] of node "<PLL Instance Name>" is driven by clock~clkctrl which is OUTCLK output port of Clock Control Block
type node clock~clkctrl
The help file provides the following:
CAUSE:
ACTION:
The specified PLL's input clock is not driven by a dedicated input pin. As a result, the input clock delay will not be fully compensated
by the PLL. Additionally, jitter performance depends on the switching rate of other design elements. This can also occur if a global
signal assignment is applied to the clock input pin, which forces the clock to use the non-dedicated global clock network.
If you want compensation of the specified input clock or better jitter performance, connect the input clock only to an input pin, or
assign the input pin only to a dedicated input clock location for the PLL. If you do not want compensation of the specified input clock,
then set the PLL to No Compensation mode.
When assigning the input pin to the proper dedicated clock pin location, refer to Clock Networks and PLLs in Cyclone IV Devices (PDF) for the
proper port mapping of dedicated clock input pins to PLLs.
There are many reports available for use after a successful compilation or I/O analysis. For example, you can use the “All Package Pins” and “I/O
Bank Usage” reports within the Compilation – Fitter – Resource Section to see all of the I/O standards and I/O configurable options that are
assigned to all of the pins in your design, as well as view the required VCCIO for each I/O bank. These reports must match your schematic pin
connections.
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The review table has the following heading:
Plane/Signal
Schematic Name
Connection Guidelines
Comments / Issues
The first column (Plane/Signal) lists the FPGA voltage or signal pin name. You should only edit this column to remove dedicated or dual purpose
pin names that are not available for your device density and package option.
The second column (Schematic Name) is for you to enter your schematic name(s) for the signal(s) or plane connected to the FPGA pin(s).
The third column (Connection Guidelines) should be considered “read only” as this contains Altera’s recommended connection guidelines for the
voltage plane or signal.
The fourth column (Comments/Issues) is an area provided as a “notepad” for you to comment on any deviations from the connection guidelines,
and to verify guidelines are met. In many cases there are notes that provide further information and detail that compliment the connection
guidelines.
Here is an example of how the worksheet can be used:
Plane/Signal
<Plane / Signal name
provided by Altera>
VCCINT
Schematic Name
<user entered text>
+1.2V
Connection Guidelines
<Device Specific Guidelines provided by
Altera>
Comments / Issues
<user entered text>
Connected to +1.2V plane, no isolation
is necessary.
Missing low and medium range
decoupling, check PDN.
See Notes (1-1) (1-2) (1-3) (1-6) (1-7).
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Legal Note:
PLEASE REVIEW THE FOLLOWING TERMS AND CONDITIONS CAREFULLY BEFORE USING THIS SCHEMATIC REVIEW WORKSHEET
(“WORKSHEET”) PROVIDED TO YOU. BY USING THIS WORKSHEET, YOU INDICATE YOUR ACCEPTANCE OF SUCH TERMS AND
CONDITIONS, WHICH CONSTITUTE THE LICENSE AGREEMENT ("AGREEMENT") BETWEEN YOU AND ALTERA CORPORATION OR ITS
APPLICABLE SUBSIDIARIES ("ALTERA").
1. Subject to the terms and conditions of this Agreement, Altera grants to you, for no additional fee, a non-exclusive and non-transferable right to
use this Worksheet for the sole purpose of verifying the validity of the pin connections of an Altera programmable logic device-based design. You
may not use this Worksheet for any other purpose. There are no implied licenses granted under this Agreement, and all rights, except for those
granted under this Agreement, remain with Altera.
2. Altera does not guarantee or imply the reliability, or serviceability, of this Worksheet or other items provided as part of this Worksheet. This
Worksheet is provided 'AS IS'. ALTERA DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. ALTERA HAS NO OBLIGATION TO PROVIDE
YOU WITH ANY SUPPORT OR MAINTENANCE.
3. In no event shall the aggregate liability of Altera relating to this Agreement or the subject matter hereof under any legal theory (whether in tort,
contract, or otherwise), exceed One Hundred US Dollars (US$100.00). In no event shall Altera be liable for any lost revenue, lost profits, or other
consequential, indirect, or special damages caused by your use of this Worksheet even if advised of the possibility of such damages.
4. This Agreement may be terminated by either party for any reason at any time upon 30-days’ prior written notice. This Agreement shall be
governed by the laws of the State of California, without regard to conflict of law or choice of law principles. You agree to submit to the exclusive
jurisdiction of the courts in the County of Santa Clara, State of California for the resolution of any dispute or claim arising out of or relating to this
Agreement. The parties hereby agree that the party who is not the substantially prevailing party with respect to a dispute, claim, or controversy
relating to this Agreement shall pay the costs actually incurred by the substantially prevailing party in relation to such dispute, claim, or
controversy, including attorneys' fees. Failure to enforce any term or condition of this Agreement shall not be deemed a waiver of the right to later
enforce such term or condition or any other term or condition of the Agreement.
BY USING THIS WORKSHEET, YOU ACKNOWLEDGE THAT YOU HAVE READ THIS AGREEMENT, UNDERSTAND IT, AND AGREE TO BE
BOUND BY ITS TERMS AND CONDITIONS. YOU AND ALTERA FURTHER AGREE THAT IT IS THE COMPLETE AND EXCLUSIVE
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ORAL OR WRITTEN, AND ANY OTHER COMMUNICATIONS BETWEEN YOU AND ALTERA RELATING TO THE SUBJECT MATTER OF THIS
AGREEMENT.
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Index
Section I:
Section II:
Section III:
Section IV:
a:
b:
c:
Section V:
a:
b:
Section VI:
Power
Configuration
Transceiver
I/O
Clock Pins
Dedicated and Dual Purpose Pins
Dual Purpose Differential I/O pins
External Memory Interface Pins
DDR/2 Interface Pins
DDR/2 Termination Guidelines
Document Revision History
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Section I: Power
Cyclone IV Recommended Reference Literature/Tool List
Cyclone IV Pin Out Files
Cyclone IV Device Family Pin Connection Guidelines (PDF)
Cyclone III and Cyclone IV PowerPlay Early Power Estimator
Cyclone III and Cyclone IV PowerPlay Early Power Estimator User Guide (PDF)
Power Delivery Network (PDN) Tool For Arria® V, Stratix® V, Cyclone IV, and Arria II GZ Devices
Device-Specific Power Delivery Network (PDN) Tool User Guide (PDF)
PowerPlay Power Analyzer Support Resources
AN 592: Cyclone IV Design Guidelines (PDF)
AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs (PDF)
AN 597: Getting Started Flow for Board Designs (PDF)
Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)
Index
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Plane/Signal
VCCINT
Schematic Name
Connection Guidelines
These are internal logic array voltage supply
pins.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
In Cyclone IV GX devices, all VCCINT pins
must be connected to a 1.2V supply. VCCINT
can be shared with VCCD_PLL and
VCCL_GXB with proper isolation filters.
See Notes (1-1) (1-2) (1-3) (1-6) (1-7).
In Cyclone IV E devices, all VCCINT pins
must be connected to either a 1.0V supply or
a 1.2 V supply. VCCINT can be shared with
VCCD_PLL with a proper isolation filter.
Decoupling depends on the design decoupling
requirements of the specific board.
Index Top of Section
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Plane/Signal
VCCD_PLL
(Cyclone IV GX)
Schematic Name
VCCD_PLL[1..4]
(Cyclone IV E)
Connection Guidelines
Digital power for PLLs [1..8] in Cyclone IV GX
devices. Digital power for PLLs [1..4] in
Cyclone IV E devices. These pins must be
connected to power even if the PLLs are not
used.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Notes (1-1) (1-2) (1-3) (1-5) (1-6)
(1-7).
In Cyclone IV GX devices, these pins must be
connected to a 1.2V supply.
With a proper isolation filter these pins can be
sourced from the same regulator as VCCINT
and VCCL_GXB. Use an isolated switching
power supply with a +/- 3% maximum voltage
ripple.
In Cyclone IV E devices, these pins must be
connected to either a 1.0V supply (for 1.0V
VCCINT) or a 1.2V supply (for 1.2V VCCINT).
With a proper isolation filter these pins can be
sourced from the same regulator as VCCINT.
Use an isolated switching power supply with ±
3 % maximum voltage ripple.
Decoupling depends on the design decoupling
requirements of the specific board.
Index Top of Section
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Plane/Signal
VCCA
(Cyclone IV GX)
Schematic Name
VCCA[1..4]
(Cyclone IV E)
Connection Guidelines
Analog power for PLLs [1..8] in Cyclone IV GX
devices. Analog power for PLLs [1..4] in
Cyclone IV E devices. All VCCA pins must be
powered and must be powered up and
powered down at the same time, even if some
or all of the PLLs are not used.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Notes (1-1) (1-2) (1-4) (1-5) (1-6)
(1-7).
Connect these pins to 2.5 V, even if the PLL is
not used. Use an isolated linear or switching
power supply with +/- 3% maximum voltage
ripple.
In Cyclone IV GX devices, these pins can
share the same regulator as VCCA_GXB and
VCCH_GXB with a proper isolation filter.
Isolate VCCA pins from other power pins for
better jitter performance.
Decoupling depends on the design decoupling
requirements of the specific board.
Index Top of Section
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Plane/Signal
VCCIO[3..9]
(Cyclone IV GX)
Schematic Name
VCCIO[1..8]
(Cyclone IV E)
Connection Guidelines
In Cyclone IV GX devices, connect VCCIO
pins on banks 4, 5, 6, 7, and 8 to any of the
following voltages: 1.2V, 1.5V, 1.8V, 2.5V,
3.0V, or 3.3V depending on the I/O standard
assigned to the I/O bank. VCCIO on banks 3
and 9 can be connected to 1.5V, 1.8V, 2.5V,
3.0V, or 3.3V.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Notes (1-1) (1-2) (1-6) (1-7).
I/O banks 3, 8, and 9 contain configuration
pins. If FPP configuration is used, connect
VCCIO of banks 3, 8, and 9 to the same
voltage level.
When these pins require 2.5V, they can share
VCCH_GXB, VCCA_GXB, VCCA, and / or
VCC_CLKIN with a common 2.5V supply with
proper isolation filters.
In Cyclone IV E devices, connect these pins
to 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V
supplies, depending on the I/O standard
assigned to the I/O bank.
Decoupling depends on the design decoupling
requirements of the specific board.
Index Top of Section
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Plane/Signal
VCC_CLKIN[3,8]
(Cyclone IV GX)
Schematic Name
Connection Guidelines
Differential clock input power supply for I/O
banks 3 and 8.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
VCC_CLKIN must be set to 2.5V if the CLKIN
is used as a transceiver refclk.
See Notes (1-1) (1-6) (1-7).
EP4CGX30 and smaller densities have
VCC_CLKIN on banks 3A and 8A that support
1.2V, 1.5V, 1.8V, 2.5V, 3.0V, and 3.3V.
EP4CGX50 and larger densities have
VCC_CLKIN on banks 3A, 3B, 8A, and 8B
that support 1.2V, 1.5V, 1.8V, 2.5V, 3.0V, and
3.3V.
These pins can be tied to the same 2.5V
plane as VCCA, but only when VCC_CLKIN
requires 2.5V.
Decoupling depends on the design decoupling
requirements of the specific board.
Index Top of Section
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Plane/Signal
VREFB[3..8]N[0..2]
(Cyclone IV GX)
Schematic Name
VREFB[1..8]N[0..2]
(Cyclone IV E)
(Not all pins are
available in each
device / package
combination)
Connection Guidelines
Input reference voltage for each I/O bank. If a
bank uses a voltage-referenced I/O standard,
then these pins are used as the voltagereference pins for the bank. When used for
input reference voltage functions, all of the
used VREF pins within a bank are shorted
together and must be connected to the same
voltage.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Note (1-1).
If voltage reference I/O standards are not
used in the bank, the VREF pins are available
as user I/O pins. The pin capacitance is
higher on VREF pins than regular I/O pins,
thus you should avoid placing fast edge rate
signals such as clocks on these pins, and
avoid using these pins in buses since the I/O
timing will not be consistent with the rest of
the bus.
If VREF pins are not used, designers should
connect them to either the VCCIO in the bank
in which the pin resides or GND. Ensure the
reserve unused pin option used in Quartus II
software for these pins do not conflict with the
board connection.
In Cyclone IV GX devices, there are dualpurpose I/O pins in bank 9. If input pins with
VREF I/O standards are used on these dualpurpose I/O pins during user mode, it will
share the VREF pin in bank 8.
Decoupling depends on the design decoupling
requirements of the specific board.
Index Top of Section
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Plane/Signal
GND
Schematic Name
GNDA[1..4]
(Cyclone IV E)
Connection Guidelines
Device ground pins. All GND pins must be
connected to the board GND plane.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
For the 144 pin EQFP package, the exposed
ground pad at the bottom of the package is
used for electrical connectivity and must be
connected to GND.
See Notes (1-1) (1-2) (1-6).
Ground pins for PLL[1..4] and other analog
circuitry in Cyclone IV E devices.
Verify Guidelines have been met or list
required actions for compliance.
The designer can consider connecting the
GNDA pins to the GND plane without isolating
the analog ground plane on the board
provided the digital GND plane(s) are stable,
quiet, and with no ground bounce effect.
See Notes (1-1) (1-2) (1-6).
Index Top of Section
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Notes:
1-1. Capacitance values for the power supply should be selected after consideration of the amount of power they need to supply over the
operating frequency of the circuit being decoupled. A target impedance for the power plane should be calculated based on current draw and
voltage ripple requirements of the plane. The power plane should then be decoupled using the appropriate number of capacitors to achieve this
impedance.
On-board capacitors do not decouple higher than approximately 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages.
Proper board design techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling. To
assist in decoupling analysis, Altera's Power Delivery Network (PDN) Tool For Arria V, Stratix V, Cyclone IV, and Arria II GZ Devices serves as an
excellent decoupling analysis tool.
1-2. This worksheet does not include power estimation for the different power supplies provided. Ensure each power supply is adequate for the
device current requirements. Refer to Altera’s Early Power Estimation Tools and PowerPlay Power Analyzer Support Resources for further
guidance.
Use Altera’s Early Power Estimation Tools to ensure the junction temperature of the device is within operating specifications based on your design
activity.
1-3. There are two variants of Cyclone IV E devices; one powered with a core voltage VCCINT of 1.0V, and the other powered with a core voltage
VCCINT of 1.2V. Each variant has different ordering codes.
1-4. These supplies may share power planes across multiple Cyclone IV devices.
1-5. Use separate power islands for the VCCA pins and the VCCD_PLL pins. The PLL power supplies may originate from other planes on the
board, but must be isolated using ferrite beads or other equivalent methods. If using ferrite beads, choose an 0402 package with low DC
resistance, higher current rating than the maximum steady state current for the supply is connected to (VCCA or VCCD_PLL), and high
impedance at 100MHz. Refer to AN583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs (PDF) for further guidance.
1-6. Altera highly recommends using an independent PCB via for each independent power or ground ball on the package. Sharing power or
ground pin vias on the PCB could lead to noise coupling into the device and result in reduced jitter performance.
1-7. Refer to the Cyclone IV Device Family Pin Connection Guidelines (PDF) for examples on power supply sharing guidelines.
Index Top of Section
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Reviewed against Cyclone IV Device Family Errata Sheet (PDF) version:
Additional Comments:
Index Top of Section
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Section II: Configuration
Cyclone IV Recommended Reference Literature/Tool List
Cyclone IV Pin Out Files
Cyclone IV Device Family Pin Connection Guidelines (PDF)
Configuration, and Remote System Upgrades in Cyclone IV Devices (PDF)
JTAG Boundary-Scan Testing in Cyclone IV Devices (PDF)
USB-Blaster Download Cable User Guide (PDF)
ByteBlaster II Download Cable User Guide (PDF)
AN 597: Getting Started Flow for Board Designs (PDF)
Index
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Configuration Scheme
Plane/Signal
Configuration Voltage
Schematic Name
MSEL[0:3]
Connection Guidelines
Comments / Issues
Configuration input pins that set the Cyclone
IV device configuration scheme. The
EP4CGX15, EP4CGX22, and EP4CGX30
(F324, F169 package) do not have the
MSEL[3] pin and do not support FPP
configuration. The E144 and F256 package in
the Cyclone IV E devices do not have the
MSEL[3] pin and do not support the AS Fast
POR configuration scheme at the 3.0V or
2.5V configuration voltage standard, or the AP
configuration scheme.
Verify Guidelines have been met or list
required actions for compliance.
These pins are internally connected through a
9-KΩ resistor to GND. Do not leave these pins
floating. When these pins are unused,
connect them to GND. Depending on the
configuration scheme used, these pins should
be tied to VCCA or GND either directly or
through 0-Ω resistors.
If only JTAG configuration is used, connect
these pins to GND.
Refer to Configuration and Remote System
Upgrades in Cyclone IV Devices (PDF) for
more information.
Index Top of Section
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Plane/Signal
Schematic Name
Connection Guidelines
Comments / Issues
nCE
In a multi-device configuration, nCE of the first
device is tied low while its nCEO pin drives
the nCE of the next device in the chain. In
single device configuration and JTAG
programming, nCE should be connected to
GND.
Verify Guidelines have been met or list
required actions for compliance.
nCONFIG
If you are using PS configuration scheme with
a download cable, connect this pin through a
10-KΩ resistor to VCCA.
Verify Guidelines have been met or list
required actions for compliance.
For other configuration schemes, if this pin is
not used, this pin must be connected directly
or through a 10-KΩ resistor to VCCIO.
CONF_DONE
This pin is not available as a user I/O pin.
CONF_DONE should be pulled high by an
external 10-KΩ pull-up resistor.
Verify Guidelines have been met or list
required actions for compliance.
When using a Passive configuration scheme
this pin should also be monitored by the
configuration device or controller.
Index Top of Section
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Plane/Signal
Schematic Name
nCEO
Connection Guidelines
Comments / Issues
When not using this pin, you can leave it
unconnected.
Verify Guidelines have been met or list
required actions for compliance.
During multi-device configuration, this pin
feeds the nCE pin of a subsequent device. In
this case, tie the 10-KΩ pull-up resistor to an
acceptable voltage for all devices in the chain
which satisfies the input voltage of the
receiving device.
During single device configuration, this pin
can be used as a regular I/O.
This pin is not available for regular I/O usage
in multi-device configuration mode, see
rd04132011_29.
nSTATUS
This pin is not available as a user I/O pin.
nSTATUS should be pulled high by an
external 10-KΩ pull-up resistor.
Verify Guidelines have been met or list
required actions for compliance.
When using a Passive configuration scheme
this pin should also be monitored by the
configuration device or controller.
Index Top of Section
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Plane/Signal
Schematic Name
TCK
Connection Guidelines
Comments / Issues
Connect this pin to a 1-KΩ pull-down resistor
to GND.
Verify Guidelines have been met or list
required actions for compliance.
Treat this signal like a clock and follow typical
clock routing guidelines.
TMS
TDI
TDO
Connect this pin to a 1-KΩ to 10-KΩ pull-up
resistor to VCCA.
Verify Guidelines have been met or list
required actions for compliance.
To disable the JTAG circuitry, connect TMS to
VCCA.
See Notes (2-1) (2-2).
Connect this pin to a 1-KΩ to 10-KΩ pull-up
resistor to VCCA.
Verify Guidelines have been met or list
required actions for compliance.
To disable the JTAG circuitry, connect TDI to
VCCA.
See Notes (2-1) (2-2).
If the TDO pin is not used, leave this pin
unconnected.
Verify Guidelines have been met or list
required actions for compliance.
Index Top of Section
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Optional Dual Purpose
Pins
Plane/Signal
Schematic Name
Connection Guidelines
Comments / Issues
nCSO
(Cyclone IV GX)
This pin functions as nCSO in AS mode and
as FLASH_nCE in AP mode.
Verify Guidelines have been met or
list required actions for compliance.
nCSO, FLASH_nCE
(Cyclone IV E)
When not programming the device in AS
mode, nCSO is not used. When not
programming the device in AP mode,
FLASH_nCE is not used.
See Note (2-3).
If the pin is not used as an I/O, you should
leave the pin unconnected.
ASDO, DATA1
This pin functions as ASDO in AS mode, and
as DATA1 in PS and FPP modes.
Verify Guidelines have been met or
list required actions for compliance.
When not programming the device in AS
mode, this pin is available as a user I/O pin. If
the pin is not used as an I/O, then you should
leave the pin unconnected.
DATA[2:7]
When not programming the device in AS
mode, these pins are available as a user I/O
pins. If these pins are not used as I/Os, you
should leave them unconnected.
Verify Guidelines have been met or
list required actions for compliance.
DATA[8:15]
(Cyclone IV E)
When not programming the device in AP
mode, these pins are available as user I/O
pins. If these pins are not used as I/Os, you
should leave them unconnected.
Verify Guidelines have been met or
list required actions for compliance.
See Note (2-3).
Index Top of Section
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Plane/Signal
Schematic Name
PADD[0..23]
(Cyclone IV E)
nRESET
(Cyclone IV E)
nAVD
(Cyclone IV E)
nOE
(Cyclone IV E)
nWE
(Cyclone IV E)
Connection Guidelines
Comments / Issues
When not programming the device in AP
mode, these pins are available as user I/O
pins. If these pins are not used as I/Os, you
should leave them unconnected.
Verify Guidelines have been met or
list required actions for compliance.
When not programming the device in AP
mode, nRESET is not used and is available
as a user I/O pin. If these pins are not used as
I/Os, you should leave them unconnected.
Verify Guidelines have been met or
list required actions for compliance.
When not programming the device in AP
mode, nAVD is not used and is available as a
user I/O pin. If these pins are not used as
I/Os, you should leave them unconnected.
Verify Guidelines have been met or
list required actions for compliance.
When not programming the device in AP
mode, nOE is not used and is available as a
user I/O pin. If these pins are not used as
I/Os, you should leave them unconnected.
Verify Guidelines have been met or
list required actions for compliance.
When not programming the device in AP
mode, nWE is not used and is available as a
user I/O pin. If these pins are not used as
I/Os, you should leave them unconnected.
Verify Guidelines have been met or
list required actions for compliance.
See Note (2-3).
See Note (2-3).
See Note (2-3).
See Note (2-3).
See Note (2-3).
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 22 of 54
<Project Name> <Date>
Plane/Signal
Schematic Name
DCLK
Connection Guidelines
Comments / Issues
Dedicated configuration clock pin. In PS and
FPP configuration, DCLK is used to clock
configuration data from an external source
into the FPGA. In AS and AP modes, DCLK
is an output from the FPGA that provides
timing for the configuration interface.
Verify Guidelines have been met or
list required actions for compliance.
See Note (2-3).
Do not leave this pin floating. Drive this pin
either high or low.
You can configure DCLK as a user I/O only
after active serial configuration.
CRC_ERROR
Active high signal that indicates that the error
detection circuit has detected errors in the
configuration SRAM bits.
Verify Guidelines have been met or
list required actions for compliance.
See Notes (2-4) (2-5).
When using this pin, connect it to an external
10-KΩ pull-up resistor to an acceptable
voltage for all devices in the chain that
satisfies the input voltage of the receiving
device.
When not using CRC error detection, this pin
can be used as regular I/O.
When not using this pin, it can be left floating.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 23 of 54
<Project Name> <Date>
Plane/Signal
Schematic Name
Connection Guidelines
Comments / Issues
DEV_CLRn
When the dedicated input DEV_CLRn is not
used for its dedicated function, and if this pin
is not used as an I/O, tie this pin to GND.
Verify Guidelines have been met or
list required actions for compliance.
DEV_OE
When the dedicated input DEV_OE is not
used for its dedicated function, and if this pin
is not used as an I/O, t tie this pin to GND.
Verify Guidelines have been met or
list required actions for compliance.
DATA0
If you are using a serial configuration device
in AS configuration mode, you must connect a
25-Ω series resistor at the near end of the
serial configuration device for the DATA0 pin.
Verify Guidelines have been met or
list required actions for compliance.
When the dedicated input for DATA0 is not
used and this pin is not used as an I/O pin,
then you should to leave this pin
unconnected.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 24 of 54
<Project Name> <Date>
Plane/Signal
Schematic Name
INIT_DONE
Connection Guidelines
Comments / Issues
When using this pin, connect it to an external
10-KΩ pull-up resistor to an acceptable
voltage for all devices in the chain that
satisfies the input voltage of the receiving
device.
Verify Guidelines have been met or list
required actions for compliance.
When not using this pin, it can be left floating
or tied to GND.
This pin can be used as an I/O pin when not
enabled as INIT_DONE in the Quartus II
software. It cannot be used as a user I/O
after configuration if INIT_DONE is enabled in
the Quartus II software.
CLKUSR
If CLKUSR is not enabled for use as a usersupplied configuration clock, it can be used as
a user I/O pin.
Verify Guidelines have been met or list
required actions for compliance.
If the CLKUSR pin is not used as a
configuration clock input and the pin is not
used as an I/O, then you should connect this
pin to GND.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 25 of 54
<Project Name> <Date>
Plane/Signal
Schematic Name
JTAG Header
Connection Guidelines
Comments / Issues
Power the ByteBlaster II or USB-Blaster
cable’s VCC (pin 4 of the header) with VCCA.
Verify Guidelines have been met or list
required actions for compliance.
For multi-device JTAG chains with different
VCCIO voltages, voltage translators may be
required to meet the I/O voltages for the
devices in the chain and JTAG header.
The ByteBlaster II and USB-Blaster cables do
not support a target supply voltage of 1.2 V.
For the target supply voltage value, refer to
the ByteBlaster II Download Cable User
Guide and the USB-Blaster Download Cable
User Guide.
Notes:
2-1. You must follow specific requirements when interfacing Cyclone IV devices with 2.5V, 3.0V, and 3.3V configuration voltage standards. All I/O
pin input signals must maintain a maximum AC voltage of 4.1V. Refer to Configuration and JTAG Pin I/O Requirements in Configuration and
Remote System Upgrades in Cyclone IV Devices (PDF).
2-2. Connect the pull-up resistor to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin), ByteBlaster II, ByteBlasterMV, or
EthernetBlaster cable. The voltage supply can be connected to the VCCA of the device.
2-3. Configuration in AP mode is only supported in Cyclone IV E devices and not in Cyclone IV GX devices.
2-4. CRC error detection is only supported in Cyclone IV E devices with VCCINT 1.2 V, and not in Cyclone IV E devices with VCCINT 1.0 V.
2-5. There are two variants of Cyclone IV E devices; one powered with a core voltage VCCINT of 1.0V, and the other powered with a core voltage
VCCINT of 1.2V. Each variant has different ordering codes.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 26 of 54
<Project Name> <Date>
Reviewed against Cyclone IV Device Family Errata Sheet (PDF) version:
Additional Comments:
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 27 of 54
<Project Name> <Date>
Section III: Transceiver
(Skip this section for Cyclone IV E device reviews)
Cyclone IV Recommended Reference Literature/Tool List
Cyclone IV Pin Out Files
Cyclone IV Device Family Pin Connection Guidelines (PDF)
Cyclone III and Cyclone IV PowerPlay Early Power Estimator
Cyclone III and Cyclone IV PowerPlay Early Power Estimator User Guide (PDF)
Power Delivery Network (PDN) Tool For Arria V, Stratix V, Cyclone IV, and Arria II GZ Devices
Device-Specific Power Delivery Network (PDN) Tool User Guide (PDF)
AN 592: Cyclone IV Design Guidelines (PDF)
AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs (PDF)
AN 597: Getting Started Flow for Board Designs (PDF)
Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)
Index
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 28 of 54
<Project Name> <Date>
Plane/Signal
Schematic Name
VCCL_GXB
Connection Guidelines
Comments / Issues
Supplies power to the transceiver PMA TX,
PMA RX and clocking.
Verify Guidelines have been met or list
required actions for compliance.
Connect to a 1.2V supply. With a proper
isolation filter these pins can be sourced from
the same regulator as VCCINT and
VCCD_PLL. Use an isolated switching power
supply with +/- 3% maximum voltage ripple.
See Notes (3-1) (3-2) (3-3) (3-6) (3-7)
(3-8).
Decoupling for these pins depends on the
design decoupling requirements of the
specific board design.
VCCH_GXB
Supplies power to the transceiver PMA output
(TX) buffer.
Verify Guidelines have been met or list
required actions for compliance.
Connect to a 2.5V supply. These pins can be
tied to the same 2.5V plane as VCCA_GXB.
Use an isolated linear or switching power
supply with +/- 3% maximum voltage ripple.
See Notes (3-1) (3-2) (3-3) (3-6) (3-7)
(3-8).
These pins may be sourced from the same
regulator as VCCA with a proper isolation
filter.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board design.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 29 of 54
<Project Name> <Date>
Plane/Signal
Schematic Name
VCCA_GXB
Connection Guidelines
Comments / Issues
Supplies power to the transceiver PMA
regulator.
Verify Guidelines have been met or list
required actions for compliance.
Connect to a 2.5V supply. These pins may be
tied to the same 2.5V plane as VCCH_GXB.
Use an isolated linear or switching power
supply with +/- 3% maximum voltage ripple.
See Notes (3-1) (3-2) (3-3) (3-6) (3-7)
(3-8).
These pins may be sourced from the same
regulator as VCCA with a proper isolation
filter.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board design.
RREF0
Reference resistor for transceiver.
This pin must be connected to its own
individual 2.00-KΩ +/- 1% resistor to GND. In
the PCB layout, the trace from this pin to the
resistor needs to be routed so that it avoids
any aggressor signals.
Verify Guidelines have been met or list
required actions for compliance.
See Note (3-8).
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 30 of 54
<Project Name> <Date>
Plane/Signal
Schematic Name
REFCLK[0..5]p/n
(Not all pins are available in
each device / package
combination)
Note, these pins can be used
for non-transceiver clock pins.
Refer to the I/O section for
these clock functions.
Connection Guidelines
Comments / Issues
In Cyclone IV GX devices, these pins are
optional high speed differential reference
clock positive input pins (REFCLKp) and clock
negative input pins (REFCLKn) and should be
AC-coupled if used for this function.
Verify Guidelines have been met or list
required actions for compliance.
See Notes (3-4) (3-5).
Connect all unused REFCLKp pins either
individually to GND through a 10-KΩ resistor
or tie all unused pins together through a single
10-KΩ resistor. Ensure that the trace from the
pins to the resistor(s) is as short as possible.
Connect all unused REFCLKn pins either
individually to GND through a 10-KΩ resistor
or tie all unused pins together through a single
10-KΩ resistor. Ensure that the trace from the
pins to the resistor(s) is as short as possible.
AC coupled REFCLK pins require an off chip
resistor divider (or equivalent) to restore Vcm
and requires off chip termination. Examples
are shown in the Clocking section in Cyclone
IV Transceiver Architecture (PDF).
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 31 of 54
<Project Name> <Date>
Plane/Signal
Schematic Name
GXB_RX[0..7]p/n
(Not all pins are available in
each device / package
combination)
Connection Guidelines
Comments / Issues
High speed positive differential receiver
channels (GXB_RXp) and high speed
negative differential receiver channels
(GXB_RXn).
Verify Guidelines have been met or list
required actions for compliance.
See Notes (3-4) (3-5).
These pins may be AC-coupled or DCcoupled when used.
For PCIe applications using the Hard IP (HIP)
block, assign PCIe link logical channel 0 to
physical channel 0 of the transceiver block.
Check device handbook to see which
transceiver blocks have the HIP blocks.
Connect all unused GXB_RXp pins either
individually to GND through a 10-KΩ resistor
or tie all unused pins together through a single
10-KΩ resistor. Ensure the trace from the
pins to the resistor(s) is as short as possible.
Connect all unused GXB_RXp pins either
individually to GND through a 10-KΩ resistor
or tie all unused pins together through a single
10-KΩ resistor. Ensure the trace from the
pins to the resistor(s) is as short as possible.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 32 of 54
<Project Name> <Date>
Plane/Signal
Schematic Name
GXB_TX[0..7]p/n
(Not all pins are available in
each device / package
combination)
Connection Guidelines
Comments / Issues
High speed positive differential transmitter
channels (GXB_TXp) and high speed
negative differential channels (GXB_TXn).
Verify Guidelines have been met or list
required actions for compliance.
See Note (3-5).
Leave all unused GXB_TXp and GXB_TXn
pins floating.
For PCIe applications using the Hard IP (HIP)
block, assign PCIe link logical channel 0 to
physical channel 0 of the transceiver block.
Check device handbook to see which
transceiver blocks have the HIP blocks.
.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 33 of 54
<Project Name> <Date>
Notes:
3-1. Capacitance values for the power supply should be selected after consideration of the amount of power they need to supply over the
operating frequency of the circuit being decoupled. A target impedance for the power plane should be calculated based on current draw and
voltage ripple requirements of the plane. The power plane should then be decoupled using the appropriate number of capacitors to achieve this
impedance.
On-board capacitors do not decouple higher than approximately 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages.
Proper board design techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling. To
assist in decoupling analysis, Altera's Power Delivery Network (PDN) Tool For Arria V, Stratix V, Cyclone IV, and Arria II GZ Devices serves as an
excellent decoupling analysis tool.
3-2. This worksheet does not include power estimation for the different power supplies provided. Ensure each power supply is adequate for the
device current requirements. Refer to Altera’s Early Power Estimation Tools and PowerPlay Power Analyzer Support Resources for further
guidance.
Use Altera’s Early Power Estimation Tools to ensure the junction temperature of the device is within operating specifications based on your design
activity.
3-3. These supplies may share power planes across multiple Cyclone IV devices.
3-4. For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel. The PCI Express protocol requires the ACcoupling capacitor to be placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.
3-5. The Quartus II *.pin file created after compiling the design project in Quartus II lists unused transceiver or clock input pins as GXB_GND*
(unused GXB_RX, REFCLK), GXB_NC (unused GXB_TX) and GND+ (unused input clocks and PLLs). Verify that any pins listed as such in the
Quartus II *.pin file are connected to the board as indicated in these recommendations.
3-6. Altera highly recommends using an independent PCB via for each independent power or ground ball on the package. Sharing power or
ground pin vias on the PCB could lead to noise coupling into the device and result in reduced jitter performance.
3-7. Refer to the Cyclone IV Device Family Pin Connection Guidelines (PDF) for examples on power supply sharing guidelines.
3-8. If none of the transceivers are used in the Cyclone IV GX devices, then you can tie the transceiver power pins VCCL_GXB, VCCH_GXB, and
VCCA_GXB to GND. All power pins must either be powered up or tied to GND. In addition, you can connect the RREF0 pin directly to GND.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 34 of 54
<Project Name> <Date>
Reviewed against Cyclone IV Device Family Errata Sheet (PDF) version:
Additional Comments:
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 35 of 54
<Project Name> <Date>
Section IV: I/O
Cyclone IV Recommended Reference Literature/Tool List
Cyclone IV Pin Out Files
Cyclone IV Device Family Pin Connection Guidelines (PDF)
AN 447: Interfacing Cyclone III and Cyclone IV Devices with 3.3/3.0/2.5V LVTTL/LVCMOS I/O Systems (PDF)
AN 592: Cyclone IV Design Guidelines (PDF)
AN 597: Getting Started Flow for Board Designs (PDF)
Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)
Index
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 36 of 54
<Project Name> <Date>
Part A: Clock Pins
Plane/Signal
CLK[5,7,9,11,12,14,
17,19,20,22]/
DIFFCLK_[0..9]p,
(Cyclone IV GX)*
Schematic Name
CLK[2,4,6,9,11,13,15],
DIFFCLK_[1..7]p
(Cyclone IV E)
(Not all pins are
available in each device
/ package combination)
*For Cyclone IV GX
devices, some of these
pin functions include
transceiver REFCLK
pins. Refer to the
transceiver section for
these clock functions.
Connection Guidelines
Dedicated global clock input pins that can
also be used for the positive terminal inputs
for differential global clock input or user input
pins.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Notes (4-1) (4-2) (4-3).
Connect unused CLK or DIFFCLK pins to
GND.
Use dedicated clock pins to drive clocks into
the device. These pins can connect to the
device PLLs.
These pins do not support output operations
or the programmable weak pull up resistor.
In Cyclone IV GX devices, the following
dedicated clock pins do not have connectivity
to global resources, but can drive specific
MPLLs and GPLLs. This affects the
EP4CGX30 in the 484 package, and all
EP4CGX50, EP4CGX75, EP4CGX110, and
EP4CGX150 devices:
REFCLK0p/DIFFCLK_0p/CLKIO20
REFCLK1p/DIFFCLK_1p/CLKIO22
REFCLK4p/DIFFCLK_8p/CLKIO17
REFCLK5p/DIFFCLK_9p/CLKIO19
Refer to Clock Networks and PLLs in
Cyclone IV Devices (PDF) for further details.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 37 of 54
<Project Name> <Date>
Plane/Signal
CLK[4,6,8,10,13,15]/
DIFFCLK_[0..9]n,
(Cyclone IV GX)*
Schematic Name
Connection Guidelines
Dedicated global clock input pins that can
also be used for the negative terminal inputs
for differential global clock input or user input
pins.
CLK[1,3,5,7,8,10,12,14],
DIFFCLK_[1..7]n
(Cyclone IV E)
Connect unused CLK or DIFFCLK pins to
GND.
(Not all pins are
available in each device
/ package combination)
Use dedicated clock pins to drive clocks into
the device. These pins can connect to the
device PLLs.
*For Cyclone IV GX
devices, some of these
pin functions include
transceiver REFCLK
pins. Refer to the
transceiver section for
these clock functions.
These pins do not support output operations
or the programmable weak pull up resistor.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Notes (4-1) (4-2) (4-3).
In Cyclone IV GX devices, the following
dedicated clock pins do not have connectivity
to global resources, but can drive specific
MPLLs and GPLLs when used as the
negative terminal for differential clock inputs.
This affects the EP4CGX30 in the 484
package, and all EP4CGX50, EP4CGX75,
EP4CGX110, and EP4CGX150 devices:
REFCLK0n/DIFFCLK_0n
REFCLK1n/DIFFCLK_1n
REFCLK4n/DIFFCLK_8n
REFCLK5n/DIFFCLK_9n
Refer to Clock Networks and PLLs in
Cyclone IV Devices (PDF) for further details.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 38 of 54
<Project Name> <Date>
Plane/Signal
PLL[1..8]_CLKOUTp
(Cyclone IV GX)
Schematic Name
PLL[1..4]_CLKOUTp
(Cyclone IV E)
(Not all pins are
available in each
device / package
combination)
PLL[1..8]_CLKOUTn
(Cyclone IV GX)
PLL[1..4]_CLKOUTn
(Cyclone IV E)
(Not all pins are
available in each
device / package
combination)
Connection Guidelines
Optional positive terminal for external PLL
clock outputs. Each pin can be assigned to
single-ended or differential I/O standards if it
is being driven by a PLL output.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Notes (4-1) (4-4).
When not using this pin as a clock output, this
pin may be used as a user I/O pin.
When not using these pins, connect them as
defined in the Quartus II software. They can
be reserved as inputs tristate with weak pull
up resistor enabled, or as outputs driving
GND.
Optional negative terminal for external PLL
clock outputs. Each pin can be assigned to
single-ended or differential I/O standards if it
is being driven by a PLL output.
Verify Guidelines have been met or list
required actions for compliance.
See Notes (4-1) (4-4).
When not using this pin as a clock output, this
pin may be used as a user I/O pin.
When not using these pins, connect them as
defined in the Quartus II software. They can
be reserved as inputs tristate with weak pull
up resistor enabled, or as outputs driving
GND.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 39 of 54
<Project Name> <Date>
Part B: Dedicated and Dual Purpose Pins
Plane/Signal
Schematic Name
RUP[2..4]
(Cyclone IV GX)
RUP[1..4]
(Cyclone IV E)
Connection Guidelines
Reference pins for on-chip termination (OCT)
block in I/O banks 4, 5, and 7 in Cyclone IV
GX devices, and I/O banks 2, 4, 5, and 7 in
Cyclone IV E devices.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Note (4-1).
The external precision resistor RUP must be
connected to the designated RUP pin within
the same bank when used. The external
precision resistor RDN must be connected to
the designated RDN pin within the same bank
when used. If RUP and RDN are not used,
these pins can function as a regular I/O pins.
RDN[2..4]
(Cyclone IV GX)
RDN[1..4]
(Cyclone IV E)
When using OCT tie RUP pins to the required
bank VCCIO through either a 25-Ω or 50-Ω
resistor, depending on the desired I/O
standard.
When using OCT tie RDN pins to GND
through either a 25-Ω or 50-Ω resistor,
depending on the desired I/O standard.
When the device does not use this dedicated
input for the external precision resistor or as
an I/O, it is recommended that unused RUP
pins be connected to VCCIO of the bank in
which the RUP pin resides or GND and
unused RDN pins be connected to GND.
Ensure the reserve unused pin option used in
Quartus II software for these pins do not
conflict with the board connection.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 40 of 54
<Project Name> <Date>
Plane/Signal
NC
Schematic Name
Connection Guidelines
Do not drive signals into these pins.
When designing for device migration, these
pins may be connected to power, ground, or a
signal trace depending on the pin assignment
of the devices selected for migration.
However, if device migration is not a concern,
leave these pins floating.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Note (4-1).
For further information see Knowledge
Database solution rd03132006_933.
Additional Comments:
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 41 of 54
<Project Name> <Date>
Part C: Dual Purpose Differential I/O pins
Plane/Signal
Schematic Name
DIFFIO_[R,T,B]
[0..72][p,n]
(Cyclone IV GX)
DIFFIO_[L,R,T,B]
[0..61][p,n]
(Cyclone IV E)
(Not all pins are
available in each
device / package
combination)
Connection Guidelines
Dual-purpose differential transmitter/receiver
channels. These channels can be used for
transmitting/receiving LVDS compatible
signals. Pins with a "p" suffix carry the positive
signal for the differential channel. Pins with an
"n" suffix carry the negative signal for the
differential channel.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Note (4-1).
Differential receivers require external
differential termination.
In Cyclone IV GX devices, true differential
outputs are supported only on row I/O banks 5
and 6 on the right side of the device.
In Cyclone IV E devices, true differential
outputs are supported only on row I/O banks
1, 2, 5 and 5 on the left and right sides of the
device.
External resistors are required for the
differential outputs on column (top and
bottom) I/O banks.
If not used for differential signaling, these pins
are available as single ended user I/O pins.
Unused pins can be left unconnected or tied
to GND. If unconnected, use Quartus II
software programmable options to internally
bias these pins. They can be reserved as
inputs tristate with weak pull up resistor
enabled, or as outputs driving GND.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 42 of 54
<Project Name> <Date>
Notes:
4-1. Refer to Knowledge Database solution rd12102002_3281 for further information regarding the concerns when I/O pins are left floating with no
internal or external bias. Ensure there are no conflicts between the Quartus II software device wide default configuration for unused I/Os and the
board level connection. Altera recommends setting unused I/O pins on a project wide basis to behave as inputs tri-state with weak pull up resistor
enabled. Individual unused pins can be reserved with specific behavior such as output driving ground or as output driving VCC to comply with the
PCB level connection.
4-2. The number of dedicated global clocks for each device density is different. Refer to Clock Networks and PLLs in Cyclone IV Devices (PDF)
for device specific resource availability.
4-3. In Cyclone IV GX devices, the number of optional high speed differential reference clock input pins for each device density is different. Refer
to I/O Features in Cyclone IV Devices (PDF) for device specific resource availability.
4-4. The number of PLLs consisting of GPLLs and MPLLs for each device density is different:
EP4CGX15 devices support 3 PLLs.
EP4CGX22 and EP4CGX30 (except F484 package) supports 4 PLLs.
EP4CGX30 in the F484 package and EP4CGX50 and larger Cyclone IV GX densities support 8 PLLs.
EP4CE6 and EP4CE10 devices support 2 PLLs.
EP4CE15 and other larger Cyclone IV E densities support 4 PLLs.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 43 of 54
<Project Name> <Date>
Reviewed against Cyclone IV Device Family Errata Sheet (PDF) version:
Additional Comments:
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 44 of 54
<Project Name> <Date>
Section V: External Memory Interfaces
Cyclone IV Device Literature
Cyclone IV Recommended Reference Literature/Tool List
Cyclone IV Device Family Pin Connection Guidelines (PDF)
Cyclone IV Pin-Outs
Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)
External Memory Interface Literature
External Memory Interfaces in Cyclone IV Devices (PDF)
DDR and DDR2 Literature
Using DDR and DDR2 SDRAM Devices in Cyclone III Devices (PDF)
AN 597: Getting Started Flow for Board Designs (PDF)
Index
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 45 of 54
<Project Name> <Date>
Part A: DDR/2
Interface Pins
Plane/Signal
Data pins - DQ
Schematic Name
Connection Guidelines
Place it on DQ pins of the DQ/DQS group.
The order of the DQ bits within a designated
DQ group/bus is not important; however, use
caution when making pin assignments if you
plan on migrating to a different memory
interface that has a different DQ bus width
(e.g. migrating from x4 to x8). Analyze the
available DQ pins across all pertinent DQS
columns in the pin list.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
Data strobe - DQS
Only Single ended DQS is supported.
Connect the DQS pin to the DQS pin of the
corresponding DQ/DQS group.
Verify Guidelines have been met or list
required actions for compliance.
Data Mask DM
Place it on one of the DQ pins in the group.
DM pins need to be part of the write DQS/DQ
group.
Verify Guidelines have been met or list
required actions for compliance.
mem_clk and
mem_clk_n
Place them on differential I/O pair within the
same back as DQ/DQS pins.
Verify Guidelines have been met or list
required actions for compliance.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 46 of 54
<Project Name> <Date>
Plane/Signal
clock_source
Schematic Name
Connection Guidelines
Input clock pin to the DDR2 core PLLDedicated PLL clock input pin with direct (not
using global clock) connection to the PLL and
DLL required by the interface.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
Address
Any user I/O pin. To minimize skew, you
should place address and command pins in
the same bank or side of the device as the
following pins:
● mem_clk* pins.
● DQ, DQS, or DM pins.
Verify Guidelines have been met or list
required actions for compliance.
Command
Any user I/O pin. To minimize skew, you
should place address and command pins in
the same bank or side of the device as the
following pins:
● mem_clk* pins.
● DQ, DQS, or DM pins.
Verify Guidelines have been met or list
required actions for compliance.
Reset
Dedicated clock input pin. (high fan-out signal)
Verify Guidelines have been met or list
required actions for compliance.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
Page 47 of 54
<Project Name> <Date>
Plane/Signal
RUP[2..4]
(Cyclone IV GX)
Schematic Name
RUP[1..4]
(Cyclone IV E)
RDN[2..4]
(Cyclone IV GX)
RDN[1..4]
(Cyclone IV E)
Connection Guidelines
Used when calibrated OCT for the memory
interface pins is implemented.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
RUP should be in a 1.8V VCCIO bank for
DDR2 and 2.5V VCCIO bank for DDR
interface. Make sure that the VCCIO of your
DDR/2 interface bank and the VCCIO of the
bank with RUP pin match.
If the RUP pin is used for standard non
external memory interfaces, refer to section
“Dedicated and Dual purpose pins” for
connection guidelines.
Used when calibrated OCT for the memory
interface pins is implemented.
Verify Guidelines have been met or list
required actions for compliance.
RDN should be in a 1.8V VCCIO bank for
DDR2 and 2.5V VCCIO bank for DDR
interface. Make sure that the VCCIO of your
DDR/2 interface bank and the VCCIO of the
bank with RDN pin match.
If the RUP pin is used for standard non
external memory interfaces, refer to section
“Dedicated and Dual purpose pins” for
connection guidelines.
Additional Comments:
Index Top of Section
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DS-01011-3.1
Page 48 of 54
<Project Name> <Date>
Part B: DDR/2
Termination
Guidelines
Plane/Signal
Memory clocks @
Memory
Schematic Name
Connection Guidelines
Memory clocks use Unidirectional class I
termination. They are typically differentially
terminated with an effective 100-Ω resistance.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
For DIMM no termination is required as
termination is placed on the DIMM itself.
Memory clocks @
FPGA
Source
<variation_name>_pin_assignments.tcl file to
set appropriate current strengths.
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
DQS @ Memory
For DDR2 use ODT feature. For DDR use
external parallel 50-Ω termination.
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
DQS @FPGA
For FPGA side source
<variation_name>_pin_assignments.tcl file to
set appropriate current strengths.
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
DM @ Memory
For DDR2 use ODT feature. For DDR use
external parallel 50-Ω termination.
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
Index Top of Section
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<Project Name> <Date>
Plane/Signal
DQ @FPGA
Schematic Name
Connection Guidelines
For FPGA side source
<variation_name>_pin_assignments.tcl file to
set appropriate current strengths.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
DQ @ Memory
For DDR2 use ODT feature. . For DDR use
external parallel 50-Ω termination.
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
DM @ FPGA
For FPGA side source
<variation_name>_pin_assignments.tcl file to
set appropriate current strengths.
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
Address [BA,
mem_addr] @ Memory
Unidirectional class I termination. For multiloads Altera recommends the ideal topology is
a balanced symmetrical tree. Altera
recommends that the class I termination to
VTT is placed:
■ At the DIMM connector (for interfaces using
DIMMs).
■ At the first split or division of the
symmetrical tree for discrete devices.
Nonsymmetrical topologies or DIMMs result in
over or undershoot and oscillations on the
line, which may require compensation
capacitors or a lower than ideal drive strength
to be specified resulting in de-rated interface
performance.
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
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<Project Name> <Date>
Plane/Signal
Address [BA,
mem_addr] @ FPGA
Schematic Name
Connection Guidelines
For FPGA side source
<variation_name>_pin_assignments.tcl file to
set appropriate current strengths.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
Command [CKE,
CS_N, RAS, CAS,
WE_N] @ Memory
Command [CKE,
CS_N, RAS, CAS,
WE_N] @ FPGA
Unidirectional class I termination. For multiloads Altera recommends the ideal topology is
a balanced symmetrical tree. Altera
recommends that the class I termination to
VTT is placed:
■ At the DIMM connector (for interfaces using
DIMMs).
■ At the first split or division of the
symmetrical tree for discrete devices.
Nonsymmetrical topologies or DIMMs result in
over or undershoot and oscillations on the
line, which may require compensation
capacitors or a lower than ideal drive strength
to be specified resulting in de-rated interface
performance.
Verify Guidelines have been met or list
required actions for compliance.
For FPGA side source
<variation_name>_pin_assignments.tcl file to
set appropriate current strengths.
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
See Note (5-1).
Notes:
5-1. The termination schemes suggested in the table are general guidelines. You should do board level simulation for your particular system/board
to determine optimal termination scheme.
Index Top of Section
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DS-01011-3.1
Page 51 of 54
<Project Name> <Date>
Miscellaneous
Pin Description
Vref
Schematic Name
Connection Guidelines
Use a voltage regulator to generate this
voltage.
Comments/ Issues
Verify Guidelines have been met or list
required actions for compliance.
Vtt
Use a voltage regulator to generate this
voltage.
See Note (5-2).
Verify Guidelines have been met or list
required actions for compliance.
RUP & RDN
RUP pin is connected to VCCIO (1.8V)
through an external 50-Ω ±1% resistor . RDN
pin is connected to GND through an 50-Ω
±1% resistor.
See Note (5-2).
Verify Guidelines have been met or list
required actions for compliance.
If the RUP and RDN pins are used for
standard non external memory interfaces,
refer to section “Dedicated and Dual purpose
pins” for connection guidelines.
Notes:
5-2. This worksheet does not calculate required decoupling, it is expected the designer will select decoupling based on analysis of power required
and impedance of power path required based on static and switching current values. To assist in decoupling analysis, Altera's Power Delivery
Network (PDN) Tool serves as an excellent decoupling analysis tool.
Capacitance values for the power supply should be selected after consideration of the amount of power they need to supply over the frequency of
operation of the particular circuit being decoupled. A target impedance for the power plane should be calculated based on current draw and
voltage drop requirements of the device/supply. The power plane should then be decoupled using the appropriate number of capacitors. On-board
capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Proper board design
techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling.
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
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<Project Name> <Date>
Reviewed against Cyclone IV Device Family Errata Sheet (PDF) version:
Additional Comments:
Index Top of Section
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
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<Project Name> <Date>
Section VI: Document Revision History
Revision
Description of Changes
Synchronized to Cyclone IV Device Family Pin Connection Guidelines version 1.5
Removed CLK0 for Cyclone IV E devices.
For MSEL[0..3] connection guidelines, removed “except for F484 package and added F329 and F169
packages.
For DCLK connection guideline, added DCLK can be used as user I/O only in active serial
configuration.
Added “All power pins must either be powered up or tied to GND” to note 3-8.
Date
V3.0
Added PLL6 and PLL7 to the Cyclone IV GX PLL[1..8]_CLKOUTp/n signals.
June 2012
V2.1
Added a mandatory comment in all sections for reviewers to identify Errata Sheet version used for the
review.
November 2011
V2.0
Updated VCCD_PLL and VCC_CLKIN connection guidelines.
Added exposed GND pad requirements for the EQFP 144 pin package.
Added note 3-8.
Added REFCLK pin descriptions to the transceiver section.
Updated the GXB_RX and GXB_TX connection guidelines.
Updated the CLK/DIFFCLK pin descriptions and connection guidelines.
Updated the PLL_CLKOUT connection guidelines.
Updated DIFFIO signal names for Cyclone IV GX devices.
Synchronized to the Cyclone IV Device Family Pin Connection Guidelines version 1.4.
July 2011
V1.0
Initial release, based on Cyclone IV Device Family Pin Connection Guidelines version 1.1.
April 2010
V3.1
May 2013
Index
Cyclone IV Schematic Review Worksheet 3.1
DS-01011-3.1
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