16-Bit, 8-Channel Simultaneous Sampling Data Acquisition System ADAS3023 Data Sheet
Data Sheet
FEATURES
Ease-of-use, 16-bit complete data acquisition system
Simultaneous sampling selection of 2, 4, 6, and 8 channels
Differential input voltage range: ±20.48 V maximum
High impedance 8-channel input: >500 MΩ
High input common-mode rejection: 95.0 dB
User-programmable input ranges
On-chip 4.096 V reference and buffer
No latency/pipeline delay (SAR architecture)
Serial 4-wire 1.8 V to 5 V SPI-/SPORT-compatible interface
40-lead LFCSP package (6 mm × 6 mm)
−40°C to +85°C industrial temperature range
APPLICATIONS
Multichannel data acquisition and system monitoring
Process control
Power line monitoring
Automated test equipment
Patient monitoring
Spectrum analysis
Instrumentation
GENERAL DESCRIPTION
The ADAS3023 is a complete 16-bit successive approximationbased analog-to-digital data acquisition system. This device is capable of simultaneously sampling up to 500 kSPS for two channels, 250 kSPS for four channels, 167 kSPS for six channels, and 125 kSPS for eight channels manufactured on the Analog
Devices, Inc., proprietary iCMOS® high voltage industrial process technology.
The ADAS3023 integrates eight channels of low leakage track and hold, a programmable gain instrumentation amplifier
(PGIA) stage with a high common-mode rejection offering four differential input ranges, a precision low drift 4.096 V reference and buffer, and a 16-bit charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC). The
ADAS3023 can resolve differential input ranges of up to ±20.48 V when using ±15 V supplies.
16-Bit, 8-Channel Simultaneous
Sampling Data Acquisition System
ADAS3023
DIFF TO
COM
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
FUNCTIONAL BLOCK DIAGRAM
VDDH AVDD DVDD VIO RESET PD
TRACK
AND
HOLD
PGIA
ADAS3023
VSSH AGND DGND REFx
Figure 1.
LOGIC/
INTERFACE
BUF
PulSAR
ADC
REF
Table 1. Typical Input Range Selection
Input Range, V
IN
0 V to 1 V
0 V to 2.5 V
0 V to 5 V
0 V to 10 V
±1.28 V
±2.56 V
±5.12 V
±10.24 V
1
See Figure 39 and Figure 40 in the Analog Inputs section for more
information.
CNV
BUSY
CS
SCK
DIN
SDO
REFIN
The ADAS3023 simplifies design challenges by eliminating signal buffering, level shifting, amplification and attenuation, common-mode rejection, settling time, or any of the other analog signal conditioning challenges, yet allows for smaller form factor, faster time to market, and lower costs.
The ADAS3023 is factory calibrated and its operation is specified from −40°C to +85°C.
Rev. A
Document Feedback
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Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
ADAS3023
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Timing Specifications .................................................................. 6
Absolute Maximum Ratings ............................................................ 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 19
Overview ...................................................................................... 19
Operation ..................................................................................... 19
Transfer Functions...................................................................... 20
REVISION HISTORY
2/14—Rev. 0 to Rev. A
Changes to Table 2 ............................................................................ 5
Changes to Figure 38 ...................................................................... 21
5/13—Revision 0: Initial Version
Data Sheet
Typical Application Connection Diagram .............................. 21
Analog Inputs ............................................................................. 21
Voltage Reference Input/Output .............................................. 22
Power Supply ............................................................................... 24
Power Dissipation Modes .......................................................... 24
Conversion Modes ..................................................................... 25
Digital Interface .............................................................................. 26
Conversion Control ................................................................... 26
RESET and Power-Down (PD) Inputs .................................... 26
Serial Data Interface ................................................................... 27
General Timing .......................................................................... 28
Configuration Register .............................................................. 29
Packaging and Ordering Information ......................................... 30
Outline Dimensions ................................................................... 30
Ordering Guide .......................................................................... 30
Rev. A | Page 2 of 32
Data Sheet ADAS3023
SPECIFICATIONS
VDDH = 15 V ± 5%, VSSH = −15 V ± 5%, AVDD = DVDD = 5 V ± 5%; VIO = 1.8 V to AVDD, Internal Reference V
REF
= 4.096 V, f
S
=
500 kSPS, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT (IN0 to IN7, COM)
Input Impedance
Operating Input Voltage Range 2
Differential Input Voltage Ranges, V
IN
THROUGHPUT
Conversion Rate
DC ACCURACY
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Transition Noise
Gain Error Match, Delta Mean
Gain Error Temperature Drift
Offset Error Match, Delta Mean
Offset Error Temperature Drift
Signal-to-Noise Ratio
Signal-to-Noise + Distortion (SINAD)
Test Conditions/Comments
Z
V
V
IN
IN
INX
, on any single pin
− COM
PGIA gain = 0.2, V
IN
PGIA gain = 0.4, V
IN
= 40.96 V p-p
= 20.48 V p-p
PGIA gain = 0.8, V
IN
= 10.24 V p-p
PGIA gain = 1.6, V
IN
= 5.12 V p-p
Two channels
Four channels
Six channels
Eight channels
Full-scale step
PGIA gain = 0.2, 0.4, or 0.8, COM = 0 V
PGIA gain = 1.6, COM = 0 V
All PGIA gains, COM = 0 V
PGIA gain = 0.2 or 0.4
PGIA gain = 0.8
PGIA gain = 1.6
External reference, all PGIA gains
External reference, all PGIA gains
External reference, PGIA gain = 0.2, 0.4, or 0.8
External reference, PGIA gain = 1.6
External reference, PGIA gain = 0.2
External reference, PGIA gain = 0.4
External reference, PGIA gain = 0.8
External reference, PGIA gain = 1.6
External reference, PGIA gain = 0.2, 0.4, 0.8, or 1.6 −15
External reference, PGIA gain = 0.2 or 0.4, IN0 to IN7 0
External reference, PGIA gain = 0.8, IN0 to IN7
External reference, PGIA gain = 1.6, IN0 to IN7
0
0
Internal reference
−0.05
−65
−85
−10
0
0
0
0
0
16
−2.5
−3
−0.95
−0.075
Min
16
500
VSSH + 2.5
−5V
REF
−2.5V
REF
−1.25V
REF
−0.625V
REF
Typ Max
Bits
MΩ
VDDH − 2.5 V
+5V
REF
+2.5V
REF
V
V
+1.25V
REF
V
+0.625V
REF
V
±1
±1
−35
−45
0
130
±1
0.5
1.5
2.5
500
250
167
125
820
+2.5
+3
±0.5 +1.25
6
7
10
+0.075
+0.05
1
2
+12
+12
+10
250
+15
2
3
5
%FS ppm/°C ppm/°C
LSB
LSB
LSB
LSB
LSB ppm/°C ppm/°C ppm/°C
LSB
LSB
LSB
LSB
LSB
%FS kSPS kSPS kSPS kSPS ns
Bits f
IN
= 1 kHz, COM = 0 V
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6 f
IN
= 1 kHz, two, four, six, and eight channels
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
90.0
89.5
87.5
85.0
89.5
89.0
87.0
84.0
91.5
91.0
89.0
86.5
91.0
90.5
88.5
86.0 dB dB dB dB dB dB dB dB
Rev. A | Page 3 of 32
ADAS3023
Parameter
Dynamic Range
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
DC Common-Mode Rejection Ratio
(CMRR)
−3 dB Input Bandwidth
INTERNAL REFERENCE
REFx Pins
Output Voltage
Output Current
Temperature Drift
Line Regulation
Internal Reference
Buffer Only
Turn-On Settling Time
EXTERNAL REFERENCE
Voltage Range
Current Drain
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
V
IL
V
IH
I
IL
I
IH
Data Format
V
OL
V
OH
POWER SUPPLIES
VIO
AVDD
DVDD
VDDH
VSSH
Test Conditions/Comments
f
IN
= 1 kHz, −60 dB input
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6 f
IN
= 1 kHz, all PGIA gains f
IN
= 1 kHz, all PGIA gains f
IN
= 1 kHz, all channels inactive
All channels
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
−40 dBFS
T
A
= 25°C
T
A
= 25°C
REFEN bit = 1
REFEN bit = 0, REFIN pin = 2.5V
AVDD = 5 V ± 5%
AVDD = 5 V ± 5%
T
A
= 25°C
C
REFIN
, C
REF1
, C
REF2
= 10 µF||0.1 µF
REFEN bit = 0
REFx input, REFIN = 0 V
REFIN input (buffered) f
S
= 500 kSPS
VIO > 3 V
VIO > 3 V
VIO ≤ 3 V
VIO ≤ 3 V
I
SINK
= +500 µA
I
SOURCE
= −500 µA
VDDH > input voltage + 2.5 V
VSSH < input voltage − 2.5 V
Rev. A | Page 4 of 32
Data Sheet
Min
91.0
90.5
88.0
86.0
Typ Max
92
91.5
89.5
87.0
−100
105
95
95.0
95.0
95.0
95.0
8 dB dB dB dB
MHz
4.088
2.495
±5
±1
20
4.096 4.104
250
4
2.5
100
2.505
4.000
−0.3
0.7 × VIO
−0.3
0.9 × VIO
−1
−1
4.096 4.104
2.5
100
2.505
+0.3 × VIO
VIO + 0.3
+0.1 × VIO
VIO + 0.3
+1
+1
VIO − 0.3
Twos complement
0.4
V
V
V
V
µA
µA
V
V
µA
V
V
1.8
4.75
4.75
14.25
−15.75
5
AVDD + 0.3 V
5.25 V
5
15
5.25
15.75
−15 −14.25
V
V
V
V
µA ppm/°C ppm/°C
μV/V ppm
V ms dB dB dB dB dB
dB dB
Data Sheet ADAS3023
Parameter
I
VDDH
I
VSSH
I
AVDD
I
DVDD
I
VIO
Power Supply Sensitivity
Test Conditions/Comments
Two channels
Four channels
Six channels
Min
Eight channels
PD = 1
Two channels
Four channels
−5.5
−6.5
Six channels
Eight channels
All PGIA gains, PD = 1
All PGIA gains, PD = 0, reference buffer enabled
−10.0
−10.0
All PGIA gains, PD = 0, reference buffer disabled
All PGIA gains, PD = 1
All PGIA gains, PD = 0
All PGIA gains, PD = 1
All PGIA gains, PD = 0, VIO = 3.3 V
All PGIA gains, PD = 1
External reference, T
A
= 25°C
PGIA gain = 0.2 or 0.4, VDDH/VSSH = ±15 V ± 5%
PGIA gain = 0.8, VDDH/VSSH = ±15 V ± 5%
PGIA gain = 1.6, VDDH/VSSH = ±15 V ± 5%
PGIA gain = 0.2 or 0.4, AVDD, DVDD = ±5 V ± 5%
PGIA gain = 0.8, AVDD, DVDD = ±5 V ± 5%
PGIA gain = 1.6, AVDD, DVDD = ±5 V ± 5%
Typ Max
5.0
6.0
9.5
5.5
7.0
10.5
9.5
10.0
10.5
−5.0
−5.5
−8.5
−8.5
10.0
16.0 17.0
100
15.5
2.5 3
100
1.0
10.0
±0.1
±0.2
±0.4
±1.0
±1.5
±2.5
TEMPERATURE RANGE
Specified Performance T
MIN
to T
MAX
−40 +85 °C
1
for the LSB size.
2
Full-scale differential input ranges of ±2.56 V, ±5.12 V, ±10.24 V, and ±20.48 V are set by the configuration register.
3 If using the external multiplexer in front of the ADAS3023 , it must be switched at least 820 ns prior to the rising edge of CNV.
4
5 measured and specified separately.
All ac specifications expressed in decibels are referenced to the full-scale input range (FSR) and are tested with an input signal at 0.5 dB below full scale, unless
6 otherwise specified.
This is the output from the internal band gap reference.
7
There is no pipeline delay. Conversion results are available immediately after a conversion is completed.
LSB
LSB
LSB
LSB
LSB
LSB mA
µA mA
µA mA
µA
mA mA mA mA
µA mA mA mA mA
µA mA
Rev. A | Page 5 of 32
ADAS3023 Data Sheet
TIMING SPECIFICATIONS
VDDH = 15 V ± 5%, VSSH = −15 V ± 5%, AVDD = DVDD = 5 V ± 5%, VIO = 1.8 V to AVDD, Internal Reference V
REF
= 4.096 V, f
S
=
500 kSPS, all specifications T
MIN
to T
MAX
Table 3.
Parameter
TIME BETWEEN CONVERSIONS
Two Channels
Four Channels
Six Channels
Eight Channels
Normal Mode (Default), CMS = 1
Two Channels
Four Channels
Six Channels
Eight Channels
CONVERSION TIME: CNV RISING EDGE TO DATA AVAILABLE
Warp Mode, CMS = 0
Two Channels
Four Channels
Six Channels
Eight Channels
Normal Mode (Default), CMS = 1
Two Channels
Four Channels
Six Channels
Eight Channels
CNV
Pulse Width
CNV High to Hold Time (Aperture Delay)
CNV High to BUSY/SDO2 Delay
SCK
Period
Low Time
High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO > 4.5 V
VIO > 3 V
VIO > 2.7 V
VIO > 2.3 V
VIO > 1.8 V
CS/RESET/PD
CS/RESET/PD Low to SDO D15 MSB Valid
VIO > 4.5 V
VIO > 3 V
VIO > 2.7 V
VIO > 2.3 V
VIO > 1.8 V
CS/RESET/PD High to SDO High Impedance
CNV Rising to CS t
EN t
DIS t
CCS t
CNVH t
AD t
CBD
Symbol
t
CYC t
CONV t
SCK t
SCKL t
SCKH t
SDOH t
SDOV
5
10
Min
8.0
2.1
4.1
2.0
4.0
6.0
6.1
8.1
4 t
SDOV
+ 3
5
5
Typ
2
1485 1630
2850 3340
4215 5000
5580 6700
1575 1720
2940 3430
4305 5090
5670 6790
520
Max
1000
1000
1000
1000
1000
1000
1000
1000
24
25
37
12
18
7
8
10
15
20
25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Unit
µs
µs
µs
µs
µs
µs
µs
µs ns ns ns ns ns ns ns ns ns
Rev. A | Page 6 of 32
Data Sheet
Parameter
DIN
DIN Valid Setup Time from SCK Falling Edge
DIN Valid Hold Time from SCK Falling Edge
Symbol
t
DINS t
DINH
RESET/PD HIGH PULSE t
RH
1
2
See Figure 2 and Figure 3 for load conditions.
Circuit and Voltage Diagrams
I
OL
500µA
Min
4
4
5
Typ
ADAS3023
Max Unit
ns ns ns
TO SDO
C
L
50pF
1.4V
500µA I
OH
Figure 2. Load Circuit for Digital Interface Timing
70% VIO
30% VIO t
DELAY
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2 t
DELAY
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2
1
2V IF VIO > 2.5V; VIO – 0.5V IF VIO < 2.5V.
2
0.8V IF VIO > 2.5V; 0.5V IF VIO < 2.5V.
Figure 3. Voltage Levels for Timing
Rev. A | Page 7 of 32
ADAS3023
Timing Diagrams
SOC
Data Sheet
SOC SOC
POWER
UP
PHASE
CNV t
CONV
CONVERSION (n)
EOC t
CYC
NOTE 1
ACQUISITION (n + 1)
NOTE 2
CONVERSION (n + 1)
EOC
NOTE 1
ACQUISITION (n + 2) t
CNVH
NOTE 4 t
AD
NOTE 3 CS
SCK
DIN
SDO
NOTE 2
1 16 1
CFG (n + 2)
CH0 CH1
16 1 16 1 16 1
CFG (n + 3)
CH0 CH1
16 1 16
CH7 CH7
BUSY/
SDO2 t
CBD
DATA (n) DATA (n + 1)
NOTES
1. DATA ACCESS CAN ONLY OCCUR AFTER CONVERSION. BOTH CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF THE CONVERSION (EOC).
2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED FOR CONVERSION RESULT. AN ADDITIONAL 16 EDGES AFTER THE LAST CONVERSION RESULT ON BUSY READS BACK THE CFG ASSOCIATED
WITH CONVERSION.
3. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS IS SHOWN WITH FULL INDEPENDENT CONTROL.
4. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING INSTANT. A MINIMUM TIME OF AT LEAST THE APERATURE DELAY, t
AD, SHOULD LAPSE PRIOR TO DATA ACCESS.
Figure 4. General Timing Diagram with BUSY/SDO2 Disabled
SOC SOC SOC
EOC t
CYC
EOC t
CONV
POWER
UP
PHASE
CONVERSION (n)
NOTE 1
ACQUISITION (n + 1) CONVERSION (n + 1)
NOTE 1
ACQUISITION (n + 2)
CNV t
CNVH
NOTE 4 t
AD
CS NOTE 3
1 16 1 16 1 16 1 16 1 16 1 16 1 16 1 16
NOTE 2
SCK
DIN
SDO
BUSY/
SDO2
CFG (n + 2)
CH0
CH4
CH1
CH5
CH2
CH6
CH3
CH7
CFG (n + 3)
CH0
CH4
CH1
CH5
CH2
CH6
CH3
CH7
DATA (n)
NOTES
1. DATA ACCESS CAN ONLY OCCUR AFTER CONVERSION. BOTH CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF THE CONVERSION (EOC).
DATA (n + 1)
2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED FOR CONVERSION RESULT. AN ADDITIONAL 16 EDGES AFTER THE LAST CONVERSION RESULT ON BUSY READS BACK THE CFG ASSOCIATED
WITH CONVERSION.
3. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS IS SHOWN WITH FULL INDEPENDENT CONTROL.
4. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING INSTANT. A MINIMUM TIME OF AT LEAST THE APERATURE DELAY, t
AD, SHOULD LAPSE PRIOR TO DATA ACCESS.
Figure 5. General Timing Diagram with BUSY/SDO2 Enabled
Rev. A | Page 8 of 32
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Analog Inputs/Outputs
INx, COM to AGND
REFx to AGND
VSSH − 0.3 V to VDDH + 0.3 V
AGND − 0.3 V to AVDD + 0.3 V
REFIN to AGND
REFN to AGND
Ground Voltage Differences
AGND, RGND, DGND
Supply Voltages
VDDH to AGND
VSSH to AGND
AVDD, DVDD, VIO to AGND
ACAP, DCAP, RCAP to AGND
Digital Inputs/Outputs
CNV, DIN, SCK, RESET, PD, CS to DGND
SDO, BUSY/SDO2 to DGND
Internal Power Dissipation
Junction Temperature
Storage Temperature Range
Thermal Impedance
θ
JA
(LFCSP)
θ
JC
(LFCSP)
AGND − 0.3 V to +2.7 V
±0.3 V
±0.3 V
–0.3 V to +16.5 V
+0.3 V to −16.5 V
−0.3 V to +7 V
−0.3 V to +2.7 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
2 W
125°C
−65°C to +125°C
44.1°C/W
0.28°C/W
ADAS3023
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. A | Page 9 of 32
ADAS3023
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN0
IN1
IN2
IN3
AGND
IN4
IN5
IN6
IN7
COM
9
10
7
8
5
6
3
4
1
2
PIN 1
INDICATOR
ADAS3023
TOP VIEW
(Not to Scale)
30 AGND
29 AGND
28 AVDD
27 DVDD
26 ACAP
25 DCAP
24 AGND
23 AGND
22 DGND
21 DGND
Data Sheet
NOTES
1. CONNECT THE EXPOSED PAD TO VSSH.
Figure 6. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic
1 to 4
6 to 9
5, 14, 23,
24, 29,
30, 40
10
IN0 to IN3
IN4 to IN7
AGND
COM
AI
AI
P
AI
Input Channel 0 to Input Channel 3.
Input Channel 4 to Input Channel 7.
Analog Ground. Connect AGND to the system analog ground plane.
11
12
13
15
16
17
18
19
20
21, 22
25
26
CS
DIN
RESET
PD
SCK
VIO
SDO
DI
DI
DI
DO
BUSY/SDO2 DO
CNV
DGND
DCAP
ACAP
DI
P
DI
P
P
P
IN0 to IN7 Common Channel Input. Input Channel IN0 to Input Channel IN7 are referenced to a common point. The maximum voltage on this pin is ±10.24 V for all PGIA gains.
Chip Select. Active low signal. Enables the digital interface for writing and reading data. Use the CS pin when sharing the serial bus. For a dedicated and simplified ADAS3023 serial interface, tie CS to DGND or CNV.
Data Input. DIN is the serial data input for writing the 16-bit configuration (CFG) word that is clocked into the device on the SCK rising edges. The CFG is an internal register that is updated on the rising edge of the next end of a conversion pulse, which coincides with the falling edge of BUSY/SDO2. The CFG register is written into the device on the first 16 clocks after conversion. To avoid corrupting a conversion due to digital activity on the serial bus, do not write data during a conversion.
Asynchronous Reset. A low-to-high transition resets the ADAS3023 . The current conversion, if active, is aborted and the CFG register is reset to the default state.
Power-Down. A low-to-high transition powers down the ADAS3023 , minimizing the device operating current. Note that PD must be held high until the user is ready to power on the device. After powering on the device, the user must wait 100 ms until the reference is enabled and then wait for the completion of one dummy conversion before the device is ready to convert. Note that the RESET pin remains low for
100 ns after the release of PD. See the Power-Down Mode section for more information.
Serial Clock Input. The DIN and SDO data sent to and from the ADAS3023 are synchronized with SCK.
Digital Interface Supply. Nominally, it is recommended that VIO be at the same voltage as the supply of the host interface: 1.8 V, 2.5 V, 3.3 V, or 5 V.
Serial Data Output. The conversion result is output on this pin and synchronized to the SCK falling edges. The conversion results are presented on this pin in twos complement format.
Busy/Serial Data Output 2. The converter busy signal is always output on the BUSY/SDO2 pin when CS is logic high. If SDO2 is enabled when CS is brought low after the EOC, the SDO outputs the data. The conversion result is output on this pin and synchronized to the SCK falling edges. The conversion results are presented on this pin in twos complement format.
Convert Input. A conversion is initiated on the rising edge of the CNV pin.
Digital Ground. Connect DGND to the system digital ground plane.
Internal 2.5 V Digital Regulator Output. Decouple DCAP, an internally regulated output, using a 10 μF and a 0.1 μF local capacitor.
Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal ADC core and to all of the supporting analog circuits, except for the internal reference. Decouple this internally regulated output (ACAP) using a 10 μF capacitor and a 0.1 μF local capacitor.
Rev. A | Page 10 of 32
Data Sheet ADAS3023
Pin No. Mnemonic
27
28
31
32
33, 34
35
36, 37
38
39
DVDD
AVDD
RCAP
P
P
P
REFIN Internal 2.5 V Band Gap Reference Output, Reference Buffer Input, or Reference Power-Down Input.
REF1 and REF2 must be tied together externally. See the Voltage Reference Input/Output section for
more information.
REF1, REF2 AI/O Reference Input/Output. Regardless of the reference method, REF1 and REF2 need individual decoupling using external 10 μF ceramic capacitors connected as close to REF1, REF2, and REFN as
possible. See the Voltage Reference Input/Output section for more information.
RGND
REFN
P
P
Digital 5 V Supply. Decouple the DVDD supply to DGND using a 10 μF capacitor and 0.1 μF local capacitor.
Analog 5 V Supply. Decouple the AVDD supply to AGND using a 10 μF capacitor and 0.1 μF local capacitor.
Internal 2.5 V Analog Regulator Output. RCAP supplies power to the internal reference. Decouple this internally regulated output (RCAP) using a 10 μF capacitor and a 0.1 μF local capacitor.
VSSH
VDDH
EP
P
P
N/A
Reference Supply Ground. Connect RGND to the system analog ground plane.
Reference Input/Output Ground. Connect the 10 μF capacitors that are on REF1 and REF2 to the REFN pins, then connect the REFN pins to the system analog ground plane.
High Voltage Analog Negative Supply. Nominally, the supply of VSSH is −15 V. Decouple VSSH using a
10 μF capacitor and a 0.1 μF local capacitor. Connect the exposed pad to VSSH.
High Voltage Analog Positive Supply. Nominally, the supply of VDDH is 15 V. Decouple VDDH using a
10 μF capacitor and a 0.1 μF local capacitor.
Exposed Pad. Connect the exposed pad to VSSH.
1 AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, P = power, and N/A means not applicable.
Rev. A | Page 11 of 32
ADAS3023
TYPICAL PERFORMANCE CHARACTERISTICS
VDDH = 15 V, VSSH = −15 V, AVDD = DVDD = 5 V, VIO = 1.8 V to AVDD, unless otherwise noted.
2.0
1.5
FOR ALL PGIA GAINS
INL MAX = 0.875
INL MIN = –1.216
400000
350000
PGIA GAIN = 0.4
f
S
= 500kSPS
INTERNAL REFERENCE
325285
1.0
300000
0.75
0.50
0.25
0
–0.25
–0.50
0.5
0
–0.5
–1.0
–1.5
–2.0
0 8192 16384 24576 32768
CODE
40960 49152 57344 65536
Figure 7. Integral Nonlinearity (INL) vs. Code for All PGIA Gains
1.00
–0.75
–1.00
0
FOR ALL PGIA GAINS
DNL MAX = 0.794
DNL MIN = –0.661
8192 16384 24576 32768
CODE
40960 49152 57344 65536
Figure 8. Differential Nonlinearity (DNL) vs. Code for All PGIA Gains
400000
350000
PGIA GAIN = 0.2
f
S
= 500kSPS
INTERNAL REFERENCE
300000
278780
250000
200000
190408
150000
100000
50000
0
0 0 0 83
23813
6909
7 0 0
250000
200000
150000
100000
50000
0
0 0 0
962
74640
97631
Data Sheet
1481
1
400000
350000
PGIA GAIN = 0.8
f
S
= 500kSPS
INTERNAL REFERENCE
300000
250000
200000
248346
188714
150000
100000
50000
0
0 0 201
18671
43158
908 2
0 0
CODE IN HEX
Figure 10. Histogram of a DC Input at Code Center, PGIA Gain = 0.4
0 0
CODE IN HEX
Figure 11. Histogram of a DC Input at Code Center, PGIA Gain = 0.8
400000
350000
PGIA GAIN = 1.6
f
S
= 500kSPS
INTERNAL REFERENCE
300000
250000
200000
185455
171423
150000
100000
50000
0
0 6 450
9497
70413
56261
6254 238
3
CODE IN HEX
Figure 9. Histogram of a DC Input at Code Center, PGIA Gain = 0.2
CODE IN HEX
Figure 12. Histogram of a DC Input at Code Center, PGIA Gain = 1.6
Rev. A | Page 12 of 32
Data Sheet
60
50
40
30
20
14 15 13 13
11
10
3
5
6
2
3
2
3
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
REFERENCE DRIFT (ppm/°C)
Figure 13. Reference Drift, Internal Reference
60
50
46
40
30 28
–100
–120
–140
–160
0
20
13
10
0
2
1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
REFERENCE BUFFER DRIFT (ppm/°C)
Figure 14. Reference Buffer Drift, Internal Reference
0
–20
–40
–60
PGIA GAIN = 0.2
f
S f
IN
= 500kSPS
= 1.12kHz
SNR = 91.3dB
SINAD = 91.3dB
THD = –110.6dB
SFDR = 106.6dB
INTERNAL REFERENCE
–80
250 50 100 150
FREQUENCY (kHz)
200
Figure 15. 1 kHz FFT, PGIA Gain = 0.2
–80
–100
–120
–140
–160
0
0
–20
–40
–60
ADAS3023
PGIA GAIN = 0.4
f
S
= 500kSPS f
IN
= 1.12kHz
SNR = 91.2dB
SINAD = 91.1dB
THD = –107.0dB
SFDR = 106.0dB
INTERNAL REFERENCE
50 100 150
FREQUENCY (kHz)
200
Figure 16. 1 kHz FFT, PGIA Gain = 0.4
PGIA GAIN = 0.8
f
S
= 500kSPS f
IN
= 1.12kHz
SNR = 89.7dB
SINAD = 89.6dB
THD = –104.0dB
SFDR = 105.0dB
INTERNAL REFERENCE
250
0
–20
–40
–60
–80
–100
–120
–140
–160
0
0
–20
–40
–60
–80
–100
–120
–140
–160
0
50 100 150
FREQUENCY (kHz)
200
Figure 17. 1 kHz FFT, PGIA Gain = 0.8
PGIA GAIN = 1.6
f
S
= 500kSPS f
IN
= 1.12kHz
SNR = 87.3dB
SINAD = 87.2dB
THD = –103.0dB
SFDR = 106.0dB
INTERNAL REFERENCE
50 100 150
FREQUENCY (kHz)
200
Figure 18. 1 kHz FFT, PGIA Gain = 1.6
250
250
Rev. A | Page 13 of 32
ADAS3023
–80
CH1, 2 ACTIVE CHANNELS, 500kSPS, PGIA GAIN = 0.8
CH3, 4 ACTIVE CHANNELS, 200kSPS, PGIA GAIN = 0.8
CH4, 6 ACTIVE CHANNELS, 100kSPS, PGIA GAIN = 0.8
CH4, 8 ACTIVE CHANNELS, 100kSPS, PGIA GAIN = 0.2
CH4, 8 ACTIVE CHANNELS, 100kSPS, PGIA GAIN = 0.4
–85
–90
–95
–100
–105
100
CH4, 8 ACTIVE CHANNELS, 100kSPS, PGIA GAIN = 0.8
CH4, 8 ACTIVE CHANNELS, 100kSPS, PGIA GAIN = 1.6
1k 10k
FREQUENCY (Hz)
100k
Figure 19. Crosstalk vs. Frequency
110
100
1M
PGIA GAIN = 0.2
PGIA GAIN = 0.4
PGIA GAIN = 0.8
PGIA GAIN = 1.6
90
80
70
60
50
40
1 10 100
FREQUENCY (Hz)
1k
Figure 20. CMRR vs. Frequency
10k
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
10
VDDH = 15V
6 ACTIVE CHANNELS, PGIA GAIN = 1.6
8 ACTIVE CHANNELS, PGIA GAIN = 1.6
6 ACTIVE CHANNELS, PGIA GAIN = 0.2
8 ACTIVE CHANNELS, PGIA GAIN = 0.2
4 ACTIVE CHANNELS, PGIA GAIN = 1.6
4 ACTIVE CHANNELS, PGIA GAIN = 0.2
2 ACTIVE CHANNELS, PGIA GAIN = 1.6
2 ACTIVE CHANNELS, PGIA GAIN = 0.2
100 1000
THROUGHPUT (kSPS)
Figure 21. VDDH Current vs. Throughput
Data Sheet
–6.0
–6.5
–7.0
–7.5
–8.0
–8.5
–9.0
–9.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–10.0
–10.5
–11.0
10
2 ACTIVE CHANNELS, PGIA GAIN = 0.2
2 ACTIVE CHANNELS, PGIA GAIN = 1.6
4 ACTIVE CHANNELS, PGIA GAIN = 0.2
4 ACTIVE CHANNELS, PGIA GAIN = 1.6
8 ACTIVE CHANNELS, PGIA GAIN = 0.2
8 ACTIVE CHANNELS, PGIA GAIN = 1.6
VSSH = –15V
6 ACTIVE CHANNELS, PGIA GAIN = 0.2
6 ACTIVE CHANNELS, PGIA GAIN = 1.6
100 1000
THROUGHPUT (kSPS)
Figure 22. VSSH Current vs. Throughput
17
16
15
14
20
AVDD = 5V
19
18
INTERNAL REFERENCE
13
12
EXTERNAL REFERENCE
11
10
10 100
THROUGHPUT (kSPS)
Figure 23. AVDD Current vs. Throughput
2.0
1.7
1.4
1.1
0.8
0.5
10
3.5
DVDD = 5V
3.2
2.9
2.6
2.3
100
THROUGHPUT (kSPS)
Figure 24. DVDD Current vs. Throughput
1000
1000
Rev. A | Page 14 of 32
Data Sheet
100
98
96
94
92
90
88
86
84
82
80
CH1, PGIA GAIN = 0.4,
CH2, PGIA GAIN = 0.8,
CH5, PGIA GAIN = 0.8,
CH3, PGIA GAIN = 1.6, f f
S
= 500kSPS f
S
= 250kSPS
S
= 125kSPS f
S
= 167kSPS
TEMPERATURE (°C)
Figure 25. SNR vs. Temperature
–100
–105
–110
–115
–80
–85
–90
–95
CH1, PGIA GAIN = 0.4,
CH2, PGIA GAIN = 0.8,
CH5, PGIA GAIN = 0.8,
CH3, PGIA GAIN = 1.6, f
S
= 500kSPS f f
S
= 250kSPS f
S
= 125kSPS
S
= 167kSPS
–120
TEMPERATURE (°C)
Figure 26. THD vs. Temperature
0
–1
2
1
–2
–3
–4
–5
5
4
3
PGIA GAIN = 0.2
EXTERNAL REFERENCE f
S
= 125kSPS
T
A
= 25°C
CH0
CH4
CH1
CH5
CH2
CH6
CH3
CH7
TEMPERATURE (°C)
Figure 27. Normalized Offset Error Drift, PGIA GAin = 0.2
ADAS3023
0
–1
–2
–3
–4
–5
2
1
5
4
3
PGIA GAIN = 0.4
EXTERNAL REFERENCE f
T
S
= 125kSPS
A
= 25°C
CH0
CH4
CH1
CH5
CH2
CH6
CH3
CH7
TEMPERATURE (°C)
Figure 28. Normalized Offset Error Drift, PGIA Gain = 0.4
0
–1
–2
–3
–4
–5
2
1
5
4
3
PGIA GAIN = 0.8
EXTERNAL REFERENCE f
T
S
= 125kSPS
A
= 25°C
CH0
CH4
CH1
CH5
CH2
CH6
CH3
CH7
TEMPERATURE (°C)
Figure 29. Normalized Offset Error Drift, PGIA Gain = 0.8
0
–2
–4
–6
–8
–10
4
2
10
8
6
PGIA GAIN = 1.6
EXTERNAL REFERENCE f
T
S
= 125kSPS
A
= 25°C
CH0
CH4
CH1
CH5
CH2
CH6
CH3
CH7
TEMPERATURE (°C)
Figure 30. Normalized Offset Error Drift, PGIA Gain = 1.6
Rev. A | Page 15 of 32
ADAS3023
5
4
3
PGIA GAIN = 0.2
EXTERNAL REFERENCE f
S
= 125kSPS
T
A
= 25°C
0
–1
–2
–3
–4
–5
2
1
CH0
CH4
CH1
CH5
CH2
CH6
CH3
CH7
TEMPERATURE (°C)
Figure 31. Normalized Gain Error Drift Error, PGIA Gain = 0.2
0
–1
–2
–3
–4
–5
2
1
5
4
3
PGIA GAIN = 0.4
EXTERNAL REFERENCE f
S
= 125kSPS
T
A
= 25°C
CH0
CH4
CH1
CH5
CH2
CH6
CH3
CH7
TEMPERATURE (°C)
Figure 32. Normalized Gain Error Drift Error, PGIA Gain = 0.4
Data Sheet
0
–1
–2
–3
–4
–5
2
1
5
4
3
PGIA GAIN = 0.8
EXTERNAL REFERENCE f
T
S
= 125kSPS
A
= 25°C
CH0
CH4
CH1
CH5
CH2
CH6
CH3
CH7
TEMPERATURE (°C)
Figure 33. Normalized Gain Error Drift Error, PGIA Gain = 0.8
0
–2
–4
–6
–8
–10
4
2
10
8
6
PGIA GAIN = 1.6
EXTERNAL REFERENCE f
T
S
= 125kSPS
A
= 25°C
CH0
CH4
CH1
CH5
CH2
CH6
CH3
CH7
TEMPERATURE (°C)
Figure 34. Normalized Gain Error Drift Error, PGIA Gain = 1.6
Rev. A | Page 16 of 32
Data Sheet
TERMINOLOGY
Operating Input Voltage Range
Operating input voltage range is the maximum input voltage range, including common-mode, which can be applied to the input channels, IN0 to IN7, and COM.
Differential Input Voltage Range
Differential input voltage range is the maximum differential full-scale input range. The value changes according to the selected programmable gain setting.
Channel Off Leakage
Channel off leakage is the leakage current with the channel turned off.
Channel On Leakage
Channel on leakage is the leakage current with the channel turned on.
Common-Mode Rejection Ratio (CMRR)
CMRR is computed as the ratio of the signal magnitude of the converted result, referred to input, in the converted result to the amplitude of the common modulation signal applied to an input pair, expressed in decibels. CMRR is a measure of the ability of the ADAS3023 to reject signals, such as power line noise, that are common to the inputs. This specification is tested and specified for all input channels, IN0 to IN7, with respect to COM.
Transient Response
Transient response is a measure of the time required for the
ADAS3023 to properly acquire the input after a full-scale step function is applied to the system.
Least Significant Bit (LSB)
The LSB is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is
LSB
(V) =
2
V
2
REF
N
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 37).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. DNL is often specified in terms of resolution for which no missing codes are guaranteed.
ADAS3023
Offset Error
Ideally, the MSB transition occurs at an input level that is ½ LSB above analog ground. The offset error is the deviation of the actual transition from that point.
Gain Error
Ideally, the last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale. The gain error is the deviation in LSB (or percentage of full-scale range) of the actual level of the last transition from the ideal level after the offset error is removed. Closely related is the fullscale error (also in LSB or percentage of full-scale range), which includes the effects of the offset error.
Aperture Delay
Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and the point at which the input signal is held for a conversion.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with a −60 dBFS input signal applied to the inputs. The value for dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal.
Rev. A | Page 17 of 32
ADAS3023
Channel-to-Channel Crosstalk
Channel-to-channel crosstalk is a measure of the level of crosstalk between any channel and all other channels. The crosstalk is measured by applying a dc input to the channel under test and applying a full-scale, 10 kHz sine wave signal to all other channels.
The crosstalk is the amount of signal that leaks into the test channel expressed in decibels.
Data Sheet
Reference Voltage Temperature Coefficient
The reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of devices at the maximum and minimum reference output voltage (V
REF
) measured at T
MIN
, T
A
(25°C), and T
MAX
expressed in ppm/°C.
TCV
REF
( ppm/
°
C )
=
V
V
REF
REF
(
Max
(
25
°
C
)
×
) –
V
REF
(
T
MAX
(
Min
)
–
T
MIN
)
×
10
6 where:
V
REF
(Max) is the maximum V
REF
at T
MIN
, T
A
(25°C), or T
MAX
.
V
REF
(Min) is the minimum V
REF
at T
MIN
, T
A
(25°C), or T
MAX
.
V
REF
(25°C) = V
REF
at 25°C.
T
MAX
= +85°C.
T
MIN
= −40°C.
Rev. A | Page 18 of 32
Data Sheet
THEORY OF OPERATION
OVERVIEW
The ADAS3023 is a 16-bit, 8-channel simultaneous system on a single chip that integrates the typical components used in a data acquisition system in one easy to use, programmable device. It is capable of converting two channels simultaneously up to 500,000 samples per second (500 kSPS) throughput. The ADAS3023 features
• High impedance inputs
• High common-mode rejection
• An 8-channel, low leakage track and hold
• A programmable gain instrumentation amplifier (PGIA) with four selectable differential input ranges from ±2.56 V to ±20.48 V
• A 16-bit PulSAR® ADC with no missing codes
• An internal, precision, low drift 4.096 V reference and buffer
The ADAS3023 uses the Analog Devices patented high voltage
iCMOS process allowing up to a ±20.48 V differential input voltage range when using ±15 V supplies, which makes the device suitable for industrial applications.
The device is housed in a small 6 mm × 6 mm, 40-lead LFCSP package and can operate over the industrial temperature range of
−40°C to +85°C. A typical discrete multichannel data acquisition system containing similar circuitry requires more space on the circuit board than the ADAS3023 . Therefore, advantages of the
ADAS3023 solution include a reduced footprint and less complex design requirements, leading to faster time to market and lower costs.
OPERATION
The analog circuitry of the ADAS3023 consists of a high impedance, low leakage, track-and-hold PGIA with a high common-mode rejection that can accept the full-scale differential voltages of ±2.56 V, ±5.12 V, ±10.24 V, and ±20.48 V (see
ADAS3023 can be configured to sample two, four, six, or eight channels simultaneously.
ADAS3023
The ADAS3023 offers true high impedance inputs in a differential structure and rejects common-mode signals present on the inputs.
This architecture does not require additional input buffers (op amps) that are usually required for signal buffering, level shifting, amplification, attenuation, and kickback reduction when using switched capacitor-based SAR ADCs.
Digital control of the programmable gain setting of each channel input is set via the configuration (CFG) register.
The conversion results are output in twos complement format on the serial data output (SDO) and through an optional secondary serial data output on the BUSY/SDO2 pin. The digital interface uses a dedicated chip select (CS) to control data access to and from the ADAS3023 together with a BUSY/SDO2 output, asynchronous reset (RESET), and power-down (PD) inputs.
The internal reference of the ADAS3023 uses an internal temperature compensated 2.5 V output band gap reference, followed by a precision buffer amplifier to provide the 4.096 V high precision system reference.
All of these components are configured through a serial (SPIcompatible), 16-bit CFG register. Configuration and conversion results are read after the conversions are completed.
The ADAS3023 requires a minimum of three power supplies
+15 V, −15 V, and +5 V. Internal low dropout regulators provide the necessary 2.5 V system voltages that must be decoupled externally via dedicated pins (ACAP, DCAP, and RCAP). The
ADAS3023 can be interfaced to any 1.8 V to 5 V digital logic family using the dedicated VIO logic level voltage supply (see
A rising edge on the CNV pin initiates a conversion and changes the ADAS3023 from track to hold. In this state, the ADAS3023 performs the analog signal conditioning and conversion. When the signal conditioning is completed, the ADAS3023 returns to the track state while, at the same time, quantizes the sample. This two-tiered process satisfies the necessary settling time requirement and achieves a fast throughput rate of up to 500 kSPS with 16-bit accuracy.
VDDH AVDD DVDD VIO RESET
DIFF TO
COM
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
TRACK
AND
HOLD
PGIA
LOGIC/
INTERFACE
PulSAR
ADC
ADAS3023
BUF
REF
VSSH AGND DGND REFx
Figure 35. Simplified Block Diagram
PD
CNV
BUSY
CS
SCK
DIN
SDO
REFIN
Rev. A | Page 19 of 32
ADAS3023 t
CONV
CNV t
CYC t
ACQ
PHASE
CONVERSION ACQUISITION
Figure 36. System Timing
Regardless of the type of signal, (single-ended symmetric or asymmetric), the ADAS3023 converts all signals present on the enabled inputs and COM pin in a differential fashion identical to an industry-standard difference or instrumentation amplifier.
The conversion results are available after the conversion is complete and can be read back at any time before the end of the next conversion. Avoid reading back data during the quiet period, indicated by BUSY/SDO2 being active high. Because the ADAS3023 has an on-board conversion clock, the serial clock (SCK) is not required for the conversion process; it is only required to present results to the user.
Data Sheet
TRANSFER FUNCTIONS
The ideal transfer characteristic for the ADAS3023 is shown in
Figure 37. The inputs are configured for differential input ranges
and the data outputs are in twos complement format, as listed in
TWOS
COMPLEMENT
STRAIGHT
BINARY
011...111
011...110
011...101
111...111
111...110
111...101
Table 6. Output Codes and Ideal Input Voltages
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
Differential Analog Inputs, V
REF
= 4.096 V
(32,767 × V
REF
)/(32,768 × PGIA gain)
(V
REF
/(32,768 × PGIA gain))
0
−(V
REF
/(32,768 × PGIA gain))
−(32,767 × V
REF
)/(32,768 × PGIA gain)
−V
REF
× PGIA gain
100...010
100...001
100...000
000...010
000...001
000...000
–FSR
–FSR + 1LSB
–FSR + 0.5LSB
+FSR – 1LSB
+FSR – 1.5LSB
ANALOG INPUT
Figure 37. ADC Ideal Transfer Function
Digital Output Code
(Twos Complement Hex)
0x7FFF
0x0001
0x0000
0xFFFF
0x8001
0x8000
Rev. A | Page 20 of 32
Data Sheet ADAS3023
V
IN
= +5V
ENABLE
C
C
1
12nF
+ +
C
C
2
10pF
R
C
1
100kΩ
RF2
4.22kΩ
C
IN
1µF
+
R
EN
50kΩ
ADP1613
COMP SS
FB
EN
GND
RF1B
47.5kΩ
FREQ
VIN
SW
R
B
0
1Ω
R
S
1
0Ω
L2
47µH
L1
47µH
D2
+
C
OUT
3
4.7µF
+
C2
1µF
1.78Ω
R
FILT
D1
C1
1µF
C
OUT
1
1µF
+
L3
1µF
C
OUT
2.2µF
2
+
C
V
5
1µF
+
R
S
2
DNI
C
SS
1µF
+
Z1
DNI
+15V
+5V
VDDH AVDD DVDD VIO RESET PD
DIFF TO
COM
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
TRACK
AND
HOLD
PGIA
ADAS3023
LOGIC/
INTERFACE
PulSAR
ADC
BUF
VSSH
–15V
AGND DGND
CNV
BUSY
CS
SCK
DIN
SDO
REFIN
REF
REFx
+5V
4.096V
+
–
+5V
ADR434
AD8031
Figure 38. Complete 5 V, Single-Supply, 8-Channel Data Acquisition System with PGIA
VDDH
TYPICAL APPLICATION CONNECTION DIAGRAM
ADP1613 is used in an inexpensive
SEPIC-Ćuk topology, which is an ideal candidate for providing the ADAS3023 with the necessary high voltage ±15 V robust supplies (at 20 mA) and low output ripple (3 mV maximum) from an external 5 V supply. The ADP1613 satisfies the specification requirements of the ADAS3023 using minimal external components yet achieves greater than 86% efficiency. See the CN-0201 circuit note for complete information about this test setup.
ANALOG INPUTS
Input Structure
The ADAS3023 uses a differential input structure between each of the channel inputs, IN0 to IN7, and a common reference
(COM), all of which sample simultaneously.
Figure 39 shows an equivalent circuit of the inputs. The diodes
provide ESD protection for the analog inputs (IN0 to IN7) and
COM from the high voltage supplies (VDDH and VSSH). Ensure that the analog input signal does not exceed the supply rails by more than 0.3 V because this can cause the diodes to become forward-biased and to start conducting current. The voltages beyond the absolute maximum ratings may cause permanent damage to the ADAS3023
INx OR COM
VSSH
C
PIN
TRACK
AND
HOLD
PGIA
AGND
Figure 39. Equivalent Analog Input Circuit
Programmable Gain
The ADAS3023 incorporates a programmable gain instrumentation amplifier (PGIA) with four selectable ranges. The
PGIA settings are specified in terms of the maximum absolute differential input voltage across an input pin and the COM pin, for example INx to COM. The power on and default conditions are preset to the ±20.48 V (PGIA = 11) input range.
Note that because the ADAS3023 can use any input type, such as bipolar single-ended and pseudo bipolar, setting the PGIA is important to make full use of the allowable input span.
Rev. A | Page 21 of 32
ADAS3023
Table 7 describes each differential input range and the corre-
sponding LSB size, PGIA bit settings, and PGIA gain.
Table 7. Differential Input Ranges, LSB Size, and PGIA
Settings
Differential Input Ranges,
INx − COM (V) LSB (μV)
PGIA
CFG
PGIA
Gain
(V/V)
±20.48
±10.24
±5.12
±2.56
625
312.5
156.3
78.13
11
00
01
10
0.2
0.4
0.8
1.6
Common-Mode Operating Range
The differential input common-mode range changes according to the input range selected for a given channel and the high voltage power supplies. Note that the operating input voltage of
any input pin, as defined in the Specifications section, requires
a minimum of 2.5 V of headroom from the VDDH/VSSH supplies or
(VSSH + 2.5 V) ≤ INx/COM ≤ (VDDH – 2.5 V)
The following sections offer some examples of setting the PGIA for various input signals. Note that the ADAS3023 always takes the difference between the INx and COM signals.
Single-Ended Signals with a Nonzero DC Offset
(Asymmetrical)
When a 5.12 V p-p signal with a 2.56 V dc offset is connected to one of the inputs (INx+) and the dc ground sense of the signal is connected to COM, the PGIA gain configuration is set to 01 for the ±5.12 V range because the maximum differential voltage across the inputs is +5.12 V. This scenario uses only half the codes available for the transfer function.
INx+
+5.12V
INx+
5.12V p-p
V
OFF
ADAS3023
V
OFF
0V
COM
COM
Figure 40. Typical Single-Ended Unipolar Input Using Only Half of the Codes
Single-Ended Signals with a 0 V DC Offset (Symmetrical)
Compared with the example in the Single-Ended Signals with a
Nonzero DC Offset (Asymmetrical) section, a better solution
for single-ended signals, when possible, is to remove as much differential dc offset between INx and COM such that the average voltage is 0 V (symmetrical around the ground sense). The differential voltage across the inputs is never greater than
±2.56 V, and the PGIA gain configuration is set for a ±2.56 V range (10). This scenario uses all of the codes available for the transfer function, making full use of the allowable differential input range.
Data Sheet
INx+
INx+
+2.56V
0V 5.12V p-p
ADAS3023
COM
–2.56V
COM
Figure 41. Optimal Single-Ended Configuration Using All Codes
Notice that the voltages in the examples are not integer values due to the 4.096 V reference and the scaling ratios of the PGIA.
The maximum allowed dc offset voltage on the COM input pin
for various PGIA gains in this case is shown in Table 8.
Table 8. DC Offset Voltage on COM Input and PGIA
PGIA Gain (V/V) DC Offset Voltage on COM (V)
0.2
0.4
0.8
1.6
0
0
±5.12
±7.68
1 Full-scale signal on INx.
VOLTAGE REFERENCE INPUT/OUTPUT
The ADAS3023 allows the choice of an internal reference, an external reference using an internal buffer, or an external reference.
The internal reference of the ADAS3023 provides excellent performance and can be used in nearly any application. Setting the reference selection mode uses the internal reference enable bit, REFEN, and the REFIN pin as described in the following
sections (Internal Reference, External Reference and Internal
Buffer, External Reference, and Reference Decoupling).
Internal Reference
The precision internal reference is factory trimmed and is suitable for most applications.
Setting the REFEN bit in the CFG register to 1 (default) enables the internal reference and produces 4.096 V on the REF1 and
REF2 pins; this 4.096 V output serves as the main system reference.
The unbuffered 2.5 V (typical) band gap reference voltage is output on the REFIN pin, which requires an external parallel combination of 10 μF and 0.1 μF capacitors to reduce the noise on the output. Because the current output of REFIN is limited, it can be used as a source when followed by a suitable buffer, such as the AD8031 . Note that excessive loading of the REFIN output lowers the 4.096 V system reference because the internal amplifier uses a fixed gain.
The internal reference output is trimmed to the targeted value of 4.096 V with an initial accuracy of ±8 mV. The reference is also temperature compensated to provide a typical drift of
±5 ppm/°C.
When the internal reference is used, decouple the ADAS3023 ,
as shown in Figure 42. Note that both the REF1 and REF2 con-
nections are shorted together and externally decoupled with
Rev. A | Page 22 of 32
Data Sheet
suitable decoupling on the REFIN output and the RCAP internally regulated supply.
0.1µF 0.1µF 0.1µF
10µF
REFN REF2
10µF
REFN REF1
10µF
REFN REFIN
ADAS3023
loading for op amps usually refers to the ability of the amplifier to remain marginally stable in ac applications but can also play a role in dc applications, such as a reference source.
Keep in mind that the reference source sees the dynamics of the bit decision process on the reference pins and further analysis beyond the scope of this data sheet may be required.
REFERENCE
SOURCE = 4.096V
ADAS3023
BAND
GAP
RCAP
1µF
10µF
0.1µF
10µF
0.1µF
External Reference and Internal Buffer
The external reference and internal buffer are useful where a common system reference is used or when improved drift performance is required.
Setting Bit REFEN to 0 disables the internal band gap reference, allowing the user to provide an external voltage reference (2.5 V typical) to the REFIN pin. The internal buffer remains enabled, thus reducing the need for an external buffer amplifier to generate the main system reference. Where REFIN = 2.5 V and REF1 and
REF2 output 4.096 V, this serves as the main system reference.
For this configuration, connect the external source, as shown in
Figure 43. Any type of 2.5 V reference can be used in this config-
uration (low power, low drift, small package, and so forth) because the internal buffer handles the dynamics of the ADAS3023 reference requirements.
0.1µF 0.1µF 0.1µF
REFERENCE
SOURCE = 2.5V
10µF 10µF 10µF
REFN
Figure 42. 4.096V Internal Reference Connection
REF2 REFN
ADAS3023
REF1
RGND
REFN
BAND
GAP
REFIN
RCAP
1µF
RGND
Figure 43. External Reference Using Internal Buffer
External Reference
For applications that require a precise, low drift, 4.096 V reference, an external reference can be used. Note that in this mode, disabling the internal buffer requires setting REFEN to 0, and driving or connecting REFIN to AGND; thus, both hardware and software control are necessary. Attempting to drive the REF1 and REF2 pins alone prior to disabling the internal buffer can cause source/sink contention in the outputs of the driving amplifiers.
Connect the precision 4.096 V reference directly to REF1 and
REF2, which are the main system reference (see Figure 44); two
recommended references are the ADR434 or ADR444 .
If an op amp is used as an external reference source, take note of the concerns regarding driving capacitive loads. Capacitive
Rev. A | Page 23 of 32
REFN REF2 REFN
ADAS3023
REF1 REFIN
BAND
GAP
RCAP
1µF
RGND
Figure 44. External Reference
Reference Decoupling
With any of the reference topologies described in the Voltage
Reference Input/Output section, the REF1 and REF2 reference
pins of the ADAS3023 have dynamic impedances and require sufficient decoupling, regardless of whether the pins are used as inputs or outputs. This decoupling usually consists of a low ESR capacitor connected to each REF1 and REF2 pin and to the accompanying REFN return paths. Ceramic chip capacitors (X5R, 1206 size) are recommended for decoupling in all of the reference
topologies described in the Voltage Reference Input/Output
section.
The placement of the reference decoupling capacitors plays an important role in system performance. Using thick printed circuit board (PCB) traces, mount the decoupling capacitors on the same side as the ADAS3023, close to the REF1 and REF2 pins. Route the return paths to the REFN inputs that, in turn, connect to the analog ground plane of the system. When it is necessary to connect to an internal PCB, minimize the resistance of the return path to ground by using as many through vias as possible.
Using the shortest distance and several vias, connect the REFN and RGND inputs to the analog ground plane of the system, preferably adjacent to the solder pads. One common mistake is to route these traces to an individual trace that connects to the ground of the system. This can introduce noise, which may adversely affect the LSB sensitivity. To prevent such noise, use
PCBs with multiple layers, including ground planes, rather than using single or double sided boards.
Smaller reference decoupling capacitor values (as low as 2.2 µF) can be used with little impact, mainly on DNL and THD. Furthermore, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) that is common in decoupling schemes for high frequency noise rejection.
For applications that use multiple ADAS3023 devices or other
PulSAR ADCs, using the internal reference buffer is most effective
ADAS3023 Data Sheet
to buffer the external reference voltage and, thereby, reduce SAR conversion crosstalk.
The voltage reference temperature coefficient (TC) directly affects the full-scale accuracy of the system; therefore, in applications where full-scale accuracy is crucial, care must be taken with the TC. For example, a ±15 ppm/°C TC of the reference changes the full-scale accuracy by ±1 LSB/°C.
POWER SUPPLY
The ADAS3023 uses five supplies: AVDD, DVDD, VIO, VDDH,
and VSSH (see Table 9). Note that the ACAP, DCAP, and RCAP
pins are for informational purposes only because they are the outputs of the internal supply regulators.
VIO is the variable digital input/output supply and allows direct interface with any logic between 1.8 V and 5 V (DVDD supply maximum). To reduce the supplies that are required, VIO can, alternatively, be connected to DVDD when DVDD is supplied from the analog supply through an RC filter. The recommended low dropout regulators are ADP3334 , ADP1715 , ADP7102 , and
ADP7104 for the AVDD, DVDD, and VIO supplies. Note that the user must bring up the ADAS3023 power supplies in the following sequence:
1. VIO
2. VDDH
3. VSSH
4. DVDD
5. AVDD
6. REFx
Table 9. Supplies
Mnemonic Function
AVDD
DVDD
VIO
VDDH
VSSH
ACAP
DCAP
RCAP
Analog 5 V core
Digital 5 V core
Yes
Yes, or can connect to
AVDD
Digital input/output Yes, and can connect to
DVDD (for the 5 V level)
Positive high voltage Yes, +15 V typical
Negative high voltage
Analog 2.5 V core
Digital 2.5 V core
Analog 2.5 V core
Required
Yes, −15 V typical
No, on chip
No, on chip
No, on chip
High Voltage Supplies
The high voltage bipolar supplies, VDDH and VSSH, are required and must be at least 2.5 V larger than the maximum operating input voltage. Specifically, any operating input voltage
(as defined in Table 2) of an input pin requires 2.5 V of headroom
from the VDDH/VSSH supplies or
(VSSH + 2.5 V) ≤ INx/COM ≤ (VDDH − 2.5 V)
Sufficient decoupling of these supplies is also required, consisting of at least a 10 μF capacitor and 100 nF capacitor on each supply.
Core Supplies
The AVDD and DVDD pins supply the ADAS3023 analog and digital cores, respectively. Sufficient decoupling of these supplies is required, consisting of at least a 10 μF capacitor and 100 nF capacitor on each supply. Place the 100 nF capacitors as close as possible to the ADAS3023 . To reduce the number of supplies that are required, supply the DVDD from the analog supply by connecting a simple RC filter between AVDD and DVDD, as shown in
+5V ANALOG
SUPPLY
10µF
+
+15V
10µF
+
–15V
10µF
+
100nF
100nF
100nF
20Ω
10µF
+
AVDD AGND DVDD DGND
VDDH
VSSH
ADAS3023
VIO
Figure 45. Supply Connections
100nF
100nF
+5V DIGITAL
SUPPLY
+1.8V TO +5V
DIGITAL I/O
SUPPLY
DGND
POWER DISSIPATION MODES
The ADAS3023 offers two power dissipation modes: fully operational mode and power-down mode.
Fully Operational Mode
In fully operational mode, the conversions normally.
Power-Down Mode
ADAS3023 can perform the
To minimize the operating currents of the device when it is idle, place the device in full power-down mode by bringing the PD input high; this places the ADAS3023 into a deep sleep mode in which CNV activity is ignored and the digital interface is inactive.
Refer to the RESET and Power-Down (PD) Inputs section for
timing details. In deep sleep mode, the internal regulators
(ACAP, RCAP, and DCAP) and the voltage reference are powered down.
10µF
+
To reestablish operation, return PD to logic low. Note that, before the device can operate at the specified performance, the reference voltage must charge up the external reservoir capacitor(s) and be allowed the specified settling time. RESET must be applied after returning PD to low to restore the ADAS3023 digital core, including the CFG register, to its default state. Therefore, the desired CFG must be rewritten to the device and one dummy conversion must be completed before the device operation is restored to the configuration programmed prior to PD assertion. Note that when using the internal reference, sufficient time is required to settle it to the nominal value. For a typical connection, it requires 100 ms
to settle to the nominal value (see Figure 41).
Rev. A | Page 24 of 32
Data Sheet
CONVERSION MODES
The ADAS3023 offers two conversion modes to accommodate varying applications, and both modes are set with the conversion mode select bit, CMS (Bit 1) of the CFG register.
Warp Mode (CMS = 0)
Setting CMS to 0 is useful where the full 2-channel throughput of 500 kSPS is required. However, in this mode, the maximum time between conversions is restricted. If this maximum period is exceeded, the conversion result can be corrupted. Therefore, the warp mode is best suited for continuously sampled applications.
ADAS3023
Normal Mode (CMS = 1, Default)
Setting CMS to 1 is useful for all applications where the full
500 kSPS sample rate of the device is not required. In this mode, there is no maximum time restriction between conversions. This mode is the default condition from the assertion of an asynchronous reset. The main difference between the normal mode and warp mode is that the BUSY/SDO2 time, t
CONV
, is slightly longer in normal mode than in warp mode.
Rev. A | Page 25 of 32
ADAS3023
DIGITAL INTERFACE
The ADAS3023 digital interface consists of asynchronous inputs and a 4-wire serial interface for conversion result readback and configuration register programming.
This interface uses the three asynchronous signals (CNV, RESET, and PD) and a 4-wire serial interface comprised of CS, SDO,
SCK, and DIN. CS can also be tied to CNV for some applications.
Conversion results are presented to the serial data output pin
(SDO) after the end of a conversion. The 16-bit configuration word, CFG, is programmed on the serial data input pin, DIN during the first 16 SCKs of any data transfer. This CFG register controls the settings, such as selecting the number of channels to be converted, the programmable gain settings for each channel
group, and the reference choice (see Configuration Register
section for more information).
CONVERSION CONTROL
The CNV input initiates conversions for N enabled channels as defined in the CFG register. The ADAS3023 is fully asynchronous and can perform conversions at any frequency from dc up to
500 kSPS, depending on the settings specified in the configuration register and the system serial clock rate.
CNV Rising—Start of Conversion (SOC)
A rising edge on the CNV changes the state of the ADAS3023 from track mode to hold mode, as well as all that is necessary to initiate a conversion. All conversion clocks are generated internally. After a conversion is initiated, the ADAS3023 ignores other activity on the CNV line (governed by the throughput rate) until the end of the conversion.
While the ADAS3023 is performing a conversion and the BUSY/
SDO2 output is driven high, the ADAS3023 uses a unique 2-phase conversion process, allowing for safe data access and quiet time.
The CNV signal is decoupled from the CS pin, allowing multiple
ADAS3023 devices to be controlled by the same processor. For applications where SNR is critical, the CNV source requires very low jitter, which is achieved by using a dedicated oscillator or by clocking CNV with a high frequency, low jitter clock. For applications where jitter is more tolerable or a single device is in use, tie
CNV to CS. For more information on sample clock jitter and aperture delay, see the MT-007 Mini Tutorial , Aperture Time,
Aperture Jitter, Aperture Delay Time—Removing the Confusion.
Although CNV is a digital signal, take care to ensure fast, clean edges with minimal overshoot, undershoot, and ringing. In addition, avoid digital activity close to the sampling instant because such activity can result in degraded SNR performance.
BUSY/SDO2 Falling Edge—End of Conversion (EOC)
The EOC is indicated by BUSY/SDO2 returning low and can be used as a host interrupt. In addition, the EOC gates data access to and from the ADAS3023 . If the conversion result is not read prior to the next EOC event, the data is lost. Furthermore, if the
CFG update is not completed prior to the EOC, it is discarded and
Rev. A | Page 26 of 32
BUSY
CS t
CCS t
DIS t
EN
Data Sheet
the current configuration is applied to future conversions. This pipeline ensures that the ADAS3023 has sufficient time to acquire the next sample to the specified 16-bit accuracy.
Register Pipeline
The CFG register is written on the first 16 SCKs following the
EOC event, and it is updated on the next EOC event. To ensure that all CFG updates are applied during a known safe instant to the various circuit elements, the asynchronous data transfer is synchronized to the ADAS3023 timing engine using the EOC event. This synchronization introduces an inherent delay between updating the CFG register setting and the application of the configuration to a conversion. This pipeline, from the end of the current conversion (n), consists of a one-deep delay before the CFG setting takes effect. This means that two SOC and EOC events must elapse before the setting (that is, the new channel, gain, and so forth) takes effect. Note that the nomenclature (n),
(n + 1), and so forth is used in the remainder of the following
digital sections (Serial Data Interface, General Timing, and
Configuration Register) for simplicity. Note, however, that there
is no pipeline after the end of a conversion before data can be read back.
RESET AND POWER-DOWN (PD) INPUTS
The asynchronous RESET and PD inputs can be used to reset and power down the ADAS3023 , respectively. Timing details
t
RH t
ACQ
SEE NOTE
CNV n – 1 n
RESET/
PD
SDO n – 2 UNDEFINED x
CFG x n + 1 x DEFAULT x
SEE NOTE
NOTES
1. WHEN THE PART IS RELEASED FROM RESET, t
ACQ
MUST BE
MET FOR CONVERSION n IF USING THE DEFAULT CFG
SETTING FOR CHANNEL IN0. WHEN THE PART IS RELEASED
FROM POWER-DOWN, t
ACQ
IS NOT REQUIRED, AND THE FIRST
TWO CONVERSIONS, n AND n + 1, ARE UNDEFINED.
Figure 46. RESET and PD Timing
A rising edge on RESET or PD aborts the conversion process and places SDO into high impedance, regardless of the CS level. Note that RESET has a minimum pulse width (active high) time for setting the ADAS3023
into the reset state. See the Configuration
Register section for the default CFG setting when the
ADAS3023 returns from the reset state. If this default setting is used after
RESET is deasserted (Logic 0), for the conversion result to be valid, a period equal to the acquisition time (t
ACQ
) must elapse before CNV can be asserted; otherwise, if a conversion is initiated, the result is corrupted. In addition, the output data from the previous conversion is cleared upon a reset; attempting
Data Sheet
to access the data result prior to initiating a new conversion produces an invalid result.
Upon the device returning from power-down mode or from a reset when the default CFG is not used, there is no t
ACQ
requirement because the first two conversions from power-up are undefined/ invalid because the one-deep delay pipeline requirement must be satisfied to reconfigure the device to the desired setting.
SERIAL DATA INTERFACE
The ADAS3023 uses a simple 4-wire interface and is compatible with FPGAs, DSPs, and common serial interfaces such as a serial peripheral interface (SPI), QSPI™, and MICROWIRE®. The
t
SCK t
SCKL
CS
SCK t
SCKH t
DIS
ADAS3023
interface uses the CS, SCK, SDO, and DIN signals. Timing signals
for a serial interface are shown in Figure 47.
SDO is activated when CS is asserted. The conversion result is output on SDO and updated on the SCK falling edges. Simultaneously, the 16-bit CFG word is updated, if needed, on the serial data input (DIN). The state of BUSY/SDO2 (Bit 0) determines the output format of the MSB data when SDO is activated after the
EOC. Note that, in Figure 47, SCK is shown as idling high. SCK
can idle high or low, requiring the system developer to design an interface that suits setup and hold times for both SDO and DIN.
t
SDOH t
EN
SDO
(MISO)
DIN
(MOSI) t
SDOV t
DINS t
DINH
Figure 47. Serial Timing
Rev. A | Page 27 of 32
ADAS3023
GENERAL TIMING
Figure 48 and Figure 49 conversion timing diagrams show the
specific timing parameters, including the complete register to conversion and readback pipeline delay. These figures detail the timing from a power up or from returning from a full power down by use of the PD input. When the BUSY/SDO2 output is not enabled after the EOC, the data available on the SDO output
(MSB first) can be read after the16 SCK rising edges in sequential fashion (from Channel 0 (CH0) to Channel 7 (CH7)), as shown
SOC
EOC t
CYC
POWER
UP t
CONV
NOTE 1
PHASE CONVERSION (n) ACQUISITION (n + 1)
CNV t
CNVH
NOTE 4 t
AD
NOTE 3 CS
SCK
DIN
SDO
NOTE 2
1 16 1
CFG (n + 2)
CH0 CH1
16 1
CH7
16
SOC
The converter busy signal is always output on the BUSY/SDO2 pin when CS is logic high. When the BUSY/SDO2 output is enabled when CS is brought low after the EOC, the SDO outputs the data of Channel 0 to Channel 3 (CH0, CH1, CH2, and CH3), and the SDO2 outputs the data of Channel 4 to Channel 7 (CH4, CH5,
CH6, and CH7) after 16 SCK rising edges, as shown in Figure 49.
The conversion result output on BUSY/SDO2 pin synchronizes to the SCK falling edges. The conversion results are in twos complement format. Reading or writing data during the quiet conversion phase (t
CONV
) may cause incorrect bit decisions.
SOC
NOTE 2
CONVERSION (n + 1)
EOC
NOTE 1
1 16 1
CFG (n + 3)
CH0 CH1
16
Data Sheet
ACQUISITION (n + 2)
1
CH7
16
CS
SCK
DIN
SDO
BUSY/
SDO2
BUSY/
SDO2 t
CBD
DATA (n) DATA (n + 1)
NOTES
1. DATA ACCESS CAN ONLY OCCUR AFTER CONVERSION. BOTH CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF THE CONVERSION (EOC).
2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED FOR CONVERSION RESULT. AN ADDITIONAL 16 EDGES AFTER THE LAST CONVERSION RESULT ON BUSY READS BACK THE CFG ASSOCIATED
WITH CONVERSION.
3. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS IS SHOWN WITH FULL INDEPENDENT CONTROL.
4. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING INSTANT. A MINIMUM TIME OF AT LEAST THE APERATURE DELAY, t
AD, SHOULD LAPSE PRIOR TO DATA ACCESS.
SOC
Figure 48. General Timing Diagram with BUSY/SDO2 Disabled
SOC SOC
EOC t
CYC
EOC t
CONV
POWER
UP
PHASE CONVERSION (n)
NOTE 1
ACQUISITION (n + 1) CONVERSION (n + 1)
NOTE 1
ACQUISITION (n + 2)
CNV t
CNVH
NOTE 4 t
AD
NOTE 3
NOTE 2
1 16 1
CFG (n + 2)
CH0
CH4
CH1
CH5
16 1
CH2
CH6
16 1
CH3
CH7
16 1
CFG (n + 3)
CH0
CH4
16 1
CH1
CH5
16 1
CH2
CH6
16 1
CH3
CH7
16
DATA (n) DATA (n + 1)
NOTES
1. DATA ACCESS CAN ONLY OCCUR AFTER CONVERSION. BOTH CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF THE CONVERSION (EOC).
2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED FOR CONVERSION RESULT. AN ADDITIONAL 16 EDGES AFTER THE LAST CONVERSION RESULT ON BUSY READS BACK THE CFG ASSOCIATED
WITH CONVERSION.
3. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS IS SHOWN WITH FULL INDEPENDENT CONTROL.
4. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING INSTANT. A MINIMUM TIME OF AT LEAST THE APERATURE DELAY, t
AD, SHOULD LAPSE PRIOR TO DATA ACCESS.
Figure 49. General Timing Diagram with BUSY/SDO2 Enabled
Rev. A | Page 28 of 32
Data Sheet ADAS3023
CONFIGURATION REGISTER
The configuration register, CFG, is a 16-bit programmable register for selecting all of the user-programmable options of the ADAS3023
The register is loaded when data is read back for the first
16 SCK rising edges, and it is updated at the next EOC. Note that there is always a one-deep delay when writing to CFG, and when reading back from CFG, it is the setting associated with the current conversion. required for the user specified CFG to take effect. To ensure the digital core is in the default state, apply an external reset after the deassertion of PD. The default value is CFG[15:0] = 0xFFFF. To read back the contents of the configuration register, CFG, an additional 16 SCKs are provided after all of the channel data have been read, and CFG is made available on the SDO output.
The default CFG settings configure the ADAS3023 as follows:
The default CFG setting is applied when the ADAS3023 returns from the reset state (RESET = high) to the operational state
(RESET = low). Returning from the full power-down state
(PD = high) to an enabled state (PD = low), the default CFG setting is not applied and at least one dummy conversion is
• Overwrites contents of the CFG register.
• Selects the eight input channels mode.
• Configures the PGIA gain to 0.20 (±20.48 V).
• Enables the internal reference.
• Selects normal conversion mode.
• Disables the SDO2 readout mode.
Table 10. Configuration Register, CFG Bit Map; Default Value = 0xFFFF (1111 1111 1111 1111)
15 14 13 12 11 10 9 8 7 6 5 4
CFG INx INx RSV PGIA PGIA PGIA PGIA PGIA PGIA PGIA PGIA
3 2 1 0
RSV REFEN CMS BUSY/SDO2
Table 11. Configuration Register Description
Bit No. Bit Name
15 CFG
[14:13] INx
Description
Configuration update.
0 = keeps current configuration settings.
1 = overwrites contents of register.
Selection of the number of channels to be converted simultaneously.
12 RSV
[11:4] PGIA
1
1
Bit 14
0
0
Bit 13
0
1
0
1
Reserved. Setting or clearing this bit has no effect.
Programmable gain selection (see the Programmable Gain section).
Bit (Odd)
0
0
1
Bit (Even)
0
1
0
6
8
Channels
2
4
PGIA Gain
±10.24 V
±5.12 V
±2.56 V
1
0
3
2
[11:10] PGIA
[9:8]
[7:6]
[5:4]
PGIA
PGIA
PGIA
RSV
REFEN
CMS
1
Sets the gain of IN0.
Sets the gain of IN1.
Sets the gain of IN3 to IN2.
Sets the gain of IN4 to IN7.
1 ±20.48 V (default)
Reserved. Setting or clearing this bit has no effect.
0 = disables the internal reference. Disable the internal reference buffer by pulling REFIN to ground.
1 = enables the internal reference (default).
Conversion mode selection (see the Conversion Modes section).
0 = uses the warp mode for conversions with a time between conversion restriction.
1 = uses the normal mode for conversions (default).
BUSY/SDO2 Secondary data output control using the BUSY/SDO2 pin.
0 = enables the device
busy status when the CS pin is held high. On the CS falling edge, the MSB of Channel 1 is presented on the BUSY/SDO2 input and subsequent data is presented on the SCK falling edges.
1 = enables the device busy status only (default). All data is transmitted via the SDO pin on the SCK falling edge.
Rev. A | Page 29 of 32
ADAS3023
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
PIN 1
INDICATOR
0.50
BSC
30
31
0.30
0.25
0.18
EXPOSED
PAD
40
1
PIN 1
INDICATOR
*4.70
4.60 SQ
4.50
Data Sheet
1.00
0.95
0.85
SEATING
PLANE
ORDERING GUIDE
ADAS3023BCPZ
ADAS3023BCPZ-RL7
EVAL-ADAS3023EDZ
1 Z = RoHS Compliant Part.
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
TOP VIEW
0.45
0.40
0.35
21
20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
11
10
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 50. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-15)
Dimensions shown in millimeters
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Package Option
CP-40-15
CP-40-15
Rev. A | Page 30 of 32
Data Sheet
NOTES
ADAS3023
Rev. A | Page 31 of 32
ADAS3023
NOTES
Data Sheet
©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10942-0-2/14(A)
Rev. A | Page 32 of 32
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