Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad,
SPI Interface, 4.5 V to 5.5 V in TSSOP
Data Sheet
AD5024/AD5044/AD5064
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
VREFIN
VDD
AD5064-1
LDAC
INTERFACE
LOGIC AND
SHIFT
REGISTER
SYNC
DIN
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC B
INPUT
REGISTER
DAC
REGISTER
DAC C
INPUT
REGISTER
DAC
REGISTER
DAC D
VOUTA
DAC A
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
VOUTD
SDO
LDAC CLR
POWER-ON
RESET
POWER-DOWN
LOGIC
POR
GND
Figure 1. AD5064-1 Functional Equivalent and Pin Compatible with AD5666
VREFA VREFB
VDD
AD5024/
AD5044/
AD5064 LDAC
APPLICATIONS
BUFFER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC C
INPUT
REGISTER
DAC
REGISTER
DAC D
VOUTA
DAC A
SCLK
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
SYNC
INTERFACE
LOGIC AND
SHIFT
REGISTER
BUFFER
VOUTB
DAC B
BUFFER
VOUTC
DIN
BUFFER
POR
VREFC VREFD
GND
06803-001
LDAC CLR
VOUTD
POWER-DOWN
LOGIC
POWER-ON
RESET
Figure 2. AD5024/AD5044/AD5064 with Individual Reference Pins
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD5024/AD5044/AD5064/AD5064-1 are low power, quad
12-/14-/16-bit buffered voltage output nanoDAC® converters
that offer relative accuracy specifications of 1 LSB INL and 1 LSB
DNL with the AD5024/AD5044/AD5064 individual reference
pin and the AD5064-1 common reference pin options. The
AD5024/AD5044/AD5064/AD5064-1 can operate from a single
4.5 V to 5.5 V supply. The AD5024/AD5044/AD5064/AD5064-1
also offer a differential accuracy specification of ±1 LSB. The
parts use a versatile 3-wire, low power Schmitt trigger serial
interface that operates at clock rates up to 50 MHz and is compatible with standard SPI, QSPI™, MICROWIRE™, and DSP interface
standards. Integrated reference buffers and output amplifiers are
also provided on-chip. The AD5024/AD5044/AD5064/AD5064-1
incorporate a power-on reset circuit that ensures the DAC
output powers up to zero scale or midscale and remains there
until a valid write takes place to the device. The AD5024/AD5044/
AD5064/AD5064-1 contain a power-down feature that reduces
the current consumption of the device to typically 400 nA at 5 V
and provides software selectable output loads while in powerdown mode. Total unadjusted error for the parts is <2 mV.
1.
2.
3.
4.
Rev. F
BUFFER
INPUT
REGISTER
SCLK
06803-064
Low power quad 12-/14-/16-bit DAC, ±1 LSB INL
Pin compatible and performance upgrade to AD5666
Individual and common voltage reference pin options
Rail-to-rail operation
4.5 V to 5.5 V power supply
Power-on reset to zero scale or midscale
3 power-down functions and per-channel power-down
Hardware LDAC with software LDAC override function
CLR function to programmable code
SDO daisy-chaining option
14-/16-lead TSSOP
Internal reference buffer and internal output amplifier
Quad channel available in 14-/16-lead TSSOP packages.
16-bit accurate, 1 LSB INL.
High speed serial interface with clock speeds up to 50 MHz.
Reset to known output voltage (zero scale or midscale).
Table 1. Related Devices
Part No.
AD5666
AD5025/AD5045/AD5065
AD5062, AD5063
AD5061
AD5040/AD5060
Description
Quad,16-bit buffered DAC,
16 LSB INL, TSSOP
Dual, 16-bit buffered DACs,
1 LSB INL, TSSOP
16-bit nanoDAC, 1 LSB INL, SOT-23,
MSOP
16-bit nanoDAC, 4 LSB INL, SOT-23
14-/16-bit nanoDAC, 1 LSB INL,
SOT-23
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AD5024/AD5044/AD5064
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Amplifier ........................................................................ 19
Applications ....................................................................................... 1
Serial Interface ............................................................................ 19
Functional Block Diagrams ............................................................. 1
Shift Register ............................................................................... 19
General Description ......................................................................... 1
Modes of Operation ................................................................... 21
Product Highlights ........................................................................... 1
Power-On Reset .......................................................................... 22
Revision History ............................................................................... 2
Power-Down Modes .................................................................. 22
Specifications..................................................................................... 3
Clear Code Register ................................................................... 23
AC Characteristics ........................................................................ 4
LDAC Function .......................................................................... 23
Timing Characteristics ................................................................ 5
Power Supply Bypassing and Grounding ................................ 24
Absolute Maximum Ratings ............................................................ 7
Microprocessor Interfacing ....................................................... 25
ESD Caution .................................................................................. 7
Applications Information .............................................................. 26
Pin Configurations and Function Descriptions ........................... 8
Using a Reference as a Power Supply ....................................... 26
Typical Performance Characteristics ........................................... 10
Bipolar Operation....................................................................... 26
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 19
Using the AD5024/AD5044/AD5064/AD5064-1 with a
Galvanically Isolated Interface ................................................. 26
Digital-to-Analog Converter .................................................... 19
Outline Dimensions ....................................................................... 27
DAC Architecture ....................................................................... 19
Ordering Guide .......................................................................... 28
Reference Buffer ......................................................................... 19
REVISION HISTORY
6/13—Rev. E to Rev. F
Change to Standalone Mode Section ........................................... 21
5/11—Rev. D to Rev. E
Changes to Table 4 ............................................................................ 5
Changes to Figure 4 and Figure 5 ................................................... 6
8/10—Rev. C to Rev. D
Change to Minimum SYNC High Time (Single Channel
Update) Parameter, Table 4 ............................................................. 5
5/10—Rev. B to Rev. C
Changes to Power-On Reset Section ............................................ 22
6/09—Rev. A to Rev. B
Changes to Figure 1 .......................................................................... 1
3/09—Rev. 0 to Rev. A
Added 14-Lead TSSOP ...................................................... Universal
Added Figure 1; Renumbered Sequentially .................................. 1
Changes to Features Section, General Description Section,
Product Highlights Section, Figure 2, and Table 1....................... 1
Changes to Table 2 ............................................................................ 3
Changes to Timing Characteristics Section and Table 4 ............. 5
Added Circuit and Timing Diagrams Section and Figure 3 ....... 5
Added Figure 5...................................................................................6
Changes to Figure 4 ...........................................................................6
Added Figure 6...................................................................................8
Added Table 6; Renumbered Sequentially .....................................8
Changed Input Shift Register to Shift Register Throughout .......8
Changes to Table 7.............................................................................9
Changes to Typical Performance Characteristics Section ........ 10
Changes to Terminology Section ................................................. 17
Changes to Digital-to-Analog Converter Section, Reference
Buffer Section, Output Amplifier Section, Serial Interface
Section, Shift Register Section, and Table 8 ................................ 19
Changes to Figure 47, Figure 48, and Figure 49 Captions ........ 20
Added Modes of Operation Section, Daisy-Chaining Section,
Table 10, and Table 11 .................................................................... 21
Changes to Table 13 and Power-Down Mode Section .............. 22
Changes to Table 16 ....................................................................... 24
Changes to Figure 52 to Figure 55................................................ 25
Changes to Bipolar Operation Section and Figure 56 to
Figure 58 .......................................................................................... 26
Added Figure 59 ............................................................................. 27
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
8/08—Revision 0: Initial Version
Rev. F | Page 2 of 28
Data Sheet
AD5024/AD5044/AD5064
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD, unless otherwise specified. All specifications TMIN to
TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE 3
Resolution
Min
B Grade 1
Typ
16
14
12
Relative Accuracy (INL) 4
Differential Nonlinearity (DNL)4
Total Unadjusted Error
Offset Error4, 5
Offset Error Temperature
Coefficient4, 6
Full-Scale Error4
Gain Error4
Gain Temperature Coefficient4, 6
Power-Up Time 7
DC PSRR
REFERENCE INPUTS
Reference Input Range
Reference Current
LOGIC INPUTS
Input Current 8
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance6
Max
Unit
Conditions/Comments
AD5064/AD5064-1
AD5044
AD5024
AD5064/AD5064-1; TA = −40°C to
+105°C
AD5064/AD5064-1; TA = −40°C to
+125°C
AD5044
AD5024
±0.5
±1
±0.5
±4
Bits
Bits
Bits
LSB
±0.5
±2
±0.5
±4
LSB
±0.25
±0.12
±0.2
±1
±0.5
±1
±2
±1.8
±0.2
±2
±0.01
±0.005
±1
0
±0.2
±0.2
±2
±0.07
±0.05
±0.01
±0.005
±1
±1
±2
±1.8
VREF = 2.5 V, VDD = 5.5 V
40
40
40
40
40
40
µV/mA
µV
Due to single-channel, full-scale output
change, RL = 5 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
VDD
1
V
nF
RL = 5 kΩ, RL =100 kΩ, and RL = ∞
0
±0.07
±0.05
LSB
LSB
LSB
mV
mV
µV/°C
% FSR
% FSR
ppm
FSR/°C
µV
VDD
1
All 1s loaded to DAC register, VREF < VDD
VREF < VDD
0.5
0.5
Ω
100
100
kΩ
Output impedance tolerance ± 20 kΩ
1
1
kΩ
Output impedance tolerance ± 400 Ω
60
45
4.5
−92
60
45
4.5
−92
mA
mA
µs
dB
DAC = full scale, output shorted to GND
DAC = zero scale, output shorted to VDD
2.2
35
140
120
32
Reference Input Impedance
Min
16
DC Crosstalk4, 6
OUTPUT CHARACTERISTICS6
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Normal Mode
Power-Down Mode
Output Connected to
100 kΩ Network
Output Connected to
1 kΩ Network
Short-Circuit Current
Max
A Grade1, 2
Typ
VDD
50
2.2
35
160
140
120
32
±1
0.8
2.2
2.2
4
4
Rev. F | Page 3 of 28
VDD
50
V
µA
160
µA
kΩ
kΩ
±1
0.8
µA
V
V
pF
VDD ± 10%, DAC = full scale, VREF < VDD
Per DAC channel; individual reference
option
Single reference option
Individual reference option
Single reference option
AD5024/AD5044/AD5064
Parameter
LOGIC OUTPUTS (SDO) 9
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage
Current
High Impedance Output
Capacitance6
POWER REQUIREMENTS
VDD
IDD 10
Normal Mode
All Power-Down Modes 11
Min
Data Sheet
B Grade 1
Typ
Max
A Grade1, 2
Typ
Min
0.4
VDD − 1
Max
Unit
Conditions/Comments
0.4
V
ISINK = 2 mA
ISOURCE = 2 mA
±1
μA
VDD − 1
±0.002
±1
±0.002
7
7
4.5
5.5
4
0.4
4.5
6
2
30
4
0.4
pF
5.5
V
6
2
30
mA
µA
µA
DAC active, excludes load current
VIH = VDD, VIL = GND, Code = midscale
TA = −40°C to +105°C
TA = −40°C to +125°C
Temperature range is −40°C to +125°C, typical at 25°C.
A grade offered in AD5064 only.
3
Linearity and total unadjusted error are calculated using a reduced code range—AD5064/AD5064-1: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256;
AD5024: Code 32 to Code 4064. Output unloaded.
4
See the Terminology section.
5
Offset error calculated using a reduced code range—AD5064/AD5064-1: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Code 4064.
Output unloaded
6
Guaranteed by design and characterization; not production tested.
7
Time to exit power-down mode to normal mode; 32nd clock edge to 90% of DAC midscale value, output unloaded.
8
Current flowing into individual digital pins. VDD = 5.5 V; VREF = 4.096 V; Code = midscale.
9
AD5064-1 only.
10
Interface inactive. All DACs active. DAC outputs unloaded.
11
All four DACs powered down.
1
2
AC CHARACTERISTICS
VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD. All specifications TMIN to TMAX, unless otherwise
noted.
Table 3.
Parameter 1, 2
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Reference Feedthrough
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
AC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
Output Noise
1
2
3
Min
Typ
5.8
Max
8
Unit
µs
10.7
13
µs
1.5
3
−90
0.1
1.9
2
3.5
6
340
−80
64
60
6
V/µs
nV-sec
dB
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
kHz
dB
nV/√Hz
nV/√Hz
μV p-p
Conditions/Comments 3
¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, RL = 5 kΩ,
single-channel update
¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, RL = 5 kΩ, all channel
update
1 LSB change around major carry
VREF = 3 V ± 0.86 V p-p, frequency = 100 Hz to 100 kHz
VREF = 3 V ± 0.86 V p-p
VREF = 3 V ± 0.2 V p-p, frequency = 10 kHz
DAC code = 0x8400, frequency = 1 kHz
DAC code = 0x8400, frequency = 10 kHz
0.1 Hz to 10 Hz
Guaranteed by design and characterization; not production tested.
See the Terminology section.
Temperature range is −40°C to +125°C, typical at 25°C.
Rev. F | Page 4 of 28
Data Sheet
AD5024/AD5044/AD5064
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and
Figure 5. VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter 1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time (Single Channel Update)
Minimum SYNC High Time (All Channel Update)
SYNC Rising Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SCLK Falling Edge to LDAC Rising Edge
CLR Minimum Pulse Width Low
SCLK Falling Edge to LDAC Falling Edge
CLR Pulse Activation Time
SCLK Rising Edge to SDO Valid
SCLK Falling Edge to SYNC Rising Edge
SYNC Rising Edge to SCLK Rising Edge
SYNC Rising Edge to LDAC/CLR Falling Edge (Single Channel Update)
SYNC Rising Edge to LDAC/CLR Falling Edge (All Channel Update)
Power-up Time 4
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t8
t9
t10
t11
t12
t13
t14
t15 2, 3
t162
t172
t182
t182
Min
20
10
10
17
5
5
5
3
8
17
20
20
10
10
10.6
Typ
Max
30
22
5
8
2
8
4.5
Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested.
Daisy-chain mode only.
3
Measured with the load circuit of Figure 3. t15 determines the maximum SCLK frequency in daisy-chain mode. AD5064-1 only.
4
Time to exit power-down mode to normal mode of AD5024/AD5044/AD5064/AD5064-1, 32nd clock edge to 90% of DAC midscale value, with output unloaded.
1
2
Circuit and Timing Diagrams
2mA
VOH (MIN) + VOL (MAX)
2
CL
50pF
2mA
IOH
06803-002
TO OUTPUT
PIN
IOL
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. F | Page 5 of 28
Unit
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
µs
ns
ns
ns
µs
µs
µs
AD5024/AD5044/AD5064
Data Sheet
t1
t9
SCLK
t8
t2
t3
t4
t7
SYNC
t5
DIN
t6
DB31
DB0
t13
t10
LDAC1
t11
LDAC2
t12
CLR
06803-003
t14
VOUT
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 4. Serial Write Operation
SCLK
32
t8
64
t17
t4
t16
SYNC
t5
DIN
t6
DB31
DB0
DB0
DB31
INPUT WORD FOR DAC N + 1
INPUT WORD FOR DAC N
t15
DB31
SDO
UNDEFINED
DB0
INPUT WORD FOR DAC N
t18
t10
LDAC1
CLR
1IF
IN DAISY-CHAIN MODE, LDAC MUST BE USED ASYNCHRONOUSLY.
Figure 5. Daisy-Chain Timing Diagram
Rev. F | Page 6 of 28
t12
06803-004
t18
Data Sheet
AD5024/AD5044/AD5064
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to GND
Digital Input Voltage to GND
VOUT to GND
VREF to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ MAX)
TSSOP Package
Power Dissipation
θJA Thermal Impedance
Reflow Soldering Peak Temperature
Pb-Free
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
(TJ MAX − TA)/θJA
113°C/W
260°C
Rev. F | Page 7 of 28
AD5024/AD5044/AD5064
Data Sheet
LDAC
1
14
SCLK
SYNC
2
13
DIN
VDD
3
12
GND
VOUTA
4
AD5064-1
11
VOUTB
TOP VIEW
(Not to Scale)
10 VOUTD
VOUTC
5
POR
6
9
CLR
VREFIN
7
8
SDO
06803-065
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 6. 14-Lead TSSOP (RU-14)
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
LDAC
2
SYNC
3
VDD
4
5
6
VOUTA
VOUTC
POR
7
8
VREFIN
SDO
9
CLR
10
11
12
13
VOUTD
VOUTB
GND
DIN
14
SCLK
Description
LDAC can be operated in two modes, asynchronously and synchronously, as shown in Figure 4. Pulsing
this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows
all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode.
When daisy-chain mode is enabled, this pin cannot be tied permanently low; the LDAC pin should be
used in asynchronous LDAC update mode, as shown in Figure 5, and the LDAC pin must be brought
high after pulsing.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the
falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of
SYNC acts as an interrupt and the write sequence is ignored by the device.
Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to VDD
powers up all four DACs to midscale.
This is a common pin for reference input for DAC A, DAC B, DAC C, and DAC D.
Serial Data Output. Can be used to daisy-chain a number of AD5064-1 devices together. The serial data
is transferred on the rising edge of SCLK and is valid on the falling edge of the clock.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the shift register on the
falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 50 MHz.
Rev. F | Page 8 of 28
Data Sheet
AD5024/AD5044/AD5064
LDAC
1
16 SCLK
SYNC
2
15 DIN
3
4
VREF A
5
VOUTA
6
VOUTC
7
POR
8
AD5024/
AD5044/
AD5064
TOP VIEW
(Not to Scale)
14 GND
13 VOUTB
12 VOUTD
11 VREF D
10 CLR
9
VREF C
06803-005
VDD
VREF B
Figure 7. 16-Lead TSSOP (RU-16) Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
Mnemonic
LDAC
2
SYNC
3
VDD
4
5
6
7
8
VREFB
VREFA
VOUTA
VOUTC
POR
9
10
VREFC
CLR
11
12
13
14
15
VREFD
VOUTD
VOUTB
GND
DIN
16
SCLK
Description
LDAC can be operated in two modes, asynchronously and synchronously, as shown in Figure 4. Pulsing
this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows
all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the
falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of
SYNC acts as an interrupt and the write sequence is ignored by the device.
Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
DAC B Reference Input. This is the reference voltage input pin for DAC B.
DAC A Reference Input. This is the reference voltage input pin for DAC A.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Power-On Reset. Tying this pin to GND powers up the part to 0 V. Tying this pin to VDD powers up the
part to midscale.
DAC C Reference Input. This is the reference voltage input pin for DAC C.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
DAC D Reference Input. This is the reference voltage input pin for DAC D.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the shift register on the
falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 50 MHz.
Rev. F | Page 9 of 28
AD5024/AD5044/AD5064
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–1.0
512
16,640
32,768
48,896
VDD = 5V
VREF = 4.096V
TA = 25°C
06803-022
DNL (LSB)
VDD = 5V
= 4.096V
V
0.8 T REF
A = 25°C
06803-019
INL (LSB)
1.0
–0.8
–1.0
512
65,024
16,640
DAC CODE
48,896
65,024
Figure 11. AD5064/AD5064-1 DNL
Figure 8. AD5064/AD5064-1 INL
1.0
1.0
VDD = 5V
0.8 VREF = 4.096V
TA = 25°C
0.6
0.6
0.4
0.2
0.2
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–1.0
512
1024
1536
2048
2560
3072
3584
06803-023
DNL (LSB)
0.4
0
VDD = 5V
VREF = 4.096V
TA = 25°C
0.8
06803-020
INL (LSB)
32,768
DAC CODE
–0.8
–1.0
0
4096
4096
8192
12,288
16,384
12,288
16,384
DAC CODE
DAC CODE
Figure 12. AD5044 DNL
Figure 9. AD5044 INL
1.00
1.0
VDD = 5V
VREF = 4.096V
TA = 25°C
0.8
VDD = 5V
VREF = 4.096V
TA = 25°C
0.75
0.6
0.50
0.25
DNL (LSB)
0.2
0
–0.2
0
–0.25
–0.4
–0.50
–0.6
–0.8
–1.0
0
512
1024
1536
2048
2560
3072
3584
–1.00
4096
06803-024
–0.75
06803-021
INL (LSB)
0.4
0
4096
8192
DAC CODE
DAC CODE
Figure 13. AD5024 DNL
Figure 10. AD5024 INL
Rev. F | Page 10 of 28
Data Sheet
AD5024/AD5044/AD5064
0.20
1.2
VDD = 5V
VREF = 4.096V
TA = 25°C
0.15
1.0
0.8
0.10
0.6
0.4
TUE (mV)
0.05
TUE (mV)
TA = 25°C
0
–0.05
0.2
MAX TUE @ VDD = 5.5V
0
MIN TUE @ VDD = 5.5V
–0.2
–0.15
–0.8
06803-025
–0.6
–0.20
512
16,640
32,768
48,896
06803-028
–0.4
–0.10
–1.0
–1.2
2.0
65,024
2.5
3.0
DAC CODE
Figure 14. Total Unadjusted Error (TUE)
5.0
5.5
0.010
GAIN ERROR (%FSR)
DAC A
MAX INL ERROR @ VDD = 5.5V
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
MIN INL ERROR @ VDD = 5.5V
0.005
0
DAC B
DAC D
DAC C
–0.005
2.5
3.0
3.5
4.0
4.5
5.0
VDD = 5.5V
VREF = 4.096V
–0.015
–60 –40 –20
5.5
06803-029
–0.010
0
Figure 15. INL vs. Reference Input Voltage
40
60
80
100
120
140
Figure 18. Gain Error vs. Temperature
1.6
0.6
VDD = 5.5V
VREF = 4.096V
0.5
DAC C
OFFSET ERROR (mV)
0.4
MAX DNL ERROR @ VDD = 5.5V
MIN DNL ERROR @ VDD = 5.5V
0.3
0.2
0.1
DAC D
0
–0.1
DAC A
–0.2
3.0
3.5
4.0
4.5
5.0
06803-030
DAC B
06803-027
1.4 TA = 25°C
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
2.0
2.5
20
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
DNL ERROR (LSB)
4.5
0.015
TA = 25°C
0.6
0.4
–1.4
–1.6
2.0
4.0
Figure 17. TUE vs. Reference Input Voltage
06803-026
INL ERROR (LSB)
1.6
1.4
1.2
1.0
0.8
3.5
REFERENCE VOLTAGE (V)
–0.3
–0.4
–60
5.5
–40
–20
0
20
40
60
80
100
TEMPERATURE (ºC)
REFERENCE VOLTAGE (V)
Figure 16. DNL vs. Reference Input Voltage
Figure 19. Offset Error vs. Temperature
Rev. F | Page 11 of 28
120
140
AD5024/AD5044/AD5064
Data Sheet
10
0.2
VDD = 5.5V
VREF = 4.096
TA = 25°C
VREF = 4.096V
TA = 25°C
8
IDD (mA)
ERROR (%FSR)
0.1
GAIN ERROR
0
6
4
FULL-SCALE ERROR
–0.1
06803-031
2
4.75
5.00
5.25
0
0
5.50
10,000
20,000
30,000
VDD (V)
40,000
50,000
60,000
06803-034
–0.2
4.50
70,000
DAC CODE
Figure 20. Gain Error and Full-Scale Error vs. Supply Voltage
Figure 23. Supply Current vs. Code
10
0.12
VDD = 5.5V
VREF = 4.096
CODE = MIDSCALE
VREF = 4.096V
TA = 25°C
8
IDD (mA)
OFFSET ERROR (mV)
0.09
0.06
6
4
0.03
0
4.50
4.75
5.00
5.25
0
–40
5.50
–20
0
20
VDD (V)
35
30
80
100
120
Figure 24. Supply Current vs. Temperature
10
MEAN: 4.11699
SD: 0.0544403
LIMITS: LOW: 3 HIGH: 4.3
CPk: LOW: 6.84 HIGH: 1.12
VREF = 4.096V
TA = 25°C
CODE = MIDSCALE
VDD = 5.5V
VREF = 4.096
TA = 25°C
8
IDD (mA)
25
20
15
6
4
10
2
0
3.9
4.0
4.1
4.2
IDD POWER-UP (mA)
4.3
0
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
SUPPLY VOLTAGE (V)
Figure 25. Supply Current vs. Supply Voltage
Figure 22. IDD Histogram, VDD = 5.0 V
Rev. F | Page 12 of 28
5.4
5.5
06803-036
5
06803-033
HITS
60
TEMPERATURE (°C)
Figure 21. Offset Error Voltage vs. Supply Voltage
40
40
06803-035
06803-032
2
Data Sheet
10
AD5024/AD5044/AD5064
VREF = 4.096V
TA = 25°C
OUTPUT UNLOADED
VDD = 5.5V
VREF = 4.096
TA = 25°C
VDD
8
IDD (mA)
6
1
DAC A
4
3
06803-040
2
0
1
2
3
4
06803-037
0
5
DIGITAL INPUT VOLTAGE (V)
CH1 2V
Figure 26. Supply Current vs. Digital Input Voltage
CH3 2V
M2ms
T 20.4%
A CH1
2.52V
Figure 29. Power-On Reset to Midscale
5.0
CH1 = SCLK
4.5
OUTPUT VOLTAGE (V)
4.0
1
3.5
VDD = 5V, VREF = 4.096V
TA = 25ºC
1/4 SCALE TO 3/4 SCALE
3/4 SCALE TO 1/4 SCALE
OUTPUT LOADED WITH 5kΩ
AND 200pF TO GND
3.0
2.5
2.0
VDD = 5V
POWER-UP TO MIDSCALE
OUTPUT UNLOADED
CH2 = VOUT
1.5
2
06803-038
0.5
0
06803-041
1.0
0
2
4
6
8
10
12
14
CH1 5V
CH2 500mV
TIME (µs)
M2µs
T 55%
A CH2
1.2V
Figure 30. Exiting Power-Down to Midscale
Figure 27. Settling Time
6
VREF = 4.096V
TA = 25°C
VDD = 5V
VREF = 4.096V
TA = 25°C
CODE = 0x8000 TO 0x7FFF
OUTPUT UNLOADED WITH 5kΩ
AND 200pF
5
GLITCH AMPLITUDE (mV)
VDD
1
DAC A
3
4
3
2
1
0
–2
06803-039
CH1 2V
CH3 2V
M2ms
T 20.4%
A CH1
06803-042
–1
–3
2.52V
0
2.5
5.0
7.5
TIME (μs)
Figure 31. Digital-to-Analog Glitch Impulse
Figure 28. Power-On Reset to 0 V
Rev. F | Page 13 of 28
10.0
AD5024/AD5044/AD5064
Data Sheet
0
7
VDD = 5V, VREF = 4.096V
TA = 25ºC
6
–20
4
VOUT LEVEL (dB)
–30
3
2
1
0
–40
–50
–60
–70
–1
–80
06803-043
–2
–3
0
2.5
5.0
7.5
06803-046
GLITCH AMPLITUDE (mV)
5
–4
VDD = 5V,
TA = 25ºC
DAC LOADED WITH MIDSCALE
VREF = 3.0V ± 200mV p-p
–10
–90
–100
10.0
5
20
10
TIME (μs)
Figure 32. Analog Crosstalk
55
9
10
24
VDD = 5V, VREF = 3.0V
22 TA = 25°C
1/4 SCALE TO 3/4 SCALE
WITHIN ±1LSB
20
VDD = 5V, VREF = 4.096V
TA = 25°C
5
4
18
SETTLING TIME (μs)
3
2
1
0
16
14
12
10
–1
8
06803-044
–2
–3
0
2.5
5.0
7.5
06803-047
GLITCH AMPLITUDE (mV)
50
Figure 35. Total Harmonic Distortion
7
6
–4
30
40
FREQUENCY (kHz)
6
4
10.0
0
1
2
3
TIME (μs)
4
5
6
7
8
CAPACITANCE (nF)
Figure 33. DAC-to-DAC Crosstalk
Figure 36. Settling Time vs. Capacitive Load
VDD = 5V, VREF = 4.096V
TA = 25ºC
DAC LOADED WITH MIDSCALE
CLR
1μV/DIV
1
DAC A
2
4s/DIV
CH1 5V
Figure 34. 0.1 Hz to 10 Hz Output Noise Plot
06803-048
06803-045
VDD = 5V
VREF = 4.096V
TA = 25ºC
CH2 2V
M2µs
T 11%
Figure 37. Hardware CLR
Rev. F | Page 14 of 28
A CH1
2.5V
Data Sheet
AD5024/AD5044/AD5064
10
0.10
0.08
0
CODE = MIDSCALE
VDD = 5V, VREF = 4.096V
0.06
0.04
∆VOUT (V)
–20
–30
0.02
0
–0.02
–0.04
–40
CH A
CH B
CH C
CH D
3dB POINT
–0.06
06803-049
–50
–60
10
100
1000
06803-052
ATTENUATION (dB)
–10
–0.08
–0.10
–25
10000
–20
–15
–10
FREQUENCY (kHz)
–5
0
10
15
20
25
30
Figure 41. Typical Current Limiting Plot
Figure 38. Multiplying Bandwidth
5.0
TA = 25°C
VDD = 5V, VREF = 4.096V
4.5
DAC A 295mV p-p
4.0
OUTPUT VOLTAGE (V)
5
IOUT (mA)
3.5
3.0
VDD = 5V, VREF = 4.096V
TA = 25°C
1/4 SCALE TO 3/4 SCALE
3/4 SCALE TO 1/4 SCALE
OUTPUT LOADED WITH 5kΩ
AND 200pF TO GND
2.5
2.0
1.5
06803-050
0.5
0
06803-053
1.0
0
2
4
6
8
10
12
14
CH1 50mV
CH2 5V
TIME (µs)
A CH2
1.2V
Figure 42. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale,
No Load
Figure 39. Typical Output Slew Rate
0.0010
0.0008
M4µs
T 8.6%
TA = 25°C
VDD = 5V, VREF = 4.096V
CODE = MIDSCALE
VDD = 5V, VREF = 4.096V
DAC A 200mV p-p
0.0006
0.0002
0
–0.0002
–0.0006
–0.0008
–25
SCLK
–20
–15
–10
–5
0
5
10
15
20
25
CH1 50mV
30
CURRENT (mA)
Figure 40. Typical Output Load Regulation
CH2 5V
M4µs
T 8.6%
A CH2
06803-054
–0.0004
06803-051
∆VOLTAGE (V)
0.0004
1.2V
Figure 43. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale,
5 kΩ/200 pF Load
Rev. F | Page 15 of 28
AD5024/AD5044/AD5064
Data Sheet
VDD = 5V,VREF = 4.096V
TA = 25°C
TA = 25°C
VDD = 5V, VREF = 4.096V
06803-055
SCLK
CH1 20mV
CH2 5V
M4µs
T 8.6%
A CH2
06803-056
DAC A 170mV p-p
DAC A 129mV p-p
SCLK
1.2V
CH1 20mV
Figure 44. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale,
No Load
CH2 5V
M4µs
T 8.6%
A CH2
1.2V
Figure 45. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale,
5 kΩ/200 pF Load
Rev. F | Page 16 of 28
Data Sheet
AD5024/AD5044/AD5064
TERMINOLOGY
Relative Accuracy (INL)
For the DAC, relative accuracy, or integral nonlinearity (INL),
is a measure of the maximum deviation in LSBs from a straight
line passing through the endpoints of the DAC transfer function.
Figure 8, Figure 9, and Figure 10 show plots of typical INL vs.
code.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in decibels. VREF is held at 2.5 V, and VDD is varied by ±10%.
Measured with VREF < VDD.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Figure 11,
Figure 12, and Figure 13 show plots of typical DNL vs. code.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.
Offset Error
Offset error is a measure of the difference between the actual
VOUT and the ideal VOUT, expressed in millivolts in the linear
region of the transfer function. Offset error is calculated using
a reduced code range—AD5064/AD5604-1: Code 512 to Code
65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to
Code 4064, with output unloaded. Offset error can be negative or
positive and is expressed in millivolts.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in microvolts per milliamp.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Offset Error Temperature Coefficient
Offset error temperature coefficient is a measure of the change
in offset error with a change in temperature. It is expressed in
microvolts per degree Celsius.
Gain Temperature Coefficient
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in parts per million of
full-scale range per degree Celsius.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be VREF − 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range. Measured with VREF < VDD.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nanovoltseconds and is measured when the digital input code is changed
by 1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 31.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is, LDAC is high). It is expressed in
decibels.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device, but it is measured when the DAC is not being written
to (SYNC held high). It is specified in nanovolt-seconds and
measured with one simultaneous data and clock pulse loaded
to the DAC.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nanovolt-seconds.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s or vice versa) while keeping LDAC
high, and then pulsing LDAC low and monitoring the output of
the DAC whose digital code has not changed. The area of the
glitch is expressed in nanovolt-seconds.
Rev. F | Page 17 of 28
AD5024/AD5044/AD5064
Data Sheet
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
LDAC low and monitoring the output of another DAC. The
energy of the glitch is expressed in nanovolt-seconds.
Multiplying Bandwidth
The multiplying bandwidth is a measure of the finite bandwidth
of the amplifiers within the DAC. A sine wave on the reference
(with full-scale code loaded to the DAC) appears on the output.
The multiplying bandwidth, expressed in kilohertz, is the
frequency at which the output amplitude falls to 3 dB below
the input.
Total Harmonic Distortion (THD)
Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measure of the harmonics present on the DAC output. It is
measured in decibels.
Rev. F | Page 18 of 28
Data Sheet
AD5024/AD5044/AD5064
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
OUTPUT AMPLIFIER
The AD5024/AD5044/AD5064/AD5064-1 are single 12-/14-/
16-bit, serial input, voltage output DACs with an individual
reference pin. The AD5064-1 model (see the Ordering Guide)
is a 16-bit, serial input, voltage output DAC that is identical to
other AD5064 models but with a single reference pin for all
DACs. The parts operate from supply voltages of 4.5 V to 5.5 V.
Data is written to the AD5024/AD5044/AD5064/AD5064-1 in a
32-bit word format via a 3-wire serial interface. The AD5024/
AD5044/AD5064/AD5064-1 incorporate a power-on reset circuit
that ensures that the DAC output powers up to a known output
state. The devices also have a software power-down mode that
reduces the typical current consumption to typically 400 nA.
The output buffer amplifier can generate rail-to-rail voltages
on its output, which gives an output range of 0 V to VDD. The
amplifier is capable of driving a load of 5 kΩ in parallel with
200 pF to GND. The slew rate is 1.5 V/µs with a ¼ to ¾ scale
settling time of 5.8 µs.
SERIAL INTERFACE
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
D
VOUT = VREFIN ×  N 
2 
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register (0 to 65,535 for the 16-bit AD5064).
N is the DAC resolution.
DAC ARCHITECTURE
The DAC architecture of the AD5064 consists of two matched
DAC sections. A simplified circuit diagram is shown in Figure 46.
The four MSBs of the 16-bit data word are decoded to drive
15 switches, E1 to E15. Each of these switches connects one of
15 matched resistors to either GND or the VREF buffer output.
The remaining 12 bits of the data-word drive the S0 to S11
switches of a 12-bit voltage mode R-2R ladder network.
VOUT
2R
2R
2R
2R
2R
2R
2R
S0
S1
S11
E1
E2
E15
12-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
06803-006
VREF
Figure 46. DAC Ladder Structure
REFERENCE BUFFER
The AD5024/AD5044/AD5064/AD5064-1 operate with an external reference. For most models, each DAC has a dedicated voltage
reference pin. The AD5064-1 model has a single voltage reference
pin for all DACs. The reference input pin has an input range of
2.2 V to VDD. This input voltage is then buffered internally to
provide a reference for the DAC core.
The AD5024/AD5044/AD5064/AD5064-1 have a 3-wire serial
interface (SYNC, SCLK, and DIN) that is compatible with SPI,
QSPI, and MICROWIRE interface standards as well as most
DSPs. See Figure 4 for a timing diagram of a typical write
sequence. The AD5064-1 model contains an SDO pin to allow
the user to daisy-chain multiple devices together (see the DaisyChaining section).
SHIFT REGISTER
The AD5024/AD5044/AD5064/AD5064-1 shift register is 32 bits
wide. The first four bits are don’t cares. The next four bits are the
command bits, C3 to C0 (see Table 8), followed by the 4-bit
DAC address bits, A3 to A0 (see Table 9), and finally the bit
data-word. The data-word comprises 12-bit, 14-bit, or 16-bit input
code, followed by eight, six, or four don’t care bits for the AD5024,
AD5044, and AD5064/AD5064-1, respectively (see Figure 47,
Figure 48, and Figure 49). These data bits are transferred to the
DAC register on the 32nd falling edge of SCLK. Commands can be
executed on individually selected DAC channels or on all DACs.
Table 8. Command Definitions
C3
0
0
0
0
0
0
0
0
1
1
1
1
Command
C2 C1
0
0
0
0
0
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
C0
0
1
0
1
0
1
0
1
0
1
1
Description
Write to Input Register n
Update DAC Register n
Write to Input Register n, update all
(software LDAC)
Write to and update DAC Channel n
Power down/power up DAC
Load clear code register
Load LDAC register
Reset (power-on reset)
Set up DCEN register1 (daisy-chain enable)
Reserved
Reserved
Available in the AD5064-1 14-lead TSSOP package only.
Table 9. Address Commands
A3
0
0
0
0
1
Rev. F | Page 19 of 28
Address (n)
A2
A1
0
0
0
0
0
1
0
1
1
1
A0
0
1
0
1
1
Selected DAC Channel
DAC A
DAC B
DAC C
DAC D
All DACs
AD5024/AD5044/AD5064
Data Sheet
DB31 (MSB)
X
X
DB0 (LSB)
X
X
C3
C2
C1
C0
A3
A2
A1
A0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
COMMAND BITS
06803-009
DATA BITS
ADDRESS BITS
Figure 47. AD5024 Shift Register Content
DB31 (MSB)
X
X
DB0 (LSB)
X
X
C3
C2
C1
C0
A3
A2
A1
A0
D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
COMMAND BITS
06803-008
DATA BITS
ADDRESS BITS
Figure 48. AD5044 Shift Register Content
DB31 (MSB)
X
X
X
C3
C2
C1
C0
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
COMMAND BITS
06803-007
DATA BITS
ADDRESS BITS
Figure 49. AD5064/AD5064-1 Shift Register Content
SCLK
SYNC
DIN
DB31
DB31
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 32ND FALLING EDGE
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 32ND FALLING EDGE
Figure 50. SYNC Interrupt Facility
Rev. F | Page 20 of 28
06803-010
X
DB0 (LSB)
Data Sheet
AD5024/AD5044/AD5064
MODES OF OPERATION
There are three main modes of operation: standalone mode
where a single device is used, daisy-chain mode for a system
that contains several DACs, and power-down mode when the
supply current falls to 0.4 µA at 5 V.
Standalone Mode
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5024/AD5044/AD5064/AD5064-1
compatible with high speed DSPs. On the 32nd falling clock edge,
the last data bit is clocked in and the programmed function is
executed, that is, an LDAC-dependent change in DAC register
contents and/or a change in the mode of operation. At this
stage, the SYNC line can be kept low or be brought high. In
either case, it must be brought high for a minimum of 3 µs
(single channel, see Table 4, t8 parameter) before the next write
sequence so that a falling edge of SYNC can initiate the next
write sequence. SYNC should be idled at rails between write
sequences for even lower power operation of the part.
SYNC Interrupt
In a normal write sequence, the SYNC line is kept low for at
least 32 falling edges of SCLK, and the DAC is updated on the
32nd falling edge. However, if SYNC is brought high before the
32nd falling edge, this acts as an interrupt to the write sequence.
The write sequence is seen as invalid. Neither an update of the
DAC register contents nor a change in the operating mode
occurs (see Figure 50).
Daisy-Chaining
For systems that contain several DACs the SDO pin can be
used to daisy-chain several devices together and provide serial
readback.
The daisy-chain mode is enabled through a software executable
daisy-chain enable (DCEN) command. Command 1000 is
reserved for this DCEN function (see Table 8). The daisy-chain
mode is enabled by setting Bit DB1 in the DCEN register. The
default setting is standalone mode, where DB1 = 0.
Table 10 shows how the state of the bit corresponds to the mode
of operation of the device.
Table 10. DCEN (Daisy-Chain Enable) Register
DB1
0
1
DB0
X
X
Description
Standalone mode (default)
DCEN mode
The SCLK is continuously applied to the shift register when
SYNC is low. If more than 32 clock pulses are applied, the data
ripples out of the shift register and appears on the SDO line.
This data is clocked out on the rising edge of SCLK and is valid
on the falling edge. By connecting this line to the DIN input on
the next DAC in the chain, a daisy-chain interface is constructed.
Each DAC in the system requires 32 clock pulses; therefore, the
total number of clock cycles must equal 32N, where N is the
total number of devices that are updated. If SYNC is taken high
at a clock that is not a multiple of 32, it is considered an invalid
frame and the data is discarded.
When the serial transfer to all devices is complete, SYNC is
taken high. This prevents any further data from being clocked
into the shift register.
In daisy-chain mode, the LDAC pin cannot be tied permanently
low. The LDAC pin must be used in asynchronous LDAC update
mode, as shown in Figure 5. The LDAC pin must be brought
high after pulsing. This allows all DAC outputs to simultaneously update.
The serial clock can be continuous or a gated clock. A continuous
SCLK source can be used only if SYNC can be held low for the
correct number of clock cycles. In gated clock mode, a burst
clock containing the exact number of clock cycles must be used,
and SYNC must be taken high after the final clock to latch the data.
Table 11. 32-Bit Shift Register Contents for Daisy-Chain Enable
MSB
DB31 to DB28
X
Don’t cares
DB27
1
DB26
DB25
DB24
0
0
0
Command bits (C3 to C0)
DB23
X
DB22
DB21
DB20
X
X
X
Address bits (A3 to A0)
Rev. F | Page 21 of 28
DB19 to DB2
X
Don’t cares
LSB
DB1
DB0
1/0
X
DCEN register
AD5024/AD5044/AD5064
Data Sheet
The AD5024/AD5044/AD5064/AD5064-1 contain a power-on
reset circuit that initializes the registers to their default values
and controls the output voltage during power-up. By connecting
the POR pin low, the AD5024/AD5044/AD5064/AD5064-1
output powers up to zero scale. Note that this is outside the
linear region of the DAC; by connecting the POR pin high, the
AD5024/AD5044/AD5064/AD5064-1 output powers up to
midscale. The output remains powered up at this level until a
valid write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the
output of the DAC while it is in the process of powering up.
There is also a software executable reset function that resets the
DAC to the power-on reset code. Command 0111 is designated
for this reset function (see Table 8). Any events on LDAC or
CLR during power-on reset are ignored. The power-on reset
circuit is triggered when VDD passes 2.6 V approximately and
takes 50 µs to complete. No writes to the AD5024/AD5044/
AD5064/AD5064-1 should take place during this time. For
applications which have a slow VDD ramp time (for example,
more than 2 ms to 3ms), it is recommended that a software
reset command is written when the power supplies have
reached their final value.
Any or all DACs (DAC D to DAC A) can be powered down to
the selected mode by setting the corresponding four bits (DB3,
DB2, DB1, DB0) to 1. See Table 13 for the contents of the shift
register during power-down/power-up operation.
When both Bit DB9 and Bit D8 in the shift register are set to 0,
the part works normally with its normal power consumption of
4 mA at 5 V. However, for the three power-down modes, the
supply current falls to 0.4 μA at 5 V. Not only does the supply
current fall, but the output stage is also internally switched from
the output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode. There are three
different power-down options. The output is connected internally to GND through either a 1 kΩ or a 100 kΩ resistor, or it is
left open-circuited (three-state). The output stage is illustrated in
Figure 51.
DAC
AMPLIFIER
VOUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
POWER-DOWN MODES
The AD5024/AD5044/AD5064/AD5064-1 contain three
separate power-down modes. Command 0100 is designated for
the power-down function (see Table 8). These power-down
modes are software-programmable by setting two bits, Bit DB9
and Bit DB8, in the shift register. Table 12 shows how the state of
the bits corresponds to the mode of operation of the device.
Table 12. Modes of Operation
DB9
0
DB8
0
0
1
1
1
0
1
06803-011
POWER-ON RESET
Figure 51. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The DAC register can be
updated while the device is in power-down mode. The time to
exit power-down is typically 4.5 µs for VDD = 5 V (see Figure 30).
Operating Mode
Normal operation
Power-down modes:
1 kΩ to GND
100 kΩ to GND
Three-state
Table 13. 32-Bit Shift Register Contents for Power-Up/Power-Down Function
MSB
DB31
to
DB28
X
Don’t
cares
LSB
DB27 DB26 DB25 DB24
0
1
0
0
Command bits (C3 to C0)
DB23 DB22 DB21 DB20
X
X
X
X
Address bits (A3 to A0)—
don’t cares
DB19
to
DB10
X
Don’t
cares
Rev. F | Page 22 of 28
DB9 DB8
PD1
PD0
Powerdown mode
DB7
to
DB4
X
Don’t
cares
DB3
DB2
DB1
DB0
DAC D DAC C DAC B DAC A
Power-down/power-up channel
selection—set bit to 1 to select
Data Sheet
AD5024/AD5044/AD5064
CLEAR CODE REGISTER
Synchronous LDAC: After new data is read, the DAC registers
are updated on the falling edge of the 32nd SCLK pulse, provided
LDAC is held low.
The AD5024/AD5044/AD5064/AD5064-1 have a hardware
CLR pin that is an asynchronous clear input. The CLR input is
falling edge sensitive. Bringing the CLR line low clears the
contents of the input register and the DAC registers to the data
contained in the user-configurable CLR register and sets the
analog outputs accordingly (see Table 14). This function can be
used in system calibration or reset to load zero scale, midscale,
or full scale to all channels together. Note that zero scale and full
scale are outside the linear region of the DAC. These clear code
values are user-programmable by setting two bits, Bit DB1 and
Bit DB0, in the shift register (see Table 14). The default setting
clears the outputs to 0 V. Command 0101 is designated for
loading the clear code register (see Table 8).
Asynchronous LDAC: The outputs are not updated at the same
time that the input registers are written to. When LDAC is
pulsed low, the DAC registers are updated with the contents of
the input registers.
Software LDAC Function
Alternatively, the outputs of all DACs can be updated simultaneously or individually using the software LDAC function by
writing to Input Register n and updating all DAC registers.
Command 0010 is reserved for this software LDAC function.
Writing to the DAC using Command 0110 loads the 4-bit
LDAC register (DB3 to DB0). The default for each channel
is 0; that is, the LDAC pin works normally. Setting the bits to 1
updates the DAC channel regardless of the state of the hardware
LDAC pin, so that it effectively sees the hardware LDAC pin as
being tied low (see Table 15 for the LDAC register mode of
operation.) This flexibility is useful in applications where the
user wants to simultaneously update select channels while the
remainder of the channels are synchronously updating.
Table 14. Clear Code Register
DB1 (CR1)
0
0
1
1
DB0 (CR0)
0
1
0
1
Clears to Code
0x0000
0x8000
0xFFFF
No operation
The part exits clear code mode on the 32nd falling edge of the
next write to the part. If hardware CLR pin is activated during a
write sequence, the write is aborted.
Table 15. LDAC Overwrite Definition
Load LDAC Register
The CLR pulse activation time, which is the falling edge of CLR
to when the output starts to change, is typically 10.6 μs. See
Table 16 for contents of the shift register while loading the clear
code register.
LDAC Bits
(DB3 to DB0)
0
1
LDAC FUNCTION
LDAC Pin
LDAC Operation
1 or 0
X1
Determined by the LDAC pin.
DAC channels update, overrides
the LDAC pin. DAC channels see
LDAC as 0.
Hardware LDAC Pin
1
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin, as shown in Figure 4. LDAC can be
permanently low or pulsed. There are two methods of using the
hardware LDAC pin, synchronously and asynchronously.
X = don’t care.
The LDAC register gives the user extra flexibility and control
over the hardware LDAC pin (see Table 17). Setting the LDAC
bits (DB0 to DB3) to 0 for a DAC channel means that this
channel’s update is controlled by the hardware LDAC pin.
Table 16. 32-Bit Shift Register Contents for Clear Code Function
MSB
DB31 to DB28
X
Don’t cares
DB27
DB26
DB25
DB24
0
1
0
1
Command bits (C3 to C0)
DB23
X
DB22
DB21
DB20
X
X
X
Address bits (A3 to A0)
DB19 to DB2
X
Don’t cares
LSB
DB1
DB0
1/0
1/0
Clear code register
(CR1 to CR0)
Table 17. 32-Bit Shift Register Contents for LDAC Overwrite Function
MSB
DB31 to
DB28
X
Don’t
cares
LSB
DB27 DB26 DB25 DB24
0
1
1
0
Command bits (C3 to C0)
DB23 DB22 DB21 DB20
X
X
X
X
Address bits (A3 to A0)—
don’t cares
Rev. F | Page 23 of 28
DB19
to DB4
X
Don’t
cares
DB3
DB2
DB1
DB0
DAC D
DAC C
DAC B
DAC A
Setting LDAC bits to 1 overrides LDAC pin
AD5024/AD5044/AD5064
Data Sheet
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board (PCB) containing the AD5024/AD5044/
AD5064/AD5064-1 should have separate analog and digital
sections. If the AD5024/AD5044/AD5064/AD5064-1 are in a
system where other devices require an AGND-to-DGND
connection, the connection should be made at one point only.
This ground point should be as close as possible to the
AD5024/AD5044/AD5064/AD5064-1.
The power supply to the AD5024/AD5044/AD5064/AD5064-1
should be bypassed with 10 µF and 0.1 µF capacitors. The capacitors should be as physically close as possible to the device, with
the 0.1 µF capacitor ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. It is important that the
0.1 µF capacitor have low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of common
ceramic types of capacitors. This 0.1 µF capacitor provides a low
impedance path to ground for high frequencies caused by
transient currents due to internal logic switching.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals should
be shielded from other parts of the board by digital ground. Avoid
crossover of digital and analog signals, if possible. When traces
cross on opposite sides of the board, ensure that they run at right
angles to each other to reduce feedthrough effects through the
board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the
ground plane only and the signal traces are placed on the solder
side. However, this is not always possible with a 2-layer board.
Rev. F | Page 24 of 28
Data Sheet
AD5024/AD5044/AD5064
AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSPBF53x Interface
Figure 52 shows a serial interface between the AD5024/AD5044/
AD5064/AD5064-1 and the Blackfin® ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dualchannel synchronous serial ports, SPORT1 and SPORT0, for
serial and multiprocessor communications. Using SPORT0 to
connect to the AD5024/AD5044/AD5064/AD5064-1, the setup
for the interface is as follows: DT0PRI drives the DIN pin of the
AD5024/AD5044/AD5064/AD5064-1, and TSCLK0 drives the
SCLK of the parts. The SYNC pin is driven from TFS0.
TSCLK0
SYNC
DIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 54 shows a serial interface between the AD5024/AD5044/
AD5064/AD5064-1 and the 80C51/80L51 microcontroller. The
setup for the interface is as follows: TxD of the 80C51/80L51
drives SCLK of the AD5024/AD5044/AD5064/AD5064-1, and
RxD drives the serial data line of the part. The SYNC signal is
again derived from a bit-programmable pin on the port. In this
case, Port Line P3.3 is used. When data is to be transmitted to the
AD5024/AD5044/AD5064/AD5064-1, P3.3 is taken low. The
80C51/80L51 transmit data in 8-bit bytes only; thus, only eight
falling clock edges occur in the transmit cycle. To load data to
the DAC, P3.3 is left low after the first eight bits are transmitted,
and a second write cycle is initiated to transmit the second byte of
data. P3.3 is taken high following the completion of this cycle.
The 80C51/80L51 output the serial data in a format that has the
LSB first. The AD5024/AD5044/AD5064/AD5064-1 must
receive data with the MSB first. The 80C51/80L51 transmit
routine should take this into account.
80C51/80L51*
Figure 52. AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSP-BF53x
Interface
AD5024/
AD5044/
AD5064/
AD5064-1*
AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11
Interface
P3.3
SYNC
TxD
SCLK
Figure 53 shows a serial interface between the AD5024/AD5044/
AD5064/AD5064-1 and the 68HC11/68L11 microcontroller.
SCK of the 68HC11/68L11 drives the SCLK of the AD5024/
AD5044/AD5064/AD5064-1, and the MOSI output drives the
serial data line of the DAC.
RxD
DIN
AD5024/
AD5044/
AD5064/
AD5064-1*
PC7
SYNC
SCK
SCLK
MOSI
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE
Interface
Figure 55 shows an interface between the AD5024/AD5044/
AD5064/AD5064-1 and any MICROWIRE-compatible device.
Serial data is shifted out on the falling edge of the serial clock and is
clocked into the AD5024/AD5044/AD5064/AD5064-1 on the
rising edge of the SCLK.
06803-013
68HC11/68L11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 54. AD5024/AD5044/AD5064/AD5064-1 to 80C512/80L51 Interface
MICROWIRE*
Figure 53. AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11 Interface
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
The 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SYNC line is taken low (PC7). When the 68HC11/68L11 is
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5024/AD5044/
AD5064, PC7 is left low after the first eight bits are transferred,
and a second serial write operation is performed to the DAC.
PC7 is taken high at the end of this procedure.
AD5024/
AD5044/
AD5064/
AD5064-1*
CS
SYNC
SK
DIN
SO
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
06803-015
TFS0
DT0PRI
AD5024/
AD5044/
AD5064/
AD5064-1*
06803-012
ADSP-BF53x*
AD5024/AD5044/AD5064/AD5064-1 to 80C51/80L51
Interface
06803-014
MICROPROCESSOR INTERFACING
Figure 55. AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE Interface
Rev. F | Page 25 of 28
AD5024/AD5044/AD5064
Data Sheet
APPLICATIONS INFORMATION
Because the supply current required by the AD5024/AD5044/
AD5064/AD5064-1 is extremely low, an alternative option is to
use a voltage reference to supply the required voltage to the parts
(see Figure 56). This is especially useful if the power supply is
quite noisy or if the system supply voltages are at some value
other than 5 V (for example, 15 V). The voltage reference outputs
a steady supply voltage for the AD5024/AD5044/AD5064/
AD5064-1. If the low dropout REF195 is used, it must supply
3 mA of current to the AD5024/AD5044/AD5064/AD5064-1,
with no load on the output of the DAC. When the DAC output is
loaded, the REF195 also needs to supply the current to the load.
The total current required (with a 5 kΩ load on the DAC output) is
This is an output voltage range of ±5 V, with 0x0000 corresponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
R2 = 10kΩ
+5V
R1 = 10kΩ
+5V
VREF
5V
VDD
10µF
0.1µF
3 mA + (5 V/5 kΩ) = 4 mA
5V
SYNC
SCLK
AD5024/
AD5044/
AD5064/
AD5064-1
VOUT = 0V TO 5V
06803-016
DIN
Figure 56. REF195 as Power Supply to the AD5024/AD5044/AD5064/AD5064-1
BIPOLAR OPERATION
The AD5024/AD5044/AD5064/AD5064-1 have been designed
for single-supply operation, but a bipolar output range is also
possible using the circuit shown in Figure 57. The circuit gives an
output voltage range of ±5 V. Rail-to-rail operation at the
amplifier output is achievable using an AD8638 or an AD8639
as the output amplifier.
Assuming VDD = VREF, the output voltage for any input code can
be calculated as follows:
In process control applications in industrial environments, it
is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous
common-mode voltages that can occur in the area where the
DAC is functioning. iCoupler® provides isolation in excess of
2.5 kV. The AD5024/AD5044/AD5064/AD5064-1 use a 3-wire
serial logic interface, so the ADuM1300 three-channel digital
isolator provides the required isolation (see Figure 58). The
power supply to the part also needs to be isolated, which is done
by using a transformer. On the DAC side of the transformer, a
5 V regulator provides the 5 V supply required for the AD5024/
AD5044/AD5064/AD5064-1.
5V
REGULATOR
where D represents the input code in decimal (0 to 65,535).
10µF
POWER
0.1µF
VDD
SCLK
VIA
VOA
SCLK
ADuM1300

 D   R1 + R2 
 R2 
= VDD × 
×

 − VDD × 
R1
65
,
536

 R1 




SDI
VIB
VOB
SYNC
DATA
VIC
VOC
DIN
With VDD = 5 V, R1 = R2 = 10 kΩ,
AD5024/
AD5044/
AD5064/
AD5064-1
VOUTx
GND
06803-018
 10 × D 
VOUT = 
 −5V
 65,536 
–5V
USING THE AD5024/AD5044/AD5064/AD5064-1
WITH A GALVANICALLY ISOLATED INTERFACE
VDD
VOUT
AD5024/
AD5044/
AD5064/
AD5064-1
Figure 57. Bipolar Operation
15V
3-WIRE
SERIAL
INTERFACE
±5V
VOUTA
3-WIRE
SERIAL INTERFACE
The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 3 ppm (15 µV) error for the 4 mA current
drawn from it. This corresponds to a 0.196 LSB error.
REF195
AD8638/
AD8639
VREFA
06803-017
USING A REFERENCE AS A POWER SUPPLY
Figure 58. AD5024/AD5044/AD5064/AD5064-1 with a Galvanically Isolated
Interface
Rev. F | Page 26 of 28
Data Sheet
AD5024/AD5044/AD5064
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.20
0.09
SEATING
PLANE
0.30
0.19
8°
0°
0.75
0.60
0.45
061908-A
1.05
1.00
0.80
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 59. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.65
BSC
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 60. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. F | Page 27 of 28
0.75
0.60
0.45
AD5024/AD5044/AD5064
Data Sheet
ORDERING GUIDE
Model 1
AD5064ARUZ-1
AD5064ARUZ-1REEL7
AD5064BRUZ-1
AD5064BRUZ-1REEL7
AD5064BRUZ
AD5064BRUZ-REEL7
AD5044BRUZ
AD5044BRUZ-REEL7
AD5024BRUZ
AD5024BRUZ-REEL7
EVAL-AD5064-1EBZ
EVAL-AD5064EBZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Accuracy
±4 LSB INL
±4 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±0.5 LSB INL
±0.5 LSB INL
Resolution
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
14 Bits
14 Bits
12 Bits
12 Bits
Z = RoHS Compliant Part.
©2008–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06803-0-6/13(F)
Rev. F | Page 28 of 28
Package Description
14-lead TSSOP
14-lead TSSOP
14-lead TSSOP
14-lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
14-Lead TSSOP Evaluation Board
16-Lead TSSOP Evaluation Board
Package Option
RU-14
RU-14
RU-14
RU-14
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
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