datasheet for VL493T5663D

datasheet for VL493T5663D
Product Specifications
PART NO:
REV: 1.3
VL493T5663D-E7/E6/D5/CC
General Information
2GB 256MX72 DDR2 SDRAM ECC 200 PIN SO-RDIMM
Description:
The VL493T5663D is a 256Mx72 Double Data Rate DDR2 SDRAM high density SO-RDIMM. This memory
module consists of eighteen CMOS 128Mx8 bit with 8 banks DDR2 Synchronous DRAMs in BGA packages,
two 25-bit Registered buffers in BGA packages, a zero delay PLL clock in BGA package, and a 2K EEPROM
in an 8-pin MLF package. This module is a 200-pin small-outline registered dual in-line memory module and is
intended for mounting into a connector socket. Decoupling capacitors are mounted on the printed circuit board
for each DDR2 SDRAM.
Features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Registered SO-RDIMM 29.85mm (1.175”) module height
Supports ECC error detection and correction
Data transfer rates: PC2-6400, PC2-3200, PC2-4200 or PC2-5300
Utilizes 1Gbit DDR2 SDRAM components
Performance range: 667Mb/sec/pin, 533Mb/sec/pin, or 400Mb/sec/pin
Power supply: Vdd = Vddq = 1.8V ± 0.1V
JEDEC standard 1.8V I/O (SSTL_18-Compatible)
On-die termination (ODT)
Differential data strobe (DQS, DQS#) option
Differential clock inputs (CK, CK#)
7.8us average periodic refresh interval
Programmable CAS# Latency: 3, 4, 5, 6
Posted CAS# additive Latency: 0, 1, 2, 3, and 4
Eight internal banks for concurrent operation (component)
On memory PLL Clock and Register drivers
Serial presence detect (SPD) with +1.7V to +3.6V EEPROM
JEDEC pin out
Order Information :
VL493T5663D-E7 X X
DRAM DIE (option)
DRAM MANUFACTURER
S - SAMSUNG
M - MICRON
MODULE SPEED
E7: PC2-6400 @ CL6
E6: PC2-5300 @ CL5
D5: PC2-4200 @ CL4
CC: PC2-3200 @ CL3
Pin Name
Function
A0~A13
Address Inputs
BA0~BA2
Bank Address Inputs
DQ0~DQ63
D ata Input/Output
CB0~CB7
C heck Bits
DQS0~DQS8
D ata Strobes
DQS0#~DQS8#
D ata Strobes C omplement
ODT0, ODT1
On-di e Termi nati on C ontrol
C K, C K#
C lock Input
C K E 0, C K E 1
C lock Enables
C S 0#, C S 1#
C hi p Selects
RAS#
Row Address Strobes
C AS#
C olumn Address Strobes
WE#
Write Enable
RESET#
Register Reset Input
DM0~DM8
D ata Masks
VD D
Voltage Supply 1.8V +/- 0.1V
A10/AP
Address Input/Autoprecharge
VD D SPD
SPD Voltage Supply 1.7V to
3.6V
VSS
Ground
SA0~SA1
SPD Address
SD A
SPD D ata Input/Output
SC L
SPD C lock Input
VREF
SSTL_18 Reference Voltage
NC
No C onnect
VL : Lead-free/RoHS
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 1 OF 10
Product Specifications
PART NO:
REV: 1.3
VL493T5663D-E7/E6/D5/CC
Pin Configuration
200-PIN DDR2 SO-RDIMM FRONT
200-PIN DDR2 SO-RDIMM BACK
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREF
51
DQ18
101
VD D
15 1
VSS
2
VSS
52
VSS
102
A6
152
VSS
3
DQ0
53
DQ19
103
A5
153
DQS5#
4
DQ4
54
DQ28
104
A4
154
DM5
5
VSS
55
VSS
105
A3
155
DQS5
6
DQ5
56
DQ29
106
VD D
156
VSS
7
DQ1
57
DQ24
107
A2
157
VSS
8
VSS
58
VSS
108
A1
158
DQ46
9
DQS0#
59
DQ25
109
VD D
159
DQ42
10
DM0
60
DM3
110
A0
160
DQ47
11
DQS0
61
VSS
111
A10/AP
161
DQ43
12
VSS
62
VSS
112
BA1
162
VSS
13
VSS
63
DQS3#
113
BA0
163
VSS
14
DQ6
64
DQ30
114
VD D
164
DQ52
15
DQ2
65
DQS3
115
RAS#
165
DQ48
16
DQ7
66
DQ31
116
WE#
166
DQ53
17
DQ3
67
VSS
117
VD D
167
DQ49
18
VSS
68
VSS
118
C S 0#
168
VSS
19
VSS
69
DQ26
119
C AS#
169
VSS
20
DQ12
70
C B4
120
ODT0
170
DM6
21
DQ8
71
DQ27
121
C S 1#
171
DQS6#
22
DQ13
72
C B5
122
A 13
172
VSS
23
DQ9
73
VSS
123
VD D
173
DQS6
24
VSS
74
VSS
124
VD D
174
DQ54
25
VSS
75
C B0
125
ODT1
175
VSS
26
DM1
76
DM8
126
CK
176
DQ55
27
DQS1#
77
C B1
127
NC/
C S 3#
177
DQ50
28
VSS
78
VSS
128
CK#
178
VSS
29
DQS1
79
VSS
129
DQ32
179
DQ51
30
DQ14
80
C B6
130
VSS
180
DQ60
31
VSS
81
DQS8#
131
VSS
181
VSS
32
DQ15
82
C B7
132
DQ36
182
DQ61
33
DQ10
83
DQS8
133
DQ33
183
DQ56
34
VSS
84
VSS
134
DQ37
184
VSS
35
DQ11
85
VSS
135
DQS4#
185
DQ57
36
DQ20
86
C B2
136
VSS
186
DM7
37
VSS
87
C KE0
137
DQS4
187
VSS
38
DQ21
88
C B3
138
DM4
188
DQ62
39
DQ16
89
CKE1
139
VSS
189
DQS7#
40
VSS
90
VSS
140
VSS
190
VSS
41
DQ17
91
NC/
C S 2#
141
DQ34
191
DQS7
42
RESET#
92
BA2
142
DQ38
192
DQ63
43
VSS
93
VDD
143
DQ35
193
DQ58
44
DM2
94
NC
144
DQ39
194
SD A
45
DQS2#
95
A 12
145
VSS
195
VSS
46
VSS
96
A11
146
VSS
196
SC L
47
DQS2
97
A9
147
DQ40
197
DQ59
48
DQ22
98
VD D
148
DQ44
198
SA1
49
VSS
99
A7
149
DQ41
199
VD D SPD
50
DQ23
100
A8
150
DQ45
200
SA0
Note: 1. CS2#, CS3# (pins 91, 127) are used for 4 rank DIMMs
2. RESET (pin 42) RESET is connected to both OE of the PLL and Reset of the register for 72-bit Registered SO-RDIMM ONLY
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 2 OF 10
Product Specifications
PART NO:
VL493T5663D-E7/E6/D5/CC
REV: 1.3
Functional Block Diagram
RCS1#
RCS0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DM/
RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
D0
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D9
DQS1
DQS1#
DM1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
CS# DQS DQS#
D13
DQS5
DQS5#
DM5
DM/
RDQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
D1
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D10
DQS2
DQS2#
DM2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
CS# DQS DQS#
D14
DQS6
DQS6#
DM6
DM/
RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
D2
DM/
RDQS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
CS# DQS DQS#
DM/
RDQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D11
DQS3
DQS3#
DM3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
CS# DQS DQS#
D15
DQS7
DQS7#
DM7
DM/
RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
D3
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D12
DQS8
DQS8#
DM8
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
CS# DQS DQS#
D16
VDDSPD
Serial PD
VDD/VDDQ
D0 - D17
VREF
D0 - D17
VSS
D0 - D17
Serial PD
DM/
RDQS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CS0#
CS1#
BA0-BA2
A0-A13
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1:2
R
E
G
I
S
T
E
R
RESET#**
CS# DQS DQS#
D8
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
SCL
SDA
WP A0
A1
A2
D17
SA0 SA1
SA2
RCS0# -> CS# : DDR2 SDRAMs D0-D8
120
RCS1# -> CS# : DDR2 SDRAMs D9-D17
CK
CK0
RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D17
PLL
CK0#
CK#
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17
RRAS# -> RAS:# DDR2 SDRAMs D0-D17
RESET#**
RCAS# -> CAS:# DDR2 SDRAMs D0-D17
RWE# ->WE# : DDR 2 SDRAMs D0-D17
See note on page 2
RCKE0 -> CKE : DDR2 SDRAMs D0-D8
Notes :
RCKE1 -> CKE : DDR2 SDRAMs D9-D17
Unless otherwise noted, resister values are 22 Ohms
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8
RODT1 -> ODT1 : DDR2 SDRAMs D9-D17
RST#
CK**
** RESET#, CK and CK# connects to both Registers. Other signals connect to one of two Registers.
CK #**
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 3 OF 10
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
REGISTER X 2
X2
X2
X2
X2
X2
X2
X2
X2
X2
Product Specifications
PART NO:
REV: 1.3
VL493T5663D-E7/E6/D5/CC
Absolute Maximum Ratings
Symbol
Parameter
MIN
MAX
Unit
VDD
Voltage on VDD pin relative to VSS
-1.0
2.3
V
VDDQ
Voltage on VDDQ pin relative to VSS
-0.5
2.3
V
VDDL
Voltage on VDDL pin relative to VSS
-0.5
2.3
V
Voltage on any pin relative to VSS
-0.5
2.3
V
Storage temperature
-55
100
Command/Address,
RAS#, CAS#, WE#,
CS#, CKE, ODT, BA
-5
5
uA
C K, C K#
-10
10
uA
DM
-10
10
uA
DQ, DQS, DQS#
-10
10
uA
-36
36
uA
VIN, VOUT
TSTG
Input leakage current; Any input
0V<VIN<VDD; VREF input
0V<VIN<0.95V; Other pins not under
test = 0V
IL
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT are
disabled
IOZ
IVREF
VREF leakage current; VREF = Valid VREF level
0
C
DC Operating Conditions
All voltages referenced to VSS
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Supply voltage
VDD
1.7
1.8
1.9
V
1
I/O Supply voltage
VDDQ
1.7
1.8
1.9
V
4
VDDL Supply voltage
VDDL
1.7
1.8
1.9
V
4
I/O Reference voltage
VREF
0.49 x VDDQ
0.50 x VDDQ
0.51 x VDDQ
V
2
I/O Termination voltage
VTT
VREF-0.04
VREF
VREF+0.04
V
3
Notes: 1. VDD, VDDQ must track each other. VDDQ must be less than or equal to VDD.
2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-topeak noise on VREF may not exceed +/-1percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2
percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF and must track variations in the DC level of VREF.
4. VDDQ tracks with VDD; VDDL tracks with VDD.
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 4 OF 10
Product Specifications
PART NO:
REV: 1.3
VL493T5663D-E7/E6/D5/CC
Operating Temperature Condition
Parameter
Operating temperature
Symbol
Rating
TOPER
0 to 95
Units
Notes
C
1,2
0
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JEDEC JESD51.2
2. At 0 - 850C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when
85°C < TOPER <= 95°C
Input DC Logic Level
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
Input High (Logic 1) Voltage
VIH(DC)
VREF + 0.125
VDDQ + 0.300
V
Input Low (Logic 0) Voltage
VIL(DC)
-0.300
VREF - 0.125
V
Input AC Logic Level
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533
VIH(AC)
VREF + 0.250
-
V
AC Input High (Logic 1) Voltage DDR2-667 & DDR2-800
VIH(AC)
VREF + 0.200
-
V
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
VIL(AC)
-
VREF - 0.250
V
AC Input Low (Logic 0) Voltage DDR2-667 & DDR2-800
VIL(AC)
-
VREF - 0.200
V
Input/Output Capacitance
TA=250C, f=100MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A13, BA0~BA2, RAS#, CAS#, WE#)
CIN1
11
12
pF
Input capacitance (CKE0, CKE1), (ODT0, ODT1)
CIN2
11
12
pF
Input capacitance (CS0# ~ CS1#)
CIN3
11
12
pF
Input capacitance (CK, CK#)
CIN4
10
11
pF
CIO (E6,E7)
9
11
pF
CIO (D5,CC)
9
12
pF
Input/Output capacitance (DQ, DQS, DQS#, DM, CB)
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 5 OF 10
Product Specifications
PART NO:
REV: 1.3
VL493T5663D-E7/E6/D5/CC
IDD Specification
Condition
Symbol
-E7
-E6
-D5
-CC
Unit
Operating one bank active-precharge;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD0*
13 45
1300
1255
1210
mA
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4; CL = CL(IDD);tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING; Data pattern is same as IDD4W.
IDD1*
1435
1390
1345
1300
mA
Precharge pow er-dow n current;
All banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
IDD2P**
670
670
670
670
mA
Precharge quiet standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
IDD2Q**
1120
1120
1120
1030
mA
Precharge standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are SWITCHING.
IDD2N**
1300
1210
12 10
1120
mA
Active pow er-dow n current;
All banks open; tCK= tCK(IDD); CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs
are FLOATING.
1120
1120
1030
1030
mA
IDD3P**
724
724
724
724
mA
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
Active standby current;
All banks open;tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD));CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
IDD3N**
1570
1480
1480
1390
mA
Operating burst w rite current;
All banks open; Continuous burst writes; BL = 4; CL = CL(IDD); AL = 0; tCK= tCK(IDD);
tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD4W*
1840
1705
1615
1480
mA
Operating burst read current;
All banks open; Continuous burst reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = 0;
tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W.
IDD4R*
1930
1795
1705
1570
mA
Burst auto refresh current;
tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH; CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs
are SWITCHING.
IDD5**
3190
3100
3100
3010
mA
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are
FLOATING.
IDD6**
270
270
270
270
mA
IDD7*
2875
2695
2695
2560
mA
Normal
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = tRCD(IDD) - 1*tCK(IDD);
tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
SWITCHING.
Notes:
IDD specification is based on Samsung components. Other DRAM Manufacturers specification may be different.
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P ( CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 6 OF 10
Product Specifications
PART NO:
REV: 1.3
VL493T5663D-E7/E6/D5/CC
AC Timing Parameters & Specifications
-E7
Parameter
Clock
Data
-D5
-CC
Min
Max
Min
Max
Min
Max
Min
Max
Unit
CL=5
tCK (5)
2500
8000
3000
8000
-
-
-
-
ps
CL=4
tCK (4)
-
-
3750
8000
3,750
8,000
5,000
8,000
ps
CL=3
tCK (3)
-
-
5000
8000
5,000
8,000
5,000
8,000
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Half clock period
tHP
MIN
(tCH,tCL)
Clock jitter
tJIT
-100
100
-125
125
-125
125
-125
125
ps
DQ output access time from CK/CK#
tAC
-400
400
-450
+450
-500
+500
-600
+600
ps
Data-out high impedance window from CK/CK#
tHZ
tAC (MAX)
ps
Data-out low-impedance window from CK/CK#
tLZ
tAC (MIN)
tAC (MAX)
ps
DQ and DM input setup time relative to DQS
tDS
50
100
100
150
DQ and DM input hold time relative to DQS
tDH
125
175
225
275
DQ and DM input pulse width (for each input)
tDIPW
0.35
0.35
0.35
0.35
Data hold skew factor
tQHS
DQ–DQS hold, DQS to first DQ to go nonvalid,
p e r a cce ss
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
Data valid output window (DVW)
tDVW
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
ns
DQS input high pulse width
tDQSH
0.35
0.35
0.35
0.35
tCK
DQS input low pulse width
tDQSL
0.35
0.35
0.35
0.35
tCK
DQS output access time fromCK/CK#
tDQSCK
-350
DQS falling edge to CK rising – setup time
tDSS
0.2
0.2
0.2
0.2
tCK
DQS falling edge from CK rising – hold time
tDSH
0.2
0.2
0.2
0.2
tCK
DQS–DQ skew, DQS to last DQ valid, per group,
p e r a cce ss
tDQSQ
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
DQS write preamble setup time
tWPRES
0
0
0
0
ps
DQS write preamble
tWPRE
0.35
0.35
0.35
0.35
tCK
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching transition
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
Clock cycle time
Data Strobe
-E6
Symbol
MIN
(tCH,tCL)
tAC (MAX)
MIN
(tCH,tCL)
tAC (MAX)
tAC (MAX)
tAC (MIN)
300
tAC (MAX)
tAC (MAX)
tAC (MIN)
340
350
-400
200
+400
MIN
(tCH,tCL)
tAC (MAX)
400
-450
240
+450
tCK
450
-500
300
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 7 OF 10
tAC (MIN)
ps
+500
ps
ps
350
ps
0.9
1.1
tCK
0.4
0.6
tCK
Product Specifications
PART NO:
REV: 1.3
VL493T5663D-E7/E6/D5/CC
AC Timing Parameters & Specifications ( cont')
-E7
Parameter
Min
Address and control i nput pulse wi dth for each
i nput
Address and control i nput setup ti me
Address and control i nput hold ti me
Command and Address
C AS# to C AS# command delay
Self Refresh
Min
-D 5
Max
Min
-C C
Max
Min
Max
U nit
tIPW
0.6
0.6
0.6
0.6
tCK
tIS
175
200
250
350
ps
tIH
250
275
375
475
ps
tCCD
2
2
2
2
ps
tRC
55
55
55
55
ns
AC TIVE bank a to AC TIVE bank b command
tRRD
7.5
7.5
7.5
7.5
ns
AC TIVE to READ or WRITE delay
tRCD
12.5
15
15
15
ns
Four Bank Acti vate peri od
tFAW
37.5
37.5
37.5
37.5
ns
AC TIVE to PREC HARGE command
tRAS
45
Internal READ to precharge command delay
tRTP
7.5
70,000
40
70,000
7.5
40
70,000
40
7.5
70,000
7.5
ns
ns
Wri te recovery ti me
tWR
15
15
15
15
ns
Auto precharge wri te recovery + precharge ti me
tDAL
tWR+tRP
tWR+tRP
tWR+tRP
tWR+tRP
ns
Internal WRITE to READ command delay
tWTR
7.5
7.5
7.5
10
ns
PREC HARGE command peri od
tRP
12.5
15
15
15
ns
PREC HARGE ALL command peri od
tRPA
tRP+tCK
tRP+tCK
tRP+tCK
tRP+tCK
ns
LOAD MOD E command cycle ti me
tMRD
2
2
2
2
tCK
tDELAY
tIS+tCK+tIH
tIS+tCK+tIH
tIS+tCK+tIH
tIS+tCK+tIH
ns
REFRESH to Acti ve or Refresh to Refresh
command i nterval
tRFC
127.5
Average peri odi c refresh i nterval
tREFI
70,000
127.5
7.8
70,000
127.5
7.8
70,000
127.5
7.8
70,000
ns
7.8
us
Exi t self refresh to non-READ command
tXSNR
tRFC(MIN)+10
Exi t self refresh to READ
tXSRD
200
200
200
200
tCK
Exi t self refresh ti mi ng reference
tISXR
tIS
tIS
tIS
tIS
ps
OD T turn-on delay
tAOND
2
2
2
2
2
2
2
2
tCK
tAC(MAX)+
700
tAC(MIN)
tAC(MAX)+
700
tAC(MIN)
tAC(MAX)+
1000
tAC(MIN)
tAC(MAX)+
1000
tRFC(MIN)+10
tRFC(MIN)+10
tRFC(MIN)+10
ns
ps
OD T turn-on
tAON
tAC(MIN)
OD T turn-off delay
tAOFD
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
tCK
tAOF
tAC(MIN)
tAC(MAX)+
600
tAC(MIN)
tAC(MAX)+
600
tAC(MIN)
tAC(MAX)+
600
tAC(MIN)
tAC(MAX)+
600
ps
tAONPD
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
ps
OD T turn-off (power-down mode)
tAOFPD
tAC(MIN)+
2000
2.5 x tCK
+ tAC(MAX)+
1000
tAC(MIN)+
2000
2.5 x tCK
+ tAC(MAX)+
1000
tAC(MIN)+
2000
2.5 x tCK
+ tAC(MAX)+
1000
tAC(MIN)+
2000
2.5 x tCK
+ tAC(MAX)+
1000
ps
OD T to power-down entry latency
tANPD
3
3
3
3
tCK
OD T turn-off
ODT
Max
AC TIVE to AC TIVE (same bank) command
C KE low to C K,C K# uncertai nty
Power-Down
-E6
Symbol
OD T turn-on (power-down mode)
OD T power-down exi t latency
tAXPD
10
8
8
8
tCK
Exi t acti ve power-down to READ command,
MR[bi t12=0]
tXARD
2
2
2
2
tCK
Exi t acti ve power-down to READ command,
MR[bi t12=1]
tXARDS
8-AL
7-AL
6-AL
6-AL
tCK
Exi t precharge power-down to any non-READ
command.
tXP
2
2
2
2
tCK
CKE mi ni mum hi gh/low ti me
tCKE
3
3
3
3
tCK
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 8 OF 10
Product Specifications
PART NO:
REV: 1.3
VL493T5663D-E7/E6/D5/CC
Package Dimensions
FRONT VIEW
3.66
MAX
67.60
4.00 +/- 0.10 (2X)
29.85
1.80 (2X)
TYP
20.00 TYP
6.00 TYP
2.55 TYP
1.00 +/- 0.10
2.15 TYP
0.45 TYP
1.00 TYP
PIN 1
0.60 TYP
PIN 199
63.60 TYP
BACK VIEW
4.20 TYP
PIN 200
47.40 TYP
PIN 2
11.40 TYP
15.35 TYP
NOTE:
All dimesions are in millimeters with tolerance +/- 0.15mm unless otherwise specified.
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 9 OF 10
Product Specifications
PART NO:
VL493T5663D-E7/E6/D5/CC
Revision History:
Date
Rev.
P ag e
C h an g es
10/02/2007
1.0
All
Released spec
02/26/2008
1.1
All
All pages: Added speed DDR2-800 (E7) & Page 5: updated IDD table
02/12/2009
1.2
06/15/2009
1.3
1, 4, 5, 6, 7, 8, 10 Data sheet update
9
Dimension Package update
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 10 OF 10
REV: 1.3
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