User manual | datasheet for MSM8128JX by Apta Group

TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE
128K x 8 SRAM
MSM8128 - 85/10/12
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
Description
The MSM8128 is a 1Mbit monolithic SRAM
organised as 128K x 8. It is available in with
access times of 85, 100 & 120ns. It has a low
power standby version and has 3.0V battery
backup capability. It is directly TTL compatible
and has common data inputs and outputs.
Two pinout variants (single and dual CS) are
available.
All versions may be screened in accordance with
MIL-STD-883.
Issue 4.4 : February 2000
131,072 x 8 CMOS Static RAM
Features
Access Times of 85/100/120 ns
JEDEC standard Dual CS footprints.
Operating Power
605 mW (max)
Low Power Standby (-L) 2.53 mW (max)
Low Voltage Data Retention.
Completely Static Operation
Directly TTL compatible.
May be processed in accordance with MIL-STD-883
Block Diagram
Pin Definition
32
32
32
Flatpack
LCC
JLCC
Package details on pages 8 & 9.
Package Type
G
W
J
D0
A0
A1
A2
A3
A4
A5
A6
A7
13
12
11
10
9
8
7
6
5
4
3
2
28
29
WE
26
A9
27
25
A11
A8
24
OE
1
A13
23
A10
VCC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
D7
D6
D5
D4
D3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TOP VIEW
J
22
14
15
16
17
18
19
20
21
D1
D2
GND
D3
D4
D5
D6
D7
512 X 2048
CS1
MEMORY ARRAY
Package Details
Pin Count
Description
1
2
3
4
5
6
7
8 TOP VIEW
S,V
9
10
11
12
13
14
15
16
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
32
31
30
See Page 9 for X pinout
Pin Functions
A0-A16
Address Inputs
D0-7
Data Input/Output
CS1
Chip Select 1
CS2
Chip Select 2
OE
Output Enable
WE
Write Enable
NC
No Connect
VCC
Power (+5V)
GND
Ground
A12
A14
A16
NC
VCC
A15
CS2
MSM8128 - 70/85/10/12
Issue 4.4 : February 2000
DC OPERATING CONDITIONS
Absolute Maximum Ratings
Voltage on any pin relative to VSS
Power Dissipation
Storage Temperature
Notes :
VT
PT
TSTG
-0.5V
to
1
to
-55
+7.0
V
W
o
C
+150
(1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Recommended Operating Conditions
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
VCC
VIH
VIL
TA
TAI
TAM
min
typ
max
4.5
2.2
-0.3
0
-40
-55
5.0
-
5.5
5.8
0.8
70
85
125
V
V
V
o
C
o
C (I suffix)
o
C (M, MB suffix)
DC Electrical Characteristics (VCC = 5.0V±10%, TA=-55°C to +125°C)
Parameter
Symbol
Input Leakage Current
Output Leakage Current
Average Supply Current
Standby Supply Current
-L Part
ILI
Il/O
ICC1
ISB1
ISB2
Output Voltage
VOL
VOH
Test Condition
VIH=0V to Vcc
CS1=VIH, CS2 =VIL, VI/O=0V to Vcc ,OE=VIH
Min. Cycle, VIN=VIL or VIH
CS1=VIH,CS2 = VIL , I/P's static
CS1≥VCC-0.2V, 0.2V≥CS2≥VCC-0.2V , VIN ≥ 0.2V
IOL = 2.1 mA
IOH = -1.0 mA
min
typ
-1
-1
-
-
1
1
110
3.5
460
µA
µA
mA
mA
uA
2.4
-
0.4
-
V
V
Capacitance (VCC=5V±10%,TA=25oC)
Parameter
I/P Capacitance
I/O Capacitance
Symbol
Test Condition
typ
max
Unit
CIN
CI/O
VIN=0V
VI/O=0V
-
8
10
pF
pF
Note: This parameter is sampled and not 100% tested.
2
max Unit
MSM8128 - 70/85/10/12
Issue 4.4 : February 2000
Operating Modes
The table below shows the logic inputs required to control the MSM8128 SRAM.
Mode
CS1
CS2
OE
Not Selected
1
X
X
Not Selected
X
0
Output Disable
0
Read
Write
VCC Current
I/O Pin
Reference Cycle
X
ISB1,ISB2
High Z
Power Down
X
X
ISB,ISB1
High Z
Power Down
1
1
1
ICC
High Z
0
1
0
1
ICC
DOUT
Read Cycle
0
1
X
0
ICC
DIN
Write Cycle
1 = VIH,
WE
0 = VIL,
X = Don't Care
Low Vcc Data Retention Characteristics - L Version Only (TA=-55°C to +125oC)
Parameter
VCC for Data Retention
Symbol Test Condition
VDR
ICCDR
max
2.0
-
-
0
5
-
700
-
Unit
V
VCC=3.0V,VIN ≥ 0V, CS1 ≥VCC-0.2V,
CS2 ≥ VCC-0.2V or 0V ≤ CS2 ≤ 0.2V.
Chip Deselect to Data Retention tCDR
Operation Recovery Time
tR
typ
CS1 ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or
0V ≤ CS2 ≤ 0.2V. VIN ≥ 0V
Data Retention Current
min
See Retention Waveform
See Retention Waveform
µA
ns
ms
Notes (1) CS2 controls address buffer, WE buffer, CS1 buffer and OE buffer. If CS2 controls data retention mode,
Vin levels (WE,OE,CS1,I/O) can be in the high impedance state. If CS1 controls Data Retention mode,
CS2 must be ≥ VCC - 0.2V or 0V ≤ CS2 ≤ 0.2V. The other input levels (address, WE,OE,I/O) can be in the
high impedance state.
AC Test Conditions
Output Load
I/O Pin
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: See Load Diagram
* Vcc=5V±10%
166 Ω
1.76V
30pF
3
MSM8128 - 70/85/10/12
Issue 4.4 : February 2000
AC OPERATING CONDITIONS
Read Cycle
Parameter
Symbol
Read Cycle Time
Address Access Time
Chip Select (CS1) Access Time(2)
Chip Select (CS2) Access Time(2)
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection (CS1) to Output in Low Z
Chip Selection (CS2) to Output in Low Z
Output Enable to Output in Low Z
Chip Disable (CS1) to Output in High Z(3)
Chip Disable (CS2) to Output in High Z(3)
Output Disable to Output in High Z(3)
tRC
tAA
tACS1
tACS2
tOE
tOH
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
Write Cycle
Parameter
Symbol
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time (WE, CS1)
(CS2)
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
123456789012345
123456789012345
123456789012345
123456789012345
123456789012345
123456789012345
tWC
tCW
tAW
tAS
tWP
tWR1
tWR2
tWHZ
tDW
tDH
tOW
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
70
85
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
min
max
min
max
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
70
85
1234567890123456789
1234567890123456789
1234567890123456789
70
85
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
70
85
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
70
85
1234567890123456789
1234567890123456789
1234567890123456789
35
45
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
5
5
1234567890123456789
1234567890123456789
1234567890123456789
10
10
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
10
10
1234567890123456789
1234567890123456789
1234567890123456789
5
5
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
0
35
0
35
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
0
35
0
35
1234567890123456789
1234567890123456789
1234567890123456789
0
30
0
30
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
70
85
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
min
max
min
max
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
70
85
1234567890123456789
1234567890123456789
1234567890123456789
60
75
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
60
75
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
0
0
1234567890123456789
1234567890123456789
1234567890123456789
50
60
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
5
5
1234567890123456789
1234567890123456789
1234567890123456789
5
5
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
0
30
0
30
1234567890123456789
1234567890123456789
1234567890123456789
30
35
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
0
0
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
5
5
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
Consult Factory
4
min
10
max
min
100
10
10
10
5
0
0
0
100
100
100
50
35
35
35
120
10
10
10
5
0
0
0
min
10
max
100
85
85
0
70
5
5
0
40
0
5
35
-
12
max Unit
120
120
120
60
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
min max Unit
120
100
100
0
70
5
5
0
45
0
5
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MSM8128 - 70/85/10/12
Issue 4.4 : February 2000
Read Cycle Timing Waveform (1,2 )
t
RC
Address
t
AA
OE
t OE
t
OH
t OLZ
CS1
t CLZ1
t ACS1 (2)
t
CHZ1 (3)
CS2
t ACS2 (2)
t
t OHZ (3)
CLZ2
Data Valid
Dout
t CHZ2 (3)
Notes:
(1) WE is High for Read Cycle.
(2) Address valid prior to or coincident with CS1 transition low or CS2 high.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels. At any given temperature and voltage condition, tCHZ max is less than
tCLZ min both for a given device and from device to device. This parameter is sampled and not 100% tested.
5
MSM8128 - 70/85/10/12
Issue 4.4 : February 2000
Write Cycle No.1 Timing Waveform
t WC
Address
tWR1,2 (2)
t AW
t AS (3)
(6)
CS1
t CW (4)
(6)
CS2
OE
WE
t OHZ(3,9)
t WP(1)
High - Z
Dout
t DH
t DW
Data Valid
Din
Write Cycle No.2 Timing Waveform (5)
t WC
Address
t AW
t WR1,2 (2)
(6)
CS1
t CW (4)
CS2
(6)
t AS (3)
t WP (1)
t OH
WE
t OW
t WHZ(3,9)
(8)
High - Z
Dout
t DW
High - Z
Data Valid
Din
6
t DH
(7)
MSM8128 - 70/85/10/12
Issue 4.4 : February 2000
Low VCC Data Retention Timing Waveform 1 (CS1 controlled)
Vcc
DATA RETENTION MODE
4.5V
4.5V
t CDR
tR
2.2V
2.2V
V DR
CS1
CS1≥Vcc-0.2V
0V
Low VCC Data Retention Timing Waveform 2 (CS2 controlled)
Vcc
DATA RETENTION MODE
4.5V
tR
tCDR
4.5V
CS2
V DR2
0.4V
CS2 ≤ 0.2V
0V
AC Characteristics Notes
(1) A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among
CS1 going low, CS2 going high and WE going low. A write ends at the earliest transition among CS1 going high, CS2
going low and WE going high. tWP is measured from the beginning of write to the end of write.
(2) tWR is measured from the earlier of CS1 or WE going high or CS2 going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If CS1 goes low simultaneously with WE going low or after WE going low, outputs remain in high impedance state.
(5) OE is continuously low. (OE=VIL)
(6) Dout is in the same phase as written data of this write cycle.
(7) Dout is the read data of next address.
(8) If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Input signals out of phase must not be
applied to I/O pins.
(9) tWHZ is defined as the time at which the outputs achieve the open circuit conditions and is not referenced to output voltage
levels. These parameters are sampled and not 100% tested.
7
MSM8128 - 70/85/10/12
Issue 4.4 : February 2000
32 pin Flatpack - 'G' Package
20.58 (0 .8 10)
18.92 (0 .7 45)
19.17 (0 .7 55)
0.0 50
ty p.
21.08 (0 .8 30)
0.0 45
m ax
0.0 17
+ /- 0.00 2
10.54 (0 .4 15)
0.2 75 m in
0.2 75 m in
10.29 (0 .4 05)
3.1 7 (0.12 5)
2.6 7 (0.10 5)
7.2 4 (0.28 5)
0.1 27 (0 .0 05)
1.0 2 (0.04 0)
0 7 6 (0 03 0)
6 9 6 (0 27 5)
32 pad LCC (extended) -'W' Package
0.64 (0.025) typ
1.27 (0.050) typ
2.03 (0.080)
11.70 (0.460)
max
11.30 (0.445)
9.92 (0.390)
10.42 (0.410)
17.65 (0.695)
18.03 (0.710)
No. 1 Index
7.87 (0.310)
1.27 (0.050)
typ
7.37 (0.290)
32 pad JLCC (extended) - 'J' Package
0.71 (0.028) typ
1.27 (0.050) typ
1.98 (0.078)
1.72 (0.068)
12.14 (0.478)
11.60 (0.457)
4.32 (0.170)
0.43 (0.017)
typ
10.41 (0.410)
9.91 (0.390)
17.53 (0.690)
16.51 (0.650)
17.95 (0.707)
18.49 (0.728)
No. 1 Index
7.87 (0.310)
7.37 (0.290)
3.81 (0.150)
11.18 (0.440)
10.16 (0.400)
8
MSM8128 - 70/85/10/12
Issue 4.4 : February 2000
D0
A0
A1
A2
A3
A4
A5
A6
A7
12
11
10
9
8
7
6
5
4
3
2
TOP VIEW
J,W
24
25
26
27
28
29
OE
A11
A9
A8
A13
A14
1
23
14
15
16
17
18
19
20
A10
D1
D2
GND
D3
D4
D5
D6
22
VCC
A15
NC
WE
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
21
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
D7
1
2
3
4
5
6
7
8 TOP VIEW
VX,SX
9
10
11
12
13
14
15
16
CS
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
13
Alternate Pin Definition
32
31
30
A12
A15
A16
NC
VCC
WE
NC
Military Screening Procedure
Component Screening Flow for high reliability product is in accordance with Mil-883 method 5004
MB COMPONENT SCREENING FLOW
SCREEN
TEST METHOD
LEVEL
Visual and Mechanical
Internal visual
Temperature cycle
Constant acceleration
Pre-Burn-in electrical
Burn-in
2010 Condition B or manufacturers equivalent
1010 Condition C (10 Cycles,-65oC to +150oC)
2001 Condition E (Y, only) (30,000g)
Per applicable device specifications at TA=+25oC
Method 1015,Condition D,TA=+125oC,160hrs min
Final Electrical Tests
Per applicable Device Specification
Static (dc)
a) @ TA=+25oC and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Functional
a) @ TA=+25oC and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Switching (ac)
a) @ TA=+25oC and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Percent Defective allowable (PDA)
Calculated at post-burn-in at TA=+25oC
5%
Hermeticity
1014
Fine
Gross
Condition A
Condition C
100%
100%
External Visual
2009 Per vendor or customer specification
100%
9
100%
100%
100%
100%
100%
MSM8128 - 70/85/10/12
Issue 4.4 : February 2000
Ordering Information
MSM8128SLMB - 85
Speed
85 = 85 ns
10 = 100 ns
12 = 120 ns
Temp. range/screening
Blank
I
M
MB
Power Consumption
Blank = Standard Power
L = Low Power
Package
= Commercial
= Industrial
= Military
= Screened in accordance
with MIL-STD-883.
w = 32 pad LCC (extended)
J = 32 pad JLCC (extended)
G = 32 lead Flatpack
WX = 32 pad LCC (Single CS)
JX = 32 pad JLCC (Single CS
GX = 32 lead Flatpack (Single CS)
Organisation
8128 = 128K x 8 SRAM
THESE DEVICES ARE NOT RECOMMENDED FOR NEW
DESIGNS AND MAY BE MADE OBSOLETE WITHOUT
NOTICE....
Although this data is believed to be accurate the information contained herein is not intended to and does not create any
warranty of merchantibility or fitness for a particular purpose.
Our products are subjected to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval of
a company director.
10

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