Low Noise Stereo Codec with Enhanced Recording and Playback Processing ADAU1381

Low Noise Stereo Codec with Enhanced
Recording and Playback Processing
ADAU1381
FEATURES
GENERAL DESCRIPTION
24-bit stereo audio ADC and DAC
400 mW speaker amplifier (into 8 Ω load)
Built-in sound engine for audio processing
Wind noise detection and autofiltering
Enhanced stereo capture (ESC)
Dual-band automatic level control (ALC)
6-band equalizer, including notch filter
Sampling rates from 8 kHz to 96 kHz
Stereo pseudo differential microphone input
Optional stereo digital microphone input pulse-density
modulation (PDM)
Stereo line output
PLL supporting a range of input clock rates
Analog and digital I/O 1.8 V to 3.3 V
Software control via SigmaStudio graphical user interface
Software-controllable, clickless mute
Software register and hardware pin standby mode
32-lead, 5 mm × 5 mm LFCSP or 30-ball, 6 × 5 bump WLCSP
The ADAU1381 is a low power, 24-bit stereo audio codec. The
low noise DAC and ADC support sample rates from 8 kHz to
96 kHz. Low current draw and power saving modes make the
ADAU1381 ideal for battery-powered audio applications.
A configurable sound engine provides enhanced record and
playback processing to improve overall audio quality.
The record path includes two digital stereo microphone inputs
and an analog stereo input path. The analog inputs can be
configured for either a pseudo differential or a single-ended
stereo source. A dedicated analog beep input signal can be
mixed into any output path. The ADAU1381 includes a stereo
line output and speaker driver, which makes the device capable of
supporting dynamic speakers.
The serial control bus supports the I2C® or SPI protocols, and
the serial audio bus is programmable for I2S, left-justified, rightjustified, or TDM mode. A programmable PLL supports flexible
clock generation for all standard rates and available master clocks
from 11 MHz to 20 MHz.
APPLICATIONS
Digital still cameras
Digital video cameras
AGND2
AVDD2
AGND1
AVDD1
DVDDOUT
DGND
IOVDD
CM
FUNCTIONAL BLOCK DIAGRAM
ADAU1381
REGULATOR
BEEP
PGA
SOUND ENGINE
LMIC/LMICN/
MICD1
PGA
LMICP
AOUTL
DECIMATION
FILTERS
LEFT
ADC
AOUTR
LEFT
DAC
WIND NOISE
OUTPUT
MIXER
NOTCH FILTER
EQUALIZER
RMIC/RMICN/
MICD2
PGA
RMICP
RIGHT
ADC
SPP
RIGHT
DAC
SPN
AUTOMATIC LEVEL
CONTROL
08313-001
SDA/COUT
SCL/CCLK
ADDR0/CDATA
DAC_SDATA/
GPIO0
LRCLK/GPIO3
ADDR1/CLATCH
I2C/SPI
CONTROL PORT
SERIAL DATA
INPUT/OUTPUT PORTS
BCLK/GPIO2
PLL
MCKI
MICROPHONE
BIAS
ADC_SDATA/
GPIO1
PDN
MICBIAS
DIGITAL VOLUME
CONTROL
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved.
ADAU1381
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Signal Path ........................................................................ 30
Applications....................................................................................... 1
Analog-to-Digital Converters................................................... 31
General Description ......................................................................... 1
Digital Dual-Band Automatic Level Control (ALC) ............. 31
Functional Block Diagram .............................................................. 1
Playback Signal Path ...................................................................... 32
Revision History ............................................................................... 3
Output Signal Paths ................................................................... 32
Specifications..................................................................................... 4
Digital-to-Analog Converters................................................... 32
Record Side Performance Specifications................................... 4
Line Outputs ............................................................................... 32
Output Side Performance Specifications................................... 6
Speaker Output........................................................................... 32
Power Supply Specifications........................................................ 8
Control Ports................................................................................... 33
Typical Power Management Measurements ............................. 9
I2C Port ........................................................................................ 33
Digital Filters................................................................................. 9
SPI Port ........................................................................................ 36
Digital Input/Output Specifications......................................... 10
Memory and Register Access.................................................... 36
Digital Timing Specifications ................................................... 11
Serial Data Input/Output Ports .................................................... 38
Absolute Maximum Ratings.......................................................... 14
TDM Modes................................................................................ 38
Thermal Resistance .................................................................... 14
General-Purpose Input/Outputs .................................................. 40
ESD Caution................................................................................ 14
Sound Engine.................................................................................. 41
Pin Configuration and Function Descriptions........................... 15
Signal Processing........................................................................ 41
Typical Performance Characteristics ........................................... 17
Processing Flow .......................................................................... 41
System Block Diagrams ................................................................. 20
Programming.............................................................................. 41
Theory of Operation ...................................................................... 24
Parameter Memory .................................................................... 41
Startup, Initialization, and Power ................................................. 25
Applications Information .............................................................. 42
Power-Up Sequence ................................................................... 25
Power Supply Bypass Capacitors.............................................. 42
Clock Generation and Management........................................ 26
GSM Noise Filter ........................................................................ 42
Enabling Digital Power to Functional Subsystems ................ 26
Grounding ................................................................................... 42
Setting Up the Sound Engine.................................................... 26
Speaker Driver Supply Trace (AVDD2) .................................. 42
Power Reduction Modes............................................................ 26
Exposed Pad PCB Design ......................................................... 42
Power-Down Sequence.............................................................. 26
Control Register Map..................................................................... 43
Clocking and Sampling Rates ....................................................... 27
Clock Management, Internal Regulator, and PLL Control... 44
Core Clock................................................................................... 27
Record Path Configuration....................................................... 48
Sampling Rates............................................................................ 27
Serial Port Configuration .......................................................... 53
PLL ............................................................................................... 28
Audio Converter Configuration............................................... 58
Record Signal Path.......................................................................... 30
Playback Path Configuration.................................................... 63
Rev. B | Page 2 of 84
ADAU1381
Pad Configuration.......................................................................70
Outline Dimensions........................................................................84
Digital Subsystem Configuration..............................................77
Ordering Guide ...........................................................................84
REVISION HISTORY
1/11—Rev. A to Rev. B
Changes to Pin PDN Description in Table 10 .............................16
Changes to Power-Down Pin (PDN) Section..............................26
Changes to Table 23 ........................................................................36
3/10—Rev. 0 to Rev. A
Changes to Output Side Performance Specifications Section
Condition Statement.....................................................................6
Added Endnote 1 to Table 3.............................................................8
Changes to Figure 23 ......................................................................20
Changes to Figure 24 ......................................................................21
Changes to Figure 25 ......................................................................22
Changes to Figure 26 ......................................................................23
Changes to Table 27 ........................................................................43
Added Register 16434 (0x4032), Dejitter Control Section ........76
Changes to Ordering Guide...........................................................84
10/09—Revision 0: Initial Version
Rev. B | Page 3 of 84
ADAU1381
SPECIFICATIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
Supply voltages AVDD = AVDD1 = AVDD2 = I/O supply = 3.3 V, digital supply = 1.5 V, unless otherwise noted; temperature = 25°C;
master clock (MCLK) = 12.288 MHz (fS = 48 kHz, 256 × fS mode); input sample rate = 48 kHz; measurement bandwidth = 20 Hz to 20 kHz;
word width = 24 bits; load capacitance (digital output) = 20 pF; load current (digital output) = 2 mA; high level input voltage = 0.7 × IOVDD;
and low level input voltage = 0.3 × IOVDD. All power management registers are set to their default states.
RECORD SIDE PERFORMANCE SPECIFICATIONS
Specifications guaranteed at 25°C (ambient).
Table 1.
Parameter
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
Digital Attenuation Step
Digital Attenuation Range
INPUT RESISTANCE
Noninverting Inputs PGA
(LMICP, RMICP)
Inverting Inputs PGA (LMICN, RMICN)
Beep Input PGA
SINGLE-ENDED MICROPHONE INPUT
TO ADC PATH
Full-Scale Input Voltage (0 dB)
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
Test Conditions/Comments
Min
Typ
Max
Unit
All ADCs
24
0.375
95
Bits
dB
dB
All gain settings
500
kΩ
0 dB gain
6 dB gain
10 dB gain
14 dB gain
17 dB gain
20 dB gain
26 dB gain
32 dB gain
0 dB
6 dB
10 dB
14 dB
−23 dB
20 dB
26 dB
32 dB
62
32
22
14
10
8
5
4
20
9
6
3.5
50
2
2
2
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
−60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
−3 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
V rms
V rms (V p-p)
V rms (V p-p)
96
99.2
92
96.5
dB
dB
dB
dB
−88
−90
dB
dB
96
100
92
97
dB
dB
dB
dB
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
Rev. B | Page 4 of 84
94
92
ADAU1381
Parameter
Left/Right Microphone PGA Gain
Range
Left/Right Microphone PGA Mute
Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
Power Supply Rejection Ratio
DIFFERENTIAL MICROPHONE INPUT TO
ADC PATH
Full-Scale Input Voltage (0 dB)
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
Left/Right Microphone PGA Mute
Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
Common-Mode Rejection Ratio
BEEP TO LINE OUTPUT PATH
Full-Scale Input Voltage (0 dB)
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
Test Conditions/Comments
AVDD = 3.3 V
Min
0
AVDD = 3.3 V; mute set by Register
0x400E, Bit 1, and Register 0x400F, Bit 1
AVDD = 3.3 V
AVDD = 3.3 V
AVDD = 3.3 V
AVDD = 3.3 V
CM capacitor = 10 μF
AVDD = 3.3 V, 100 mV p-p at 217 Hz
AVDD = 3.3 V, 100 mV p-p at 1 kHz
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
−60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
−3 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 3.3 V; mute set by Register
0x400E, Bit 1, and Register 0x400F, Bit 1
AVDD = 3.3 V
AVDD = 3.3 V
AVDD = 3.3 V
AVDD = 3.3 V
AVDD = 3.3 V, 100 mV rms, 1 kHz
AVDD = 3.3 V, 100 mV rms, 20 kHz
94
92
Typ
Max
32
Unit
dB
−98
dB
50
0.25
−1
−98
mdB
mV
%
dB
−55
−55
dB
dB
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
V rms
V rms (V p-p)
V rms (V p-p)
96
99.2
92
96.5
dB
dB
dB
dB
−84
−85
dB
dB
96
100
92
97
−98
dB
dB
dB
dB
dB
50
0.25
−1
−85
−60
−45
mdB
mV
%
dB
dB
dB
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
−3 dBFS input, measured at AOUTL pin,
beep gain set to 0 dB
AVDD = 1.8 V
AVDD = 3.3 V
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
V rms
V rms (V p-p)
V rms (V p-p)
−88
−88
dB
dB
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
99
105
96
102
dB
dB
dB
dB
Rev. B | Page 5 of 84
ADAU1381
Parameter
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Beep Input Mute Attenuation
Offset Error
Gain Error
Interchannel Gain Mismatch
Beep Input PGA Gain Range
Beep Playback Mixer Gain Range
Power Supply Rejection Ratio
MICROPHONE BIAS
Bias Voltage
0.65 × AVDD
0.90 × AVDD
Bias Current Source
Noise in the Signal Bandwidth
Test Conditions/Comments
−60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 3.3 V; mute set by
Register 0x4008, Bit 3
AVDD = 3.3 V
AVDD = 3.3 V
Min
AVDD = 3.3 V
AVDD = 3.3 V
CM capacitor = 10 μF
AVDD = 3.3 V, 100 mV p-p at 217 Hz
AVDD = 3.3 V, 100 mV p-p at 1 kHz
Microphone bias enabled
−23
−15
AVDD = 1.8 V, low bias
AVDD = 3.3 V, low bias
AVDD = 1.8 V, high bias
AVDD = 3.3 V, high bias
AVDD = 3.3 V, high bias, high
performance
AVDD = 3.3 V, 20 Hz to 20 kHz
High bias, high performance
High bias, low performance
Low bias, high performance
Low bias, low performance
AVDD = 1.8 V, 20 Hz to 20 kHz
High bias, high performance
High bias, low performance
Low bias, high performance
Low bias, low performance
Typ
Max
Unit
99
105
96
102
−90
dB
dB
dB
dB
dB
10
−0.3
30
mV
dB
mdB
dB
dB
+32
+6
−58
−72
dB
dB
1.17
2.145
1.62
2.97
V
V
V
V
mA
5
39
78
25
35
nV√Hz
nV√Hz
nV√Hz
nV√Hz
35
45
23
23
nV√Hz
nV√Hz
nV√Hz
nV√Hz
OUTPUT SIDE PERFORMANCE SPECIFICATIONS
Specifications guaranteed at 25°C (ambient). The output load for the speaker output path is an 8 Ω, 400 mW speaker.
Table 2.
Parameter
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
Digital Attenuation Step
Digital Attenuation Range
DAC TO LINE OUTPUT PATH
Full-Scale Output Voltage (0 dB)
Line Output Mute Attenuation,
DAC to Mixer Path Muted
Line Output Mute Attenuation,
Line Output Muted
Test Conditions/Comments
Min
Typ
Max
Unit
All DACs
24
0.375
95
Bits
dB
dB
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 3.3 V; mute set by Register
0x401C, Bit 5, and Register 0x401E, Bit 6
AVDD = 3.3 V; mute set by Register
0x4025, Bit 1, and Register 0x4026, Bit 1
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
−85
V rms
V rms (V p-p)
V rms (V p-p)
dB
−85
dB
Rev. B | Page 6 of 84
ADAU1381
Parameter
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
Power Supply Rejection Ratio
Gain Error
Interchannel Gain Mismatch
Offset Error
DAC TO SPEAKER OUTPUT PATH
Differential Full-Scale Output Voltage
(0 dB)
Total Harmonic Distortion + Noise
4 Ω Load
8 Ω Load
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
Power Supply Rejection Ratio
Differential Offset Error
Mono Mixer Mute Attenuation,
DAC to Mixer Path Muted
BEEP TO SPEAKER OUTPUT PATH
Differential Full-Scale Output Voltage
(0 dB)
Test Conditions/Comments
−60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
−3 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
Min
Typ
Unit
−88
−88
dB
dB
dB
dB
dB
dB
dB
99
103
97
100
dB
dB
dB
dB
−55
−63
−1
50
10
dB
dB
dB
mdB
mV
AVDD/1.65
V rms
AVDD = 1.8 V
AVDD = 3.3 V
1.1 (3.12)
2.0 (5.66)
V rms (V p-p)
V rms (V p-p)
AVDD = 1.8 V, PO = 50 mW
AVDD = 3.3 V, PO = 175 mW
AVDD = 1.8 V, PO = 50 mW
AVDD = 3.3 V, PO = 175 mW
AVDD = 3.3 V, PO = 330 mW
AVDD = 3.3 V, PO = 440 mW
−60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
−60
−60
−60
−60
−60
−16
dB
dB
dB
dB
dB
dB
100
105
98
103
dB
dB
dB
dB
94
92
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
CM capacitor = 10 μF
AVDD = 3.3 V, 100 mV p-p at 217 Hz
AVDD = 3.3 V, 100 mV p-p at 1 kHz
AVDD = 3.3 V
AVDD = 3.3 V
AVDD = 3.3 V
PO = output power
Scales linearly with AVDD
94
92
99
103
97
100
Max
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
CM capacitor = 10 μF
AVDD = 3.3 V,100 mV p-p at 217 Hz
AVDD = 3.3 V, 100 mV p-p at 1 kHz
AVDD = 3.3 V
Mute set by Register 0x401F, Bit 0
100
105
98
103
dB
dB
dB
dB
−55
−55
2
−90
dB
dB
mV
dB
PO = output power
Scales linearly with AVDD
AVDD/1.65
V rms
AVDD = 1.8 V
AVDD = 3.3 V
1.1 (3.12)
2.0 (5.66)
V rms (V p-p)
V rms (V p-p)
Rev. B | Page 7 of 84
ADAU1381
Parameter
Total Harmonic Distortion + Noise
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
Power Supply Rejection Ratio
Differential Offset Error
Mono Mixer Mute Attenuation,
Beep to Mixer Path Muted
REFERENCE (CM PIN)
Common-Mode Reference Output
Test Conditions/Comments
Min
Typ
Max
Unit
8 Ω, 1 nF load, AVDD = 1.8 V, PO = 50 mW
AVDD = 3.3 V, PO = 175 mW
−60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
−60
−60
dB
dB
97
103
94
100
dB
dB
dB
dB
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
CM capacitor = 10 μF
100 mV p-p at 217 Hz
100 mV p-p at 1 kHz
98
103
96
101
dB
dB
dB
dB
−57
−60
2
−90
dB
dB
mV
dB
AVDD/2
V
Mute set by Register 0x401F, Bit 0
POWER SUPPLY SPECIFICATIONS
AVDD1 and AVDD2 must always be equal. Power supply measurements are taken with the sound engine processing path enabled.
Table 3.
Parameter
AVDD1, AVDD2
IOVDD
Digital I/O Current (IOVDD = 3.3 V)
Slave Mode, Analog I/O,
12.288 MHz External MCLK Input
Master Mode, MCKO Disabled
Digital I/O Current (IOVDD = 1.8 V)
Slave Mode, Analog I/O,
12.288 MHz External MCLK Input
Master Mode, MCKO Disabled
Analog Current (AVDD)
1
Test Conditions/Comments
20 pF capacitive load on all digital pins
fS = 48 kHz
Min
1.8 1
1.63
Typ
3.3
3.3
Max
3.65
3.65
Unit
V
V
0.20
mA
fS = 96 kHz
fS = 8 kHz
fS = 48 kHz
fS = 96 kHz
fS = 8 kHz
20 pF capacitive load on all digital pins
fS = 48 kHz
0.35
0.04
1.25
2.50
0.22
mA
mA
mA
mA
mA
0.10
mA
fS = 96 kHz
fS = 8 kHz
fS = 48 kHz
fS = 96 kHz
fS = 8 kHz
See Table 4
0.18
0.02
0.68
1.33
0.12
mA
mA
mA
mA
mA
The zero-cross detection of the beep path is not supported at AVDD1, AVDD2 < 2.2 V.
Rev. B | Page 8 of 84
ADAU1381
TYPICAL POWER MANAGEMENT MEASUREMENTS
Master clock = 12.288 MHz, PLL is active in integer mode at a 256 × fS input rate for fS = 48 kHz, analog and digital input tones are
−1 dBFS with a frequency of 1 kHz. Analog input and output are simultaneously active. Pseudo differential stereo input is routed to
ADCs, and DACs are routed to stereo line output with a 16 kΩ load. ADC input at −1 dBFS, DAC input at 0 dBFS. The speaker output is
disabled. The serial port is configured in slave mode. The beep path is disabled. The sound engine processing path is enabled. Current
measurements are given in units of mA rms.
Table 4. Mixer Boost and Power Management Conditions
Operating Voltage
AVDD = IOVDD = 3.3 V
Power Management Mode 1
Normal (default)
Extreme power saving
Enhanced performance
Power saving
AVDD = IOVDD = 1.8 V
Normal (default)
Extreme power saving
Enhanced performance
Power saving
1
2
Mixer Boost Mode 2
Normal operation
Boost Level 1
Boost Level 2
Boost Level 3
Normal operation
Boost Level 1
Boost Level 2
Boost Level 3
Normal operation
Boost Level 1
Boost Level 2
Boost Level 3
Normal operation
Boost Level 1
Boost Level 2
Boost Level 3
Normal operation
Boost Level 1
Boost Level 2
Boost Level 3
Normal operation
Boost Level 1
Boost Level 2
Boost Level 3
Normal operation
Boost Level 1
Boost Level 2
Boost Level 3
Normal operation
Boost Level 1
Boost Level 2
Boost Level 3
Typical AVDD Current
Consumption (mA)
16.84
16.88
16.92
17.00
15.66
15.68
15.70
15.75
17.43
17.50
17.53
17.63
16.25
16.28
16.31
16.38
15.15
15.19
15.23
15.30
14.03
14.05
14.07
14.12
15.71
15.76
15.81
15.89
14.59
14.62
14.65
14.71
Typical ADC
THD + N (dB)
88.5
88.5
88.5
88.5
88.0
88.0
88.0
88.0
88.5
88.5
88.5
88.5
89.0
89.0
89.0
89.0
88.5
88.5
88.5
88.5
86.5
86.5
86.5
86.5
88.5
88.5
88.5
88.5
88.0
88.0
88.0
88.0
Typical Line Output
THD + N (dB)
93.0
93.0
93.0
93.0
87.5
87.5
87.5
87.5
94.5
94.5
94.5
94.5
90.5
90.5
90.5
90.5
89.5
89.5
89.5
89.5
85.5
85.5
85.5
85.5
90.5
90.5
90.5
90.5
88.0
88.0
88.0
88.0
Set by Register 0x4009, Bits[4:1], and Register 0x4029, Bits[5:2].
Set by Register 0x4009, Bits[6:5].
DIGITAL FILTERS
Table 5.
Parameter
ADC DECIMATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Mode
All modes, typ value is for 48 kHz
Factor
Min
0.4375 × fS
Typ
21
±0.015
24
27
0.5 × fS
0.5625 × fS
70
22.9844/fS
Rev. B | Page 9 of 84
479
Max
Unit
kHz
dB
kHz
kHz
dB
μs
ADAU1381
Parameter
DAC INTERPOLATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Mode
Factor
Min
Typ
48 kHz mode, typ value is for 48 kHz
96 kHz mode, typ value is for 96 kHz
48 kHz mode, typ value is for 48 kHz
96 kHz mode, typ value is for 96 kHz
48 kHz mode, typ value is for 48 kHz
96 kHz mode, typ value is for 96 kHz
48 kHz mode, typ value is for 48 kHz
96 kHz mode, typ value is for 96 kHz
48 kHz mode, typ value is for 48 kHz
96 kHz mode, typ value is for 96 kHz
48 kHz mode, typ value is for 48 kHz
96 kHz mode, typ value is for 96 kHz
0.4535 × fS
0.3646 × fS
35
22
69
Max
±0.01
±0.05
0.5 × fS
0.5 × fS
0.5465 × fS
0.6354 × fS
24
48
26
61
70
70
25/fS
11/fS
521
115
Unit
kHz
kHz
dB
dB
kHz
kHz
kHz
kHz
dB
dB
μs
μs
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−25°C < TA < +85°C, IOVDD = 1.62 V to 3.63 V, unless otherwise specified.
Table 6.
Parameter
HIGH LEVEL INPUT VOLTAGE (VIH)
LOW LEVEL INPUT VOLTAGE (VIL)
INPUT LEAKAGE
HIGH LEVEL OUTPUT VOLTAGE (VOH)
LOW LEVEL OUTPUT VOLTAGE (VOL)
Conditions/Comments
IOVDD ≥ 2.97 V
1.8 V ≤ IOVDD ≤ 2.97 V
IOVDD < 1.8 V
IIH at VIH = 2.4 V
IIL at VIL = 0.8 V
IIL of MCKI
IIH with internal pull-up
IIL with internal pull-down
IIH with internal pull-up
IIL with internal pull-down
For low drive strength, IOH = 2 mA and IOL = 2 mA
at IOVDD = 3.3 V, IOH = 0.6 mA and IOL = 0.6 mA at
IOVDD = 1.8 V; for high drive strength, IOH = 3 mA
and IOL = 3 mA at IOVDD = 3.3 V, IOH = 0.9 mA and
IOL = 0.9 mA at IOVDD = 1.8 V
For low drive strength, IOH = 2 mA and IOL = 2 mA
at IOVDD = 3.3 V, IOH = 0.6 mA and IOL = 0.6 mA at
IOVDD = 1.8 V; for high drive strength, IOH = 3 mA
and IOL = 3 mA at IOVDD = 3.3 V, IOH = 0.9 mA and
IOL = 0.9 mA at IOVDD = 1.8 V
INPUT CAPACITANCE
Rev. B | Page 10 of 84
Min
0.7 × IOVDD
Typ
Max
0.3 × IOVDD
0.2 × IOVDD
0.1 × IOVDD
±0.17
±0.17
−7
±0.7
−7
5
±0.18
IOVDD − 0.4
Unit
V
V
V
V
μA
μA
μA
μA
μA
μA
μA
V
0.4
V
5
pF
ADAU1381
DIGITAL TIMING SPECIFICATIONS
−25°C < TA < +85°C, IOVDD = 1.62 V to 3.63 V, unless otherwise specified.
Table 7. Digital Timing
Parameter
MASTER CLOCK
tMP
Duty Cycle
SERIAL PORT
tBIL
tBIH
tLIS
tLIH
tSIS
tSIH
tSODM
SPI PORT
fCCLK,R
fCCLK,R
fCCLK,W
fCCLK,W
tCCPL
tCCPH
tCLS
tCLH
tCLPH
tCDS
tCDH
tCOD
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tSCR
tSCF
tSDR
tSDF
tBFT
DIGITAL MICROPHONE
tDCF
tDCR
tDDV
tDDH
tMIN
50
30
Limit
tMAX
Unit
Description
90.9
70
ns
%
Master clock (MCLK) period (that is, period of the signal input to MCKI).
70
ns
ns
ns
ns
ns
ns
ns
BCLK pulse width low.
BCLK pulse width high.
LRCLK setup. Time to BCLK rising.
LRCLK hold. Time from BCLK rising.
DAC_SDATA setup. Time to BCLK rising.
DAC_SDATA hold. Time from BCLK rising.
ADC_SDATA delay. Time from BCLK falling in master mode.
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
CCLK frequency, read operation, IOVDD = 1.8 V ± 10%.
CCLK frequency, read operation, IOVDD = 3.3 V ± 10%.
CCLK frequency, write operation, IOVDD = 1.8 V ± 10%.
CCLK frequency, write operation, IOVDD = 3.3 V ± 10%.
CCLK pulse width low.
CCLK pulse width high.
CLATCH setup. Time to CCLK rising.
CLATCH hold. Time from CCLK rising.
CLATCH pulse width high.
CDATA setup. Time to CCLK rising.
CDATA hold. Time from CCLK rising.
COUT delay from CCLK edge to valid data, IOVDD = 1.8 V ± 10%.
COUT delay from CCLK edge to valid data, IOVDD = 3.3 V ± 10%.
10
10
5
5
5
5
5
10
25
25
10
10
10
5
10
5
5
70
40
400
0.6
1.3
0.6
0.6
100
300
300
300
300
0.6
22
0
10
10
30
12
ns
kHz
μs
μs
μs
μs
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
SCL frequency.
SCL high.
SCL low.
Setup time; relevant for repeated start condition.
Hold time. After this period, the first clock is generated.
Data setup time.
SCL rise time.
SCL fall time.
SDA rise time.
SDA fall time.
Bus-free time. Time between stop and start.
RL = 1 MΩ, CL = 14 pF.
Digital microphone clock fall time.
Digital microphone clock rise time.
Digital microphone delay time for valid data.
Digital microphone delay time for data three-stated.
Rev. B | Page 11 of 84
ADAU1381
Digital Timing Diagrams
tLIH
tBIH
BCLK
tBIL
tLIS
LRCLK
tSIS
DAC_SDATA
LEFT-JUSTIFIED
MODE
MSB
MSB – 1
tSIH
tSIS
DAC_SDATA
I2S MODE
MSB
tSIH
tSIS
tSIS
DAC_SDATA
RIGHT-JUSTIFIED
MODE
LSB
MSB
tSIH
tSIH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
08313-002
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Serial Input Port Timing
tBIH
BCLK
tBIL
LRCLK
ADC_SDATA
LEFT-JUSTIFIED
MODE
tSODM
MSB
MSB – 1
tSODM
ADC_SDATA
I2S MODE
MSB
tSODM
ADC_SDATA
RIGHT-JUSTIFIED
MODE
MSB
LSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
08313-003
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 3. Serial Output Port Timing
Rev. B | Page 12 of 84
ADAU1381
tCLS
tCLH
tCLPH
tCCPL
tCCPH
CLATCH
CCLK
CDATA
tCDH
tCDS
COUT
08313-004
tCOD
Figure 4. SPI Port Timing
tSDR
tSCH
tDS
tSCH
SDA
tSDF
tSCR
SCL
tSCLL
tSCS
tSCF
tBFT
2
Figure 5. I C Port Timing
tDCF
tDCR
CLK
DATA1/
DATA2 DATA1
DATA2
tDDH
tDDV
tDDV
DATA1
DATA2
Figure 6. Digital Microphone Timing
Rev. B | Page 13 of 84
08313-106
tDDH
08313-005
tSCLH
ADAU1381
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 8.
Parameter
Power Supply (AVDD1 = AVDD2)
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range (Case)
Storage Temperature Range
Rating
−0.3 V to +3.9 V
±20 mA
–0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−25°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
In Table 9, θJA is the junction-to-ambient thermal resistance, θJB is
the junction-to-board thermal resistance, θJC is the junction-to-case
thermal resistance, ψJB is the in-use junction-to-top of package thermal resistance, and ψJT is the in-use junction-to-board thermal
resistance. All characteristics are for a 4-layer board.
Table 9. Thermal Resistance
Package Type
32-Lead LFCSP
30-Ball WLCSP
ESD CAUTION
Rev. B | Page 14 of 84
θJA
35
39
θJB
19
7
θJC
2.5
0.5
ψJB
18
ψJT
0.3
Unit
°C/W
°C/W
ADAU1381
32
31
30
29
28
27
26
25
MICBIAS
BEEP
LMIC/LMICN/MICD1
LMICP
RMICP
RMIC/RMICN/MICD2
AOUTL
AOUTR
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
ADAU1381
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
NC
AGND2
SPP
NC
SPN
AVDD2
MCKO
MCKI
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE
ADAU1381 GROUNDS. FOR INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE SOLDERED TO THE
GROUND PLANE.
08313-007
SDA/COUT
ADDR0/CDATA
ADDR1/CLATCH
IOVDD
DAC_SDATA/GPIO0
ADC_SDATA/GPIO1
BCLK/GPIO2
LRCLK/GPIO3
9
10
11
12
13
14
15
16
CM
PDN
AGND1
AVDD1
DVDDOUT
DGND
GPIO
SCL/CCLK
1
2
3
4
5
6
A
AGND2
AOUTL
RMICP
LMIC/
LIMICN/
MICD1
MICBIAS
CM
B
SPP
AOUTR
RMIC/
RMICN/
MICD2
LMICP
BEEP
AGND1
C
SPN
LRCLK/
GPIO3
ADDR0/
CDATA
SCL/
CCLK
PDN
AVDD1
D
AVDD2
MCKO
ADC_
SDATA/
GPIO1
ADDR1/
CLATCH
GPIO
DVDDOUT
E
MCKI
BCLK/
GPIO2
DAC_
SDATA/
GPIO0
IOVDD
SDA/
COUT
DGND
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 8. 30-Ball, 6 × 5 WLCSP Pin Configuration (Bottom View)
Rev. B | Page 15 of 84
08313-008
Figure 7. 32-Lead LFCSP Pin Configuration
ADAU1381
Table 10. Pin Function Descriptions
Pin No.
LFCSP
1
WLCSP
A6
Mnemonic
CM
Type 1
A_OUT
2
C5
PDN
A_IN
3
4
5
B6
C6
D6
AGND1
AVDD1
DVDDOUT
PWR
PWR
PWR
6
7
8
9
10
11
12
E6
D5
C4
E5
C3
D4
E4
DGND
GPIO
SCL/CCLK
SDA/COUT
ADDR0/CDATA
ADDR1/CLATCH
IOVDD
PWR
D_IO
D_IN
D_IO
D_IN
D_IN
PWR
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
E3
D3
E2
C2
E1
D2
D1
C1
N/A
B1
A1
N/A
B2
A2
B3
DAC_SDATA/GPIO0
ADC_SDATA/GPIO1
BCLK/GPIO2
LRCLK/GPIO3
MCKI
MCKO
AVDD2
SPN
NC
SPP
AGND2
NC
AOUTR
AOUTL
RMIC/RMICN/MICD2
D_IO
D_IO
D_IO
D_IO
D_IN
D_OUT
PWR
A_OUT
28
29
30
A3
B4
A4
RMICP
LMICP
LMIC/LMICN/MICD1
A_IN
A_IN
A_IN
31
32
B5
A5
BEEP
MICBIAS
THERM_PAD
(Exposed Pad)
A_IN
PWR
1
A_OUT
PWR
A_OUT
A_OUT
A_IN
Description
VDD/2 V Common-Mode Reference. A 10 μF to 47 μF decoupling capacitor should be
connected between this pin and ground to reduce crosstalk between the ADCs and
DACs. The material of the capacitors is not critical. This pin can be used to bias external
analog circuits, as long as they are not drawing current from CM (for example, the
noninverting input of an op amp).
Power-Down. Connecting this pin to GND powers down the chip. Resides in AVDD1
domain.
Analog Ground.
Analog Power Supply. Should be equivalent to AVDD2.
Digital Core Supply Decoupling Point. The digital supply is generated from an onboard regulator and does not require an external supply. DVDDOUT should be
decoupled to DGND with a 100 nF capacitor.
Digital Ground.
Dedicated General-Purpose Input/Output.
I2C Clock/SPI Clock.
I2C Data/SPI Data Output.
I2C Address 0/SPI Data Input.
I2C Address 1/SPI Latch Signal.
Supply for Digital Input and Output Pins. The digital output pins are supplied from
IOVDD, which sets the highest allowed input voltage for the digital input pins. The
current draw of this pin is variable because it is dependent on the loads of the digital
outputs. IOVDD should be decoupled to DGND with a 100 nF capacitor.
DAC Serial Input Data/General-Purpose Input and Output.
ADC Serial Output Data/General-Purpose Input and Output.
Serial Data Port Bit Clock/General-Purpose Input and Output.
Serial Data Port Frame Clock/General-Purpose Input and Output.
Master Clock Input.
Master Clock Output.
Analog Power Supply. Should be equivalent to AVDD1.
Speaker Amplifier Negative Signal Output.
No Connect.
Speaker Amplifier Positive Signal Output.
Speaker Amplifier Ground.
No Connect.
Line Output Amplifier, Right Channel.
Line Output Amplifier, Left Channel.
Right Channel Input from Single-Ended Source/Right Channel Input from Negative
Pseudo Differential Source/Digital Microphone Input 2.
Right Channel Input from Positive Pseudo Differential Source.
Left Channel Input from Positive Pseudo Differential Source.
Left Channel Input from Single-Ended Source/Left Channel Input from Negative
Pseudo Differential Source/Digital Microphone Input 1.
Beep Signal Input.
Microphone Bias.
Exposed Pad. The exposed pad is connected internally to the ADAU1381 grounds. For
increased reliability of the solder joints and maximum thermal capability, it is
recommended that the pad be soldered to the ground plane.
A_OUT = analog output, A_IN = analog input, PWR = power, D_IO = digital input/output, D_OUT = digital output, and D_IN = digital input.
Rev. B | Page 16 of 84
ADAU1381
0
0.10
–10
0.08
–20
0.06
–30
0.04
MAGNITUDE (dBFS)
–40
–50
–60
–70
0.02
0
–0.02
–0.04
–80
–0.06
–90
–0.08
–0.10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
FREQUENCY (NORMALIZED TO fS)
08313-009
–100
Figure 9. ADC Decimation Filter, 64× Oversampling,
Normalized to fS
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
08313-012
MAGNITUDE (dBFS)
TYPICAL PERFORMANCE CHARACTERISTICS
0.50
FREQUENCY (NORMALIZED TO fS)
Figure 12. ADC Decimation Filter Pass-Band Ripple, 128× Oversampling,
Normalized to fS
0
0.04
–10
–20
–30
MAGNITUDE (dBFS)
MAGNITUDE (dBFS)
0.02
0
–0.02
–0.04
–40
–50
–60
–70
–80
–0.06
–90
0.10
0.15
0.20
0.25
0.30
0.35
0.40
FREQUENCY (NORMALIZED TO fS)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
FREQUENCY (NORMALIZED TO fS)
1.0
08313-013
0.05
08313-010
0
–100
Figure 13. ADC Decimation Filter, Double-Rate Mode,
Normalized to fS
Figure 10. ADC Decimation Filter Pass-Band Ripple, 64× Oversampling,
Normalized to fS
0
0.04
–10
0.02
MAGNITUDE (dBFS)
–30
–40
–50
–60
–70
0
–0.02
–0.04
–80
–100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
FREQUENCY (NORMALIZED TO fS)
Figure 11. ADC Decimation Filter, 128× Oversampling,
Normalized to fS
1.0
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
FREQUENCY (NORMALIZED TO fS)
0.40
08313-014
–0.06
–90
08313-011
MAGNITUDE (dBFS)
–20
Figure 14. ADC Decimation Filter Pass-Band Ripple, Double-Rate Mode,
Normalized to fS
Rev. B | Page 17 of 84
0
0.05
–10
0.04
–20
0.03
–30
0.02
MAGNITUDE (dBFS)
–40
–50
–60
–70
0.01
0
–0.01
–0.02
–80
–0.03
–90
–0.04
–0.05
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
FREQUENCY (NORMALIZED TO fS)
08313-015
–100
Figure 15. DAC Interpolation Filter, 64× Oversampling,
Normalized to fS
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
FREQUENCY (NORMALIZED TO fS)
08313-018
MAGNITUDE (dBFS)
ADAU1381
Figure 18. DAC Interpolation Filter Pass-Band Ripple, 128× Oversampling,
Normalized to fS
0.20
0
–10
0.15
–20
MAGNITUDE (dBFS)
MAGNITUDE (dBFS)
0.10
0.05
0
–0.05
–30
–40
–50
–60
–70
–0.10
–80
–0.15
–90
0.10
0.15
0.20
0.25
0.30
0.35
0.40
FREQUENCY (NORMALIZED TO fS)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
08313-019
0.05
0.40
08313-020
–100
0
08313-016
–0.20
FREQUENCY (NORMALIZED TO fS)
Figure 16. DAC Interpolation Filter Pass-Band Ripple, 64× Oversampling,
Normalized to fS
Figure 19. DAC Interpolation Filter, Double-Rate Mode,
Normalized to fS
0
0.20
–10
0.15
–20
MAGNITUDE (dBFS)
–40
–50
–60
–70
0.05
0
–0.05
–0.10
–80
–0.15
–90
–100
–0.20
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
FREQUENCY (NORMALIZED TO fS)
Figure 17. DAC Interpolation Filter, 128× Oversampling,
Normalized to fS
1.0
08313-017
MAGNITUDE (dBFS)
0.10
–30
0
0.05
0.10
0.15
0.20
0.25
0.30
FREQUENCY (NORMALIZED TO fS)
0.35
Figure 20. DAC Interpolation Filter Pass-Band Ripple, Double-Rate Mode,
Normalized to fS
Rev. B | Page 18 of 84
ADAU1381
0
0
–10
–20
–20
–40
THD + N (dB)
THD + N (dB)
–30
–50
–60
–40
–60
–70
–80
–80
–90
1
10
100
SPEAKER OUTPUT POWER (mW)
600
Figure 21. THD + N vs. Speaker Output Power, 8 Ω Load, 3.3 V Supply
1
10
SPEAKER OUTPUT POWER (mW)
100
08313-122
–100
08313-121
–100
Figure 22. THD + N vs. Speaker Output Power, 8 Ω Load, 1.8 V Supply
Rev. B | Page 19 of 84
ADAU1381
SYSTEM BLOCK DIAGRAMS
IOVDD
10µF
AVDD1
10µF
10µF
+
+
0.1µF
0.1µF
+
AVDD2
47µF
0.1µF
+
MICBIAS
8Ω
SPEAKER
OUT
–
0.1µF
0.1µF
49.9kΩ
AVDD2
AVDD1
DVDDOUT
10µF
IOVDD
DIFFERENTIAL INPUT
(LEFT)
MICBIAS
+
100pF
LMIC/LMICN/MICD1
SPN
LMICP
SPP
10kΩ
10kΩ
10Ω 220µF
AOUTL
10µF
STEREO SINGLE-ENDED
HEADPHONE OUTPUT
49.9kΩ
10kΩ
ADAU1381
100pF
DIFFERENTIAL INPUT
(RIGHT)
10µF
10kΩ
RMIC/RMICN/MICD2
49.9kΩ
LEFT_OUT
+
AOUTR
10kΩ
10kΩ
10Ω 220µF
+
RMICP
CM
10µF
100nF
+
RIGHT_OUT
10µF
49.9kΩ
GPIO
10µF
STEREO
HEADPHONE
AMPLIFIER
GPIO
BEEP
DAC_SDATA/GPIO0
ADC_SDATA/GPIO1
BCLK/GPIO2
LRCLK/GPIO3
EXTERNAL
BEEP INPUT
MCKI
PDN
PDN
08313-021
MCKO
SYSTEM
CONTROLLER
AGND2
49.9Ω
AGND1
ADDR1/CLATCH
ADDR0/CDATA
SDA/COUT
SCL/CCLK
2.2pF
DGND
MCKO
49.9Ω
THERM_PAD
(EXPOSED PAD)
EXTERNAL
MCLK SOURCE
SERIAL
DATA
Figure 23. System Block Diagram with Differential Inputs
Rev. B | Page 20 of 84
ADAU1381
IOVDD
10µF
AVDD1
10µF
10µF
+
+
0.1µF
0.1µF
+
AVDD2
47µF
0.1µF
+
MICBIAS
8Ω
SPEAKER
OUT
–
0.1µF
0.1µF
2kΩ
AVDD2
AVDD1
DVDDOUT
MICBIAS
IOVDD
MICBIAS
+
100pF
SPN
0.1µF
10kΩ
SPP
ANALOG
MIC 1
LMIC/LMICN/MICD1
10µF
10kΩ
LMICP
AOUTR
CM
ADAU1381
ANALOG
MIC 2
10kΩ
10kΩ
0.1µF
10kΩ
10kΩ
10Ω 220µF
10µF
+
RMIC/RMICN/MICD2
49.9kΩ
LEFT_OUT
100pF
MICBIAS
2kΩ
10Ω 220µF
AOUTL
CM
+
49.9kΩ
STEREO SINGLE-ENDED
HEADPHONE OUTPUT
CM
CM
RMICP
100nF
+
RIGHT_OUT
10µF
GPIO
10µF
STEREO
HEADPHONE
AMPLIFIER
GPIO
BEEP
DAC_SDATA/GPIO0
ADC_SDATA/GPIO1
BCLK/GPIO2
LRCLK/GPIO3
EXTERNAL
BEEP INPUT
MCKI
MCKO
PDN
08313-022
PDN
SYSTEM
CONTROLLER
AGND2
49.9Ω
AGND1
ADDR1/CLATCH
ADDR0/CDATA
SDA/COUT
SCL/CCLK
2.2pF
DGND
MCKO
49.9Ω
THERM_PAD
(EXPOSED PAD)
EXTERNAL
MCLK SOURCE
SERIAL
DATA
Figure 24. System Block Diagram with Analog Microphone Inputs
Rev. B | Page 21 of 84
ADAU1381
IOVDD
10µF
AVDD1
10µF
10µF
+
+
0.1µF
0.1µF
+
AVDD2
47µF
0.1µF
+
MICBIAS
8Ω
SPEAKER
OUT
–
0.1µF
0.1µF
AVDD2
AVDD1
DVDDOUT
IOVDD
MICBIAS
+
100pF
SPN
SINGLE-ENDED
STEREO INPUT
10kΩ
SPP
10kΩ
10µF
CM
49.9kΩ
10Ω 220µF
AOUTL
LMIC/LMICN/MICD1
AOUTR
LMICP
LEFT_OUT
+
1kΩ
STEREO SINGLE-ENDED
HEADPHONE OUTPUT
10kΩ
CM
ADAU1381
100pF
10µF
1kΩ
RMIC/RMICN/MICD2
10kΩ
CM
49.9kΩ
10kΩ
10kΩ
10Ω 220µF
+
RMICP
CM
100nF
+
RIGHT_OUT
10µF
GPIO
10µF
STEREO
HEADPHONE
AMPLIFIER
GPIO
BEEP
DAC_SDATA/GPIO0
ADC_SDATA/GPIO1
BCLK/GPIO2
LRCLK/GPIO3
EXTERNAL
BEEP INPUT
MCKI
MCKO
PDN
08313-023
PDN
SYSTEM
CONTROLLER
AGND2
49.9Ω
AGND1
ADDR1/CLATCH
ADDR0/CDATA
SDA/COUT
SCL/CCLK
2.2pF
DGND
MCKO
49.9Ω
THERM_PAD
(EXPOSED PAD)
EXTERNAL
MCLK SOURCE
SERIAL
DATA
Figure 25. System Block Diagram with Single-Ended Stereo Line Inputs
Rev. B | Page 22 of 84
ADAU1381
IOVDD
10µF
AVDD1
10µF
10µF
+
+
0.1µF
0.1µF
+
AVDD2
47µF
0.1µF
+
MICBIAS
8Ω
SPEAKER
OUT
–
0.1µF
0.1µF
AVDD2
AVDD1
DVDDOUT
IOVDD
MICBIAS
+
100pF
SPN
BCLK OR MCLKO
10kΩ
SPP
10kΩ
10Ω 220µF
AOUTL
LMIC/LMICN/MICD1
AOUTR
LMICP
10kΩ
ADAU1381
100pF
RMIC/RMICN/MICD2
10kΩ
10kΩ
RMICP
10kΩ
10Ω 220µF
+
1kΩ
LEFT_OUT
+
STEREO DIGITAL
MIC INPUT
STEREO SINGLE-ENDED
HEADPHONE OUTPUT
CM
100nF
+
RIGHT_OUT
10µF
GPIO
10µF
STEREO
HEADPHONE
AMPLIFIER
GPIO
BEEP
DAC_SDATA/GPIO0
ADC_SDATA/GPIO1
BCLK/GPIO2
LRCLK/GPIO3
EXTERNAL
BEEP INPUT
MCKI
MCKO
PDN
08313-024
PDN
SYSTEM
CONTROLLER
AGND2
49.9Ω
AGND1
ADDR1/CLATCH
ADDR0/CDATA
SDA/COUT
SCL/CCLK
2.2pF
DGND
MCKO
BCLK
49.9Ω
THERM_PAD
(EXPOSED PAD)
EXTERNAL
MCLK SOURCE
SERIAL
DATA
Figure 26. System Block Diagram with Stereo Digital Microphone Inputs
Rev. B | Page 23 of 84
ADAU1381
THEORY OF OPERATION
The ADAU1381 is a low power audio codec with an integrated,
fixed-function audio processing sound engine. It is an all-in-one
package that offers high quality audio, low power, small size, and
many advanced features. The stereo ADC and stereo DAC each
have a dynamic range (DNR) performance of at least 96.5 dB and
a total harmonic distortion plus noise (THD + N) performance
of at least −90 dB. The serial data port is compatible with I2S, leftjustified, right-justified, and TDM modes for interfacing to digital
audio data. The operating voltage range is 1.8 V to 3.65 V, with
an on-board regulator generating the internal digital supply voltage.
The record path includes very flexible input configurations that
can accept differential or single-ended analog microphone inputs
as well as two stereo digital microphone inputs. There is also a
beep input pin (BEEP) dedicated to analog beep signals that are
common in digital still camera applications. A microphone bias
pin that can power electrets-type microphones is also available.
Each input signal has its own programmable gain amplifier (PGA)
for input volume adjustment. An automatic level control (ALC)
is built into the sound engine to maintain a constant input recording volume.
The ADCs and DACs are high quality, 24-bit Σ-Δ converters
that operate at selectable 64× or 128× oversampling rates. The
base sampling rate of the converters is set by the input clock rate
and can be further scaled with the converter control register
settings. The converters can operate at sampling frequencies
from 8 kHz to 96 kHz. The ADCs and DACs also include very
fine-step digital volume controls.
The playback path allows input signals and DAC outputs to be
mixed into speaker and/or line outputs. The speaker driver is
capable of driving 400 mW into an 8 Ω load.
The fixed-function sound engine contains a digital audio
processing flow optimized for digital still camera stereo audio
processing. However, the flexibility offered by the built-in
sound engine allows this codec to be used for a wide variety of
low power applications. Signal processing blocks included in the
sound engine include the following:
•
•
•
•
•
•
•
•
Wind noise detection and autofiltering
Dual-band compression with programmable crossover,
compression curves, and timing
Programmable multiband equalizer
Configurable notch filter
Enhanced stereo capture algorithm
Automatic level control
Digital volume control
Multiplexers for signal routing
The ADAU1381 can generate its internal clocks from a wide
range of input clocks by using the on-board fractional PLL.
The PLL accepts inputs from 11 MHz to 20 MHz.
The ADAU1381 is provided in a small, 32-lead, 5 mm × 5 mm
lead frame chip scale package (LFCSP) with an exposed bottom
pad, or a 30-ball (6 × 5 bump), 3.4 mm × 2.64 mm wafer level
chip scale package (WLCSP).
Rev. B | Page 24 of 84
ADAU1381
STARTUP, INITIALIZATION, AND POWER
POWER-UP SEQUENCE
This section details the procedure for setting up the ADAU1381
properly. Figure 27 provides an overview of how to initialize the IC.
If AVDD1 and AVDD2 are from the same supply, they can
power up simultaneously. If AVDD1 and AVDD2 are from
separate supplies, then AVDD1 should be powered up first.
IOVDD should be applied simultaneously with AVDD1, if
possible.
START
ARE AVDD1 AND AVDD2
SUPPLIED SEPARATELY?
YES
NO
NO
CAN AVDD1 AND AVDD2
BE SIMULTANEOUSLY
SUPPLIED?
The ADAU1381 uses a power-on reset (POR) circuit to reset the
registers upon power-up. The POR monitors the DVDDOUT
pin and generates a reset signal whenever power is applied to
the chip. During the reset, the ADAU1381 is set to the default
values documented in the register map (see the Control Register
Map section).
YES
SUPPLY POWER
TO AVDD1
SUPPLY POWER TO AVDD1/AVDD2
PINS SIMULTANEOUSLY
SUPPLY POWER
TO AVDD2
The POR is also used to prevent clicks and pops on the speaker
driver output. The power-up sequencing and timing involved is
described in Figure 28 in this section, and in Figure 36 and
Figure 37 of the Speaker Output section.
SUPPLY POWER TO IOVDD
WAIT 14ms FOR POWER-ON RESET
AND INITIALIZATION ROM BOOT
A self-boot ROM initializes the memories after the POR has
completed. When the self-boot sequence is complete, the control
registers are accessible via the I2C/SPI control port and should
then be configured as required for the application. Typically,
with a 10 μF capacitor on AVDD1, the power supply ramp-up,
POR, and self-boot combined take approximately 14 ms.
CONFIGURE CLOCK GENERATION
REGISTER 16384 (0x4000)
AND REGISTER 16386 (0x4002)
WAIT FOR PLL LOCK
(2.4ms TO 3.5ms)
ENABLE DIGITAL POWER TO
FUNCTIONAL SUBSYSTEMS
REGISTER 16512 (0x4080)
AND REGISTER 16513 (0x4081)
08313-025
SET UP SOUND ENGINE REGISTERS
FOR CUSTOMIZED SIGNAL PATH
(INCLUDING VOLUME, SAMPLE RATES,
FILTER COEFFICIENTS)
INITIALIZATION
COMPLETE
Figure 27. Initialization Sequence
MAIN SUPPLY ENABLED
MAIN SUPPLY DISABLED
AVDD1
1.5V
AVDD2
1.5V
DVDDOUT
1.35V
POWER-UP
(INTERNAL
SIGNAL)
0.95V
POR
ACTIVE
POR ACTIVATES
POR COMPLETE/SELF-BOOT INITIATES
SELF-BOOT COMPLETE/MEMORY
IS ACCESSIBLE
IOVDD
14ms
INPUT/OUTPUT
PINS
HIGH-Z
ACTIVE
Figure 28. Power-Up and Power-Down Sequence Timing Diagram
Rev. B | Page 25 of 84
HIGH-Z
08313-026
INTERNAL MCLK
(NOT TO SCALE)
ADAU1381
CLOCK GENERATION AND MANAGEMENT
The ADAU1381 uses a flexible clocking scheme that enables the
use of many different input clock rates. The PLL can be bypassed
or used, resulting in two different approaches to clock management. For more information about clocking schemes, PLL
configuration, and sampling rates, see the Clocking and
Sampling Rates section.
Case 1: PLL Is Bypassed
If the PLL is bypassed, the core clock is derived directly from
the master clock (MCLK) input. The rate of this clock must be
set properly in Register 16384 (0x4000), clock control, Bits[2:1],
input master clock frequency. When the PLL is bypassed,
supported external clock rates are 256 × fS, 512 × fS, 768 × fS,
and 1024 × fS, where fS is the base sampling rate. The core clock
of the chip is off until Register 16384 (0x4000), clock control,
Bit 0, core clock enable, is set to 1.
Case 2: PLL Is Used
The core clock to the entire chip is off during the PLL lock
acquisition period. The user can poll the lock bit to determine
when the PLL has locked. After lock is acquired, the ADAU1381
can be started by setting Register 16384 (0x4000), clock control,
Bit 0, core clock enable, to 1.This bit enables the core clock to all
the internal functional blocks of the ADAU1381.
PLL Lock Acquisition
During the lock acquisition period, only Register 16384 (0x4000),
clock control, and Register 16386 (0x4002), PLL control, are
accessible through the control port. Reading from or writing to
any other address is prohibited until Register 16384 (0x4000),
clock control, Bit 0, core clock enable, and Register 16386 (0x4002),
PLL control, Bit 1, PLL lock, are set to 1.
Register 16386 (0x4002), PLL control, is a 48-bit register for which
all bits must be written with a single continuous write to the
control port.
The PLL lock time is dependent on the MCLK rate. Typical lock
times are provided in Table 11.
Table 11. PLL Lock Time
PLL Mode
Fractional
Integer
Fractional
Fractional
Fractional
Fractional
Fractional
MCLK Frequency
12 MHz
12.288 MHz
13 MHz
14.4 MHz
19.2 MHz
19.68 MHz
19.8 MHz
Lock Time (Typical)
3.0 ms
2.96 ms
2.4 ms
2.4 ms
2.98 ms
2.98 ms
2.98 ms
ENABLING DIGITAL POWER TO FUNCTIONAL
SUBSYSTEMS
To power subsystems in the device, they must be enabled using
Register 16512 (0x4080), Digital Power-Down 0, and Register
16513 (0x4081), Digital Power-Down 1. The exact settings depend
on the application. However, to proceed with the initialization
sequence and access the RAMs and registers of the ADAU1381,
Register 16512 (0x4080), Digital Power-Down 0, Bit 6, memory
controller, and Bit 0, sound engine, must be enabled.
SETTING UP THE SOUND ENGINE
After the PLL has locked, the ADAU1381 is in an operational
state, and the control port can be used to configure the sound
engine. For more information, see the Sound Engine section.
POWER REDUCTION MODES
Sections of the ADAU1381 chip can be turned on and off as
needed to reduce power consumption. These include the ADCs,
the DACs, and the PLL.
In addition, some functions can be set in the registers to operate
in power saving, normal, or enhanced performance operation.
See the respective portions of the General-Purpose Input/Outputs
section for more information.
Each digital filter of the ADCs and DACs can be set to a 64× or
128× (default) oversampling ratio. Setting the oversampling ratio
to 64× lowers power consumption with a minimal impact on
performance. See the Typical Performance Characteristics section
and the Typical Power Management Measurements section for
specifications and graphs of the filters.
Detailed information regarding individual power reduction control
registers can be found in the Control Register Map section of this
document.
Power-Down Pin (PDN)
The power-down pin provides a simple hardware-based
method for initiating low power mode without requiring access
via the control port. When the PDN pin is lowered to the same
potential as ground, the internal digital regulator is disabled
and the device ceases to function, with power consumption
dropping to a very low level. The common-mode voltage sinks,
and all internal memories and registers lose their contents.
When the PDN pin is raised back to the same potential as
AVDD1, the device reinitializes in its default state, as described
in the Power-Up Sequence section.
POWER-DOWN SEQUENCE
When powering down the device, the IOVDD, AVDD1, and
AVDD2 supplies should be disabled at the same time, if possible,
but only after the analog and speaker outputs have been muted. If
the supplies cannot be disabled simultaneously, the preferred
sequence is IOVDD first, AVDD2 second, and AVDD1 last.
Rev. B | Page 26 of 84
ADAU1381
CLOCKING AND SAMPLING RATES
SOUND ENGINE
FRAME RATE
fS /
0.5, 1, 1.5, 2, 3, 4, 6
CORE
CLOCK
AUTOMATICALLY SET TO 1024 × fS
WHEN PLL CLOCK SOURCE SELECTED
CONVERTER
SAMPLING RATE
ADCs
DACs
fS /
0.5, 1, 1.5, 2, 3, 4, 6
SERIAL PORT
SAMPLING RATE
SERIAL DATA
INPUT/OUTPUT
PORTS
ADC_SDATA/GPIO1
fS /
0.5, 1, 1.5, 2, 3, 4, 6
08313-027
INPUT DIVIDE
1, 2, 3, 4
INPUT MASTER
CLOCK FREQUENCY
256 × fS, 512 × fS,
768 × fS, 1024 × fS
DAC_SDATA/GPIO0
MCKI
f × (R + N/M)
INTEGER, NUMERATOR,
DENOMINATOR
BCLK/GPIO2
f/X
CLOCK CONTROL
LRCLK/GPIO3
PLL CONTROL
SOUND
ENGINE
Figure 29. Clock Routing Diagram
CORE CLOCK
The core clock divider generates a core clock either from the
PLL or directly from MCLK and can be set in Register 16384
(0x4000), clock control.
The core clock is always in 256 × fS mode. Direct MCLK frequencies must correspond to a value listed in Table 12, where fS
is the base sampling frequency. PLL outputs are always in 1024
× fS mode, and the clock control register automatically sets the
core clock divider to f/4 when using the PLL.
For example, if the input to Bit 3 = 49.152 MHz (from PLL),
then Bits[2:1] = 1024 × fS; therefore,
fS = 49.152 MHz/1024 = 48 kHz
Table 13. Clock Control Register (Register 16384, 0x4000)
Bits
3
Bit Name
Clock source select
[2:1]
Input master clock
frequency
0
Core clock enable
Table 12. Core Clock Frequency Dividers
Input Clock Rate
256 × fS
512 × fS
768 × fS
1024 × fS
Core Clock Divider
f/1
f/2
f/3
f/4
Core Clock
256 × fS
Settings
0: direct from MCKI pin (default)
1: PLL clock
00: 256 × fS (default)
01: 512 × fS
10: 768 × fS
11: 1024 × fS
0: core clock disabled (default)
1: core clock enabled
SAMPLING RATES
Clocks for the converters, the serial ports, and the sound engine are
derived from the core clock. The core clock can be derived directly
from MCLK, or it can be generated by the PLL. Register 16384
(0x4000), clock control, Bit 3, clock source select, determines
the clock source.
Bits[2:1], input master clock frequency, should be set according
to the expected input clock rate selected by Bit 3, clock source
select. The clock source select value also determines the core
clock rate and the base sampling frequency, fS.
The ADCs, DACs, and serial port share a common sampling
rate that is set in Register 16407 (0x4017), Converter Control 0.
Bits[2:0], converter sampling rate, set the sampling rate as a ratio of
the base sampling frequency. The sound engine sampling rate is
set in Register 16619 (0x40EB), sound engine frame rate, Bits[3:0],
sound engine frame rate, and the serial port sampling rate is set
in Register 16632 (0x40F8), serial port sampling rate, Bits[2:0],
serial port control sampling rate.
It is strongly recommended that the sampling rates for the
converters, serial ports, and sound engine be set to the same
value, unless appropriate compensation filtering is done within
the sound engine.
Rev. B | Page 27 of 84
ADAU1381
Fractional Mode
Table 14 and Table 15 list the sampling rate divisions for
common base sampling rates.
Fractional mode is used when the MCLK is a fractional
(R + (N/M)) multiple of the PLL output.
Table 14. Base Sampling Rate Divisions for fS = 48 kHz
Base Sampling
Frequency
fS = 48 kHz
For example, if MCLK = 12 MHz and fS = 48 kHz, then
Sampling Rate Scaling
fS/1
fS/6
fS/4
fS/3
fS/2
fS/1.5
fS/0.5
Sampling Rate
48 kHz
8 kHz
12 kHz
16 kHz
24 kHz
32 kHz
96 kHz
Table 15. Base Sampling Rate Divisions for fS = 44.1 kHz
Base Sampling
Frequency
fS = 44.1 kHz
Sampling Rate Scaling
fS/1
fS/6
fS/4
fS/3
fS/2
fS/1.5
fS/0.5
Sampling Rate
44.1 kHz
7.35 kHz
11.025 kHz
14.7 kHz
22.05 kHz
29.4 kHz
88.2 kHz
PLL Required Output = 1024 × 48 kHz = 49.152 MHz
R + (N/M) = 49.152 MHz/12 MHz = 4 + (12/125)
Common fractional PLL parameter settings for 44.1 kHz and
48 kHz sampling rates can be found in Table 16 and Table 17.
Table 16. Fractional PLL Parameter Settings for fS = 44.1 kHz1
MCLK
Input
(MHz)
12
13
14.4
19.2
19.68
19.8
1
Input
Divider
(X)
1
1
2
2
2
2
Integer
(R)
3
3
6
4
4
4
Denominator
(M)
625
8125
125
125
1025
1375
Numerator
(N)
477
3849
34
88
604
772
Desired core clock = 11.2896 MHz, PLL output = 45.1584 MHz.
Table 17. Fractional PLL Parameter Settings for fS = 48 kHz1
PLL
The PLL uses the MCLK as a reference to generate the core
clock. PLL settings are set in Register 16386 (0x4002), PLL
control. Depending on the MCLK frequency, the PLL must be
set for either integer or fractional mode. The PLL can accept
input frequencies in the range of 11 MHz to 20 MHz.
All six bytes in the PLL control register must be written with a
single continuous write to the control port.
MCKI
÷X
× (R + N/M)
1
08313-028
TO PLL
CLOCK DIVIDER
MCLK
Input
(MHz)
12
13
14.4
19.2
19.68
19.8
Input
Divider
(X)
1
1
2
2
2
2
Integer
(R)
4
3
6
5
4
4
Denominator
(M)
125
1625
75
25
205
825
Numerator
(N)
12
1269
62
3
204
796
Desired core clock = 12.288 MHz, PLL output = 49.152 MHz.
The PLL outputs a clock in the range of 41 MHz to 54 MHz,
which should be taken into account when calculating PLL
values and MCLK frequencies.
Figure 30. PLL Block Diagram
Integer Mode
Integer mode is used when the MCLK is an integer (R) multiple
of the PLL output (1024 × fS).
For example, if MCLK = 12.288 MHz and fS = 48 kHz, then
PLL Required Output = 1024 × 48 kHz = 49.152 MHz
R = 49.152 MHz/12.288 MHz = 4
In integer mode, the values set for N and M are ignored.
Rev. B | Page 28 of 84
ADAU1381
The ADC and DAC sampling rate can be set in Register 16407
(0x4017), Converter Control 0, Bits[2:0], converter sampling
rate. The sound engine sampling rate and serial port sampling
rate are similarly set in Register 16619 (0x40EB), sound engine
frame rate, Bits[3:0], sound engine frame rate, and Register
16632 (0x40F8), serial port sampling rate, Bits[2:0], serial port
control sampling rate, respectively.
Table 18. Sampling Rates for 256 × 48 kHz Core Clock
Core Clock
12.288 MHz
Table 18 and Table 19 depict example sampling rate settings.
The (1 × 256) case is the base sampling rate.
Sampling Rate Divider
(1 × 256)
(6 × 256)
(4 × 256)
(3 × 256)
(2 × 256)
(1.5 × 256)
(0.5 × 256)
Sampling Rate
48 kHz
8 kHz
12 kHz
16 kHz
24 kHz
32 kHz
96 kHz
Table 19. Sampling Rates for 256 × 44.1 kHz Core Clock
Core Clock
11.2896 MHz
Rev. B | Page 29 of 84
Sampling Rate Divider
(1 × 256)
(6 × 256)
(4 × 256)
(3 × 256)
(2 × 256)
(1.5 × 256)
(0.5 × 256)
Sampling Rate
44.1 kHz
7.35 kHz
11.025 kHz
14.7 kHz
22.05 kHz
29.4 kHz
88.2 kHz
ADAU1381
RECORD SIGNAL PATH
Analog Beep Input
BEEP
PGA
The BEEP pin is used for mono single-ended signals, such as a
beep warning. This signal bypasses the ADCs and the sound
engine and is mixed directly into any of the analog outputs.
LMIC/LMICN/
MICD1
PGA
LMICP
A BEEP pin input can also be amplified or muted by a PGA, up
to 32 dB in Register 16392 (0x4008), digital microphone and analog
beep control. The beep input must be enabled in Register 16400
(0x4010), microphone bias control and beep enable.
LEFT
ADC
DECIMATORS
CM
RMIC/RMICN/
MICD2
Microphone Bias
The MICBIAS pin provides a voltage reference for electret
microphones. Register 16400 (0x4010), microphone bias
control and beep enable, sets the operation mode of this pin.
RIGHT
ADC
CM
08313-029
PGA
RMICP
Example Configurations
Figure 31. Record Signal Path Diagram
TO DECIMATORS
LMIC/LMICN/
MICD1
The ADAU1381 can be configured for three types of microphone
inputs: single-ended, differential, or digital. The LMIC/LMICN/
MICD1 and RMIC/RMICN/MICD2 pins encompass all of these
configurations. LMICP and RMICP are used only during
differential configurations (see Figure 31, the record signal path
diagram).
Each analog input has individual gain controls (boost or cut). These
signals are routed to their respective right or left channel ADC.
PGA
LMICP
CM
TO DECIMATORS
RMIC/RMICN/
MICD2
PGA
RMICP
08313-030
INPUT SIGNAL PATH
CM
Analog Microphone Inputs
For differential inputs, RMICN and RMICP denote the negative
and positive input for the right channel, respectively. LMICN
and LMICP denote the negative and positive input for the left
channel, respectively.
Figure 32. Stereo Digital Microphone Input Configuration
LMIC/LMICN/
MICD1
PGA
LMICP
LMIC and RMIC inputs are single-ended line inputs. Together,
they can be used as a stereo single-ended input.
TO LEFT
ADC
CM
RMIC/RMICN/
MICD2
When a digital PDM microphone connected to the MICD1 or
MICD2 pin is used, Register 16392 (0x4008), digital microphone
and analog beep control, must be set appropriately to enable the
microphone input of choice. The MCKO output clock provides
the clock for the microphone and must be set accordingly in
Register 16384 (0x4000), clock control, depending on the
streaming PDM rate of the microphone.
The digital microphone signal bypasses the ADCs and is routed
directly into the decimation filters. The digital microphone and
ADCs share these decimation filters; therefore, both cannot be
used simultaneously.
Rev. B | Page 30 of 84
PGA
RMICP
TO RIGHT
ADC
CM
Figure 33. Single-Ended Input Configuration
08313-031
Digital Microphone Inputs
ADAU1381
Digital ADC Volume Control
LMIC/LMICN/
MICD1
PGA
LMICP
The ADC output (digital input) volume can be adjusted in
Register 16410 (0x401A), left ADC attenuator, Bits[7:0], left ADC
digital attenuator, for the left channel digital volume control and
in Register 16411 (0x401B), right ADC attenuator, Bits[7:0], right
ADC digital attenuator, for right channel digital volume control.
TO LEFT
ADC
CM
RMIC/RMICN/
MICD2
High-Pass Filter
CM
A high-pass filter is used in the ADC path to remove dc offsets
and can be selected in Register 16409 (0x4019), ADC control,
Bit 5, high-pass filter select, where it can be enabled or disabled.
08313-032
PGA
RMICP
TO RIGHT
ADC
Figure 34. Differential Input Configuration
DIGITAL DUAL-BAND AUTOMATIC LEVEL
CONTROL (ALC)
ANALOG-TO-DIGITAL CONVERTERS
The ADAU1381 uses two 24-bit Σ-Δ analog-to-digital converters
(ADCs) with selectable oversampling rates of either 64× or 128×.
The full-scale input to the ADCs depends on AVDD1. At 3.3 V,
the full-scale input level is 1.0 V rms. Inputs greater than the
full-scale value result in clipping and distortion.
The ADAU1381 includes an automatic level control (ALC). The
ALC adjusts the input gain continuously for a varying input signal
as dictated by the user-defined ALC settings. This allows the input
recording level to remain constant. Although this functionality
relates mainly to the record signal path, it is implemented digitally
in the sound engine.
Rev. B | Page 31 of 84
ADAU1381
PLAYBACK SIGNAL PATH
LEFT PLAYBACK
MIXER
beep signal. The mixer can be controlled in Register 16415
(0x401F), playback mono mixer control.
LINE OUT
AMPLIFIER
LEFT
DAC
AOUTL
LEFT
PLAYBACK
BEEP GAIN
MONO
PLAYBACK
BEEP GAIN
BEEP FROM
RECORD PGA
The drivers are low noise, Class AB mono amplifiers designed to
drive 8 Ω, 400 mW speakers. The output is differential and does
not require external capacitors. The gain settings for the speaker
drivers can be set in Register 16423 (0x4027), playback speaker
output control. In this register, the drivers can be set for any of
the four gain settings: 0 dB, 2 dB, 4 dB, or 6 dB. Additionally,
the speaker driver can be muted or powered down completely.
MONO
OUTPUT
GAIN
MONO
PLAYBACK
MIXER
SPP
RIGHT
PLAYBACK
BEEP GAIN
–1
SPN
MONO OUTPUT
INVERTER
RIGHT
DAC
08313-033
AOUTR
RIGHT PLAYBACK LINE OUT
MIXER
AMPLIFIER
Figure 35. Playback Signal Path Diagram
OUTPUT SIGNAL PATHS
The outputs of the ADAU1381 include a left and right line output
and speaker driver. The beep input signal can be mixed into any
of these outputs, with separate gain control for each path.
DIGITAL-TO-ANALOG CONVERTERS
The ADAU1381 uses two 24-bit Σ-Δ digital-to-analog converters
(DACs) with selectable oversampling rates of 64× or 128×. The
full-scale output of the DACs depends on AVDD1. At 3.3 V, the
full-scale output level is 1.0 V rms.
For pop and click suppression, an internal precharge sequence with
output gating/enabling occurs after the mono driver is enabled.
The sequence lasts for 8 ms, and then the internal mute signal
rising edge occurs (see Figure 36 for the power-up sequence
timing diagram).
The power-down sequence is essentially the reverse of the startup sequence, as depicted in Figure 37.
SPEAKER
OUTPUT
ENABLE
MONO
OUTPUT
MUTE
4ms
SPP
HIGH-Z
SPN
HIGH-Z
4ms
VCM
VCM
Digital DAC Volume Control
A de-emphasis filter is used in the DAC path to remove high
frequency noise in an FM system. This filter can be enabled or
disabled in Register 16426 (0x402A), DAC control.
<1µA
1.1mA
2.3mA + SIGNAL
CURRENT
2.3mA
DAC
DAC VOLUME MUTED
DAC VOLUME
INCREASES
BEEP
BEEP VOLUME MUTED
BEEP VOLUME
INCREASES
Figure 36. Speaker Driver Power-Up Sequence
SPEAKER
OUTPUT
ENABLE
4ms
MONO
OUTPUT
MUTE
LINE OUTPUTS
The AOUTL and AOUTR pins are the left and right line outputs,
respectively. Both outputs have a line output amplifier that can
be set in the control registers.
VCM
SPP
IAVDD2
Similarly, the right playback mixer mixes the right DAC and the
beep input and is dedicated to the AOUTR output.
2.3mA + SIGNAL
CURRENT
4ms
HIGH-Z
VCM
SPN
The left playback mixer is dedicated to the AOUTL output. This
mixer mixes the left DAC and the beep signal.
HIGH-Z
2.3mA
1.1mA
<1µA
DAC
DAC VOLUME
DECREASES
DAC VOLUME MUTED
BEEP
BEEP VOLUME
DECREASES
BEEP VOLUME MUTED
SPEAKER OUTPUT
The SPP and SPN pins are the positive and negative speaker
outputs, respectively. Each output has a speaker driver.
08313-034
De-Emphasis Filter
IAVDD2
Figure 37. Speaker Driver Power-Down Sequence
The speaker outputs are derived from the mono playback mixer,
which sums the right and left DAC outputs and mixes with the
Rev. B | Page 32 of 84
08313-035
The DAC output (digital output) volume can be adjusted in
Register 16427 (0x402B), left DAC attenuator, for the left channel
digital volume control and in Register 16428 (0x402C), right
DAC attenuator, for the right channel digital volume control.
ADAU1381
CONTROL PORTS
The ADAU1381 can operate in one of two control modes: I2C
control or SPI control.
The ADAU1381 has both a 4-wire SPI control port and a 2-wire
I2C bus control port. Each can be used to set the registers. The
part defaults to I2C mode but can be put into SPI control mode
by pulling the CLATCH pin low three times.
The control port is capable of full read/write operation for all
addressable registers. Most sound engine processing parameters
are controlled by writing new values to the sound engine parameter
register using the control port. Other functions, such as mute,
input/output mode control, and analog signal paths, can be
programmed by writing to the appropriate registers.
All addresses can be accessed in either a single-address mode or
a burst mode. The first byte (Byte 0) of a control port write contains
the 7-bit chip address plus the R/W bit. The next two bytes (Byte 1
and Byte 2) together form the subaddress of the register location
within the ADAU1381. All subsequent bytes (starting with Byte 3)
contain the data, such as control port data, register data, or sound
engine parameter data. The number of bytes per word depends
on the type of data that is being written. The exact formats for
specific types of writes and reads are shown in Figure 40 to
Figure 43.
The ADAU1381 has several mechanisms for updating sound
engine parameters in real time without causing pops or clicks.
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 20 details these
multiple functions.
Burst mode addressing, where the subaddresses are automatically incremented at word boundaries, can be used for writing
large amounts of data to contiguous memory locations. This
increment happens automatically after a single-word write unless a
stop condition is encountered. The registers in the ADAU1381
range in width from one to six bytes; therefore, the auto-increment
feature knows the mapping between subaddresses and the word
length of the destination register. A data transfer is always
terminated by a stop condition.
Both SDA and SCL should have 2.0 kΩ pull-up resistors on the
lines connected to them. The voltage on these signal lines should
not be more than AVDD1.
Table 21. I2C Address Byte Format
Bit 0
0
Bit 1
1
Bit 2
1
Bit 3
1
Bit 4
0
Bit 5
ADDR1
Bit 6
ADDR0
Bit 7
R/W
Table 22. I2C Addresses
ADDR1
0
0
0
0
1
1
1
1
ADDR0
0
0
1
1
0
0
1
1
R/W
0
1
0
1
0
1
0
1
Slave Address
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
Addressing
Table 20. Control Port Pin Functions
Pin
SCL/CCLK
SDA/COUT
ADDR1/CLATCH
ADDR0/CDATA
I2C Mode
SCL—input
SDA—open-collector output
I2C Address Bit 1—input
I2C Address Bit 0—input
SPI Mode
CCLK—input
COUT—output
CLATCH—input
CDATA—input
I2C PORT
The ADAU1381 supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the ADAU1381 and the system I2C master controller.
In I2C mode, the ADAU1381 is always a slave on the bus, meaning
it cannot initiate a data transfer. Each slave device is recognized by
a unique address. The address byte format is shown in Table 21.
The address resides in the first seven bits of the I2C write. The
LSB of this byte sets either a read or write operation. Logic 1
corresponds to a read operation, and Logic 0 corresponds to a
write operation. The full byte addresses, including the pin settings
and R/W bit, are shown in Table 22.
Initially, each device on the I2C bus is in an idle state and
monitoring the SDA and SCL lines for a start condition and
the proper address. The I2C master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address or
an address and data stream follow. All devices on the bus respond
to the start condition and shift the next eight bits (the 7-bit
address plus the R/W bit), MSB first. The device that recognizes
the transmitted address responds by pulling the data line low
during the ninth clock pulse. This ninth bit is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and return to the idle condition.
The R/W bit determines the direction of the data. A Logic 0 on the
LSB of the first byte means the master writes information to the
peripheral, whereas a Logic 1 means the master reads information
from the peripheral after writing the subaddress and repeating
the start address. A data transfer takes place until a stop condition
is encountered. A stop condition occurs when SDA transitions
from low to high while SCL is held high. Figure 38 shows the
timing of an I2C write, and Figure 39 shows an I2C read.
Rev. B | Page 33 of 84
ADAU1381
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, the ADAU1381
immediately jumps to the idle condition. During a given SCL
high period, the user should issue only one start condition, one
stop condition, or a single stop condition followed by a single
start condition. If an invalid subaddress is issued by the user,
the ADAU1381 does not issue an acknowledge and returns to
the idle condition. If the user exceeds the highest subaddress while
in auto-increment mode, one of two actions is taken. In read mode,
the ADAU1381 outputs the highest subaddress register contents
until the master device issues a no acknowledge, indicating the
end of a read. A no-acknowledge condition is where the SDA
line is not pulled low on the ninth clock pulse on SCL. If the
highest subaddress location is reached while in write mode, the
data for the invalid byte is not loaded into any subaddress register,
a no acknowledge is issued by the ADAU1381, and the part returns
to the idle condition.
SCL
SDA
1
0
1
1
0
ADDR1 ADDR0 R/W
ACKNOWLEDGE
BY ADAU1381
START BY
MASTER
ACKNOWLEDGE
BY ADAU1381
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE 1
SCL
(CONTINUED)
SDA
(CONTINUED)
ACKNOWLEDGE STOP BY
BY ADAU1381 MASTER
08313-036
ACKNOWLEDGE
BY ADAU1381
FRAME 4
DATA BYTE 1
FRAME 3
SUBADDRESS BYTE 2
Figure 38. I2C Write to ADAU1381 Clocking
SCL
SDA
0
1
1
1
0
ADDR1
START BY
MASTER
ADDR0
R/W
ACKNOWLEDGE
BY ADAU1381
ACKNOWLEDGE
BY ADAU1381
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE 1
SCL
(CONTINUED)
SDA
(CONTINUED)
0
ACKNOWLEDGE
BY ADAU1381
1
1
1
0
ADDR1
REPEATED
START BY MASTER
FRAME 3
SUBADDRESS BYTE 2
ADDR0
R/W
ACKNOWLEDGE
BY ADAU1381
FRAME 4
CHIP ADDRESS BYTE
SCL
(CONTINUED)
ACKNOWLEDGE
BY ADAU1381
FRAME 5
READ DATA BYTE 1
ACKNOWLEDGE
BY MASTER
FRAME 6
READ DATA BYTE 2
Figure 39. I2C Read from ADAU1381 Clocking
Rev. B | Page 34 of 84
STOP BY
MASTER
08313-037
SDA
(CONTINUED)
ADAU1381
I2C Read and Write Operations
of the subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/W bit set to 1 (read).
This causes the ADAU1381 SDA to reverse and begin driving
data back to the master. The master then responds every ninth
pulse with an acknowledge pulse to the ADAU1381.
Figure 40 shows the timing of a single-word write operation.
Every ninth clock pulse, the ADAU1381 issues an acknowledge
by pulling SDA low.
Figure 41 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The ADAU1381 knows to increment its
subaddress register every two bytes because the requested
subaddress corresponds to a register or memory area with a
2-byte word length.
Figure 43 shows the timing of a burst mode read sequence. This
figure shows an example where the target read registers are two
bytes. The ADAU1381 increments its subaddress every two bytes
because the requested subaddress corresponds to a register or
memory area with word lengths of two bytes. Other address
ranges may have a variety of word lengths ranging from one to
five bytes. The ADAU1381 always decodes the subaddress and
sets the auto-increment circuit so that the address increments
after the appropriate number of bytes.
The timing of a single-word read operation is shown in Figure 42.
Note that the first R/W bit is 0, indicating a write operation. This is
because the subaddress still needs to be written to set up the
internal address. After the ADAU1381 acknowledges the receipt
CHIP ADDRESS,
R/W = 0
AS
SUBADDRESS,
HIGH BYTE
AS
SUBADDRESS,
LOW BYTE
DATA
BYTE 1
AS
DATA
BYTE 2
AS
AS
...
DATA
BYTE N
AS
P
08313-038
S
S = START BIT, P = STOP BIT, AS = ACKNOWLEDGE BY SLAVE.
SHOWS A ONE-WORD WRITE, WHERE EACH WORD HAS N BYTES.
Figure 40. Single-Word I2C Write Sequence
CHIP
ADDRESS,
R/W = 0
AS
SUBADDRESS,
HIGH BYTE
AS
SUBADDRESS,
LOW BYTE
AS
AS
AS
AS
AS
...
DATA-WORD 1, DATA-WORD 1, DATA-WORD 2, DATA-WORD 2,
BYTE 1
BYTE 2
BYTE 1
BYTE 2
AS
AS
P
DATA-WORD N, DATA-WORD N,
BYTE 1
BYTE 2
S = START BIT, P = STOP BIT, AS = ACKNOWLEDGE BY SLAVE.
SHOWS AN N-WORD WRITE, WHERE EACH WORD HAS TWO BYTES. (OTHER WORD LENGTHS ARE POSSIBLE, RANGING FROM ONE TO FIVE BYTES.)
08313-039
S
Figure 41. Burst Mode I2C Write Sequence
CHIP ADDRESS,
R/W = 0
AS
SUBADDRESS,
HIGH BYTE
AS
SUBADDRESS,
LOW BYTE
AS
S
CHIP ADDRESS,
R/W = 1
AS
DATA
BYTE 1
AM
DATA
BYTE 2
AM
DATA
BYTE N
...
AM
P
AM
P
08313-040
S
S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE.
SHOWS A ONE-WORD READ, WHERE EACH WORD HAS N BYTES.
Figure 42. Single-Word I2C Read Sequence
CHIP
ADDRESS,
R/W = 0
AS
SUBADDRESS,
HIGH BYTE
AS
SUBADDRESS,
LOW BYTE
AS
S
CHIP
ADDRESS,
R/W = 1
AS
AM
DATA-WORD 1,
BYTE 1
AM
DATA-WORD 1,
BYTE 2
...
AM
DATA-WORD N, DATA-WORD N,
BYTE 1
BYTE 2
S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE.
SHOWS AN N-WORD READ, WHERE EACH WORD HAS TWO BYTES. (OTHER WORD LENGTHS ARE POSSIBLE, RANGING FROM ONE TO FIVE BYTES.)
Figure 43. Burst Mode I2C Read Sequence
Rev. B | Page 35 of 84
08313-041
S
ADAU1381
SPI PORT
Data Bytes
By default, the ADAU1381 is in I2C mode, but can be put into SPI
control mode by pulling CLATCH low three times. The SPI port
uses a 4-wire interface, consisting of CLATCH, CCLK, CDATA,
and COUT signals, and is always a slave port. The CLATCH signal
goes low at the beginning of a transaction and high at the end of
a transaction. The CCLK signal latches CDATA on a low-to-high
transition. COUT data is shifted out of the ADAU1381 on the
falling edge of CCLK and should be clocked into a receiving
device, such as a microcontroller, on the CCLK rising edge. The
CDATA signal carries the serial input data, and the COUT signal is
the serial output data. The COUT signal remains three-stated until
a read operation is requested. This allows other SPI-compatible
peripherals to share the same readback line. All SPI transactions
have the same basic format shown in Table 24. A timing diagram
is shown in Figure 4. All data should be written MSB first. The
ADAU1381 can be taken out of SPI mode only by a full reset.
The number of data bytes varies according to the register being
accessed. During a burst mode write, an initial subaddress is
written followed by a continuous sequence of data for consecutive
register locations. A sample timing diagram for a single-write
SPI operation to the parameter memory is shown in Figure 44.
A sample timing diagram of a single-read SPI operation is shown in
Figure 45. The COUT pin goes from three-state to being driven at
the beginning of Byte 3. In this example, Byte 0 to Byte 2 contain
the addresses and R/W bit, and subsequent bytes carry the data.
SPI Read/Write Clock Frequency (CCLK)
The SPI port of the ADAU1381 has asymmetrical read and
write clock frequencies. It is possible to write data into the
device at higher data rates than reading data out of the device.
More detailed information is available in the Digital Timing
Specifications section.
MEMORY AND REGISTER ACCESS
Chip Address R/W
The first byte of an SPI transaction includes the 7-bit chip address
and an R/W bit. The chip address is always 0x38. The LSB of
this first byte determines whether the SPI transaction is a read
(Logic 1) or a write (Logic 0).
Several conditions must be true to have full access to all memory
and registers via the control port:
•
•
Table 23. SPI Address Byte Format
Bit 0
0
Bit 1
0
Bit 2
0
Bit 3
0
Bit 4
0
Bit 5
0
Bit 6
0
Bit 7
R/W
•
•
Subaddress
The 12-bit subaddress word is decoded into a location in one of
the registers. This subaddress is the location of the appropriate
register. The MSBs of the subaddress are zero-padded to bring the
word to a full 2-byte length.
The ADAU1381 must have finished its initialization,
including power-on reset, PLL lock, and self-boot.
The core clock must be enabled (Register 16384 (0x4000),
clock control, Bit 0, core clock enable, set to 1).
The memory controller must be powered (Register 16512
(0x4080), Digital Power-Down 0, Bit 6, memory controller, set
to 1).
The sound engine must be powered (Register 16512 (0x4080),
Digital Power-Down 0, Bit 0, sound engine, set to 1).
Table 24. Generic Control Word Format
Byte 0
CHIP_ADR[6:0], R/W
1
Byte 1
SUBADR[15:8]
Byte 2
SUBADR[7:0]
Continues to end of data.
Rev. B | Page 36 of 84
Byte 3
Data
Byte 4 1
Data
ADAU1381
CLATCH
CDATA
BYTE 0
BYTE 1
BYTE 2
08313-042
CCLK
BYTE 3
Figure 44. SPI Write to ADAU1381 Clocking (Single-Write Mode)
CLATCH
CCLK
COUT
BYTE 1
BYTE 0
BYTE 3
HIGH-Z
DATA
Figure 45. SPI Read from ADAU1381 Clocking (Single-Read Mode)
Rev. B | Page 37 of 84
DATA
HIGH-Z
08313-043
CDATA
ADAU1381
SERIAL DATA INPUT/OUTPUT PORTS
The flexible serial data input and output ports of the ADAU1381
can be set to accept or transmit data in 2-channel format or in a
4-channel or 8-channel TDM stream to interface to external ADCs
or DACs. Data is processed by default in twos complement, MSB
first format, unless otherwise configured in the control registers.
By default, the left channel data field precedes the right channel
data field in 2-channel streams. In TDM 4 mode, Slot 0 and Slot 1
are in the first half of the audio frame, and Slot 2 and Slot 3 are
in the second half of the audio frame. In TDM 8 mode, Slot 0 to
Slot 3 are in the first half of the audio frame, and Slot 4 to Slot 7
are in the second half of the frame. The serial modes and the
position of the data in the frame are set in Register 16405 (0x4015),
Serial Port Control 0; Register 16406 (0x4016), Serial Port Control 1;
Register 16407 (0x4017), Converter Control 0; and Register 16408
(0x4018), Converter Control 1.
TDM MODES
The serial data clocks must be synchronous with the ADAU1381
master clock input. The LRCLK and BCLK pins are used to clock
both the serial input and output ports. The ADAU1381 can be
set as the master or the slave in a system. Because there is only
one set of serial data clocks, the input and output ports must
always be both master or both slave.
The ADAU1381 TDM implementation is a TDM audio stream.
Unlike a true TDM bus, its output does not become high impedance during periods when it is not transmitting data.
Register 16405 (0x4015), Serial Port Control 0, and Register
16406 (0x4016), Serial Port Control 1, allow control of clock
polarity and data input modes. The valid data formats are I2S,
left-justified, right-justified (24-/20-/18-/16-bit), and TDM. In
all modes except for the right-justified modes, the serial port
inputs an arbitrary number of audio data bits, up to a limit of 24.
Extra bits do not cause an error, but they are truncated internally.
The serial port can operate with an arbitrary number of BCLK
transitions in each LRCLK frame.
The LRCLK in TDM mode can be input to the ADAU1381
either as a 50% duty cycle clock or as a bit-wide pulse.
When the LRCLK is set as a pulse, a 47 pF capacitor should be
connected between the LRCLK pin and ground, as shown in
Figure 46. This is necessary in both master and slave modes to
properly align the LRCLK signal to the serial data stream.
ADAU1381
LRCLK
08313-044
47pF
BCLK
Figure 46. TDM Pulse Mode LRCLK Capacitor Alignment
In TDM 8 mode, the ADAU1381 can be a master for fS up to
48 kHz. Table 25 lists the modes in which the serial output port
can function.
Table 25. Serial Output Port Master/Slave Mode Capabilities
fS
48 kHz
96 kHz
2-Channel Modes (I2S, LeftJustified, Right-Justified)
Master and slave
Master and slave
8-Channel TDM
Master and slave
Slave
Table 26 describes the proper configurations for standard audio
data formats. Right-justified modes must be configured manually
using Register 16406 (0x4016), Serial Port Control 1, Bits[7:5],
number of bit clock cycles per frame, and Bits[1:0], data delay
from LRCLK edge.
Table 26. Data Format Configurations
Format
I2S (see Figure 47)
LRCLK Polarity
Frame begins on falling edge
LRCLK Mode
50% duty cycle
Left-Justified
(see Figure 48)
Right-Justified
(see Figure 49)
Frame begins on rising edge
50% duty cycle
Frame begins on rising edge
50% duty cycle
Frame begins on falling edge
50% duty cycle
Frame begins on rising edge
Pulse
TDM with Clock
(see Figure 50)
TDM with Pulse
(see Figure 51)
BCLK Polarity
Data changes
on falling edge
Data changes
on falling edge
Data changes
on falling edge
Data changes
on falling edge
Data changes
on falling edge
Rev. B | Page 38 of 84
BCLK Cycles/
Audio Frame
64
64
64
64 to 256
64 to 256
Data Delay from
LRCLK Edge
Delayed from LRCLK edge
by 1 BCLK
Aligned with LRCLK edge
Delayed from LRCLK edge
by 8, 12, or 16 BCLKs to
align LSB with right edge
of frame.
Delayed from start of word
clock by 1 BCLK
Delayed from start of word
clock by 1 BCLK
ADAU1381
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
LSB
MSB
LSB
MSB
08313-045
SDATA
1/fS
2
Figure 47. I S Mode—16 Bits to 24 Bits per Channel
MSB
LSB
MSB
LSB
08313-046
SDATA
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
BCLK
1/fS
Figure 48. Left-Justified Mode—16 Bits to 24 Bits per Channel
RIGHT CHANNEL
SDATA
MSB
LSB
MSB
LSB
08313-047
LEFT CHANNEL
LRCLK
BCLK
1/fS
Figure 49. Right-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
256 BCLKs
BCLK
32 BCLKs
DATA
SLOT 1
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SLOT 6
SLOT 7
SLOT 8
LRCLK
MSB
MSB – 1
MSB – 2
08313-048
BCLK
DATA
Figure 50. TDM Mode
LRCLK
BCLK
MSB TDM
MSB TDM
CH
0
8TH
CH
SLOT 0
SLOT 1
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SLOT 6
SLOT 7
08313-049
SDATA
32
BCLKs
Figure 51. TDM Mode with Pulse Word Clock
Rev. B | Page 39 of 84
ADAU1381
GENERAL-PURPOSE INPUT/OUTPUTS
The serial data input/output pins are shared with the generalpurpose input/output function. Each of these four pins can be
set to only one function. The function of these pins is set in
Register 16628 (0x40F4), serial data/GPIO pin configuration.
The GPIO pins can be used as either inputs or outputs. These pins
are readable and can be set either through the control interface
or directly by the sound engine. When set as inputs, these pins
can be used with push-button switches or rotary encoders to
control sound engine program settings. Digital outputs can be
used to drive LEDs or external logic to indicate the status of
internal signals and control other devices. Examples of this use
include indicating signal overload, signal present, and button
press confirmation.
When set as an output, each pin can typically drive 2 mA. This
is enough current to directly drive some high efficiency LEDs.
Standard LEDs require about 20 mA of current and can be driven
from a GPIO output with an external transistor or buffer. Because
of issues that may arise from simultaneously driving or sinking a
large current on many pins, care should be taken in the application
design to avoid connecting high efficiency LEDs directly to many
or all of the GPIO pins. If many LEDs are required, use an external
driver. When the GPIO pins are set as open-collector outputs,
they should be pulled up to a maximum voltage of what is set
on IOVDD.
The configuration of the GPIO functions is set up in Register 16582
to Register 16586 (0x40C6 to 0x40CA), GPIO pin control.
GPIOs Set from Control Port
The GPIO pins can also be set to be directly controlled from the
I2C/SPI control port. When the pins are set into this mode, five
memory locations are enabled for the GPIO pin settings (see
Table 69). The physical settings on the GPIO pins mirror the
settings of the LSB of these 4-byte-wide memory locations.
Rev. B | Page 40 of 84
ADAU1381
SOUND ENGINE
SIGNAL PROCESSING
The ADAU1381 is designed to provide a fixed-function signal
processing flow specifically catered to digital still cameras and other
low power applications.
PROCESSING FLOW
SigmaStudio is also capable of one-click generation of C-compatible
data and header files, which can then be integrated directly into
a system’s host processor.
PARAMETER MEMORY
The processing flow is outlined in Figure 52.
PROGRAMMING
Although the sound engine’s audio processing flow is fixedfunction, processing parameters and signal paths can be
modified by the user.
Real-time tuning and parameter generation is made possible by
SigmaStudio™, a graphical user interface that can communicate
with the ADAU1381 control port via the EVAL-ADUSB2EBZ
LINE INPUT
communications interface board (see the AD1940 product page
for ordering information).
The sound engine makes use of a parameter memory to store
signal processing parameter values, such as filter coefficients.
This memory space is mapped to addresses starting at 0x0000
and is accessible via the control port. The parameter memory
allows the user to modify signal processing parameters in real
time during operation of the sound engine.
ADC
MONO
DAC
MIX
ADC
DIGITAL MIC
BEEP
LINE OUTPUT
STEREO
ADAU1381 SOUND ENGINE
RECORD
STEREO
RECORD
WIND
NOISE
REDUCTION
DIGITAL STEREO
INPUT
ENHANCED
STEREO
CAPTURE
ROUTING
DUAL-BAND
SIX-BAND
LOGIC
DYNAMIC
ROUTING
DUAL-BAND
EQUALIZER
PROCESSOR
SIX
BAND
LOGIC
DYNAMIC
ROUTING
DUAL-BAND
EQUALIZER
SIX
BAND
PROCESSOR
LOGIC
DYNAMIC
EQUALIZER
PROCESSOR
DIGITAL
OUTPUT
MUTE
MUTE
PLAYBACK
STEREO
PLAYBACK
ROUTING
LOGIC
FLAG
Figure 52. Sound Engine Signal Processing Flow
Rev. B | Page 41 of 84
08313-050
STEREO
ADAU1381
APPLICATIONS INFORMATION
POWER SUPPLY BYPASS CAPACITORS
GROUNDING
Each analog and digital power supply pin should be bypassed to
its nearest appropriate ground pin with a single 100 nF capacitor.
The connections to each side of the capacitor should be as short
as possible, and the trace should stay on a single layer with no
vias. For maximum effectiveness, locate the capacitor equidistant
from the power and ground pins or, when equidistant placement
is not possible, slightly closer to the power pin. Thermal connections to the ground planes should be made on the far side of the
capacitor.
A single ground plane should be used in the application layout.
Components in an analog signal path should be placed away
from digital signals.
Each supply signal on the board should also be bypassed with a
single bulk capacitor (10 μF to 47 μF).
The ADAU1381 LFCSP package has an exposed pad on the
underside. This pad is used to couple the package to the PCB
for heat dissipation when using the outputs to drive earpiece or
headphone loads. When designing a board for the ADAU1381,
special consideration should be given to the following:
VDD
GND
SPEAKER DRIVER SUPPLY TRACE (AVDD2)
The trace supplying power to the AVDD2 pin has higher current
requirements than the AVDD1 pin (up to 300 mA). An appropriately thick trace is recommended.
EXPOSED PAD PCB DESIGN
•
CAPACITOR
TO VDD
TO GND
08313-051
•
Figure 53. Recommended Power Supply Bypass Capacitor Layout
A copper layer equal in size to the exposed pad should be
on all layers of the board, from top to bottom, and should
connect somewhere to a dedicated copper board layer (see
Figure 55).
Vias should be placed to connect all layers of copper,
allowing for efficient heat and energy conductivity. For an
example, see Figure 56, which has nine vias arranged in a
3 inch × 3 inch grid in the pad area.
In mobile applications, excessive 217 Hz GSM noise on the
analog supply pins can degrade the quality of the audio signal.
To avoid this problem, it is recommended that an LC filter be
used in series with the bypass capacitors for the AVDD pins.
This filter should consist of a 1.2 nH inductor and a 9.1 pF
capacitor in series between AVDDx and ground, as shown in
Figure 54.
TOP
GROUND
POWER
BOTTOM
VIAS
COPPER SQUARES
Figure 55. Exposed Pad Layout Example, Side View
10µF
+
0.1µF
0.1µF
AVDD2
08313-054
AVDD1
08313-052
1.2nH 9.1pF
Figure 54. GSM Filter on the Analog Supply Pins
Figure 56. Exposed Pad Layout Example, Top View
Rev. B | Page 42 of 84
08313-053
GSM NOISE FILTER
ADAU1381
CONTROL REGISTER MAP
All registers except the PLL control register are 1-byte write and read registers.
Table 27.
Hex
0x4000
0x4001
0x4002
0x4008
0x4009
0x400E
0x400F
0x4010
0x4015
0x4016
0x4017
0x4018
0x4019
0x401A
0x401B
0x401C
0x401E
0x401F
0x4020
0x4025
0x4026
0x4027
0x4028
0x4029
0x402A
0x402B
0x402C
0x402D
0x402E
0x402F
0x4030
0x4031
0x4032
0x4080
0x4081
0x40C6 to 0x40CA
0x03E8 to 0x03EC
0x40E9 to 0x40EA
0x40EB
0x40F2
0x40F3
0x40F4
0x40F6
0x40F8
Address
Decimal
16384
16385
16386
16392
16393
16398
16399
16400
16405
16406
16407
16408
16409
16410
16411
16412
16414
16415
16416
16421
16422
16423
16424
16425
16426
16427
16428
16429
16430
16431
16432
16433
16434
16512
16513
16582 to 16586
1000 to 1004
16617 to 16618
16619
16626
16627
16628
16630
16632
Name
Clock control
Regulator control
PLL control (48-bit register)
Digital microphone and analog beep control
Record power management
Record gain left PGA
Record gain right PGA
Microphone bias control and beep enable
Serial Port Control 0
Serial Port Control 1
Converter Control 0
Converter Control 1
ADC control
Left ADC attenuator
Right ADC attenuator
Playback mixer left control
Playback mixer right control
Playback mono mixer control
Playback clamp amplifier control
Left line output mute
Right line output mute
Playback speaker output control
Beep zero-crossing detector control
Playback power management
DAC control
Left DAC attenuator
Right DAC attenuator
Serial Port Pad Control 0
Serial Port Pad Control 1
Communication Port Pad Control 0
Communication Port Pad Control 1
MCKO control
Dejitter control
Digital Power-Down 0
Digital Power-Down 1
GPIO pin control
GPIO pin value registers
Nonmodulo registers
Sound engine frame rate
Serial input route control
Serial output route control
Serial data/GPIO pin configuration
Sound engine run
Serial port sampling rate
Rev. B | Page 43 of 84
ADAU1381
CLOCK MANAGEMENT, INTERNAL REGULATOR,
AND PLL CONTROL
Register 16384 (0x4000), Clock Control
The clock control register sets the clocking scheme for the
ADAU1381. The system clock can be generated from either the
PLL or directly from the MCKI (master clock input) pin. Additionally, the MCKO (master clock output) pin can be configured.
Bits[6:5], MCKO Frequency
These bits set the frequency to be output on MCKO as a multiple
of the base sampling frequency (32×, 64×, 128×, or 256×). The
MCKO pin can be used to provide digital microphones with a clock.
Bit 4, MCKO Enable
the PLL is always 1024 × fS, and Bits[2:1] should be set to 11.
PLL parameters can be set in the PLL control register. Inputs
directly from MCKI require an exact clock rate as described in
the Bits[2:1], Input Master Clock Frequency section.
Bits[2:1], Input Master Clock Frequency
The maximum clock speed allowed is 1024 × 48 kHz. These bits set
the expected input master clock frequency for proper clock divider
values in order to output a constant system clock of 256 × fS. When
using the PLL, these bits must always be set to 1024 × fS. When
bypassing the PLL, the external clock frequency on the MCKI pin
must be 256 × fS, 512 × fS, 768 × fS, or 1024 × fS. Table 29 and
Table 30 show the relationship between the system clock and the
internal master clock for base sampling frequencies of 44.1 kHz
and 48 kHz.
This bit enables or disables the MCKO pin.
Bit 0, Core Clock Enable
Bit 3, Clock Source Select
This bit enables the internal master clock to start the IC.
The clock source select bit either routes the MCLK input through
the PLL or bypasses the PLL. When using the PLL, the output of
Table 28. Clock Control Register
Bits
7
[6:5]
4
3
[2:1]
0
Description
Reserved
MCKO frequency
00: 32 × fS
01: 64 × fS
10: 128 × fS
11: 256 × fS
MCKO enable
0: disabled
1: enabled
Clock source select
0: direct from MCKI pin
1: PLL clock
Input master clock frequency
00: 256 × fS
01: 512 × fS
10: 768 × fS
11: 1024 × fS
Core clock enable
0: core clock disabled
1: core clock enabled
Default
00
0
0
00
0
Table 29. Core Clock Output for fS = 44.1 kHz
MCLK Input Setting
256 × fS
512 × fS
768 × fS
1024 × fS
MCLK Input Value
11.2896 MHz
22.5792 MHz
33.8688 MHz
45.1584 MHz
MCLK Input Divider
1
2
3
4
Core Clock
11.2896 MHz
11.2896 MHz
11.2896 MHz
11.2896 MHz
MCLK Input Divider
1
2
3
4
Core Clock
12.288 MHz
12.288 MHz
12.288 MHz
12.288 MHz
Table 30. Core Clock Output for fS = 48 kHz
MCLK Input Setting
256 × fS
512 × fS
768 × fS
1024 × fS
MCLK Input Value
12.288 MHz
24.576 MHz
36.864 MHz
49.152 MHz
Rev. B | Page 44 of 84
ADAU1381
Register 16385 (0x4001), Regulator Control
Bits[2:1], Regulator Output Level
Bits[10:9], Input Divider
These bits set the regulated voltage output for the digital core,
DVDDOUT. After the initialization sequence has completed,
the regulator output is set to 1.4 V. The recommended regulator
output level when the device begins to process audio is 1.5 V.
Therefore, this register should be set to 1.5 V when the sound
engine is being configured.
Register 16386 (0x4002), PLL Control
This is a 48-bit register that must be written to in a single burst
write. PLL operating parameters are used to scale the MCLK
input to the desired clock core in order to obtain an appropriate
PLL clock (PLL output frequency). The PLL can be configured
for either fractional or integer-N type MCLK inputs.
Bits[47:40], Denominator MSB
Byte 1, M[15:8] of the denominator (M) for fractional part of feedback divider. This is concatenated with Denominator LSB, M[7:0].
The input divider (X) divides the input clock to offer a wider
range of input clocks.
Bit 8, PLL Type
This selects the type of PLL operation, fractional or integer-N.
Fractional Type PLL
Fractional type MCLK inputs are scaled to the corresponding
desired core clock input using the parameters outlined in Table 33
and Table 34 as examples of typical base sampling frequencies
(44.1 kHz and 48 kHz). A numerical-controlled oscillator is
used to divide the PLL_CLK by a mixed number given by the
addition of the integer part (R) and fractional part (N/M).
For example, if the MCLK is 12 MHz, the required clock is
12.288 MHz, and fS is 48 kHz, then the PLL clock is 49.152 MHz
because PLL clock is always 1024 × fS; therefore,
PLL Clock/MCLK = 4.096 = 4 + (12/125) = R + (N/M)
Bits[39:32], Denominator LSB
In this case, the input divider is X = 1.
Byte 0, M[7:0] of the denominator (M) for fractional part of feedback divider. This is concatenated with Denominator MSB, M[15:8].
This allows the MCLK input to emulate the desired required clock
and output a 49.152 MHz PLL clock. Figure 30 shows how the PLL
uses the parameters to emulate the required 12.288 MHz clock.
Bits[31:24], Numerator MSB
Byte 1, N[15:8] of the numerator (N) for fractional part of the feedback divider. This is concatenated with Numerator LSB, N[7:0].
Bits[23:16], Numerator LSB
Byte 0, N[7:0] of the numerator (N) for fractional part of the feedback divider. This is concatenated with Numerator MSB, N[15:8].
Integer-N Type PLL
Integer-N type MCLK inputs are any integer multiple of the
desired core clock. The fractional part (N/M) is 0; however, the
PLL type bit must be set for integer-N.
Bit 1, PLL Lock
The PLL lock bit is a read-only bit. Reading a 1 from this bit
indicates that the PLL has locked to the input master clock.
Bits[14:11], Integer
Integer (R) parameter used in both integer-N and fractional
PLL operation. This value must be between 2 and 8.
Bit 0, PLL Enable
This bit enables the PLL.
Table 31. Regulator Control Register
Bits
[7:3]
[2:1]
0
Description
Reserved
Regulator output level
00: 1.5 V
01: 1.4 V
10: 1.6 V
11: 1.7 V
Reserved
Rev. B | Page 45 of 84
Default
01
ADAU1381
Table 32. PLL Control Register
Bits
[47:40]
[39:32]
[31:24]
[23:16]
15
[14:11]
[10:9]
8
[7:2]
1
0
Description
Denominator MSB
00000000 and 00000000: M[15:8] and M[7:0] = 0
…
00000000 and 11111101: M[15:8] and M[7:0] = 125
…
11111111 and 11111111: M[15:8] and M[7:0] = 65,535
Denominator LSB
00000000 and 00000000: M[15:8] and M[7:0] = 0
…
00000000 and 11111101: M[15:8] and M[7:0] = 125
…
11111111 and 11111111: M[15:8] and M[7:0] = 65,535
Numerator MSB
00000000 and 00000000: N[15:8] and N[7:0] = 0
…
00000000 and 00001100: N[15:8] and N[7:0] = 12
…
11111111 and 11111111: N[15:8] and N[7:0] = 65,535
Numerator LSB
00000000 and 00000000: N[15:8] and N[7:0] = 0
…
00000000 and 00001100: N[15:8] and N[7:0] = 12
…
11111111 and 11111111: N[15:8] and N[7:0] = 65,535
Reserved
Integer
0010: R = 2
0011: R = 3
0100: R = 4
0101: R = 5
0110: R = 6
0111: R = 7
1000: R = 8
Input divider
00: no division
01: divide by X = 2
10: divide by X = 3
11: divide by X = 4
PLL type
0: integer-N
1: fractional
Reserved
PLL lock (read only)
0: unlocked
1: locked (sticky bit)
PLL enable
0: disabled
1: enabled
Rev. B | Page 46 of 84
Default
00000111
01010011
00000010
10000111
0011
00
1
1
1
ADAU1381
Table 33. Fractional PLL Parameter Settings for fS = 44.1 kHz (fS = 44.1 kHz, Core Clock = 256 × 44.1 kHz, PLL Clock = 45.1584 MHz)
MCLK Input (MHz)
12
13
14.4
19.2
19.68
19.8
Input Divider (X)
1
1
1
1
1
1
Integer (R)
3
3
3
2
2
2
Denominator (M)
625
8125
125
125
2035
1375
Numerator (N)
477
3849
17
44
302
386
Table 34. Fractional PLL Parameter Settings for fS = 48 kHz (fS = 48 kHz, Core Clock = 256 × 48 kHz, PLL Clock = 49.152 MHz)
MCLK Input (MHz)
12
13
14.4
19.2
19.68
19.8
Input Divider (X)
1
1
1
1
1
1
Integer (R)
4
3
3
2
2
2
Rev. B | Page 47 of 84
Denominator (M)
125
1625
75
25
205
825
Numerator (N)
12
1269
31
14
102
398
ADAU1381
RECORD PATH CONFIGURATION
Bit 3, Beep Input Mute
Register 16392 (0x4008), Digital Microphone and
Analog Beep Control
This bit mutes the beep input.
This register controls the digital microphone settings and the
analog beep input gain.
Bits[5:4], Digital Microphone Enable
These bits control the enable function for the stereo digital
microphones. The analog front end is powered down when
using a digital microphone.
Bits[2:0], Beep Input Gain
This bit controls the gain setting for the analog beep input; it
defaults at 0 dB and can be set as high as 32 dB. The beep signal
must be enabled in Register 16400 (0x4010), microphone bias
control and beep enable.
Table 35. Digital Microphone and Analog Beep Control Register
Bits
[7:6]
[5:4]
3
[2:0]
Description
Reserved
Digital microphone enable
00: disabled
01: MICD1 enabled
10: MICD2 enabled
11: reserved
Beep input mute
0: muted
1: unmuted
Beep input gain. Note that Setting 100 sets the input beep gain to −23 dB.
000: 0 dB
001: +6 dB
010: +10 dB
011: +14 dB
100: −23 dB
101: +20 dB
110: +26 dB
111: +32 dB
Rev. B | Page 48 of 84
Default
00
0
000
ADAU1381
Register 16393 (0x4009), Record Power Management
Bits[6:5], Mixer Amplifier Boost
This register manages the power consumption for the record
path. In particular, the current distribution for the mixer boosts,
ADC, front-end mixer, and PGAs can be set in one of four
modes. The four modes of operation available that affect the
performance of the device are normal operation, power saving,
enhanced performance, and extreme power saving. Normal
operation has a base current of 2.5 μA, enhanced performance
has a base current of 3 μA, power saving has a base current of
a 2 μA, and extreme power saving has a base current of 1.5 μA.
Enhanced performance offers the highest performance, but
with the trade-off of higher power consumption.
These bits set the power mode of operation for the front-end
mixer boost. With higher AVDD1 levels, distortion may become
an issue affecting performance. Each boost level enhances the
THD + N performance at 3.3 V AVDD1.
Bits[4:3], ADC Bias Control
These bits set the bias current for the ADCs based on the mode
of operation selected.
Bits[2:1], Front-End Bias Control
These bits set the bias current for the PGAs and mixers in the
front-end record path.
Table 36. Record Power Management Register
Bits
7
[6:5]
[4:3]
[2:1]
0
Description
Reserved
Mixer amplifier boost
00: normal operation
01: Boost Level 1
10: Boost Level 2
11: Boost Level 3
ADC bias control
00: normal operation
01: extreme power saving
10: power saving
11: enhanced performance
Front-end bias control
00: normal operation
01: extreme power saving
10: power saving
11: enhanced performance
Reserved
Rev. B | Page 49 of 84
Default
00
00
00
ADAU1381
Register 16398 (0x400E), Record Gain Left PGA
The record gain left PGA control register controls the left channel
input PGA. This register configures the input for either differential or single-ended signals and sets the left channel input
recording volume.
input pin (LMICP) is disabled, and the complementary input of
the PGA is switched to common mode.
Bit 1, Record Path Left Mute
This bit mutes the left channel input PGA.
Bit 0, Left PGA Enable
Bits[7:5], Left Input Gain
These bits set the left channel analog microphone input PGA gain.
This bit enables the left channel input PGA
Bit 2, Single-Ended Left Input Enable
If this bit is high (enabled), a single-ended input can be input on
the LMIC pin and gained by the PGA. The positive differential
Table 37. Record Gain Left PGA Register
Bits
[7:5]
[4:3]
2
1
0
Description
Left input gain
000: 0 dB
001: 6 dB
010: 10 dB
011: 14 dB
100: 17 dB
101: 20 dB
110: 26 dB
111: 32 dB
Reserved
Single-ended left input enable
0: disabled
1: enabled
Record path left mute
0: muted
1: unmuted
Left PGA enable
0: disabled
1: enabled
Default
000
0
0
0
Rev. B | Page 50 of 84
ADAU1381
Register 16399 (0x400F), Record Gain Right PGA
The record gain right PGA control register controls the right
channel input PGA. This register configures the input for either
differential or single-ended signals and sets the right channel
input recording volume.
input pin (RMICP) is disabled, and the complementary input of
the PGA is switched to common mode.
Bit 1, Record Path Right Mute
This bit mutes the entire right channel input PGA.
Bit 0, Right PGA Enable
Bits[7:5], Right Input Gain
These bits set the right channel analog microphone input PGA gain.
This bit enables the right channel PGA.
Bit 2, Single-Ended Right Input Enable
If this bit is high (enabled), a single-ended input can be input on
the RMIC pin and gained by the PGA. The positive differential
Table 38. Record Gain Right PGA Register
Bits
[7:5]
[4:3]
2
1
0
Description
Right input gain
000: 0 dB
001: 6 dB
010: 10 dB
011: 14 dB
100: 17 dB
101: 20 dB
110: 26 dB
111: 32 dB
Reserved
Single-ended right input enable
0: disabled
1: enabled
Record path right mute
0: muted
1: unmuted
Right PGA enable
0: disabled
1: enabled
Default
000
0
0
0
Rev. B | Page 51 of 84
ADAU1381
Register 16400 (0x4010), Microphone Bias Control and
Beep Enable
Bit 4, Beep Input Enable
This bit enables the beep signal, which is input to the BEEP pin.
Setting this bit to 0 mutes the beep signal for all output paths.
Bit 2, Microphone Gain
Provides two voltage bias options, 0.65 × AVDD1 and 0.90 ×
AVDD1. A higher bias contributes to a higher microphone gain.
The maximum current that can be drawn from MICBIAS is 5 mA.
Bit 0, Microphone Bias Enable
This bit enables the MICBIAS output.
Bit 3, Microphone High Performance
This bit puts the microphone bias into high performance mode,
by offering more current to the microphone.
Table 39. Microphone Bias Control and Beep Enable Register
Bits
[7:5]
4
3
2
1
0
Description
Reserved
Beep input enable
0: disabled
1: enabled
Microphone high performance
0: high power
1: low performance
Microphone gain
0: enabled
1: disabled
Reserved
Microphone bias enable
0: disabled
1: enabled
Default
0
0
0
0
Rev. B | Page 52 of 84
ADAU1381
SERIAL PORT CONFIGURATION
Bits[2:1], Channels per Frame
Register 16405 (0x4015), Serial Port Control 0
Bit 5, LRCLK Mode
These bits set the number of channels contained in the data stream
(see Figure 59). The possible choices are stereo (used in standard
I2S signals), TDM 4 (a 4-channel time division multiplexed stream),
or TDM 8 (an 8-channel time division multiplexed stream). The
TDM output modes are simply multichannel data streams, and
the data pin does not become high impedance during periods
when it is not outputting data.
This bit sets the serial port frame clock (LRCLK) as either a
50% duty cycle waveform or a pulse synchronization waveform.
When in slave mode, the pulse should be at least 1 BCLK cycle
wide to guarantee proper data transfer.
Bit 4, BCLK Polarity
This bit sets the polarity of the bit clock (BCLK) signal. This
setting determines whether the data and frame clock signals
change on a rising (+) or falling (−) edge of the BCLK signal
(see Figure 57). Standard I2S signals use negative BCLK polarity.
Bit 3, LRCLK Polarity
Within a TDM stream, channels are grouped by pair, as shown
in Figure 60.
Bit 0, Serial Data Port Mode
This bit sets the clock pins as either master or slave. Both
LRCLK and BCLK are the bus master of the serial port when
master mode is enabled.
The polarity of LRCLK determines whether the left stereo channel
is initiated on a rising (+) or falling (−) edge of the LRCLK signal
(see Figure 58). Standard I2S signals use negative LRCLK polarity.
Table 40. Serial Port Control 0 Register
Bits
[7:6]
5
4
3
[2:1]
0
Description
Reserved
LRCLK mode
0: 50% duty cycle clock
1: pulse mode; pulse should be at least 1 BCLK wide
BCLK polarity
0: data changes on falling (−) edge
1: data changes on rising (+) edge
LRCLK polarity
0: left frame starts on falling (−) edge
1: left frame starts on rising (+) edge
Channels per frame
00: stereo (two channels)
01: TDM 4 (four channels)
10: TDM 8 (eight channels)
11: reserved
Serial data port mode
0: slave
1: master
Rev. B | Page 53 of 84
Default
0
0
0
00
0
ADAU1381
BCLK POLARITY
LRCLK
BCLK
SDATA
LRCLK
08313-055
BCLK
SDATA
Figure 57. Serial Port BCLK Polarity
LRCLK POLARITY
LRCLK
R
L
R
L
R
08313-056
L
LRCLK
Figure 58. Serial Port LRCLK Polarity
1/fLRCLK
LRCLK
1
TDM 4 CHANNELS
2
1
TDM 8 CHANNELS
2
1
2
3
3
4
4
5
6
7
8
08313-057
STEREO CHANNELS
Figure 59. Channels per Frame
1/fLRCLK
LRCLK
TDM 4 CHANNELS
TDM 8 CHANNELS
1
1
2
3
4
FIRST PAIR
SECOND PAIR
THIRD PAIR
FOURTH PAIR
2
3
4
5
Figure 60. TDM Channel Pairs
Rev. B | Page 54 of 84
6
7
8
08313-058
SECOND PAIR
FIRST PAIR
ADAU1381
Bit 2, MSB Position
Register 16406 (0x4016), Serial Port Control 1
Bits[7:5], Number of Bit Clock Cycles per Frame
These bits set the number of BCLK cycles contained in one
LRCLK period. The frequency of BCLK is calculated as the
number of bit clock cycles per frame times the sample rate of
the serial port in hertz. Figure 61 and Figure 62 show examples
of different settings for these bits.
Bit 4, ADC Channel Position in TDM
This register sets the order of the ADC channels when output on
the serial output port. A setting of 0 puts the left channel first in its
respective TDM channel pair. A setting of 1 puts the right channel
first in its respective TDM channel pair. This bit should be set in
conjunction with Register 16408 (0x4018), Converter Control 1,
Bits[1:0], on-chip ADC data selection in TDM mode, to select
where the data should appear in the TDM stream. Figure 63
shows a setting of 0, and Figure 64 shows a setting of 1.
Bit 3, DAC Channel Position in TDM
This register sets the order of the DAC channels when output on
the serial output port. A setting of 0 puts the left channel first in its
respective TDM channel pair. A setting of 1 puts the right channel
first in its respective TDM channel pair. This bit should be set in
conjunction with Register 16407 (0x4017), Converter Control 0,
Bits[6:5], on-chip DAC data selection in TDM mode, to select
where the data should appear in the TDM stream. Figure 63
shows a setting of 0, and Figure 64 shows a setting of 1.
This bit sets the bit-level endianness (or bit order) of the data
stream. A setting of 0 results in a big-endian order, with the MSB
coming first in the stream and the LSB coming last. A setting of 1
results in a little-endian order, with the LSB coming first in the
stream and the MSB coming last. Figure 65 shows examples of
the two settings with a 24-bit audio stream in an MSB delay-by-0
configuration. In Figure 65, M stands for MSB, and L stands for
LSB.
Bits[1:0], Data Delay from LRCLK Edge
These bits set the delay between the LRCLK edge and the first
data bit in the stream. The I2S standard is a delay of one BCLK
cycle. Examples of different data delay settings are shown in
Figure 66, with a 64 BCLK cycle per frame, 24-bit audio data,
big-endian bit order configuration. In Figure 66, M represents
the most significant bit of the audio channel’s data, and L represents
the least significant bit.
The first example setting (delay by 0) in Figure 66 represents a leftjustified mode because the least significant bit aligns with the
beginning of the audio frame. The third example setting (delay
by 8) represents a right-justified mode because the least significant
bit aligns with the end of the audio frame. A delay-by-16 setting
would not be valid in this mode because the audio data would
exceed the boundaries of the frame clock period.
Figure 67 shows an example of delay by 16 for a 16-bit audio
stream with 64 BCLK cycles per frame.
Table 41. Serial Port Control 1 Register
Bits
[7:5]
4
3
2
[1:0]
Description
Number of bit clock cycles per frame
000: 64
001: 32
010: 48
011: 128
100: 256
101: reserved
110: reserved
111: reserved
ADC channel position in TDM
0: left first
1: right first
DAC channel position in TDM
0: left first
1: right first
MSB position
0: MSB first
1: MSB last
Data delay from LRCLK edge
00: 1 BCLK cycle
01: 0 BCLK cycles
10: 8 BCLK cycles
11: 16 BCLK cycles
Default
000
0
0
0
00
Rev. B | Page 55 of 84
ADAU1381
1/fLRCLK
BCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
08313-059
LRCLK
Figure 61. Example: 32 BCLK Cycles per Frame
1/fLRCLK
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Figure 62. Example: 48 BCLK Cycles per Frame
1/fLRCLK
LRCLK
FIRST PAIR
RIGHT
LEFT
RIGHT
FIRST PAIR
SECOND PAIR
THIRD PAIR
FOURTH PAIR
RIGHT
LEFT
TDM 8 CHANNELS
SECOND PAIR
LEFT
TDM 4 CHANNELS
LEFT
RIGHT
LEFT
RIGHT
LEFT
08313-061
2
RIGHT
Figure 63. Left First Channel Selection in TDM
1/fLRCLK
LRCLK
FIRST PAIR
RIGHT
LEFT
RIGHT
LEFT
FIRST PAIR
SECOND PAIR
THIRD PAIR
FOURTH PAIR
TDM 4 CHANNELS
LEFT
RIGHT
TDM 8 CHANNELS
SECOND PAIR
RIGHT
LEFT
RIGHT
LEFT
RIGHT
08313-062
1
LEFT
Figure 64. Right First Channel Selection in TDM
BCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB FIRST
M
L
LSB FIRST
L
M
Figure 65. MSB Position Settings
Rev. B | Page 56 of 84
16
17
18
19
20
21
22
23
24
08313-063
BCLK
08313-060
LRCLK
ADAU1381
1/fLRCLK
LRCLK
SERIAL DATA
(DELAY BY 1)
SERIAL DATA
(DELAY BY 8)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
M
L
M
M
L
M
L
M
L
L
M
08313-064
BCLK
SERIAL DATA
(DELAY BY 0)
L
Figure 66. Serial Audio Data Delay Example Settings
1/fLRCLK
LRCLK
SERIAL DATA
(DELAY BY 16)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
M
L
Figure 67. Serial Audio Data Delay by 16 Example
Rev. B | Page 57 of 84
M
L
08313-065
BCLK
ADAU1381
AUDIO CONVERTER CONFIGURATION
Bit 4, DAC Oversampling Ratio
Register 16407 (0x4017), Converter Control 0
Bits[6:5], On-Chip DAC Data Selection in TDM Mode
This bit sets the oversampling ratio of the DAC relative to the
audio sample rate. The higher rate yields slightly better audio
quality but increases power consumption.
These bits set the position of the DAC input channels on a TDM
stream. In TDM 4 mode, valid settings are first pair or second
pair. In TDM 8 mode, valid settings are first pair, second pair,
third pair, or fourth pair. These bits should be set in conjunction
with Register 16406 (0x4016), Serial Port Control 1, Bit 3, DAC
channel position in TDM, to select where the data should appear
in the TDM stream.
Figure 68, Figure 69, and Figure 70 show examples of different
TDM settings.
Bit 3, ADC Oversampling Ratio
This bit sets the oversampling ratio of the ADC relative to the
audio sample rate. The higher rate yields slightly better audio
quality but increases power consumption.
Bits[2:0], Converter Sampling Rate
These bits set the sampling rate of the audio ADCs and DACs
relative to the sound engine’s audio sample rate.
Table 42. Converter Control 0 Register
Bits
7
[6:5]
4
3
[2:0]
Description
Reserved
On-chip DAC data selection in TDM mode
00: first pair
01: second pair
10: third pair
11: fourth pair
DAC oversampling ratio
0: 128
1: 64
ADC oversampling ratio
0: 128
1: 64
Converter sampling rate; the numbers in parentheses are example values for a base sample rate of 48 kHz
000: fS (48 kHz)
001: fS/6 (8 kHz)
010: fS/4 (12 kHz)
011: fS/3 (16 kHz)
100: fS/2 (24 kHz)
101: fS/1.5 (32 kHz)
110: fS × 2 (96 kHz)
111: reserved
Rev. B | Page 58 of 84
Default
00
0
0
000
ADAU1381
1/fLRCLK
LRCLK
RIGHT
FIRST PAIR
SECOND PAIR
TDM 8 CHANNELS
LEFT
THIRD PAIR
FOURTH PAIR
RIGHT
08313-066
SECOND PAIR
FIRST PAIR
LEFT
TDM 4 CHANNELS
Figure 68. Example of Left Channel First, First Pair TDM Setting
1/fLRCLK
LRCLK
TDM 4 CHANNELS
FIRST PAIR
SECOND PAIR
RIGHT
TDM 8 CHANNELS
RIGHT
LEFT
THIRD PAIR
FOURTH PAIR
LEFT
08313-067
SECOND PAIR
FIRST PAIR
Figure 69. Example of Right Channel First, Second Pair TDM Setting
1/fLRCLK
FIRST PAIR
SECOND PAIR
THIRD PAIR
FOURTH PAIR
LEFT
TDM 8 CHANNELS
Figure 70. Example of Left Channel First, Fourth Pair TDM Setting
Rev. B | Page 59 of 84
RIGHT
08313-068
LRCLK
ADAU1381
Register 16408 (0x4018), Converter Control 1
Bits[1:0], On-Chip ADC Data Selection in TDM Mode
with Register 16406 (0x4016), Serial Port Control 1, Bit 4, ADC
channel position in TDM, to select where the data should appear
in the TDM stream.
These bits set the position of the ADC output channels on a TDM
stream. In TDM 4 mode, valid settings are first pair or second
pair. In TDM 8 mode, valid settings are first pair, second pair,
third pair, or fourth pair. These bits should be set in conjunction
Figure 68, Figure 69, and Figure 70 show examples of different
TDM settings.
Table 43. Converter Control 1 Register
Bits
[7:2]
[1:0]
Description
Reserved
On-chip ADC data selection in TDM mode
00: first pair
01: second pair
10: third pair
11: fourth pair
Default
00
Rev. B | Page 60 of 84
ADAU1381
Bit 3, Digital Microphone Channel Swap
Register 16409 (0x4019), ADC Control
Bit 6, Invert Input Polarity
This bit enables an optional polarity inverter in the ADC path,
which is an amplifier with a gain of −1, representing a 180°
phase shift.
Bit 5, High-Pass Filter Select
This bit allows the left and right channels of the digital microphone
input to swap. Standard mode is the left channel on the rising
edge and the right channel on the falling edge. Swapped mode is
the right channel on the rising edge and the left channel on the
falling edge.
Bit 2, Digital Microphone Input Select
This bit enables an optional high-pass filter in the ADC path,
with a cutoff frequency of 2 Hz when fS = 48 kHz. The cutoff
frequency scales linearly with fS.
Bit 4, Digital Microphone Data Polarity Swap
This bit inverts the polarity of valid data states for the digital
microphone data stream. A typical PDM microphone can drive
its data output pin either high or low, not both. This bit must be
configured accordingly to recognize a valid output state of the
microphone. The default is negative, meaning that a digital
logic low signal is recognized by the ADAU1381 as a pulse in
the PDM signal.
This bit must be enabled in order to use the digital microphone
inputs. When this bit is asserted, the on-chip ADCs are off, BCLK
is the master at 128 × fS, and ADC_SDATA is expected to have
the left and right channels interleaved. This bit must be disabled
to use the ADCs.
Bits[1:0], ADC Enable
These bits must be configured to use the ADCs. ADC channels
can be enabled or disabled individually.
Table 44. ADC Control Register
Bits
7
6
5
4
3
2
[1:0]
Description
Reserved
Invert input polarity
0: normal
1: inverted
High-pass filter select
0: disabled
1: enabled
Digital microphone data polarity swap
0: negative
1: positive
Digital microphone channel swap
0: standard mode
1: swapped mode
Digital microphone input select
0: digital microphone input off
1: select digital microphone input, ADCs off
ADC enable
00: both off
01: left on
10: right on
11: both on
Default
0
0
0
0
0
00
Rev. B | Page 61 of 84
ADAU1381
Register 16410 (0x401A), Left ADC Attenuator
Bits[7:0], Left ADC Digital Attenuator
Register 16411 (0x401B), Right ADC Attenuator
Bits[7:0], Right ADC Digital Attenuator
These bits control a 256-step, logarithmically spaced volume
control from 0 dB to −95.625 dB, in increments of 0.375 dB.
When a new value is entered into this register, the volume control
slews gradually to the new value, avoiding pops and clicks in the
process. The slew ramp is logarithmic, incrementing 0.375 dB
per audio frame.
These bits control a 256-step, logarithmically spaced volume
control from 0 dB to −95.625 dB, in increments of 0.375 dB.
When a new value is entered into this register, the volume control
slews gradually to the new value, avoiding pops and clicks in the
process. The slew ramp is logarithmic, incrementing 0.375 dB
per audio frame.
Table 45. Left ADC Attenuator Register
Bits
[7:0]
Description
Left ADC digital attenuator; attenuation is in increments of 0.375 dB with each step of slewing
00000000: 0 dB
00000001: −0.375 dB
00000010: −0.75 dB
…
11111110: −95.25 dB
11111111: −95.625 dB
Default
00000000
Table 46. Right ADC Attenuator Register
Bits
[7:0]
Description
Right ADC digital attenuator; attenuation is in increments of 0.375 dB with each step of slewing
00000000: 0 dB
00000001: −0.375 dB
00000010: −0.75 dB
…
11111110: −95.25 dB
11111111: −95.625 dB
Rev. B | Page 62 of 84
Default
00000000
ADAU1381
PLAYBACK PATH CONFIGURATION
Register 16412 (0x401C), Playback Mixer Left Control
Bit 5, Left DAC Mute
This bit mutes the left DAC output. It does not have any slew
and is updated immediately when the register write has been
completed. This results in an abrupt cutoff of the audio output
and should therefore be preceded by a soft mute in the sound
engine or a slew mute using the DAC attenuator.
Bits[4:1], Left Playback Beep Gain
These bits set the gain of the beep signal in the left playback
path. If the zero-crossing detector is activated, the change in
gain is applied on the next detected zero crossing or when the
timeout period expires, whichever comes first. The gain control
is in 3 dB increments and should not be incremented more than
3 dB at a time in order to avoid audible artifacts on the output.
Register 16414 (0x401E), Playback Mixer Right Control
Bit 6, Right DAC Mute
This bit mutes the right DAC output. It does not have any slew
and is updated immediately when the register write has been
completed. This results in an abrupt cutoff of the audio output
and should therefore be preceded by a soft mute in the sound
engine or a slew mute using the DAC attenuator.
Bits[4:1], Right Playback Beep Gain
These bits set the gain of the beep signal in the right playback
path. If the zero-crossing detector is activated, the change in
gain is applied on the next detected zero crossing or when the
timeout period expires, whichever comes first. The gain control
is in 3 dB increments and should not be incremented more than
3 dB at a time in order to avoid audible artifacts on the output.
Table 47. Playback Mixer Left Control Register
Bits
[7:6]
5
[4:1]
0
Description
Reserved
Left DAC mute
0: muted
1: unmuted
Left playback beep gain
0000: muted
0001: −15 dB
0010: −12 dB
0011: −9 dB
0100: −6 dB
0101: −3 dB
0110: 0 dB
0111: +3 dB
1000: +6 dB
Reserved
Default
0
0000
Table 48. Playback Mixer Right Control Register
Bits
7
6
5
[4:1]
0
Description
Reserved
Right DAC mute
0: muted
1: unmuted
Reserved
Right playback beep gain
0000: muted
0001: −15 dB
...
1000: +6 dB
Reserved
Default
0
0000
Rev. B | Page 63 of 84
ADAU1381
Register 16415 (0x401F), Playback Mono Mixer Control
Bit 7, Left DAC Mute
This bit mutes the left DAC output, but does not power down
the DAC. Use of this bit does not result in power savings.
Bit 6, Right DAC Mute
This bit mutes the right DAC output, but does not power down
the DAC. Use of this bit does not result in power savings.
Bits[5:2], Mono Playback Beep Gain
These bits set the gain of the beep output signal in mono mode.
If the zero-crossing detector is active, then the gain change
takes place on the next zero crossing in the beep signal or when
the timeout occurs, whichever comes first.
Bit 0, Mono Output Mute
This bit mutes the mono line output.
Register 16416 (0x4020), Playback Clamp Amp Control
The playback clamp amp is an amplifier on the line output path.
If the line outputs are muted using Register 16421 (0x4025), left
line output mute, or Register 16422 (0x4026), right line output
mute, this amplifier serves to maintain a common-mode voltage
on the line output pins. This helps to avoid a pop or click when
the line outputs are reenabled.
Bit 1, Clamp Amplifier Power Saving Mode
The clamp amplifier has two operating modes: high power
mode and low power mode. The high power mode has more
current available to maintain a stable common-mode voltage on
the output pins. The low power mode may be slightly less stable,
depending on operating conditions, but saves several microamps.
Bit 0, Clamp Amplifier Control
This bit enables or disables the clamp amp. It is enabled by default.
The clamp amp should usually be enabled in systems where the
line outputs are used.
Table 49. Playback Mono Mixer Control Register
Bits
7
6
[5:2]
1
0
Description
Left DAC mute
0: muted
1: unmuted
Right DAC mute
0: muted
1: unmuted
Mono playback beep gain
0000: muted
0001: −15 dB
0010: −12 dB
0011: −9 dB
0100: −6 dB
0101: −3 dB
0110: 0 dB
0111: +3 dB
1000: +6 dB
Reserved
Mono output mute (active low)
0: muted
1: unmuted
Default
0
0
0000
0
Table 50. Playback Clamp Amplifier Control Register
Bits
[7:2]
1
0
Description
Reserved
Clamp amplifier power saving mode
0: high power
1: low power
Clamp amplifier control
0: enabled
1: disabled
Default
1
0
Rev. B | Page 64 of 84
ADAU1381
Register 16421 (0x4025), Left Line Output Mute
Bit 1, Left Line Output Mute
Register 16422 (0x4026), Right Line Output Mute
Bit 1, Right Line Output Mute
This bit mutes the left line output. It does not have any effect on
the speaker outputs.
This bit mutes the right line output. It does not have any effect
on the speaker outputs.
Table 51. Left Line Output Mute Register
Bits
[7:2]
1
0
Description
Reserved
Left line output mute (active low)
0: muted
1: unmuted
Reserved
Default
0
Table 52. Right Line Output Mute Register
Bits
[7:2]
1
0
Description
Reserved
Right line output mute (active low)
0: muted
1: unmuted
Reserved
Default
0
Rev. B | Page 65 of 84
ADAU1381
Register 16423 (0x4027), Playback Speaker Output
Control
Bits[7:6], Speaker Output Gain Control
Register 16424 (0x4028), Beep Zero-Crossing Detector
Control
Bits[4:3], Detector Timeout
These bits control the gain of the speaker output. In general, this
parameter should be tuned at a system level, set once during system
initialization and not altered during operation of the system.
The timeout detector waits the specified amount of time for a
beep zero crossing before forcing the mute or unmute in the
playback path beep gains (that is, the left playback beep gain,
right playback beep gain, and mono playback beep gain).
Bit 0, Speaker Output Enable
This bit enables the speaker output. It initiates the speaker powerup and power-down sequences shown in Figure 36 and Figure 37.
Bit 0, Zero-Crossing Detector Enable
This bit enables the zero-crossing detector. Disabling the beep
zero-crossing detector may cause clicks and pops on the output
when using the beep path.
Table 53. Playback Speaker Output Control Register
Bits
[7:6]
[5:1]
0
Description
Speaker output gain control
00: 0 dB
01: 2 dB
10: 4 dB
11: 6 dB
Reserved
Speaker output enable
0: disabled
1: enabled
Default
00
0
Table 54. Beep Zero-Crossing Detector Control Register
Bits
[7:5]
[4:3]
[2:1]
0
Description
Reserved
Detector timeout
00: 20 ms
01: 10 ms
10: 5 ms
11: 2.5 ms
Reserved
Zero-crossing detector enable
0: disabled
1: enabled
Default
11
1
Rev. B | Page 66 of 84
ADAU1381
Register 16425 (0x4029), Playback Power Management
Bits[5:4], DAC Bias Control
This register controls the unity current supplied to each functional
block described. Within the functional blocks, the current can
be multiplied. Normal operation has a base current of 2.5 μA,
enhanced performance has a base current of 3 μA, power saving
has a base current of 2 μA, and extreme power saving has a base
current of 1.5 μA. Enhanced performance mode offers the best
audio quality but also uses the most current.
These bits control the amount of unity bias current allotted to
the DAC.
Bit [7:6], Speaker Amplifier Bias Control
This bit enables the playback mixers and amplifiers.
These bits control the amount of unity bias current allotted to
the speaker amplifier.
Bit 0, Back-End Left Enable
Bits[3:2], Back-End Bias Control
These bits control the amount of unity bias current allotted to
the playback mixers and amplifiers.
Bit 1, Back-End Right Enable
This bit enables the playback mixers and amplifiers.
Table 55. Playback Power Management Register
Bits
[7:6]
[5:4]
[3:2]
1
0
Description
Speaker amplifier bias control
00: normal operation
01: power saving
10: enhanced performance
00: reserved
DAC bias control
00: normal operation
01: extreme power saving
10: power saving
00: enhanced performance
Back-end bias control
00: normal operation
01: extreme power saving
10: power saving
00: enhanced performance
Back-end right enable
0: disabled
1: enabled
Back-end left enable
0: disabled
1: enabled
Default
00
00
00
0
0
Rev. B | Page 67 of 84
ADAU1381
Bit 5, Invert Input Polarity
Register 16426 (0x402A), DAC Control
Bits[7:6], Mono Mode
These bits control the output mode of the DAC. Setting these
bits to 00 outputs two distinct channels, left and right. Setting
these bits to 01 outputs the left input channel on both the left
and right outputs, and the right input channel is lost. Setting
these bits to 10 outputs the right input channel on both the left
and right outputs, and the left input channel is lost. Setting these
bits to 11 mixes the left and right input channels and outputs
the mixed mono signal on both the left and right outputs.
This bit applies a gain of −1, or a 180° phase shift, to the DAC
output signal.
Bit 2, DAC De-Emphasis Filter Enable
This bit enables a de-emphasis filter and should be used when a
preemphasized signal is input to the DACs.
Bits[1:0], DAC Enable
These bits allow the DACs to be individually enabled or disabled.
Disabling unused DACs can result in significant power savings.
Table 56. DAC Control Register
Bits
[7:6]
5
[4:3]
2
[1:0]
Description
Mono mode
00: stereo output
01: both output left channel
10: both output right channel
11: both output left/right mix
Invert input polarity
0: normal
1: inverted
Reserved
DAC de-emphasis filter enable
0: disabled
1: enabled
DAC enable
00: both off
01: left on
10: right on
11: both on
Default
00
0
0
00
Rev. B | Page 68 of 84
ADAU1381
Register 16427 (0x402B), Left DAC Attenuator
Bits[7:0], Left DAC Digital Attenuator
Register 16428 (0x402C), Right DAC Attenuator
Bits[7:0], Right DAC Digital Attenuator
These bits control a 256-step, logarithmically spaced volume
control from 0 dB to −95.625 dB, in increments of 0.375 dB.
When a new value is entered into this register, the volume control
slews gradually to the new value, avoiding pops and clicks in the
process. The slew ramp is logarithmic, incrementing 0.375 dB
per audio frame.
These bits control a 256-step, logarithmically spaced volume
control from 0 dB to −95.625 dB, in increments of 0.375 dB.
When a new value is entered into this register, the volume control
slews gradually to the new value, avoiding pops and clicks in the
process. The slew ramp is logarithmic, incrementing 0.375 dB
per audio frame.
Table 57. Left DAC Attenuator Register
Bits
[7:0]
Description
Left DAC digital attenuator, in increments of 0.375 dB with each step of slewing
00000000: 0 dB
00000001: −0.375 dB
00000010: −0.75 dB
…
11111110: −95. 25
11111111: −95.625 dB
Default
00000000
Table 58. Right DAC Attenuator Register
Bits
[7:0]
Description
Right DAC digital attenuator, in increments of 0.375 dB with each step of slewing
00000000: 0 dB
00000001: −0.375 dB
00000010: −0.75 dB
…
11111110: −95. 25
11111111: −95.625 dB
Rev. B | Page 69 of 84
Default
00000000
ADAU1381
PAD CONFIGURATION
Figure 71 shows a block diagram of the pad design for the GPIO/serial port and communications port pins.
DIGITAL
I/O
SUPPLY SUPPLY
DATA OUT
OUTPUT ENABLE
LEVEL
SHIFTER
OUTPUT
CONTROL
LOGIC
OUTPUT PULL-UP ENABLE
(CONTROLS PMOS)
DEBOUNCE
ENABLE
INPUT
ENABLE
PULL-UP
ENABLE
6×
DATA IN
DEBOUNCE
LEVEL
SHIFTER
INPUT
ESD
PAD
12×
PULL-DOWN
ENABLE
WEAK PULL-UP ENABLE
WEAK PULL-DOWN ENABLE
LEVEL
SHIFTER
WEAK PULL-UP/PULL-DOWN
240kΩ NOMINAL
190kΩ WORST CASE
08313-069
DRIVE STRENGTH
(CONTROLS NUMBER OF PARALLEL TRANSISTOR PAIRS)
IOVDD = 3.3V; LOW = 2.0mA, HIGH = 4.0mA
IOVDD = 1.8V; LOW = 0.75mA, HIGH = 1.5mA
Figure 71. Pad Configuration, Internal Design
Rev. B | Page 70 of 84
ADAU1381
Bits[3:2], LRCLK Pad Pull-Up/Pull-Down
Register 16429 (0x402D), Serial Port Pad Control 0
Bits[7:6], ADC_SDATA Pad Pull-Up/Pull-Down
These bits enable or disable a weak pull-up or pull-down device
on the pad. The effective resistance of the pull-up or pull-down
is nominally 240 kΩ.
Bits[5:4], DAC_SDATA Pad Pull-Up/Pull-Down
These bits enable or disable a weak pull-up or pull-down device
on the pad. The effective resistance of the pull-up or pull-down
is nominally 240 kΩ.
These bits enable or disable a weak pull-up or pull-down device
on the pad. The effective resistance of the pull-up or pull-down
is nominally 240 kΩ.
Bits[1:0], BCLK Pad Pull-Up/Pull-Down
These bits enable or disable a weak pull-up or pull-down device
on the pad. The effective resistance of the pull-up or pull-down
is nominally 240 kΩ.
Table 59. Serial Port Pad Control 0 Register
Bits
[7:6]
[5:4]
[3:2]
[1:0]
Description
ADC_SDATA pad pull-up/pull-down
00: pull-up
01: reserved
10: none (default)
11: pull-down
DAC_SDATA pad pull-up/pull-down
00: pull-up
01: reserved
10: none (default)
11: pull-down
LRCLK pad pull-up/pull-down
00: pull-up
01: reserved
10: none (default)
11: pull-down
BCLK pad pull-up/pull-down
00: pull-up
01: reserved
10: none (default)
11: pull-down
Default
11
11
11
11
Rev. B | Page 71 of 84
ADAU1381
Bit 1, LRCLK Pin Drive Strength
Register 16430 (0x402E), Serial Port Pad Control 1
Bit 3, ADC_SDATA Pin Drive Strength
This bit sets the drive strength of the ADC_SDATA pin. Low mode
yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD =
1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA
when IOVDD = 1.8 V.
Bit 2, DAC_SDATA Pin Drive Strength
This bit sets the drive strength of the DAC_SDATA pin. Low mode
yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD =
1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA
when IOVDD = 1.8 V.
This bit sets the drive strength of the LRCLK pin. Low mode yields
2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V.
High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when
IOVDD = 1.8 V.
Bit 0, BCLK Pin Drive Strength
This bit sets the drive strength of the BCLK pin. Low mode yields
2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V.
High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when
IOVDD = 1.8 V.
Table 60. Serial Port Pad Control 1 Register
Bits
[7:4]
3
2
1
0
Description
Reserved
ADC_SDATA pin drive strength
0: low
1: high
DAC_SDATA pin drive strength
0: low
1: high
LRCLK pin drive strength
0: low
1: high
BCLK pin drive strength
0: low
1: high
Default
0
0
0
0
Rev. B | Page 72 of 84
ADAU1381
Bits[3:2], SCL/CCLK Pad Pull-Up/Pull-Down
Register 16431 (0x402F), Communication Port Pad
Control 0
Bits[7:6], CDATA Pad Pull-Up/Pull-Down
These bits enable or disable a weak pull-up or pull-down device
on the pad. The effective resistance of the pull-up or pull-down
is nominally 240 kΩ.
Bits[5:4], CLATCH Pad Pull-Up/Pull-Down
These bits enable or disable a weak pull-up or pull-down device
on the pad. The effective resistance of the pull-up or pull-down
is nominally 240 kΩ.
These bits enable or disable a weak pull-up or pull-down device
on the pad. The effective resistance of the pull-up or pull-down
is nominally 240 kΩ.
Bits[1:0], SDA/COUT Pad Pull-Up/Pull-Down
These bits enable or disable a weak pull-up or pull-down device
on the pad. The effective resistance of the pull-up or pull-down
is nominally 240 kΩ.
Table 61. Communication Port Pad Control 0 Register
Bits
[7:6]
[5:4]
[3:2]
[1:0]
Description
CDATA pad pull-up/pull-down
00: pull-up
01: reserved
10: none (default)
11: pull-down
CLATCH pad pull-up/pull-down
00: pull-up
01: reserved
10: none (default)
11: pull-down
SCL/CCLK pad pull-up/pull-down
00: pull-up
01: reserved
10: none (default)
11: pull-down
SDA/COUT pad pull-up/pull-down
00: pull-up
01: reserved
10: none (default)
11: pull-down
Default
11
00
11
11
Rev. B | Page 73 of 84
ADAU1381
Bit 1, SCL/CCLK Pin Drive Strength
Register 16432 (0x4030), Communication Port Pad
Control 1
Bit 3, CDATA Pin Drive Strength
This bit sets the drive strength of the CDATA pin. Low mode yields
2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V.
High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when
IOVDD = 1.8 V.
Bit 2, CLATCH Pin Drive Strength
This bit sets the drive strength of the CLATCH pin. Low mode
yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD =
1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA
when IOVDD = 1.8 V.
This bit sets the drive strength of the SCL/CCLK pin. Low mode
yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD =
1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA
when IOVDD = 1.8 V.
Bit 0, SDA/COUT Pin Drive Strength
This bit sets the drive strength of the SDA/COUT pin. Low mode
yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD =
1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA
when IOVDD = 1.8 V.
Table 62. Communication Port Pad Control 1 Register
Bits
[7:4]
3
2
1
0
Description
Reserved
CDATA pin drive strength
0: low
1: high
CLATCH pin drive strength
0: low
1: high
SCL/CCLK pin drive strength
0: low
1: high
SDA/COUT pin drive strength
0: low
1: high
Default
0
0
0
0
Rev. B | Page 74 of 84
ADAU1381
Bit 1, MCKO Pull-Up Enable
Register 16433 (0x4031), MCKO Control
Bit 2, MCKO Pin Drive Strength
This bit sets the drive strength of the MCKO pin. Low mode yields
2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V.
High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when
IOVDD = 1.8 V.
This bit enables or disables a weak pull-up device on the pad.
The effective resistance of the pull-up is nominally 240 kΩ.
Bit 0, MCKO Pull-Down Enable
This bit enables or disables a weak pull-down device on the pad.
The effective resistance of the pull-down is nominally 240 kΩ.
Table 63. MCKO Control Register
Bits
[7:3]
2
1
0
Description
Reserved
MCKO pin drive strength
0: low
1: high
MCKO pull-up enable (active low)
0: pull-down disabled
1: pull-down enabled
MCKO pull-down enable
0: pull-down disabled
1: pull-down enabled
Default
0
0
1
Rev. B | Page 75 of 84
ADAU1381
Register 16434 (0x4032), Dejitter Control
Bits[7:0], Dejitter Window Size
The dejitter control register not only allows the size of the
dejitter window to be set, but also allows all dejitter circuits in
the device to be activated or bypassed. Dejitter circuits protect
against duplicate samples or skipped samples due to jitter from
the serial ports in slave mode. Disabling and reenabling certain
subsystems in the device—that is, the ADCs, serial ports, sound
engine/DSP core, and DACs—during operation can cause the
associated dejitter circuits to fail. As a result, audio data fails to
be output to the next subsystem in the device.
When the serial ports are in master mode, the dejitter circuit
can be bypassed by setting the dejitter window to 0. When the
serial ports are in slave mode, the dejitter circuit can be reinitialized
prior to outputting audio from the device, guaranteeing that audio
is output to the next subsystem in the device. Any time audio
needs to pass through the ADCs, serial port, sound engine/DSP
core, or DACs, the dejitter circuit can be bypassed and reset by
setting the dejitter window size to 0. Then, the dejitter circuit can
be immediately reactivated, without a wait period, by setting the
dejitter window size to the default value of 5.
Table 64. Dejitter Control Register
Bits
[7:0]
Description
Dejitter window size
00000000: 0 core clock cycles
00000101: 5 core clock cycles
Default
00000101
Rev. B | Page 76 of 84
ADAU1381
DIGITAL SUBSYSTEM CONFIGURATION
Bit 3, Serial Output Routing
Register 16512 (0x4080), Digital Power-Down 0
Bit 7, ADC Engine
Setting this bit to 0 disables the routing paths for the record signal
path, which goes from the sound engine to the serial port output.
Setting this bit to 0 disables the ADCs and the digital microphone inputs.
Bit 2, Serial Input Routing
Bit 6, Memory Controller
Setting this bit to 0 disables all memory access, which disables
the sound engine, ADCs, and DACs, as well as prohibits memory
access via the control port.
Setting this bit to 0 disables the routing paths for the playback signal path, which goes from the serial input ports to the
sound engine.
Bit 1, Serial Port, ADC, DAC, and Frame Pulse Clock
Generator
Setting this bit to 0—in conjunction with Bit 4, serial ports—
disables the serial ports.
Setting this bit to 0 disables the internal clock generator, which
generates all master clocks for the serial ports, sound engine,
ADCs, and DACs. This bit must be enabled if audio is being
passed through the ADAU1381.
Bit 4, Serial Ports
Bit 0, Sound Engine
Setting this bit to 0—in conjunction with Bit 5, clock domain
transfer—disables the serial ports.
Setting this bit to 0 disables the sound engine and makes the
memory inaccessible. This bit must be enabled in order to
process audio and change parameter values.
Bit 5, Clock Domain Transfer
Table 65. Digital Power-Down 0 Register
Bit
7
6
5
4
3
2
1
0
Description
ADC engine
0: disabled
1: enabled
Memory controller
0: disabled
1: enabled
Clock domain transfer (when using the serial ports)
0: disabled
1: enabled
Serial ports
0: disabled
1: enabled
Serial output routing
0: disabled
1: enabled
Serial input routing
0: disabled
1: enabled
Serial port, ADC, DAC, and frame pulse clock generator
0: disabled
1: enabled
Sound engine
0: disabled
1: enabled
Rev. B | Page 77 of 84
Default
0
0
0
0
0
0
0
0
ADAU1381
Register 16513 (0x4081), Digital Power-Down 1
Bit 3, Output Precharge
Bit 1, Digital Microphone
The output precharge system allows the outputs to be biased before
they are enabled and prevents pops or clicks from appearing on
the output. This bit should be set to 1 at all times.
Bit 0, DAC Engine
Setting this bit to 0 disables the digital microphone input.
Setting this bit to 0 disables the DACs.
Bit 2, Zero-Crossing Detector
Setting this bit to 0 disables the zero-crossing detector for beep
playback.
Table 66. Digital Power-Down 1 Register
Bits
[7:4]
3
2
1
0
Description
Reserved
Output precharge
0: disabled
1: enabled
Zero-crossing detector
0: disabled
1: enabled
Digital microphone
0: disabled
1: enabled
DAC engine
0: disabled
1: enabled
Default
1
1
0
0
Rev. B | Page 78 of 84
ADAU1381
The GPIO pin can be set directly by the sound engine and therefore
should be set as 1011 or 1100 (outputs set by the sound engine).
In order for GPIO0 through GPIO3 to be used, they should be
configured as 1001 or 1010 (outputs set by the I2C/SPI port).
Register 16582 to Register 16586 (0x40C6 to 0x40CA),
GPIO Pin Control
Bits[3:0], GPIO Pin Function
The GPIO pin control register sets the functionality of each
GPIO pin as depicted in Table 68. GPIO0 to GPIO3 use the
same pins as the serial port and must be enabled in Register
16628 (0x40F4), serial data/GPIO pin configuration. Pin 7 is
a dedicated GPIO.
There are five GPIO pin value registers that allow the input/output
data value of the GPIO pin to be written to or read directly from
the control port. The corresponding addresses are listed in Table 69.
Each value register contains four bytes and can store only one of
two values: logic high or logic low. Logic high is stored as 0x00,
0x80, 0x00, 0x00. Logic low is stored as 0x00, 0x00, 0x00, 0x00.
Table 67. GPIO Pin Control Register
Decimal
16582
Address
Hex
0x40C6
Register
GPIO pin control
16583
0x40C7
GPIO0 control
16584
0x40C8
GPIO1 control
16585
0x40C9
GPIO2 control
16586
0x40CA
GPIO3 control
Bits
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
Description
Reserved
Dedicated GPIO (Pin 7) function (see Table 68)
Reserved
GPIO0 pin function (see Table 68)
Reserved
GPIO1 pin function (see Table 68)
Reserved
GPIO2 pin function (see Table 68)
Reserved
GPIO3 pin function (see Table 68)
Table 68. GPIO Pin Functions
GPIO Bits[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
GPIO Pin Function
Input without debounce
Input with debounce (0.3 ms)
Input with debounce (0.6 ms)
Input with debounce (0.9 ms)
Input with debounce (5 ms)
Input with debounce (10 ms)
Input with debounce (20 ms)
Input with debounce (40 ms)
Input controlled by I2C/SPI port
Output set by I2C/SPI port with pull-up
Output set by I2C/SPI port without pull-up
Output set by engine with pull-up
Output set by engine without pull-up
Reserved
Output CRC error (sticky)
Output watchdog error (sticky)
Register 1000 to Register 1004 (0x03E8 to 0x03EC), GPIO Pin Value
Table 69. Addresses of GPIO Pin Value Registers
Decimal
1000
1001
1002
1003
1004
Address
Hex
0x03E8
0x03E9
0x03EA
0x03EB
0x03EC
Register
GPIO pin value, GPIO
GPIO pin value, GPIO0
GPIO pin value, GPIO1
GPIO pin value, GPIO2
GPIO pin value, GPIO3
Rev. B | Page 79 of 84
Default
1100
1100
1100
1100
1100
ADAU1381
Register 16617 and Register 16618 (0x40E9 and 0x40EA),
Nonmodulo
Register 16619 (0x40EB), Sound Engine Frame Rate
Bits[3:0], Sound Engine Frame Rate
These registers set the boundary for the nonmodulo RAM space
used by the sound engine. An appropriate value is automatically
loaded to this register during initialization. It should not be
modified for any reason.
These bits set the frequency of the frame start pulse, which is
delivered to the sound engine to begin processing on each audio
frame. It effectively determines the sample rate of audio in the
sound engine. This register should always be set to none at least
one frame prior to disabling Register 16630 (0x40F6), sound
engine run, Bit 0, sound engine run, to allow the sound engine
to finish processing the current frame before halting.
Table 70. Nonmodulo Registers
Bits
[31:0]
Description
Reserved
Table 71. Sound Engine Frame Rate Register
Bits
[7:4]
[3:0]
Description
Reserved
Sound engine frame rate
0000: fS × 2 (96 kHz)
0001: fS (48 kHz)
0010: fS/1.5 (32 kHz)
0011: fS/2 (24 kHz)
0100: fS/3 (16 kHz)
0101: fS/4 (12 kHz)
0110: fS/6 (8 kHz)
0111: serial data input rate
1000: serial data output rate
1001: fS × 4 (192 kHz)
1010: none
…
1111: none
Default
0000
Rev. B | Page 80 of 84
ADAU1381
Register 16626 (0x40F2), Serial Input Route Control
Bits[3:0], Input Routing
These bits select which serial data input channels are routed to the DACs (see Figure 72).
Table 72. Serial Input Route Control Register
Bits
[7:4]
[3:0]
1
Description
Reserved
Input routing
0000: serial input to sound engine to DACs
0001: serial input [L0, R0] 1 to DACs [L, R]
0010: reserved
0011: serial input [L1, R1]1 to DACs [L, R]
0100: reserved
0101: serial input [L2, R2]1 to DACs [L, R]
0110: reserved
0111: serial input [L3, R3]1 to DACs [L, R]
1000: reserved
1001: serial input [R0, L0]1 to DACs [L, R]
1010: reserved
1011: serial input [R1, L1]1 to DACs [L, R]
1100: reserved
1101: serial input [R2, L2]1 to DACs [L, R]
1110: reserved
1111: serial input [R3, L3]1 to DACs [L, R]
Default
0000
Lx = left side of Channel x; Rx = right side of Channel x.
Rev. B | Page 81 of 84
ADAU1381
Register 16627 (0x40F3), Serial Output Route Control
Bits[3:0], Output Routing
These bits select where the ADC outputs are routed in the serial data stream (see Figure 72).
Table 73. Serial Output Route Control Register
Bits
[7:4]
[3:0]
Default
0000
Lx = left side of Channel x; Rx = right side of Channel x.
1/fLRCLK
LRCLK
L0
STEREO CHANNELS
L0
TDM 4 CHANNELS
TDM 8 CHANNELS
R0
L0
R0
R0
L1
L1
R1
L2
Figure 72. Serial Port Routing Control
Rev. B | Page 82 of 84
R1
R2
L3
R3
08313-070
1
Description
Reserved
Output routing
0000: ADCs to sound engine to serial outputs
0001: ADCs [L, R] to serial output [L0, R0] 1
0010: reserved
0011: ADCs [L, R] to serial output [L1, R1]1
0100: reserved
0101: ADCs [L, R] to serial output [L2, R2]1
0110: reserved
0111: ADCs [L, R] to serial output [L3, R3]1
1000: reserved
1001: ADCs [L, R] to serial output [R0, L0]1
1010: reserved
1011: ADCs [L, R] to serial output [R1, L1]1
1100: reserved
1101: ADCs [L, R] to serial output [R2, L2]1
1110: reserved
1111: ADCs [L, R] to serial output [R3, L3]1
ADAU1381
Register 16628 (0x40F4), Serial Data/GPIO Pin
Configuration
Bits[3:0], GPIO[0:3]
Before going into standby mode, the following sequence must
be performed:
1.
The serial data/GPIO pin configuration register controls the
functionality of the serial data port pins. If the bits in this
register are set to 1, then the GPIO[0:3] pins become GPIO
interfaces to the sound engine. If these bits are set to 0, they
remain LRCLK, BCLK, or serial port data pins, respectively.
2.
3.
Set the sound engine frame rate in Register 16619 to
0x7F (none).
Wait 3 ms.
Set the sound engine run bit in Register 16630 to 0x00.
When reenabling the sound engine run bit, the following
sequence must be followed:
Register 16630 (0x40F6), Sound Engine Run
Bit 0, Sound Engine Run
1.
This bit, in conjunction with the sound engine frame rate, initiates
audio processing in the sound engine. When this bit is enabled,
the program counter begins to increment when a new frame of
audio data is input to the sound engine. When this bit is disabled,
the sound engine goes into standby mode.
2.
Set the sound engine frame rate in Register 16619 to an
appropriate value.
Set the sound engine run bit in Register 16630 to 0x01.
Register 16632 (0x40F8), Serial Port Sampling Rate
Bits[2:0], Serial Port Control Sampling Rate
These bits set the serial port sampling rate as a function of the
audio sampling rate, fS. In most applications, the serial port
sampling rate, sound engine sampling rate, and ADC and DAC
sampling rates should be equal.
Table 74. Serial Data/GPIO Pin Configuration Register
Bits
[7:4]
3
2
1
0
Description
Reserved
GPIO0
0: LRCLK
1: GPIO enabled
GPIO1
0: BCLK
1: GPIO enabled
GPIO2
0: serial data output
1: GPIO enabled
GPIO3
0: serial data input
1: GPIO enabled
Default
0
0
0
0
Table 75. Sound Engine Run Register
Bits
[7:1]
0
Description
Reserved
Sound engine run
0: sound engine standby
1: run the sound engine
Default
0
Table 76. Serial Port Sampling Rate Register
Bits
[7:3]
[2:0]
Description
Reserved
Serial port control sampling rate
000: fS/1 (48 kHz)
001: fS/6 (8 kHz)
010: fS/4 (12 kHz)
011: fS/3 (16 kHz)
100: fS/2 (24 kHz)
101: fS/1.5 (32 kHz)
110: fS/0.5 (96 kHz)
111: reserved
Default
000
Rev. B | Page 83 of 84
ADAU1381
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
25
24
PIN 1
INDICATOR
4.75
BSC SQ
EXPOSED
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
12° MAX
17
16
SEATING
PLANE
0.30
0.23
0.18
3.65
3.50 SQ
3.35
9
8
0.25 MIN
0.80 MAX
0.65 TYP
3.50 REF
0.05 MAX
0.02 NOM
1.00
0.85
0.80
1
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
100608-A
TOP
VIEW
0.50
BSC
32
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 73. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-4)
Dimensions shown in millimeters
0.650
0.595
0.540
3.44
3.40
3.36
SEATING
PLANE
6
5
4
3
2
1
A
BALL A1
IDENTIFIER
2.68
2.64
2.60
B
0.34
0.32
0.30
2.00
REF
C
D
E
0.50
BALL PITCH
TOP VIEW
(BALL SIDE DOWN)
BOTTOM VIEW
2.50 REF
082808-A
(BALL SIDE UP)
0.27
0.24
0.21
Figure 74. 30-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-30-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADAU1381BCPZ
ADAU1381BCPZ-RL
ADAU1381BCPZ-RL7
ADAU1381BCBZ-RL
ADAU1381BCBZ-RL7
EVAL-ADAU1381Z
1
Temperature Range
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
Package Description
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ, 13” Tape and Reel
32-Lead LFCSP_VQ, 7” Tape and Reel
30-Ball WLCSP, 13” Tape and Reel
30-Ball WLCSP, 7” Tape and Reel
Evaluation Board
Package Option
CP-32-4
CP-32-4
CP-32-4
CB-30-2
CB-30-2
Z = RoHS Compliant Part.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08313-0-1/11(B)
Rev. B | Page 84 of 84
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