ECE351 Digital Systems Design, Spring 2016 Lab 3

ECE351 Digital Systems Design, Spring 2016
Lab 3
This lab will create a design to demonstrate using the VGA controller on the Basys2
board. The design will utilize a VHDL VGA interface module provided by Digilent to
control the VGA port, and will create a checkerboard pattern on an attached monitor with
a highlighted square that can be moved by the buttons. The detailed instructions about
how to operate the VGA interface and connector on the Basys2 board can be found at:
http://web.eecs.utk.edu/~weigao/ece351/spring2016/VGA_RefComp.zip.
Task 1 (30%):
Develop a block diagram of the VGA interface module. Before using the block diagram,
you should understand its operation by creating a simple block diagram of its VHDL
code. The block diagram should be similar in complexity to those presented in class. This
block diagram can be hand-drawn, and should be turned in with your VHDL code
developed for Task 2.
Task 2 (70%):
Below is an image of the VGA output expected for this lab. Using the VGA interface
module, create a “checkerboard” pattern with 20 columns and 15 rows. The blocks
should alternate green, blue, green, etc., as shown in the picture.
Figure 1: Image of the lab assignment – VGA output
In addition, one block should be highlighted red. The red highlighted block can be moved
by the pushbuttons around the screen.
If the highlighted block reaches an edge of the screen, it should wrap around to the other
edge. In addition to highlighting the screen, a light should blink from LED0 to LED7
(and then loop back to LED0), moving from one LED to the next each second.
Describing this in a different way, a light should “walk” across the LEDs at a rate of one
LED per second (only one LED should be highlighted at any time) and should loop
around when the edge is reached. The timing for this should be derived from the VGA
timing. That is, since you know that the screen is rewritten 60 times per second (since the
refresh rate of the module is 60 Hz), you should move the LED every time the screen is
refreshed 60 seconds.
Switch0 will be used as a reset.
A summary of the expected inputs and outputs of this task is as follows:
Users Inputs:
• Switch0: Active high reset.
• Button0: Move the highlighted block up. The block should only move once for
each button press.
• Button1: Move the highlighted block down. The block should only move once for
each button press.
• Button2: Move the highlighted block right. The block should only move once for
each button press.
• Button3: Move the highlighted block left. The block should only move once for
each button press.
Outputs:
• VGA Port: See Figure 1.
• LEDs: A light should walk across the LEDs at the rate of one LED per second.
The timing should be derived from the timing created by the VGA module.
Some Notes:
1) Your implemented design should only be one VHDL file, not including the
provided VGA module. The top level file should only include one
entity/architecture pair. In addition, you should have a testbench VHDL file.
2) Read the section in the Basys2 manual describing the operation of the VGA
module before beginning this lab!
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