Si4706-D50 High-Performance FM and RDS/RBDS Receiver

Si4706-D50 High-Performance FM and RDS/RBDS Receiver
Si 4 7 0 6 - D50
H I G H - P ERFORMANCE FM A N D RDS/RBDS R ECEIVER
Features











Automatic gain control (AGC)
Integrated FM LNA
Image-rejection mixer
Frequency synthesizer with
integrated VCO
Low-IF direct conversion with no
external ceramic filters
2.7 to 5.5 V supply voltage
Dual 1.8 and 2.7 V power supplies
Stereo audio out
I2S Digital audio out
 20-pin 3 x 3 mm QFN package
Pb-free/RoHS compliant
Ordering Information:
See page 29.

Pin Assignments
Si4706-GM
Applications
(Top View)


Personal navigation devices (PND)
 GPS-enabled handsets and portable
devices
NC
Cellular handsets
 Portable media devices
 Dedicated data receiver
Description
NC 1
20 19 18 17 16
FMI 2
Si4706
Half-wavelength
antenna
FMI
Embedded
antenna
ADC
LNA
PGA
DAC
LOUT
DAC
ROUT
DSP
LPI
ADC
RFGND
0/90
AFC
SEN
GPO
DCLK
DOUT
LPI 4
13 ROUT
8
9
10 11 VA
VD
7
RCLK
12 GND
6
SDIO
RST 5
This product, its features, and/or its
architecture is covered by one or
more of the following patents, as well
as other patents, pending and
issued, both foreign and domestic:
7,127,217; 7,272,373; 7,272,375;
7,321,324; 7,355,476; 7,426,376;
7,471,940; 7,339,503; 7,339,504.
DFS
VD
CONTROL
INTERFACE
XTAL
OSC
RST
VA
REG
Rev. 1.0 7/10
RDS
SDIO
2.7–5.5 V
RSSI
SCLK
32.768 kHz (TYP)
RCLK
DIGITAL INTERFACE
AGC
14 LOUT
GND
PAD
SEN
Functional Block Diagram
15 DOUT
RFGND 3
SCLK
The Si4706-D50 FM/RDS/RDBS receiver provides the highest performance and
lowest power consumption available for portable devices today. The 100% CMOS
IC integrates the complete FM and data receiver function from antenna to analog
or digital audio and data out in a single 3 x 3 mm 20-pin QFN.
DFS


GPO3/DCLK


GPO2/INT

Worldwide FM band support
(76–108 MHz)
Advanced patented RDS/RBDS
decoding engine
Lowest power consumption
Outstanding RDS sensitivity,
synchronization, and reliability
Received signal quality indicators
On-chip tuned resonance for
embedded antenna support
Multipath detection and mitigation
FM Hi-cut control
Advanced FM stereo-mono blend
GPO1

Copyright © 2010 by Silicon Laboratories
Si4706-D50
Si4706-D50
2
Rev. 1.0
Si4706-D50
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.3. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4. Received Signal Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.7. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8. FM Hi-Cut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.9. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.10. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.11. Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.12. Embedded Antenna Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.13. RDS Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.14. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.15. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.16. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.17. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.18. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6. Pin Descriptions: Si4706-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8. Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.1. Si4706 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9. Package Outline: Si4706 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10. PCB Land Pattern: Si4706 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Rev. 1.0
3
Si4706-D50
1. Electrical Specifications
Table 1. Recommended Operating Conditions*
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Analog Supply Voltage
VA
2.7
—
5.5
V
Digital and Interface Supply Voltage
VD
1.62
—
3.6
V
Analog Power Supply Powerup Rise Time
VARISE
10
—
—
µs
Digital Power Supply Powerup Rise Time
VDRISE
10
—
—
µs
TA
–20
25
85
C
Ambient Temperature
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VA = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Symbol
Value
Unit
Analog Supply Voltage
VA
–0.5 to 5.8
V
Digital and Interface Supply Voltage
VD
–0.5 to 3.9
V
3
Input Current
IIN
10
mA
Input Voltage3
VIN
–0.3 to (VIO + 0.3)
V
Operating Temperature
TOP
–40 to 95
C
Storage Temperature
TSTG
–55 to 150
C
0.4
VpK
RF Input Level
4
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4706 device is a high-performance RF integrated circuit with certain pins having an ESD rating of < 2 kV HBM.
Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins DFS, SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2, and GPO3.
4. At RF input pins FMI and LPI.
4
Rev. 1.0
Si4706-D50
Table 3. DC Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
IFMVA
Digital Output Mode
—
7.5
8.6
mA
Analog Output Mode
—
8.8
9.7
mA
FM Receiver to Line Output
VASupply Current
VA Supply Current
VD Supply Current
IFMID
Digital Output Mode
—
8.5
11.1
mA
VD Supply Current
IFMID
Analog Output Mode
—
8.4
11.1
mA
—
4
15
µA
—
3
10
µA
Supplies and Interface
VA Powerdown Current
IDDPD
VD Powerdown Current
IIOPD
SCLK, RCLK inactive
1
VIH
0.7 x VD
—
VD + 0.3
V
Low Level Input Voltage1
VIL
–0.3
—
0.3 x VD
V
1
IIH
VIN = VD = 3.6 V
–10
—
10
µA
Low Level Input Current1
IIL
VIN = 0 V,
VD = 3.6 V
–10
—
10
µA
High Level Output Voltage2
VOH
IOUT = 500 µA
0.8 x VD
—
—
V
Low Level Output Voltage2
VOL
IOUT = –500 µA
—
—
0.2 x VD
V
High Level Input Voltage
High Level Input Current
Notes:
1. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
2. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
Rev. 1.0
5
Si4706-D50
Table 4. Reset Timing Characteristics1,2,3
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Unit
RST Pulse Width and GPO1, GPO2/INT Setup to RST
tSRST
100
—
—
µs
GPO1, GPO2/INT Hold from RST
tHRST
30
—
—
ns
Important Notes:
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is high
impedance, then minimum tSRST is 100 µs to provide time for on-chip 1 M devices (active while RST is low) to pull
GPO1 high and GPO2 low.
tSRST
RST
70%
GPO1
70%
GPO2
70%
tHRST
30%
30%
30%
Figure 1. Reset Timing Parameters for Busmode Select Method
6
Rev. 1.0
Si4706-D50
Table 5. 2-Wire Control Interface Characteristics1,2,3
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fSCL
0
—
400
kHz
SCLK Low Time
tLOW
1.3
—
—
µs
SCLK High Time
tHIGH
0.6
—
—
µs
SCLK Input to SDIO  Setup
(START)
tSU:STA
0.6
—
—
µs
SCLK Input to SDIO  Hold
(START)
tHD:STA
0.6
—
—
µs
SDIO Input to SCLK  Setup
tSU:DAT
100
—
—
ns
SDIO Input to SCLK  Hold 4, 5
tHD:DAT
0
—
900
ns
SCLK Input to SDIO  Setup
(STOP)
tSU:STO
0.6
—
—
µs
STOP to START Time
tBUF
1.3
—
—
µs
SDIO Output Fall Time
tf:OUT
—
250
ns
—
300
ns
Cb
20 + 0.1 ----------1pF
SDIO Input, SCLK Rise/Fall Time
tf:IN
tr:IN
Cb
20 + 0.1 ----------1pF
SCLK, SDIO Capacitive Loading
Cb
—
—
50
pF
Input Filter Pulse Suppression
tSP
—
—
50
ns
Notes:
1. When VD = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si4706 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum tHD:DAT
specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 kHz, tHD:DAT may be violated
as long as all other timing parameters are met.
Rev. 1.0
7
Si4706-D50
SCLK
70%
SDIO
70%
tSU:STA tHD:STA
tLOW
START
tr:IN
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
30%
30%
tf:IN,
tf:OUT
tHD:DAT tSU:DAT
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
A6-A0,
R/W
SDIO
START
ADDRESS + R/W
D7-D0
ACK
DATA
D7-D0
ACK
DATA
ACK
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
8
Rev. 1.0
STOP
Si4706-D50
Table 6. 3-Wire Control Interface Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fCLK
0
—
2.5
MHz
SCLK High Time
tHIGH
25
—
—
ns
SCLK Low Time
tLOW
25
—
—
ns
tS
20
—
—
ns
SDIO Input to SCLK Hold
tHSDIO
10
—
—
ns
SEN Input to SCLK Hold
tHSEN
10
—
—
ns
SCLK to SDIO Output Valid
tCDV
Read
2
—
25
ns
SCLK to SDIO Output High Z
tCDZ
Read
2
—
25
ns
SCLK, SEN, SDIO, Rise/Fall Time
tR, tF
—
—
10
ns
SDIO Input, SEN to SCLK Setup
SCLK
70%
30%
tR
tF
tHSDIO
tS
SEN
70%
SDIO
70%
tHIGH
tLOW
tHSEN
tS
30%
A7
30%
A6-A5,
R/W,
A4-A1
A0
D15
D14-D1
Address In
D0
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
SCLK
70%
SEN
70%
30%
tHSDIO
tS
tCDV
tHSEN
tCDZ
tS
30%
70%
SDIO
A7
30%
A6-A5,
R/W,
A4-A1
Address In
A0
D15
½ Cycle Bus
Turnaround
D14-D1
D0
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
Rev. 1.0
9
Si4706-D50
Table 7. Digital Audio Interface Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
DCLK Cycle Time
tDCT
26
—
1000
ns
DCLK Pulse Width High
tDCH
10
—
—
ns
DCLK Pulse Width Low
tDCL
10
—
—
ns
DFS Setup Time to DCLK Rising Edge
tSU:DFS
5
—
—
ns
DFS Hold Time from DCLK Rising Edge
tHD:DFS
5
—
—
ns
tPD:DOUT
0
—
12
ns
DOUT Propagation Delay from DCLK Falling
Edge
tDCH
tDCL
DCLK
tDCT
DFS
tHD:DFS
tSU:DFS
DOUT
tPD:OUT
Figure 6. Digital Audio Interface Timing Parameters, I2S Mode
10
Rev. 1.0
Si4706-D50
Table 8. FM Receiver Characteristics1,2
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C, 76–108 MHz)
Parameter
Symbol
Min
Typ
Max
Unit
76
—
108
MHz
f = 2 kHz,
RDS BLER < 5%
—
8
—
µV EMF
RDS Synchronization Persistence3,4
f = 2 kHz
RDSSYNC = 1  10 sec
—
3.8/60
—
µV
EMF/RDS
BLER%
RDS Synchronization Stability3,4
f = 2 kHz
RDSSYNC = 1  10 sec
—
5.9/10
—
µV EMF/
RDS
BLER%
RDS Synchronization Time3,4,5
f = 2 kHz
—
40
—
ms
f = 2 kHz
—
60
—
ms
3
4
5
k
4
5
6
pF
100
105
—
dBµV EMF
—
40
—
dB
m = 0.3
40
50
—
dB
Audio Sensitivity4,6,7
(S+N)/N = 26 dB
—
2.2
3.5
µV EMF
Audio Sensitivity with 50  Network3,6,7
(S+N)/N = 26 dB
—
1.1
—
µV EMF
—
3.5
—
µV EMF
Input Frequency
fRF
RDS Sensitivity3,4
RDS PI Lock Time
LNA Input
Test Condition
3,4,5,6
Resistance3
LNA Input Capacitance3
Input IP3
3
400 and 800 kHz
blockers, AGC disabled
Image Rejection3
AM Suppression3
LPI Sensitivity3
Adjacent Channel Selectivity
±200 kHz
35
50
—
dB
Alternate Channel Selectivity
±400 kHz
60
70
—
dB
f = ±400 kHz
—
34
—
dBµV
f = ±4 MHz
—
30
—
dBµV
3,8,9,10
Blocking Sensitivity
Notes:
1. Additional testing information is available in application note, “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test
Procedure.” Volume = maximum for all tests. Tested at RF = 98.5 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN332: Si47xx Programming Guide”,
and “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines”. Silicon Laboratories will evaluate
schematics and layouts for qualified customers.
3. Guaranteed by characterization.
4. Half-wavelength FM antenna matching network.
5. VEMF = 1 mV.
6. f = 22.5 kHz.
7. BAF = 300 Hz to 15 kHz, A-weighted.
8. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
9. Blocker Amplitude = 100 dBµV
10. Sensitivity measured at (S+N)/N = 26 dB.
11. f = 75 kHz.
12. At temperature 25 °C.
Rev. 1.0
11
Si4706-D50
Table 8. FM Receiver Characteristics1,2 (Continued)
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C, 76–108 MHz)
Parameter
Symbol
Intermod Sensitivity3,6,7,8,9,10
Spurious Response Rejection3
Test Condition
Min
Typ
Max
Unit
f1 = ±400 kHz
f2 = ±800 kHz
—
40
—
dBµV
f1 = ±4 MHz
f2 = ±8 MHz
—
35
—
µV EMF
In-band
35
—
—
dB
72
80
90
mVRMS
6
Audio Output Voltage
Audio Output L/R Imbalance
Mono
–1
—
1
dB
Audio Frequency Response Low3
–3 dB
—
—
30
Hz
Audio Frequency Response High3
–3 dB
15
—
—
kHz
35
40
—
dB
55
63
—
dB
—
58
—
dB
—
0.1
0.5
%
FM_DEEMPHASIS = 2
70
75
80
µs
FM_DEEMPHASIS = 1
45
50
54
µs
Audio Stereo
Separation5,6
Audio Mono S/N
5,6,7
Audio Stereo S/N5,6,7
Audio THD5,11
3
De-emphasis Time Constant
Audio Output Load Resistance3
RL
Single-ended, at
LOUT/ROUT pins
10
—
—
k
Audio Output Load Capacitance3
CL
Single-ended, at
LOUT/ROUT pins
—
—
50
pF
RCLK tolerance
= 100 ppm
—
—
60
ms/channel
From powerdown
—
—
110
ms
Input levels of 8 and
60 dBµV at RF Input
–3
—
3
dB
Seek/Tune Time3
Powerup Time3
RSSI
Offset12
Notes:
1. Additional testing information is available in application note, “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test
Procedure.” Volume = maximum for all tests. Tested at RF = 98.5 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN332: Si47xx Programming Guide”,
and “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines”. Silicon Laboratories will evaluate
schematics and layouts for qualified customers.
3. Guaranteed by characterization.
4. Half-wavelength FM antenna matching network.
5. VEMF = 1 mV.
6. f = 22.5 kHz.
7. BAF = 300 Hz to 15 kHz, A-weighted.
8. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
9. Blocker Amplitude = 100 dBµV
10. Sensitivity measured at (S+N)/N = 26 dB.
11. f = 75 kHz.
12. At temperature 25 °C.
12
Rev. 1.0
Si4706-D50
Table 9. 64–75.9 MHz Input Frequency FM Receiver Characteristics1,2,3
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Unit
64
—
75.9
MHz
—
4
—
µV EMF
3
4
5
k
4
5
6
pF
—
105
—
dBµV EMF
m = 0.3
40
50
—
dB
Adjacent Channel Selectivity
±200 kHz
—
50
—
dB
Alternate Channel Selectivity
±400 kHz
—
70
—
dB
Audio Output Voltage4,5,7
72
80
90
mVRMS
Audio Output L/R Imbalance5,7,8
—
—
1
dB
Input Frequency
fRF
Audio Sensitivity 3,4,5
LNA Input
Test Condition
(S+N)/N = 26 dB
Resistance5
5
LNA Input Capacitance
Input IP3
6
AM Suppression4,5,7
Audio Frequency Response Low
–3 dB
—
—
30
Hz
Audio Frequency Response High
–3 dB
15
—
—
kHz
Audio Mono S/N4,5,7,9,10
55
63
—
dB
Audio THD5,7,8
—
0.1
0.5
%
FM_DEEMPHASIS = 2
70
75
80
µs
FM_DEEMPHASIS = 1
45
50
54
µs
De-emphasis Time Constant
Audio Output Load Resistance10
RL
Single-ended
10
—
—
k
Audio Output Load Capacitance10
CL
Single-ended
—
—
50
pF
RCLK tolerance
= 100 ppm
—
—
60
ms/channel
From powerdown
—
—
110
ms
Input levels of 8 and
60 dBµV EMF
–3
—
3
dB
Seek/Tune Time
Powerup Time
11
RSSI Offset
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.5 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. Guaranteed by characterization.
4. f = 22.5 kHz.
5. VEMF = 1 mV.
6. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled.
7. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
8. f = 75 kHz.
9. BAF = 300 Hz to 15 kHz, A-weighted.
10. At LOUT and ROUT pins.
11. At temperature (25 °C).
Rev. 1.0
13
Si4706-D50
Table 10. Reference Clock and Crystal Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
31.130
32.768
40,000
kHz
–100
—
100
ppm
1
—
4095
31.130
32.768
34.406
kHz
—
32.768
—
kHz
–100
—
100
ppm
—
—
3.5
pF
Reference Clock
RCLK Supported Frequencies1,2
1,3
RCLK Frequency Tolerance
REFCLK_PRESCALE1,2
REFCLK
1
Crystal Oscillator
Crystal Oscillator Frequency
1
Crystal Frequency Tolerance1,3
Board Capacitance
1
Notes:
1. Guaranteed by characterization.
2. The Si4706 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies
between 31.130 kHz and 40 MHz that are not supported. See “AN332: Si47xx Programming Guide,” Table 6 for more
details.
3. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing.
14
Rev. 1.0
Si4706-D50
2. Typical Application Schematic
GPO1
GPO2/INT
FMI
LPI
NC
2 FMI
3 RFGND
4 LPI
5
19
18
GPO2/INT
17
GPO3/DCLK
DFS 16
1
GPO1
NC 20
R1
R2
U1
Si4706
DOUT
GPO3/DCLK
DFS
15 R3
DOUT
Optional: Digital Audio Output
LOUT
ROUT
GND
VA
RST
14
13
12
LOUT
ROUT
11
VBATTERY
2.7 to 5.5 V
RST
6
7
8
9
10
SEN
SCLK
SDIO
RCLK
VD
C1
X1
GPO3
SEN
SCLK
C4
SDIO
RCLK
VIO
1.62 to 3.6 V
C2
RCLK
C3
Optional: for crystal oscillator option
Notes:
1. Place C1 close to VA pin.
2. Pins 1 and 20 are no connects, leave floating.
3. Place C4 close to VD pin.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 or Pin 4 connects to the FM antenna interface. Pin 2 is for a half-wave antenna. Pin 4 is for an embedded antenna.
6. Place Si4706 as close as possible to antenna jack and keep the FMI and LPI traces as short as possible.
Rev. 1.0
15
Si4706-D50
3. Bill of Materials
Component(s)
Value/Description
Supplier
C1
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
Murata
C4
Supply bypass capacitor, 100 nF, ±10%, Z5U/X7R
Murata
U1
Si4706 FM Radio Receiver
Silicon Laboratories
Optional Components
C2, C3
16
Crystal load capacitors, 22 pF, ±5%, COG
(Optional: for crystal oscillator option)
Venkel
X1
32.768 kHz crystal (Optional: for crystal oscillator option)
Epson
R1
Resistor, 2 k(Optional: for digital audio)
Venkel
R2
Resistor, 2 k(Optional: for digital audio)
Venkel
R3
Resistor, 600 (Optional: for digital audio)
Venkel
Rev. 1.0
Si4706-D50
4. Functional Description
4.1. Overview
Si4706
Half-wavelength
antenna
FMI
Integrated
antenna
ADC
LNA
PGA
DAC
LOUT
DAC
ROUT
DSP
LPI
ADC
RFGND
0/90
RDS
GPO
DCLK
DOUT
DFS
VD
XTAL
OSC
SEN
REG
CONTROL
INTERFACE
RST
VA
SDIO
2.7–5.5 V
RSSI
AFC
SCLK
32.768 kHz (TYP)
RCLK
DIGITAL INTERFACE
AGC
Figure 7. Functional Block Diagram
The Si4706-D50 offers advanced audio processing plus
advanced RDS processing in a very small, 100%
CMOS receiver integrated circuit. The device provides
both analog and digital audio out, and a highly flexible
RDS pre-processor and 100 block RDS buffer. It is an
ideal product for handsets and portable devices seeking
to optimize both sound and data receiver performance.
For sound, the advanced audio processing is
unprecedented in portable devices. For RDS data
applications such as song-tagging, meta-data, traffic
message channel, or other open data applications, the
advanced and patented R(B)DS decoding engine offers
outstanding data synchronization and integrity. The
RDS engine includes demodulation, symbol decoding,
advanced error correction, detailed visibility to blockerror rates (BLER), advanced decoder reliability, and
synchronization status. The Si4706 provides complete,
decoded and error-corrected RDS groups (100 blocks),
up to 25 groups at a time. The Si4706 offers several
modes of operation for various applications which
require more or less visibility to the RDS status and
group data.
*Note: The term “RDS” will be used to mean “RDS/RBDS”
throughout the document.
The Si4706 receiver draws on Silicon Laboratories’
broadcast audio expertise and patent portfolio, using a
digital low intermediate frequency (low-IF) receiver
architecture proven by hundreds of millions of Silicon
Laboratories’ broadcast audio receivers shipped
worldwide.
Silicon Labs has shipped 1/2 billion broadcast audio
receivers worldwide using this architecture. The low-IF
architecture allows the Si4706 to deliver superior
performance while integrating the great majority of
external components required by competing solutions.
The Si4706 digital integration reduces the required
external components of traditional offerings, resulting in
a solution requiring only an external bypass capacitor
and occupying board space of approximately 15 mm2.
The Si4706 is the first FM radio receiver IC to support
embedded antenna technology, allowing the FM
antenna to be integrated into the enclosure or PCB of a
portable device. For portable navigation devices, the
Si4706 embedded antenna feature permits integration
of the FM antenna into the enclosure of the device and
eliminates the need for external antenna cables. Refer
to “AN383: Si47xx Antenna, Schematic, Layout, And
Design Guidelines” for antenna design guidelines.
Rev. 1.0
17
Si4706-D50
The Si4706 is feature-rich, providing highly automated
performance with default settings and extensive
programmability and flexibility for customized system
performance.
The Si4706 performs much of the FM demodulation
digitally to achieve high fidelity, optimal performance
versus power consumption, and flexibility of design. The
on-board DSP provides unmatched pilot rejection,
selectivity, and optimum sound quality. The integrated
micro-controller offers both the manufacturer and the
end-user unmatched programmability and flexibility in
the listening experience.
4.2. FM Receiver
The Si4706 FM receiver is based on the proven
Si4700/01/02/03 FM radio receiver. The part leverages
Silicon Laboratories' proven and patented FM broadcast
radio receiver digital architecture, delivering excellent RF
performance and interference rejection. The proven
digital techniques provide good sensitivity in weak signal
environments while allowing superb selectivity and intermodulation immunity in strong signal environments.
The part supports the worldwide FM broadcast band (64
to 108 MHz) with channel spacings of 50–200 kHz. The
low-IF architecture utilizes a single converter stage and
digitizes the signal using a high-resolution analog-todigital converter. The audio output can be directed
either to an external headphone amplifier via analog
in/out or to other system ICs through digital audio
interface (I2S).
4.3. Stereo Audio Processing
Modulation Level
The output of the FM demodulator is a stereo
multiplexed (MPX) signal. The MPX standard was
developed in 1961, and is used worldwide. Today's
MPX signal format consists of left + right (L+R) audio,
left – right (L–R) audio, a 19 kHz pilot tone, and
RDS/RBDS data as shown in Figure 8.
Mono Audio
Left + Right
0
Stereo
Pilot
15 19 23
Stereo Audio
Left - Right
38
Frequency (kHz)
Figure 8. MPX Signal Spectrum
18
RDS/
RBDS
53
57
4.3.1. Stereo Decoder
The Si4706 integrated stereo decoder automatically
decodes the MPX signal using DSP techniques. The 0–
15 kHz (L+R) signal is the mono output of the FM tuner.
Stereo is generated from the (L+R), (L–R), and a 19 kHz
pilot tone. The pilot tone is used as a reference to
recover the (L–R) signal. Output left and right channels
are obtained by adding and subtracting the (L+R) and
(L–R) signals, respectively.
4.3.2. Stereo-Mono Blending
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. Three metrics, received signal
strength indicator (RSSI), signal-to-noise ratio (SNR),
and
multipath
interference,
are
monitored
simultaneously in forcing a blend from stereo to mono.
The metric which reflects the minimum signal quality
takes precedence and the signal is blended
appropriately.
All three metrics have programmable stereo/mono
thresholds and attack/release rates detailed in “AN322:
Si47xx Programming Guide.” If a metric falls below its
mono threshold, the signal is blended from stereo to full
mono. If all metrics are above their respective stereo
thresholds, then no action is taken to blend the signal. If
a metric falls between its mono and stereo thresholds,
then the signal is blended to the level proportional to the
metric’s value between its mono and stereo thresholds,
with an associated attack and release rate.
Stereo/mono status can be monitored with the
FM_RSQ_STATUS command.
4.4. Received Signal Qualifiers
The quality of a tuned signal can vary depending on
many factors including environmental conditions, time of
day, and position of the antenna. To adequately manage
the audio output and avoid unpleasant audible effects to
the end-user, the Si4706-D50 monitors and provides
indicators of the signal quality, allowing the host
processor to perform additional processing if required
by the customer. The Si4706-D50 monitors signal
quality metrics including RSSI, SNR, and multipath
interference on FM signals. These metrics are used to
optimize signal processing and are also reported to the
host processor. The signal processing algorithms can
use
either
Silicon
Labs'
optimized
settings
(recommended) or be customized to modify
performance.
Rev. 1.0
Si4706-D50
4.5. De-emphasis
4.10. Seek
Pre-emphasis and de-emphasis is a technique used by
FM broadcasters to improve the signal-to-noise ratio of
FM receivers by reducing the effects of high-frequency
interference and noise. When the FM signal is
transmitted, a pre-emphasis filter is applied to
accentuate the high audio frequencies. The Si4706
incorporates a de-emphasis filter that attenuates high
frequencies to restore a flat frequency response. Two
time constants are used in various regions. The deemphasis time constant is programmable to 50 or 75 µs
and is set by the FM_DEEMPHASIS property.
The Si4706 seek functionality is performed completely
on-chip and will search up or down the selected
frequency band for a valid channel. A valid channel is
qualified according to a series of programmable signal
indicators and thresholds. The seek function can be
made to stop at the band edge and provide an interrupt,
or wrap the band and continue seeking until arriving at
the original departure frequency. The device sets
interrupts with found valid stations or, if the seek results
in zero found valid stations, the device indicates failure
and again sets an interrupt. Refer to “AN332: Si47xx
Programming Guide.”
The Si4706-D50 uses RSSI, SNR, and AFC to qualify
stations. Most of these variables have programmable
thresholds for modifying the seek function according to
customer needs.
4.6. Stereo DAC
High-fidelity stereo digital-to-analog converters (DACs)
drive analog audio signals onto the LOUT and ROUT
pins. The audio output may be muted. Volume is
adjusted digitally with the RX_VOLUME property.
4.7. Soft Mute
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal
conditions. The soft mute feature is triggered by the
SNR metric. The SNR threshold for activating soft mute
is programmable, as are soft mute attenuation levels
and attack and decay rates.
4.8. FM Hi-Cut Control
Hi-cut control is employed on audio outputs with
degradation of the signal due to low SNR and/or
multipath interference. Two metrics, SNR and multipath
interference, are monitored concurrently in forcing hi-cut
of the audio outputs. Programmable minimum and
maximum thresholds are available for both metrics. The
transition frequency for hi-cut is also programmable with
up to seven hi-cut filter settings. A single set of attack
and release rates for hi-cut are programmable for both
metrics from a range of 2 ms to 64 s. The level of hi-cut
applied can be monitored with the FM_RSQ_STATUS
command. Hi-cut can be disabled by setting the hi-cut
filter to the default audio bandwidth of 15 kHz.
RSSI is employed first to screen all possible candidate
stations. SNR and AFC are subsequently used in
screening the RSSI qualified stations. The more
thresholds the system engages, the higher the
confidence that any found stations will indeed be valid
broadcast stations; however, the more challenging
levels the thresholds are set to, the longer the overall
seek time as more stations and more qualifiers will be
assessed. The Si4706-D50 defaults set RSSI to a midlevel threshold and add an SNR threshold set to a level
delivering acceptable audio performance. This trade-off
will eliminate very low RSSI stations while keeping the
seek time to acceptable levels. Generally, the time to
auto-scan and store valid channels for an entire FM
band with all thresholds engaged is very short
depending on the band content.
Seek is initiated using the FM_SEEK_START
command. The RSSI and SNR threshold settings are
adjustable using properties.
4.9. Tuning
The frequency synthesizer uses Silicon Laboratories’
proven technology, including a completely integrated
VCO. The frequency synthesizer generates the
quadrature local oscillator signal used to downconvert
the RF input to a low intermediate frequency. The VCO
frequency is locked to the reference clock and adjusted
with an automatic frequency control (AFC) servo loop
during reception. The tuning frequency can be directly
programmed using the FM_TUNE_FREQ. The Si4706
supports channel spacing of 50, 100, or 200 kHz in FM
mode.
Rev. 1.0
19
Si4706-D50
4.11. Digital Audio Interface
4.11.2. Audio Sample Rates
The digital audio interface operates in slave mode and
supports a variety of MSB-first audio data formats
including I2S and left-justified modes. The interface has
three pins: digital data input (DIN), digital frame
synchronization input (DFS), and a digital bit
synchronization input clock (DCLK). The Si4706
supports a number of industry-standard sampling rates
including 32, 40, 44.1, and 48 kHz. The digital audio
interface enables low-power operation by eliminating
the need for redundant DACs and ADCs on the audio
baseband processor.
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.
4.11.1. Audio Data Formats
The digital audio interface operates in slave mode and
supports three different audio data formats:
I2S
 Left-Justified
 DSP Mode

In I2S mode, by default the MSB is captured on the
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
In left-justified mode, by default the MSB is captured on
the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
In DSP mode, the DFS becomes a pulse with a width of
1DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
In all audio formats, depending on the word size, DCLK
frequency, and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
captured on the falling edge of DCLK via properties.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
20
Rev. 1.0
Si4706-D50
(OFALL = 1)
INVERTED
DCLK
(OFALL = 0)
DCLK
LEFT CHANNEL
DFS
I2S
(OMODE = 0000)
RIGHT CHANNEL
1 DCLK
1 DCLK
1
DOUT
2
n-2
3
n-1
MSB
n
1
LSB
MSB
2
n-2
3
n-1
n
LSB
Figure 9. I2S Digital Audio Format
(OFALL = 1)
INVERTED
DCLK
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
RIGHT CHANNEL
Left-Justified
(OMODE = 0110)
1
DOUT
2
3
n-2
n-1
MSB
n
1
LSB
MSB
2
n-2
3
n-1
n
LSB
Figure 10. Left-Justified Digital Audio Format
(OFALL = 0)
DCLK
DFS
RIGHT CHANNEL
LEFT CHANNEL
(OMODE = 1100)
DOUT
(MSB at 1 rising edge)
1
st
2
3
n-2
n-1
MSB
(OMODE = 1000)
1
LSB
MSB
n-1
n
1
LSB
MSB
2
3
n-2
1
2
3
n-2
MSB
n-1
n
LSB
LEFT CHANNEL
1 DCLK
DOUT
(MSB at 2 rising edge)
nd
n
RIGHT CHANNEL
2
3
n-2
n-1
n
LSB
Figure 11. DSP Digital Audio Format
Rev. 1.0
21
Si4706-D50
4.12. Embedded Antenna Support
The Si4706 is the first FM receiver to support the fast
growing trend to integrate the FM receiver antenna into
the device enclosure. The chip is designed with this
function in mind from the outset, with multiple
international patents pending, thus it is superior to many
other options in price, board space, and performance.
Testing indicates that, when using Silicon Laboratories'
patented techniques, embedded antenna performance
can be very similar in many key metrics to a standard
half-wavelength antenna. Refer to “AN383: Si47xx
Antenna, Schematic, Layout, And Design Guidelines”
for additional details on the implementation of support
for an embedded antenna.
Figure 12 shows a conceptual block diagram of the
Si4706 architecture used to support the embedded
antenna. The half-wavelength FM receive antenna is
therefore optional. Host software can detect the
presence of an external antenna and switch between
the embedded antenna if desired.
Si4706
Half-wavelength
antenna
FMI
Integrated
antenna
LNA
LPI
RFGND
AGC
Figure 12. Conceptual Block Diagram of the Si4706 Embedded Antenna Support
22
Rev. 1.0
Si4706-D50
4.13. RDS Decoder
The Si4706 implements an advanced, patented, highperformance RDS processor for demodulation, symbol
decoding, block synchronization, error detection, and
error correction. The RDS decoder provides several
significant benefits over traditional implementations,
including very fast and robust RDS synchronization in
noisy signal levels with very high block error rates
(BLER), industry-leading sensitivity, and improved data
reliability in all signal environments.
Figure 13
illustrates
the
benefit
of
robust
synchronization. The Si4706's strong synchronization
performance at noisy signal levels minimizes or even
eliminates re-synchronization time required as the
signal carrier-to-noise ratio (CNR) fluctuates. The
Si4706 decoder is continuously synchronized to the
RDS block/group despite loss of data due to data block
errors. This translates to lower loss of data compared to
competing solutions.
Figure 14 illustrates the Si4706 RDS decoder
performance. With the aid of robust synchronization, the
decoder additionally provides for operation at lower
sensitivity levels for a given BLER compared to
competing solutions, and delivers reception in
environments where signal power is very low or
compromised. The decoder failure probability drops
Re-synchronization time in
typical RDS decoder using
hard decision techniques.
significantly when compared to competing solutions.
The Si4706 also provides unmatched flexibility in
programming the interaction between the host
processor and the device. The Si4706 can be
configured to provide varying levels of visibility from
very high visibility to each RDS block with
corresponding BLER, to a lower level of granularity
providing complete RDS groups with BLER by block.
Additionally, the Si4706 can provide interrupts on
changes to RDS block A and/or B. The Si4706 device
provides a configurable interrupt when RDS is
synchronized and RDS group data has been received.
The device provides configurable interrupts for up to
100 blocks with detailed BLER (25 groups), providing
flexibility in interrupt configuration to the host controller.
The Si4706 reports RDS decoder synchronization
status and detailed bit errors for each RDS block with
the FM_RDS_STATUS command. The range of
reportable bit errors that are detected and corrected are
0, 1-2, 3-5, and "not correctable." More than five bit
errors indicates that the corresponding block
information word is not correctable.
Si4706 RDS advanced decoder
with persistent synchronization
delivers data during “dead time.”
CNR
Level at which typical RDS decoder returns
block error and declares sync loss.
Level at which Si4706 advanced
RDS decoder declares sync loss.
time
Figure 13. Illustrative Si4706 Advanced RDS Synchronization
Rev. 1.0
23
Si4706-D50
Decoder Failure Probability
1.E+00
Probability
1.E-01
1.E-02
RDS Standard Limits
1.E-03
Si4706 RDS Decoder
1.E-04
0
1
2
3
4
5
6
Eb/N0
Figure 14. Si4706 Preliminary Decoder Performance
4.14. Reference Clock
The Si4706 reference clock is programmable,
supporting RCLK frequencies in Table 10. Refer to
Table 3, “DC Characteristics” on page 5 for switching
voltage levels and Table 10, “Reference Clock and
Crystal Characteristics” on page 14 for frequency
tolerance information.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to "2. Typical Application
Schematic" on page 15. This mode is enabled using the
POWER_UP command. Refer to Refer to “AN332:
Si47xx Programming Guide”.
24
The Si4706 performance may be affected by data
activity on the SDIO bus when using the integrated
internal oscillator. SDIO activity results from polling the
tuner for status or communicating with other devices
that share the SDIO bus. If there is SDIO bus activity
while the Si4706 is performing the seek/tune function,
the crystal oscillator may experience jitter, which may
result in mistunes, false stops, and/or lower SNR.
For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended
during Si4706 seek and tune operations. This is
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The seek/tune complete
(STC) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
Rev. 1.0
Si4706-D50
4.15. Control Interface
4.15.1. 2-Wire Control Interface Mode
A serial port slave interface is provided, which allows an
external controller to send commands to the Si4706 and
receive responses from the device. The serial port can
operate in two bus modes: 2-wire mode and 3-wire
mode. The Si4706 selects the bus mode by sampling
the state of the GPO1 and GPO2 pins on the rising
edge of RST. The GPO1 pin includes an internal pull-up
resistor, which is connected while RST is low, and the
GPO2 pin includes an internal pull-down resistor, which
is connected while RST is low. Therefore, it is only
necessary for the user to actively drive pins which differ
from these states. See Table 11.
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
Table 11. Bus Mode Select on Rising Edge of
RST
Bus Mode
GPO1
GPO2
2-Wire
1
0
3-Wire
0 (must drive)
0
After the rising edge of RST, the pins GPO1 and GPO2
are used as general purpose output (O) pins as
described in Section “4.16. GPO Outputs”. In any bus
mode, commands may only be sent after VIO and VDD
supplies are applied.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
The 2-wire bus mode uses only the SCLK and SDIO
pins for signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a 7-bit
device address, followed by a read/write bit (read = 1,
write = 0). The Si4706 acknowledges the control word
by driving SDIO low on the next falling edge of SCLK.
Although the Si4706 will respond to only a single device
address, this address can be changed with the SEN pin
(note that the SEN pin is not used for signaling in 2-wire
mode). When SEN = 0, the 7-bit device address is
0010001b. When SEN = 1, the address is 1100011b.
For write operations, the user then sends an 8-bit data
byte on SDIO, which is captured by the device on rising
edges of SCLK. The Si4706 acknowledges each data
byte by driving SDIO low for one cycle, on the next
falling edge of SCLK. The user may write up to 8 data
bytes in a single 2-wire transaction. The first byte is a
command, and the next seven bytes are arguments.
For read operations, after the Si4706 has
acknowledged the control byte, it will drive an 8-bit data
byte on SDIO, changing the state of SDIO on the falling
edge of SCLK. The user acknowledges each data byte
by driving SDIO low for one cycle, on the next falling
edge of SCLK. If a data byte is not acknowledged, the
transaction will end. The user may read up to 16 data
bytes in a single 2-wire transaction. These bytes contain
the response data from the Si4706.
A 2-wire transaction ends with the STOP condition,
which occurs when SDIO rises while SCLK is high. For
details on timing specifications and diagrams, refer to
Table 5, “2-Wire Control Interface Characteristics” on
page 7; Figure 2, “2-Wire Control Interface Read and
Write Timing Parameters,” on page 8, and Figure 3, “2Wire Control Interface Read and Write Timing Diagram,”
on page 8.
Rev. 1.0
25
Si4706-D50
4.15.2. 3-Wire Control Interface Mode
4.17. Reset, Powerup, and Powerdown
When selecting 3-wire mode, the user must ensure that
a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
Setting the RST pin low will disable analog and digital
circuitry, reset the registers to their default settings, and
disable the bus. Setting the RST pin high will bring the
device out of reset. A powerdown mode is available to
reduce power consumption when the part is idle. Putting
the device in powerdown mode will disable analog and
digital circuitry while keeping the bus active.
The 3-wire bus mode uses the SCLK, SDIO, and SEN_
pins. A transaction begins when the user drives SEN
low. Next, the user drives a 9-bit control word on SDIO,
which is captured by the device on rising edges of
SCLK. The control word consists of a 3-bit device
address (A7:A5 = 101b), a read/write bit (read = 1, write
= 0), and a 5-bit register address (A4:A0).
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turn-around. Next,
the Si4706 will drive the 16-bit read data word serially
on SDIO, changing the state of SDIO on each rising
edge of SCLK.
A transaction ends when the user sets SEN high, then
pulses SCLK high and low one final time. SCLK may
either stop or continue to toggle while SEN is high.
In 3-wire mode, commands are sent by first writing each
argument to register(s) 0xA1–0xA3, then writing the
command word to register 0xA0. A response is
retrieved by reading registers 0xA8–0xAF.
For details on timing specifications and diagrams, refer
to Table 6, “3-Wire Control Interface Characteristics” on
page 9; Figure 4, “3-Wire Control Interface Write Timing
Parameters,” on page 9, and Figure 5, “3-Wire Control
Interface Read Timing Parameters,” on page 9.
4.16. GPO Outputs
4.18. Programming with Commands
To ease development time and offer maximum
customization, the Si4706 provides a simple yet
powerful software interface to program the receiver. The
device is programmed using commands, arguments,
properties, and responses. To perform an action, the
user writes a command byte and associated arguments,
causing the chip to execute the given command.
Commands control an action such as powerup the
device, shut down the device, or tune to a station.
Arguments are specific to a given command and are
used to modify the command. A complete list of
commands is available in “AN332: Si47xx Programming
Guide”.
Properties are a special command argument used to
modify the default chip operation and are generally
configured immediately after powerup. Examples of
properties are de-emphasis level, RSSI seek threshold,
and soft mute attenuation threshold. Responses provide
the user information and are echoed after a command
and associated arguments are issued. All commands
provide a one-byte status update indicating interrupt
and clear-to-send status information. For a detailed
description of the commands and properties for the
Si4706, see “AN332: Si47xx Programming Guide”.
The Si4706 provides three general-purpose output pins.
The GPO pins can be configured to output a constant
low, constant high, or high-Z. The GPO pins are
multiplexed with the bus mode pins or DCLK,
depending on the application schematic of the device.
GPO2/INT can be configured to provide interrupts for
seek and tune complete, receive signal quality, and
RDS.
26
Rev. 1.0
Si4706-D50
5. Commands and Properties
Refer to “AN332: Si47xx Programming Guide”.
Rev. 1.0
27
Si4706-D50
NC 1
DFS
GPO3/DCLK
GPO2/INT
GPO1
NC
6. Pin Descriptions: Si4706-GM
20 19 18 17 16
FMI 2
15 DOUT
RFGND 3
14 LOUT
GND
PAD
LPI 4
13 ROUT
7
8
9
SDIO
RCLK
10 11 VA
VD
6
SCLK
12 GND
SEN
RST 5
Pin Number(s)
Name
1, 20
NC
No connect. Leave floating.
2
FMI
FM RF input.
3
RFGND
4
LPI
Loop antenna RF input.
5
RST
Device reset input (active low).
6
SEN
Serial enable input (active low).
7
SCLK
Serial clock input.
8
SDIO
Serial data input/output.
9
RCLK
External reference or crystal oscillator input.
10
VD
Digital and I/O supply voltage.
11
VA
Analog supply voltage. May be connected directly to battery.
13
ROUT
Right audio analog line output.
14
LOUT
Left audio analog line output.
15
DOUT
Digital audio output data.
16
DFS
17
GPO3/DCLK
18
GPO2/INT
19
GPO1
General purpose output.
12, GND PAD
GND
Ground. Connect to ground plane on PCB.
28
Description
RF ground. Connect to ground plane on PCB.
Digital frame synchronization.
General purpose output/digital bit synchronous clock or crystal oscillator
input.
General purpose output/interrupt.
Rev. 1.0
Si4706-D50
7. Ordering Guide
Part Number*
Si4706-D50-GM
Description
FM RDS Broadcast Radio Receiver
Package
Type
Operating
Temperature
QFN
Pb-free
–20 to 85 °C
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option.
Rev. 1.0
29
Si4706-D50
8. Package Markings
8.1. Si4706 Top Mark
0650
DTTT
YWW
Figure 15. Si4706 Top Mark
8.2. Top Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
Part Number
06 = Si4706
Firmware Revision
50 = Firmware Revision 50
R = Die Revision
D = Revision D Die
TTT = Internal Code
Internal tracking code
Line 2 Marking:
Line 3 Marking:
Circle = 0.5 mm Diameter Pin 1 Identifier
(Bottom-Left Justified)
Y = Year
WW = Workweek
30
Assigned by the Assembly House. Corresponds to the last
significant digit of the year and workweek of the mold date.
Rev. 1.0
Si4706-D50
9. Package Outline: Si4706 QFN
Figure 16 illustrates the package details for the Si4706. Table 12 lists the values for the dimensions shown in the
illustration.
Figure 16. 20-Pin Quad Flat No-Lead (QFN)
Table 12. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
Nom
Max
A
0.50
0.55
0.60
f
A1
0.00
0.02
0.05
L
0.35
0.40
0.45
b
0.18
0.25
0.30
L1
0.00
—
0.10
c
0.27
0.32
0.37
D
D2
3.00 BSC
1.60
e
1.70
1.80
0.50 BSC
E
E2
Min
3.00 BSC
1.60
1.70
Nom
Max
2.53 BSC
aaa
—
—
0.05
bbb
—
—
0.05
ccc
—
—
0.08
ddd
—
—
0.10
eee
—
—
0.10
1.80
Notes:
1. All dimensions are shown in millimeters unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
Rev. 1.0
31
Si4706-D50
10. PCB Land Pattern: Si4706 QFN
Figure 17 illustrates the PCB land pattern details for the Si4706-GM. Table 13 lists the values for the dimensions
shown in the illustration.
Figure 17. PCB Land Pattern
32
Rev. 1.0
Si4706-D50
Table 13. PCB Land Pattern Dimensions
Symbol
Millimeters
Min
D
D2
Symbol
Max
2.71 REF
Max
GE
2.10
—
W
—
0.34
0.50 BSC
X
—
0.28
E
2.71 REF
Y
f
GD
1.60
1.80
Min
e
E2
1.60
Millimeters
1.80
2.53 BSC
2.10
0.61 REF
ZE
—
3.31
ZD
—
3.31
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing is per the ANSI Y14.5M-1994 specification.
3. This land pattern design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at maximum material condition (MMC). Least material
condition (LMC) is calculated based on a fabrication allowance of 0.05 mm.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for small body components.
Rev. 1.0
33
Si4706-D50
11. Additional Reference Resources







34
Customer Support Site:
This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA
is required for complete access. Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support
request.
AN332: Si47xx Programming Guide
AN342: Quick Start Guide
AN383: Si47xx Antenna, Schematic, Layout and Design Guidelines
AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure
Si47xx EVB User’s Guide
Si4706-D50ER063010 Errata
Rev. 1.0
Si4706-D50
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2

Added line in Table 3 for VD supply current in Analog
Output Mode
 Split Table 8 into Table 8 covering 76–108 MHz, and
Table 9 covering 64–75.9 MHz
 Corrected Top Mark to show D revision instead of C
revision in sections 8.1 and 8.2
Revision 0.2 to Revision 1.0





Added maximum current consumption specs to
Table 3
Added LPI sensitivity spec to Table 8
Added Intermod sensitivity spec to Table 8
Added sensitivity specs to Table 8
Updated typical blocking sensitivity specs in Table 8
Rev. 1.0
35
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