HY62LF16206B

HY62LF16206B
HY62LF16206B-DT12C
128Kx16bit full CMOS SRAM
Document Title
128K x16 bit 2.5V Low Low Power Full CMOS Slow SRAM
Revision History
Revision No
History
Draft Date
Remark
00
Initial
Apr. 6. 2003
Final
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.00 /Apr. 2003
Hynix Semiconductor
HY62LF16206B-DT12C
128Kx16bit full CMOS SRAM
DESCRIPTION
FEATURES
The HY62LF16206B is a high speed, super low
power and 2Mbit full CMOS SRAM organized as
128K words by 16bits. The HY62LF16206B uses
high performance full CMOS process technology
and is designed for high speed and low power
circuit technology. It is particularly well-suited for
the high density low power system application.
This device has a data retention mode that
guarantees data to remain valid at a minimum
power supply voltage of 1.2V.
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Battery backup(L-part)
-. 1.2V(min) data retention
• Standard pin configuration
-. 48-TSOP1
Product
Voltage
No.
(V)
HY62LF16206B
2.3~2.7
Notes :
1. Current value is max.
Speed
(ns)
120
Operation
Current/Icc(mA)
1
PIN CONNECTION
ROW
DECODER
MEMORY ARRAY
128K x 16
A16
I/O16
CONTRO
L
LOGIC
/CS1
CS2
/OE
/LB
/UB
/WE
I/O1
DATA I/O
BUFFER
48-TSOP1(Forward)
A0
WRITE DRIVER
A16
NC
VSS
IO16
IO8
IO15
IO7
IO14
IO6
IO13
IO5
VCC
IO12
IO4
IO11
IO3
IO10
IO2
IO9
IO1
/OE
VSS
/CS1
A0
SENSE AMP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
COLUMNDECODER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Temperature
(°C)
0~70
BLOCK DIAGRAM
ADD INPUT BUFFER
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
/WE
CS2
NC
/UB
/LB
NC
NC
A7
A6
A5
A4
A3
A2
A1
Standby Current(uA)
D
20
PIN CONNECTION
Pin Name
/CS1
CS2
/WE
/OE
/LB
/UB
Pin Function
Chip Select 1
Chip Select 2
Write Enable
Output Enable
Lower Byte Control(I/O1~I/O8)
Upper Byte Control(I/O9~I/O16)
Pin Name
I/O1~I/O16
A0~A16
Vcc
Vss
NC
Pin Function
Data Inputs / Outputs
Address Inputs
Power(2.3V~2.7V)
Ground
No Connection
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.00 /Apr. 2003
Hynix Semiconductor
HY62LF16206B-DT12C
ORDERING INFORMATION
Part No.
HY62LF16206B-DT12C
Speed
120
Power
D-part
Temp.
0℃ ~ 70℃
Package
48-TSOP1
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VIN, VOUT
Vcc
TA
TSTG
PD
TSOLDER
Parameter
Input/Output Voltage
Power Supply
Operating Temperature
Storage Temperature
Power Dissipation
Ball Soldering Temperature & Time
Rating
-0.3 to 3.3
-0.3 to 3.3
0 to 70
-40 to 125
1.0
260 • 10
Unit
V
V
°C
°C
W
°C•se
c
Remark
Note :
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1
CS2
/WE
/OE
/LB
/UB
H
X
X
L
L
X
L
X
H
H
X
X
X
H
H
X
X
X
H
H
L
H
H
L
L
H
L
X
X
X
H
L
X
L
H
L
L
H
L
X
X
H
X
L
H
L
L
H
L
L
Mode
Deselected
Output Disabled
Read
Write
I/O1~I/O8
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
I/O
I/O9~I/O16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
Power
Standby
Active
Note:
1. H=VIH, L=VIL, X=don't care(Vil or Vih)
2. UB, LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8.
When UB is LOW, data is written or read to the upper byte, I/O 9 -I/O 16.
Rev.00 /Apr. 2003
2
HY62LF16206B-DT12C
RECOMMENDED DC OPERATING CONDITION
Symbol
Parameter
Min.
Vcc
Supply Voltage
2.3
Vss
Ground
0
VIH
Input High Voltage
2.0
VIL
Input Low Voltage
-0.3(1)
Note :
1. VIL = -1.5V for pulse width less than 30ns
Typ.
2.5
0
-
Max.
2.7
0
Vcc+0.3
0.4
Unit
V
V
V
V
DC ELECTRICAL CHARACTERISTICS
Vcc = 2.3V~2.7V, TA = 0°C to 70°C
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
Icc
ICC1
Operating Power Supply
Current
Average Operating
Current
ISB
Standby Current
(TTL Input)
ISB1
Standby Current
(CMOS Input)
Test Condition
Vss < VIN < Vcc
Vss < VOUT < Vcc, /CS1 = VIH or
CS2= VIL, /OE = VIH or /WE = VIL,
or /UB = /LB = VIH
/CS1 = VIL, CS2 = VIH,
VIN = VIH or VIL, II/O = 0mA
Cycle Time=Min.100% duty,
/CS1 = 0.2V, CS2 = Vcc-0.2V,
/WE = Vcc-0.2V, II/O = 0mA
Other Inputs = Vcc-0.2V/0.2V
Cycle time = 1us,
/CS1 < 0.2V, CS2≥Vcc-0.2V,
VIN<0.2V or Vin≥Vcc-0.2V,
II/O = 0mA
/CS1 = VIH, CS2 = VIL
/UB = /LB = VIH, VIN = VIH or VIL
/CS1 > Vcc - 0.2V or
CS2 < Vss+0.2V or
/UB = /LB > Vcc - 0.2V,
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
IOL = 1.0mA
IOH = -0.5mA
VOL
Output Low Voltage
VOH
Output High Voltage
Notes :
1. Typical values are at Vcc = 2.5V, TA = 25°C
2. Typical values are sampled and not 100% tested
Min.
-1
-1
Typ.
-
Max.
1
1
Unit
uA
uA
-
-
1
mA
-
-
5
mA
-
-
2
mA
-
-
0.3
mA
-
-
20
uA
1.8
-
0.4
-
V
V
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol
Parameter
Condition
CIN
Input Capacitance(Add, /CS, /WE, /OE)
VIN = 0V
COUT
Output Capacitance(I/O)
VI/O = 0V
Note :
1. These parameters are sampled and not 100% tested
Rev.00 /Apr. 2003
Max.
10
10
Unit
pF
pF
3
HY62LF16206B-DT12C
AC CHARACTERISTICS
Vcc = 2.3V~2.7V, TA = 0°C to 70°C, unless otherwise specified
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Symbol
Parameter
READ CYCLE
tRC
Read Cycle Time
tAA
Address Access Time
tACS
Chip Select Access Time
tOE
Output Enable to Output Valid
tBA
/LB, /UB Access Time
tCLZ
Chip Select to Output in Low Z
tOLZ
Output Enable to Output in Low Z
tBLZ
/LB, /UB Enable to Output in Low Z
tCHZ
Chip Deselection to Output in High Z
tOHZ
Out Disable to Output in High Z
tBHZ
/LB, /UB Disable to Output in High Z
tOH
Output Hold from Address Change
WRITE CYCLE
tWC
Write Cycle Time
tCW
Chip Selection to End of Write
tAW
Address Valid to End of Write
tBW
/LB, /UB Valid to End of Write
tAS
Address Set-up Time
tWP
Write Pulse Width
tWR
Write Recovery Time
tWHZ
Write to Output in High Z
tDW
Data to Write Time Overlap
tDH
Data Hold from Write Time
tOW
Output Active from End of Write
-12
Min.
Max.
Unit
120
10
5
10
0
0
0
10
120
120
80
120
45
45
45
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
120
100
100
100
0
85
0
0
60
0
10
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
TA = 0°C to 70°C, unless otherwise specified
Parameter
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Level
Output Load tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW
Others
Value
0.4V to 2.2V
5ns
1.1V
CL = 5pF + 1TTL Load
CL = 30pF + 1TTL Load
AC TEST LOADS
TTL
CL(1)
Note :
1. Including jig and scope capacitance
Rev.00 /Apr. 2003
4
HY62LF16206B-DT12C
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
tRC
ADDR
tAA
tOH
tACS
/CS1
CS2
tCHZ(3)
tBA
/UB ,/ LB
tBHZ(3)
tOE
/OE
Data
Out
tCLZ(3)
High-Z
tOLZ(3)
tBLZ(3)
tOHZ(3)
Data Valid
READ CYCLE 2(Note 2,3,4)
tRC
ADDR
tAA
tOH
tOH
Data
Out
Previous Data
Data Valid
READ CYCLE 3(Note 1,2,4)
/CS1
/UB, /LB
CS2
tACS
tCLZ(3)
Data
Out
tCHZ(3)
Data Valid
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS1, a high CS2 and low /UB
and/or /LB.
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active. CS2 in low for the standby, high for active.
/UB and /LB in high for the standby, low for active
Rev.00 /Apr. 2003
5
HY62LF16206B-DT12C
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
tW C
ADDR
tW R(2)
tCW
/CS1
CS2
tAW
tBW
/UB,/LB
tW P
/W E
tAS
Data In
tDW
High-Z
tDH
Data Valid
tW HZ(3,7)
tO W
(5)
(6)
Data
O ut
WRITE CYCLE 2 (1,4,8) (/CS1, CS2 Controlled)
tW C
ADDR
tCW
tAS
tW R (2)
/CS1
tAW
CS2
tBW
/UB,/LB
tW P
/W E
tDW
Data In
Data
Out
High-Z
tDH
Data Valid
High-Z
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1, a high CS2 and low /UB and/or /LB.
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high or CS2 going low to the end of
write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS1, /LB and /UB low transition with CS2 high transition occur simultaneously with the /WE low
transition or after the /WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured ±200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS1 in high for the standby, low for active. CS2 in low for the standby, high for active.
/UB and /LB in high for the standby, low for active
Rev.00 /Apr. 2003
6
HY62LF16206B-DT12C
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = 0°C to 70°C
Symbol
Parameter
VDR
Vcc for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to Data
Retention Time
Operating Recovery Time
Test Condition
/CS1 > Vcc - 0.2V or CS2 < Vss+0.2V
or /UB = /LB > Vcc-0.2V,
VIN > Vcc - 0.2V or VIN < Vss + 0.2V
Vcc=1.5V, /CS1 > Vcc - 0.2V,
CS2 < Vss+0.2V,
/UB = /LB > Vcc-0.2V or
VIN > Vcc - 0.2V or VIN < Vss + 0.2V
See Data Retention Timing Diagram
tR
Notes:
1. Typical values are under the condition of TA = 25°C.
2. Typical Values are sampled and not 100% tested
3. tRC is read cycle time.
Min.
1.2
Typ.
-
Max.
2.7
Unit
V
-
-
20
uA
0
-
-
ns
tRC(3)
-
-
ns
DATA RETENTION TIMING DIAGRAM 1
DATA RETENTION MODE
VCC
2.3V
tCDR
tR
VIH
VDR
CS1>VCC-0.2V
/CS1
VSS
DATA RETENTION TIMING DIAGRAM 2
DATA RETENTION MODE
VCC
2.3V
tCDR
tR
CS2
VDR
0.4V
VSS
Rev.00 /Apr. 2003
CS2<0.2V
7
HY62LF16206B-DT12C
PACKAGE INFORMATION
48pin Thin Small Outline Package Forward
#48
#1
UNIT : mm
12.0± 0.1
0.22± 0.05
#25
#24
0.145
0.5
BSC
16.4 ± 0.1
18.0 ± 0.2
1.2(max)
0.8 ± 0.2
Rev.00 /Apr. 2003
0~10˚
8
HY62LF16206B-DT12C
MARKING INSTRUCTION
-
Top Side
Package
TSOP-I
(Forward)
Marking Example
h
y
n
i
x
H
Y
6
2
L
y
y
w
w
p
F
1
6
2
0
K
O
6
B
D
T
R
E
A
1
2
C
Index
• hynix
• KOREA
: Hynix Logo
: Origin Country
• HY62LF16206B
HY
62
L
F
16
20
6
B
: Part Name
: HYNIX
: Product Group
: Operating Voltage
: Tech. + Classification
: Organization
: Density
: Mode
: Version
• yy
• ww
•p
: Year ( ex : 03 = year 2003, 04 = year 2004 )
: Work Week ( ex : 12 = ww12 )
: Process Code
-A
: 12mm X 18mm
•D
•T
• 12
•C
: Power Consumption
: Package Type
: Speed
: Temperature
Note
- Capital Letter
- Small Letter
: Fixed Item
: Non-fixed Item
Rev.00 /Apr. 2003
: Slow SRAM
: 2.5V(2.3V ~ 2.7V)
: Full CMOS
: x16
: 2M
: 2CS with /UB,/LB;tCS
: 3rd Generation
: Low Low Power
: TSOP-I
: 120ns
: Commercial ( 0 ~ 70 °C )
9
HY62LF16206B-DT12C
-
Bottom Side
Package
TSOP-I
(Forward)
Marking Example
x
x
x
x
x
x
x
x
Index
• xxxxxxxx
: FAB Run No.
Note
- Capital Letter
- Small Letter
: Fixed Item
: Non-fixed Item
Rev.00 /Apr. 2003
10
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