MV GX3700 M

GX3700/GX3700e
User Configurable FPGA Board
User’s Guide
Last updated January 26, 2012
GEOTEST
MARVIN TEST SYSTEMS, INC.
GX3700 User’s Guide
i
Safety and Handling
Each product shipped by Geotest is carefully inspected and tested prior to shipping. The shipping box provides
protection during shipment, and can be used for storage of both the hardware and the software when they are not in
use.
The circuit boards are extremely delicate and require care in handling and installation. Do not remove the boards
from their protective plastic coverings or from the shipping box until you are ready to install the boards into your
computer.
If a board is removed from the computer for any reason, be sure to store it in its original shipping box. Do not store
boards on top of workbenches or other areas where they might be susceptible to damage or exposure to strong
electromagnetic or electrostatic fields. Store circuit boards in protective anti-electrostatic wrapping and away from
electromagnetic fields.
Be sure to make a single copy of the software CD for installation. Store the original CD in a safe place away from
electromagnetic or electrostatic fields. Return compact disks (CD) to their protective case or sleeve and store in the
original shipping box or other suitable location.
Warranty
Geotest products are warranted against defects in materials and workmanship for a period of 12 months. Geotest
shall repair or replace (at its discretion) any defective product during the stated warranty period. The software
warranty includes any revisions or new versions released during the warranty period. Revisions and new versions
may be covered by a software support agreement. If you need to return a board, please contact Geotest Customer
Technical Services Department via http://www.geotestinc.com/magic/ - the Geotest on-line support system.
If You Need Help
Visit our web site at http://www.geotestinc.com for more information about Geotest products, services and support
options. Our web site contains sections describing support options and application notes, as well as a download area
for downloading patches, example, patches and new or revised instrument drivers. To submit a support issue
including suggestion, bug report or questions please use the following link: http://www.geotestinc.com/magic/
You can also use Geotest technical support phone line (949) 263-2222. This service is available between 8:30 AM
and 5:30 PM Pacific Standard Time.
Disclaimer
In no event shall Geotest or any of its representatives be liable for any consequential damages whatsoever (including
unlimited damages for loss of business profits, business interruption, loss of business information, or any other
losses) arising out of the use of or inability to use this product, even if Geotest has been advised of the possibility for
such damages.
Copyright
Copyright  2003-2012 by Geotest, Marvin Test Systems, Inc. All rights reserved. No part of this document can be
reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical,
photocopying, recording, or otherwise, without the prior written consent of Geotest.
ii GX3700 User’s Guide
Trademarks
ATEasy, CalEasy, DIOEasy®, DtifEasy, WaveEasy
Geotest – Marvin Test
Systems Inc.
C++ Builder, Delphi
Embarcadero
Technologies Inc.
LabView, LabWindowstm/CVI
National Instruments
Quartus II
Altera Corporation
Microsoft Developer Studio, Microsoft Visual C++, Microsoft Visual Basic,, .NET,
Windows 95, 98, NT, ME, 2000, XP, VISTA and Windows 7
All other trademarks are the property of their respective owners.
Microsoft Corporation
GX3700 User’s Guide
iii
Table of Contents
Safety and Handling...................................................................................................................................................i
Warranty ....................................................................................................................................................................i
If You Need Help .......................................................................................................................................................i
Disclaimer ..................................................................................................................................................................i
Copyright ...................................................................................................................................................................i
Trademarks .............................................................................................................................................................. ii
Table of Contents ....................................................................................................................................... iii
Chapter 1 - Introduction ............................................................................................................................. 1
Manual Scope and Organization ...............................................................................................................................1
Manual Scope.......................................................................................................................................................1
Manual Organization............................................................................................................................................1
Conventions Used in this Manual .............................................................................................................................1
Chapter 2 - Overview .................................................................................................................................. 3
Introduction...............................................................................................................................................................3
Features .....................................................................................................................................................................3
Applications ..............................................................................................................................................................4
Board Description .....................................................................................................................................................4
Architecture ..............................................................................................................................................................7
Inter-FPGA Bus Interface Timing ............................................................................................................................8
DMA FIFO Interface Timing....................................................................................................................................9
Specifications .......................................................................................................................................................... 10
Digital I/O Channel ............................................................................................................................................ 10
Expansion Board Interface ................................................................................................................................. 10
Timing Source .................................................................................................................................................... 10
User FPGA ......................................................................................................................................................... 10
Power ................................................................................................................................................................. 10
Environmental .................................................................................................................................................... 10
Virtual Panel Description ........................................................................................................................................ 11
Virtual Panel Initialize Dialog ................................................................................................................................ 12
Virtual Panel Setup Page ........................................................................................................................................ 13
Virtual Panel I/O Page ............................................................................................................................................ 14
Virtual Panel About Page........................................................................................................................................ 15
Chapter 3 - Installation and Connections ............................................................................................... 17
Getting Started ........................................................................................................................................................ 17
Interfaces and Accessories ..................................................................................................................................... 17
iv GX3700 User’s Guide
Packing List ....................................................................................................................................................... 17
Unpacking and Inspection .................................................................................................................................. 17
System Requirements ......................................................................................................................................... 18
Installation of the GXFPGA Software .................................................................................................................... 18
Setup Maintenance Program ................................................................................................................................... 18
Overview of the GXFPGA Software ...................................................................................................................... 19
Installation Folders ................................................................................................................................................. 19
Configuring Your PXI System using the PXI/PCI Explorer................................................................................... 20
Board Installation .................................................................................................................................................... 21
Before you Begin ............................................................................................................................................... 21
Electric Static Discharge (ESD) Precautions ..................................................................................................... 21
Installing a Board ............................................................................................................................................... 21
Plug & Play Driver Installation .......................................................................................................................... 23
Removing a Board ............................................................................................................................................. 23
Connectors .............................................................................................................................................................. 24
Jumpers ................................................................................................................................................................... 25
GX3700 Connectors – J1-J4 Flex I/O ..................................................................................................................... 28
GX3700 J1 – Flex I/O Connector ...................................................................................................................... 28
GX3700 J2 – Flex I/O Connector ...................................................................................................................... 29
GX3700 J3 – Flex I/O Connector ...................................................................................................................... 30
GX3700 J4 – Flex I/O Connector ...................................................................................................................... 31
Chapter 4 - Programming the Board ....................................................................................................... 33
The GXFPGA Driver .............................................................................................................................................. 33
Programming Using C/C++ Tools .......................................................................................................................... 33
Programming Using Visual Basic and Visual Basic .NET ..................................................................................... 33
Programming Using Pascal/Delphi ......................................................................................................................... 33
Programming GXFPGA Boards Using ATEasy® ................................................................................................... 34
Programming Using LabView and LabView/Real Time ........................................................................................ 34
Using and Programming under Linux ..................................................................................................................... 34
Using the GXFPGA driver functions ...................................................................................................................... 35
Initialization, HW Slot Numbers and VISA Resource ....................................................................................... 35
Board Handle ..................................................................................................................................................... 36
Reset ................................................................................................................................................................... 36
Error Handling ................................................................................................................................................... 36
Driver Version.................................................................................................................................................... 36
Programming Examples .......................................................................................................................................... 36
Distributing the Driver ............................................................................................................................................ 36
GX3700 User’s Guide
v
Chapter 5 - GXFPGA Tutorial ................................................................................................................... 37
Introduction............................................................................................................................................................. 37
Downloading Altera Design FPGA Design Tools .................................................................................................. 37
Create New Project ................................................................................................................................................. 38
Device Selection ................................................................................................................................................ 38
Pin Assignment Setup ........................................................................................................................................ 39
Pin Assignments Table....................................................................................................................................... 39
Schematic entry project ...................................................................................................................................... 41
Verilog entry project .......................................................................................................................................... 42
Creating Design File with Schematic Entry ....................................................................................................... 43
Phase 1: Creating the FPGA design - 32 bit Full Adder ......................................................................................... 43
Components Used .............................................................................................................................................. 43
Schematic view .................................................................................................................................................. 44
Design ................................................................................................................................................................ 45
Phase 2: Creating the FPGA Design - 2 to 1 Clock Mux ........................................................................................ 53
Components Used .............................................................................................................................................. 53
Design ................................................................................................................................................................ 53
Phase 3: Creating the FPGA Design - 32 bit Dynamic Digital Pattern Sequencer ................................................. 54
Components Used .............................................................................................................................................. 54
Design ................................................................................................................................................................ 54
Configure Project to Output SVF and RPD Files ................................................................................................... 58
Compile an Example Project and Build RPD and SVF Files.................................................................................. 60
Load Gx3700 with SVF File ................................................................................................................................... 62
Testing the Design .................................................................................................................................................. 62
Adder Testing ..................................................................................................................................................... 62
Clock Mux Testing............................................................................................................................................. 63
Digital Sequencer Testing .................................................................................................................................. 63
Chapter 6 - GX3700 Expansion Boards .................................................................................................. 65
Overview................................................................................................................................................................. 65
Expansion Board Design Guide .............................................................................................................................. 65
Mechanical Layout Guide ....................................................................................................................................... 70
Expansion Board Connectors and Electrical Requirements .................................................................................... 73
P8 Connector .......................................................................................................................................................... 74
GX3701 Expansion Board ...................................................................................................................................... 80
GX3701 Programming ............................................................................................................................................ 80
GX3701 TTL Expansion Board Specification ........................................................................................................ 80
Chapter 7 - Function Reference ............................................................................................................... 81
vi GX3700 User’s Guide
Introduction............................................................................................................................................................. 81
GXFPGA Functions ................................................................................................................................................ 82
GxFpgaDiscardEvents ............................................................................................................................................ 84
GxFpgaDmaFreeMemory ....................................................................................................................................... 85
GxFpgaDmaGetTransferStatus ............................................................................................................................... 86
GxFpgaDmaTransfer .............................................................................................................................................. 87
GxFpgaGetBoardSummary..................................................................................................................................... 88
GxFpgaGetBoardType ............................................................................................................................................ 89
GxFpgaGetEepromSummary .................................................................................................................................. 90
GxFpgaGetDriverSummary .................................................................................................................................... 91
GxFpgaGetErrorString ............................................................................................................................................ 92
GxFpgaGetExpansionBoardID ............................................................................................................................... 95
GxFpgaInitialize ..................................................................................................................................................... 96
GxFpgaInitializeVisa .............................................................................................................................................. 97
GxFpgaLoad ........................................................................................................................................................... 98
GxFpgaLoadFromEeprom ...................................................................................................................................... 99
GxFpgaLoadStatus................................................................................................................................................ 100
GxFpgaLoadStatusMessage .................................................................................................................................. 101
GxFpgaPanel......................................................................................................................................................... 102
GxFpgaRead ......................................................................................................................................................... 103
GxFpgaReadRegister ............................................................................................................................................ 104
GxFpgaReset......................................................................................................................................................... 105
GxFpgaSetEvent ................................................................................................................................................... 106
GxFpgaUpgradeFirmware .................................................................................................................................... 107
GxFpgaUpgradeFirmwareStatus ........................................................................................................................... 108
GxFpgaWaitOnEvent............................................................................................................................................ 109
GxFpgaWrite ........................................................................................................................................................ 110
GxFpgaWriteRegister ........................................................................................................................................... 111
Index ......................................................................................................................................................... 113
Chapter 1 - Introduction
1
Chapter 1 - Introduction
Manual Scope and Organization
Manual Scope
The purpose of this manual is to provide all the necessary information to install, use, and maintain the GX3700
instrument. This manual assumes the reader has a general knowledge of PC based computers, Windows operating
systems, and some understanding of digital I/O.
This manual also provides programming information using the GX3700 driver (referred in this manual GXFPGA).
Therefore, good understanding of programming development tools and languages may be necessary.
Manual Organization
The GX3700 manual is organized in the following manner:
Chapter
Content
Chapter 1 - Introduction
Introduces the GX3700 manual. Lists all the supported board and shows warning
conventions used in the manual.
Chapter 2 – Overview
Describes the GX3700 features, board description, its architecture, specifications and
the panel description and operation.
Chapter 3 –Installation
and Connections
Provides instructions on how to install a GX3700board and the GXFPGA software.
Chapter 4 –
Programming the Board
Provides a list of the GXFPGA software driver files, general purpose and generic driver
functions, and programming methods. Discusses supported application development
tools and programming examples.
Chapter 5 – GXFPGA
Tutorial and Example
Provides an example of how to use the Quartus II to design and FPGA and then load and
test the design using the GXFPGA panel.
Chapter 6 – Expansion
Boards
Describes how to design a GX3700 expansion board and describes several standard
expansion boards available from Geotest.
Chapter 7 – Functions
Reference
Provides a list of the GX3700 driver functions. Each function description provides
syntax, parameters, and any special programming comments.
Conventions Used in this Manual
Symbol Convention
Meaning
Static Sensitive Electronic Devices. Handle Carefully.
Warnings that may pose a personal danger to your health. For example, shock hazard.
Cautions where computer components may be damaged if not handled carefully.
Tips that aid you in your work.
2 GX3700 User’s Guide
Formatting
Convention
Meaning
Monospaced Text
Examples of field syntax and programming samples.
Bold type
Words or characters you type as the manual instructs. For example: function or panel
names.
Italic type
Specialized terms. Titles of other reference books. Placeholders for items you must
supply, such as function parameters
Chapter 2 - Overview
3
Chapter 2 - Overview
Introduction
The GX3700e is a user configurable, FPGA based, 3U PXI Express card which offers 160 digital I/O signals which
can be configured for single-ended or differential interfaces. The card employs the Altera Stratix III FPGA, which
can support data rates up to 1.2 Gb/s (SerDes interface) and features over 65,000 logic elements and 2.636 Kb of
memory. The GX3700e is supplied with an integral expansion board providing access to the FPGA’s 160 I/Os.
Alternatively, users can design their own custom expansion cards for specific applications eliminating the need for
additional external boards which are cumbersome and physically difficult to integrate into a test system. The design
of the FPGA is done by using Altera’s free Quartus II Web Edition tool set. Once the user has compiled the FPGA
design, the configuration file can be loaded directly into the FPGA or via an on-board EEPROM.
Features
The GX3700e’s digital I/O signals are 5 volt tolerant. Logic families supported by the I/O interface include LVTTL,
LVDS and LVCMOS. The FPGA’s I/Os includes 160 single ended I/O with support for 32 differential pairs, 4
dedicated global clock inputs (2 differential pairs), and various VCCIO voltages. At power up, all I/Os will be
isolated from the UUT. The FPGA device supports up to four phase lock loops (PLL) for clock synthesis, clock
generation and for support of the I/O interface. An on-board 80 MHz oscillator is available for use with the FGPA
device or alternatively, the PXI 10 MHz or 100 MHz clock can be used as a clock reference by the FPGA.
The FPGA has access to all of the PXI Express bus resources including the PXI 10 MHz clock, PXIe 100 MHz
clock, PXIe Sync100, PXIe DStar triggers, the local bus, and the PXI triggers; allowing the user to create a custom
instrument which incorporates all of the PXI Express bus resources. Control and access to the FPGA is provided via
the GX3700e’s driver which includes tools for downloading the compiled FPGA code as well as register read and
write functionality.
The GX3700e include the provision to add a daughter board which will provide additional flexibility for those users
who wish to design their own custom interfaces for specific applications.
Communication between the customer-programmable FPGA and the PXI/PXIe bus is implemented via a dedicated
FPGA device (Interface FPGA). The Interface FPGA contains control and status registers for the board and provides
in-system programmability of the customer-programmable FPGA. The Interface FPGA interfaces directly to the
PXI/PXIe bus and will decode/encode the bus protocol.
The GX3700 have external SRAM, flash, and an external clock source that will be accessible by the customer.
The GX3700 employs the Altera Stratix III 780 pin device. Key features for the Altera device includes:
• 55,856 logic elements (LEs) and 2.34 Mbits of memory
• Supports up to four phase-locked loops (PLLs) for clock synthesis, clock generation and support of I/O
interfaces
• Up to five outputs per PLL can be accessed
• Dynamically reconfigurable logic supports programmable phase shift, frequency multiplication/division, and insystem frequency re-programming without reconfiguring the device
• Support for high-speed external memory interfaces including DDR, DDR2, SDR , SDRAM, and QDRII SRAM
at up to 400 megabits per second (Mbps)
• 327 I/O pins arranged in eight I/O banks that support a wide range of industry I/O standards
• Supports up to 875 Mbps receive and 840 Mbps transmit LVDS communications data rates
• Support for Bus LVDS (BLVDS), LVDS, RSDS®, mini-LVDS and PPDS® differential I/O standards
4 GX3700 User’s Guide
• Supported I/O standards include LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X, LVPECL, LVDS, mini-LVDS,
RSDS, and PPDS; PCI Express Base
•
160 single ended I/Os.
•
32 differential pairs.
•
4 dedicated global clock inputs (2 differential pairs).
•
VCCIO can be preset using on-board jumpers to 1.2V, 2.5V, or 3.3V.
•
16MB internal FPGA SRAM.
•
1MB external SRAM in addition to internal FPGA SRAM.
•
16MB flash
•
User controlled LED.
•
Integrated DMA engine.
•
All of PXI/PXIe instrumentation signals such as differential Star Trigger, SYNC100, CLK100, CLK10, local
bus, trigger bus, and single-ended Star Trigger are available to customer.
Applications
•
Automatic Test Equipment (ATE) and Functional Test
•
Data Acquisition
•
Process Control
•
Factory Automation
Board Description
The GX3700 is a 3U PXI instrument card that consists of 160 TTL I/O Channels divided into groups of 40 channels.
Each of these groups is tied to a 68 pin SCSI type connector on the front panel of the instrument (J1-J4). The
instrument is also has several user configurable jumpers (JP3-JP6) that force the I/O to be routed through the front
connectors rather than the expansion board. A short on JP7 will force the user FPGA to be configured automatically
on boot up with the contents of the EEPROM. For more information about the connectors and jumpers and their
location on the board refer to Chapter 3 – Installation and Connections.
Chapter 2 - Overview
Figure 2-1: GX3700e Board
5
6 GX3700 User’s Guide
Figure 2-2: GX3700 Board
Chapter 2 - Overview
Architecture
The GX3700 provides 160 I/O Channels that can be connected to the front connectors or the optional expansion
board, in groups of 40.
Program
EEPROM
Data
Altera Stratix III
FPGA
780 PINS
160 I/O
UUT I/F
Expansion
Board
PXI
Interface
Address
PXI Bus
PXI Local Bus
And Trigger Bus
PXI
10 MHz
Figure 2-3: Inter-FPGA Bus Timing Diagram
The User FPGA, a Stratix III, can be configured either through the EEPROM or directly through the PXI Interface.
The User FPGA has access to PXI resources such as the local bus, trigger bus, and PXI 10Mhz clock source. The
User FPGA is connected to the PXI Interface FPGA to give access to PCI resources and memory. This allows the
User FPGA to communicate with the host system’s operating system by way of the provided GXFPGA software.
7
8 GX3700 User’s Guide
Inter-FPGA Bus Interface Timing
The Flex FPGA communicates with the PCI/PCIe host via the PXI/PXIe Bridge FPGA. The following figure shows
the inter-FPGA timing diagram for communication between the two FPGAs.
PCIClock
CS(3:1)/LEXT
Addr(19:2)
A1
A2
A3
A4
D1
D2
D3
D4
WrEn
FDt (31:0)
Write Cycle
PCIClock
CS(3:1)/LEXT
Addr (19:2)
A1
A2
A3
A4
D1
D2
D3
RdEn
LRead_DV
FDt (31:0)
One or
more clock
cycles
D4
Read Cycle
Figure 2-4 – Inter-FPGA Bus Interface Diagram
Chapter 2 - Overview
DMA FIFO Interface Timing
The PXI Bridge FPGA contains the DMA engine for transferring data between the Flex FPGA and the PCI/PCIe
host. Unlike a Scatter-Gather DMA engine, this one will need a contiguous memory space.
There are two 32-bit buses between the PXI Bridge FPGA and the Flex FPGA for transmit and receive of DMA
data.
For DMA write, the DMA controller will read data from the Flex FPGA and write this data to the host PC. The
controller will only read data when it’s in DMA write mode and will only read when the EMPTY signal is deasserted. The controller will only read up to the number of byte count specified for the DMA transfer and will not
read more even if the FIFO is still empty.
For DMA read, the DMA controller will read data from the PC host and will write this data to the Flex FPGA.
When in DMA read mode, the Flex FPGA must expect data and must store it. Otherwise, this data will be lost.
PCIClock
RX_DMA_FIFOFUL
L
RX_DMA_DV
RX_DMA_DAT(31:0)
D1
D2
D3
D4
DMA Read FIFO I/F Read from PC host and write to memory
PCIClock
TX_DMA_FIFOEMPTY
TX_DMA_FIFO_RD
TX_DMA_
DV
Zero or more
clock cycles
D1
D2
D3
D4
TX_DMA_DAT(31:0)
DMA Write FIFO I/F Read from memory and write to PC host
Figure 2-5: DMA FIFOs Timing Diagram
9
10 GX3700 User’s Guide
Specifications
The following table outlines the specifications of the GX3700.
Digital I/O Channel
Logic Families
LVTTL and LVCMOS, 5 volt compatible
Output Current
+/ 4.0 mA
Input Leakage Current
+/- 10 uA
Power On State
Programmable by line, default is disconnect at power on
Number of Channels
4 banks of 40 I/O signals. Direction is configurable on a
per pin basis Disconnect on a per bank basis
Protection
Overvoltage: -0.5V to 7.0V (input) Short circuit: up to 8
outputs may be shorted at a time
Connectors
(4) SCSI III, VHDCI type, 68 pin female
Expansion Board Interface
Board ID
4 bits
Digital I/O
160, each bank of 40 can be configured to bypass or
access the expansion board
FPGA Flex I/O
4 signals
Master Clear
Power
From PXI interface
+/- 12 volts, +5 volts, +3.3 volts, +2.5 volts, +1.2 volts
Timing Source
PXI 10 MHZ
PXI Bus
Internal
80 MHz oscillator, +/- 20 ppm
User FPGA
FPGA Type
Stratix III, EP3SL50F780
Number of PLLs
Four
Logic Elements
55,856
Internal Memory
2.34 Mb
Power
3.3 VDC
5 VDC
400 mA (typ.); 1 A (Max.)
300 mA (typ.); 1.2 A (Max.)
12 VDC (For Expansion Board)
Environmental
Operating Temperature
Storage Temperature
Size
Weight
0 to 50° C
-20° C to 70° C
3U PXI
200 g
Chapter 2 - Overview
11
Virtual Panel Description
The GX3700 includes a virtual panel program, which enables full utilization of the various configurations and
controlling modes. To fully understand the front panel operation, it is best to become familiar with the functionality
of the board.
To open the virtual panel application, select GX3700 Panel from the Geotest, GXFPGA menu under the Start
menu. The GX3700 virtual panel opens as shown here:
Figure 2-6: GX3700 Virtual Panel
Initialize – Opens the Initialize Dialog (see Initialize Dialog paragraph) in order to initialize the board driver. The
current settings of the selected board will not change after calling initialize. The panel will reflect the current
settings of the board after the Initialize dialog closes.
Reset – Resets the PXI board settings to their default state and clears the reading.
Apply – Applies changed settings to the board.
Close – Closes the panel. Closing the panel does not affect the board settings.
Help – Opens the on-line help window. In addition to the help menu, the caption shows a What’s This Help button
(?) button. This button can be used to obtain help on any control that is displayed in the panel window. To displays
the What’s This Help information click on the (?) button and then click on the control – a small window will
displays the information regarding this control.
12 GX3700 User’s Guide
Virtual Panel Initialize Dialog
The Initialize dialog initializes the driver for the selected board. The board settings will not change after initialize is
called. Once initialized, the panel will reflect the current settings of the board.
The Initialize dialog supports two different device drivers that can be used to access and control the board:
1. Use Geotest’s HW – This is the device driver installed by the setup program and is the default driver. When
selected, the Slot Number list displays the available GX3700 boards installed in the system and their slots. The
chassis, slots, devices and their resources are also displayed by the HW resource manager, PXI/PCI Explorer
applet that can be opened from the Windows Control Panel. The PXI/PCI Explorer can be used to configure
the system chassis, controllers, slots and devices. The configuration is saved to PXISYS.INI and PXIeSYS.INI
located in the Windows folder. These configuration files are also used by VISA. The following figure shows the
slot number 0x105 (chassis 1 Slot 5). This is the slot number argument (nSlot) passed by the panel when calling
the driver GxFpgaInitialize function which is used to initialize the driver for the specified board.
Figure 2-7: Initialize Dialog Box using Geotest’s HW driver
2. Use VISA – This is a third party device driver usually provided by National Instrument (NI-VISA). When
selected, the Resource list displays the available boards installed in the system and their VISA resource
address. The chassis, slots, devices and their resources are also displayed by the VISA resource manager,
Measurement & Automation (NI-MAX) and by Geotest PXI/PCI Explorer. The following figure shows
PXI9::13::INSTR as the VISA resource (PCI bus 9 and Device 13). This is a VISA resource string argument
(szVisaResource) which is passed by the panel when calling the driver GxFpgaInitializeVisa function which
initializes the driver for the specified board.
Figure 2-8: Initialize Dialog Box using VISA resources
Chapter 2 - Overview
13
Virtual Panel Setup Page
After the board is initialized, the panel is enabled and will display the current setting of the board. The following
picture shows the Setup page settings:
Figure 2-9: GX3700 Virtual Panel – Setup page
The following controls are shown in the Setup page:
Volatile radio button: Select this radio button to load the File to the Volatile (current) FPGA configuration.
EEPROM radio button: Select this radio button to load File to the EEPROM FPGA.
Load From EEPROM button: Loads the volatile (current FPGA) with the FPGA configuration that is stored in the
EEPROM
File text box: File path to the programming file intended to load the volatile FPGA or EEPROM. The File type must
be Serial Vector File (.SVF) for Volatile loading or Raw Programming Data (.RPD) file for EEPROM.
Load Button: Starts the loading process, either to the volatile FPGA or to the EEPROM, depending on which radio
button the user selects.
EEPROM Last Updated On Text: Indicates the last time the EEPROM was loaded.
EEPROM File Name Text: Indicates the last file name that was written to the EEPROM.
14 GX3700 User’s Guide
Expansion Board Bypass Checkboxes: These checkboxes control the routing of each of the FPGA’s I/O Banks.
When the box is checked, it indicates that the I/O Bank will be connected directly to the I/O front connectors. If the
box is unchecked, it indicates that the I/O Bank will be connected to the expansion board.
Virtual Panel I/O Page
Clicking on the I/O tab will show the I/O page as shown in Figure 2-9: GX3700 Virtual Panel – I/O page
Figure 2-10: GX3700 Virtual Panel – I/O page
The following controls are shown in the I/O page:
Offset Text Field: The offset into the FPGA Register or Memory space (BAR2-4) in bytes. This field can be used
with a decimal or hexadecimal value (prefix the value with 0x). The offset is limited to 0x400 bytes when reading
the register space and 0x40000 bytes when reading the memory space. Offset must be specified on a 4 byte
alignment.
Write Text Field: The 32 bit data (hexadecimal or decimal) to be written the specified offset in either FPGA
Register or Memory space (BAR2-4).
Write Button: Write the 32 bit double word to either the FPGA Register or Memory space at the specified offset.
Read Text Field: The 32 bit data that has been read from the specified offset in either FGPA Register or Memory
space. Value is specified in hexadecimal.
Read Button: Read the 32 bit double word from either the FPGA Register or Memory space at the specified offset.
Chapter 2 - Overview
15
Virtual Panel About Page
Clicking on the About tab will show the About page as shown in Figure 2-7
Figure 2-11: GX3700 Virtual Panel – About Page
The top part of the About page displays version and copyright of the GX3700 driver. The bottom part displays the
board summary, including the main board FPGA version an each installed I/O Module FPGA version. The About
page also contains a button Upgrade Firmware… used to upgrade the board FPGA. This button maybe used only
when the board requires upgrade as directed by Geotest support. The upgrade requires a firmware file (.jam) that is
written to the board FPGA. After the upgrade is complete you must shut down the computer to recycle power to the
board.
16 GX3700 User’s Guide
Chapter 3 - Installation and Connections
17
Chapter 3 - Installation and Connections
Getting Started
This section includes general hardware installation procedures for the GX3700 board and installation instructions for
the GX3700 (GXFPGA) software. Before proceeding, please refer to the appropriate chapter to become familiar
with the board being installed.
To Find Information on..
Refer to..
Hardware Installation
This Chapter
GX3700 Driver Installation
This Chapter
Programming
Chapter 4
GXFPGA Design Tools and Tutorial
Chapter 5
Expansion Boards
Chapter 6
GX3700 Function Reference
Chapter 7
Interfaces and Accessories
The following accessories are available from Geotest for GX3700 switching board.
Part / Model Number
Description
GT95015
Connector Interface SCSI to 100 Mil Grid Differential
GT95021
GT95022
2’ 68-Pin shielded cable
3’ 68-Pin shielded cable
GT95028
10’ 68-Pin shielded cable
GT95031
6’ 68-Pin shielded cable
Packing List
All GX3700 boards have the same basic packing list, which includes:
1.
2.
GX3700 Board
GXFPGA Driver Disk
Unpacking and Inspection
After removing the board from the shipping carton:
Caution - Static sensitive devices are present. Ground yourself to discharge static.
1.
Remove the board from the static bag by handling only the metal portions.
2.
Be sure to check the contents of the shipping carton to verify that all of the items found in it match the packing
list.
3.
Inspect the board for possible damage. If there is any sign of damage, return the board immediately. Please refer
to the warranty information at the beginning of the manual.
18 GX3700 User’s Guide
System Requirements
The GX3700 Instrument board is designed to run on PXI compatible computer running Windows 9x, Windows Me,
Windows NT, Windows 2000, XP, Vista and above. In addition, Microsoft Windows Explorer version 4.0 or above
is required to view the online help.
The board requires one unoccupied 3U PXI bus slot.
Installation of the GXFPGA Software
Before installing the board it is recommended that you install the GXFPGA software as described in this section. To
install the GXFPGA software, follow the instruction described below:
1.
Insert the Geotest CD-ROM and locate the GXFPGA.EXE setup program. If you computer’s Auto Run is
configured, when inserting the CD a browser will show several options. Select the Geotest Files option and
then locate the setup file. If Auto Run is not configured you can open the Windows explorer and locate the
setup files (usually located under \Files\Setup folder). You can also download the file from Geotest’s web
site (www.geotestinc.com).
183H
2.
Run the GXFPGA setup and follow the instruction on the Setup screen to install the GXFPGA driver.
Note: When installing under Windows NT/2000/XP/VISTA, you may be required to restart the setup after
logging-in as a user with Administrator privileges. This is required in-order to upgrade your system with
newer Windows components and to install kernel-mode device drivers (HW.SYS and HWDEVICE.SYS)
which are required by the GXFPGA driver to access resources on your board.
3.
The first setup screen to appear is the Welcome screen. Click Next to continue.
4.
Enter the folder where GXFPGA is to be installed. Either click Browse to set up a new folder, or click
Next to accept the default entry of C:\Program Files\Geotest\GXFPGA.
5.
Select the type of Setup you wish and click Next. You can choose between Typical, Run-Time and
Custom setups types. The Typical setup type installs all files. Run-Time setup type will install only the
files required for controlling the board either from its driver or from its virtual panel. The Custom setup
type lets you select from the available components.
The program will now start its installation. During the installation, Setup may upgrade some of the Windows shared
components and files. The Setup may ask you to reboot after completion if some of the components it replaced were
used by another application during the installation – do so before attempting to use the software.
You can now continue with the installation to install the board. After the board installation is complete you can test
your installation by starting a panel program that lets you control the board interactively. The panel program can be
started by selecting it from the Start, Programs, GXFPGA menu located in the Windows Taskbar.
Setup Maintenance Program
You can run the Setup again after GXFPGA has been installed from the original disk or from the Windows Control
Panel – Add Remove Programs applet. Setup will be in the Maintenance mode when running for the second time.
The Maintenance window show below allows you to modify the current GXFPGA installation. The following
options are available in Maintenance mode:
Modify. When you want to add or remove GXFPGA components.
Repair. When you have corrupted files and need to reinstall.
Remove. When you want to completely remove GXFPGA.
Select one of the options and click Next and follow the instruction on the screen until Setup is complete.
Chapter 3 - Installation and Connections
19
Overview of the GXFPGA Software
Once the software is installed, the following tools and software components are available:
•
GXFPGA Panel – Configures and controls the GXFPGA board various features via an interactive user
interface.
•
GXFPGA driver - A DLL based function library (GXFPGA.DLL, located in the Windows System folder)
used to program and control the board. The driver uses Geotest’s HW driver or VISA supplied by third
party vendor to access and control the GXFPGA boards.
•
Programming files and examples – Interface files and libraries for support of various programming tools.
A complete list of files and development tools supported by the driver is included in subsequent sections of
this manual.
•
Documentation – On-Line help and User’s Guide for the board, GXFPGA driver and panel.
•
HW driver and PXI/PCI Explorer applet – HW driver allows the GXFPGA driver to access and
program the supported boards. The explorer applet configures the PXI chassis, controllers and devices. This
is required for accurate identification of your PXI instruments later on when installed in your system. The
applet configuration is saved to PXISYS.ini and PXIeSYS.ini and is used by Geotest instruments HW
driver and VISA. The applet can be used to assign chassis numbers, Legacy Slot numbers and instrument
alias names. The HW driver is installed and shared with all Geotest products to support accessing the PC
resources. Similar to HW driver, VISA provides a standard way for instrument manufacturers and users to
write and use instruments drivers. VISA is a standard maintained by the VXI Plug & Play System Alliance
and the PXI Systems Alliance organizations (http://www.vxipnp.org/, http://www.pxisa.org/). The VISA
resource manager such as National Instruments Measurement & Automation (NI-MAX) displays and
configures instruments and their address (similar to Geotest’s PXI/PCI Explorer). The GXFPGA driver can
work with either HW or VISA to control an access the supported boards.
185H
186H
Installation Folders
The GX3700 driver files are installed in the default folder C:\Program Files\Geotest\GXFPGA. You can
change the default GXFPGA folder to one of your choosing at the time of installation.
During the installation, GXFPGA Setup creates and copies files to the following folders:
Name
Purpose / Contents
…\Geotest\GXFPGA
The GXFPGA folder. Contains panel programs, programming libraries,
interface files and examples, on-line help files and other documentation.
…\Geotest\HW
HW device driver. Provide access to your board hardware resources such
as memory, IO ports and PCI board configuration. See the
README.TXT located in this directory for more information.
…\ATEasy\Drivers
ATEasy drivers folder. GXFPGA Driver and example are copied to this
directory only if ATEasy is installed to your machine.
…\Windows\System (Windows
9x/Me), or …\Windows\System32
when running Windows
NT/2000/XP/VISTA/7
Windows System directory. Contains the GXFPGA DLL driver, HW
driver shared files and some upgraded system components, such as the
HTML help viewer, etc.
20 GX3700 User’s Guide
Configuring Your PXI System using the PXI/PCI Explorer
To configure your PXI/PCI system using the PXI/PCI Explorer applet follow these steps:
1.
2.
3.
4.
Start the PXI/PCI Explorer applet. The applet can be start from the Windows Control Panel or from the
Windows Start Menu, Geotest, HW, PXI/PCI Explorer.
Identify Chassis and Controllers. After the PXI/PCI Explorer is started, it will scan your system for
changes and will display the current configuration. The PXI/PCI Explorer automatically detects systems
that have Geotest controllers and chassis. In addition, the applet detects PXI-MXI-3/4 extenders in your
system (manufactured by National Instruments). If your chassis is not shown in the explorer main window,
use the Identify Chassis/Controller commands to identify your system. Chassis and Controller
manufacturers should provide INI and driver files for their chassis and controllers which are used by these
commands.
Change chassis numbers, PXI devices Legacy Slot numbering and PXI devices Alias names. These are
optional steps and can be performed if you would like your chassis to have different numbers. Legacy slots
numbers are used by older Geotest or VISA drivers. Alias names can provide a way to address a PXI
device using a logical name (e.g. “FPGA1”). For more information regarding slot numbers and alias names,
see the GX3700Initialize and GxFpgaInitializeVisa functions.
Save your work. PXI Explorer saves the configuration to the following files located in the Windows
folder: PXISYS.ini, PXIeSYS.ini and GxPxiSys.ini. Click on the Save button to save your changes. The
PXI/Explorer will prompt you to save the changes if changes were made or detected (an asterisk sign ‘ *‘ in
the caption indicated changes).
Figure 3-1: PXI/PCI Explorer
Chapter 3 - Installation and Connections
21
Board Installation
Before you Begin
•
Install the GXFPGA driver as described in the prior section.
•
Configure your PXI/PC system using PXI/PCI Explorer as described in the prior section.
•
Verify that all the components listed in the packing list (see previous section in this chapter) are present.
Electric Static Discharge (ESD) Precautions
To reduce the risk of damage to the GX3700 board, the following precautions should be observed:
Leave the board in the anti-static bags until installation requires removal. The anti-static bag protects the board
from harmful static electricity.
Save the anti-static bag in case the board is removed from the computer in the future.
Carefully unpack and install the board. Do not drop or handle the board roughly.
Handle the board by the edges. Avoid contact with any components on the circuit board.
Caution – Do not insert or remove any board while the computer is on. Turn off the power from the PXI
chassis before installation.
Installing a Board
Install the board as follows:
1.
Install first the GXFPGA Driver as described in the next section.
2.
Turn off the PXI chassis and unplug the power cord.
3.
Locate a PXI empty slot on the PXI chassis.
4.
Place the module edges into the PXI chassis rails (top and bottom).
5.
Carefully slide the PXI board to the rear of the chassis, make sure that the ejector handles are pushed out (as
shown in Figure 3-2).
372H
22 GX3700 User’s Guide
Figure 3-2: Ejector handles position during module insertion
6.
After you feel resistance, push in the ejector handles as shown in Figure 3-3 to secure the module into the
frame.
37H
Figure 3-3: Ejector handles position after module insertion
7.
Tighten the module’s front panel to the chassis to secure the module in.
8.
Connect any necessary cables to the board.
9.
Plug the power cord in and turn on the PXI chassis.
Chapter 3 - Installation and Connections
23
Plug & Play Driver Installation
Plug & Play operating systems such as Windows 9x, Me, Windows 2000, XP or VISTA (Not Windows NT) notifies
the user that a new board was found using the New Hardware Found wizard after restarting the system with the
new board.
If another Geotest board software package was already installed, Windows will suggest using the driver information
file: HW.INF. The file is located in your Program Files\Geotest\HW folder. Click Next to confirm and follow the
instructions on the screen to complete the driver installation.
If the operating system was unable to find the driver (since the GXFPGA driver was not installed prior to the board
installation), you may install the GXFPGA driver as described in the prior section, then click on the Have Disk
button and browse to select the HW.INF file located in C:\Program File\Geotest\HW.
If you are unable to locate the driver click Cancel to the found New Hardware wizard and exit the New Hardware
Found Wizard, install the GXFPGA driver, reboot your computer and repeat this procedure.
The Windows Device Manager (open from the System applet from the Windows Control Panel) must display the
proper board name before continuing to use the board software (no Yellow warning icon shown next to device). If
the device is displayed with an error you can select it and press delete and then press F5 to rescan the system again
and to start the New Hardware Found wizard.
Removing a Board
Remove the board as follows:
1.
Turn off the PXI chassis and unplug the power cord.
2.
Locate a PXI slot on the PXI chassis.
3.
Disconnect and remove any cables/connectors connected to the board.
4.
Un-tighten the module’s front panel screws to the chassis.
5.
Push out the ejector handles and slide the PXI board away from the chassis.
6.
Optionally – uninstall the GXFPGA driver.
24 GX3700 User’s Guide
Connectors
The following table and figures describes the GX3700 connectors.
Connector
Description
J1
FLEX I/O differential channels 1-32 or single ended 1-64
J2
FLEX I/O channels 33-64
J3
FLEX I/O channels 65-96
J4
FLEX I/O channels 97-128
Table 3-1: GX3700 Connectors
Figure 3-4 shows the available GX3700 front board connectors
Figure 3-4: GX3700e Connectors J1-J4
Figure 3-5: GX3700 Connectors J1-J4
Chapter 3 - Installation and Connections
Jumpers
Jumpers
Description
JP2
For future consideration only. Normally disconnected.
JP3
Connect 3.3V to VCCIO for customer programmable FPGA. Normally connected.
JP4
Connect 2.5V to VCCIO for customer programmable FPGA. Normally disconnected.
JP5
Connect 1.2V to VCCIO for customer programmable FPGA. Normally disconnected.
Table 3-2: GX3700 Jumpers
Figure 3-5 shows GX3700 board JP2, JP3, JP4 and JP5 jumpers (in red rectangular):
Figure 3-6: GX3700 – Front View Jumpers JP3-JP5 and JP2
25
26 GX3700 User’s Guide
Figure 3-7: GX3700e – Front View Jumpers JP3-JP5 and JP2
Chapter 3 - Installation and Connections
JP3
JP4
JP5
Figure 3-8: GX3700/GX3700e Jumpers JP3-JP5
Figure 3-7 shows GX3700 board JP2 Jumper:
JP2
Figure 3-9: GX3700/GX3700e Jumper JP2
27
28 GX3700 User’s Guide
GX3700 Connectors – J1-J4 Flex I/O
Connections to the GX3700 may be made with 68-pin VHDCI male plug connector. Shielded cables with matching
connectors are available from Geotest.
GX3700 J1 – Flex I/O Connector
Pin
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Function
Flex I/O 1P
Flex I/O 2P
Flex I/O 3P
Flex I/O 4P
Flex I/O 5P
Flex I/O 6P
Flex I/O 7P
Flex I/O 8P
Flex I/O 9P
Flex I/O 10P
Diff Clock Input P
Flex I/O 12P
Diff Clock Input P
Flex I/O 14P
Flex I/O 15P
Flex I/O 16P
Flex I/O 17P
Pin
#
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Function
Flex I/O 18P
Flex I/O 19P
Flex I/O 20P
Flex I/O 21P
Flex I/O 22P
Flex I/O 23P
Flex I/O 24P
Flex I/O 25P
Flex I/O 26P
Flex I/O 27P
Flex I/O 28P
Flex I/O 29P
Flex I/O 30P
Flex I/O 31P
Flex I/O 32P
User 3.3V
GND
Pin
#
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Function
Flex I/O 1N
Flex I/O 2N
Flex I/O 3N
Flex I/O 4N
Flex I/O 5N
Flex I/O 6N
Flex I/O 7N
Flex I/O 8N
Flex I/O 9N
Flex I/O 10N
Diff Clock Input N
Flex I/O 12N
Diff Clock Input N
Flex I/O 14N GND
Flex I/O 15N
Flex I/O 16N
Flex I/O 17N GND
Table 3-3: J1 Flex IO Pin Out
P: positive differential I/O signal (e.g. Flex I/O 1P)
N: negative differential I/O signal (e.g. Flex I/O 1N)
Diff Clock Input: Dedicated differential clock inputs.
Pin
#
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Function
Flex I/O 18N
Flex I/O 19N
Flex I/O 20N
Flex I/O 21N
Flex I/O 22N
Flex I/O 23N
Flex I/O 24N
Flex I/O 25N
Flex I/O 26N
Flex I/O 27N
Flex I/O 28N
Flex I/O 29N
Flex I/O 30N
Flex I/O 31N
Flex I/O 32N
User 3.3V
GND
Chapter 3 - Installation and Connections
29
GX3700 J2 – Flex I/O Connector
Pin#
Function
Pin#
Function
Pin#
Function
Pin#
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Flex I/O 33P
Flex I/O 34N
Flex I/O 33N
Flex I/O 34N
Flex I/O 35P
Flex I/O 36P
Flex I/O 35P
Flex I/O 36P
Flex I/O 37P
Flex I/O 38P
Flex I/O 37N
Flex I/O 38N
Flex I/O 39P
Flex I/O 40P
Flex I/O 39N
Flex I/O 40N
Flex I/O 41P
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Flex I/O 42P
Flex I/O 41N
Flex I/O 42N
Flex I/O 53
Flex I/O 54
Flex I/O 55
Flex I/O 56
Flex I/O 57
Flex I/O 58
Flex I/O 59
Flex I/O 60
Flex I/O 61
Flex I/O 62
Flex I/O 63
Flex I/O 64
User 3.3V
GND
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
User 3.3V
GND
Table 3-3: J2 Flex IO Pin Out
P: positive differential I/O signal (e.g. Flex I/O 1P)
N: negative differential I/O signal (e.g. Flex I/O 1N)
30 GX3700 User’s Guide
GX3700 J3 – Flex I/O Connector
Pin#
Function
Pin#
Function
Pin#
Function
Pin#
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Flex I/O 65
Flex I/O 66
Flex I/O 67
Flex I/O 68
Flex I/O 69
Flex I/O 70
Flex I/O 71
Flex I/O 72
Flex I/O 73
Flex I/O 74
Flex I/O 75
Flex I/O 76
Flex I/O 77
Flex I/O 78
Flex I/O 79
Flex I/O 80
Flex I/O 81
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Flex I/O 82
Flex I/O 83
Flex I/O 84
Flex I/O 85
Flex I/O 86
Flex I/O 87
Flex I/O 88
Flex I/O 89
Flex I/O 90
Flex I/O 91
Flex I/O 92
Flex I/O 93
Flex I/O 94
Flex I/O 95
Flex I/O 96
User 5V
GND
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
User 5V
GND
Table 3-4: J3 Flex IO Pin Out
Chapter 3 - Installation and Connections
GX3700 J4 – Flex I/O Connector
Pin#
Function
Pin#
Function
Pin#
Function
Pin#
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Flex I/O 97
Flex I/O 98
Flex I/O 99
Flex I/O 100
Flex I/O 101
Flex I/O 102
Flex I/O 103
Flex I/O 104
Flex I/O 105
Flex I/O 106
Flex I/O 107
Flex I/O 108
Flex I/O 109
Flex I/O 110
Flex I/O 111
Flex I/O 112
Flex I/O 113
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Flex I/O 114
Flex I/O 115
Flex I/O 116
Flex I/O 117
Flex I/O 118
Flex I/O 119
Flex I/O 120
Flex I/O 121
Flex I/O 122
Flex I/O 123
Flex I/O 124
Flex I/O 125
Flex I/O 126
Flex I/O 127
Flex I/O 128
User 5V
GND
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
User 5V
GND
Table 3-5: J4 Flex IO Pin Out
31
32 GX3700 User’s Guide
Chapter 4 - Programming the Board
33
Chapter 4 - Programming the Board
This chapter contains information about how to program the GX3700 board using the GXFPGA driver.
The GXFPGA driver contains functions to initialize, reset, and control the board. A brief description of the
functions, as well as how and when to use them, is included in this chapter.
The GXFPGA driver supports many development tools. Using these tools with the driver is described in this
chapter. In addition, the GXFPGA directory contains examples written for these development tools.
The GXFPGA Driver
The GXFPGA DLL driver is provided with support for 32 bit Windows (GXFPGA.DLL) and 64 bit Windows
(GXFPGA64.DLL). Additional drivers are provided for other operating systems such as Linux and LabView RealTime, see the readme file for more information regarding these drivers. The 32 bit DLL is used with 32 bit
applications running under Windows 2000/XP/VISTA/7 and the 64 runs on Windows XP/Vista/6 64 bit editions.
The DLL uses device driver (HW provided by Geotest or VISA provided by a third party vendor) to access the
board resources. The device driver HW includes HW.SYS and HW64.SYS is installed by the GXFPGA setup
program and is shared by other Geotest products (ATEasy, GTDIO, etc).
The DLL can be used with various development tools such as Microsoft Visual C++, Borland C++ Builder,
Microsoft Visual Basic, Borland Pascal or Delphi, ATEasy and more. The following paragraphs describe how to
create an application that uses the driver with various development tools. Refer to the paragraph describing the
specific development tool for more information.
Programming Using C/C++ Tools
The following steps are required to use the GXFPGA driver with C/C++ development tools:
•
Include the GXFPGA.h header file in the C/C++ source file that uses the GXFPGA function. This header file is
used for all driver types. The file contains function prototypes and constant declarations to be used by the
compiler for the application.
•
Add the required .LIB file to the projects. This can be import library GXFPGA.lib and GXFPGA64.lib (for 64
bit applications) for Microsoft Visual C++ and GXFPGABC.lib for Borland C++. Windows based applications
that explicitly load the DLL by calling the Windows LoadLibrary() API should not include the .LIB file in the
project.
•
Add code to call the GXFPGA as required by the application.
•
Build the project.
•
Run, test, and debug the application.
Programming Using Visual Basic and Visual Basic .NET
To use the driver with Visual Basic 4.0 or above (for 32-bit applications), the user must include the GXFPGA.bas to
the project. The file can be loaded using Add File from the Visual Basic File menu. The GXFPGA.bas contains
function declarations for the DLL driver. If you are using Visual Basic .NET – use the GXFPGA.vb.
Programming Using Pascal/Delphi
To use the driver with Borland Pascal or Delphi, the user must include the GXFPGA.pas to the project. The
GXFPGA.pas file contains a unit with function prototypes for the DLL functions. Include the GXFPGA unit in the
uses statement before making calls to the GXFPGA functions.
34 GX3700 User’s Guide
Programming GXFPGA Boards Using ATEasy®
The GXFPGA package is supplied with a separate ATEasy driver for each board types. For example, the GX3700 is
supplied with GXFPGA.drv ATEasy driver. The ATEasy driver uses the GXFPGA.dll to program the board. In
addition, each driver is supplied with an example that contains a program and a system file pre-configured with the
ATEasy driver. Use the driver shortcut property page from the System Drivers sub-module to change the PXI HW
slot number or VISA resource string before attempting to run the example.
Using commands declared in the ATEasy driver are easier to use than using the DLL functions directly. The driver
commands will also generate exceptions that allow the ATEasy application to trap errors without checking the status
code returned by the DLL function after each function call.
The ATEasy driver contains commands that are similar to the DLL functions in name and parameters, with the
following exceptions:
The nHandle parameter is omitted. The driver handles this parameter automatically. ATEasy uses driver logical
names instead i.e. FPGA1 for GX3700.
The nStatus parameter was omitted. Use the Get Status commands instead of checking the status. After calling a
DLL function the ATEasy driver will check the returned status and will call the error statement (in case of an error
status) to generate exception that can be easily trapped by the application using the OnError module event or using
the try-catch statement.
Some ATEasy drivers contain additional commands to permit easier access to the board features. For example
parameters for a function may be omitted by using a command item instead of typing the parameter value. The
commands are self-documented. Their syntax is similar to English. In addition, you may generate the commands
from the code editor context menu or by using the ATEasy’s code completion feature instead of typing them
directly.
Programming Using LabView and LabView/Real Time
To use the driver with LabView use the provided lab view library GXFPGA.llb. The library is located in the
GXFPGA folder. An example for LabView is also provided in the Examples folder. A DLL located in the
LabViewRT folder can be used for deployment with LabView/Real-Time.
Using and Programming under Linux
Geotest provides a separate software package with Linux driver (Geotest Drivers Pack for Linux). The software
package can be downloaded from the Geotest website. See the ReadMe.txt in that package for more information
regarding using and programming the driver under Linux.
Chapter 4 - Programming the Board
35
Using the GXFPGA driver functions
The following paragraphs describe the steps required to program the boards.
Initialization, HW Slot Numbers and VISA Resource
The GXFPGA driver supports two device drivers HW and VISA which are used to initialize, identify and control the
board. The user can use the GxFpgaInitialize to initialize the board‘s driver using HW and GxFpgaInitializeVisa
to initialize using VISA. The following describes the two different methods used to initialize:
1.
Geotest’s HW – This is the default device driver that is installed by the GXFPGA driver. To initialize and
control the board using the HW use the GxFpgaInitialize(nSlot, pnHandle, pnStatus) function. The function
initializes the driver for the board at the specified PXI slot number (nSlot) and returns boards handle. The
PXI/PCI Explorer applet in the Windows Control Panel displays the PXI slot assignments. You can specify
the nSlot parameter in the following way:
•
A combination of chassis number (chassis # x 256) with the chassis slot number, e.g. 0x105 for chassis
1 and slot 5. The chassis number can be set by the PXI/PCI Explorer applet.
•
Legacy nSlot is used by earlier versions of HW/VISA. The slot number contains no chassis number
and can be changed using the PXI/PCI Explorer applet: 23 in this example.
Figure 4-1: PXI/PCI Explorer
2.
VISA – This is a third party library usually supplied by National Instruments (NI-VISA). You must ensure that
the VISA installed supports PXI and PCI devices (not all VISA providers supports PXI/PCI). GXFPGA setup
installs a VISA compatible driver for the GXFPGA board in-order to be recognized by the VISA provider. Use
the GXFPGA function GxFpgaInitializeVisa (szVisaResource, pnHandle, pnStatus) to initialize the driver’s
36 GX3700 User’s Guide
board using VISA. The first argument szVisaResource is a string that is displayed by the VISA resource
manager such as NI Measurement and Automation (NI_MAX). It is also displayed by Geotest PXI/PCI
Explorer as shown in the prior figure. The VISA resource string can be specified in several ways as the
following examples demonstrate:
•
Using chassis, slot: “PXI0::CHASSIS1::SLOT5”
•
Using the PCI Bus/Device combination: “PXI9::13::INSTR” (bus 9, device 9).
•
Using the alias: for example “COUNTER1”. Use the PXI/PCI Explorer to set the device alias.
Information about VISA is available at http://www.pxisa.org.
189H
Board Handle
The GxFpgaInitialize and the GxFpgaInitializeVisa functions return a handle that is required by other driver
functions in order to program the board. This handle is usually saved in the program as a global variable for later use
when calling other functions. The initialize functions do not change the state of the board or its settings.
Reset
The Reset function sets the board to a known default state. A reset is usually performed after the board is initialized.
See the Function Reference for more information regarding the reset function.
Error Handling
All the GXFPGA functions returns status - pnStatus - in the last parameter. This parameter can be later used for
error handling. The status is zero for success status or less than zero for errors. When the status is error, the program
can call the GxFpgaGetErrorString function to return a string representing the error. The GxFpgaGetErrorString
reference contains possible error numbers and their associated error strings.
Driver Version
The GxFpgaGetDriverSummary function can be used to return the current GXFPGA driver version. It can be used
to differentiate between the driver versions. See the Function Reference for more information.
Programming Examples
The README.txt located on the GXFPGA folder contains a list of the GXFPGA programming examples provided
with the GXFPGA software. Examples are provided for various programming languages including C, VB.NET, VB
(6.0). ATEasy and more.
Distributing the Driver
Once the application is developed, the driver files (GXFPGA.dll, GXFPGA64.dll and the HW device driver files)
can be shipped with the application. Typically, the GXFPGA.dll should be copied to the Windows System directory.
The HW device driver files should be installed using a special setup program HWSETUP.EXE that is provided with
GXFPGA driver files (see Geotest\HW folder) or a standalone setup HW.exe. Alternatively, you can provide the
GXFPGA.exe setup to be installed along with the board.
Chapter 5 - GXFPGA Tutorial
37
Chapter 5 - GXFPGA Tutorial
Introduction
This tutorial will go over the basic workflow to start designing and loading a FPGA configuration for the Gx3700.
The example provides two design methods: schematic entry and Verilog entry. The “Tutorial design top reg.doc”
contains the design register map.
The tutorial contents will entail:
•
Downloading and installing the FPGA design tool
•
Creating a new FPGA Design project with the Stratix III as the target device
•
Setup the pin assignment to work with the GX3700 and Stratix III FPGA
•
Use the design tool to create an example FPGA configuration
•
Compile the project and generate the SVF and RPD programming files
•
Loading the board with the generated programming files
•
Testing the design using the Gx3700 Front Panel software and ATEasy
The example configuration is broken down into three phases, each with a distinct function:
•
Phase 1: Take two values located in PCI Registers and generate a Sum (Adder) which can then be read
through a third PCI Register.
•
Phase 2: 2 to 1 multiplexer to choose between the 10 MHz Clock and the PCI Clock which will be output
on one of the FlexIO pins. The clock will be selected through a PCI Register.
•
Phase 3: A simple dynamic digital sequencer with a memory depth of 32 double words (written to through
the PCI bus) driven by a PLL that continuously outputs digital patterns to the 32 FlexIO pins on J2
connector.
The source code for the examples in this chapter is provided in the Examples\Quartus\Gx3700 folder.
Downloading Altera Design FPGA Design Tools
The Geotest Gx3700 User programmable FPGA board can be designed using the free Altera Quartus II Web Edition
or Subscription Edition design tool. This FPGA design tool allows end users to generate fully featured FPGA
designs that can be downloaded to the Gx3700 board using the Geotest GXFPGA software API or software front
panel. Other 3rd party tools can also be used to design the FPGA. Before proceeding with this tutorial, you must have
Altera Quartus II installed on your PC. More information about this tool and how to download it can be found at
http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html.
38 GX3700 User’s Guide
Create New Project
Figure 5-1: Quartus II Start Dialog
After installing Quartus II Web Edition, start the application and select Create a new Project to start the New
Project Wizard or select File, New, New Quartus Project.
Click on Next and then select the Project Folder and enter tutorial_design_top as the project name.
Click on Next twice (skip the adding files window).
Device Selection
The next window will allow you to select the FPGA target device. Select Stratix III as the Family and
EP3SL50F780C3 as the Available Devices selection.
Click on Next twice (skip the Specify Tools window).
A window summarizing all the choices made for the creation of this project is shown. Click on Finish.
Chapter 5 - GXFPGA Tutorial
39
Pin Assignment Setup
You should now have an empty skeleton project loaded in Quartus II. Before you can get started on the FPGA
design, you must assign the FPGA pins distinct names so that you can reference them in your design. This can be
accomplished by running a TCL script which contains all the information necessary to configure the pin
assignments as well as settings the project to e either schematic entry or Verilog entry. These pin assignments are
unique to this Stratix III FPGA and the GX3700 in particular. The following table lists all the pin assignments and
their respective descriptions. The Pin Alias’s listed in the table are the pin names you will be using in your design to
reference the actual hardware pins on the FPGA.
Pin Assignments Table
Pin Alias (Node Name)
Description
Clocks
10Mhz
Input. 10 MHz Reference Clock Signal from the PXI Backplane
PCIClock
Input. 33 MHz PCI Bus clock or 125MHz PCI Express application clock.
RefClk
Input. 80 Mhz Reference Clock onboard the GX3700
PCI Bus
Addr[2..19]
Input. The PCI Address lines from the PCI bus
FDt[0..31]
Bidir. PCI Data lines from the PCI bus
CS[1..3]
Input. Chip Select lines from the PCI bus.
CS[1] is for FPGA registers, CS[2] is for internal SRAM, CS[3] is currently not used.
LEXT
Input. External SRAM chip select. This is chip select for external SRAM on PCB.
RdEn
Input. PCI Read Enable line from the PCI bus
WrEn
Input. PCI Write Enable line from the PCI bus
LREAD_DV
Output. Read data valid. This is data valid for FDt(31:0) data bus.
LUW
Input. Currently not used. Upper Word.
LLW
Input. Currently not used. Lower Word.
LRESET
Input. Currently not used. Reset coming from PXI bridge FPGA.
PXI Bus
PxiTrig[0..7]
Bidir. PXI Bus trigger signals
StarTrig
Output. PXI Star Trigger signal
PXI_LBL6
Bidir. PXI Local Bus Left 6. This is local bus according to PXIe spec.
PXI_LBR6
Bidir. PXI Local Bus Right 6. This is local bus according to PXIe spec.
PXIe_DSTARA
Input. PXIe DSTAR trigger A. This is DSTAR trigger according to PXIe spec.
PXIe_DSTARB
Input. PXIe DSTAR trigger B. This is DSTAR trigger according to PXIe spec.
PXIe_DSTARC
Output. PXIe DSTAR trigger C. This is DSTAR trigger according to PXIe spec.
PXIE_100M
Input. PXIe 100MHz clock. This is 100MHz clock according to PXIe spec.
PXIE_SYNC100
Input. PXIe Sync100. This is Sync100 signal according to PXIe spec.
I/O
FlexIO[1..160]
Bidir. The physical IO Channels including 4 global clock inputs (2 differential pairs).
40 GX3700 User’s Guide
External Flash
Fsm_a[1..23]
Output. Address bus shared by external SRAM and flash.
Fsd[0..31]
Bidir. Data bus shared by external SRAM and flash.
Flash_ce_n
Output. Flash chip enable.
Flash_oe_n
Output. Flash output enable.
Flash_we_n
Output. Flash write enable.
Flash_reset_n
Output. Flash chip reset
Flash_byte_n
Output. Flash byte/word select.
Flash_busy_n
Input. Flash busy
External SRAM
Sram_be_n[0..3]
Output. External SRAM byte enable.
Sram_ce_n
Output. External SRAM chip select.
Sram_oe_n
Output. External SRAM output enable.
Sram_we_n
Output. External SRAM write enable.
RX DMA FIFO I/F
RX_DMA_DAT[0..31]
Input. Receive DMA data coming from PC host.
RX_DMA_DV
Input. Receive DMA data valid.
RX_DMA_FIFOFULL
Output. Receive DMA FIFO full. This will throttle data from PC host.
RX_DMA_SP1
Output. Spare. Currently not used.
RX_DMA_SP2
Output. Spare. Currently not used.
TX DMA FIFO I/F
TX_DMA_DAT[0..31]
Output. Transmit DMA data from memory going to PC host.
TX_DMA_DV
Output. Transmit DMA data valid.
Output. Transmit DMA FIFO empty. When empty and is sending data to PC host, the
TX_DMA_FIFOEMPTY DMA engine in PXI bridge FPGA will assert FIFO read enable TX_DMA_FIFO_RD.
TX_DMA_FIFO_RD
Input. Transmit DMA FIFO read enable.
Misc
Spare[0..7]
Bidir. Do Not Use. Spares connected to PXI bridge FPGA.
IRQ
Output. Interrupt output pin going to PXI bridge FPGA
IRQ = 1 means interrupt will be generated to PC host.
IRQ = 0 means no interrupt.
FSpr[0..3]
Bidir. Spare Signals connected to Expansion Board
MClr
Input. FPGA Master Clear, Active High
TP[0..5]
Bidir. Connected to test header J7 on the GX3700 PCB
ACTIVE_LED_N
Output. Active LED. Connect to LD1 LED on board. ‘0’ = LED on, ‘1’ = LED off.
Table 5-1: Pin Assignments Table
Chapter 5 - GXFPGA Tutorial
41
Schematic entry project
In order to configure the project as schematic entry and configure the pin assignment the TCL configuration script
should be added to the project. To add the script to the project, click on Project | Add/Remove Files in Project…
In the dialog box, click on the … button and browse for GX3700Schem.tcl file in the “C:\Program
Files\Geotest\GxFpga\Examples\Quartus\Gx3700\Tutorial\ folder. Click Open and then the Add button.
Figure 5-2: Add Tcl Script to Project
Then click on Tools | TCL Scripts … Select the configuration script file, GX3700Schem.tcl and click on Run. This
will configure your FPGA pin assignments.
Note: The TCL file will automatically add all the source files needed for the tutorial design to the Quartus II project.
You can view the pin assignments by running the Pin Planner application which is found in the Tasks list as
highlighted below:
42 GX3700 User’s Guide
Figure 5-3: Task Flow
The Pin Planner will display a matrix of the physical FPGA pins and their mapped names as well as the I/O standard
supported by the pin. These mapped names are used in the FPGA design, as wire names and I/O pins, to connect to
the physical connections of the FPGA.
Verilog entry project
In order to configure the project as Verilog entry and configure the pin assignment the TCL configuration script
should be added to the project. To add the script to the project, click on Project | Add/Remove Files in Project…
In the dialog box, click on the … button and browse for GX3700Verilog tcl file in the “C:\Program
Files\Geotest\GxFpga\Examples\Quartus\Gx3700\Tutorial\ folder. Click Open and then the Add button.
Then click on Tools | TCL Scripts … Select the configuration script file, GX3700Verilog.tcl and click on Run.
This will configure your FPGA pin assignments.
Note: The TCL file will automatically add all the source files needed for the tutorial design to the Quartus II project.
You can view the pin assignments by running the Pin Planner application which is found in the Tasks list as
highlighted below:
Chapter 5 - GXFPGA Tutorial
43
Creating Design File with Schematic Entry
At this point you will have successfully created an FPGA design based on the source codes provided. This section
will walk you through the steps of creating your own source file using schematic entry.
Note: There is more than one way to accomplish the following designs.
Phase 1: Creating the FPGA design - 32 bit Full Adder
This design will take two double word (32 bit) values, located in the first two double words in the Register space
(byte offset 0x0 and 0x4), and add them together. The sum of the two values will be immediately output to the third
double word in the Register space (byte offset 0x8).
Components Used
1x 32 bit Full Adder
1x Decoder
2x D Flip Flops
1x Tristate Buffer
2x AND Gate
1x Constant
Figure 5-4: Phase 1 Adder Components
44 GX3700 User’s Guide
Schematic view
In order to open the schematic view, click on File menu, and then New the following dialog appears.
Select Block Diagram/Schematic File:
Figure 5-5: Open Schematic view Dialog Box
Chapter 5 - GXFPGA Tutorial
45
Design
First start with creating the circuitry required to decode the PCI Address when data is to be written from the PC to
the FPGA. This circuit will be used in all three functions of this example project. The signals required for PCI Write
access will be the PCI Clock, Write Enable, Chip Select 1, and some PCI Address lines. The PCI Address lines 5
to 2 will be fed to a decoder which will generate a 32 bit value, and the result will be ANDed with the Chip Select 1
bit. Each Chip Select bit represents a certain PCI BAR access (GX3700 has two bars, memory and register
memories). Bit 1 represents BAR1 of the PCI memory space (bit 2 for BAR2). BAR1 is the general purpose Control
Register BAR for the GX3700. The results of the AND operation will be once again ANDed to the Write Enable
PCI signal.
Double click on the blank space in the schematic view and select lpm_decode from the Megafunction, Gates
directory.
Figure 5-6: Symbol Insert Dialog Box
Make sure the Launch MegaWizard Plug-In checkbox is unchecked.
Click OK and place the symbol on the blank design document.
46 GX3700 User’s Guide
Now that the Decoder has been placed, some of its parameters have to be set. Right click on the Decoder symbol and
select Properties. Click on the Parameters tab. Set the Width and Decodes properties as shown below:
Figure 5-7: Decoder Properties
Click OK when done. Place another symbol on the design by double clicking on the design document, and selecting
Input Pin from Primitives, Pin, Input. After placing the input pin symbol, rename it to Addr[6..2]. The symbol
will now represent 5 PCI address lines that will be used to communicate with the PC.
Chapter 5 - GXFPGA Tutorial
47
Also place 2 AND gates after the Decoder and a few more input pins with the appropriate names DecAddr, Sel and
WE as the following figure shows:
Figure 5-8: PCI Address Decoder Circuit
Note: To wire several signals together (as a bus), such as Addr[6..2] or Sel[31..0], use the Bus Wiring Tool
highlighted in red below.
Figure 5-9: Bus Wiring Tool
Now that the PCI address decoder circuit is complete, we can feed the appropriate bits from the WE bus to D Flip
Flops that will store data clocked in from the PCI data lines. For example, the first double word in PCI memory
(representing the first number to be summed) will be written to a D Flip Flop with its enable line tied to WE[0] (the
first bit in the WE bus). The second double word to be added will be written to another D Flip Flop with its enable
line tied to WE[1]. Finally, the PCI Clock signal (33Mhz) will be used as the clock source of the D Flip Flops. Note
that each bit of the Sel and WE busses represent a consecutive double word address (bit 0 corresponds with byte 0,
bit 1 corresponds with byte 4, bit 2 corresponds with byte 8 etc.)
Place two D Flips Flops (located at primitives, storage, dffe) and an input pin named PCIClock. We will leave the
D Flip Flops input lines (D) disconnected for now. Eventually the PCI data lines will drive these inputs.
Wire the output of the AND gate to D Flips Flops as shown below.
48 GX3700 User’s Guide
Figure 5-10: D Flip Flops
The D Flips Flops will feed a 32 bit adder and the resulting summation will be wired to the PCI data lines so that the
PC can read the result.
The 32 bit adder will be placed onto the design using the MegaFunction wizard tool. This tool will customize a
component by allowing you to make selections through a wizard.
Double click on the design window and navigate to megafunctions, arithmetic, lpm_add_sub. Make sure the
Launch Megafunctions Wizard checkbox is selected and click OK. You will see a dialog box like the following:
Chapter 5 - GXFPGA Tutorial
Figure 5-11: Adder Wizard
Name the output file SimpleAdder and make sure the path is the same as your project. Click Next and enter 32 as
the data width.
49
50 GX3700 User’s Guide
Figure 5-12: Adder Wizard 2
Click Next through the rest of the wizard and keep the default choices. Finally, the dialog box will show the newly
created design files that will be included in your project. Click Finish and place the newly created Adder in your
design. Wire the adder to the flip flops and add an AND gate, Read Enable pin, and tristate buffer as the following
shows:
Figure 5-13: Adder Circuit
Chapter 5 - GXFPGA Tutorial
51
Note that we are using the FDt[31..0] PCI data lines as bidirectional pins since we will be reading and writing to the
PCI bus. The Tristate buffer is used to select whether the Adder will be driving the PCI Data lines or not. The
Tristate buffer is controlled by the 3rd bit of the decoded PCI Address ANDed with the Read Enable line. When both
signals are high (Sel[2] and RdEn) it indicates that the PCI Bus is expecting the 3rd double word to be written to the
PCI bus. In our case, this means the 32 bit result from the Adder.
The inputs to the D Flips Flops can now be wired to the PCI data lines (FDt) as follows:
Figure 5-14: Adder Circuit with PCI Bus Connection
Now that the design has been completed, a revision number should be added so that the end user can read it back
from the PCI bus at the 32nd register double word location (byte address 0x7C).
Including a revision number constant to the design is a Geotest standard practice that we recommend end users to
follow. The revision constant is 32 bits long and is read as a hexadecimal number such as 0x3564A000. The first
two digits of the hexadecimal number represent the company, in this case 35 is for Geotest designs. The next two
digits are the design specific code, 64 in this case. And the last 4 digits, A000, is the revision of the design.
A constant component needs to be placed in the design (LPM_CONSTANT). When placing this component make
sure that the “Launch MegaWizard Plug-In” selection is unchecked. After placing the component, right click on it
and select properties to set the value and width of the constant as the following figures show:
52 GX3700 User’s Guide
Figure 5-15: Symbol Properties
Now place the 2 port AND gate and the tri-state buffer. You can rotate it, as shown in Figure 5-16, by right clicking
on the symbol (after placing it) and select “Rotate By Degrees | 90”.
Figure 5-16: Adder Circuit with Revision Constant
Chapter 5 - GXFPGA Tutorial
53
Phase 2: Creating the FPGA Design - 2 to 1 Clock Mux
This design will output either the PCI Clock (33Mhz) or the 10Mhz clock to IO Channel 33 (Pin 31 on Flex I/O A
connector) depending on what was written to the 4th double word in the PCI register space (byte offset 0xC). A 1
will select the 10Mhz clock signal, and a 0 will select the PCI clock signal.
Components Used
1x 2 to 1 Mux
1x D Flip Flops
Figure 5-17: Phase 2 Mux Components
Design
You will now build upon the tutorial project to add the functionality of a 2 to 1 Clock Mux. The 10Mhz clock will
be brought into the design by an input pin. The PCI Clock signal input pin is already present in the Phase 1 circuit,
so this will be reused. FlexIO[33] (IO Channel 33) will be used to output the selected clock to the outside world.
Place the 2 to 1 Mux symbol by double clicking on the design area and selecting megafuncitons others, maxplus2,
mux21.
Create three wires attached to the D, ENA(enable) and B inputs of the D Flip Flop. Name the wires FDt[0], Sel[3],
and PCIClock respectively. Note that you did not have to place new input pins to access these signals. This is due to
the fact that input pins were already created for these signals in the Phase 1 design. Therefore, you can just use
named wires to tap into the same input pins.
Figure 5-18: Clock Mux Circuit
FDt[0] is the first bit of the PCI data bus. This bit can either be 0 or 1, to indicate which clock source to choose.
Sel[3] is the 4th bit from the decoded PCI Address. When this bit is high, it indicates that the PCI Bus is addressing
the 4th double word (byte offset 0xC) of the Register space for the GX3700. In our case, the value of this double
word is used to select which clock is selected by our Mux.
54 GX3700 User’s Guide
Phase 3: Creating the FPGA Design - 32 bit Dynamic Digital Pattern Sequencer
Components Used
1x PLL
1x 32 by 32 bit RAM
1x 5 bit Counter
1x AND gate
Figure 5-19: Phase 3 Dynamic Digital Sequencer Components
Design
This design functions as a simple dynamic digital pattern generator. A PLL drives a Counter which iterates through
a 32 double word memory that outputs 32 bit wide digital patterns to the I/O Pins. The memory is loaded through
the PCI bus, allowing users to program the device with vectors through the software front panel or the DLL API.
This phase will require the use of the MegaFunction Wizard to generate all three components, PLL, RAM, and
counter. The wizard will allow you to customize the component for this particular application. The generated
component will be stored in a file (.qip) that will automatically be included in the project.
First insert the PLL component by double clicking on an empty space in the design and clicking on MegaFunction
Plug-In Manager. Choose to create a new MegaFunction variation and click Next. Then select the symbol called
ALTPLL under the I/O folder. Name the new variation SimplePLL and click Next. The next dialog box will
prompt you for the input clock frequency. We will be using a 10Mhz reference clock source so enter 10Mhz into
this field.
Chapter 5 - GXFPGA Tutorial
55
Figure 5-20: PLL Wizard Dialog Box 1
Proceed through the next few screens, with the default choices until you get to step 3 in the wizard entitled Output
Clocks. Select 50 as the division factor as shown in the following figure:
Figure 5-21: PLL Wizard Dialog Box 2
Click Next for the rest of the windows until you get to the last window showing you the files that will be created and
then click Finish. The customized component will now be included in your project automatically so that you can
start using it. Click OK to return to the design view, and then place the newly created symbol on your design.
Attach a wire to the inclk0 terminal of the PLL symbol, and name the wire 10Mhz. This will connect the wire to the
10Mhz input pin that has already been created in the phase 2 design.
Repeat the previous steps to create a new custom component using the MegaFunction Wizard and select
LPM_COUNTER from the arithmetic folder. Name the custom component SimpleCounter and click next. Select 5
bits for the output bus width. We have chosen 5 bits for the width because we need to count from 0 to31 which
requires 5 bits. You can now click next for the rest of the windows and finally click finish to place the symbol on
your design.
56 GX3700 User’s Guide
Wire the c0 output terminal from the PLL to the clock input on the counter.
Figure 5-22: PLL and Counter Circuit
The last component needed is a 32 double word RAM. You will need to deploy the MegaFunction Wizard once
again, and select the 2 port RAM component from the Memory Compiler folder. Call the new component file
SimpleRAM and click Next. Make sure to select 32 as the word length and 32 as the input width as the following
figure shows:
Figure 5-23: RAM Wizard Dialog Box 1
In the next window make sure to select a dual clock for reading and writing so that data can be written to the RAM
from the PCI bus and read out to the IO pins concurrently.
Figure 5-24: RAM Wizard Dialog Box 2
Click Next on the rest of the windows and click Finish placing the RAM component on your design. Wire the
output bus, q[4..0], from the counter to the read address, rdaddress[31..0], of the RAM component.
Connect a bus to data[31..0] and wraddress[4..0]. Name these busses FDt[31..0] and Addr[6..2] respectively. Then
connect wires to wrclock and rdclock and name the wires PCIClock, and 10Mhz respectively.
You will need to place an AND gate next to the RAM component and wire a new input pin called CS[2] and a wire
named WrEn to it. The output of the AND gate should be connected to the wren input of the RAM. This AND logic
ensures that only BAR2 PCI accesses are able to write to the RAM. This will allow us to use the FGPA Memory
Chapter 5 - GXFPGA Tutorial
space to write out digital patterns to the sequencer instead of the FPGA Register space (which is being used for
control). Note that when CS[2] is high, it signifies an access from BAR2.
Finally create a bus connected to the q[31..0] output from the RAM and name it FlexIO[32..1]. This connects the
RAM output to the 32 physical IO pins.
Figure 5-25: Dynamic Digital Sequencer Circuit
At this point the design is complete, continue with the next sections to generate SVF or RPD files and load your
design to the GX3700.
57
58 GX3700 User’s Guide
Configure Project to Output SVF and RPD Files
To ensure that a SVF file is generated upon project compilation, go to the Assignments, Device ... and click on the
Device and Pin Options button. Then click on the Programming Files and verify that the Serial Vector Format
File checkbox has been selected.
Figure 5-26: Select SVF as output file
Now click on the Configuration choose Active Serial Configuration Scheme, check Use Configuration Device
checkbox and select EPCS64 as the configuration device from the drop down selection. Finally click on OK twice
to exit the settings dialog boxes.
Chapter 5 - GXFPGA Tutorial
Figure 5-27: Select Configuration Device
59
60 GX3700 User’s Guide
Compile an Example Project and Build RPD and SVF Files
Click on Processing menu tab and choose Start Compilation to start the compilation process for the example
project. After the process has ran successfully, you should now see in Quartus II something similar to the figure
below. The green check marks indicate success and the red X indicates failure. The process will succeed only when
there is no error. There may or may not be any warning. If there is any warning, make sure that it is OK for the
design before moving forward. For this tutorial design, ignore all warnings.
Figure 5-28: Compilation Tools and Status
The SVF file will be generated after the project compilation has finished. The Compilation Task window will show
green check marks next to each major task to indicate completion.
Chapter 5 - GXFPGA Tutorial
61
In order to generate RPD file go to File, Convert Programming Files …
Select Raw Programming Data File (.rpd) as the Programming file type and tutorial_design_top.rpd as the File
Name. Click on the Add File button and select tutorial_design_top.pof. The .pof file should now appear below the
POF Data node as shown below. Finally, click the Generate button to create the RPD file.
Figure 5-29 Convert Programming Files Dialog Box
62 GX3700 User’s Guide
Load Gx3700 with SVF File
Start the GX3700 Panel (from the Windows Start menu, Geotest, GxFpga) and initialize the instrument. Next,
click on the Volatile radio box and then click on the Browse Button (…) to select the newly generated SVF file
(tutorial_design_top.svf). Finally click on the Load button to begin programming the card. You will see the
progress bar indicate the status of the load. Once the load has completed, the status bar should be unfilled.
Figure 5-30: Software Front Panel
Testing the Design
Now that the design has been completed, compiled and loaded into the GX3700, we can move on to the testing.
There are two ways to access the FPGA, either through the software front panel or through the driver API DLL. We
will demonstrate the programming method using ATEasy to access the driver API DLL.
Adder Testing
The software front panel will be used to test Phase 1 of the design which adds two 32 bit numbers together. Click on
the I/O Tab to get started. The Adder phase is controlled through the FPGA Register space.
Offset 0x0 points to the first 32 bit number that will be summed and offset 0x4 points to the second 32 bit number
that will be summed. Write values to both these locations.
Chapter 5 - GXFPGA Tutorial
63
The sum can be obtained by reading the 32 bit value at offset 0x8. Verify that the correct sum is read back as shown
in Figure 5-31.
Figure 5-31: Using the Software Front Panel to read back the Sum
Clock Mux Testing
The software front panel will once again be used to test Phase 2 of the design. This part of the design uses a Mux to
select between the PCI Clock and the 10 Mhz reference clock. The selected clock is output to I/O Channel 63 which
is located on pin 31 on the Flex I/O J2 connector of the GX3700. The Mux is controlled through the FPGA Register
space.
Writing a 0x0 to offset 0xC will route the PCI/PCIe Clock signal to I/O Channel 63. Writing 0x1 to the same offset
will route the 10 Mhz clock to this same channel. Try switching between both values while monitoring pin 31 of J2
with an oscilloscope. You should see the appropriate clock signals.
Digital Sequencer Testing
For this test, connect an oscilloscope to I/O Channel 65 (pin 1 of J3) to monitor the output signal of the sequencer.
You can access the FPGA memory through the software front panel or through ATEasy. When using the software
front panel, write values to the first 32 double words of the FPGA Memory space (offsets 0x0, 0x4, 0x8, 0xC etc).
As you write to these locations, the data patterns being output on I/O Channel 1 should be updating dynamically. If
you fill the 32 double word memory with a clock pattern (alternating 1’s and 0’s), you should be able to measure a
frequency of 100Khz.
64 GX3700 User’s Guide
When using ATEasy, include the GxFPGA.drv driver and set it up with the correct slot number. Add a variable
called i of type long. You can then run the following code to write to the FPGA memory:
REDIM adwData[32]
adwData[0] = 1
For i=0 to 31
FPGA Write Memory(i*4, 4, adwData[i])
Next
This code will set the first double word to 1 and the rest to 0‘s resulting in a frequency of 6.25 Khz.
Chapter 6 - GX3700 Expansion Boards
65
Chapter 6 - GX3700 Expansion Boards
Overview
The GX3700 requires a piggy-back expansion board to connect to the outside world, a simple; feed through
expansion board is provided. Custom expansion boards can be developed by customers. The following information
is provided to assist the user with developing expansion boards. This information is for both, GX3700 and 3700e.
Expansion Board Design Guide
The expansion board mates with the GX3700 using one connector (P8) and two mounting holes. Two other
connectors – J1 and J2 – exist on the expansion board and are attached to the front panel when the expansion board
is mounted. Figure 6-1 depicts a bottom view of the expansion board and Figure 6-2 and Figure 6-3 detail the
complete GX3700 with the feed through expansion board assembly.
Figure 6-1: GX3701 Expansion Board – Bottom View
66 GX3700 User’s Guide
P8 Connector
Figure 6-2: GX3700e Assembly with Expansion Board
Chapter 6 - GX3700 Expansion Boards
Figure 6-3: GX3700e with Expansion Board Mounted
67
68 GX3700 User’s Guide
P8 Connector
Figure 6-4: GX3700 Assembly with Expansion Board
Chapter 6 - GX3700 Expansion Boards
Figure 6-5: GX3700 with Expansion Board Mounted
69
70 GX3700 User’s Guide
Mechanical Layout Guide
The locations of the mounting holes and connectors are critical to ensure a proper fit between the GX3700 and the
expansion board. Figure 6-6 describes the mechanical details of a typical board and the locations of connectors and
mounting holes. The figure presents a transparent view of the board from the top, with dimensions for critical
component locations. The coordinates for the connectors are pointing to the component reference point. For P1 it is
the middle between pads 1 and 2 of the footprint, as shown in Figure 6-7. For J1 and J2 it is the center of pad A1 of
the footprint, as shown in Figure 6-8.
Note: Dimensions are in mils unless noted otherwise.
Figure 6-6: Mechanical Details – Top View of Typical Board. Dimensions are in mils unless noted otherwise.
Chapter 6 - GX3700 Expansion Boards
Figure 6-7: Component P1 Reference Point
Figure 6-8: Components J1, J2 Reference Point
71
72 GX3700 User’s Guide
Figure 6-9 describes the recommended maximum dimensions for the expansion board and the recommended
maximum component height. The maximum board area is about 110 Sq centimeters or about 17 sq inches.
50mm
95mm
20mm
130mm
75mm
45mm
Maximum component height:
Top side – 1mm
Bottom side – 8mm
Maximum component height:
Top side – 1mm
Bottom side – 12mm
Maximum component height:
Top side – 1mm
Bottom side – 7mm
98mm
Figure 6-9: Mechanical Details – Top view, Maximum Board Dimensions
Chapter 6 - GX3700 Expansion Boards
73
Expansion Board Connectors and Electrical Requirements
P1 is a High Speed Terminal Strip with Rugged Ground Plan manufactured by Samtec (http://www.samtec.com/). It
has a middle bar that is used for ground and power connections. The part number for P1 is QFS-104-06.25-SL-D-A.
Figure 6-10 shows a schematic diagram of P1.
P1A QFS208
VCC_IO
FlxDif31_N
FlxDif31_P
FlxDif29_N
FlxDif29_P
FlxDif27_P
FlxDif27_N
FlxDif25_P
FlxDif25_N
FlxDif23_P
FlxDif23_N
FlxDif21_N
FlxDif21_P
FlxDif19_P
FlxDif19_N
FlxDif17_P
FlxDif17_N
P
P
P
P
P
P
P
P
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
A
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
P1C QFS208
FlxIO53
FlxIO55
FlxIO57
FlxIO59
FlxIO61
FlxIO63
FlxIO97
FlxIO98
FlxIO99
FlxIO100
FlxIO101
FlxIO102
FlxIO103
FlxIO104
FlxIO105
FlxIO106
FlxIO107
FlxIO108
FlxIO109
FlxIO110
FlxIO111
FlxIO112
FlxIO113
FlxIO114
FlxIO115
FlxIO116
2.5V
P
P
P
P
P
P
P
P
FlxDif32_N
FlxDif32_P
FlxDif30_P
FlxDif30_N
FlxDif28_P
FlxDif28_N
FlxDif26_N
FlxDif26_P
FlxDif24_N
FlxDif24_P
FlxDif22_N
FlxDif22_P
FlxDif20_N
FlxDif20_P
FlxDif18_N
FlxDif18_P
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156 C
FlxIO54
FlxIO56
FlxIO58
FlxIO60
FlxIO62
FlxIO64
FlxIO96
FlxIO95
FlxIO94
FlxIO93
FlxIO92
FlxIO91
FlxIO90
FlxIO89
FlxIO88
FlxIO87
FlxIO86
FlxIO85
FlxIO84
FlxIO83
FlxIO82
FlxIO81
FlxIO80
FlxIO79
FlxIO78
FlxIO77
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
- Net is part of Differential Pair
P1B QFS208
FlxDif15_P
FlxDif15_N
FlxDif13_P
FlxDif13_N
FlxDif11_N
FlxDif11_P
FlxDif9_N
FlxDif9_P
FlxDif7_N
FlxDif7_P
FlxDif5_P
FlxDif5_N
FlxDif3_N
FlxDif3_P
FlxDif1_P
FlxDif1_N
FlxIO33
FlxIO35
FlxIO37
FlxIO39
FlxIO41
FlxIO43
FlxIO45
FlxIO47
FlxIO49
FlxIO51
P
P
P
P
P
P
P
P
P
P
P
P
P
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104 B
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
P1D QFS208
P
P
P
P
P
P
P
P
P
P
P
P
P
FlxDif16_P
FlxDif16_N
FlxDif14_N
FlxDif14_P
FlxDif12_N
FlxDif12_P
FlxDif10_P
FlxDif10_N
FlxDif8_N
FlxDif8_P
FlxDif6_N
FlxDif6_P
FlxDif4_P
FlxDif4_N
FlxDif2_N
FlxDif2_P
FlxIO34
FlxIO36
FlxIO38
FlxIO40
FlxIO42
FlxIO44
FlxIO46
FlxIO48
FlxIO50
FlxIO52
FlxIO117
FlxIO118
FlxIO119
FlxIO120
FlxIO121
FlxIO122
FlxIO123
FlxIO124
FlxIO125
FlxIO126
FlxIO127
FlxIO128
Piggy Back ID.
Open='1', GND='0'
Master Clear
Pull downs
to GND
Do Not Use.
PbID0
PbID1
PbID2
PbID3
MClr
R1
PSpr0
R2
PSpr1
R3
PSpr2
R4
PSpr3
10.0K
-12V
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208 D
C9
0.1uF
3.3V
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
FlxIO76
FlxIO75
FlxIO74
FlxIO73
FlxIO72
FlxIO71
FlxIO70
FlxIO69
FlxIO68
FlxIO67
FlxIO66
FlxIO65
R5
R6
R7
R8
FSpr3
FSpr2
FSpr1
FSpr0
10.0K
1.2V
Function ID
Use pull-ups to 3,3V
or pull-downs.
+12V
C8
0.1uF
5V
Figure 6-10: GX3700 Expansion Board – Host Connectors
J1 and J2 are used to connect the expansion board signals to the user application. Each one is a dual VHDCI 68 pins.
There are few vendors for these connectors; one option is Honda PN HDRA-E68W1LFDTC-SL+. Each connector
has two parts A and B. J1A corresponds to J2 on the front panel, J1B to J1, J2A to J4 and J2B to J3 on the front
panel. Customers can us other connectors for their application but that will require changing the design of the front
panel.
The following table lists the assignments for the expansion board signals.
74 GX3700 User’s Guide
P8 Connector
The following table describes the GX3700 expansion board P8 pin assignments:
User
connector
Name
Expansion
Connector
FPGA pin
Remark
J1-1
Flex Diff 1P
P1-82
AG22
J1-35
Flex Diff 1N
P1-84
AH22
J1-2
Flex Diff 2P
P1-83
AG19
J1-36
Flex Diff 2N
P1-81
AF19
J1-3
Flex Diff 3P
P1-80
AH21
J1-37
Flex Diff 3N
P1-78
AH20
J1-4
Flex Diff 4P
P1-77
AD18
J1-38
Flex Diff 4N
P1-79
AE19
J1-5
Flex Diff 5P
P1-74
AG18
J1-39
Flex Diff 5N
P1-76
AH19
J1-6
Flex Diff 6P
P1-75
AE18
J1-40
Flex Diff 6N
P1-73
AF17
J1-7
Flex Diff 7P
P1-72
AH18
J1-41
Flex Diff 7N
P1-70
AH17
J1-8
Flex Diff 8P
P1-71
AE17
J1-42
Flex Diff 8N
P1-69
AF16
J1-9
Flex Diff 9P
P1-68
AG16
J1-43
Flex Diff 9N
P1-66
AH16
J1-10
Flex Diff 10P
P1-65
AD16
J1-44
Flex Diff 10N
P1-67
AE16
J1-11
Flex Diff 11P
P1-64
AG15
Dedicated Clock Input
J1-45
Flex Diff 11N
P1-62
AH15
Dedicated Clock Input
J1-12
Flex Diff 12P
P1-63
AD13
J1-46
Flex Diff 12N
P1-61
AE13
J1-13
Flex Diff 13P
P1-58
AG13
Dedicated Clock Input
J1-47
Flex Diff 13N
P1-60
AH14
Dedicated Clock Input
J1-14
Flex Diff 14P
P1-59
AD12
J1-48
Flex Diff 14N
P1-57
AE12
J1-15
Flex Diff 15P
P1-54
AG12
J1-49
Flex Diff 15N
P1-56
AH13
J1-16
Flex Diff 16P
P1-53
AF10
J1-50
Flex Diff 16N
P1-55
AF11
J1-17
Flex Diff 17P
P1-50
AH11
J1-51
Flex Diff 17N
P1-52
AH12
Chapter 6 - GX3700 Expansion Boards
User
connector
Name
Expansion
Connector
FPGA pin
Remark
J1-18
Flex Diff 18P
P1-51
AE9
J1-52
Flex Diff 18N
P1-49
AF9
J1-19
Flex Diff 19P
P1-46
AG10
J1-53
Flex Diff 19N
P1-48
AH10
J1-20
Flex Diff 20P
P1-47
AF8
J1-54
Flex Diff 20N
P1-45
AE8
J1-21
Flex Diff 21P
P1-44
AG9
J1-55
Flex Diff 21N
P1-42
AH8
J1-22
Flex Diff 22P
P1-43
AE6
J1-56
Flex Diff 22N
P1-41
AF6
J1-23
Flex Diff 23P
P1-38
AG7
J1-57
Flex Diff 23N
P1-40
AH7
J1-24
Flex Diff 24P
P1-39
AE5
J1-58
Flex Diff 24N
P1-37
AF5
J1-25
Flex Diff 25P
P1-34
AG6
J1-59
Flex Diff 25N
P1-36
AH6
J1-26
Flex Diff 26P
P1-35
AF2
J1-60
Flex Diff 26N
P1-33
AG1
J1-27
Flex Diff 27P
P1-30
AH4
J1-61
Flex Diff 27N
P1-32
AH5
J1-28
Flex Diff 28P
P1-29
AE2
J1-62
Flex Diff 28N
P1-31
AF1
J1-29
Flex Diff 29P
P1-28
AG4
J1-63
Flex Diff 29N
P1-26
AH3
J1-30
Flex Diff 30P
P1-25
AD1
J1-64
Flex Diff 30N
P1-27
AE1
J1-31
Flex Diff 31P
P1-24
AG3
J1-65
Flex Diff 31N
P1-22
AH2
J1-32
Flex Diff 32P
P1-23
AC2
J1-66
Flex Diff 32N
P1-21
AC1
J1-34,68
GND
P1-A,C
Power
J1-33,67
User 3.3V
P1-B
Power
J2-1
FlexIO33
P1-86
AH23
Routed to Expansion as Flex Diff 33P
J2-2
FlexIO34
P1-85
AF20
Routed to Expansion as Flex Diff 34N
J2-3
FlexIO35
P1-88
AH24
Routed to Expansion as Flex Diff 33N
J2-4
FlexIO36
P1-87
AE20
Routed to Expansion as Flex Diff 34P
J2-5
FlexIO37
P1-90
AG25
Routed to Expansion as Flex Diff 35P
75
76 GX3700 User’s Guide
User
connector
Name
Expansion
Connector
FPGA pin
Remark
J2-6
FlexIO38
P1-89
AF21
Routed to Expansion as Flex Diff 36P
J2-7
FlexIO39
P1-92
AH25
Routed to Expansion as Flex Diff 35N
J2-8
FlexIO40
P1-91
AE21
Routed to Expansion as Flex Diff 36N
J2-9
FlexIO41
P1-94
AH26
Routed to Expansion as Flex Diff 37P
J2-10
FlexIO42
P1-93
AE22
Routed to Expansion as Flex Diff 38P
J2-11
FlexIO43
P1-96
AG27
Routed to Expansion as Flex Diff 37N
J2-12
FlexIO44
P1-95
AD22
Routed to Expansion as Flex Diff 38N
J2-13
FlexIO45
P1-98
AH27
Routed to Expansion as Flex Diff 39P
J2-14
FlexIO46
P1-97
AF23
Routed to Expansion as Flex Diff 40P
J2-15
FlexIO47
P1-100
AF26
Routed to Expansion as Flex Diff 39N
J2-16
FlexIO48
P1-099
AG24
Routed to Expansion as Flex Diff 40N
J2-17
FlexIO49
P1-102
AE23
Routed to Expansion as Flex Diff 41P
J2-18
FlexIO50
P1-101
AF24
Routed to Expansion as Flex Diff 42N
J2-19
FlexIO51
P1-104
AD24
Routed to Expansion as Flex Diff 41N
J2-20
FlexIO52
P1-103
AE24
Routed to Expansion as Flex Diff 42P
J2-21
FlexIO53
P1-106
AB1
J2-22
FlexIO54
P1-105
B1
J2-23
FlexIO55
P1-108
AB2
J2-24
FlexIO56
P1-107
C1
J2-25
FlexIO57
P1-110
AE4
J2-26
FlexIO58
P1-109
D1
J2-27
FlexIO59
P1-112
AD6
J2-28
FlexIO60
P1-111
D2
J2-29
FlexIO61
P1-114
AE7
J2-30
FlexIO62
P1-113
E1
J2-31
FlexIO63
P1-116
AD7
J2-32
FlexIO64
P1-115
E2
J2-34-66,68
GND
P1-A,C
Power
J2-33,67
User 3.3V
P1-B
Power
J3-1
FlexIO65
P1-179
AA18
J3-2
FlexIO66
P1-177
Y17
J3-3
FlexIO67
P1-175
AB17
J3-4
FlexIO68
P1-173
AC17
J3-5
FlexIO69
P1-171
AB16
J3-6
FlexIO70
P1-169
AC16
J3-7
FlexIO71
P1-167
Y15
J3-8
FlexIO72
P1-165
AA15
Chapter 6 - GX3700 Expansion Boards
User
connector
Name
Expansion
Connector
FPGA pin
Remark
J3-9
FlexIO73
P1-163
Y14
J3-10
FlexIO74
P1-161
Y13
J3-11
FlexIO75
P1-159
AA13
J3-12
FlexIO76
P1-157
AB13
J3-13
FlexIO77
P1-155
AA1
J3-14
FlexIO78
P1-153
Y2
J3-15
FlexIO79
P1-151
Y1
J3-16
FlexIO80
P1-149
W2
J3-17
FlexIO81
P1-147
W1
J3-18
FlexIO82
P1-145
V3
J3-19
FlexIO83
P1-143
V1
J3-20
FlexIO84
P1-141
U3
J3-21
FlexIO85
P1-139
T2
J3-22
FlexIO86
P1-137
N2
J3-23
FlexIO87
P1-135
L2
J3-24
FlexIO88
P1-133
L1
J3-25
FlexIO89
P1-131
K2
J3-26
FlexIO90
P1-129
K1
J3-27
FlexIO91
P1-127
J1
J3-28
FlexIO92
P1-125
H2
J3-29
FlexIO93
P1-123
H1
J3-30
FlexIO94
P1-121
G2
J3-31
FlexIO95
P1-119
G1
J3-32
FlexIO96
P1-117
F1
J3-34-66,68
GND
P1-A,C
Power
J3-33,67
User 5V
P1-D
Power
J4-1
FlexIO97
P1-118
AC7
J4-2
FlexIO98
P1-120
AB7
J4-3
FlexIO99
P1-122
AC8
J4-4
FlexIO100
P1-124
AB8
J4-5
FlexIO101
P1-126
AH9
J4-6
FlexIO102
P1-128
AD9
J4-7
FlexIO103
P1-130
AC9
J4-8
FlexIO104
P1-132
AB9
J4-9
FlexIO105
P1-134
AA9
J4-10
FlexIO106
P1-136
Y9
J4-11
FlexIO107
P1-138
AE10
77
78 GX3700 User’s Guide
User
connector
Name
Expansion
Connector
FPGA pin
Remark
J4-12
FlexIO108
P1-140
AC10
J4-13
FlexIO109
P1-142
AA10
J4-14
FlexIO110
P1-144
Y10
J4-15
FlexIO111
P1-146
AE11
J4-16
FlexIO112
P1-148
AC11
J4-17
FlexIO113
P1-150
AB11
J4-18
FlexIO114
P1-152
Y11
J4-19
FlexIO115
P1-154
AF12
J4-20
FlexIO116
P1-156
AC12
J4-21
FlexIO117
P1-158
Y18
J4-22
FlexIO118
P1-160
AD19
J4-23
FlexIO119
P1-162
AC19
J4-24
FlexIO120
P1-164
AB19
J4-25
FlexIO121
P1-166
AA19
J4-26
FlexIO122
P1-168
Y19
J4-27
FlexIO123
P1-170
AC20
J4-28
FlexIO124
P1-172
AB20
J4-29
FlexIO125
P1-174
AG21
J4-30
FlexIO126
P1-176
AD21
J4-31
FlexIO127
P1-178
AC21
J4-32
FlexIO128
P1-180
AB21
J4-34-66,68
GND
P1-A,C
Power
J4-33,67
User 5V
P1-D
Power
N/A
2.5V
P1-1,3,5,7,9
Power
P1-2,4,6,8,10
VCC I/O of the I/O banks of FPGA used
on expansion board. Selectable on the
GX3700 carrier by jumper as 1.2V, 2.5V
or 3.3V.
N/A
VCC_IO
1.2V
P1-193,195,
197,199,201
Power
N/A
N/A
+12V
P1-205,207
Power
N/A
-12V
P1-208
Power
N/A
MClr
P1-194
Input, Master Clear
PSpr0
P1-198
Do Not Use
PSpr1
P1-200
Do Not Use
PSpr2
P1-202
Do Not Use
PSpr3
P1-204
Do Not Use
PbID0
P1-184
Output, Piggy Back ID. Pull up on carrier
Chapter 6 - GX3700 Expansion Boards
User
connector
FPGA pin
Name
Expansion
Connector
Remark
PbID1
P1-186
Output, Piggy Back ID. Pull up on carrier
PbID2
P1-188
Output, Piggy Back ID. Pull up on carrier
PbID3
P1-200
Output, Piggy Back ID. Pull up on carrier
FSpr0
P1-189
L22
Output, Spare. Can be used as Function ID
FSpr1
P1-187
J16
Output, Spare. Can be used as Function ID
FSpr2
P1-185
J15
Output, Spare. Can be used as Function ID
FSpr3
P1-183
J14
Output, Spare. Can be used as Function ID
Notes for Host connector P1:
1.
2.
3.
4.
5.
6.
7.
79
Maximum 1A per pin.
PSpr[3..0] are reserved. Should be connected to ground using 1K-50K resistors.
PbID[3..0] are used to identify the expansion board. Leave pins unconnected for logic ‘1’ or connect to
ground for logic ‘0’. The GX3700 software driver can read these pins to identify the specific expansion
board installed.
FSpr[3..0] are spare pins connected to the user FPGA. Should be connected to ground or 3.3V using 1K50K resistors if not used in the design. Can also be used as an additional identification field.
MClr is a Master Clear input to the Expansion board. It is active low and is asserted by the controller at
power-up or by a software command at any time.
The Flex I/O signals must never be driven more than VCC_IO. If higher voltage logic is used in the
Expansion board design, these signals must be protected.
During the user FPGA configuration phase, the Flex I/O pins have a weak pull-up that may cause an unintentional condition in the Expansion board. Pull-down resistors should be used where necessary.
80 GX3700 User’s Guide
GX3701 Expansion Board
The GX3701 expansion module used to support different voltage levels:
•
GX3501 - 80 Channel TLL Buffer Expansion Card for GX3700. Each group of 40 channels can be
configured with an on-board jumper to support TTL of LVTTL logic levels. Each channel can be
configured to an input or output under software control. Together with the GX3700 the combined card is
called GX3601.
GX3701 Programming
Use the GXFPGA GxFpgaxxx driver functions to program the board. The functions are described in details in
Chapter 7. Some of the functions are also available from the software front panel.
GX3701 TTL Expansion Board Specification
Number of Channels
160 I/O; up to 84 I/O can be configured as 42 differential I/O channels
4 I/O are single-ended or 2 differential clock inputs
Logic Family
TTL or LVTTL, 5 volt tolerant inputs
Output Current
+/- 8 mA, sink or source
Input Leakage Current
+/- 5 uA
Power On State
All channels are configured as inputs
Input Protection
Overvoltage: -0.5 V to 6.5 V (input)
Chapter 7 - Function Reference
81
Chapter 7 - Function Reference
Introduction
The GXFPGA driver functions reference chapter is organized in alphabetical order. Each function is presented
starting with the syntax of the function, a short description of the function parameters description and type followed
by a Comments, an Example (written in C), and a See Also sections.
All function parameters follow the same rules:
•
Strings are ASCIIZ (null or zero character terminated).
•
Most function’s first parameter is nHandle (16-bit integer). This parameter is required for operating the board
and is returned by the GxFpgaInitialize or the GxFpgaInitializeVisa functions. The nHandle is used to
identify the board when calling a function for programming and controlling the operation of that board.
•
All functions return a status with the last parameter named pnStatus. The pnStatus is zero if the function was
successful, or less than a zero on error. The description of the error is available using the
GxFpgaGetErrorString function or by using a predefined constant, defined in the driver interface files:
GXFPGA.H, GXFPGA.BAS, GXFPGAVB, GXFPGA.PAS or GXFPGA.DRV.
•
Parameter name are prefixed as follows:
Prefix
Type
Example
a
Array, prefix this before the simple type.
anArray (Array of
Short)
n
Short (signed 16-bit)
nMode
d
Double - 8 bytes floating point
dReading
dw
Double word (unsigned 32-bit)
dwTimeout
l
Long (signed 32-bit)
lBits
p
Pointer. Usually used to return a value. Prefix this before the simple
type.
pnStatus
sz
Null (zero value character) terminated string
szMsg
w
Unsigned short (unsigned 16-bit)
wParam
hwnd
Window handle (32-bit integer).
hwndPanel
Table 7-1: Parameter Prefixes
82 GX3700 User’s Guide
GXFPGA Functions
The following list is a summary of functions available for the GX3700:
Driver Functions
Description
General Functions
GxFpgaInitialize
Initializes the driver for the board at the specified slot number using HW. The
function returns a handle that can be used with other GXFPGA functions to
program the board
GxFpgaInitializeVisa
Initializes the driver for the specified slot using VISA. The function returns a
handle that can be used with other GXFPGA functions to program the board.
GxFpgaReset
Resets the GX3700 interface FPGA and User FPGA to their default state.
GxFpgaGetBoardSummary
Returns the board summary.
GxFpgaGetBoardType
Returns the board type.
GxFpgaGetDriverSummary
Returns the driver name and version.
GxFpgaGetErrorString
Returns the error string associated with the specified error number.
GxFpgaPanel
Opens the instrument panel dialog to used to interactively control the board.
FPGA Settings Functions
GxFpgaGetEepromSummary
Returns the timestamp and filename of the last FPGA configuration written to
EEPROM.
GxFpgaGetExpansionBoardID
Returns the current Expansion Board ID.
GxFpgaLoad
Loads the volatile FPGA or the non volatile EEPROM with FPGA
configuration data in the form of SVF or RPD files respectively.
GxFpgaLoadFromEeprom
Loads the FPGA with the contents of the EEPROM.
GxFpgaLoadStatus
Returns the progress of the last asynchronous load in percentage.
GxFpgaLoadStatusMessage
Returns a string describes the current load progress of the last asynchronous
load.
GxFpgaRead
Reads the specified number of data elements from the User’s FPGA specified
BAR memory.
GxFpgaReadRegister
Reads a 32 bit User’s FPGA register.
GxFpgaWrite
Writes the specified number of data elements to the User’s FPGA specified
BAR memory.
GxFpgaWriteRegister
Writes a buffer of 32 bit double words to the User’s FPGA’s register space.
Event (Interrupt) Functions
GxFpgaSetEvent
Enables or disables an event handler
GxFpgaDiscardEvents
Clears the events queue
GxFpgaWaitOnEvent
Waits until event received or timeout occurred
DMA Functions
GxFpgaDmaFreeMemory
Free the DMA block of continues physical memory that was previously
allocated when the user called GxFpgaDmaTransfer API
GxFpgaDmaGetTransferStatus
Returns the DMA transfer status register.
GxFpgaDmaTransfer
Transfers a block of data using DMA.
Chapter 7 - Function Reference
Driver Functions
Description
Upgrade firmware functions
GxFpgaUpgradeFirmware
Upgrades the board’s firmware.
GxFpgaUpgradeFirmwareStatus
Monitor the firmware upgrade process.
83
84 GX3700 User’s Guide
GxFpgaDiscardEvents
Purpose
Clears the event queue.
Syntax
GxFpgaDiscardEvents (nHandle, nEventType, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
nEventType
SHORT
Event type. Use the constant GT_EVENT_INTERRUPT (1). No other value is
supported.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
The function clears the event queue and remove all pending events. Setting an event handler using the
GxFpgaSetEvent automatically clears the event queue.
Example
The following example uses discard events to reset the queue after lengthy operation:
GxFpgaInitialize (1, &nHandle, &nStatus);
GxFpgaSetEvent(nHandle, GT_EVENT_INTERRUPT, TRUE, NULL, (PVOID)1, &nStatus);
while (TRUE)
{
! wait up to 1000 ms for the event
GxFpgaWaitOnEvent(nHandle, GT_EVENT_INTERRUPT, 1000, &nStatus);
if (nStatus!=0)
! success event occurred
{
printf(“no event occurred - exiting”);
break;
}
else
{
! do something lengthy …
! now ready to receive more events
GxFpgaDiscardEvents(nHandle, GT_EVENT_INTERRUPT, &nStatus);
}
See Also
GxFpgaInitialize, GxFpgaGetErrorString, GxFpgaWaitOnEvent, GxFpgaSeyEvent
Chapter 7 - Function Reference
85
GxFpgaDmaFreeMemory
Purpose
Free the DMA block of continues physical memory that was previously allocated when the user called
GxFpgaDmaTransfer API.
Syntax
GxFpgaDmaFreeMemory (nHandle, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
The first time the use calls the GxFpgaDmaTransfer API, a 64KB block of continues physical memory is allocated
for the DMA usage. The user can free this block of physical memory back to the OS by calling this function.
Example
The following example free any previously allocated block of 64KB of continues physical memory.
SHORT
nStatus;
GxFpgaDmaFreeMemory (nHandle, &nStatus);
See Also
GxFpgaDmaTransfer, GxFpgaGetErrorString
86 GX3700 User’s Guide
GxFpgaDmaGetTransferStatus
Purpose
Returns the DMA transfer status register.
Syntax
GxFpgaDmaGetTransferStatus (nHandle, pnDmaStatus, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
pnDmaStatus
SHORT
0.
1.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
No DMA Transfer
DMA Transfer is in progress.
Example
The following example returns the DMA transfer status:
SHORT nDmaStatus;
GxFpgaDmaGetTransferStatus (nHandle, &nDmaStatus, &nStatus);
See Also
GxFpgaDmaTransfer, GxFpgaGetErrorString
Chapter 7 - Function Reference
87
GxFpgaDmaTransfer
Purpose
Transfers a block of data using DMA.
Syntax
GxFpgaDmaTransfer (nHandle, bDmaRd, pvData, nElementSize, dwSize, dwMode, pvOp, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
bDmaRd
BOOL
Transfer operation:
0. GXFPGA_DMA_READ = DMA write opearation. The function will write the
buffer data (pvData) content to the User’s FLEX FPGA memory location.
1. GXFPGA_DMA_WRITE = DMA read opearation. The function will copy the
speciread from the User’s FLEX FPGA memory location to the buffer (pvData).
pvData
PVOID
Pointer to an array of data. The array must be greater or equal to dwSize parameter.
nElementSize
SHORT
The pvData buffer element size.
dwSize
DWORD
Number of elements in the pvData buffer. Maximum number of bytes that can be
transferred at once is 65528.
dwMode
DWORD
Not used.
pvOp
PVOID
Not used.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
The function utilizes the built in DMA capabilities in order to transfer data to or from the User’s FLEX FPGA at the
fastest speed.
Note: The user need to setup the path to the target memory as it design depended.
Example
The following example read a block of 256 bytes of data from User’s FLEX FPGA memory location to the buffer:
DWORD adwData[256]
GxFpgaDmaTransfer (nHandle, GXFPGA_DMA_READ, 0, &adwData, 4, 256, 0, 0, &nStatus);
See Also
GxFpgaDmaGetTransferStatus, GxFpgaGetErrorString
88 GX3700 User’s Guide
GxFpgaGetBoardSummary
Purpose
Returns the board information.
Syntax
GxFpgaGetBoardSummary (nHandle, pszSummary, nMaxLen, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
pszSummary
PSTR
Buffer to contain the returned board info (null terminated) string.
nMaxLen
SHORT
pszSummary buffer size .
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
The function returns the board information including the board firmware version and the board serial number.
Example
The following example returns the board information:
CHAR szSummary[1024];
GxFpgaGetBoardSummary (nHandle, szSummary, 1024, &nStatus);
See Also
GxFpgaInitialize, GxFpgaGetEepromSummary, GxFpgaGetErrorString
Chapter 7 - Function Reference
GxFpgaGetBoardType
Purpose
Returns the board type.
Syntax
GxFpgaGetBoardType (nHandle, pnType, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
pnType
PSHORT
Returned board type:
0. GXFPGA_UNKNOWN_BOARD_TYPE: unknown board type
1. GXFPGA_BOARD_TYPE_GX3500: board type is GX3500
2. GXFPGA_BOARD_TYPE_GX3500E: board type is GX3500E
3. GXFPGA_BOARD_TYPE_GX3700: board type is GX3700
4. GXFPGA_BOARD_TYPE_GX3700E: board type is GX3700E
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Example
The following example returns the board type:
SHORT nType;
GxFpgaGetBoardType(nHandle, &nType, &nStatus);
See Also
GxFpgaInitialize, GxFpgaGetEepromSummary, GxFpgaGetErrorString
89
90 GX3700 User’s Guide
GxFpgaGetEepromSummary
Purpose
Returns the timestamp and filename of the last FPGA configuration written to EEPROM.
Syntax
GxFpgaGetEepromSummary (nHandle, pszSummary, nMaxLen, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
pszSummary
PSTR
Buffer to contain a summary indicating last FPGA EEPROM write timestamp and file
name.
nMaxLen
SHORT
pszSummary buffer size .
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
The function returns the time stamp and file name indicating the last recorded EEPROM loading.
Example
The following example returns the EEPROM summary:
CHAR szSummary[1024];
GxFpgaGetEepromSummary (nHandle, szSummary, 1024, &nStatus);
See Also
GxFpgaLoad, GxFpgaGetBoardSummary, GxFpgaGetErrorString
Chapter 7 - Function Reference
GxFpgaGetDriverSummary
Purpose
Returns the driver name and version.
Syntax
GxFpgaGetDriverSummary (pszSummary ,nSummaryMaxLen, pdwVersion, pnStatus)
Parameters
Name
Type
Comments
pszSummary
PSTR
Buffer to the returned driver summary string.
nSummaryMaxLen
SHORT
The size of the summary string buffer.
pdwVersion
PDWORD
Returned version number. The high order word specifies the major version
number where the low order word specifies the minor version number.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
The returned string is: "GXFPGA Driver for GX3700. Version 1.00, Copyright © 2009 Geotest – MTS inc.".
Example
The following example prints the driver version:
CHAR sz[128];
DWORD dwVersion;
SHORT nStatus;
GxFpgaGetDriverSummary (sz, sizeof sz, &dwVersion, &nStatus);
printf("Driver Version %d.%d", (INT)(dwVersion>>16), (INT)
dwVersion &0xFFFF);
See Also
GxFpgaGetBoardSummary, GxFpgaGetErrorString
91
92 GX3700 User’s Guide
GxFpgaGetErrorString
Purpose
Returns the error string associated with the specified error number.
Syntax
GxFpgaGetErrorString (nError , pszMsg, nErrorMaxLen, pnStatus)
Parameters
Name
Type
Comments
nError
SHORT
Error number.
pszMsg
PSTR
Buffer to the returned error string.
nErrorMaxLen
SHORT
The size of the error string buffer.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
The function returns the error string associated with the nError as returned from other driver functions.
The following table displays the possible error values; not all errors apply to this board type:
Resource Errors
0
No error has occurred
-1
Unable to open the HW driver. Check if HW is properly installed
-2
Board does not exist in this slot/base address
-3
Different board exist in the specified PCI slot/base address
-4
PCI slot not configured properly. You may configure using the PciExplorer from the Windows Control
Panel
-5
Unable to register the PCI device
-6
Unable to allocate system resource for the device
-7
Unable to allocate memory
-8
Unable to create panel
-9
Unable to create Windows timer
-10
Bad or Wrong board EEPROM
-11
Not in calibration mode
-12
Board is not calibrated
-13
Function is not supported by the specified board
General Parameter Errors
-20
Invalid or unknown error number
-21
Invalid parameter
-22
Illegal slot number
-23
Illegal board handle
-24
Illegal string length
Chapter 7 - Function Reference
-25
Illegal operation mode
-26
Parameter is out of the allowed range
VISA Errors
-30
Unable to Load VISA32/64.DLL, make sure VISA library is installed
-31
Unable to open default VISA resource manager, make sure VISA is properly installed
-32
Unable to open the specified VISA resource
-33
VISA viGetAttribute error
-34
VISA viInXX error
-35
VISA ViMapAddress error
Miscellaneous Errors
-41
Unable to enable interrupt or event
-42
Unable to disable interrupt or event
-43
Event or interrupt timeout
-44
Event or interrupt wait error
Board Specific Errors
-50
Offset is out of range
-51
File Name is not valid
-52
Programming file could not be opened
-53
User FPGA Volatile Programming error
-54
User FPGA EEPROM Programming error
-55
Cannot program through software, External Programmer Detected
-56
FPGA or EEPROM is currently being loaded and is busy
-57
FPGA could not be reloaded with the EEPROM data
-58
Size and Offset must be multiple of 4
-59
Expansion board required for function not found
-60
FPGA device program failure
-61
Mismatch the data width and number of bytes
-62
Offset must be multiple of 4
-63
Invalid data width, can be 1 byte, 2 bytes or 4 bytes
-64
Invalid DMA data size
-65
Invalid DMA board's offset
-66
Error: timeout when reading using DMA.
-67
Error: timeout when writing using DMA
-70
Invalid time stamp in on-board EEPROM
-71
Error: timeout when reading from the on-board EEPROM
-72
Error: timeout when writing to the on-board EEPROM
93
94 GX3700 User’s Guide
Example
The following example initializes the board. If the initialization failed, the following error string is printed:
CHAR
sz[256];
SHORT nStatus, nHandle;
GxFpgaInitialize (3, &Handle, &Status);
if (nStatus<0)
{
GxFpgaGetErrorString(nStatus, sz, sizeof sz, &nStatus);
printf(sz); // prints the error string returns
}
Chapter 7 - Function Reference
GxFpgaGetExpansionBoardID
Purpose
Returns the current Expansion Board ID.
Syntax
GxFpgaGetExpansionBoardID (nHandle, pucExpansionBoardID, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
pucExpansionBoardID
PBYTE
Returned value that identifies the currently installed expansion board.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
The returned expansion board ID identifies the type of expansion board being used:
ucExpansionBoardID
Type of board
Examples
0x1
PIO expansion board
GX3701, GX3709, GX3710
0xF
No expansion board installed
N/A
Comments
The expansion board ID is read from P8 pins 19, 21, 23 and 25 to from a 4 bit integer (0-15).
Example
The following example returns the expansion board ID to the ucExpansionBoardID:
BYTE ucExpansionBoardID;
GxFpgaGetExpansionBoardID (nHandle, &ucExpansionBoardID, &nStatus);
See Also
GxFpgaGetErrorString
95
96 GX3700 User’s Guide
GxFpgaInitialize
Purpose
Initializes the driver for the board at the specified slot number. The function returns a handle that can be used with
other GXFPGA functions to program the board.
Syntax
GxFpgaInitialize (nSlot, pnHandle, pnStatus)
Parameters
Name
Type
Comments
nSlot
SHORT
GX3700 board slot number on the PXI bus.
pnHandle
PSHORT
Returned handle for the board. The handle is set to zero on error and <> 0 on
success.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
The GxFpgaInitialize function verifies whether or not the GX3700 board exists in the specified PXI slot. The
function does not change any of the board settings. The function uses the HW driver to access and program the
board.
The Geotest HW device driver is installed with the driver and is the default device driver. The function returns a
handle that for use with other Counter functions to program the board. The function does not change any of the
board settings.
The specified PXI slot number is displayed by the PXI/PCI Explorer applet that can be opened from the Windows
Control Panel. You may also use the label on the chassis below the PXI slot where the board is installed. The
function accepts two types of slot numbers:
•
A combination of chassis number (chassis # x 256) with the chassis slot number. For example 0x105 (chassis 1
slot 5).
•
Legacy nSlot as used by earlier versions of HW/VISA. The slot number contains no chassis number and can be
changed using the PXI/PCI Explorer applet (1-255).
The returned handle pnHandle is used to identify the specified board with other GX3700 functions.
Example
The following example initializes two GX3700 boards at slot 1 and 2.
SHORT nHandle1, nHandle2, nStatus;
GxFpgaInitilize (1, &nHandle1, &nStatus);
GxFpgaInitilize (2, &nHandle2, &nStatus);
if (nHandle1==0 || nHandle2==0)
{
printf(“Unable to Initialize the board”)
return;
}
See Also
GxFpgaInitializeVisa, GxFpgaReset, GxFpgaGetErrorString
Chapter 7 - Function Reference
97
GxFpgaInitializeVisa
Purpose
Initializes the driver for the specified PXI slot using the default VISA provider.
Syntax
GxFpgaInitializeVisa (szVisaResource, pnHandle, pnStatus)
Parameters
Name
Type
Comments
szVisaResource
LPCTSTR
String identifying the location of the specified board in order to establish a
session.
pnHandle
PSHORT
Returned Handle (session identifier) that can be used to call any other operations
of that resource
pnStatus
PSHORT
Returned status: 0 on success, 1 on failure.
Comments
The GxFpgaInitializeVisa opens a VISA session to the specified resource. The function uses the default VISA
provider configured in your system to access the board. You must ensure that the default VISA provider support
PXI/PCI devices and that the board is visible in the VISA resource manager before calling this function.
The first argument szVisaResource is a string that is displayed by the VISA resource manager such as NI
Measurement and Automation (NI_MAX). It is also displayed by Geotest PXI/PCI Explorer as shown in the prior
figure. The VISA resource string can be specified in several ways as follows:
•
Using chassis, slot, for example: “PXI0::CHASSIS1::SLOT5”
•
Using the PCI Bus/Device combination, for example: “PXI9::13::INSTR” (bus 9, device 9).
•
Using alias, for example: “FPGA1”. Use the PXI/PCI Explorer to set the device alias.
The function returns a board handle (session identifier) that can be used to call any other operations of that resource.
The session is opened with VI_TMO_IMMEDIATE and VI_NO_LOCK VISA attributes. On terminating the
application the driver automatically invokes viClose() terminating the session.
Example
The following example initializes a GX3700 boards at PXI bus 5 and device 11.
SHORT nHandle, nStatus;
GxFpgaInitializeVisa (“PXI5::11::INSTR”, &nHandle, &nStatus);
if (nHandle==0)
{
printf("Unable to Initialize the board")
return;
}
See Also
GxFpgaInitialize, GxFpgaReset, GxFpgaGetErrorString
98 GX3700 User’s Guide
GxFpgaLoad
Purpose
Loads the volatile FPGA or the non volatile EEPROM with FPGA configuration data in the form of SVF or RPD
files respectively.
Syntax
GxFpgaLoad (nHandle, nTarget, szFileName nMode,, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
nTarget
SHORT
Target can be as follows:
0. GXFPGA_LOAD_TARGET_VOLATILE
1. GXFPGA_LOAD_TARGET_EEPROM
szFileName
LPCSTR
Path and file name of the file containing the FPGA configuration data. If the
programming mode is Volatile, then the file will have a .SVF extension. If the
programming mode is EEPROM, then the file will have an .RPD extension.
nMode
SHORT
The loading mode can be as follows:
0. GXFPGA_LOAD_MODE_SYNC
1. GXFPGA_LOAD_MODE_ASYNC
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
This function can operate in synchronous mode or asynchronous mode. Synchronous mode means that the function
is blocking and does not return until after the load operation has completed. The Asynchronous mode means that the
function is non-blocking and returns immediately and allows the calling program to check the load status by calling
GxFpgaLoadStatus.
Use the GxFpgaLoadFromEeprom function to load the volatile memory from the EEPROM. By default when the
card is powered up the volatile memory will be automatically load the configuration from the EEPROM.
Example
The following example loads the volatile FPGA with a Serial Vector File (SVF) in synchronous mode
GxFpgaLoad(nHandle, GXFPGA_LOAD_TARGET_VOLATILE, “C:\\MyDesign.SVF”, GXFPGA_LOAD_MODE_SYNC
&nStatus);
See Also
GxFpgaLoadStatus, GxFpgaLoadStatusMessage, GxFpgaGetEepromSummary, GxFpgaLoadFromEeprom,
GxFpgaGetErrorString
Chapter 7 - Function Reference
GxFpgaLoadFromEeprom
Purpose
Loads the FPGA with the contents of the EEPROM.
Syntax
GxFpgaLoadFromEeprom (nHandle, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
By default when JP2 jumper is present, when the card is powered up the volatile memory will be automatically
loaded with the configuration from the EEPROM.
Example
The following example loads the FPGA with the contents of the EEPROM:
GxFpgaLoadFromEeprom (nHandle, &nStatus);
See Also
GxFpgaLoad, GxFpgaGetErrorString
99
100 GX3700 User’s Guide
GxFpgaLoadStatus
Purpose
Returns the progress of the last asynchronous load in percentage.
Syntax
GxFpgaLoadStatus (nHandle,, pnPercentCompleted, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
pnPercentCompleted
PSHORT
The percent complete of the current load, 0-100.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
100 percent indicates that the load has completed. This function is used to check the load status after calling
GxFpgaLoad in Asynchronous mode.
Example
The following load an FPGA file in asynchronous mode and prints the progress:
SHORT nPercentage=0, nPriorPrecentage, nStatus, n;
CHAR szMsg[1024];
GxFpgaLoad(nHandle, GXFPGA_LOAD_TARGET_VOLATILE, “C:\\MyDesign.SVF”, GXFPGA_LOAD_MODE_ASYNC
&nStatus);
while (nStatus==0 && nPrecentage<100)
{
GxFpgaLoadStauts (nHandle, &nPercentage, &nStatus);
GxFpgaLoadStautsMessage (nHandle, szMsg, sizeof szMsg, &n);
if (nPrecentage!=nPriorPrecentage)
printf(“Load Complete=%i, Status=%s”, nPrecentage, szMsg);
nPriorPrecentage=nPrecentage;
sleep(300);
}
printf(“Load Complete=%i, Status=%s”, nPrecentage, szMsg);
See Also
GxFpgaLoad, GxFpgaLoadStatusMessage, GxFpgaGetErrorString
Chapter 7 - Function Reference
GxFpgaLoadStatusMessage
Purpose
Returns a string describes the current load progress of the last asynchronous load.
Syntax
GxFpgaLoadStatusMessage (nHandle,, pszMsg, nMsgMaxLen, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
pszMsg
PSTR
A buffer to the returned message describing the current load status.
nMsgMaxLen
SHORT
Size of the pszMsg.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
The function returns the current load status into the user-supplied buffer. You can use the function to display the
status progress and result after calling GxFpgaLoad in Asynchronous mode.
Example
The following load an FPGA file in asynchronous mode and prints the progress:
SHORT nPercentage=0, nPriorPrecentage, nStatus, n;
CHAR szMsg[1024];
GxFpgaLoad(nHandle, GXFPGA_LOAD_TARGET_VOLATILE, “C:\\MyDesign.SVF”, GXFPGA_LOAD_MODE_ASYNC
&nStatus);
while (nStatus==0 && nPrecentage<100)
{
GxFpgaLoadStauts (nHandle, &nPercentage, &nStatus);
GxFpgaLoadStautsMessage (nHandle, szMsg, sizeof szMsg, &n);
if (nPrecentage!=nPriorPrecentage)
printf(“Load Complete=%i, Status=%s”, nPrecentage, szMsg);
nPriorPrecentage=nPrecentage;
sleep(300);
}
printf(“Load Complete=%i, Status=%s”, nPrecentage, szMsg);
See Also
GxFpgaLoad, GxFpgaLoadStatus, GxFpgaGetErrorString
101
102 GX3700 User’s Guide
GxFpgaPanel
Purpose
Opens a virtual panel used to interactively control the GX3700.
Syntax
GxFpgaPanel (pnHandle, hwndParent, nMode, phwndPanel, pnStatus)
Parameters
Name
Type
Comments
pnHandle
PSHORT
Handle to a GX3700 board.
hwndParent
HWND
Panel parent window handle. A value of 0 sets the desktop as the parent window.
nMode
SHORT
The mode in which the panel main window is created. 0 for modeless window and 1
for modal window.
phwndPanel
HWND
Returned window handle for the panel.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
The function is used to create the panel window. The panel window may be open as a modal or a modeless window
depending on the nMode parameters.
If the mode is set to modal dialog (nMode=1), the panel will disable the parent window (hwndParent) and the
function will return only after the window was closed by the user. In that case, the pnHandle may return the handle
created by the user using the panel Initialize dialog. This handle may be used when calling other GXFPGA
functions.
If a modeless dialog was created (nMode=0), the function returns immediately after creating the panel window
returning the window handle to the panel - phwndPanel. It is the responsibility of calling program to dispatch
windows messages to this window so that the window can respond to messages.
Example
The following example opens the panel in modal mode:
DWORD dwPanel;
SHORT nHandle=0, nStatus;
GxFpgaPanel(&nHandle, 0, 1, &dwPanel, &nStatus);
See Also
GxFpgaInitialize, GxFpgaGetErrorString
Chapter 7 - Function Reference
103
GxFpgaRead
Purpose
Reads the specified number of data elements from the User’s FPGA specified BAR memory.
Syntax
GxFpgaRead (nHandle, nMemoryBar, dwOffset, pvData, nElementSize, dwSize, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
nMemoryBar
SHORT
The board’s specified memory mapped address space BAR number, values are as
follows:
1. GXFPGA_MEMORY_BAR1: Memory mapped address space BAR 1.
2. GXFPGA_MEMORY_BAR2: Memory mapped address space BAR 2.
3. GXFPGA_MEMORY_BAR3: Memory mapped address space BAR 3.
4. GXFPGA_MEMORY_BAR4: Memory mapped address space BAR 4.
dwOffset
DWORD
The offset in the FPGA’s shared memory space in terms of bytes, must be aligned to 4
bytes address.
pvData
PVOID
A buffer that will be written to the FPGA’s shared memory. Buffer size must be as
indicated by the dwSize.
nElementSize
SHORT
The data Size in bytes.
dwSize
DWORD
The number of data elements to be read from the memory location.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Example
The following example read 100 DWORD data points from BAR2 memory space at offset 8:
DWORD adwData[100];
GxFpgaRead (nHandle, GXFPGA_MEMORY_BAR2, 0x8, &adwData, 4, 100, &nStatus);
See Also
GxFpgaWrite, GxFpgaWriteRegister, GxFpgaGetErrorString
104 GX3700 User’s Guide
GxFpgaReadRegister
Purpose
Reads a 32 bit FPGA register.
Syntax
GxFpgaReadRegister (nHandle, dwOffset, pvData, dwSize, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
dwOffset
DWORD
The offset in the FPGA’s register space in terms of bytes, must be aligned to 4 bytes
address.
pvData
PVOID
A buffer that will contain the data read. Buffer size must be as indicated by the dwSize.
dwSize
DWORD
The number of bytes to be read from the memory location must be multiple of 4.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
This function will read one or more double words from the FPGA’s registers. The offset to be read from must be 4
byte aligned.
The Maximum value of dwOffset is 0x400.
Example
DWORD adwData[100];
GxFpgaReadRegister (nHandle, 0x8, &adwData, 400, &nStatus);
See Also
GxFpgaWriteRegister, GxFpgaGetErrorString
Chapter 7 - Function Reference
GxFpgaReset
Purpose
Resets the GX3700 interface FPGA and User FPGA to their default state.
Syntax
GxFpgaReset (nHandle, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Example
The following example initializes and resets the GX3700 board:
GxFpgaInitialize (1, &nHandle, &nStatus);
GxFpgaReset (nHandle, &nStatus);
See Also
GxFpgaInitialize, GxFpgaGetErrorString
105
106 GX3700 User’s Guide
GxFpgaSetEvent
Purpose
Enables or disables an event handler.
Syntax
GxFpgaSetEvent (nHandle, nEventType, bEnable, procCallback,pvUserData, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
nEventType
SHORT
Event type. Use the constant GT_EVENT_INTERRUPT (1). No other value
is supported.
bEnable
BOOL
Enable (<>0) or disable (0) the event.
procCallback
PROCEDURE
Optional. User supplied procedure, called by the driver when an event
occurred.
pvUserData
PVOID
User data (pointer or value) that is passed to the callback procedure when an
events occurred.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
If NULL is passed in to the procCallback parameter the only way to get notified that an event has occurred is to call
the GxFpgaWaitOnEvent function.
The procCallback should be defined as follows:
GxFpgaCallback (nHandle, nEventType,,pvUserData, pnStatus) : Long
Example
The following example output whether an event received during 1 second:
GxFpgaInitialize (1, &nHandle, &nStatus);
GxFpgaSetEvent(nHandle, GT_EVENT_INTERRUPT, TRUE, NULL, (PVOID)1, &nStatus);
! wait up to 1000 ms for the event
GxFpgaWaitOnEvent(nHandle, GT_EVENT_INTERRUPT, 1000, &nStatus);
if (nStatus==0)
! success event occurred
printf(“event occurred”);
else
printf(“No event occurred”);
GxFpgaSetEvent(nHandle, GT_EVENT_INTERRUPT, FALSE, NULL, (PVOID)1, &nStatus);
See Also
GxFpgaInitialize, GxFpgaGetErrorString, GxFpgaWaitOnEvent, GxFpgaDiscardEvents
Chapter 7 - Function Reference
107
GxFpgaUpgradeFirmware
Purpose
Upgrades the board’s firmware.
Syntax
GxFpgaUpgradeFirmware (nHandle, szFile ,nMode, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
szFile
PCSTR
Path and file name of the firmware file. The firmware file extension is RPD.
nMode
SHORT
The upgrading firmware mode can be as follows:
0. GT_FIRMWARE_UPGRADE_MODE_SYNC: the function returns when upgrading
firmware is done or in case of an error.
1. GT_ FIRMWARE_UPGRADE_MODE_ASYNC: the function returns immediately.
The user can monitor the progress of upgrading firmware using the
GxFpgaUpgradeFirmwareStatus API.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
This function used in order to upgrade the board’s firmware. The firmware file can only obtained by request from
Geotest.
Note: Loading an incorrect firmware file to the board can permanently damage the board.
Example
The following example loads Upgrades the board’s firmware using synchronous mode:
GxFpgaUpgradeFirmware (nHandle, “C:\\Gx3700Fw.rpd”, GT_LOAD_MODE_SYNC, &nStatus);
See Also
GxFpgaUpgradeFirmwareStatus, GxFpgaGetErrorString
108 GX3700 User’s Guide
GxFpgaUpgradeFirmwareStatus
Purpose
Monitor the firmware upgrade process.
Syntax
GxFpgaUpgradeFirmwareStatus (nHandle, pszMsg, nMsgMaxLen, pnProgress, pbIsDone, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
pszMsg
PSTR
Buffer to contain the message from the firmware upgrade process.
nMsgMaxLen
SHORT
pszMsg buffer size .
pnProgress
PSHORT
Returns the firmware upgrades progress.
pbIsDone
PBOOL
Returned TRUE if the firmware upgrades is done.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
This function is used in order to monitor the firmware upgrade process whenever the user called
GxFpgaUpgradeFirmware API with GT_ FIRMWARE_UPGRADE_MODE_ASYNC mode.
Note: In order to prevent CPU over load if the function is called form within a loop, a delay of about 500mSec will
be activated if the time differences between consecutive calls are less than 500mSec.
Example
The following example loads Upgrades the board’s firmware using asynchronous mode, and ten monitors the
firmware upgrade process:
CHAR
CHAR
BOOL
sz[256];
szMsg[256];
bIsDone=FALSE;
GxFpgaUpgradeFirmware (nHandle, “C:\\Gx3700Fw.rpd”, GT_UPGRADE_FIRMWARE_MODE_ASYNC, &nStatus);
if (nStatus<0)
{
GxFpgaGetErrorString(nStatus, sz, sizeof sz, &nStatus);
printf(sz); // prints the error string returns
}
While (bIsDone==FALSE || nStatus<0)
{
GxFpgaUpgradeFirmwareStatus (nHandle, szMsg, sizeof szMsg, &nProgress, &bIsDone, &nStatus);
printf(“Upgrade Progress %i”, nProgress);
sleep(1000);
}
if (nStatus<0)
{
GxFpgaGetErrorString(nStatus, sz, sizeof sz, &nStatus);
printf(sz); // prints the error string returns
}
See Also
GxFpgaUpgradeFirmware, GxFpgaGetErrorString
Chapter 7 - Function Reference
109
GxFpgaWaitOnEvent
Purpose
Waits until event received or timeout occurred.
Syntax
GxFpgaWaitOnEvent (nHandle, nEventType, lTimeout, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
nEventType
SHORT
Event type. Use the constant GT_EVENT_INTERRUPT (1). No other value
is supported.
lTimeout
LONG
Timeout to wait in mill seconds.
pnStatus
PSHORT
Returned status: 0 on success (event occurred), negative number on failure.
Comments
The function suspends the current thread until an event occurred or until the specified timeout expired.
Example
The following example output whether an event received during 1 second:
GxFpgaInitialize (1, &nHandle, &nStatus);
GxFpgaSetEvent(nHandle, GT_EVENT_INTERRUPT, TRUE, NULL, (PVOID)1, &nStatus);
! wait up to 1000 ms for the event
GxFpgaWaitOnEvent(nHandle, GT_EVENT_INTERRUPT, 1000, &nStatus);
if (nStatus==0)
! success event occurred
printf(“event occurred”);
else if (nStatus==GT_EVENT_WAIT_TIMEOUT)
printf(“No event occurred (timeout)”);
else
printf(“Event error”);
GxFpgaSetEvent(nHandle, GT_EVENT_INTERRUPT, FALSE, NULL, (PVOID)1, &nStatus);
See Also
GxFpgaInitialize, GxFpgaGetErrorString, GxFpgaSetEvent, GxFpgaDiscardEvents
110 GX3700 User’s Guide
GxFpgaWrite
Purpose
Writes the specified number of data elements to the User’s FPGA specified BAR memory.
Syntax
GxFpgaWrite (nHandle, nMemoryBar, dwOffset, pvData, nElementSize, dwSize, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
nMemoryBar
SHORT
The board’s specified memory mapped address space BAR number, values are as
follows:
1. GXFPGA_MEMORY_BAR1: Memory mapped address space BAR 1.
2. GXFPGA_MEMORY_BAR2: Memory mapped address space BAR 2.
3. GXFPGA_MEMORY_BAR3: Memory mapped address space BAR 3.
4. GXFPGA_MEMORY_BAR4: Memory mapped address space BAR 4.
dwOffset
DWORD
The offset of User’s FPGA memory space in bytes.
pvData
PVOID
A buffer that will be written to the FPGA’s shared memory. Buffer size must be as
indicated by the dwSize.
nElementSize
SHORT
The data Size in bytes.
dwSize
DWORD
The number of data elements to write to the memory location.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Example
The following example writes 100 DWORD to the User’s FPGA BAR1 memory to begin at offset 8:
DWORD adwData[100];
GxFpgaWrite (nHandle, GXFPGA_MEMORY_BAR1, 0x8, &adwData, 4, 100, &nStatus);
See Also
GxFpgaRead, GxFpgaWriteRegister, GxFpgaGetErrorString
Chapter 7 - Function Reference
111
GxFpgaWriteRegister
Purpose
Writes a buffer of 32 bit double words to the FPGA’s register space.
Syntax
GxFpgaWriteRegister (nHandle ,dwOffset, pvData, dwSize, pnStatus)
Parameters
Name
Type
Comments
nHandle
SHORT
Handle for a GX3700 board.
dwOffset
DWORD
The offset in the FPGA’s register space in terms of bytes, must be aligned to 4 bytes
address.
pvData
PDWORD
A buffer that will be written to the FPGA’s registers. Buffer size must be as indicated
by the dwSize.
dwSize
DWORD
The number of bytes to be written to the registers must be multiple of 4.
pnStatus
PSHORT
Returned status: 0 on success, negative number on failure.
Comments
This function will write one or more double words to the FPGA’s registers. The offset to be written to must be 4byte aligned
The Maximum value of dwOffset is 0x400.
Example
The following example writes 400 bytes to the card register space at offset 8:
DWORD adwData[100];
GxFpgaWriteRegister (nHandle, 0x8, &adwData, 400, &nStatus);
See Also
GxFpgaReadRegister, GxFpgaGetErrorString
112 GX3700 User’s Guide
GX3700 User’s Guide 113
Index
.
Distributing the Driver............................................. 36
.NET ......................................................................... ii
DMA FIFO Interface Timing ....................................9
A
Driver
Adder Circuit ........................................................... 50
Directory .............................................................. 19
Adder Circuit with PCI Bus Connection ................. 51
Files ..................................................................... 19
Adder Components .................................................. 43
Dynamic Digital Sequencer Circuit ......................... 57
Adder Wizard .................................................... 49, 50
E
Altera .............................................................. ii, 3, 37
Error-Handling ........................................................ 36
Applications ...............................................................4
ESD ......................................................................... 21
Architecture ...............................................................1
Examples ................................................................. 36
Architecture
Expansion Board Design Guide............................... 65
ATEasy ....................................................ii, 19, 33, 34
Expansion Boards .................................................... 65
B
F
Board Description .................................................. 1, 4
Features......................................................................3
Board Handle ........................................................... 36
Function Reference .................................................. 81
Board Installation .................................................... 21
G
Borland .................................................................... 33
Getting Started ......................................................... 17
Borland-Delphi ........................................................ 33
GX3601 ................................................................... 80
Bus Wiring Tool ...................................................... 47
GX3700Schem.tcl.................................................... 41
C
GX3700Verilog.tcl .................................................. 42
C/C++ ...................................................................... 33
GX3701 ................................................................... 80
Components Used .................................................... 43
GX3701 Specification ............................................. 80
Connector ................................................................ 24
GXFPGA ............................................................. 1, 18
Connectors ............................................. 23, 24, 28, 73
Driver-Description ............................................... 33
Corrupt files ............................................................. 18
Header-file ........................................................... 33
Creating the FPGA Design ................................ 53, 54
GXFPGA Driver ...................................................... 33
Cyclone III ............................................................... 38
GXFPGA driver functions ....................................... 35
D
GXFPGA Functions ................................................ 82
D Flip Flops ............................................................. 48
GXFPGA Software .................................................. 19
Decoder Properties .................................................. 46
GXFPGA.bas ........................................................... 33
Delphi ................................................................. ii, 33
GXFPGA.dll ............................................................ 34
Design ...................................................................... 45
GXFPGA.EXE ........................................................ 18
Design File............................................................... 43
GXFPGA.h .............................................................. 33
Device Selection ...................................................... 38
GXFPGA.lib ............................................................ 33
Directories ............................................................... 19
GXFPGA.llb ............................................................ 34
114 GX3700 User’s Guide
GXFPGA.pas ........................................................... 33
Precautions-Static-Electricity .............................. 21
GXFPGA.vb ............................................................ 33
Procedures-All-Boards .................................. 21, 23
GXFPGA64.DLL .................................................... 33
Installation Directories ............................................ 19
GXFPGA64.lib ........................................................ 33
Interfaces ................................................................. 17
GXFPGABC.lib ....................................................... 33
Inter-FPGA Bus Interface Timing .............................8
GxFpgaDiscardEvent............................................... 84
Introduction ...............................................................3
GxFpgaDiscardEvents ............................................. 82
J
GxFpgaDmaFreeMemory .................................. 82, 85
J1 ....................................................................... 24, 28
GxFpgaDmaGetTransferStatus.......................... 82, 86
J2 ....................................................................... 24, 29
GxFpgaDmaTransfer ......................................... 82, 87
J3 ....................................................................... 24, 30
GxFpgaGetBoardSummary ............................... 82, 88
J4 ....................................................................... 24, 31
GxFpgaGetBoardType....................................... 82, 89
JP2 ........................................................................... 25
GxFpgaGetDriverSummary ......................... 36, 82, 91
JP3 ........................................................................... 25
GxFpgaGetEepromSummary ............................ 82, 90
JP4 ........................................................................... 25
GxFpgaGetErrorString .................... 36, 81, 82, 92, 94
JP5 ........................................................................... 25
GxFpgaGetExpansionBoardID .......................... 82, 95
Jumpers .................................................................... 25
GxFpgaInitialize .................. 12, 20, 35, 36, 81, 82, 96
L
GxFpgaInitializeVisa ................. 12, 20, 35, 81, 82, 97
LabView .................................................................. 34
GxFpgaLoad ...................................................... 82, 98
LabView/Real Time ................................................ 34
GxFpgaLoadFromEeprom ................................. 82, 99
Linux ....................................................................... 34
GxFpgaLoadStatus .......................................... 82, 100
M
GxFpgaLoadStatusMessage ............................ 82, 101
Mechanical Guide .................................................... 70
GxFpgaPanel ................................................... 82, 102
MegaWizard Plug-In ............................................... 45
GxFpgaRead ............................................................ 82
N
GxFpgaReadRegister ....................................... 82, 104
nHandle ................................................................... 34
GxFpgaReset ................................................... 82, 105
O
GxFpgaSetEvent .............................................. 82, 106
OnError .................................................................... 34
GxFpgaUpgradeFirmware ............................... 83, 107
Open Schematic view Dialog Box ........................... 44
GxFpgaUpgradeFirmwareStatus ..................... 83, 108
Overview ...................................................................3
GxFpgaWaitOnEvent ...................................... 82, 109
P
GxFpgaWrite ........................................... 82, 103, 110
P8 Connector ........................................................... 74
GxFpgaWriteRegister ...................................... 82, 111
Packing List ............................................................. 17
H
Panel .................................. 11, 13, 14, 15, 18, 35, 102
Handle ................................................... 21, 22, 35, 36
Panel About Page..................................................... 15
HW .................................................. 18, 19, 23, 33, 36
Part / Model Number ............................................... 17
I
Pascal ....................................................................... 33
Installation ......................................................... 17, 18
PCI ........................................................................... 19
GX3700 User’s Guide 115
PCI Address Decoder Circuit .................................. 47
Setup .................................................................. 18, 19
Pin Assignment ........................................................ 39
Setup Maintenance .................................................. 18
PLL Wizard Dialog Box .......................................... 55
Setup-and-Installation .............................................. 17
Plug & Play.............................................................. 23
Slot................................................... 12, 18, 21, 23, 35
programming ........................................................... 33
Software ................................................................... 18
Programming
Specifications ...................................................... 1, 10
Borland-Delphi .................................................... 33
Specifications
Error-Handling..................................................... 36
SVF .............................................................. 58, 60, 62
Visual ................................................................... 33
Symbol Insert Dialog Box ....................................... 45
Programming Examples .......................................... 36
Symbol Properties.................................................... 52
Programming the GX3700 ....................................... 33
System
PXI..................................... 4, 7, 18, 20, 21, 22, 23, 35
Directory .............................................................. 19
PXI System .............................................................. 20
System Requirements .............................................. 18
PXI/PCI Explorer ...................... 12, 20, 35, 36, 96, 97
T
PXIeSYS.INI ........................................................... 12
Task Flow ................................................................ 42
PXISYS.INI ............................................................. 12
TCL script ................................................................ 39
Q
Testing the Design ................................................... 62
Quartus ....................................................ii, 37, 38, 39
V
R
Verilog entry project ................................................ 42
RAM Wizard Dialog Box ........................................ 56
Virtual Panel ...................... 11, 12, 13, 14, 15, 18, 102
README.TXT ....................................................... 19
Initialize Dialog ............................................. 11, 12
Removing a Board ................................................... 23
VISA .............................. 12, 19, 20, 35, 36, 82, 96, 97
Reset ........................................................................ 36
Visual....................................................................... 33
RPD ................................................................... 58, 60
Visual Basic ........................................................ ii, 33
S
Visual Basic .NET ................................................... 33
Schematic entry project ........................................... 41
Visual C++ ......................................................... ii, 33
Schematic view ........................................................ 44
116 GX3700 User’s Guide
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